diff --git a/Cargo.toml b/Cargo.toml
index c844e012..58b90fbc 100644
--- a/Cargo.toml
+++ b/Cargo.toml
@@ -11,8 +11,10 @@ cortex-m = "0.7.1"
 cortex-m-rt = { version = ">=0.6.15,<0.8", optional = true }
 
 [features]
+default = []
 rt = ["cortex-m-rt/device"]
-
+rp2040 = []
+rp235x = []
 
 [package.metadata.embassy_docs]
 src_base = "https://github.com/embassy-rs/rp-pac/blob/v$VERSION/src/"
diff --git a/build.rs b/build.rs
index 597923f5..b7ea72f5 100644
--- a/build.rs
+++ b/build.rs
@@ -5,10 +5,18 @@ use std::path::PathBuf;
 fn main() {
     if env::var_os("CARGO_FEATURE_RT").is_some() {
         let out = &PathBuf::from(env::var_os("OUT_DIR").unwrap());
-        File::create(out.join("device.x"))
-            .unwrap()
-            .write_all(include_bytes!("device.x"))
-            .unwrap();
+        if env::var_os("CARGO_FEATURE_RP2040").is_some() {
+            File::create(out.join("device.x"))
+                .unwrap()
+                .write_all(include_bytes!("device-rp2040.x"))
+                .unwrap();
+        }
+        if env::var_os("CARGO_FEATURE_RP235X").is_some() {
+            File::create(out.join("device.x"))
+                .unwrap()
+                .write_all(include_bytes!("device-rp235x.x"))
+                .unwrap();
+        }
         println!("cargo:rustc-link-search={}", out.display());
         println!("cargo:rerun-if-changed=device.x");
     }
diff --git a/device.x b/device-rp2040.x
similarity index 100%
rename from device.x
rename to device-rp2040.x
diff --git a/device-rp235x.x b/device-rp235x.x
new file mode 100644
index 00000000..e395c6cc
--- /dev/null
+++ b/device-rp235x.x
@@ -0,0 +1,50 @@
+PROVIDE(TIMER0_IRQ_0 = DefaultHandler);
+PROVIDE(TIMER0_IRQ_1 = DefaultHandler);
+PROVIDE(TIMER0_IRQ_2 = DefaultHandler);
+PROVIDE(TIMER0_IRQ_3 = DefaultHandler);
+PROVIDE(TIMER1_IRQ_0 = DefaultHandler);
+PROVIDE(TIMER1_IRQ_1 = DefaultHandler);
+PROVIDE(TIMER1_IRQ_2 = DefaultHandler);
+PROVIDE(TIMER1_IRQ_3 = DefaultHandler);
+PROVIDE(PWM_IRQ_WRAP_0 = DefaultHandler);
+PROVIDE(PWM_IRQ_WRAP_1 = DefaultHandler);
+PROVIDE(USBCTRL_IRQ = DefaultHandler);
+PROVIDE(PIO0_IRQ_0 = DefaultHandler);
+PROVIDE(PIO0_IRQ_1 = DefaultHandler);
+PROVIDE(PIO1_IRQ_0 = DefaultHandler);
+PROVIDE(PIO1_IRQ_1 = DefaultHandler);
+PROVIDE(PIO2_IRQ_0 = DefaultHandler);
+PROVIDE(PIO2_IRQ_1 = DefaultHandler);
+PROVIDE(DMA_IRQ_0 = DefaultHandler);
+PROVIDE(DMA_IRQ_1 = DefaultHandler);
+PROVIDE(DMA_IRQ_2 = DefaultHandler);
+PROVIDE(DMA_IRQ_3 = DefaultHandler);
+PROVIDE(IO_IRQ_BANK0 = DefaultHandler);
+PROVIDE(IO_IRQ_BANK0_NS = DefaultHandler);
+PROVIDE(IO_IRQ_QSPI = DefaultHandler);
+PROVIDE(IO_IRQ_QSPI_NS = DefaultHandler);
+PROVIDE(SIO_IRQ_FIFO = DefaultHandler);
+PROVIDE(SIO_IRQ_FIFO_NS = DefaultHandler);
+PROVIDE(SIO_IRQ_BELL = DefaultHandler);
+PROVIDE(SIO_IRQ_BELL_NS = DefaultHandler);
+PROVIDE(SIO_IRQ_MTIMECMP = DefaultHandler);
+PROVIDE(CLOCKS_IRQ = DefaultHandler);
+PROVIDE(PLL_SYS_IRQ = DefaultHandler);
+PROVIDE(PLL_USB_IRQ = DefaultHandler);
+PROVIDE(SPI0_IRQ = DefaultHandler);
+PROVIDE(SPI1_IRQ = DefaultHandler);
+PROVIDE(UART0_IRQ = DefaultHandler);
+PROVIDE(UART1_IRQ = DefaultHandler);
+PROVIDE(ADC_IRQ_FIFO = DefaultHandler);
+PROVIDE(I2C0_IRQ = DefaultHandler);
+PROVIDE(I2C1_IRQ = DefaultHandler);
+PROVIDE(TRNG_IRQ = DefaultHandler);
+PROVIDE(OTP_IRQ = DefaultHandler);
+PROVIDE(POWMAN_IRQ_POW = DefaultHandler);
+PROVIDE(POWMAN_IRQ_TIMER = DefaultHandler);
+PROVIDE(SWI_IRQ_0 = DefaultHandler);
+PROVIDE(SWI_IRQ_1 = DefaultHandler);
+PROVIDE(SWI_IRQ_2 = DefaultHandler);
+PROVIDE(SWI_IRQ_3 = DefaultHandler);
+PROVIDE(SWI_IRQ_4 = DefaultHandler);
+PROVIDE(SWI_IRQ_5 = DefaultHandler);
diff --git a/src/dma/vals.rs b/src/dma/vals.rs
deleted file mode 100644
index 7e3ca402..00000000
--- a/src/dma/vals.rs
+++ /dev/null
@@ -1,113 +0,0 @@
-#[repr(u8)]
-#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-pub enum Calc {
-    #[doc = "Calculate a CRC-32 (IEEE802.3 polynomial)"]
-    CRC32 = 0,
-    #[doc = "Calculate a CRC-32 (IEEE802.3 polynomial) with bit reversed data"]
-    CRC32R = 0x01,
-    #[doc = "Calculate a CRC-16-CCITT"]
-    CRC16 = 0x02,
-    #[doc = "Calculate a CRC-16-CCITT with bit reversed data"]
-    CRC16R = 0x03,
-    _RESERVED_4 = 0x04,
-    _RESERVED_5 = 0x05,
-    _RESERVED_6 = 0x06,
-    _RESERVED_7 = 0x07,
-    _RESERVED_8 = 0x08,
-    _RESERVED_9 = 0x09,
-    _RESERVED_a = 0x0a,
-    _RESERVED_b = 0x0b,
-    _RESERVED_c = 0x0c,
-    _RESERVED_d = 0x0d,
-    #[doc = "XOR reduction over all data. == 1 if the total 1 population count is odd."]
-    EVEN = 0x0e,
-    #[doc = "Calculate a simple 32-bit checksum (addition with a 32 bit accumulator)"]
-    SUM = 0x0f,
-}
-impl Calc {
-    #[inline(always)]
-    pub const fn from_bits(val: u8) -> Calc {
-        unsafe { core::mem::transmute(val & 0x0f) }
-    }
-    #[inline(always)]
-    pub const fn to_bits(self) -> u8 {
-        unsafe { core::mem::transmute(self) }
-    }
-}
-impl From<u8> for Calc {
-    #[inline(always)]
-    fn from(val: u8) -> Calc {
-        Calc::from_bits(val)
-    }
-}
-impl From<Calc> for u8 {
-    #[inline(always)]
-    fn from(val: Calc) -> u8 {
-        Calc::to_bits(val)
-    }
-}
-#[repr(u8)]
-#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-pub enum DataSize {
-    SIZE_BYTE = 0,
-    SIZE_HALFWORD = 0x01,
-    SIZE_WORD = 0x02,
-    _RESERVED_3 = 0x03,
-}
-impl DataSize {
-    #[inline(always)]
-    pub const fn from_bits(val: u8) -> DataSize {
-        unsafe { core::mem::transmute(val & 0x03) }
-    }
-    #[inline(always)]
-    pub const fn to_bits(self) -> u8 {
-        unsafe { core::mem::transmute(self) }
-    }
-}
-impl From<u8> for DataSize {
-    #[inline(always)]
-    fn from(val: u8) -> DataSize {
-        DataSize::from_bits(val)
-    }
-}
-impl From<DataSize> for u8 {
-    #[inline(always)]
-    fn from(val: DataSize) -> u8 {
-        DataSize::to_bits(val)
-    }
-}
-#[repr(transparent)]
-#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-pub struct TreqSel(pub u8);
-impl TreqSel {
-    #[doc = "Select Timer 0 as TREQ"]
-    pub const TIMER0: Self = Self(0x3b);
-    #[doc = "Select Timer 1 as TREQ"]
-    pub const TIMER1: Self = Self(0x3c);
-    #[doc = "Select Timer 2 as TREQ (Optional)"]
-    pub const TIMER2: Self = Self(0x3d);
-    #[doc = "Select Timer 3 as TREQ (Optional)"]
-    pub const TIMER3: Self = Self(0x3e);
-    #[doc = "Permanent request, for unpaced transfers."]
-    pub const PERMANENT: Self = Self(0x3f);
-}
-impl TreqSel {
-    pub const fn from_bits(val: u8) -> TreqSel {
-        Self(val & 0x3f)
-    }
-    pub const fn to_bits(self) -> u8 {
-        self.0
-    }
-}
-impl From<u8> for TreqSel {
-    #[inline(always)]
-    fn from(val: u8) -> TreqSel {
-        TreqSel::from_bits(val)
-    }
-}
-impl From<TreqSel> for u8 {
-    #[inline(always)]
-    fn from(val: TreqSel) -> u8 {
-        TreqSel::to_bits(val)
-    }
-}
diff --git a/src/lib.rs b/src/lib.rs
index a64e0a86..fde39ab5 100644
--- a/src/lib.rs
+++ b/src/lib.rs
@@ -1,173 +1,12 @@
 #![no_std]
-#![doc = include_str!("../README.md")]
 #![allow(non_camel_case_types)]
-#[derive(Copy, Clone, Debug, PartialEq, Eq)]
-pub enum Interrupt {
-    #[doc = "0 - TIMER_IRQ_0"]
-    TIMER_IRQ_0 = 0,
-    #[doc = "1 - TIMER_IRQ_1"]
-    TIMER_IRQ_1 = 1,
-    #[doc = "2 - TIMER_IRQ_2"]
-    TIMER_IRQ_2 = 2,
-    #[doc = "3 - TIMER_IRQ_3"]
-    TIMER_IRQ_3 = 3,
-    #[doc = "4 - PWM_IRQ_WRAP"]
-    PWM_IRQ_WRAP = 4,
-    #[doc = "5 - USBCTRL_IRQ"]
-    USBCTRL_IRQ = 5,
-    #[doc = "6 - XIP_IRQ"]
-    XIP_IRQ = 6,
-    #[doc = "7 - PIO0_IRQ_0"]
-    PIO0_IRQ_0 = 7,
-    #[doc = "8 - PIO0_IRQ_1"]
-    PIO0_IRQ_1 = 8,
-    #[doc = "9 - PIO1_IRQ_0"]
-    PIO1_IRQ_0 = 9,
-    #[doc = "10 - PIO1_IRQ_1"]
-    PIO1_IRQ_1 = 10,
-    #[doc = "11 - DMA_IRQ_0"]
-    DMA_IRQ_0 = 11,
-    #[doc = "12 - DMA_IRQ_1"]
-    DMA_IRQ_1 = 12,
-    #[doc = "13 - IO_IRQ_BANK0"]
-    IO_IRQ_BANK0 = 13,
-    #[doc = "14 - IO_IRQ_QSPI"]
-    IO_IRQ_QSPI = 14,
-    #[doc = "15 - SIO_IRQ_PROC0"]
-    SIO_IRQ_PROC0 = 15,
-    #[doc = "16 - SIO_IRQ_PROC1"]
-    SIO_IRQ_PROC1 = 16,
-    #[doc = "17 - CLOCKS_IRQ"]
-    CLOCKS_IRQ = 17,
-    #[doc = "18 - SPI0_IRQ"]
-    SPI0_IRQ = 18,
-    #[doc = "19 - SPI1_IRQ"]
-    SPI1_IRQ = 19,
-    #[doc = "20 - UART0_IRQ"]
-    UART0_IRQ = 20,
-    #[doc = "21 - UART1_IRQ"]
-    UART1_IRQ = 21,
-    #[doc = "22 - ADC_IRQ_FIFO"]
-    ADC_IRQ_FIFO = 22,
-    #[doc = "23 - I2C0_IRQ"]
-    I2C0_IRQ = 23,
-    #[doc = "24 - I2C1_IRQ"]
-    I2C1_IRQ = 24,
-    #[doc = "25 - RTC_IRQ"]
-    RTC_IRQ = 25,
-    #[doc = "26 - SWI_IRQ_0"]
-    SWI_IRQ_0 = 26,
-    #[doc = "27 - SWI_IRQ_1"]
-    SWI_IRQ_1 = 27,
-    #[doc = "28 - SWI_IRQ_2"]
-    SWI_IRQ_2 = 28,
-    #[doc = "29 - SWI_IRQ_3"]
-    SWI_IRQ_3 = 29,
-    #[doc = "30 - SWI_IRQ_4"]
-    SWI_IRQ_4 = 30,
-    #[doc = "31 - SWI_IRQ_5"]
-    SWI_IRQ_5 = 31,
-}
-unsafe impl cortex_m::interrupt::InterruptNumber for Interrupt {
-    #[inline(always)]
-    fn number(self) -> u16 {
-        self as u16
-    }
-}
-#[cfg(feature = "rt")]
-mod _vectors;
-#[doc = "QSPI flash execute-in-place block"]
-pub const XIP_CTRL: xip_ctrl::XipCtrl =
-    unsafe { xip_ctrl::XipCtrl::from_ptr(0x1400_0000 as usize as _) };
-#[doc = "DW_apb_ssi has the following features: * APB interface – Allows for easy integration into a DesignWare Synthesizable Components for AMBA 2 implementation. * APB3 and APB4 protocol support. * Scalable APB data bus width – Supports APB data bus widths of 8, 16, and 32 bits. * Serial-master or serial-slave operation – Enables serial communication with serial-master or serial-slave peripheral devices. * Programmable Dual/Quad/Octal SPI support in Master Mode. * Dual Data Rate (DDR) and Read Data Strobe (RDS) Support - Enables the DW_apb_ssi master to perform operations with the device in DDR and RDS modes when working in Dual/Quad/Octal mode of operation. * Data Mask Support - Enables the DW_apb_ssi to selectively update the bytes in the device. This feature is applicable only in enhanced SPI modes. * eXecute-In-Place (XIP) support - Enables the DW_apb_ssi master to behave as a memory mapped I/O and fetches the data from the device based on the APB read request. This feature is applicable only in enhanced SPI modes. * DMA Controller Interface – Enables the DW_apb_ssi to interface to a DMA controller over the bus using a handshaking interface for transfer requests. * Independent masking of interrupts – Master collision, transmit FIFO overflow, transmit FIFO empty, receive FIFO full, receive FIFO underflow, and receive FIFO overflow interrupts can all be masked independently. * Multi-master contention detection – Informs the processor of multiple serial-master accesses on the serial bus. * Bypass of meta-stability flip-flops for synchronous clocks – When the APB clock (pclk) and the DW_apb_ssi serial clock (ssi_clk) are synchronous, meta-stable flip-flops are not used when transferring control signals across these clock domains. * Programmable delay on the sample time of the received serial data bit (rxd); enables programmable control of routing delays resulting in higher serial data-bit rates. * Programmable features: - Serial interface operation – Choice of Motorola SPI, Texas Instruments Synchronous Serial Protocol or National Semiconductor Microwire. - Clock bit-rate – Dynamic control of the serial bit rate of the data transfer; used in only serial-master mode of operation. - Data Item size (4 to 32 bits) – Item size of each data transfer under the control of the programmer. * Configured features: - FIFO depth – 16 words deep. The FIFO width is fixed at 32 bits. - 1 slave select output. - Hardware slave-select – Dedicated hardware slave-select line. - Combined interrupt line - one combined interrupt line from the DW_apb_ssi to the interrupt controller. - Interrupt polarity – active high interrupt lines. - Serial clock polarity – low serial-clock polarity directly after reset. - Serial clock phase – capture on first edge of serial-clock directly after reset."]
-pub const XIP_SSI: xip_ssi::XipSsi =
-    unsafe { xip_ssi::XipSsi::from_ptr(0x1800_0000 as usize as _) };
-pub const SYSINFO: sysinfo::Sysinfo =
-    unsafe { sysinfo::Sysinfo::from_ptr(0x4000_0000 as usize as _) };
-#[doc = "Register block for various chip control signals"]
-pub const SYSCFG: syscfg::Syscfg = unsafe { syscfg::Syscfg::from_ptr(0x4000_4000 as usize as _) };
-pub const CLOCKS: clocks::Clocks = unsafe { clocks::Clocks::from_ptr(0x4000_8000 as usize as _) };
-pub const RESETS: resets::Resets = unsafe { resets::Resets::from_ptr(0x4000_c000 as usize as _) };
-pub const PSM: psm::Psm = unsafe { psm::Psm::from_ptr(0x4001_0000 as usize as _) };
-pub const IO_BANK0: io::Io = unsafe { io::Io::from_ptr(0x4001_4000 as usize as _) };
-pub const IO_QSPI: io::Io = unsafe { io::Io::from_ptr(0x4001_8000 as usize as _) };
-pub const PADS_BANK0: pads::Pads = unsafe { pads::Pads::from_ptr(0x4001_c000 as usize as _) };
-pub const PADS_QSPI: pads::Pads = unsafe { pads::Pads::from_ptr(0x4002_0000 as usize as _) };
-#[doc = "Controls the crystal oscillator"]
-pub const XOSC: xosc::Xosc = unsafe { xosc::Xosc::from_ptr(0x4002_4000 as usize as _) };
-pub const PLL_SYS: pll::Pll = unsafe { pll::Pll::from_ptr(0x4002_8000 as usize as _) };
-pub const PLL_USB: pll::Pll = unsafe { pll::Pll::from_ptr(0x4002_c000 as usize as _) };
-#[doc = "Register block for busfabric control signals and performance counters"]
-pub const BUSCTRL: busctrl::Busctrl =
-    unsafe { busctrl::Busctrl::from_ptr(0x4003_0000 as usize as _) };
-pub const UART0: uart::Uart = unsafe { uart::Uart::from_ptr(0x4003_4000 as usize as _) };
-pub const UART1: uart::Uart = unsafe { uart::Uart::from_ptr(0x4003_8000 as usize as _) };
-pub const SPI0: spi::Spi = unsafe { spi::Spi::from_ptr(0x4003_c000 as usize as _) };
-pub const SPI1: spi::Spi = unsafe { spi::Spi::from_ptr(0x4004_0000 as usize as _) };
-#[doc = "DW_apb_i2c address block List of configuration constants for the Synopsys I2C hardware (you may see references to these in I2C register header; these are *fixed* values, set at hardware design time): IC_ULTRA_FAST_MODE ................ 0x0 IC_UFM_TBUF_CNT_DEFAULT ........... 0x8 IC_UFM_SCL_LOW_COUNT .............. 0x0008 IC_UFM_SCL_HIGH_COUNT ............. 0x0006 IC_TX_TL .......................... 0x0 IC_TX_CMD_BLOCK ................... 0x1 IC_HAS_DMA ........................ 0x1 IC_HAS_ASYNC_FIFO ................. 0x0 IC_SMBUS_ARP ...................... 0x0 IC_FIRST_DATA_BYTE_STATUS ......... 0x1 IC_INTR_IO ........................ 0x1 IC_MASTER_MODE .................... 0x1 IC_DEFAULT_ACK_GENERAL_CALL ....... 0x1 IC_INTR_POL ....................... 0x1 IC_OPTIONAL_SAR ................... 0x0 IC_DEFAULT_TAR_SLAVE_ADDR ......... 0x055 IC_DEFAULT_SLAVE_ADDR ............. 0x055 IC_DEFAULT_HS_SPKLEN .............. 0x1 IC_FS_SCL_HIGH_COUNT .............. 0x0006 IC_HS_SCL_LOW_COUNT ............... 0x0008 IC_DEVICE_ID_VALUE ................ 0x0 IC_10BITADDR_MASTER ............... 0x0 IC_CLK_FREQ_OPTIMIZATION .......... 0x0 IC_DEFAULT_FS_SPKLEN .............. 0x7 IC_ADD_ENCODED_PARAMS ............. 0x0 IC_DEFAULT_SDA_HOLD ............... 0x000001 IC_DEFAULT_SDA_SETUP .............. 0x64 IC_AVOID_RX_FIFO_FLUSH_ON_TX_ABRT . 0x0 IC_CLOCK_PERIOD ................... 100 IC_EMPTYFIFO_HOLD_MASTER_EN ....... 1 IC_RESTART_EN ..................... 0x1 IC_TX_CMD_BLOCK_DEFAULT ........... 0x0 IC_BUS_CLEAR_FEATURE .............. 0x0 IC_CAP_LOADING .................... 100 IC_FS_SCL_LOW_COUNT ............... 0x000d APB_DATA_WIDTH .................... 32 IC_SDA_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff IC_SLV_DATA_NACK_ONLY ............. 0x1 IC_10BITADDR_SLAVE ................ 0x0 IC_CLK_TYPE ....................... 0x0 IC_SMBUS_UDID_MSB ................. 0x0 IC_SMBUS_SUSPEND_ALERT ............ 0x0 IC_HS_SCL_HIGH_COUNT .............. 0x0006 IC_SLV_RESTART_DET_EN ............. 0x1 IC_SMBUS .......................... 0x0 IC_OPTIONAL_SAR_DEFAULT ........... 0x0 IC_PERSISTANT_SLV_ADDR_DEFAULT .... 0x0 IC_USE_COUNTS ..................... 0x0 IC_RX_BUFFER_DEPTH ................ 16 IC_SCL_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff IC_RX_FULL_HLD_BUS_EN ............. 0x1 IC_SLAVE_DISABLE .................. 0x1 IC_RX_TL .......................... 0x0 IC_DEVICE_ID ...................... 0x0 IC_HC_COUNT_VALUES ................ 0x0 I2C_DYNAMIC_TAR_UPDATE ............ 0 IC_SMBUS_CLK_LOW_MEXT_DEFAULT ..... 0xffffffff IC_SMBUS_CLK_LOW_SEXT_DEFAULT ..... 0xffffffff IC_HS_MASTER_CODE ................. 0x1 IC_SMBUS_RST_IDLE_CNT_DEFAULT ..... 0xffff IC_SMBUS_UDID_LSB_DEFAULT ......... 0xffffffff IC_SS_SCL_HIGH_COUNT .............. 0x0028 IC_SS_SCL_LOW_COUNT ............... 0x002f IC_MAX_SPEED_MODE ................. 0x2 IC_STAT_FOR_CLK_STRETCH ........... 0x0 IC_STOP_DET_IF_MASTER_ACTIVE ...... 0x0 IC_DEFAULT_UFM_SPKLEN ............. 0x1 IC_TX_BUFFER_DEPTH ................ 16"]
-pub const I2C0: i2c::I2c = unsafe { i2c::I2c::from_ptr(0x4004_4000 as usize as _) };
-pub const I2C1: i2c::I2c = unsafe { i2c::I2c::from_ptr(0x4004_8000 as usize as _) };
-#[doc = "Control and data interface to SAR ADC"]
-pub const ADC: adc::Adc = unsafe { adc::Adc::from_ptr(0x4004_c000 as usize as _) };
-#[doc = "Simple PWM"]
-pub const PWM: pwm::Pwm = unsafe { pwm::Pwm::from_ptr(0x4005_0000 as usize as _) };
-#[doc = "Controls time and alarms time is a 64 bit value indicating the time in usec since power-on timeh is the top 32 bits of time & timel is the bottom 32 bits to change time write to timelw before timehw to read time read from timelr before timehr An alarm is set by setting alarm_enable and writing to the corresponding alarm register When an alarm is pending, the corresponding alarm_running signal will be high An alarm can be cancelled before it has finished by clearing the alarm_enable When an alarm fires, the corresponding alarm_irq is set and alarm_running is cleared To clear the interrupt write a 1 to the corresponding alarm_irq"]
-pub const TIMER: timer::Timer = unsafe { timer::Timer::from_ptr(0x4005_4000 as usize as _) };
-pub const WATCHDOG: watchdog::Watchdog =
-    unsafe { watchdog::Watchdog::from_ptr(0x4005_8000 as usize as _) };
-#[doc = "Register block to control RTC"]
-pub const RTC: rtc::Rtc = unsafe { rtc::Rtc::from_ptr(0x4005_c000 as usize as _) };
-pub const ROSC: rosc::Rosc = unsafe { rosc::Rosc::from_ptr(0x4006_0000 as usize as _) };
-#[doc = "control and status for on-chip voltage regulator and chip level reset subsystem"]
-pub const VREG_AND_CHIP_RESET: vreg_and_chip_reset::VregAndChipReset =
-    unsafe { vreg_and_chip_reset::VregAndChipReset::from_ptr(0x4006_4000 as usize as _) };
-#[doc = "Testbench manager. Allows the programmer to know what platform their software is running on."]
-pub const TBMAN: tbman::Tbman = unsafe { tbman::Tbman::from_ptr(0x4006_c000 as usize as _) };
-#[doc = "DMA with separate read and write masters"]
-pub const DMA: dma::Dma = unsafe { dma::Dma::from_ptr(0x5000_0000 as usize as _) };
-#[doc = "DPRAM layout for USB device."]
-pub const USBCTRL_DPRAM: usb_dpram::UsbDpram =
-    unsafe { usb_dpram::UsbDpram::from_ptr(0x5010_0000 as usize as _) };
-#[doc = "USB FS/LS controller device registers"]
-pub const USBCTRL_REGS: usb::Usb = unsafe { usb::Usb::from_ptr(0x5011_0000 as usize as _) };
-#[doc = "Programmable IO block"]
-pub const PIO0: pio::Pio = unsafe { pio::Pio::from_ptr(0x5020_0000 as usize as _) };
-pub const PIO1: pio::Pio = unsafe { pio::Pio::from_ptr(0x5030_0000 as usize as _) };
-#[doc = "Single-cycle IO block Provides core-local and inter-core hardware for the two processors, with single-cycle access."]
-pub const SIO: sio::Sio = unsafe { sio::Sio::from_ptr(0xd000_0000 as usize as _) };
-#[doc = r" Number available in the NVIC for configuring priority"]
-#[cfg(feature = "rt")]
-pub const NVIC_PRIO_BITS: u8 = 2;
-#[cfg(feature = "rt")]
-pub use cortex_m_rt::interrupt;
-#[cfg(feature = "rt")]
-pub use Interrupt as interrupt;
-pub mod adc;
-pub mod busctrl;
-pub mod clocks;
-pub mod common;
-pub mod dma;
-pub mod i2c;
-pub mod io;
-pub mod pads;
-pub mod pio;
-pub mod pll;
-pub mod psm;
-pub mod pwm;
-pub mod resets;
-pub mod rosc;
-pub mod rtc;
-pub mod sio;
-pub mod spi;
-pub mod syscfg;
-pub mod sysinfo;
-pub mod tbman;
-pub mod timer;
-pub mod uart;
-pub mod usb;
-pub mod usb_dpram;
-pub mod vreg_and_chip_reset;
-pub mod watchdog;
-pub mod xip_ctrl;
-pub mod xip_ssi;
-pub mod xosc;
+
+#[cfg(feature = "rp2040")]
+pub mod rp2040;
+#[cfg(feature = "rp2040")]
+pub use rp2040::*;
+
+#[cfg(feature = "rp235x")]
+pub mod rp2350;
+#[cfg(feature = "rp235x")]
+pub use rp2350::*;
diff --git a/src/_vectors.rs b/src/rp2040/_vectors.rs
similarity index 100%
rename from src/_vectors.rs
rename to src/rp2040/_vectors.rs
diff --git a/src/adc.rs b/src/rp2040/adc.rs
similarity index 100%
rename from src/adc.rs
rename to src/rp2040/adc.rs
diff --git a/src/adc/regs.rs b/src/rp2040/adc/regs.rs
similarity index 100%
rename from src/adc/regs.rs
rename to src/rp2040/adc/regs.rs
diff --git a/src/busctrl.rs b/src/rp2040/busctrl.rs
similarity index 100%
rename from src/busctrl.rs
rename to src/rp2040/busctrl.rs
diff --git a/src/busctrl/regs.rs b/src/rp2040/busctrl/regs.rs
similarity index 94%
rename from src/busctrl/regs.rs
rename to src/rp2040/busctrl/regs.rs
index 08006b14..2c37899b 100644
--- a/src/busctrl/regs.rs
+++ b/src/rp2040/busctrl/regs.rs
@@ -77,18 +77,18 @@ impl Default for BusPriorityAck {
         BusPriorityAck(0)
     }
 }
-#[doc = "Bus fabric performance counter 0"]
+#[doc = "Bus fabric performance counter 1"]
 #[repr(transparent)]
 #[derive(Copy, Clone, Eq, PartialEq)]
 pub struct Perfctr(pub u32);
 impl Perfctr {
-    #[doc = "Busfabric saturating performance counter 0 Count some event signal from the busfabric arbiters. Write any value to clear. Select an event to count using PERFSEL0"]
+    #[doc = "Busfabric saturating performance counter 1 Count some event signal from the busfabric arbiters. Write any value to clear. Select an event to count using PERFSEL1"]
     #[inline(always)]
     pub const fn perfctr(&self) -> u32 {
         let val = (self.0 >> 0usize) & 0x00ff_ffff;
         val as u32
     }
-    #[doc = "Busfabric saturating performance counter 0 Count some event signal from the busfabric arbiters. Write any value to clear. Select an event to count using PERFSEL0"]
+    #[doc = "Busfabric saturating performance counter 1 Count some event signal from the busfabric arbiters. Write any value to clear. Select an event to count using PERFSEL1"]
     #[inline(always)]
     pub fn set_perfctr(&mut self, val: u32) {
         self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize);
diff --git a/src/busctrl/vals.rs b/src/rp2040/busctrl/vals.rs
similarity index 100%
rename from src/busctrl/vals.rs
rename to src/rp2040/busctrl/vals.rs
diff --git a/src/clocks.rs b/src/rp2040/clocks.rs
similarity index 85%
rename from src/clocks.rs
rename to src/rp2040/clocks.rs
index 32eeb511..3dc733e3 100644
--- a/src/clocks.rs
+++ b/src/rp2040/clocks.rs
@@ -31,9 +31,9 @@ impl Clocks {
         assert!(n < 4usize);
         unsafe { crate::common::Reg::from_ptr(self.ptr.add(4usize + n * 12usize) as _) }
     }
-    #[doc = "Indicates which SRC is currently selected by the glitchless mux (one-hot). This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1."]
+    #[doc = "Indicates which SRC is currently selected by the glitchless mux (one-hot)."]
     #[inline(always)]
-    pub const fn clk_gpout_selected(self, n: usize) -> crate::common::Reg<u32, crate::common::R> {
+    pub const fn clk_gpout_selected(self, n: usize) -> crate::common::Reg<u32, crate::common::RW> {
         assert!(n < 4usize);
         unsafe { crate::common::Reg::from_ptr(self.ptr.add(8usize + n * 12usize) as _) }
     }
@@ -47,9 +47,9 @@ impl Clocks {
     pub const fn clk_ref_div(self) -> crate::common::Reg<regs::ClkRefDiv, crate::common::RW> {
         unsafe { crate::common::Reg::from_ptr(self.ptr.add(52usize) as _) }
     }
-    #[doc = "Indicates which SRC is currently selected by the glitchless mux (one-hot). The glitchless multiplexer does not switch instantaneously (to avoid glitches), so software should poll this register to wait for the switch to complete. This register contains one decoded bit for each of the clock sources enumerated in the CTRL SRC field. At most one of these bits will be set at any time, indicating that clock is currently present at the output of the glitchless mux. Whilst switching is in progress, this register may briefly show all-0s."]
+    #[doc = "Indicates which SRC is currently selected by the glitchless mux (one-hot)."]
     #[inline(always)]
-    pub const fn clk_ref_selected(self) -> crate::common::Reg<u32, crate::common::R> {
+    pub const fn clk_ref_selected(self) -> crate::common::Reg<u32, crate::common::RW> {
         unsafe { crate::common::Reg::from_ptr(self.ptr.add(56usize) as _) }
     }
     #[doc = "Clock control, can be changed on-the-fly (except for auxsrc)"]
@@ -62,9 +62,9 @@ impl Clocks {
     pub const fn clk_sys_div(self) -> crate::common::Reg<regs::ClkSysDiv, crate::common::RW> {
         unsafe { crate::common::Reg::from_ptr(self.ptr.add(64usize) as _) }
     }
-    #[doc = "Indicates which SRC is currently selected by the glitchless mux (one-hot). The glitchless multiplexer does not switch instantaneously (to avoid glitches), so software should poll this register to wait for the switch to complete. This register contains one decoded bit for each of the clock sources enumerated in the CTRL SRC field. At most one of these bits will be set at any time, indicating that clock is currently present at the output of the glitchless mux. Whilst switching is in progress, this register may briefly show all-0s."]
+    #[doc = "Indicates which SRC is currently selected by the glitchless mux (one-hot)."]
     #[inline(always)]
-    pub const fn clk_sys_selected(self) -> crate::common::Reg<u32, crate::common::R> {
+    pub const fn clk_sys_selected(self) -> crate::common::Reg<u32, crate::common::RW> {
         unsafe { crate::common::Reg::from_ptr(self.ptr.add(68usize) as _) }
     }
     #[doc = "Clock control, can be changed on-the-fly (except for auxsrc)"]
@@ -72,9 +72,14 @@ impl Clocks {
     pub const fn clk_peri_ctrl(self) -> crate::common::Reg<regs::ClkPeriCtrl, crate::common::RW> {
         unsafe { crate::common::Reg::from_ptr(self.ptr.add(72usize) as _) }
     }
-    #[doc = "Indicates which SRC is currently selected by the glitchless mux (one-hot). This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1."]
+    #[doc = "Clock divisor, can be changed on-the-fly"]
+    #[inline(always)]
+    pub const fn clk_peri_div(self) -> crate::common::Reg<regs::ClkPeriDiv, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(76usize) as _) }
+    }
+    #[doc = "Indicates which SRC is currently selected by the glitchless mux (one-hot)."]
     #[inline(always)]
-    pub const fn clk_peri_selected(self) -> crate::common::Reg<u32, crate::common::R> {
+    pub const fn clk_peri_selected(self) -> crate::common::Reg<u32, crate::common::RW> {
         unsafe { crate::common::Reg::from_ptr(self.ptr.add(80usize) as _) }
     }
     #[doc = "Clock control, can be changed on-the-fly (except for auxsrc)"]
@@ -87,9 +92,9 @@ impl Clocks {
     pub const fn clk_usb_div(self) -> crate::common::Reg<regs::ClkUsbDiv, crate::common::RW> {
         unsafe { crate::common::Reg::from_ptr(self.ptr.add(88usize) as _) }
     }
-    #[doc = "Indicates which SRC is currently selected by the glitchless mux (one-hot). This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1."]
+    #[doc = "Indicates which SRC is currently selected by the glitchless mux (one-hot)."]
     #[inline(always)]
-    pub const fn clk_usb_selected(self) -> crate::common::Reg<u32, crate::common::R> {
+    pub const fn clk_usb_selected(self) -> crate::common::Reg<u32, crate::common::RW> {
         unsafe { crate::common::Reg::from_ptr(self.ptr.add(92usize) as _) }
     }
     #[doc = "Clock control, can be changed on-the-fly (except for auxsrc)"]
@@ -102,9 +107,9 @@ impl Clocks {
     pub const fn clk_adc_div(self) -> crate::common::Reg<regs::ClkAdcDiv, crate::common::RW> {
         unsafe { crate::common::Reg::from_ptr(self.ptr.add(100usize) as _) }
     }
-    #[doc = "Indicates which SRC is currently selected by the glitchless mux (one-hot). This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1."]
+    #[doc = "Indicates which SRC is currently selected by the glitchless mux (one-hot)."]
     #[inline(always)]
-    pub const fn clk_adc_selected(self) -> crate::common::Reg<u32, crate::common::R> {
+    pub const fn clk_adc_selected(self) -> crate::common::Reg<u32, crate::common::RW> {
         unsafe { crate::common::Reg::from_ptr(self.ptr.add(104usize) as _) }
     }
     #[doc = "Clock control, can be changed on-the-fly (except for auxsrc)"]
@@ -117,9 +122,9 @@ impl Clocks {
     pub const fn clk_rtc_div(self) -> crate::common::Reg<regs::ClkRtcDiv, crate::common::RW> {
         unsafe { crate::common::Reg::from_ptr(self.ptr.add(112usize) as _) }
     }
-    #[doc = "Indicates which SRC is currently selected by the glitchless mux (one-hot). This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1."]
+    #[doc = "Indicates which SRC is currently selected by the glitchless mux (one-hot)."]
     #[inline(always)]
-    pub const fn clk_rtc_selected(self) -> crate::common::Reg<u32, crate::common::R> {
+    pub const fn clk_rtc_selected(self) -> crate::common::Reg<u32, crate::common::RW> {
         unsafe { crate::common::Reg::from_ptr(self.ptr.add(116usize) as _) }
     }
     #[inline(always)]
diff --git a/src/clocks/regs.rs b/src/rp2040/clocks/regs.rs
similarity index 98%
rename from src/clocks/regs.rs
rename to src/rp2040/clocks/regs.rs
index b2cc8130..6790c6dd 100644
--- a/src/clocks/regs.rs
+++ b/src/rp2040/clocks/regs.rs
@@ -245,6 +245,40 @@ impl Default for ClkPeriCtrl {
         ClkPeriCtrl(0)
     }
 }
+#[doc = "Clock divisor, can be changed on-the-fly"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct ClkPeriDiv(pub u32);
+impl ClkPeriDiv {
+    #[doc = "Fractional component of the divisor"]
+    #[inline(always)]
+    pub const fn frac(&self) -> u8 {
+        let val = (self.0 >> 0usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Fractional component of the divisor"]
+    #[inline(always)]
+    pub fn set_frac(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize);
+    }
+    #[doc = "Integer component of the divisor, 0 -> divide by 2^16"]
+    #[inline(always)]
+    pub const fn int(&self) -> u32 {
+        let val = (self.0 >> 8usize) & 0x00ff_ffff;
+        val as u32
+    }
+    #[doc = "Integer component of the divisor, 0 -> divide by 2^16"]
+    #[inline(always)]
+    pub fn set_int(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x00ff_ffff << 8usize)) | (((val as u32) & 0x00ff_ffff) << 8usize);
+    }
+}
+impl Default for ClkPeriDiv {
+    #[inline(always)]
+    fn default() -> ClkPeriDiv {
+        ClkPeriDiv(0)
+    }
+}
 #[doc = "Clock control, can be changed on-the-fly (except for auxsrc)"]
 #[repr(transparent)]
 #[derive(Copy, Clone, Eq, PartialEq)]
@@ -1341,7 +1375,7 @@ impl Default for Fc0status {
         Fc0status(0)
     }
 }
-#[doc = "Interrupt Force"]
+#[doc = "Interrupt status after masking & forcing"]
 #[repr(transparent)]
 #[derive(Copy, Clone, Eq, PartialEq)]
 pub struct Int(pub u32);
diff --git a/src/clocks/vals.rs b/src/rp2040/clocks/vals.rs
similarity index 100%
rename from src/clocks/vals.rs
rename to src/rp2040/clocks/vals.rs
diff --git a/src/common.rs b/src/rp2040/common.rs
similarity index 100%
rename from src/common.rs
rename to src/rp2040/common.rs
diff --git a/src/common/sealed.rs b/src/rp2040/common/sealed.rs
similarity index 100%
rename from src/common/sealed.rs
rename to src/rp2040/common/sealed.rs
diff --git a/src/dma.rs b/src/rp2040/dma.rs
similarity index 85%
rename from src/dma.rs
rename to src/rp2040/dma.rs
index b60413c3..1e9a4a66 100644
--- a/src/dma.rs
+++ b/src/rp2040/dma.rs
@@ -13,17 +13,17 @@ impl Channel {
     pub const fn as_ptr(&self) -> *mut () {
         self.ptr as _
     }
-    #[doc = "DMA Channel 11 Read Address pointer This register updates automatically each time a read completes. The current value is the next address to be read by this channel."]
+    #[doc = "DMA Channel 11 Read Address pointer"]
     #[inline(always)]
     pub const fn read_addr(self) -> crate::common::Reg<u32, crate::common::RW> {
         unsafe { crate::common::Reg::from_ptr(self.ptr.add(0usize) as _) }
     }
-    #[doc = "DMA Channel 11 Write Address pointer This register updates automatically each time a write completes. The current value is the next address to be written by this channel."]
+    #[doc = "DMA Channel 11 Write Address pointer"]
     #[inline(always)]
     pub const fn write_addr(self) -> crate::common::Reg<u32, crate::common::RW> {
         unsafe { crate::common::Reg::from_ptr(self.ptr.add(4usize) as _) }
     }
-    #[doc = "DMA Channel 11 Transfer Count Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD."]
+    #[doc = "DMA Channel 11 Transfer Count"]
     #[inline(always)]
     pub const fn trans_count(self) -> crate::common::Reg<u32, crate::common::RW> {
         unsafe { crate::common::Reg::from_ptr(self.ptr.add(8usize) as _) }
@@ -100,7 +100,7 @@ impl Channel {
     }
     #[doc = "Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer"]
     #[inline(always)]
-    pub const fn dbg_tcr(self) -> crate::common::Reg<u32, crate::common::R> {
+    pub const fn dbg_tcr(self) -> crate::common::Reg<u32, crate::common::RW> {
         unsafe { crate::common::Reg::from_ptr(self.ptr.add(2052usize) as _) }
     }
 }
@@ -145,6 +145,11 @@ impl Dma {
     pub const fn ints0(self) -> crate::common::Reg<regs::Ints0, crate::common::RW> {
         unsafe { crate::common::Reg::from_ptr(self.ptr.add(1036usize) as _) }
     }
+    #[doc = "Interrupt Status (raw)"]
+    #[inline(always)]
+    pub const fn intr1(self) -> crate::common::Reg<regs::Intr1, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(1040usize) as _) }
+    }
     #[doc = "Interrupt Enables for IRQ 1"]
     #[inline(always)]
     pub const fn inte1(self) -> crate::common::Reg<regs::Inte1, crate::common::RW> {
@@ -178,7 +183,7 @@ impl Dma {
     pub const fn sniff_ctrl(self) -> crate::common::Reg<regs::SniffCtrl, crate::common::RW> {
         unsafe { crate::common::Reg::from_ptr(self.ptr.add(1076usize) as _) }
     }
-    #[doc = "Data accumulator for sniff hardware Write an initial seed value here before starting a DMA transfer on the channel indicated by SNIFF_CTRL_DMACH. The hardware will update this register each time it observes a read from the indicated channel. Once the channel completes, the final result can be read from this register."]
+    #[doc = "Data accumulator for sniff hardware"]
     #[inline(always)]
     pub const fn sniff_data(self) -> crate::common::Reg<u32, crate::common::RW> {
         unsafe { crate::common::Reg::from_ptr(self.ptr.add(1080usize) as _) }
diff --git a/src/dma/regs.rs b/src/rp2040/dma/regs.rs
similarity index 94%
rename from src/dma/regs.rs
rename to src/rp2040/dma/regs.rs
index 3306ca56..e4b4f561 100644
--- a/src/dma/regs.rs
+++ b/src/rp2040/dma/regs.rs
@@ -21,7 +21,7 @@ impl Default for ChanAbort {
         ChanAbort(0)
     }
 }
-#[doc = "DMA Channel 6 Control and Status"]
+#[doc = "DMA Channel 11 Control and Status"]
 #[repr(transparent)]
 #[derive(Copy, Clone, Eq, PartialEq)]
 pub struct CtrlTrig(pub u32);
@@ -390,6 +390,29 @@ impl Default for Intr {
         Intr(0)
     }
 }
+#[doc = "Interrupt Status (raw)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Intr1(pub u32);
+impl Intr1 {
+    #[doc = "Raw interrupt status for DMA Channels 0..15. Bit n corresponds to channel n. Ignores any masking or forcing. Channel interrupts can be cleared by writing a bit mask to INTR, INTS0 or INTS1. Channel interrupts can be routed to either of two system-level IRQs based on INTE0 and INTE1. This can be used vector different channel interrupts to different ISRs: this might be done to allow NVIC IRQ preemption for more time-critical channels, or to spread IRQ load across different cores. It is also valid to ignore this behaviour and just use INTE0/INTS0/IRQ 0."]
+    #[inline(always)]
+    pub const fn intr1(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0xffff;
+        val as u16
+    }
+    #[doc = "Raw interrupt status for DMA Channels 0..15. Bit n corresponds to channel n. Ignores any masking or forcing. Channel interrupts can be cleared by writing a bit mask to INTR, INTS0 or INTS1. Channel interrupts can be routed to either of two system-level IRQs based on INTE0 and INTE1. This can be used vector different channel interrupts to different ISRs: this might be done to allow NVIC IRQ preemption for more time-critical channels, or to spread IRQ load across different cores. It is also valid to ignore this behaviour and just use INTE0/INTS0/IRQ 0."]
+    #[inline(always)]
+    pub fn set_intr1(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+    }
+}
+impl Default for Intr1 {
+    #[inline(always)]
+    fn default() -> Intr1 {
+        Intr1(0)
+    }
+}
 #[doc = "Interrupt Status for IRQ 0"]
 #[repr(transparent)]
 #[derive(Copy, Clone, Eq, PartialEq)]
diff --git a/src/rp2040/dma/vals.rs b/src/rp2040/dma/vals.rs
new file mode 100644
index 00000000..16ff1a32
--- /dev/null
+++ b/src/rp2040/dma/vals.rs
@@ -0,0 +1,213 @@
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Calc {
+    #[doc = "Calculate a CRC-32 (IEEE802.3 polynomial)"]
+    CRC32 = 0,
+    #[doc = "Calculate a CRC-32 (IEEE802.3 polynomial) with bit reversed data"]
+    CRC32R = 0x01,
+    #[doc = "Calculate a CRC-16-CCITT"]
+    CRC16 = 0x02,
+    #[doc = "Calculate a CRC-16-CCITT with bit reversed data"]
+    CRC16R = 0x03,
+    _RESERVED_4 = 0x04,
+    _RESERVED_5 = 0x05,
+    _RESERVED_6 = 0x06,
+    _RESERVED_7 = 0x07,
+    _RESERVED_8 = 0x08,
+    _RESERVED_9 = 0x09,
+    _RESERVED_a = 0x0a,
+    _RESERVED_b = 0x0b,
+    _RESERVED_c = 0x0c,
+    _RESERVED_d = 0x0d,
+    #[doc = "XOR reduction over all data. == 1 if the total 1 population count is odd."]
+    EVEN = 0x0e,
+    #[doc = "Calculate a simple 32-bit checksum (addition with a 32 bit accumulator)"]
+    SUM = 0x0f,
+}
+impl Calc {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Calc {
+        unsafe { core::mem::transmute(val & 0x0f) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Calc {
+    #[inline(always)]
+    fn from(val: u8) -> Calc {
+        Calc::from_bits(val)
+    }
+}
+impl From<Calc> for u8 {
+    #[inline(always)]
+    fn from(val: Calc) -> u8 {
+        Calc::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum DataSize {
+    SIZE_BYTE = 0,
+    SIZE_HALFWORD = 0x01,
+    SIZE_WORD = 0x02,
+    _RESERVED_3 = 0x03,
+}
+impl DataSize {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> DataSize {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for DataSize {
+    #[inline(always)]
+    fn from(val: u8) -> DataSize {
+        DataSize::from_bits(val)
+    }
+}
+impl From<DataSize> for u8 {
+    #[inline(always)]
+    fn from(val: DataSize) -> u8 {
+        DataSize::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum TreqSel {
+    #[doc = "Select PIO0's TX FIFO 0 as TREQ"]
+    PIO0_TX0 = 0,
+    #[doc = "Select PIO0's TX FIFO 1 as TREQ"]
+    PIO0_TX1 = 0x01,
+    #[doc = "Select PIO0's TX FIFO 2 as TREQ"]
+    PIO0_TX2 = 0x02,
+    #[doc = "Select PIO0's TX FIFO 3 as TREQ"]
+    PIO0_TX3 = 0x03,
+    #[doc = "Select PIO0's RX FIFO 0 as TREQ"]
+    PIO0_RX0 = 0x04,
+    #[doc = "Select PIO0's RX FIFO 1 as TREQ"]
+    PIO0_RX1 = 0x05,
+    #[doc = "Select PIO0's RX FIFO 2 as TREQ"]
+    PIO0_RX2 = 0x06,
+    #[doc = "Select PIO0's RX FIFO 3 as TREQ"]
+    PIO0_RX3 = 0x07,
+    #[doc = "Select PIO1's TX FIFO 0 as TREQ"]
+    PIO1_TX0 = 0x08,
+    #[doc = "Select PIO1's TX FIFO 1 as TREQ"]
+    PIO1_TX1 = 0x09,
+    #[doc = "Select PIO1's TX FIFO 2 as TREQ"]
+    PIO1_TX2 = 0x0a,
+    #[doc = "Select PIO1's TX FIFO 3 as TREQ"]
+    PIO1_TX3 = 0x0b,
+    #[doc = "Select PIO1's RX FIFO 0 as TREQ"]
+    PIO1_RX0 = 0x0c,
+    #[doc = "Select PIO1's RX FIFO 1 as TREQ"]
+    PIO1_RX1 = 0x0d,
+    #[doc = "Select PIO1's RX FIFO 2 as TREQ"]
+    PIO1_RX2 = 0x0e,
+    #[doc = "Select PIO1's RX FIFO 3 as TREQ"]
+    PIO1_RX3 = 0x0f,
+    #[doc = "Select SPI0's TX FIFO as TREQ"]
+    SPI0_TX = 0x10,
+    #[doc = "Select SPI0's RX FIFO as TREQ"]
+    SPI0_RX = 0x11,
+    #[doc = "Select SPI1's TX FIFO as TREQ"]
+    SPI1_TX = 0x12,
+    #[doc = "Select SPI1's RX FIFO as TREQ"]
+    SPI1_RX = 0x13,
+    #[doc = "Select UART0's TX FIFO as TREQ"]
+    UART0_TX = 0x14,
+    #[doc = "Select UART0's RX FIFO as TREQ"]
+    UART0_RX = 0x15,
+    #[doc = "Select UART1's TX FIFO as TREQ"]
+    UART1_TX = 0x16,
+    #[doc = "Select UART1's RX FIFO as TREQ"]
+    UART1_RX = 0x17,
+    #[doc = "Select PWM Counter 0's Wrap Value as TREQ"]
+    PWM_WRAP0 = 0x18,
+    #[doc = "Select PWM Counter 1's Wrap Value as TREQ"]
+    PWM_WRAP1 = 0x19,
+    #[doc = "Select PWM Counter 2's Wrap Value as TREQ"]
+    PWM_WRAP2 = 0x1a,
+    #[doc = "Select PWM Counter 3's Wrap Value as TREQ"]
+    PWM_WRAP3 = 0x1b,
+    #[doc = "Select PWM Counter 4's Wrap Value as TREQ"]
+    PWM_WRAP4 = 0x1c,
+    #[doc = "Select PWM Counter 5's Wrap Value as TREQ"]
+    PWM_WRAP5 = 0x1d,
+    #[doc = "Select PWM Counter 6's Wrap Value as TREQ"]
+    PWM_WRAP6 = 0x1e,
+    #[doc = "Select PWM Counter 7's Wrap Value as TREQ"]
+    PWM_WRAP7 = 0x1f,
+    #[doc = "Select I2C0's TX FIFO as TREQ"]
+    I2C0_TX = 0x20,
+    #[doc = "Select I2C0's RX FIFO as TREQ"]
+    I2C0_RX = 0x21,
+    #[doc = "Select I2C1's TX FIFO as TREQ"]
+    I2C1_TX = 0x22,
+    #[doc = "Select I2C1's RX FIFO as TREQ"]
+    I2C1_RX = 0x23,
+    #[doc = "Select the ADC as TREQ"]
+    ADC = 0x24,
+    #[doc = "Select the XIP Streaming FIFO as TREQ"]
+    XIP_STREAM = 0x25,
+    #[doc = "Select the XIP SSI TX FIFO as TREQ"]
+    XIP_SSITX = 0x26,
+    #[doc = "Select the XIP SSI RX FIFO as TREQ"]
+    XIP_SSIRX = 0x27,
+    _RESERVED_28 = 0x28,
+    _RESERVED_29 = 0x29,
+    _RESERVED_2a = 0x2a,
+    _RESERVED_2b = 0x2b,
+    _RESERVED_2c = 0x2c,
+    _RESERVED_2d = 0x2d,
+    _RESERVED_2e = 0x2e,
+    _RESERVED_2f = 0x2f,
+    _RESERVED_30 = 0x30,
+    _RESERVED_31 = 0x31,
+    _RESERVED_32 = 0x32,
+    _RESERVED_33 = 0x33,
+    _RESERVED_34 = 0x34,
+    _RESERVED_35 = 0x35,
+    _RESERVED_36 = 0x36,
+    _RESERVED_37 = 0x37,
+    _RESERVED_38 = 0x38,
+    _RESERVED_39 = 0x39,
+    _RESERVED_3a = 0x3a,
+    #[doc = "Select Timer 0 as TREQ"]
+    TIMER0 = 0x3b,
+    #[doc = "Select Timer 1 as TREQ"]
+    TIMER1 = 0x3c,
+    #[doc = "Select Timer 2 as TREQ (Optional)"]
+    TIMER2 = 0x3d,
+    #[doc = "Select Timer 3 as TREQ (Optional)"]
+    TIMER3 = 0x3e,
+    #[doc = "Permanent request, for unpaced transfers."]
+    PERMANENT = 0x3f,
+}
+impl TreqSel {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> TreqSel {
+        unsafe { core::mem::transmute(val & 0x3f) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for TreqSel {
+    #[inline(always)]
+    fn from(val: u8) -> TreqSel {
+        TreqSel::from_bits(val)
+    }
+}
+impl From<TreqSel> for u8 {
+    #[inline(always)]
+    fn from(val: TreqSel) -> u8 {
+        TreqSel::to_bits(val)
+    }
+}
diff --git a/src/i2c.rs b/src/rp2040/i2c.rs
similarity index 100%
rename from src/i2c.rs
rename to src/rp2040/i2c.rs
diff --git a/src/i2c/regs.rs b/src/rp2040/i2c/regs.rs
similarity index 100%
rename from src/i2c/regs.rs
rename to src/rp2040/i2c/regs.rs
diff --git a/src/i2c/vals.rs b/src/rp2040/i2c/vals.rs
similarity index 100%
rename from src/i2c/vals.rs
rename to src/rp2040/i2c/vals.rs
diff --git a/src/io.rs b/src/rp2040/io.rs
similarity index 100%
rename from src/io.rs
rename to src/rp2040/io.rs
diff --git a/src/io/regs.rs b/src/rp2040/io/regs.rs
similarity index 99%
rename from src/io/regs.rs
rename to src/rp2040/io/regs.rs
index 40595ff9..7415f977 100644
--- a/src/io/regs.rs
+++ b/src/rp2040/io/regs.rs
@@ -157,7 +157,7 @@ impl Default for GpioStatus {
         GpioStatus(0)
     }
 }
-#[doc = "Interrupt status after masking & forcing for dormant_wake"]
+#[doc = "Interrupt Enable for proc0"]
 #[repr(transparent)]
 #[derive(Copy, Clone, Eq, PartialEq)]
 pub struct Int(pub u32);
diff --git a/src/io/vals.rs b/src/rp2040/io/vals.rs
similarity index 100%
rename from src/io/vals.rs
rename to src/rp2040/io/vals.rs
diff --git a/src/rp2040/mod.rs b/src/rp2040/mod.rs
new file mode 100644
index 00000000..ba88aca3
--- /dev/null
+++ b/src/rp2040/mod.rs
@@ -0,0 +1,171 @@
+#![no_std]
+#![doc = "Peripheral access API (generated using chiptool v0.1.0 (d290630 2023-06-29))"]
+#[derive(Copy, Clone, Debug, PartialEq, Eq)]
+pub enum Interrupt {
+    #[doc = "0 - TIMER_IRQ_0"]
+    TIMER_IRQ_0 = 0,
+    #[doc = "1 - TIMER_IRQ_1"]
+    TIMER_IRQ_1 = 1,
+    #[doc = "2 - TIMER_IRQ_2"]
+    TIMER_IRQ_2 = 2,
+    #[doc = "3 - TIMER_IRQ_3"]
+    TIMER_IRQ_3 = 3,
+    #[doc = "4 - PWM_IRQ_WRAP"]
+    PWM_IRQ_WRAP = 4,
+    #[doc = "5 - USBCTRL_IRQ"]
+    USBCTRL_IRQ = 5,
+    #[doc = "6 - XIP_IRQ"]
+    XIP_IRQ = 6,
+    #[doc = "7 - PIO0_IRQ_0"]
+    PIO0_IRQ_0 = 7,
+    #[doc = "8 - PIO0_IRQ_1"]
+    PIO0_IRQ_1 = 8,
+    #[doc = "9 - PIO1_IRQ_0"]
+    PIO1_IRQ_0 = 9,
+    #[doc = "10 - PIO1_IRQ_1"]
+    PIO1_IRQ_1 = 10,
+    #[doc = "11 - DMA_IRQ_0"]
+    DMA_IRQ_0 = 11,
+    #[doc = "12 - DMA_IRQ_1"]
+    DMA_IRQ_1 = 12,
+    #[doc = "13 - IO_IRQ_BANK0"]
+    IO_IRQ_BANK0 = 13,
+    #[doc = "14 - IO_IRQ_QSPI"]
+    IO_IRQ_QSPI = 14,
+    #[doc = "15 - SIO_IRQ_PROC0"]
+    SIO_IRQ_PROC0 = 15,
+    #[doc = "16 - SIO_IRQ_PROC1"]
+    SIO_IRQ_PROC1 = 16,
+    #[doc = "17 - CLOCKS_IRQ"]
+    CLOCKS_IRQ = 17,
+    #[doc = "18 - SPI0_IRQ"]
+    SPI0_IRQ = 18,
+    #[doc = "19 - SPI1_IRQ"]
+    SPI1_IRQ = 19,
+    #[doc = "20 - UART0_IRQ"]
+    UART0_IRQ = 20,
+    #[doc = "21 - UART1_IRQ"]
+    UART1_IRQ = 21,
+    #[doc = "22 - ADC_IRQ_FIFO"]
+    ADC_IRQ_FIFO = 22,
+    #[doc = "23 - I2C0_IRQ"]
+    I2C0_IRQ = 23,
+    #[doc = "24 - I2C1_IRQ"]
+    I2C1_IRQ = 24,
+    #[doc = "25 - RTC_IRQ"]
+    RTC_IRQ = 25,
+    #[doc = "26 - SWI_IRQ_0"]
+    SWI_IRQ_0 = 26,
+    #[doc = "27 - SWI_IRQ_1"]
+    SWI_IRQ_1 = 27,
+    #[doc = "28 - SWI_IRQ_2"]
+    SWI_IRQ_2 = 28,
+    #[doc = "29 - SWI_IRQ_3"]
+    SWI_IRQ_3 = 29,
+    #[doc = "30 - SWI_IRQ_4"]
+    SWI_IRQ_4 = 30,
+    #[doc = "31 - SWI_IRQ_5"]
+    SWI_IRQ_5 = 31,
+}
+unsafe impl cortex_m::interrupt::InterruptNumber for Interrupt {
+    #[inline(always)]
+    fn number(self) -> u16 {
+        self as u16
+    }
+}
+#[cfg(feature = "rt")]
+mod _vectors;
+#[doc = "QSPI flash execute-in-place block"]
+pub const XIP_CTRL: xip_ctrl::XipCtrl =
+    unsafe { xip_ctrl::XipCtrl::from_ptr(0x1400_0000 as usize as _) };
+#[doc = "DW_apb_ssi has the following features: * APB interface – Allows for easy integration into a DesignWare Synthesizable Components for AMBA 2 implementation. * APB3 and APB4 protocol support. * Scalable APB data bus width – Supports APB data bus widths of 8, 16, and 32 bits. * Serial-master or serial-slave operation – Enables serial communication with serial-master or serial-slave peripheral devices. * Programmable Dual/Quad/Octal SPI support in Master Mode. * Dual Data Rate (DDR) and Read Data Strobe (RDS) Support - Enables the DW_apb_ssi master to perform operations with the device in DDR and RDS modes when working in Dual/Quad/Octal mode of operation. * Data Mask Support - Enables the DW_apb_ssi to selectively update the bytes in the device. This feature is applicable only in enhanced SPI modes. * eXecute-In-Place (XIP) support - Enables the DW_apb_ssi master to behave as a memory mapped I/O and fetches the data from the device based on the APB read request. This feature is applicable only in enhanced SPI modes. * DMA Controller Interface – Enables the DW_apb_ssi to interface to a DMA controller over the bus using a handshaking interface for transfer requests. * Independent masking of interrupts – Master collision, transmit FIFO overflow, transmit FIFO empty, receive FIFO full, receive FIFO underflow, and receive FIFO overflow interrupts can all be masked independently. * Multi-master contention detection – Informs the processor of multiple serial-master accesses on the serial bus. * Bypass of meta-stability flip-flops for synchronous clocks – When the APB clock (pclk) and the DW_apb_ssi serial clock (ssi_clk) are synchronous, meta-stable flip-flops are not used when transferring control signals across these clock domains. * Programmable delay on the sample time of the received serial data bit (rxd); enables programmable control of routing delays resulting in higher serial data-bit rates. * Programmable features: - Serial interface operation – Choice of Motorola SPI, Texas Instruments Synchronous Serial Protocol or National Semiconductor Microwire. - Clock bit-rate – Dynamic control of the serial bit rate of the data transfer; used in only serial-master mode of operation. - Data Item size (4 to 32 bits) – Item size of each data transfer under the control of the programmer. * Configured features: - FIFO depth – 16 words deep. The FIFO width is fixed at 32 bits. - 1 slave select output. - Hardware slave-select – Dedicated hardware slave-select line. - Combined interrupt line - one combined interrupt line from the DW_apb_ssi to the interrupt controller. - Interrupt polarity – active high interrupt lines. - Serial clock polarity – low serial-clock polarity directly after reset. - Serial clock phase – capture on first edge of serial-clock directly after reset."]
+pub const SSI: ssi::Ssi = unsafe { ssi::Ssi::from_ptr(0x1800_0000 as usize as _) };
+pub const SYSINFO: sysinfo::Sysinfo =
+    unsafe { sysinfo::Sysinfo::from_ptr(0x4000_0000 as usize as _) };
+#[doc = "Register block for various chip control signals"]
+pub const SYSCFG: syscfg::Syscfg = unsafe { syscfg::Syscfg::from_ptr(0x4000_4000 as usize as _) };
+pub const CLOCKS: clocks::Clocks = unsafe { clocks::Clocks::from_ptr(0x4000_8000 as usize as _) };
+pub const RESETS: resets::Resets = unsafe { resets::Resets::from_ptr(0x4000_c000 as usize as _) };
+pub const PSM: psm::Psm = unsafe { psm::Psm::from_ptr(0x4001_0000 as usize as _) };
+pub const IO_BANK0: io::Io = unsafe { io::Io::from_ptr(0x4001_4000 as usize as _) };
+pub const IO_QSPI: io::Io = unsafe { io::Io::from_ptr(0x4001_8000 as usize as _) };
+pub const PADS_BANK0: pads::Pads = unsafe { pads::Pads::from_ptr(0x4001_c000 as usize as _) };
+pub const PADS_QSPI: pads::Pads = unsafe { pads::Pads::from_ptr(0x4002_0000 as usize as _) };
+#[doc = "Controls the crystal oscillator"]
+pub const XOSC: xosc::Xosc = unsafe { xosc::Xosc::from_ptr(0x4002_4000 as usize as _) };
+pub const PLL_SYS: pll::Pll = unsafe { pll::Pll::from_ptr(0x4002_8000 as usize as _) };
+pub const PLL_USB: pll::Pll = unsafe { pll::Pll::from_ptr(0x4002_c000 as usize as _) };
+#[doc = "Register block for busfabric control signals and performance counters"]
+pub const BUSCTRL: busctrl::Busctrl =
+    unsafe { busctrl::Busctrl::from_ptr(0x4003_0000 as usize as _) };
+pub const UART0: uart::Uart = unsafe { uart::Uart::from_ptr(0x4003_4000 as usize as _) };
+pub const UART1: uart::Uart = unsafe { uart::Uart::from_ptr(0x4003_8000 as usize as _) };
+pub const SPI0: spi::Spi = unsafe { spi::Spi::from_ptr(0x4003_c000 as usize as _) };
+pub const SPI1: spi::Spi = unsafe { spi::Spi::from_ptr(0x4004_0000 as usize as _) };
+#[doc = "DW_apb_i2c address block List of configuration constants for the Synopsys I2C hardware (you may see references to these in I2C register header; these are *fixed* values, set at hardware design time): IC_ULTRA_FAST_MODE ................ 0x0 IC_UFM_TBUF_CNT_DEFAULT ........... 0x8 IC_UFM_SCL_LOW_COUNT .............. 0x0008 IC_UFM_SCL_HIGH_COUNT ............. 0x0006 IC_TX_TL .......................... 0x0 IC_TX_CMD_BLOCK ................... 0x1 IC_HAS_DMA ........................ 0x1 IC_HAS_ASYNC_FIFO ................. 0x0 IC_SMBUS_ARP ...................... 0x0 IC_FIRST_DATA_BYTE_STATUS ......... 0x1 IC_INTR_IO ........................ 0x1 IC_MASTER_MODE .................... 0x1 IC_DEFAULT_ACK_GENERAL_CALL ....... 0x1 IC_INTR_POL ....................... 0x1 IC_OPTIONAL_SAR ................... 0x0 IC_DEFAULT_TAR_SLAVE_ADDR ......... 0x055 IC_DEFAULT_SLAVE_ADDR ............. 0x055 IC_DEFAULT_HS_SPKLEN .............. 0x1 IC_FS_SCL_HIGH_COUNT .............. 0x0006 IC_HS_SCL_LOW_COUNT ............... 0x0008 IC_DEVICE_ID_VALUE ................ 0x0 IC_10BITADDR_MASTER ............... 0x0 IC_CLK_FREQ_OPTIMIZATION .......... 0x0 IC_DEFAULT_FS_SPKLEN .............. 0x7 IC_ADD_ENCODED_PARAMS ............. 0x0 IC_DEFAULT_SDA_HOLD ............... 0x000001 IC_DEFAULT_SDA_SETUP .............. 0x64 IC_AVOID_RX_FIFO_FLUSH_ON_TX_ABRT . 0x0 IC_CLOCK_PERIOD ................... 100 IC_EMPTYFIFO_HOLD_MASTER_EN ....... 1 IC_RESTART_EN ..................... 0x1 IC_TX_CMD_BLOCK_DEFAULT ........... 0x0 IC_BUS_CLEAR_FEATURE .............. 0x0 IC_CAP_LOADING .................... 100 IC_FS_SCL_LOW_COUNT ............... 0x000d APB_DATA_WIDTH .................... 32 IC_SDA_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff IC_SLV_DATA_NACK_ONLY ............. 0x1 IC_10BITADDR_SLAVE ................ 0x0 IC_CLK_TYPE ....................... 0x0 IC_SMBUS_UDID_MSB ................. 0x0 IC_SMBUS_SUSPEND_ALERT ............ 0x0 IC_HS_SCL_HIGH_COUNT .............. 0x0006 IC_SLV_RESTART_DET_EN ............. 0x1 IC_SMBUS .......................... 0x0 IC_OPTIONAL_SAR_DEFAULT ........... 0x0 IC_PERSISTANT_SLV_ADDR_DEFAULT .... 0x0 IC_USE_COUNTS ..................... 0x0 IC_RX_BUFFER_DEPTH ................ 16 IC_SCL_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff IC_RX_FULL_HLD_BUS_EN ............. 0x1 IC_SLAVE_DISABLE .................. 0x1 IC_RX_TL .......................... 0x0 IC_DEVICE_ID ...................... 0x0 IC_HC_COUNT_VALUES ................ 0x0 I2C_DYNAMIC_TAR_UPDATE ............ 0 IC_SMBUS_CLK_LOW_MEXT_DEFAULT ..... 0xffffffff IC_SMBUS_CLK_LOW_SEXT_DEFAULT ..... 0xffffffff IC_HS_MASTER_CODE ................. 0x1 IC_SMBUS_RST_IDLE_CNT_DEFAULT ..... 0xffff IC_SMBUS_UDID_LSB_DEFAULT ......... 0xffffffff IC_SS_SCL_HIGH_COUNT .............. 0x0028 IC_SS_SCL_LOW_COUNT ............... 0x002f IC_MAX_SPEED_MODE ................. 0x2 IC_STAT_FOR_CLK_STRETCH ........... 0x0 IC_STOP_DET_IF_MASTER_ACTIVE ...... 0x0 IC_DEFAULT_UFM_SPKLEN ............. 0x1 IC_TX_BUFFER_DEPTH ................ 16"]
+pub const I2C0: i2c::I2c = unsafe { i2c::I2c::from_ptr(0x4004_4000 as usize as _) };
+pub const I2C1: i2c::I2c = unsafe { i2c::I2c::from_ptr(0x4004_8000 as usize as _) };
+#[doc = "Control and data interface to SAR ADC"]
+pub const ADC: adc::Adc = unsafe { adc::Adc::from_ptr(0x4004_c000 as usize as _) };
+#[doc = "Simple PWM"]
+pub const PWM: pwm::Pwm = unsafe { pwm::Pwm::from_ptr(0x4005_0000 as usize as _) };
+#[doc = "Controls time and alarms time is a 64 bit value indicating the time in usec since power-on timeh is the top 32 bits of time & timel is the bottom 32 bits to change time write to timelw before timehw to read time read from timelr before timehr An alarm is set by setting alarm_enable and writing to the corresponding alarm register When an alarm is pending, the corresponding alarm_running signal will be high An alarm can be cancelled before it has finished by clearing the alarm_enable When an alarm fires, the corresponding alarm_irq is set and alarm_running is cleared To clear the interrupt write a 1 to the corresponding alarm_irq"]
+pub const TIMER: timer::Timer = unsafe { timer::Timer::from_ptr(0x4005_4000 as usize as _) };
+pub const WATCHDOG: watchdog::Watchdog =
+    unsafe { watchdog::Watchdog::from_ptr(0x4005_8000 as usize as _) };
+#[doc = "Register block to control RTC"]
+pub const RTC: rtc::Rtc = unsafe { rtc::Rtc::from_ptr(0x4005_c000 as usize as _) };
+pub const ROSC: rosc::Rosc = unsafe { rosc::Rosc::from_ptr(0x4006_0000 as usize as _) };
+#[doc = "control and status for on-chip voltage regulator and chip level reset subsystem"]
+pub const VREG_AND_CHIP_RESET: vreg_and_chip_reset::VregAndChipReset =
+    unsafe { vreg_and_chip_reset::VregAndChipReset::from_ptr(0x4006_4000 as usize as _) };
+#[doc = "Testbench manager. Allows the programmer to know what platform their software is running on."]
+pub const TBMAN: tbman::Tbman = unsafe { tbman::Tbman::from_ptr(0x4006_c000 as usize as _) };
+#[doc = "DMA with separate read and write masters"]
+pub const DMA: dma::Dma = unsafe { dma::Dma::from_ptr(0x5000_0000 as usize as _) };
+#[doc = "DPRAM layout for USB device."]
+pub const USB_DPRAM: usb_dpram::UsbDpram =
+    unsafe { usb_dpram::UsbDpram::from_ptr(0x5010_0000 as usize as _) };
+#[doc = "USB FS/LS controller device registers"]
+pub const USB: usb::Usb = unsafe { usb::Usb::from_ptr(0x5011_0000 as usize as _) };
+#[doc = "Programmable IO block"]
+pub const PIO0: pio::Pio = unsafe { pio::Pio::from_ptr(0x5020_0000 as usize as _) };
+pub const PIO1: pio::Pio = unsafe { pio::Pio::from_ptr(0x5030_0000 as usize as _) };
+#[doc = "Single-cycle IO block Provides core-local and inter-core hardware for the two processors, with single-cycle access."]
+pub const SIO: sio::Sio = unsafe { sio::Sio::from_ptr(0xd000_0000 as usize as _) };
+#[doc = r" Number available in the NVIC for configuring priority"]
+#[cfg(feature = "rt")]
+pub const NVIC_PRIO_BITS: u8 = 2;
+#[cfg(feature = "rt")]
+pub use cortex_m_rt::interrupt;
+#[cfg(feature = "rt")]
+pub use Interrupt as interrupt;
+pub mod adc;
+pub mod busctrl;
+pub mod clocks;
+pub mod common;
+pub mod dma;
+pub mod i2c;
+pub mod io;
+pub mod pads;
+pub mod pio;
+pub mod pll;
+pub mod psm;
+pub mod pwm;
+pub mod resets;
+pub mod rosc;
+pub mod rtc;
+pub mod sio;
+pub mod spi;
+pub mod ssi;
+pub mod syscfg;
+pub mod sysinfo;
+pub mod tbman;
+pub mod timer;
+pub mod uart;
+pub mod usb;
+pub mod usb_dpram;
+pub mod vreg_and_chip_reset;
+pub mod watchdog;
+pub mod xip_ctrl;
+pub mod xosc;
diff --git a/src/pads.rs b/src/rp2040/pads.rs
similarity index 100%
rename from src/pads.rs
rename to src/rp2040/pads.rs
diff --git a/src/pads/regs.rs b/src/rp2040/pads/regs.rs
similarity index 100%
rename from src/pads/regs.rs
rename to src/rp2040/pads/regs.rs
diff --git a/src/pads/vals.rs b/src/rp2040/pads/vals.rs
similarity index 100%
rename from src/pads/vals.rs
rename to src/rp2040/pads/vals.rs
diff --git a/src/pio.rs b/src/rp2040/pio.rs
similarity index 94%
rename from src/pio.rs
rename to src/rp2040/pio.rs
index 29068f8e..7eb55ace 100644
--- a/src/pio.rs
+++ b/src/rp2040/pio.rs
@@ -13,17 +13,17 @@ impl Irq {
     pub const fn as_ptr(&self) -> *mut () {
         self.ptr as _
     }
-    #[doc = "Interrupt Enable for irq0"]
+    #[doc = "Interrupt Enable for irq1"]
     #[inline(always)]
     pub const fn inte(self) -> crate::common::Reg<regs::Intr, crate::common::RW> {
         unsafe { crate::common::Reg::from_ptr(self.ptr.add(0usize) as _) }
     }
-    #[doc = "Interrupt Force for irq0"]
+    #[doc = "Interrupt Force for irq1"]
     #[inline(always)]
     pub const fn intf(self) -> crate::common::Reg<regs::Intr, crate::common::RW> {
         unsafe { crate::common::Reg::from_ptr(self.ptr.add(4usize) as _) }
     }
-    #[doc = "Interrupt status after masking & forcing for irq0"]
+    #[doc = "Interrupt status after masking & forcing for irq1"]
     #[inline(always)]
     pub const fn ints(self) -> crate::common::Reg<regs::Intr, crate::common::RW> {
         unsafe { crate::common::Reg::from_ptr(self.ptr.add(8usize) as _) }
@@ -67,13 +67,13 @@ impl Pio {
     }
     #[doc = "Direct write access to the TX FIFO for this state machine. Each write pushes one word to the FIFO. Attempting to write to a full FIFO has no effect on the FIFO state or contents, and sets the sticky FDEBUG_TXOVER error flag for this FIFO."]
     #[inline(always)]
-    pub const fn txf(self, n: usize) -> crate::common::Reg<u32, crate::common::W> {
+    pub const fn txf(self, n: usize) -> crate::common::Reg<u32, crate::common::RW> {
         assert!(n < 4usize);
         unsafe { crate::common::Reg::from_ptr(self.ptr.add(16usize + n * 4usize) as _) }
     }
     #[doc = "Direct read access to the RX FIFO for this state machine. Each read pops one word from the FIFO. Attempting to read from an empty FIFO has no effect on the FIFO state, and sets the sticky FDEBUG_RXUNDER error flag for this FIFO. The data returned to the system on a read from an empty FIFO is undefined."]
     #[inline(always)]
-    pub const fn rxf(self, n: usize) -> crate::common::Reg<u32, crate::common::R> {
+    pub const fn rxf(self, n: usize) -> crate::common::Reg<u32, crate::common::RW> {
         assert!(n < 4usize);
         unsafe { crate::common::Reg::from_ptr(self.ptr.add(32usize + n * 4usize) as _) }
     }
@@ -94,12 +94,12 @@ impl Pio {
     }
     #[doc = "Read to sample the pad output values PIO is currently driving to the GPIOs. On RP2040 there are 30 GPIOs, so the two most significant bits are hardwired to 0."]
     #[inline(always)]
-    pub const fn dbg_padout(self) -> crate::common::Reg<u32, crate::common::R> {
+    pub const fn dbg_padout(self) -> crate::common::Reg<u32, crate::common::RW> {
         unsafe { crate::common::Reg::from_ptr(self.ptr.add(60usize) as _) }
     }
     #[doc = "Read to sample the pad output enables (direction) PIO is currently driving to the GPIOs. On RP2040 there are 30 GPIOs, so the two most significant bits are hardwired to 0."]
     #[inline(always)]
-    pub const fn dbg_padoe(self) -> crate::common::Reg<u32, crate::common::R> {
+    pub const fn dbg_padoe(self) -> crate::common::Reg<u32, crate::common::RW> {
         unsafe { crate::common::Reg::from_ptr(self.ptr.add(64usize) as _) }
     }
     #[doc = "The PIO hardware has some free parameters that may vary between chip products. These should be provided in the chip datasheet, but are also exposed here."]
@@ -147,27 +147,27 @@ impl StateMachine {
     pub const fn as_ptr(&self) -> *mut () {
         self.ptr as _
     }
-    #[doc = "Clock divisor register for state machine 0 Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256)"]
+    #[doc = "Clock divisor register for state machine 2 Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256)"]
     #[inline(always)]
     pub const fn clkdiv(self) -> crate::common::Reg<regs::SmClkdiv, crate::common::RW> {
         unsafe { crate::common::Reg::from_ptr(self.ptr.add(0usize) as _) }
     }
-    #[doc = "Execution/behavioural settings for state machine 0"]
+    #[doc = "Execution/behavioural settings for state machine 2"]
     #[inline(always)]
     pub const fn execctrl(self) -> crate::common::Reg<regs::SmExecctrl, crate::common::RW> {
         unsafe { crate::common::Reg::from_ptr(self.ptr.add(4usize) as _) }
     }
-    #[doc = "Control behaviour of the input/output shift registers for state machine 0"]
+    #[doc = "Control behaviour of the input/output shift registers for state machine 2"]
     #[inline(always)]
     pub const fn shiftctrl(self) -> crate::common::Reg<regs::SmShiftctrl, crate::common::RW> {
         unsafe { crate::common::Reg::from_ptr(self.ptr.add(8usize) as _) }
     }
-    #[doc = "Current instruction address of state machine 0"]
+    #[doc = "Current instruction address of state machine 2"]
     #[inline(always)]
     pub const fn addr(self) -> crate::common::Reg<regs::SmAddr, crate::common::RW> {
         unsafe { crate::common::Reg::from_ptr(self.ptr.add(12usize) as _) }
     }
-    #[doc = "Read to see the instruction currently addressed by state machine 0's program counter Write to execute an instruction immediately (including jumps) and then resume execution."]
+    #[doc = "Read to see the instruction currently addressed by state machine 2's program counter Write to execute an instruction immediately (including jumps) and then resume execution."]
     #[inline(always)]
     pub const fn instr(self) -> crate::common::Reg<regs::SmInstr, crate::common::RW> {
         unsafe { crate::common::Reg::from_ptr(self.ptr.add(16usize) as _) }
diff --git a/src/pio/regs.rs b/src/rp2040/pio/regs.rs
similarity index 99%
rename from src/pio/regs.rs
rename to src/rp2040/pio/regs.rs
index ca04b855..8053d723 100644
--- a/src/pio/regs.rs
+++ b/src/rp2040/pio/regs.rs
@@ -284,7 +284,7 @@ impl Default for Fstat {
         Fstat(0)
     }
 }
-#[doc = "Write-only access to instruction memory location 14"]
+#[doc = "Write-only access to instruction memory location 2"]
 #[repr(transparent)]
 #[derive(Copy, Clone, Eq, PartialEq)]
 pub struct InstrMem(pub u32);
@@ -467,7 +467,7 @@ impl Default for IrqForce {
         IrqForce(0)
     }
 }
-#[doc = "Current instruction address of state machine 0"]
+#[doc = "Current instruction address of state machine 2"]
 #[repr(transparent)]
 #[derive(Copy, Clone, Eq, PartialEq)]
 pub struct SmAddr(pub u32);
@@ -488,7 +488,7 @@ impl Default for SmAddr {
         SmAddr(0)
     }
 }
-#[doc = "Clock divisor register for state machine 2 Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256)"]
+#[doc = "Clock divisor register for state machine 1 Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256)"]
 #[repr(transparent)]
 #[derive(Copy, Clone, Eq, PartialEq)]
 pub struct SmClkdiv(pub u32);
@@ -522,7 +522,7 @@ impl Default for SmClkdiv {
         SmClkdiv(0)
     }
 }
-#[doc = "Execution/behavioural settings for state machine 2"]
+#[doc = "Execution/behavioural settings for state machine 0"]
 #[repr(transparent)]
 #[derive(Copy, Clone, Eq, PartialEq)]
 pub struct SmExecctrl(pub u32);
@@ -655,7 +655,7 @@ impl Default for SmExecctrl {
         SmExecctrl(0)
     }
 }
-#[doc = "Read to see the instruction currently addressed by state machine 0's program counter Write to execute an instruction immediately (including jumps) and then resume execution."]
+#[doc = "Read to see the instruction currently addressed by state machine 3's program counter Write to execute an instruction immediately (including jumps) and then resume execution."]
 #[repr(transparent)]
 #[derive(Copy, Clone, Eq, PartialEq)]
 pub struct SmInstr(pub u32);
diff --git a/src/pio/vals.rs b/src/rp2040/pio/vals.rs
similarity index 100%
rename from src/pio/vals.rs
rename to src/rp2040/pio/vals.rs
diff --git a/src/pll.rs b/src/rp2040/pll.rs
similarity index 100%
rename from src/pll.rs
rename to src/rp2040/pll.rs
diff --git a/src/pll/regs.rs b/src/rp2040/pll/regs.rs
similarity index 100%
rename from src/pll/regs.rs
rename to src/rp2040/pll/regs.rs
diff --git a/src/psm.rs b/src/rp2040/psm.rs
similarity index 100%
rename from src/psm.rs
rename to src/rp2040/psm.rs
diff --git a/src/psm/regs.rs b/src/rp2040/psm/regs.rs
similarity index 100%
rename from src/psm/regs.rs
rename to src/rp2040/psm/regs.rs
diff --git a/src/pwm.rs b/src/rp2040/pwm.rs
similarity index 100%
rename from src/pwm.rs
rename to src/rp2040/pwm.rs
diff --git a/src/pwm/regs.rs b/src/rp2040/pwm/regs.rs
similarity index 100%
rename from src/pwm/regs.rs
rename to src/rp2040/pwm/regs.rs
diff --git a/src/pwm/vals.rs b/src/rp2040/pwm/vals.rs
similarity index 100%
rename from src/pwm/vals.rs
rename to src/rp2040/pwm/vals.rs
diff --git a/src/resets.rs b/src/rp2040/resets.rs
similarity index 100%
rename from src/resets.rs
rename to src/rp2040/resets.rs
diff --git a/src/resets/regs.rs b/src/rp2040/resets/regs.rs
similarity index 98%
rename from src/resets/regs.rs
rename to src/rp2040/resets/regs.rs
index 0a9c9666..22118fa1 100644
--- a/src/resets/regs.rs
+++ b/src/rp2040/resets/regs.rs
@@ -1,4 +1,4 @@
-#[doc = "Reset control. If a bit is set it means the peripheral is in reset. 0 means the peripheral's reset is deasserted."]
+#[doc = "Reset done. If a bit is set then a reset done signal has been returned by the peripheral. This indicates that the peripheral's registers are ready to be accessed."]
 #[repr(transparent)]
 #[derive(Copy, Clone, Eq, PartialEq)]
 pub struct Peripherals(pub u32);
diff --git a/src/rosc.rs b/src/rp2040/rosc.rs
similarity index 90%
rename from src/rosc.rs
rename to src/rp2040/rosc.rs
index aee4e179..be5d2ae4 100644
--- a/src/rosc.rs
+++ b/src/rp2040/rosc.rs
@@ -28,9 +28,9 @@ impl Rosc {
     pub const fn freqb(self) -> crate::common::Reg<regs::Freqb, crate::common::RW> {
         unsafe { crate::common::Reg::from_ptr(self.ptr.add(8usize) as _) }
     }
-    #[doc = "Ring Oscillator pause control This is used to save power by pausing the ROSC On power-up this field is initialised to WAKE An invalid write will also select WAKE Warning: setup the irq before selecting dormant mode"]
+    #[doc = "Ring Oscillator pause control"]
     #[inline(always)]
-    pub const fn dormant(self) -> crate::common::Reg<u32, crate::common::RW> {
+    pub const fn dormant(self) -> crate::common::Reg<regs::Dormant, crate::common::RW> {
         unsafe { crate::common::Reg::from_ptr(self.ptr.add(12usize) as _) }
     }
     #[doc = "Controls the output divider"]
diff --git a/src/rosc/regs.rs b/src/rp2040/rosc/regs.rs
similarity index 91%
rename from src/rosc/regs.rs
rename to src/rp2040/rosc/regs.rs
index 5d61fd98..415645d0 100644
--- a/src/rosc/regs.rs
+++ b/src/rp2040/rosc/regs.rs
@@ -24,13 +24,13 @@ impl Default for Count {
 #[derive(Copy, Clone, Eq, PartialEq)]
 pub struct Ctrl(pub u32);
 impl Ctrl {
-    #[doc = "Controls the number of delay stages in the ROSC ring LOW uses stages 0 to 7 MEDIUM uses stages 0 to 5 HIGH uses stages 0 to 3 TOOHIGH uses stages 0 to 1 and should not be used because its frequency exceeds design specifications The clock output will not glitch when changing the range up one step at a time The clock output will glitch when changing the range down Note: the values here are gray coded which is why HIGH comes before TOOHIGH"]
+    #[doc = "Controls the number of delay stages in the ROSC ring LOW uses stages 0 to 7 MEDIUM uses stages 2 to 7 HIGH uses stages 4 to 7 TOOHIGH uses stages 6 to 7 and should not be used because its frequency exceeds design specifications The clock output will not glitch when changing the range up one step at a time The clock output will glitch when changing the range down Note: the values here are gray coded which is why HIGH comes before TOOHIGH"]
     #[inline(always)]
     pub const fn freq_range(&self) -> super::vals::FreqRange {
         let val = (self.0 >> 0usize) & 0x0fff;
         super::vals::FreqRange::from_bits(val as u16)
     }
-    #[doc = "Controls the number of delay stages in the ROSC ring LOW uses stages 0 to 7 MEDIUM uses stages 0 to 5 HIGH uses stages 0 to 3 TOOHIGH uses stages 0 to 1 and should not be used because its frequency exceeds design specifications The clock output will not glitch when changing the range up one step at a time The clock output will glitch when changing the range down Note: the values here are gray coded which is why HIGH comes before TOOHIGH"]
+    #[doc = "Controls the number of delay stages in the ROSC ring LOW uses stages 0 to 7 MEDIUM uses stages 2 to 7 HIGH uses stages 4 to 7 TOOHIGH uses stages 6 to 7 and should not be used because its frequency exceeds design specifications The clock output will not glitch when changing the range up one step at a time The clock output will glitch when changing the range down Note: the values here are gray coded which is why HIGH comes before TOOHIGH"]
     #[inline(always)]
     pub fn set_freq_range(&mut self, val: super::vals::FreqRange) {
         self.0 = (self.0 & !(0x0fff << 0usize)) | (((val.to_bits() as u32) & 0x0fff) << 0usize);
@@ -76,6 +76,30 @@ impl Default for Div {
         Div(0)
     }
 }
+#[doc = "Ring Oscillator pause control"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Dormant(pub u32);
+impl Dormant {
+    #[doc = "This is used to save power by pausing the ROSC On power-up this field is initialised to WAKE An invalid write will also select WAKE Warning: setup the irq before selecting dormant mode"]
+    #[inline(always)]
+    pub const fn dormant(&self) -> super::vals::Dormant {
+        let val = (self.0 >> 0usize) & 0xffff_ffff;
+        super::vals::Dormant::from_bits(val as u32)
+    }
+    #[doc = "This is used to save power by pausing the ROSC On power-up this field is initialised to WAKE An invalid write will also select WAKE Warning: setup the irq before selecting dormant mode"]
+    #[inline(always)]
+    pub fn set_dormant(&mut self, val: super::vals::Dormant) {
+        self.0 = (self.0 & !(0xffff_ffff << 0usize))
+            | (((val.to_bits() as u32) & 0xffff_ffff) << 0usize);
+    }
+}
+impl Default for Dormant {
+    #[inline(always)]
+    fn default() -> Dormant {
+        Dormant(0)
+    }
+}
 #[doc = "The FREQA & FREQB registers control the frequency by controlling the drive strength of each stage The drive strength has 4 levels determined by the number of bits set Increasing the number of bits set increases the drive strength and increases the oscillation frequency 0 bits set is the default drive strength 1 bit set doubles the drive strength 2 bits set triples drive strength 3 bits set quadruples drive strength"]
 #[repr(transparent)]
 #[derive(Copy, Clone, Eq, PartialEq)]
diff --git a/src/rosc/vals.rs b/src/rp2040/rosc/vals.rs
similarity index 79%
rename from src/rosc/vals.rs
rename to src/rp2040/rosc/vals.rs
index 3ef92549..452dbb00 100644
--- a/src/rosc/vals.rs
+++ b/src/rp2040/rosc/vals.rs
@@ -26,6 +26,33 @@ impl From<Div> for u16 {
 }
 #[repr(transparent)]
 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub struct Dormant(pub u32);
+impl Dormant {
+    pub const DORMANT: Self = Self(0x636f_6d61);
+    pub const WAKE: Self = Self(0x7761_6b65);
+}
+impl Dormant {
+    pub const fn from_bits(val: u32) -> Dormant {
+        Self(val & 0xffff_ffff)
+    }
+    pub const fn to_bits(self) -> u32 {
+        self.0
+    }
+}
+impl From<u32> for Dormant {
+    #[inline(always)]
+    fn from(val: u32) -> Dormant {
+        Dormant::from_bits(val)
+    }
+}
+impl From<Dormant> for u32 {
+    #[inline(always)]
+    fn from(val: Dormant) -> u32 {
+        Dormant::to_bits(val)
+    }
+}
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
 pub struct Enable(pub u16);
 impl Enable {
     pub const DISABLE: Self = Self(0x0d1e);
diff --git a/src/rtc.rs b/src/rp2040/rtc.rs
similarity index 100%
rename from src/rtc.rs
rename to src/rp2040/rtc.rs
diff --git a/src/rtc/regs.rs b/src/rp2040/rtc/regs.rs
similarity index 99%
rename from src/rtc/regs.rs
rename to src/rp2040/rtc/regs.rs
index fb3c9295..da3ac3a8 100644
--- a/src/rtc/regs.rs
+++ b/src/rp2040/rtc/regs.rs
@@ -75,7 +75,7 @@ impl Default for Ctrl {
         Ctrl(0)
     }
 }
-#[doc = "Interrupt Force"]
+#[doc = "Interrupt Enable"]
 #[repr(transparent)]
 #[derive(Copy, Clone, Eq, PartialEq)]
 pub struct Int(pub u32);
diff --git a/src/sio.rs b/src/rp2040/sio.rs
similarity index 96%
rename from src/sio.rs
rename to src/rp2040/sio.rs
index c02782dc..8f397b30 100644
--- a/src/sio.rs
+++ b/src/rp2040/sio.rs
@@ -71,12 +71,12 @@ impl Fifo {
     }
     #[doc = "Write access to this core's TX FIFO"]
     #[inline(always)]
-    pub const fn wr(self) -> crate::common::Reg<u32, crate::common::W> {
+    pub const fn wr(self) -> crate::common::Reg<u32, crate::common::RW> {
         unsafe { crate::common::Reg::from_ptr(self.ptr.add(4usize) as _) }
     }
     #[doc = "Read access to this core's RX FIFO"]
     #[inline(always)]
-    pub const fn rd(self) -> crate::common::Reg<u32, crate::common::R> {
+    pub const fn rd(self) -> crate::common::Reg<u32, crate::common::RW> {
         unsafe { crate::common::Reg::from_ptr(self.ptr.add(8usize) as _) }
     }
 }
@@ -158,57 +158,57 @@ impl Interp {
     }
     #[doc = "Read LANE0 result, and simultaneously write lane results to both accumulators (POP)."]
     #[inline(always)]
-    pub const fn pop_lane0(self) -> crate::common::Reg<u32, crate::common::R> {
+    pub const fn pop_lane0(self) -> crate::common::Reg<u32, crate::common::RW> {
         unsafe { crate::common::Reg::from_ptr(self.ptr.add(20usize) as _) }
     }
     #[doc = "Read LANE1 result, and simultaneously write lane results to both accumulators (POP)."]
     #[inline(always)]
-    pub const fn pop_lane1(self) -> crate::common::Reg<u32, crate::common::R> {
+    pub const fn pop_lane1(self) -> crate::common::Reg<u32, crate::common::RW> {
         unsafe { crate::common::Reg::from_ptr(self.ptr.add(24usize) as _) }
     }
     #[doc = "Read FULL result, and simultaneously write lane results to both accumulators (POP)."]
     #[inline(always)]
-    pub const fn pop_full(self) -> crate::common::Reg<u32, crate::common::R> {
+    pub const fn pop_full(self) -> crate::common::Reg<u32, crate::common::RW> {
         unsafe { crate::common::Reg::from_ptr(self.ptr.add(28usize) as _) }
     }
     #[doc = "Read LANE0 result, without altering any internal state (PEEK)."]
     #[inline(always)]
-    pub const fn peek_lane0(self) -> crate::common::Reg<u32, crate::common::R> {
+    pub const fn peek_lane0(self) -> crate::common::Reg<u32, crate::common::RW> {
         unsafe { crate::common::Reg::from_ptr(self.ptr.add(32usize) as _) }
     }
     #[doc = "Read LANE1 result, without altering any internal state (PEEK)."]
     #[inline(always)]
-    pub const fn peek_lane1(self) -> crate::common::Reg<u32, crate::common::R> {
+    pub const fn peek_lane1(self) -> crate::common::Reg<u32, crate::common::RW> {
         unsafe { crate::common::Reg::from_ptr(self.ptr.add(36usize) as _) }
     }
     #[doc = "Read FULL result, without altering any internal state (PEEK)."]
     #[inline(always)]
-    pub const fn peek_full(self) -> crate::common::Reg<u32, crate::common::R> {
+    pub const fn peek_full(self) -> crate::common::Reg<u32, crate::common::RW> {
         unsafe { crate::common::Reg::from_ptr(self.ptr.add(40usize) as _) }
     }
     #[doc = "Control register for lane 0"]
     #[inline(always)]
-    pub const fn ctrl_lane0(self) -> crate::common::Reg<regs::Interp1ctrlLane0, crate::common::RW> {
+    pub const fn ctrl_lane0(self) -> crate::common::Reg<regs::Interp0ctrlLane0, crate::common::RW> {
         unsafe { crate::common::Reg::from_ptr(self.ptr.add(44usize) as _) }
     }
     #[doc = "Control register for lane 1"]
     #[inline(always)]
-    pub const fn ctrl_lane1(self) -> crate::common::Reg<regs::Interp1ctrlLane1, crate::common::RW> {
+    pub const fn ctrl_lane1(self) -> crate::common::Reg<regs::Interp0ctrlLane1, crate::common::RW> {
         unsafe { crate::common::Reg::from_ptr(self.ptr.add(48usize) as _) }
     }
     #[doc = "Values written here are atomically added to ACCUM0 Reading yields lane 0's raw shift and mask value (BASE0 not added)."]
     #[inline(always)]
-    pub const fn accum0_add(self) -> crate::common::Reg<regs::Interp1accum0add, crate::common::RW> {
+    pub const fn accum0_add(self) -> crate::common::Reg<regs::Interp0accum0add, crate::common::RW> {
         unsafe { crate::common::Reg::from_ptr(self.ptr.add(52usize) as _) }
     }
     #[doc = "Values written here are atomically added to ACCUM1 Reading yields lane 1's raw shift and mask value (BASE1 not added)."]
     #[inline(always)]
-    pub const fn accum1_add(self) -> crate::common::Reg<regs::Interp1accum1add, crate::common::RW> {
+    pub const fn accum1_add(self) -> crate::common::Reg<regs::Interp0accum1add, crate::common::RW> {
         unsafe { crate::common::Reg::from_ptr(self.ptr.add(56usize) as _) }
     }
     #[doc = "On write, the lower 16 bits go to BASE0, upper bits to BASE1 simultaneously. Each half is sign-extended to 32 bits if that lane's SIGNED flag is set."]
     #[inline(always)]
-    pub const fn base_1and0(self) -> crate::common::Reg<u32, crate::common::W> {
+    pub const fn base_1and0(self) -> crate::common::Reg<u32, crate::common::RW> {
         unsafe { crate::common::Reg::from_ptr(self.ptr.add(60usize) as _) }
     }
 }
@@ -228,9 +228,9 @@ impl Sio {
     pub const fn as_ptr(&self) -> *mut () {
         self.ptr as _
     }
-    #[doc = "Processor core identifier Value is 0 when read from processor core 0, and 1 when read from processor core 1."]
+    #[doc = "Processor core identifier"]
     #[inline(always)]
-    pub const fn cpuid(self) -> crate::common::Reg<u32, crate::common::R> {
+    pub const fn cpuid(self) -> crate::common::Reg<u32, crate::common::RW> {
         unsafe { crate::common::Reg::from_ptr(self.ptr.add(0usize) as _) }
     }
     #[doc = "Input value for GPIO pins"]
@@ -255,7 +255,7 @@ impl Sio {
     }
     #[doc = "Spinlock state A bitmap containing the state of all 32 spinlocks (1=locked). Mainly intended for debugging."]
     #[inline(always)]
-    pub const fn spinlock_st(self) -> crate::common::Reg<u32, crate::common::R> {
+    pub const fn spinlock_st(self) -> crate::common::Reg<u32, crate::common::RW> {
         unsafe { crate::common::Reg::from_ptr(self.ptr.add(92usize) as _) }
     }
     #[inline(always)]
diff --git a/src/sio/regs.rs b/src/rp2040/sio/regs.rs
similarity index 100%
rename from src/sio/regs.rs
rename to src/rp2040/sio/regs.rs
diff --git a/src/spi.rs b/src/rp2040/spi.rs
similarity index 100%
rename from src/spi.rs
rename to src/rp2040/spi.rs
diff --git a/src/spi/regs.rs b/src/rp2040/spi/regs.rs
similarity index 100%
rename from src/spi/regs.rs
rename to src/rp2040/spi/regs.rs
diff --git a/src/xip_ssi.rs b/src/rp2040/ssi.rs
similarity index 98%
rename from src/xip_ssi.rs
rename to src/rp2040/ssi.rs
index 64b0af86..f921539f 100644
--- a/src/xip_ssi.rs
+++ b/src/rp2040/ssi.rs
@@ -1,11 +1,11 @@
 #[doc = "DW_apb_ssi has the following features: * APB interface – Allows for easy integration into a DesignWare Synthesizable Components for AMBA 2 implementation. * APB3 and APB4 protocol support. * Scalable APB data bus width – Supports APB data bus widths of 8, 16, and 32 bits. * Serial-master or serial-slave operation – Enables serial communication with serial-master or serial-slave peripheral devices. * Programmable Dual/Quad/Octal SPI support in Master Mode. * Dual Data Rate (DDR) and Read Data Strobe (RDS) Support - Enables the DW_apb_ssi master to perform operations with the device in DDR and RDS modes when working in Dual/Quad/Octal mode of operation. * Data Mask Support - Enables the DW_apb_ssi to selectively update the bytes in the device. This feature is applicable only in enhanced SPI modes. * eXecute-In-Place (XIP) support - Enables the DW_apb_ssi master to behave as a memory mapped I/O and fetches the data from the device based on the APB read request. This feature is applicable only in enhanced SPI modes. * DMA Controller Interface – Enables the DW_apb_ssi to interface to a DMA controller over the bus using a handshaking interface for transfer requests. * Independent masking of interrupts – Master collision, transmit FIFO overflow, transmit FIFO empty, receive FIFO full, receive FIFO underflow, and receive FIFO overflow interrupts can all be masked independently. * Multi-master contention detection – Informs the processor of multiple serial-master accesses on the serial bus. * Bypass of meta-stability flip-flops for synchronous clocks – When the APB clock (pclk) and the DW_apb_ssi serial clock (ssi_clk) are synchronous, meta-stable flip-flops are not used when transferring control signals across these clock domains. * Programmable delay on the sample time of the received serial data bit (rxd); enables programmable control of routing delays resulting in higher serial data-bit rates. * Programmable features: - Serial interface operation – Choice of Motorola SPI, Texas Instruments Synchronous Serial Protocol or National Semiconductor Microwire. - Clock bit-rate – Dynamic control of the serial bit rate of the data transfer; used in only serial-master mode of operation. - Data Item size (4 to 32 bits) – Item size of each data transfer under the control of the programmer. * Configured features: - FIFO depth – 16 words deep. The FIFO width is fixed at 32 bits. - 1 slave select output. - Hardware slave-select – Dedicated hardware slave-select line. - Combined interrupt line - one combined interrupt line from the DW_apb_ssi to the interrupt controller. - Interrupt polarity – active high interrupt lines. - Serial clock polarity – low serial-clock polarity directly after reset. - Serial clock phase – capture on first edge of serial-clock directly after reset."]
 #[derive(Copy, Clone, Eq, PartialEq)]
-pub struct XipSsi {
+pub struct Ssi {
     ptr: *mut u8,
 }
-unsafe impl Send for XipSsi {}
-unsafe impl Sync for XipSsi {}
-impl XipSsi {
+unsafe impl Send for Ssi {}
+unsafe impl Sync for Ssi {}
+impl Ssi {
     #[inline(always)]
     pub const unsafe fn from_ptr(ptr: *mut ()) -> Self {
         Self { ptr: ptr as _ }
diff --git a/src/xip_ssi/regs.rs b/src/rp2040/ssi/regs.rs
similarity index 100%
rename from src/xip_ssi/regs.rs
rename to src/rp2040/ssi/regs.rs
diff --git a/src/xip_ssi/vals.rs b/src/rp2040/ssi/vals.rs
similarity index 100%
rename from src/xip_ssi/vals.rs
rename to src/rp2040/ssi/vals.rs
diff --git a/src/syscfg.rs b/src/rp2040/syscfg.rs
similarity index 93%
rename from src/syscfg.rs
rename to src/rp2040/syscfg.rs
index 20f75abe..951a62e8 100644
--- a/src/syscfg.rs
+++ b/src/rp2040/syscfg.rs
@@ -14,12 +14,12 @@ impl Syscfg {
     pub const fn as_ptr(&self) -> *mut () {
         self.ptr as _
     }
-    #[doc = "Processor core 0 NMI source mask Set a bit high to enable NMI from that IRQ"]
+    #[doc = "Processor core 0 NMI source mask"]
     #[inline(always)]
     pub const fn proc0_nmi_mask(self) -> crate::common::Reg<u32, crate::common::RW> {
         unsafe { crate::common::Reg::from_ptr(self.ptr.add(0usize) as _) }
     }
-    #[doc = "Processor core 1 NMI source mask Set a bit high to enable NMI from that IRQ"]
+    #[doc = "Processor core 1 NMI source mask"]
     #[inline(always)]
     pub const fn proc1_nmi_mask(self) -> crate::common::Reg<u32, crate::common::RW> {
         unsafe { crate::common::Reg::from_ptr(self.ptr.add(4usize) as _) }
diff --git a/src/syscfg/regs.rs b/src/rp2040/syscfg/regs.rs
similarity index 100%
rename from src/syscfg/regs.rs
rename to src/rp2040/syscfg/regs.rs
diff --git a/src/sysinfo.rs b/src/rp2040/sysinfo.rs
similarity index 92%
rename from src/sysinfo.rs
rename to src/rp2040/sysinfo.rs
index 07618cbd..23a44473 100644
--- a/src/sysinfo.rs
+++ b/src/rp2040/sysinfo.rs
@@ -25,8 +25,8 @@ impl Sysinfo {
     }
     #[doc = "Git hash of the chip source. Used to identify chip version."]
     #[inline(always)]
-    pub const fn gitref_rp2040(self) -> crate::common::Reg<u32, crate::common::R> {
-        unsafe { crate::common::Reg::from_ptr(self.ptr.add(64usize) as _) }
+    pub const fn gitref_rp2040(self) -> crate::common::Reg<u32, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(16usize) as _) }
     }
 }
 pub mod regs;
diff --git a/src/sysinfo/regs.rs b/src/rp2040/sysinfo/regs.rs
similarity index 100%
rename from src/sysinfo/regs.rs
rename to src/rp2040/sysinfo/regs.rs
diff --git a/src/tbman.rs b/src/rp2040/tbman.rs
similarity index 100%
rename from src/tbman.rs
rename to src/rp2040/tbman.rs
diff --git a/src/tbman/regs.rs b/src/rp2040/tbman/regs.rs
similarity index 100%
rename from src/tbman/regs.rs
rename to src/rp2040/tbman/regs.rs
diff --git a/src/timer.rs b/src/rp2040/timer.rs
similarity index 98%
rename from src/timer.rs
rename to src/rp2040/timer.rs
index 60798825..97645e5a 100644
--- a/src/timer.rs
+++ b/src/rp2040/timer.rs
@@ -16,22 +16,22 @@ impl Timer {
     }
     #[doc = "Write to bits 63:32 of time always write timelw before timehw"]
     #[inline(always)]
-    pub const fn timehw(self) -> crate::common::Reg<u32, crate::common::W> {
+    pub const fn timehw(self) -> crate::common::Reg<u32, crate::common::RW> {
         unsafe { crate::common::Reg::from_ptr(self.ptr.add(0usize) as _) }
     }
     #[doc = "Write to bits 31:0 of time writes do not get copied to time until timehw is written"]
     #[inline(always)]
-    pub const fn timelw(self) -> crate::common::Reg<u32, crate::common::W> {
+    pub const fn timelw(self) -> crate::common::Reg<u32, crate::common::RW> {
         unsafe { crate::common::Reg::from_ptr(self.ptr.add(4usize) as _) }
     }
     #[doc = "Read from bits 63:32 of time always read timelr before timehr"]
     #[inline(always)]
-    pub const fn timehr(self) -> crate::common::Reg<u32, crate::common::R> {
+    pub const fn timehr(self) -> crate::common::Reg<u32, crate::common::RW> {
         unsafe { crate::common::Reg::from_ptr(self.ptr.add(8usize) as _) }
     }
     #[doc = "Read from bits 31:0 of time"]
     #[inline(always)]
-    pub const fn timelr(self) -> crate::common::Reg<u32, crate::common::R> {
+    pub const fn timelr(self) -> crate::common::Reg<u32, crate::common::RW> {
         unsafe { crate::common::Reg::from_ptr(self.ptr.add(12usize) as _) }
     }
     #[doc = "Arm alarm 0, and configure the time it will fire. Once armed, the alarm fires when TIMER_ALARM0 == TIMELR. The alarm will disarm itself once it fires, and can be disarmed early using the ARMED status register."]
@@ -47,12 +47,12 @@ impl Timer {
     }
     #[doc = "Raw read from bits 63:32 of time (no side effects)"]
     #[inline(always)]
-    pub const fn timerawh(self) -> crate::common::Reg<u32, crate::common::R> {
+    pub const fn timerawh(self) -> crate::common::Reg<u32, crate::common::RW> {
         unsafe { crate::common::Reg::from_ptr(self.ptr.add(36usize) as _) }
     }
     #[doc = "Raw read from bits 31:0 of time (no side effects)"]
     #[inline(always)]
-    pub const fn timerawl(self) -> crate::common::Reg<u32, crate::common::R> {
+    pub const fn timerawl(self) -> crate::common::Reg<u32, crate::common::RW> {
         unsafe { crate::common::Reg::from_ptr(self.ptr.add(40usize) as _) }
     }
     #[doc = "Set bits high to enable pause when the corresponding debug ports are active"]
diff --git a/src/timer/regs.rs b/src/rp2040/timer/regs.rs
similarity index 99%
rename from src/timer/regs.rs
rename to src/rp2040/timer/regs.rs
index 6bbdc0b3..0250acd8 100644
--- a/src/timer/regs.rs
+++ b/src/rp2040/timer/regs.rs
@@ -53,7 +53,7 @@ impl Default for Dbgpause {
         Dbgpause(0)
     }
 }
-#[doc = "Interrupt Enable"]
+#[doc = "Raw Interrupts"]
 #[repr(transparent)]
 #[derive(Copy, Clone, Eq, PartialEq)]
 pub struct Int(pub u32);
diff --git a/src/uart.rs b/src/rp2040/uart.rs
similarity index 100%
rename from src/uart.rs
rename to src/rp2040/uart.rs
diff --git a/src/uart/regs.rs b/src/rp2040/uart/regs.rs
similarity index 100%
rename from src/uart/regs.rs
rename to src/rp2040/uart/regs.rs
diff --git a/src/usb.rs b/src/rp2040/usb.rs
similarity index 93%
rename from src/usb.rs
rename to src/rp2040/usb.rs
index 51a5edb8..1664ac6d 100644
--- a/src/usb.rs
+++ b/src/rp2040/usb.rs
@@ -102,24 +102,23 @@ impl Usb {
     pub const fn usb_muxing(self) -> crate::common::Reg<regs::UsbMuxing, crate::common::RW> {
         unsafe { crate::common::Reg::from_ptr(self.ptr.add(116usize) as _) }
     }
-    #[doc = "Overrides for the power signals in the event that the VBUS signals are not hooked up to GPIO. Set the value of the override and then the override enable to switch over to the override value."]
+    #[doc = "Overrides for the power signals in the event that the VBUS signals are not hooked up to GPIO. Set the value of the override and then the override enable so switch over to the override value."]
     #[inline(always)]
     pub const fn usb_pwr(self) -> crate::common::Reg<regs::UsbPwr, crate::common::RW> {
         unsafe { crate::common::Reg::from_ptr(self.ptr.add(120usize) as _) }
     }
-    #[doc = "This register allows for direct control of the USB phy. Use in conjunction with usbphy_direct_override register to enable each override bit."]
+    #[doc = "Note that most functions are driven directly from usb_fsls controller. This register allows more detailed control/status from the USB PHY. Useful for debug but not expected to be used in normal operation Use in conjunction with usbphy_direct_override register"]
     #[inline(always)]
     pub const fn usbphy_direct(self) -> crate::common::Reg<regs::UsbphyDirect, crate::common::RW> {
         unsafe { crate::common::Reg::from_ptr(self.ptr.add(124usize) as _) }
     }
-    #[doc = "Override enable for each control in usbphy_direct"]
     #[inline(always)]
     pub const fn usbphy_direct_override(
         self,
     ) -> crate::common::Reg<regs::UsbphyDirectOverride, crate::common::RW> {
         unsafe { crate::common::Reg::from_ptr(self.ptr.add(128usize) as _) }
     }
-    #[doc = "Used to adjust trim values of USB phy pull down resistors."]
+    #[doc = "Note that most functions are driven directly from usb_fsls controller. This register allows more detailed control/status from the USB PHY. Useful for debug but not expected to be used in normal operation"]
     #[inline(always)]
     pub const fn usbphy_trim(self) -> crate::common::Reg<regs::UsbphyTrim, crate::common::RW> {
         unsafe { crate::common::Reg::from_ptr(self.ptr.add(132usize) as _) }
diff --git a/src/usb/regs.rs b/src/rp2040/usb/regs.rs
similarity index 90%
rename from src/usb/regs.rs
rename to src/rp2040/usb/regs.rs
index a29fdddf..0c3cf86b 100644
--- a/src/usb/regs.rs
+++ b/src/rp2040/usb/regs.rs
@@ -32,7 +32,7 @@ impl Default for AddrEndp {
         AddrEndp(0)
     }
 }
-#[doc = "Interrupt endpoint 10. Only valid for HOST mode."]
+#[doc = "Interrupt endpoint 2. Only valid for HOST mode."]
 #[repr(transparent)]
 #[derive(Copy, Clone, Eq, PartialEq)]
 pub struct AddrEndpX(pub u32);
@@ -308,7 +308,7 @@ impl Default for EpStatusStallNak {
         EpStatusStallNak(0)
     }
 }
-#[doc = "Interrupt Enable"]
+#[doc = "Raw Interrupts"]
 #[repr(transparent)]
 #[derive(Copy, Clone, Eq, PartialEq)]
 pub struct Int(pub u32);
@@ -324,13 +324,13 @@ impl Int {
     pub fn set_host_conn_dis(&mut self, val: bool) {
         self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
     }
-    #[doc = "Host: raised when a device wakes up the host. Cleared by writing to SIE_STATUS.RESUME"]
+    #[doc = "Host: raised when a device wakes up the host. Cleared by writing to SIE_STATUS.RESUME_REMOTE"]
     #[inline(always)]
     pub const fn host_resume(&self) -> bool {
         let val = (self.0 >> 1usize) & 0x01;
         val != 0
     }
-    #[doc = "Host: raised when a device wakes up the host. Cleared by writing to SIE_STATUS.RESUME"]
+    #[doc = "Host: raised when a device wakes up the host. Cleared by writing to SIE_STATUS.RESUME_REMOTE"]
     #[inline(always)]
     pub fn set_host_resume(&mut self, val: bool) {
         self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
@@ -434,13 +434,13 @@ impl Int {
     pub fn set_stall(&mut self, val: bool) {
         self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize);
     }
-    #[doc = "Source: SIE_STATUS.VBUS_DETECTED"]
+    #[doc = "Source: SIE_STATUS.VBUS_DETECT"]
     #[inline(always)]
     pub const fn vbus_detect(&self) -> bool {
         let val = (self.0 >> 11usize) & 0x01;
         val != 0
     }
-    #[doc = "Source: SIE_STATUS.VBUS_DETECTED"]
+    #[doc = "Source: SIE_STATUS.VBUS_DETECT"]
     #[inline(always)]
     pub fn set_vbus_detect(&mut self, val: bool) {
         self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
@@ -478,13 +478,13 @@ impl Int {
     pub fn set_dev_suspend(&mut self, val: bool) {
         self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize);
     }
-    #[doc = "Set when the device receives a resume from the host. Cleared by writing to SIE_STATUS.RESUME"]
+    #[doc = "Set when the device receives a resume from the host. Cleared by writing to SIE_STATUS.RESUME_REMOTE"]
     #[inline(always)]
     pub const fn dev_resume_from_host(&self) -> bool {
         let val = (self.0 >> 15usize) & 0x01;
         val != 0
     }
-    #[doc = "Set when the device receives a resume from the host. Cleared by writing to SIE_STATUS.RESUME"]
+    #[doc = "Set when the device receives a resume from the host. Cleared by writing to SIE_STATUS.RESUME_REMOTE"]
     #[inline(always)]
     pub fn set_dev_resume_from_host(&mut self, val: bool) {
         self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize);
@@ -545,13 +545,13 @@ impl Default for Int {
 #[derive(Copy, Clone, Eq, PartialEq)]
 pub struct IntEpCtrl(pub u32);
 impl IntEpCtrl {
-    #[doc = "Host: Enable interrupt endpoint 1 -> 15"]
+    #[doc = "Host: Enable interrupt endpoint 1 => 15"]
     #[inline(always)]
     pub const fn int_ep_active(&self) -> u16 {
         let val = (self.0 >> 1usize) & 0x7fff;
         val as u16
     }
-    #[doc = "Host: Enable interrupt endpoint 1 -> 15"]
+    #[doc = "Host: Enable interrupt endpoint 1 => 15"]
     #[inline(always)]
     pub fn set_int_ep_active(&mut self, val: u16) {
         self.0 = (self.0 & !(0x7fff << 1usize)) | (((val as u32) & 0x7fff) << 1usize);
@@ -1218,7 +1218,7 @@ impl Default for UsbMuxing {
         UsbMuxing(0)
     }
 }
-#[doc = "Overrides for the power signals in the event that the VBUS signals are not hooked up to GPIO. Set the value of the override and then the override enable to switch over to the override value."]
+#[doc = "Overrides for the power signals in the event that the VBUS signals are not hooked up to GPIO. Set the value of the override and then the override enable so switch over to the override value."]
 #[repr(transparent)]
 #[derive(Copy, Clone, Eq, PartialEq)]
 pub struct UsbPwr(pub u32);
@@ -1284,238 +1284,230 @@ impl Default for UsbPwr {
         UsbPwr(0)
     }
 }
-#[doc = "This register allows for direct control of the USB phy. Use in conjunction with usbphy_direct_override register to enable each override bit."]
+#[doc = "Note that most functions are driven directly from usb_fsls controller. This register allows more detailed control/status from the USB PHY. Useful for debug but not expected to be used in normal operation Use in conjunction with usbphy_direct_override register"]
 #[repr(transparent)]
 #[derive(Copy, Clone, Eq, PartialEq)]
 pub struct UsbphyDirect(pub u32);
 impl UsbphyDirect {
-    #[doc = "Enable the second DP pull up resistor. 0 - Pull = Rpu2; 1 - Pull = Rpu1 + Rpu2"]
+    #[doc = "when dp_pullup_en is set high, this enables second resistor. 0 - Pull = Rpu2; 1 - Pull = Rpu1 + Rpu2"]
     #[inline(always)]
     pub const fn dp_pullup_hisel(&self) -> bool {
         let val = (self.0 >> 0usize) & 0x01;
         val != 0
     }
-    #[doc = "Enable the second DP pull up resistor. 0 - Pull = Rpu2; 1 - Pull = Rpu1 + Rpu2"]
+    #[doc = "when dp_pullup_en is set high, this enables second resistor. 0 - Pull = Rpu2; 1 - Pull = Rpu1 + Rpu2"]
     #[inline(always)]
     pub fn set_dp_pullup_hisel(&mut self, val: bool) {
         self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
     }
-    #[doc = "DP pull up enable"]
+    #[doc = "Value to drive to USB PHY when override enable is set (which will override the default value or value driven from USB controller"]
     #[inline(always)]
     pub const fn dp_pullup_en(&self) -> bool {
         let val = (self.0 >> 1usize) & 0x01;
         val != 0
     }
-    #[doc = "DP pull up enable"]
+    #[doc = "Value to drive to USB PHY when override enable is set (which will override the default value or value driven from USB controller"]
     #[inline(always)]
     pub fn set_dp_pullup_en(&mut self, val: bool) {
         self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
     }
-    #[doc = "DP pull down enable"]
+    #[doc = "Value to drive to USB PHY when override enable is set (which will override the default value or value driven from USB controller 1 - Enable Rpd on DPP"]
     #[inline(always)]
     pub const fn dp_pulldn_en(&self) -> bool {
         let val = (self.0 >> 2usize) & 0x01;
         val != 0
     }
-    #[doc = "DP pull down enable"]
+    #[doc = "Value to drive to USB PHY when override enable is set (which will override the default value or value driven from USB controller 1 - Enable Rpd on DPP"]
     #[inline(always)]
     pub fn set_dp_pulldn_en(&mut self, val: bool) {
         self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
     }
-    #[doc = "Enable the second DM pull up resistor. 0 - Pull = Rpu2; 1 - Pull = Rpu1 + Rpu2"]
+    #[doc = "when dm_pullup_en is set high, this enables second resistor. 0 - Pull = Rpu2; 1 - Pull = Rpu1 + Rpu2"]
     #[inline(always)]
     pub const fn dm_pullup_hisel(&self) -> bool {
         let val = (self.0 >> 4usize) & 0x01;
         val != 0
     }
-    #[doc = "Enable the second DM pull up resistor. 0 - Pull = Rpu2; 1 - Pull = Rpu1 + Rpu2"]
+    #[doc = "when dm_pullup_en is set high, this enables second resistor. 0 - Pull = Rpu2; 1 - Pull = Rpu1 + Rpu2"]
     #[inline(always)]
     pub fn set_dm_pullup_hisel(&mut self, val: bool) {
         self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
     }
-    #[doc = "DM pull up enable"]
+    #[doc = "Value to drive to USB PHY when override enable is set (which will override the default value or value driven from USB controller 1 - Enable Rpu on DPM"]
     #[inline(always)]
     pub const fn dm_pullup_en(&self) -> bool {
         let val = (self.0 >> 5usize) & 0x01;
         val != 0
     }
-    #[doc = "DM pull up enable"]
+    #[doc = "Value to drive to USB PHY when override enable is set (which will override the default value or value driven from USB controller 1 - Enable Rpu on DPM"]
     #[inline(always)]
     pub fn set_dm_pullup_en(&mut self, val: bool) {
         self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
     }
-    #[doc = "DM pull down enable"]
+    #[doc = "Value to drive to USB PHY when override enable is set (which will override the default value or value driven from USB controller 1 - Enable Rpd on DPM"]
     #[inline(always)]
     pub const fn dm_pulldn_en(&self) -> bool {
         let val = (self.0 >> 6usize) & 0x01;
         val != 0
     }
-    #[doc = "DM pull down enable"]
+    #[doc = "Value to drive to USB PHY when override enable is set (which will override the default value or value driven from USB controller 1 - Enable Rpd on DPM"]
     #[inline(always)]
     pub fn set_dm_pulldn_en(&mut self, val: bool) {
         self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
     }
-    #[doc = "Output enable. If TX_DIFFMODE=1, OE for DPP/DPM diff pair. 0 - DPP/DPM in Hi-Z state; 1 - DPP/DPM driving If TX_DIFFMODE=0, OE for DPP only. 0 - DPP in Hi-Z state; 1 - DPP driving"]
+    #[doc = "Value to drive to USB PHY when override enable is set (which will override the default value or value driven from USB controller TX_SEMODE=0, OE for DPP/DPM diff pair. 0 - DPP/DPM in Hi-Z state; 1 - DPP/DPM driving TX_SEMODE=1, OE for DPP only. 0 - DPP in Hi-Z state; 1 - DPP driving"]
     #[inline(always)]
     pub const fn tx_dp_oe(&self) -> bool {
         let val = (self.0 >> 8usize) & 0x01;
         val != 0
     }
-    #[doc = "Output enable. If TX_DIFFMODE=1, OE for DPP/DPM diff pair. 0 - DPP/DPM in Hi-Z state; 1 - DPP/DPM driving If TX_DIFFMODE=0, OE for DPP only. 0 - DPP in Hi-Z state; 1 - DPP driving"]
+    #[doc = "Value to drive to USB PHY when override enable is set (which will override the default value or value driven from USB controller TX_SEMODE=0, OE for DPP/DPM diff pair. 0 - DPP/DPM in Hi-Z state; 1 - DPP/DPM driving TX_SEMODE=1, OE for DPP only. 0 - DPP in Hi-Z state; 1 - DPP driving"]
     #[inline(always)]
     pub fn set_tx_dp_oe(&mut self, val: bool) {
         self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
     }
-    #[doc = "Output enable. If TX_DIFFMODE=1, Ignored. If TX_DIFFMODE=0, OE for DPM only. 0 - DPM in Hi-Z state; 1 - DPM driving"]
+    #[doc = "Value to drive to USB PHY when override enable is set (which will override the default value or value driven from USB controller TX_SEMODE=0, Ignored. TX_SEMODE=1, OE for DPM only. 0 - DPM in Hi-Z state; 1 - DPM driving"]
     #[inline(always)]
     pub const fn tx_dm_oe(&self) -> bool {
         let val = (self.0 >> 9usize) & 0x01;
         val != 0
     }
-    #[doc = "Output enable. If TX_DIFFMODE=1, Ignored. If TX_DIFFMODE=0, OE for DPM only. 0 - DPM in Hi-Z state; 1 - DPM driving"]
+    #[doc = "Value to drive to USB PHY when override enable is set (which will override the default value or value driven from USB controller TX_SEMODE=0, Ignored. TX_SEMODE=1, OE for DPM only. 0 - DPM in Hi-Z state; 1 - DPM driving"]
     #[inline(always)]
     pub fn set_tx_dm_oe(&mut self, val: bool) {
         self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
     }
-    #[doc = "Output data. If TX_DIFFMODE=1, Drives DPP/DPM diff pair. TX_DP_OE=1 to enable drive. DPP=TX_DP, DPM=~TX_DP If TX_DIFFMODE=0, Drives DPP only. TX_DP_OE=1 to enable drive. DPP=TX_DP"]
+    #[doc = "Value to drive to USB PHY when override enable is set (which will override the default value or value driven from USB controller TX_SEMODE=0, Drives DPP/DPM diff pair. TX_DP_OE=1 to enable drive. DPP=TX_DP, DPM=~TX_DP TX_SEMODE=1, Drives DPP only. TX_DP_OE=1 to enable drive. DPP=TX_DP"]
     #[inline(always)]
     pub const fn tx_dp(&self) -> bool {
         let val = (self.0 >> 10usize) & 0x01;
         val != 0
     }
-    #[doc = "Output data. If TX_DIFFMODE=1, Drives DPP/DPM diff pair. TX_DP_OE=1 to enable drive. DPP=TX_DP, DPM=~TX_DP If TX_DIFFMODE=0, Drives DPP only. TX_DP_OE=1 to enable drive. DPP=TX_DP"]
+    #[doc = "Value to drive to USB PHY when override enable is set (which will override the default value or value driven from USB controller TX_SEMODE=0, Drives DPP/DPM diff pair. TX_DP_OE=1 to enable drive. DPP=TX_DP, DPM=~TX_DP TX_SEMODE=1, Drives DPP only. TX_DP_OE=1 to enable drive. DPP=TX_DP"]
     #[inline(always)]
     pub fn set_tx_dp(&mut self, val: bool) {
         self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize);
     }
-    #[doc = "Output data. TX_DIFFMODE=1, Ignored TX_DIFFMODE=0, Drives DPM only. TX_DM_OE=1 to enable drive. DPM=TX_DM"]
+    #[doc = "Value to drive to USB PHY when override enable is set (which will override the default value or value driven from USB controller TX_SEMODE=0, Ignored TX_SEMODE=1, Drives DPM only. TX_DM_OE=1 to enable drive. DPM=TX_DM"]
     #[inline(always)]
     pub const fn tx_dm(&self) -> bool {
         let val = (self.0 >> 11usize) & 0x01;
         val != 0
     }
-    #[doc = "Output data. TX_DIFFMODE=1, Ignored TX_DIFFMODE=0, Drives DPM only. TX_DM_OE=1 to enable drive. DPM=TX_DM"]
+    #[doc = "Value to drive to USB PHY when override enable is set (which will override the default value or value driven from USB controller TX_SEMODE=0, Ignored TX_SEMODE=1, Drives DPM only. TX_DM_OE=1 to enable drive. DPM=TX_DM"]
     #[inline(always)]
     pub fn set_tx_dm(&mut self, val: bool) {
         self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
     }
-    #[doc = "RX power down override (if override enable is set). 1 = powered down."]
     #[inline(always)]
     pub const fn rx_pd(&self) -> bool {
         let val = (self.0 >> 12usize) & 0x01;
         val != 0
     }
-    #[doc = "RX power down override (if override enable is set). 1 = powered down."]
     #[inline(always)]
     pub fn set_rx_pd(&mut self, val: bool) {
         self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
     }
-    #[doc = "TX power down override (if override enable is set). 1 = powered down."]
     #[inline(always)]
     pub const fn tx_pd(&self) -> bool {
         let val = (self.0 >> 13usize) & 0x01;
         val != 0
     }
-    #[doc = "TX power down override (if override enable is set). 1 = powered down."]
     #[inline(always)]
     pub fn set_tx_pd(&mut self, val: bool) {
         self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize);
     }
-    #[doc = "TX_FSSLEW=0: Low speed slew rate TX_FSSLEW=1: Full speed slew rate"]
     #[inline(always)]
     pub const fn tx_fsslew(&self) -> bool {
         let val = (self.0 >> 14usize) & 0x01;
         val != 0
     }
-    #[doc = "TX_FSSLEW=0: Low speed slew rate TX_FSSLEW=1: Full speed slew rate"]
     #[inline(always)]
     pub fn set_tx_fsslew(&mut self, val: bool) {
         self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize);
     }
-    #[doc = "TX_DIFFMODE=0: Single ended mode TX_DIFFMODE=1: Differential drive mode (TX_DM, TX_DM_OE ignored)"]
     #[inline(always)]
     pub const fn tx_diffmode(&self) -> bool {
         let val = (self.0 >> 15usize) & 0x01;
         val != 0
     }
-    #[doc = "TX_DIFFMODE=0: Single ended mode TX_DIFFMODE=1: Differential drive mode (TX_DM, TX_DM_OE ignored)"]
     #[inline(always)]
     pub fn set_tx_diffmode(&mut self, val: bool) {
         self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize);
     }
-    #[doc = "Differential RX"]
+    #[doc = "Status bit from USB PHY RX Diff data"]
     #[inline(always)]
     pub const fn rx_dd(&self) -> bool {
         let val = (self.0 >> 16usize) & 0x01;
         val != 0
     }
-    #[doc = "Differential RX"]
+    #[doc = "Status bit from USB PHY RX Diff data"]
     #[inline(always)]
     pub fn set_rx_dd(&mut self, val: bool) {
         self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
     }
-    #[doc = "DPP pin state"]
+    #[doc = "Status bit from USB PHY DPP pin state"]
     #[inline(always)]
     pub const fn rx_dp(&self) -> bool {
         let val = (self.0 >> 17usize) & 0x01;
         val != 0
     }
-    #[doc = "DPP pin state"]
+    #[doc = "Status bit from USB PHY DPP pin state"]
     #[inline(always)]
     pub fn set_rx_dp(&mut self, val: bool) {
         self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
     }
-    #[doc = "DPM pin state"]
+    #[doc = "Status bit from USB PHY DPM pin state"]
     #[inline(always)]
     pub const fn rx_dm(&self) -> bool {
         let val = (self.0 >> 18usize) & 0x01;
         val != 0
     }
-    #[doc = "DPM pin state"]
+    #[doc = "Status bit from USB PHY DPM pin state"]
     #[inline(always)]
     pub fn set_rx_dm(&mut self, val: bool) {
         self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize);
     }
-    #[doc = "DP overcurrent"]
+    #[doc = "Status bit from USB PHY"]
     #[inline(always)]
     pub const fn dp_ovcn(&self) -> bool {
         let val = (self.0 >> 19usize) & 0x01;
         val != 0
     }
-    #[doc = "DP overcurrent"]
+    #[doc = "Status bit from USB PHY"]
     #[inline(always)]
     pub fn set_dp_ovcn(&mut self, val: bool) {
         self.0 = (self.0 & !(0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize);
     }
-    #[doc = "DM overcurrent"]
+    #[doc = "Status bit from USB PHY"]
     #[inline(always)]
     pub const fn dm_ovcn(&self) -> bool {
         let val = (self.0 >> 20usize) & 0x01;
         val != 0
     }
-    #[doc = "DM overcurrent"]
+    #[doc = "Status bit from USB PHY"]
     #[inline(always)]
     pub fn set_dm_ovcn(&mut self, val: bool) {
         self.0 = (self.0 & !(0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize);
     }
-    #[doc = "DP over voltage"]
+    #[doc = "Status bit from USB PHY"]
     #[inline(always)]
     pub const fn dp_ovv(&self) -> bool {
         let val = (self.0 >> 21usize) & 0x01;
         val != 0
     }
-    #[doc = "DP over voltage"]
+    #[doc = "Status bit from USB PHY"]
     #[inline(always)]
     pub fn set_dp_ovv(&mut self, val: bool) {
         self.0 = (self.0 & !(0x01 << 21usize)) | (((val as u32) & 0x01) << 21usize);
     }
-    #[doc = "DM over voltage"]
+    #[doc = "Status bit from USB PHY"]
     #[inline(always)]
     pub const fn dm_ovv(&self) -> bool {
         let val = (self.0 >> 22usize) & 0x01;
         val != 0
     }
-    #[doc = "DM over voltage"]
+    #[doc = "Status bit from USB PHY"]
     #[inline(always)]
     pub fn set_dm_ovv(&mut self, val: bool) {
         self.0 = (self.0 & !(0x01 << 22usize)) | (((val as u32) & 0x01) << 22usize);
@@ -1527,7 +1519,6 @@ impl Default for UsbphyDirect {
         UsbphyDirect(0)
     }
 }
-#[doc = "Override enable for each control in usbphy_direct"]
 #[repr(transparent)]
 #[derive(Copy, Clone, Eq, PartialEq)]
 pub struct UsbphyDirectOverride(pub u32);
@@ -1550,65 +1541,79 @@ impl UsbphyDirectOverride {
     pub fn set_dm_pullup_hisel_override_en(&mut self, val: bool) {
         self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
     }
+    #[doc = "Override default value or value driven from USB Controller to PHY"]
     #[inline(always)]
     pub const fn dp_pullup_en_override_en(&self) -> bool {
         let val = (self.0 >> 2usize) & 0x01;
         val != 0
     }
+    #[doc = "Override default value or value driven from USB Controller to PHY"]
     #[inline(always)]
     pub fn set_dp_pullup_en_override_en(&mut self, val: bool) {
         self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
     }
+    #[doc = "Override default value or value driven from USB Controller to PHY"]
     #[inline(always)]
     pub const fn dp_pulldn_en_override_en(&self) -> bool {
         let val = (self.0 >> 3usize) & 0x01;
         val != 0
     }
+    #[doc = "Override default value or value driven from USB Controller to PHY"]
     #[inline(always)]
     pub fn set_dp_pulldn_en_override_en(&mut self, val: bool) {
         self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
     }
+    #[doc = "Override default value or value driven from USB Controller to PHY"]
     #[inline(always)]
     pub const fn dm_pulldn_en_override_en(&self) -> bool {
         let val = (self.0 >> 4usize) & 0x01;
         val != 0
     }
+    #[doc = "Override default value or value driven from USB Controller to PHY"]
     #[inline(always)]
     pub fn set_dm_pulldn_en_override_en(&mut self, val: bool) {
         self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
     }
+    #[doc = "Override default value or value driven from USB Controller to PHY"]
     #[inline(always)]
     pub const fn tx_dp_oe_override_en(&self) -> bool {
         let val = (self.0 >> 5usize) & 0x01;
         val != 0
     }
+    #[doc = "Override default value or value driven from USB Controller to PHY"]
     #[inline(always)]
     pub fn set_tx_dp_oe_override_en(&mut self, val: bool) {
         self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
     }
+    #[doc = "Override default value or value driven from USB Controller to PHY"]
     #[inline(always)]
     pub const fn tx_dm_oe_override_en(&self) -> bool {
         let val = (self.0 >> 6usize) & 0x01;
         val != 0
     }
+    #[doc = "Override default value or value driven from USB Controller to PHY"]
     #[inline(always)]
     pub fn set_tx_dm_oe_override_en(&mut self, val: bool) {
         self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
     }
+    #[doc = "Override default value or value driven from USB Controller to PHY"]
     #[inline(always)]
     pub const fn tx_dp_override_en(&self) -> bool {
         let val = (self.0 >> 7usize) & 0x01;
         val != 0
     }
+    #[doc = "Override default value or value driven from USB Controller to PHY"]
     #[inline(always)]
     pub fn set_tx_dp_override_en(&mut self, val: bool) {
         self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
     }
+    #[doc = "Override default value or value driven from USB Controller to PHY"]
     #[inline(always)]
     pub const fn tx_dm_override_en(&self) -> bool {
         let val = (self.0 >> 8usize) & 0x01;
         val != 0
     }
+    #[doc = "Override default value or value driven from USB Controller to PHY"]
     #[inline(always)]
     pub fn set_tx_dm_override_en(&mut self, val: bool) {
         self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
@@ -1665,7 +1670,7 @@ impl Default for UsbphyDirectOverride {
         UsbphyDirectOverride(0)
     }
 }
-#[doc = "Used to adjust trim values of USB phy pull down resistors."]
+#[doc = "Note that most functions are driven directly from usb_fsls controller. This register allows more detailed control/status from the USB PHY. Useful for debug but not expected to be used in normal operation"]
 #[repr(transparent)]
 #[derive(Copy, Clone, Eq, PartialEq)]
 pub struct UsbphyTrim(pub u32);
diff --git a/src/usb_dpram.rs b/src/rp2040/usb_dpram.rs
similarity index 100%
rename from src/usb_dpram.rs
rename to src/rp2040/usb_dpram.rs
diff --git a/src/usb_dpram/regs.rs b/src/rp2040/usb_dpram/regs.rs
similarity index 100%
rename from src/usb_dpram/regs.rs
rename to src/rp2040/usb_dpram/regs.rs
diff --git a/src/usb_dpram/vals.rs b/src/rp2040/usb_dpram/vals.rs
similarity index 100%
rename from src/usb_dpram/vals.rs
rename to src/rp2040/usb_dpram/vals.rs
diff --git a/src/vreg_and_chip_reset.rs b/src/rp2040/vreg_and_chip_reset.rs
similarity index 100%
rename from src/vreg_and_chip_reset.rs
rename to src/rp2040/vreg_and_chip_reset.rs
diff --git a/src/vreg_and_chip_reset/regs.rs b/src/rp2040/vreg_and_chip_reset/regs.rs
similarity index 100%
rename from src/vreg_and_chip_reset/regs.rs
rename to src/rp2040/vreg_and_chip_reset/regs.rs
diff --git a/src/watchdog.rs b/src/rp2040/watchdog.rs
similarity index 100%
rename from src/watchdog.rs
rename to src/rp2040/watchdog.rs
diff --git a/src/watchdog/regs.rs b/src/rp2040/watchdog/regs.rs
similarity index 100%
rename from src/watchdog/regs.rs
rename to src/rp2040/watchdog/regs.rs
diff --git a/src/xip_ctrl.rs b/src/rp2040/xip_ctrl.rs
similarity index 76%
rename from src/xip_ctrl.rs
rename to src/rp2040/xip_ctrl.rs
index 44af88a5..a1841a4e 100644
--- a/src/xip_ctrl.rs
+++ b/src/rp2040/xip_ctrl.rs
@@ -29,12 +29,12 @@ impl XipCtrl {
     pub const fn stat(self) -> crate::common::Reg<regs::Stat, crate::common::RW> {
         unsafe { crate::common::Reg::from_ptr(self.ptr.add(8usize) as _) }
     }
-    #[doc = "Cache Hit counter A 32 bit saturating counter that increments upon each cache hit, i.e. when an XIP access is serviced directly from cached data. Write any value to clear."]
+    #[doc = "Cache Hit counter"]
     #[inline(always)]
     pub const fn ctr_hit(self) -> crate::common::Reg<u32, crate::common::RW> {
         unsafe { crate::common::Reg::from_ptr(self.ptr.add(12usize) as _) }
     }
-    #[doc = "Cache Access counter A 32 bit saturating counter that increments upon each XIP access, whether the cache is hit or not. This includes noncacheable accesses. Write any value to clear."]
+    #[doc = "Cache Access counter"]
     #[inline(always)]
     pub const fn ctr_acc(self) -> crate::common::Reg<u32, crate::common::RW> {
         unsafe { crate::common::Reg::from_ptr(self.ptr.add(16usize) as _) }
@@ -49,9 +49,9 @@ impl XipCtrl {
     pub const fn stream_ctr(self) -> crate::common::Reg<regs::StreamCtr, crate::common::RW> {
         unsafe { crate::common::Reg::from_ptr(self.ptr.add(24usize) as _) }
     }
-    #[doc = "FIFO stream data Streamed data is buffered here, for retrieval by the system DMA. This FIFO can also be accessed via the XIP_AUX slave, to avoid exposing the DMA to bus stalls caused by other XIP traffic."]
+    #[doc = "FIFO stream data"]
     #[inline(always)]
-    pub const fn stream_fifo(self) -> crate::common::Reg<u32, crate::common::R> {
+    pub const fn stream_fifo(self) -> crate::common::Reg<u32, crate::common::RW> {
         unsafe { crate::common::Reg::from_ptr(self.ptr.add(28usize) as _) }
     }
 }
diff --git a/src/xip_ctrl/regs.rs b/src/rp2040/xip_ctrl/regs.rs
similarity index 100%
rename from src/xip_ctrl/regs.rs
rename to src/rp2040/xip_ctrl/regs.rs
diff --git a/src/xosc.rs b/src/rp2040/xosc.rs
similarity index 81%
rename from src/xosc.rs
rename to src/rp2040/xosc.rs
index 1bd9266b..3f7af636 100644
--- a/src/xosc.rs
+++ b/src/rp2040/xosc.rs
@@ -24,9 +24,9 @@ impl Xosc {
     pub const fn status(self) -> crate::common::Reg<regs::Status, crate::common::RW> {
         unsafe { crate::common::Reg::from_ptr(self.ptr.add(4usize) as _) }
     }
-    #[doc = "Crystal Oscillator pause control This is used to save power by pausing the XOSC On power-up this field is initialised to WAKE An invalid write will also select WAKE WARNING: stop the PLLs before selecting dormant mode WARNING: setup the irq before selecting dormant mode"]
+    #[doc = "Crystal Oscillator pause control"]
     #[inline(always)]
-    pub const fn dormant(self) -> crate::common::Reg<u32, crate::common::RW> {
+    pub const fn dormant(self) -> crate::common::Reg<regs::Dormant, crate::common::RW> {
         unsafe { crate::common::Reg::from_ptr(self.ptr.add(8usize) as _) }
     }
     #[doc = "Controls the startup delay"]
diff --git a/src/xosc/regs.rs b/src/rp2040/xosc/regs.rs
similarity index 71%
rename from src/xosc/regs.rs
rename to src/rp2040/xosc/regs.rs
index 56eba56c..b3dc77af 100644
--- a/src/xosc/regs.rs
+++ b/src/rp2040/xosc/regs.rs
@@ -24,24 +24,24 @@ impl Default for Count {
 #[derive(Copy, Clone, Eq, PartialEq)]
 pub struct Ctrl(pub u32);
 impl Ctrl {
-    #[doc = "Frequency range. This resets to 0xAA0 and cannot be changed."]
+    #[doc = "Frequency range. An invalid setting will retain the previous value. The actual value being used can be read from STATUS_FREQ_RANGE. This resets to 0xAA0 and cannot be changed."]
     #[inline(always)]
     pub const fn freq_range(&self) -> super::vals::CtrlFreqRange {
         let val = (self.0 >> 0usize) & 0x0fff;
         super::vals::CtrlFreqRange::from_bits(val as u16)
     }
-    #[doc = "Frequency range. This resets to 0xAA0 and cannot be changed."]
+    #[doc = "Frequency range. An invalid setting will retain the previous value. The actual value being used can be read from STATUS_FREQ_RANGE. This resets to 0xAA0 and cannot be changed."]
     #[inline(always)]
     pub fn set_freq_range(&mut self, val: super::vals::CtrlFreqRange) {
         self.0 = (self.0 & !(0x0fff << 0usize)) | (((val.to_bits() as u32) & 0x0fff) << 0usize);
     }
-    #[doc = "On power-up this field is initialised to DISABLE and the chip runs from the ROSC. If the chip has subsequently been programmed to run from the XOSC then setting this field to DISABLE may lock-up the chip. If this is a concern then run the clk_ref from the ROSC and enable the clk_sys RESUS feature. The 12-bit code is intended to give some protection against accidental writes. An invalid setting will enable the oscillator."]
+    #[doc = "On power-up this field is initialised to DISABLE and the chip runs from the ROSC. If the chip has subsequently been programmed to run from the XOSC then DISABLE may lock-up the chip. If this is a concern then run the clk_ref from the ROSC and enable the clk_sys RESUS feature. The 12-bit code is intended to give some protection against accidental writes. An invalid setting will enable the oscillator."]
     #[inline(always)]
     pub const fn enable(&self) -> super::vals::Enable {
         let val = (self.0 >> 12usize) & 0x0fff;
         super::vals::Enable::from_bits(val as u16)
     }
-    #[doc = "On power-up this field is initialised to DISABLE and the chip runs from the ROSC. If the chip has subsequently been programmed to run from the XOSC then setting this field to DISABLE may lock-up the chip. If this is a concern then run the clk_ref from the ROSC and enable the clk_sys RESUS feature. The 12-bit code is intended to give some protection against accidental writes. An invalid setting will enable the oscillator."]
+    #[doc = "On power-up this field is initialised to DISABLE and the chip runs from the ROSC. If the chip has subsequently been programmed to run from the XOSC then DISABLE may lock-up the chip. If this is a concern then run the clk_ref from the ROSC and enable the clk_sys RESUS feature. The 12-bit code is intended to give some protection against accidental writes. An invalid setting will enable the oscillator."]
     #[inline(always)]
     pub fn set_enable(&mut self, val: super::vals::Enable) {
         self.0 = (self.0 & !(0x0fff << 12usize)) | (((val.to_bits() as u32) & 0x0fff) << 12usize);
@@ -53,6 +53,30 @@ impl Default for Ctrl {
         Ctrl(0)
     }
 }
+#[doc = "Crystal Oscillator pause control"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Dormant(pub u32);
+impl Dormant {
+    #[doc = "This is used to save power by pausing the XOSC On power-up this field is initialised to WAKE An invalid write will also select WAKE Warning: stop the PLLs before selecting dormant mode Warning: setup the irq before selecting dormant mode"]
+    #[inline(always)]
+    pub const fn dormant(&self) -> super::vals::Dormant {
+        let val = (self.0 >> 0usize) & 0xffff_ffff;
+        super::vals::Dormant::from_bits(val as u32)
+    }
+    #[doc = "This is used to save power by pausing the XOSC On power-up this field is initialised to WAKE An invalid write will also select WAKE Warning: stop the PLLs before selecting dormant mode Warning: setup the irq before selecting dormant mode"]
+    #[inline(always)]
+    pub fn set_dormant(&mut self, val: super::vals::Dormant) {
+        self.0 = (self.0 & !(0xffff_ffff << 0usize))
+            | (((val.to_bits() as u32) & 0xffff_ffff) << 0usize);
+    }
+}
+impl Default for Dormant {
+    #[inline(always)]
+    fn default() -> Dormant {
+        Dormant(0)
+    }
+}
 #[doc = "Controls the startup delay"]
 #[repr(transparent)]
 #[derive(Copy, Clone, Eq, PartialEq)]
diff --git a/src/xosc/vals.rs b/src/rp2040/xosc/vals.rs
similarity index 77%
rename from src/xosc/vals.rs
rename to src/rp2040/xosc/vals.rs
index e8400c32..237095e3 100644
--- a/src/xosc/vals.rs
+++ b/src/rp2040/xosc/vals.rs
@@ -29,6 +29,33 @@ impl From<CtrlFreqRange> for u16 {
 }
 #[repr(transparent)]
 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub struct Dormant(pub u32);
+impl Dormant {
+    pub const DORMANT: Self = Self(0x636f_6d61);
+    pub const WAKE: Self = Self(0x7761_6b65);
+}
+impl Dormant {
+    pub const fn from_bits(val: u32) -> Dormant {
+        Self(val & 0xffff_ffff)
+    }
+    pub const fn to_bits(self) -> u32 {
+        self.0
+    }
+}
+impl From<u32> for Dormant {
+    #[inline(always)]
+    fn from(val: u32) -> Dormant {
+        Dormant::from_bits(val)
+    }
+}
+impl From<Dormant> for u32 {
+    #[inline(always)]
+    fn from(val: Dormant) -> u32 {
+        Dormant::to_bits(val)
+    }
+}
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
 pub struct Enable(pub u16);
 impl Enable {
     pub const DISABLE: Self = Self(0x0d1e);
diff --git a/src/rp2350/_vectors.rs b/src/rp2350/_vectors.rs
new file mode 100644
index 00000000..9b5360ff
--- /dev/null
+++ b/src/rp2350/_vectors.rs
@@ -0,0 +1,201 @@
+extern "C" {
+    fn TIMER0_IRQ_0();
+    fn TIMER0_IRQ_1();
+    fn TIMER0_IRQ_2();
+    fn TIMER0_IRQ_3();
+    fn TIMER1_IRQ_0();
+    fn TIMER1_IRQ_1();
+    fn TIMER1_IRQ_2();
+    fn TIMER1_IRQ_3();
+    fn PWM_IRQ_WRAP_0();
+    fn PWM_IRQ_WRAP_1();
+    fn DMA_IRQ_0();
+    fn DMA_IRQ_1();
+    fn DMA_IRQ_2();
+    fn DMA_IRQ_3();
+    fn USBCTRL_IRQ();
+    fn PIO0_IRQ_0();
+    fn PIO0_IRQ_1();
+    fn PIO1_IRQ_0();
+    fn PIO1_IRQ_1();
+    fn PIO2_IRQ_0();
+    fn PIO2_IRQ_1();
+    fn IO_IRQ_BANK0();
+    fn IO_IRQ_BANK0_NS();
+    fn IO_IRQ_QSPI();
+    fn IO_IRQ_QSPI_NS();
+    fn SIO_IRQ_FIFO();
+    fn SIO_IRQ_BELL();
+    fn SIO_IRQ_FIFO_NS();
+    fn SIO_IRQ_BELL_NS();
+    fn SIO_IRQ_MTIMECMP();
+    fn CLOCKS_IRQ();
+    fn SPI0_IRQ();
+    fn SPI1_IRQ();
+    fn UART0_IRQ();
+    fn UART1_IRQ();
+    fn ADC_IRQ_FIFO();
+    fn I2C0_IRQ();
+    fn I2C1_IRQ();
+    fn OTP_IRQ();
+    fn TRNG_IRQ();
+    fn PLL_SYS_IRQ();
+    fn PLL_USB_IRQ();
+    fn POWMAN_IRQ_POW();
+    fn POWMAN_IRQ_TIMER();
+    fn SWI_IRQ_0();
+    fn SWI_IRQ_1();
+    fn SWI_IRQ_2();
+    fn SWI_IRQ_3();
+    fn SWI_IRQ_4();
+    fn SWI_IRQ_5();
+}
+pub union Vector {
+    _handler: unsafe extern "C" fn(),
+    _reserved: u32,
+}
+#[link_section = ".vector_table.interrupts"]
+#[no_mangle]
+pub static __INTERRUPTS: [Vector; 53] = [
+    Vector {
+        _handler: TIMER0_IRQ_0,
+    },
+    Vector {
+        _handler: TIMER0_IRQ_1,
+    },
+    Vector {
+        _handler: TIMER0_IRQ_2,
+    },
+    Vector {
+        _handler: TIMER0_IRQ_3,
+    },
+    Vector {
+        _handler: TIMER1_IRQ_0,
+    },
+    Vector {
+        _handler: TIMER1_IRQ_1,
+    },
+    Vector {
+        _handler: TIMER1_IRQ_2,
+    },
+    Vector {
+        _handler: TIMER1_IRQ_3,
+    },
+    Vector {
+        _handler: PWM_IRQ_WRAP_0,
+    },
+    Vector {
+        _handler: PWM_IRQ_WRAP_1,
+    },
+    Vector {
+        _handler: DMA_IRQ_0,
+    },
+    Vector {
+        _handler: DMA_IRQ_1,
+    },
+    Vector {
+        _handler: DMA_IRQ_2,
+    },
+    Vector {
+        _handler: DMA_IRQ_3,
+    },
+    Vector {
+        _handler: USBCTRL_IRQ,
+    },
+    Vector {
+        _handler: PIO0_IRQ_0,
+    },
+    Vector {
+        _handler: PIO0_IRQ_1,
+    },
+    Vector {
+        _handler: PIO1_IRQ_0,
+    },
+    Vector {
+        _handler: PIO1_IRQ_1,
+    },
+    Vector {
+        _handler: PIO2_IRQ_0,
+    },
+    Vector {
+        _handler: PIO2_IRQ_1,
+    },
+    Vector {
+        _handler: IO_IRQ_BANK0,
+    },
+    Vector {
+        _handler: IO_IRQ_BANK0_NS,
+    },
+    Vector {
+        _handler: IO_IRQ_QSPI,
+    },
+    Vector {
+        _handler: IO_IRQ_QSPI_NS,
+    },
+    Vector {
+        _handler: SIO_IRQ_FIFO,
+    },
+    Vector {
+        _handler: SIO_IRQ_BELL,
+    },
+    Vector {
+        _handler: SIO_IRQ_FIFO_NS,
+    },
+    Vector {
+        _handler: SIO_IRQ_BELL_NS,
+    },
+    Vector {
+        _handler: SIO_IRQ_MTIMECMP,
+    },
+    Vector {
+        _handler: CLOCKS_IRQ,
+    },
+    Vector { _handler: SPI0_IRQ },
+    Vector { _handler: SPI1_IRQ },
+    Vector {
+        _handler: UART0_IRQ,
+    },
+    Vector {
+        _handler: UART1_IRQ,
+    },
+    Vector {
+        _handler: ADC_IRQ_FIFO,
+    },
+    Vector { _handler: I2C0_IRQ },
+    Vector { _handler: I2C1_IRQ },
+    Vector { _handler: OTP_IRQ },
+    Vector { _handler: TRNG_IRQ },
+    Vector { _reserved: 0 },
+    Vector { _reserved: 0 },
+    Vector {
+        _handler: PLL_SYS_IRQ,
+    },
+    Vector {
+        _handler: PLL_USB_IRQ,
+    },
+    Vector {
+        _handler: POWMAN_IRQ_POW,
+    },
+    Vector {
+        _handler: POWMAN_IRQ_TIMER,
+    },
+    Vector { _reserved: 0 },
+    Vector {
+        _handler: SWI_IRQ_0,
+    },
+    Vector {
+        _handler: SWI_IRQ_1,
+    },
+    Vector {
+        _handler: SWI_IRQ_2,
+    },
+    Vector {
+        _handler: SWI_IRQ_3,
+    },
+    Vector {
+        _handler: SWI_IRQ_4,
+    },
+    Vector {
+        _handler: SWI_IRQ_5,
+    },
+];
diff --git a/src/rp2350/accessctrl.rs b/src/rp2350/accessctrl.rs
new file mode 100644
index 00000000..1a1861b1
--- /dev/null
+++ b/src/rp2350/accessctrl.rs
@@ -0,0 +1,317 @@
+#[doc = "Hardware access control registers"]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Accessctrl {
+    ptr: *mut u8,
+}
+unsafe impl Send for Accessctrl {}
+unsafe impl Sync for Accessctrl {}
+impl Accessctrl {
+    #[inline(always)]
+    pub const unsafe fn from_ptr(ptr: *mut ()) -> Self {
+        Self { ptr: ptr as _ }
+    }
+    #[inline(always)]
+    pub const fn as_ptr(&self) -> *mut () {
+        self.ptr as _
+    }
+    #[doc = "Once a LOCK bit is written to 1, ACCESSCTRL silently ignores writes from that master. LOCK is writable only by a Secure, Privileged processor or debugger. LOCK bits are only writable when their value is zero. Once set, they can never be cleared, except by a full reset of ACCESSCTRL Setting the LOCK bit does not affect whether an access raises a bus error. Unprivileged writes, or writes from the DMA, will continue to raise bus errors. All other accesses will continue not to."]
+    #[inline(always)]
+    pub const fn lock(self) -> crate::common::Reg<regs::Lock, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(0usize) as _) }
+    }
+    #[doc = "Force core 1's bus accesses to always be Non-secure, no matter the core's internal state. Useful for schemes where one core is designated as the Non-secure core, since some peripherals may filter individual registers internally based on security state but not on master ID."]
+    #[inline(always)]
+    pub const fn force_core_ns(self) -> crate::common::Reg<regs::ForceCoreNs, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(4usize) as _) }
+    }
+    #[doc = "Write 1 to reset all ACCESSCTRL configuration, except for the LOCK and FORCE_CORE_NS registers. This bit is used in the RP2350 bootrom to quickly restore ACCESSCTRL to a known state during the boot path. Note that, like all registers in ACCESSCTRL, this register is not writable when the writer's corresponding LOCK bit is set, therefore a master which has been locked out of ACCESSCTRL can not use the CFGRESET register to disturb its contents."]
+    #[inline(always)]
+    pub const fn cfgreset(self) -> crate::common::Reg<regs::Cfgreset, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(8usize) as _) }
+    }
+    #[doc = "Control whether GPIO0...31 are accessible to Non-secure code. Writable only by a Secure, Privileged processor or debugger. 0 -> Secure access only 1 -> Secure + Non-secure access"]
+    #[inline(always)]
+    pub const fn gpio_nsmask0(self) -> crate::common::Reg<u32, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(12usize) as _) }
+    }
+    #[doc = "Control whether GPIO32..47 are accessible to Non-secure code, and whether QSPI and USB bitbang are accessible through the Non-secure SIO. Writable only by a Secure, Privileged processor or debugger."]
+    #[inline(always)]
+    pub const fn gpio_nsmask1(self) -> crate::common::Reg<regs::GpioNsmask1, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(16usize) as _) }
+    }
+    #[doc = "Control whether debugger, DMA, core 0 and core 1 can access ROM, and at what security/privilege levels they can do so. Defaults to fully open access. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."]
+    #[inline(always)]
+    pub const fn rom(self) -> crate::common::Reg<regs::Rom, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(20usize) as _) }
+    }
+    #[doc = "Control whether debugger, DMA, core 0 and core 1 can access XIP_MAIN, and at what security/privilege levels they can do so. Defaults to fully open access. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."]
+    #[inline(always)]
+    pub const fn xip_main(self) -> crate::common::Reg<regs::XipMain, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(24usize) as _) }
+    }
+    #[doc = "Control whether debugger, DMA, core 0 and core 1 can access SRAM0, and at what security/privilege levels they can do so. Defaults to fully open access. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."]
+    #[inline(always)]
+    pub const fn sram0(self) -> crate::common::Reg<regs::Sram0, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(28usize) as _) }
+    }
+    #[doc = "Control whether debugger, DMA, core 0 and core 1 can access SRAM1, and at what security/privilege levels they can do so. Defaults to fully open access. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."]
+    #[inline(always)]
+    pub const fn sram1(self) -> crate::common::Reg<regs::Sram1, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(32usize) as _) }
+    }
+    #[doc = "Control whether debugger, DMA, core 0 and core 1 can access SRAM2, and at what security/privilege levels they can do so. Defaults to fully open access. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."]
+    #[inline(always)]
+    pub const fn sram2(self) -> crate::common::Reg<regs::Sram2, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(36usize) as _) }
+    }
+    #[doc = "Control whether debugger, DMA, core 0 and core 1 can access SRAM3, and at what security/privilege levels they can do so. Defaults to fully open access. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."]
+    #[inline(always)]
+    pub const fn sram3(self) -> crate::common::Reg<regs::Sram3, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(40usize) as _) }
+    }
+    #[doc = "Control whether debugger, DMA, core 0 and core 1 can access SRAM4, and at what security/privilege levels they can do so. Defaults to fully open access. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."]
+    #[inline(always)]
+    pub const fn sram4(self) -> crate::common::Reg<regs::Sram4, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(44usize) as _) }
+    }
+    #[doc = "Control whether debugger, DMA, core 0 and core 1 can access SRAM5, and at what security/privilege levels they can do so. Defaults to fully open access. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."]
+    #[inline(always)]
+    pub const fn sram5(self) -> crate::common::Reg<regs::Sram5, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(48usize) as _) }
+    }
+    #[doc = "Control whether debugger, DMA, core 0 and core 1 can access SRAM6, and at what security/privilege levels they can do so. Defaults to fully open access. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."]
+    #[inline(always)]
+    pub const fn sram6(self) -> crate::common::Reg<regs::Sram6, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(52usize) as _) }
+    }
+    #[doc = "Control whether debugger, DMA, core 0 and core 1 can access SRAM7, and at what security/privilege levels they can do so. Defaults to fully open access. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."]
+    #[inline(always)]
+    pub const fn sram7(self) -> crate::common::Reg<regs::Sram7, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(56usize) as _) }
+    }
+    #[doc = "Control whether debugger, DMA, core 0 and core 1 can access SRAM8, and at what security/privilege levels they can do so. Defaults to fully open access. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."]
+    #[inline(always)]
+    pub const fn sram8(self) -> crate::common::Reg<regs::Sram8, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(60usize) as _) }
+    }
+    #[doc = "Control whether debugger, DMA, core 0 and core 1 can access SRAM9, and at what security/privilege levels they can do so. Defaults to fully open access. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."]
+    #[inline(always)]
+    pub const fn sram9(self) -> crate::common::Reg<regs::Sram9, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(64usize) as _) }
+    }
+    #[doc = "Control whether debugger, DMA, core 0 and core 1 can access DMA, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."]
+    #[inline(always)]
+    pub const fn dma(self) -> crate::common::Reg<regs::Dma, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(68usize) as _) }
+    }
+    #[doc = "Control whether debugger, DMA, core 0 and core 1 can access USBCTRL, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."]
+    #[inline(always)]
+    pub const fn usbctrl(self) -> crate::common::Reg<regs::Usbctrl, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(72usize) as _) }
+    }
+    #[doc = "Control whether debugger, DMA, core 0 and core 1 can access PIO0, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."]
+    #[inline(always)]
+    pub const fn pio0(self) -> crate::common::Reg<regs::Pio0, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(76usize) as _) }
+    }
+    #[doc = "Control whether debugger, DMA, core 0 and core 1 can access PIO1, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."]
+    #[inline(always)]
+    pub const fn pio1(self) -> crate::common::Reg<regs::Pio1, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(80usize) as _) }
+    }
+    #[doc = "Control whether debugger, DMA, core 0 and core 1 can access PIO2, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."]
+    #[inline(always)]
+    pub const fn pio2(self) -> crate::common::Reg<regs::Pio2, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(84usize) as _) }
+    }
+    #[doc = "Control whether debugger, DMA, core 0 and core 1 can access CORESIGHT_TRACE, and at what security/privilege levels they can do so. Defaults to Secure, Privileged processor or debug access only. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."]
+    #[inline(always)]
+    pub const fn coresight_trace(
+        self,
+    ) -> crate::common::Reg<regs::CoresightTrace, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(88usize) as _) }
+    }
+    #[doc = "Control whether debugger, DMA, core 0 and core 1 can access CORESIGHT_PERIPH, and at what security/privilege levels they can do so. Defaults to Secure, Privileged processor or debug access only. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."]
+    #[inline(always)]
+    pub const fn coresight_periph(
+        self,
+    ) -> crate::common::Reg<regs::CoresightPeriph, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(92usize) as _) }
+    }
+    #[doc = "Control whether debugger, DMA, core 0 and core 1 can access SYSINFO, and at what security/privilege levels they can do so. Defaults to fully open access. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."]
+    #[inline(always)]
+    pub const fn sysinfo(self) -> crate::common::Reg<regs::Sysinfo, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(96usize) as _) }
+    }
+    #[doc = "Control whether debugger, DMA, core 0 and core 1 can access RESETS, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."]
+    #[inline(always)]
+    pub const fn resets(self) -> crate::common::Reg<regs::Resets, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(100usize) as _) }
+    }
+    #[doc = "Control whether debugger, DMA, core 0 and core 1 can access IO_BANK0, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."]
+    #[inline(always)]
+    pub const fn io_bank0(self) -> crate::common::Reg<regs::IoBank0, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(104usize) as _) }
+    }
+    #[doc = "Control whether debugger, DMA, core 0 and core 1 can access IO_BANK1, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."]
+    #[inline(always)]
+    pub const fn io_bank1(self) -> crate::common::Reg<regs::IoBank1, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(108usize) as _) }
+    }
+    #[doc = "Control whether debugger, DMA, core 0 and core 1 can access PADS_BANK0, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."]
+    #[inline(always)]
+    pub const fn pads_bank0(self) -> crate::common::Reg<regs::PadsBank0, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(112usize) as _) }
+    }
+    #[doc = "Control whether debugger, DMA, core 0 and core 1 can access PADS_QSPI, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."]
+    #[inline(always)]
+    pub const fn pads_qspi(self) -> crate::common::Reg<regs::PadsQspi, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(116usize) as _) }
+    }
+    #[doc = "Control whether debugger, DMA, core 0 and core 1 can access BUSCTRL, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."]
+    #[inline(always)]
+    pub const fn busctrl(self) -> crate::common::Reg<regs::Busctrl, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(120usize) as _) }
+    }
+    #[doc = "Control whether debugger, DMA, core 0 and core 1 can access ADC0, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."]
+    #[inline(always)]
+    pub const fn adc0(self) -> crate::common::Reg<regs::Adc0, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(124usize) as _) }
+    }
+    #[doc = "Control whether debugger, DMA, core 0 and core 1 can access HSTX, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."]
+    #[inline(always)]
+    pub const fn hstx(self) -> crate::common::Reg<regs::Hstx, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(128usize) as _) }
+    }
+    #[doc = "Control whether debugger, DMA, core 0 and core 1 can access I2C0, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."]
+    #[inline(always)]
+    pub const fn i2c0(self) -> crate::common::Reg<regs::I2c0, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(132usize) as _) }
+    }
+    #[doc = "Control whether debugger, DMA, core 0 and core 1 can access I2C1, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."]
+    #[inline(always)]
+    pub const fn i2c1(self) -> crate::common::Reg<regs::I2c1, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(136usize) as _) }
+    }
+    #[doc = "Control whether debugger, DMA, core 0 and core 1 can access PWM, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."]
+    #[inline(always)]
+    pub const fn pwm(self) -> crate::common::Reg<regs::Pwm, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(140usize) as _) }
+    }
+    #[doc = "Control whether debugger, DMA, core 0 and core 1 can access SPI0, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."]
+    #[inline(always)]
+    pub const fn spi0(self) -> crate::common::Reg<regs::Spi0, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(144usize) as _) }
+    }
+    #[doc = "Control whether debugger, DMA, core 0 and core 1 can access SPI1, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."]
+    #[inline(always)]
+    pub const fn spi1(self) -> crate::common::Reg<regs::Spi1, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(148usize) as _) }
+    }
+    #[doc = "Control whether debugger, DMA, core 0 and core 1 can access TIMER0, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."]
+    #[inline(always)]
+    pub const fn timer0(self) -> crate::common::Reg<regs::Timer0, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(152usize) as _) }
+    }
+    #[doc = "Control whether debugger, DMA, core 0 and core 1 can access TIMER1, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."]
+    #[inline(always)]
+    pub const fn timer1(self) -> crate::common::Reg<regs::Timer1, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(156usize) as _) }
+    }
+    #[doc = "Control whether debugger, DMA, core 0 and core 1 can access UART0, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."]
+    #[inline(always)]
+    pub const fn uart0(self) -> crate::common::Reg<regs::Uart0, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(160usize) as _) }
+    }
+    #[doc = "Control whether debugger, DMA, core 0 and core 1 can access UART1, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."]
+    #[inline(always)]
+    pub const fn uart1(self) -> crate::common::Reg<regs::Uart1, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(164usize) as _) }
+    }
+    #[doc = "Control whether debugger, DMA, core 0 and core 1 can access OTP, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."]
+    #[inline(always)]
+    pub const fn otp(self) -> crate::common::Reg<regs::Otp, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(168usize) as _) }
+    }
+    #[doc = "Control whether debugger, DMA, core 0 and core 1 can access TBMAN, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."]
+    #[inline(always)]
+    pub const fn tbman(self) -> crate::common::Reg<regs::Tbman, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(172usize) as _) }
+    }
+    #[doc = "Control whether debugger, DMA, core 0 and core 1 can access POWMAN, and at what security/privilege levels they can do so. Defaults to Secure, Privileged processor or debug access only. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."]
+    #[inline(always)]
+    pub const fn powman(self) -> crate::common::Reg<regs::Powman, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(176usize) as _) }
+    }
+    #[doc = "Control whether debugger, DMA, core 0 and core 1 can access TRNG, and at what security/privilege levels they can do so. Defaults to Secure, Privileged processor or debug access only. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."]
+    #[inline(always)]
+    pub const fn trng(self) -> crate::common::Reg<regs::Trng, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(180usize) as _) }
+    }
+    #[doc = "Control whether debugger, DMA, core 0 and core 1 can access SHA256, and at what security/privilege levels they can do so. Defaults to Secure, Privileged access only. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."]
+    #[inline(always)]
+    pub const fn sha256(self) -> crate::common::Reg<regs::Sha256, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(184usize) as _) }
+    }
+    #[doc = "Control whether debugger, DMA, core 0 and core 1 can access SYSCFG, and at what security/privilege levels they can do so. Defaults to Secure, Privileged processor or debug access only. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."]
+    #[inline(always)]
+    pub const fn syscfg(self) -> crate::common::Reg<regs::Syscfg, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(188usize) as _) }
+    }
+    #[doc = "Control whether debugger, DMA, core 0 and core 1 can access CLOCKS, and at what security/privilege levels they can do so. Defaults to Secure, Privileged processor or debug access only. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."]
+    #[inline(always)]
+    pub const fn clocks(self) -> crate::common::Reg<regs::Clocks, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(192usize) as _) }
+    }
+    #[doc = "Control whether debugger, DMA, core 0 and core 1 can access XOSC, and at what security/privilege levels they can do so. Defaults to Secure, Privileged processor or debug access only. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."]
+    #[inline(always)]
+    pub const fn xosc(self) -> crate::common::Reg<regs::Xosc, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(196usize) as _) }
+    }
+    #[doc = "Control whether debugger, DMA, core 0 and core 1 can access ROSC, and at what security/privilege levels they can do so. Defaults to Secure, Privileged processor or debug access only. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."]
+    #[inline(always)]
+    pub const fn rosc(self) -> crate::common::Reg<regs::Rosc, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(200usize) as _) }
+    }
+    #[doc = "Control whether debugger, DMA, core 0 and core 1 can access PLL_SYS, and at what security/privilege levels they can do so. Defaults to Secure, Privileged processor or debug access only. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."]
+    #[inline(always)]
+    pub const fn pll_sys(self) -> crate::common::Reg<regs::PllSys, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(204usize) as _) }
+    }
+    #[doc = "Control whether debugger, DMA, core 0 and core 1 can access PLL_USB, and at what security/privilege levels they can do so. Defaults to Secure, Privileged processor or debug access only. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."]
+    #[inline(always)]
+    pub const fn pll_usb(self) -> crate::common::Reg<regs::PllUsb, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(208usize) as _) }
+    }
+    #[doc = "Control whether debugger, DMA, core 0 and core 1 can access TICKS, and at what security/privilege levels they can do so. Defaults to Secure, Privileged processor or debug access only. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."]
+    #[inline(always)]
+    pub const fn ticks(self) -> crate::common::Reg<regs::Ticks, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(212usize) as _) }
+    }
+    #[doc = "Control whether debugger, DMA, core 0 and core 1 can access WATCHDOG, and at what security/privilege levels they can do so. Defaults to Secure, Privileged processor or debug access only. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."]
+    #[inline(always)]
+    pub const fn watchdog(self) -> crate::common::Reg<regs::Watchdog, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(216usize) as _) }
+    }
+    #[doc = "Control whether debugger, DMA, core 0 and core 1 can access RSM, and at what security/privilege levels they can do so. Defaults to Secure, Privileged processor or debug access only. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."]
+    #[inline(always)]
+    pub const fn rsm(self) -> crate::common::Reg<regs::Rsm, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(220usize) as _) }
+    }
+    #[doc = "Control whether debugger, DMA, core 0 and core 1 can access XIP_CTRL, and at what security/privilege levels they can do so. Defaults to Secure, Privileged processor or debug access only. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."]
+    #[inline(always)]
+    pub const fn xip_ctrl(self) -> crate::common::Reg<regs::XipCtrl, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(224usize) as _) }
+    }
+    #[doc = "Control whether debugger, DMA, core 0 and core 1 can access XIP_QMI, and at what security/privilege levels they can do so. Defaults to Secure, Privileged processor or debug access only. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."]
+    #[inline(always)]
+    pub const fn xip_qmi(self) -> crate::common::Reg<regs::XipQmi, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(228usize) as _) }
+    }
+    #[doc = "Control whether debugger, DMA, core 0 and core 1 can access XIP_AUX, and at what security/privilege levels they can do so. Defaults to Secure, Privileged access only. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."]
+    #[inline(always)]
+    pub const fn xip_aux(self) -> crate::common::Reg<regs::XipAux, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(232usize) as _) }
+    }
+}
+pub mod regs;
diff --git a/src/rp2350/accessctrl/regs.rs b/src/rp2350/accessctrl/regs.rs
new file mode 100644
index 00000000..7ba666b4
--- /dev/null
+++ b/src/rp2350/accessctrl/regs.rs
@@ -0,0 +1,5556 @@
+#[doc = "Control whether debugger, DMA, core 0 and core 1 can access ADC0, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Adc0(pub u32);
+impl Adc0 {
+    #[doc = "If 1, and NSP is also set, ADC0 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."]
+    #[inline(always)]
+    pub const fn nsu(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, and NSP is also set, ADC0 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."]
+    #[inline(always)]
+    pub fn set_nsu(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[doc = "If 1, ADC0 can be accessed from a Non-secure, Privileged context."]
+    #[inline(always)]
+    pub const fn nsp(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, ADC0 can be accessed from a Non-secure, Privileged context."]
+    #[inline(always)]
+    pub fn set_nsp(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+    #[doc = "If 1, and SP is also set, ADC0 can be accessed from a Secure, Unprivileged context."]
+    #[inline(always)]
+    pub const fn su(&self) -> bool {
+        let val = (self.0 >> 2usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, and SP is also set, ADC0 can be accessed from a Secure, Unprivileged context."]
+    #[inline(always)]
+    pub fn set_su(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+    }
+    #[doc = "If 1, ADC0 can be accessed from a Secure, Privileged context."]
+    #[inline(always)]
+    pub const fn sp(&self) -> bool {
+        let val = (self.0 >> 3usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, ADC0 can be accessed from a Secure, Privileged context."]
+    #[inline(always)]
+    pub fn set_sp(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
+    }
+    #[doc = "If 1, ADC0 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn core0(&self) -> bool {
+        let val = (self.0 >> 4usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, ADC0 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_core0(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
+    }
+    #[doc = "If 1, ADC0 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn core1(&self) -> bool {
+        let val = (self.0 >> 5usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, ADC0 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_core1(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
+    }
+    #[doc = "If 1, ADC0 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn dma(&self) -> bool {
+        let val = (self.0 >> 6usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, ADC0 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_dma(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
+    }
+    #[doc = "If 1, ADC0 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn dbg(&self) -> bool {
+        let val = (self.0 >> 7usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, ADC0 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_dbg(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
+    }
+}
+impl Default for Adc0 {
+    #[inline(always)]
+    fn default() -> Adc0 {
+        Adc0(0)
+    }
+}
+#[doc = "Control whether debugger, DMA, core 0 and core 1 can access BUSCTRL, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Busctrl(pub u32);
+impl Busctrl {
+    #[doc = "If 1, and NSP is also set, BUSCTRL can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."]
+    #[inline(always)]
+    pub const fn nsu(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, and NSP is also set, BUSCTRL can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."]
+    #[inline(always)]
+    pub fn set_nsu(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[doc = "If 1, BUSCTRL can be accessed from a Non-secure, Privileged context."]
+    #[inline(always)]
+    pub const fn nsp(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, BUSCTRL can be accessed from a Non-secure, Privileged context."]
+    #[inline(always)]
+    pub fn set_nsp(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+    #[doc = "If 1, and SP is also set, BUSCTRL can be accessed from a Secure, Unprivileged context."]
+    #[inline(always)]
+    pub const fn su(&self) -> bool {
+        let val = (self.0 >> 2usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, and SP is also set, BUSCTRL can be accessed from a Secure, Unprivileged context."]
+    #[inline(always)]
+    pub fn set_su(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+    }
+    #[doc = "If 1, BUSCTRL can be accessed from a Secure, Privileged context."]
+    #[inline(always)]
+    pub const fn sp(&self) -> bool {
+        let val = (self.0 >> 3usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, BUSCTRL can be accessed from a Secure, Privileged context."]
+    #[inline(always)]
+    pub fn set_sp(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
+    }
+    #[doc = "If 1, BUSCTRL can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn core0(&self) -> bool {
+        let val = (self.0 >> 4usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, BUSCTRL can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_core0(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
+    }
+    #[doc = "If 1, BUSCTRL can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn core1(&self) -> bool {
+        let val = (self.0 >> 5usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, BUSCTRL can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_core1(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
+    }
+    #[doc = "If 1, BUSCTRL can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn dma(&self) -> bool {
+        let val = (self.0 >> 6usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, BUSCTRL can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_dma(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
+    }
+    #[doc = "If 1, BUSCTRL can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn dbg(&self) -> bool {
+        let val = (self.0 >> 7usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, BUSCTRL can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_dbg(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
+    }
+}
+impl Default for Busctrl {
+    #[inline(always)]
+    fn default() -> Busctrl {
+        Busctrl(0)
+    }
+}
+#[doc = "Write 1 to reset all ACCESSCTRL configuration, except for the LOCK and FORCE_CORE_NS registers. This bit is used in the RP2350 bootrom to quickly restore ACCESSCTRL to a known state during the boot path. Note that, like all registers in ACCESSCTRL, this register is not writable when the writer's corresponding LOCK bit is set, therefore a master which has been locked out of ACCESSCTRL can not use the CFGRESET register to disturb its contents."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Cfgreset(pub u32);
+impl Cfgreset {
+    #[inline(always)]
+    pub const fn cfgreset(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_cfgreset(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+}
+impl Default for Cfgreset {
+    #[inline(always)]
+    fn default() -> Cfgreset {
+        Cfgreset(0)
+    }
+}
+#[doc = "Control whether debugger, DMA, core 0 and core 1 can access CLOCKS, and at what security/privilege levels they can do so. Defaults to Secure, Privileged processor or debug access only. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Clocks(pub u32);
+impl Clocks {
+    #[doc = "If 1, and NSP is also set, CLOCKS can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."]
+    #[inline(always)]
+    pub const fn nsu(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, and NSP is also set, CLOCKS can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."]
+    #[inline(always)]
+    pub fn set_nsu(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[doc = "If 1, CLOCKS can be accessed from a Non-secure, Privileged context."]
+    #[inline(always)]
+    pub const fn nsp(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, CLOCKS can be accessed from a Non-secure, Privileged context."]
+    #[inline(always)]
+    pub fn set_nsp(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+    #[doc = "If 1, and SP is also set, CLOCKS can be accessed from a Secure, Unprivileged context."]
+    #[inline(always)]
+    pub const fn su(&self) -> bool {
+        let val = (self.0 >> 2usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, and SP is also set, CLOCKS can be accessed from a Secure, Unprivileged context."]
+    #[inline(always)]
+    pub fn set_su(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+    }
+    #[doc = "If 1, CLOCKS can be accessed from a Secure, Privileged context."]
+    #[inline(always)]
+    pub const fn sp(&self) -> bool {
+        let val = (self.0 >> 3usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, CLOCKS can be accessed from a Secure, Privileged context."]
+    #[inline(always)]
+    pub fn set_sp(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
+    }
+    #[doc = "If 1, CLOCKS can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn core0(&self) -> bool {
+        let val = (self.0 >> 4usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, CLOCKS can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_core0(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
+    }
+    #[doc = "If 1, CLOCKS can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn core1(&self) -> bool {
+        let val = (self.0 >> 5usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, CLOCKS can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_core1(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
+    }
+    #[doc = "If 1, CLOCKS can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn dma(&self) -> bool {
+        let val = (self.0 >> 6usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, CLOCKS can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_dma(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
+    }
+    #[doc = "If 1, CLOCKS can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn dbg(&self) -> bool {
+        let val = (self.0 >> 7usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, CLOCKS can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_dbg(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
+    }
+}
+impl Default for Clocks {
+    #[inline(always)]
+    fn default() -> Clocks {
+        Clocks(0)
+    }
+}
+#[doc = "Control whether debugger, DMA, core 0 and core 1 can access CORESIGHT_PERIPH, and at what security/privilege levels they can do so. Defaults to Secure, Privileged processor or debug access only. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct CoresightPeriph(pub u32);
+impl CoresightPeriph {
+    #[doc = "If 1, and NSP is also set, CORESIGHT_PERIPH can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."]
+    #[inline(always)]
+    pub const fn nsu(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, and NSP is also set, CORESIGHT_PERIPH can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."]
+    #[inline(always)]
+    pub fn set_nsu(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[doc = "If 1, CORESIGHT_PERIPH can be accessed from a Non-secure, Privileged context."]
+    #[inline(always)]
+    pub const fn nsp(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, CORESIGHT_PERIPH can be accessed from a Non-secure, Privileged context."]
+    #[inline(always)]
+    pub fn set_nsp(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+    #[doc = "If 1, and SP is also set, CORESIGHT_PERIPH can be accessed from a Secure, Unprivileged context."]
+    #[inline(always)]
+    pub const fn su(&self) -> bool {
+        let val = (self.0 >> 2usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, and SP is also set, CORESIGHT_PERIPH can be accessed from a Secure, Unprivileged context."]
+    #[inline(always)]
+    pub fn set_su(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+    }
+    #[doc = "If 1, CORESIGHT_PERIPH can be accessed from a Secure, Privileged context."]
+    #[inline(always)]
+    pub const fn sp(&self) -> bool {
+        let val = (self.0 >> 3usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, CORESIGHT_PERIPH can be accessed from a Secure, Privileged context."]
+    #[inline(always)]
+    pub fn set_sp(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
+    }
+    #[doc = "If 1, CORESIGHT_PERIPH can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn core0(&self) -> bool {
+        let val = (self.0 >> 4usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, CORESIGHT_PERIPH can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_core0(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
+    }
+    #[doc = "If 1, CORESIGHT_PERIPH can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn core1(&self) -> bool {
+        let val = (self.0 >> 5usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, CORESIGHT_PERIPH can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_core1(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
+    }
+    #[doc = "If 1, CORESIGHT_PERIPH can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn dma(&self) -> bool {
+        let val = (self.0 >> 6usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, CORESIGHT_PERIPH can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_dma(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
+    }
+    #[doc = "If 1, CORESIGHT_PERIPH can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn dbg(&self) -> bool {
+        let val = (self.0 >> 7usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, CORESIGHT_PERIPH can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_dbg(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
+    }
+}
+impl Default for CoresightPeriph {
+    #[inline(always)]
+    fn default() -> CoresightPeriph {
+        CoresightPeriph(0)
+    }
+}
+#[doc = "Control whether debugger, DMA, core 0 and core 1 can access CORESIGHT_TRACE, and at what security/privilege levels they can do so. Defaults to Secure, Privileged processor or debug access only. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct CoresightTrace(pub u32);
+impl CoresightTrace {
+    #[doc = "If 1, and NSP is also set, CORESIGHT_TRACE can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."]
+    #[inline(always)]
+    pub const fn nsu(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, and NSP is also set, CORESIGHT_TRACE can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."]
+    #[inline(always)]
+    pub fn set_nsu(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[doc = "If 1, CORESIGHT_TRACE can be accessed from a Non-secure, Privileged context."]
+    #[inline(always)]
+    pub const fn nsp(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, CORESIGHT_TRACE can be accessed from a Non-secure, Privileged context."]
+    #[inline(always)]
+    pub fn set_nsp(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+    #[doc = "If 1, and SP is also set, CORESIGHT_TRACE can be accessed from a Secure, Unprivileged context."]
+    #[inline(always)]
+    pub const fn su(&self) -> bool {
+        let val = (self.0 >> 2usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, and SP is also set, CORESIGHT_TRACE can be accessed from a Secure, Unprivileged context."]
+    #[inline(always)]
+    pub fn set_su(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+    }
+    #[doc = "If 1, CORESIGHT_TRACE can be accessed from a Secure, Privileged context."]
+    #[inline(always)]
+    pub const fn sp(&self) -> bool {
+        let val = (self.0 >> 3usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, CORESIGHT_TRACE can be accessed from a Secure, Privileged context."]
+    #[inline(always)]
+    pub fn set_sp(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
+    }
+    #[doc = "If 1, CORESIGHT_TRACE can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn core0(&self) -> bool {
+        let val = (self.0 >> 4usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, CORESIGHT_TRACE can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_core0(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
+    }
+    #[doc = "If 1, CORESIGHT_TRACE can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn core1(&self) -> bool {
+        let val = (self.0 >> 5usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, CORESIGHT_TRACE can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_core1(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
+    }
+    #[doc = "If 1, CORESIGHT_TRACE can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn dma(&self) -> bool {
+        let val = (self.0 >> 6usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, CORESIGHT_TRACE can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_dma(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
+    }
+    #[doc = "If 1, CORESIGHT_TRACE can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn dbg(&self) -> bool {
+        let val = (self.0 >> 7usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, CORESIGHT_TRACE can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_dbg(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
+    }
+}
+impl Default for CoresightTrace {
+    #[inline(always)]
+    fn default() -> CoresightTrace {
+        CoresightTrace(0)
+    }
+}
+#[doc = "Control whether debugger, DMA, core 0 and core 1 can access DMA, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Dma(pub u32);
+impl Dma {
+    #[doc = "If 1, and NSP is also set, DMA can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."]
+    #[inline(always)]
+    pub const fn nsu(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, and NSP is also set, DMA can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."]
+    #[inline(always)]
+    pub fn set_nsu(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[doc = "If 1, DMA can be accessed from a Non-secure, Privileged context."]
+    #[inline(always)]
+    pub const fn nsp(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, DMA can be accessed from a Non-secure, Privileged context."]
+    #[inline(always)]
+    pub fn set_nsp(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+    #[doc = "If 1, and SP is also set, DMA can be accessed from a Secure, Unprivileged context."]
+    #[inline(always)]
+    pub const fn su(&self) -> bool {
+        let val = (self.0 >> 2usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, and SP is also set, DMA can be accessed from a Secure, Unprivileged context."]
+    #[inline(always)]
+    pub fn set_su(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+    }
+    #[doc = "If 1, DMA can be accessed from a Secure, Privileged context."]
+    #[inline(always)]
+    pub const fn sp(&self) -> bool {
+        let val = (self.0 >> 3usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, DMA can be accessed from a Secure, Privileged context."]
+    #[inline(always)]
+    pub fn set_sp(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
+    }
+    #[doc = "If 1, DMA can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn core0(&self) -> bool {
+        let val = (self.0 >> 4usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, DMA can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_core0(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
+    }
+    #[doc = "If 1, DMA can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn core1(&self) -> bool {
+        let val = (self.0 >> 5usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, DMA can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_core1(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
+    }
+    #[doc = "If 1, DMA can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn dma(&self) -> bool {
+        let val = (self.0 >> 6usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, DMA can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_dma(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
+    }
+    #[doc = "If 1, DMA can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn dbg(&self) -> bool {
+        let val = (self.0 >> 7usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, DMA can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_dbg(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
+    }
+}
+impl Default for Dma {
+    #[inline(always)]
+    fn default() -> Dma {
+        Dma(0)
+    }
+}
+#[doc = "Force core 1's bus accesses to always be Non-secure, no matter the core's internal state. Useful for schemes where one core is designated as the Non-secure core, since some peripherals may filter individual registers internally based on security state but not on master ID."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct ForceCoreNs(pub u32);
+impl ForceCoreNs {
+    #[inline(always)]
+    pub const fn core1(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_core1(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+}
+impl Default for ForceCoreNs {
+    #[inline(always)]
+    fn default() -> ForceCoreNs {
+        ForceCoreNs(0)
+    }
+}
+#[doc = "Control whether GPIO32..47 are accessible to Non-secure code, and whether QSPI and USB bitbang are accessible through the Non-secure SIO. Writable only by a Secure, Privileged processor or debugger."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct GpioNsmask1(pub u32);
+impl GpioNsmask1 {
+    #[inline(always)]
+    pub const fn gpio(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0xffff;
+        val as u16
+    }
+    #[inline(always)]
+    pub fn set_gpio(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+    }
+    #[inline(always)]
+    pub const fn usb_dp(&self) -> bool {
+        let val = (self.0 >> 24usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_usb_dp(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 24usize)) | (((val as u32) & 0x01) << 24usize);
+    }
+    #[inline(always)]
+    pub const fn usb_dm(&self) -> bool {
+        let val = (self.0 >> 25usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_usb_dm(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 25usize)) | (((val as u32) & 0x01) << 25usize);
+    }
+    #[inline(always)]
+    pub const fn qspi_sck(&self) -> bool {
+        let val = (self.0 >> 26usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_qspi_sck(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 26usize)) | (((val as u32) & 0x01) << 26usize);
+    }
+    #[inline(always)]
+    pub const fn qspi_csn(&self) -> bool {
+        let val = (self.0 >> 27usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_qspi_csn(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 27usize)) | (((val as u32) & 0x01) << 27usize);
+    }
+    #[inline(always)]
+    pub const fn qspi_sd(&self) -> u8 {
+        let val = (self.0 >> 28usize) & 0x0f;
+        val as u8
+    }
+    #[inline(always)]
+    pub fn set_qspi_sd(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x0f << 28usize)) | (((val as u32) & 0x0f) << 28usize);
+    }
+}
+impl Default for GpioNsmask1 {
+    #[inline(always)]
+    fn default() -> GpioNsmask1 {
+        GpioNsmask1(0)
+    }
+}
+#[doc = "Control whether debugger, DMA, core 0 and core 1 can access HSTX, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Hstx(pub u32);
+impl Hstx {
+    #[doc = "If 1, and NSP is also set, HSTX can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."]
+    #[inline(always)]
+    pub const fn nsu(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, and NSP is also set, HSTX can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."]
+    #[inline(always)]
+    pub fn set_nsu(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[doc = "If 1, HSTX can be accessed from a Non-secure, Privileged context."]
+    #[inline(always)]
+    pub const fn nsp(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, HSTX can be accessed from a Non-secure, Privileged context."]
+    #[inline(always)]
+    pub fn set_nsp(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+    #[doc = "If 1, and SP is also set, HSTX can be accessed from a Secure, Unprivileged context."]
+    #[inline(always)]
+    pub const fn su(&self) -> bool {
+        let val = (self.0 >> 2usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, and SP is also set, HSTX can be accessed from a Secure, Unprivileged context."]
+    #[inline(always)]
+    pub fn set_su(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+    }
+    #[doc = "If 1, HSTX can be accessed from a Secure, Privileged context."]
+    #[inline(always)]
+    pub const fn sp(&self) -> bool {
+        let val = (self.0 >> 3usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, HSTX can be accessed from a Secure, Privileged context."]
+    #[inline(always)]
+    pub fn set_sp(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
+    }
+    #[doc = "If 1, HSTX can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn core0(&self) -> bool {
+        let val = (self.0 >> 4usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, HSTX can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_core0(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
+    }
+    #[doc = "If 1, HSTX can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn core1(&self) -> bool {
+        let val = (self.0 >> 5usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, HSTX can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_core1(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
+    }
+    #[doc = "If 1, HSTX can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn dma(&self) -> bool {
+        let val = (self.0 >> 6usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, HSTX can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_dma(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
+    }
+    #[doc = "If 1, HSTX can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn dbg(&self) -> bool {
+        let val = (self.0 >> 7usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, HSTX can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_dbg(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
+    }
+}
+impl Default for Hstx {
+    #[inline(always)]
+    fn default() -> Hstx {
+        Hstx(0)
+    }
+}
+#[doc = "Control whether debugger, DMA, core 0 and core 1 can access I2C0, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct I2c0(pub u32);
+impl I2c0 {
+    #[doc = "If 1, and NSP is also set, I2C0 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."]
+    #[inline(always)]
+    pub const fn nsu(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, and NSP is also set, I2C0 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."]
+    #[inline(always)]
+    pub fn set_nsu(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[doc = "If 1, I2C0 can be accessed from a Non-secure, Privileged context."]
+    #[inline(always)]
+    pub const fn nsp(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, I2C0 can be accessed from a Non-secure, Privileged context."]
+    #[inline(always)]
+    pub fn set_nsp(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+    #[doc = "If 1, and SP is also set, I2C0 can be accessed from a Secure, Unprivileged context."]
+    #[inline(always)]
+    pub const fn su(&self) -> bool {
+        let val = (self.0 >> 2usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, and SP is also set, I2C0 can be accessed from a Secure, Unprivileged context."]
+    #[inline(always)]
+    pub fn set_su(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+    }
+    #[doc = "If 1, I2C0 can be accessed from a Secure, Privileged context."]
+    #[inline(always)]
+    pub const fn sp(&self) -> bool {
+        let val = (self.0 >> 3usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, I2C0 can be accessed from a Secure, Privileged context."]
+    #[inline(always)]
+    pub fn set_sp(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
+    }
+    #[doc = "If 1, I2C0 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn core0(&self) -> bool {
+        let val = (self.0 >> 4usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, I2C0 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_core0(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
+    }
+    #[doc = "If 1, I2C0 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn core1(&self) -> bool {
+        let val = (self.0 >> 5usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, I2C0 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_core1(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
+    }
+    #[doc = "If 1, I2C0 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn dma(&self) -> bool {
+        let val = (self.0 >> 6usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, I2C0 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_dma(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
+    }
+    #[doc = "If 1, I2C0 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn dbg(&self) -> bool {
+        let val = (self.0 >> 7usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, I2C0 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_dbg(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
+    }
+}
+impl Default for I2c0 {
+    #[inline(always)]
+    fn default() -> I2c0 {
+        I2c0(0)
+    }
+}
+#[doc = "Control whether debugger, DMA, core 0 and core 1 can access I2C1, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct I2c1(pub u32);
+impl I2c1 {
+    #[doc = "If 1, and NSP is also set, I2C1 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."]
+    #[inline(always)]
+    pub const fn nsu(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, and NSP is also set, I2C1 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."]
+    #[inline(always)]
+    pub fn set_nsu(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[doc = "If 1, I2C1 can be accessed from a Non-secure, Privileged context."]
+    #[inline(always)]
+    pub const fn nsp(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, I2C1 can be accessed from a Non-secure, Privileged context."]
+    #[inline(always)]
+    pub fn set_nsp(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+    #[doc = "If 1, and SP is also set, I2C1 can be accessed from a Secure, Unprivileged context."]
+    #[inline(always)]
+    pub const fn su(&self) -> bool {
+        let val = (self.0 >> 2usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, and SP is also set, I2C1 can be accessed from a Secure, Unprivileged context."]
+    #[inline(always)]
+    pub fn set_su(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+    }
+    #[doc = "If 1, I2C1 can be accessed from a Secure, Privileged context."]
+    #[inline(always)]
+    pub const fn sp(&self) -> bool {
+        let val = (self.0 >> 3usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, I2C1 can be accessed from a Secure, Privileged context."]
+    #[inline(always)]
+    pub fn set_sp(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
+    }
+    #[doc = "If 1, I2C1 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn core0(&self) -> bool {
+        let val = (self.0 >> 4usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, I2C1 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_core0(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
+    }
+    #[doc = "If 1, I2C1 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn core1(&self) -> bool {
+        let val = (self.0 >> 5usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, I2C1 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_core1(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
+    }
+    #[doc = "If 1, I2C1 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn dma(&self) -> bool {
+        let val = (self.0 >> 6usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, I2C1 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_dma(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
+    }
+    #[doc = "If 1, I2C1 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn dbg(&self) -> bool {
+        let val = (self.0 >> 7usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, I2C1 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_dbg(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
+    }
+}
+impl Default for I2c1 {
+    #[inline(always)]
+    fn default() -> I2c1 {
+        I2c1(0)
+    }
+}
+#[doc = "Control whether debugger, DMA, core 0 and core 1 can access IO_BANK0, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct IoBank0(pub u32);
+impl IoBank0 {
+    #[doc = "If 1, and NSP is also set, IO_BANK0 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."]
+    #[inline(always)]
+    pub const fn nsu(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, and NSP is also set, IO_BANK0 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."]
+    #[inline(always)]
+    pub fn set_nsu(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[doc = "If 1, IO_BANK0 can be accessed from a Non-secure, Privileged context."]
+    #[inline(always)]
+    pub const fn nsp(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, IO_BANK0 can be accessed from a Non-secure, Privileged context."]
+    #[inline(always)]
+    pub fn set_nsp(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+    #[doc = "If 1, and SP is also set, IO_BANK0 can be accessed from a Secure, Unprivileged context."]
+    #[inline(always)]
+    pub const fn su(&self) -> bool {
+        let val = (self.0 >> 2usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, and SP is also set, IO_BANK0 can be accessed from a Secure, Unprivileged context."]
+    #[inline(always)]
+    pub fn set_su(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+    }
+    #[doc = "If 1, IO_BANK0 can be accessed from a Secure, Privileged context."]
+    #[inline(always)]
+    pub const fn sp(&self) -> bool {
+        let val = (self.0 >> 3usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, IO_BANK0 can be accessed from a Secure, Privileged context."]
+    #[inline(always)]
+    pub fn set_sp(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
+    }
+    #[doc = "If 1, IO_BANK0 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn core0(&self) -> bool {
+        let val = (self.0 >> 4usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, IO_BANK0 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_core0(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
+    }
+    #[doc = "If 1, IO_BANK0 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn core1(&self) -> bool {
+        let val = (self.0 >> 5usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, IO_BANK0 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_core1(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
+    }
+    #[doc = "If 1, IO_BANK0 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn dma(&self) -> bool {
+        let val = (self.0 >> 6usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, IO_BANK0 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_dma(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
+    }
+    #[doc = "If 1, IO_BANK0 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn dbg(&self) -> bool {
+        let val = (self.0 >> 7usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, IO_BANK0 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_dbg(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
+    }
+}
+impl Default for IoBank0 {
+    #[inline(always)]
+    fn default() -> IoBank0 {
+        IoBank0(0)
+    }
+}
+#[doc = "Control whether debugger, DMA, core 0 and core 1 can access IO_BANK1, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct IoBank1(pub u32);
+impl IoBank1 {
+    #[doc = "If 1, and NSP is also set, IO_BANK1 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."]
+    #[inline(always)]
+    pub const fn nsu(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, and NSP is also set, IO_BANK1 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."]
+    #[inline(always)]
+    pub fn set_nsu(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[doc = "If 1, IO_BANK1 can be accessed from a Non-secure, Privileged context."]
+    #[inline(always)]
+    pub const fn nsp(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, IO_BANK1 can be accessed from a Non-secure, Privileged context."]
+    #[inline(always)]
+    pub fn set_nsp(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+    #[doc = "If 1, and SP is also set, IO_BANK1 can be accessed from a Secure, Unprivileged context."]
+    #[inline(always)]
+    pub const fn su(&self) -> bool {
+        let val = (self.0 >> 2usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, and SP is also set, IO_BANK1 can be accessed from a Secure, Unprivileged context."]
+    #[inline(always)]
+    pub fn set_su(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+    }
+    #[doc = "If 1, IO_BANK1 can be accessed from a Secure, Privileged context."]
+    #[inline(always)]
+    pub const fn sp(&self) -> bool {
+        let val = (self.0 >> 3usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, IO_BANK1 can be accessed from a Secure, Privileged context."]
+    #[inline(always)]
+    pub fn set_sp(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
+    }
+    #[doc = "If 1, IO_BANK1 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn core0(&self) -> bool {
+        let val = (self.0 >> 4usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, IO_BANK1 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_core0(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
+    }
+    #[doc = "If 1, IO_BANK1 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn core1(&self) -> bool {
+        let val = (self.0 >> 5usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, IO_BANK1 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_core1(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
+    }
+    #[doc = "If 1, IO_BANK1 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn dma(&self) -> bool {
+        let val = (self.0 >> 6usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, IO_BANK1 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_dma(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
+    }
+    #[doc = "If 1, IO_BANK1 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn dbg(&self) -> bool {
+        let val = (self.0 >> 7usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, IO_BANK1 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_dbg(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
+    }
+}
+impl Default for IoBank1 {
+    #[inline(always)]
+    fn default() -> IoBank1 {
+        IoBank1(0)
+    }
+}
+#[doc = "Once a LOCK bit is written to 1, ACCESSCTRL silently ignores writes from that master. LOCK is writable only by a Secure, Privileged processor or debugger. LOCK bits are only writable when their value is zero. Once set, they can never be cleared, except by a full reset of ACCESSCTRL Setting the LOCK bit does not affect whether an access raises a bus error. Unprivileged writes, or writes from the DMA, will continue to raise bus errors. All other accesses will continue not to."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Lock(pub u32);
+impl Lock {
+    #[inline(always)]
+    pub const fn core0(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_core0(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[inline(always)]
+    pub const fn core1(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_core1(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+    #[inline(always)]
+    pub const fn dma(&self) -> bool {
+        let val = (self.0 >> 2usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_dma(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+    }
+    #[inline(always)]
+    pub const fn debug(&self) -> bool {
+        let val = (self.0 >> 3usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_debug(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
+    }
+}
+impl Default for Lock {
+    #[inline(always)]
+    fn default() -> Lock {
+        Lock(0)
+    }
+}
+#[doc = "Control whether debugger, DMA, core 0 and core 1 can access OTP, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Otp(pub u32);
+impl Otp {
+    #[doc = "If 1, and NSP is also set, OTP can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."]
+    #[inline(always)]
+    pub const fn nsu(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, and NSP is also set, OTP can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."]
+    #[inline(always)]
+    pub fn set_nsu(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[doc = "If 1, OTP can be accessed from a Non-secure, Privileged context."]
+    #[inline(always)]
+    pub const fn nsp(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, OTP can be accessed from a Non-secure, Privileged context."]
+    #[inline(always)]
+    pub fn set_nsp(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+    #[doc = "If 1, and SP is also set, OTP can be accessed from a Secure, Unprivileged context."]
+    #[inline(always)]
+    pub const fn su(&self) -> bool {
+        let val = (self.0 >> 2usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, and SP is also set, OTP can be accessed from a Secure, Unprivileged context."]
+    #[inline(always)]
+    pub fn set_su(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+    }
+    #[doc = "If 1, OTP can be accessed from a Secure, Privileged context."]
+    #[inline(always)]
+    pub const fn sp(&self) -> bool {
+        let val = (self.0 >> 3usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, OTP can be accessed from a Secure, Privileged context."]
+    #[inline(always)]
+    pub fn set_sp(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
+    }
+    #[doc = "If 1, OTP can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn core0(&self) -> bool {
+        let val = (self.0 >> 4usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, OTP can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_core0(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
+    }
+    #[doc = "If 1, OTP can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn core1(&self) -> bool {
+        let val = (self.0 >> 5usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, OTP can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_core1(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
+    }
+    #[doc = "If 1, OTP can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn dma(&self) -> bool {
+        let val = (self.0 >> 6usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, OTP can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_dma(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
+    }
+    #[doc = "If 1, OTP can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn dbg(&self) -> bool {
+        let val = (self.0 >> 7usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, OTP can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_dbg(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
+    }
+}
+impl Default for Otp {
+    #[inline(always)]
+    fn default() -> Otp {
+        Otp(0)
+    }
+}
+#[doc = "Control whether debugger, DMA, core 0 and core 1 can access PADS_BANK0, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct PadsBank0(pub u32);
+impl PadsBank0 {
+    #[doc = "If 1, and NSP is also set, PADS_BANK0 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."]
+    #[inline(always)]
+    pub const fn nsu(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, and NSP is also set, PADS_BANK0 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."]
+    #[inline(always)]
+    pub fn set_nsu(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[doc = "If 1, PADS_BANK0 can be accessed from a Non-secure, Privileged context."]
+    #[inline(always)]
+    pub const fn nsp(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, PADS_BANK0 can be accessed from a Non-secure, Privileged context."]
+    #[inline(always)]
+    pub fn set_nsp(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+    #[doc = "If 1, and SP is also set, PADS_BANK0 can be accessed from a Secure, Unprivileged context."]
+    #[inline(always)]
+    pub const fn su(&self) -> bool {
+        let val = (self.0 >> 2usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, and SP is also set, PADS_BANK0 can be accessed from a Secure, Unprivileged context."]
+    #[inline(always)]
+    pub fn set_su(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+    }
+    #[doc = "If 1, PADS_BANK0 can be accessed from a Secure, Privileged context."]
+    #[inline(always)]
+    pub const fn sp(&self) -> bool {
+        let val = (self.0 >> 3usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, PADS_BANK0 can be accessed from a Secure, Privileged context."]
+    #[inline(always)]
+    pub fn set_sp(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
+    }
+    #[doc = "If 1, PADS_BANK0 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn core0(&self) -> bool {
+        let val = (self.0 >> 4usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, PADS_BANK0 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_core0(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
+    }
+    #[doc = "If 1, PADS_BANK0 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn core1(&self) -> bool {
+        let val = (self.0 >> 5usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, PADS_BANK0 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_core1(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
+    }
+    #[doc = "If 1, PADS_BANK0 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn dma(&self) -> bool {
+        let val = (self.0 >> 6usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, PADS_BANK0 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_dma(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
+    }
+    #[doc = "If 1, PADS_BANK0 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn dbg(&self) -> bool {
+        let val = (self.0 >> 7usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, PADS_BANK0 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_dbg(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
+    }
+}
+impl Default for PadsBank0 {
+    #[inline(always)]
+    fn default() -> PadsBank0 {
+        PadsBank0(0)
+    }
+}
+#[doc = "Control whether debugger, DMA, core 0 and core 1 can access PADS_QSPI, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct PadsQspi(pub u32);
+impl PadsQspi {
+    #[doc = "If 1, and NSP is also set, PADS_QSPI can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."]
+    #[inline(always)]
+    pub const fn nsu(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, and NSP is also set, PADS_QSPI can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."]
+    #[inline(always)]
+    pub fn set_nsu(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[doc = "If 1, PADS_QSPI can be accessed from a Non-secure, Privileged context."]
+    #[inline(always)]
+    pub const fn nsp(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, PADS_QSPI can be accessed from a Non-secure, Privileged context."]
+    #[inline(always)]
+    pub fn set_nsp(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+    #[doc = "If 1, and SP is also set, PADS_QSPI can be accessed from a Secure, Unprivileged context."]
+    #[inline(always)]
+    pub const fn su(&self) -> bool {
+        let val = (self.0 >> 2usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, and SP is also set, PADS_QSPI can be accessed from a Secure, Unprivileged context."]
+    #[inline(always)]
+    pub fn set_su(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+    }
+    #[doc = "If 1, PADS_QSPI can be accessed from a Secure, Privileged context."]
+    #[inline(always)]
+    pub const fn sp(&self) -> bool {
+        let val = (self.0 >> 3usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, PADS_QSPI can be accessed from a Secure, Privileged context."]
+    #[inline(always)]
+    pub fn set_sp(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
+    }
+    #[doc = "If 1, PADS_QSPI can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn core0(&self) -> bool {
+        let val = (self.0 >> 4usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, PADS_QSPI can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_core0(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
+    }
+    #[doc = "If 1, PADS_QSPI can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn core1(&self) -> bool {
+        let val = (self.0 >> 5usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, PADS_QSPI can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_core1(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
+    }
+    #[doc = "If 1, PADS_QSPI can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn dma(&self) -> bool {
+        let val = (self.0 >> 6usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, PADS_QSPI can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_dma(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
+    }
+    #[doc = "If 1, PADS_QSPI can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn dbg(&self) -> bool {
+        let val = (self.0 >> 7usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, PADS_QSPI can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_dbg(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
+    }
+}
+impl Default for PadsQspi {
+    #[inline(always)]
+    fn default() -> PadsQspi {
+        PadsQspi(0)
+    }
+}
+#[doc = "Control whether debugger, DMA, core 0 and core 1 can access PIO0, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Pio0(pub u32);
+impl Pio0 {
+    #[doc = "If 1, and NSP is also set, PIO0 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."]
+    #[inline(always)]
+    pub const fn nsu(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, and NSP is also set, PIO0 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."]
+    #[inline(always)]
+    pub fn set_nsu(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[doc = "If 1, PIO0 can be accessed from a Non-secure, Privileged context."]
+    #[inline(always)]
+    pub const fn nsp(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, PIO0 can be accessed from a Non-secure, Privileged context."]
+    #[inline(always)]
+    pub fn set_nsp(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+    #[doc = "If 1, and SP is also set, PIO0 can be accessed from a Secure, Unprivileged context."]
+    #[inline(always)]
+    pub const fn su(&self) -> bool {
+        let val = (self.0 >> 2usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, and SP is also set, PIO0 can be accessed from a Secure, Unprivileged context."]
+    #[inline(always)]
+    pub fn set_su(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+    }
+    #[doc = "If 1, PIO0 can be accessed from a Secure, Privileged context."]
+    #[inline(always)]
+    pub const fn sp(&self) -> bool {
+        let val = (self.0 >> 3usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, PIO0 can be accessed from a Secure, Privileged context."]
+    #[inline(always)]
+    pub fn set_sp(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
+    }
+    #[doc = "If 1, PIO0 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn core0(&self) -> bool {
+        let val = (self.0 >> 4usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, PIO0 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_core0(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
+    }
+    #[doc = "If 1, PIO0 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn core1(&self) -> bool {
+        let val = (self.0 >> 5usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, PIO0 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_core1(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
+    }
+    #[doc = "If 1, PIO0 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn dma(&self) -> bool {
+        let val = (self.0 >> 6usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, PIO0 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_dma(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
+    }
+    #[doc = "If 1, PIO0 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn dbg(&self) -> bool {
+        let val = (self.0 >> 7usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, PIO0 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_dbg(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
+    }
+}
+impl Default for Pio0 {
+    #[inline(always)]
+    fn default() -> Pio0 {
+        Pio0(0)
+    }
+}
+#[doc = "Control whether debugger, DMA, core 0 and core 1 can access PIO1, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Pio1(pub u32);
+impl Pio1 {
+    #[doc = "If 1, and NSP is also set, PIO1 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."]
+    #[inline(always)]
+    pub const fn nsu(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, and NSP is also set, PIO1 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."]
+    #[inline(always)]
+    pub fn set_nsu(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[doc = "If 1, PIO1 can be accessed from a Non-secure, Privileged context."]
+    #[inline(always)]
+    pub const fn nsp(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, PIO1 can be accessed from a Non-secure, Privileged context."]
+    #[inline(always)]
+    pub fn set_nsp(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+    #[doc = "If 1, and SP is also set, PIO1 can be accessed from a Secure, Unprivileged context."]
+    #[inline(always)]
+    pub const fn su(&self) -> bool {
+        let val = (self.0 >> 2usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, and SP is also set, PIO1 can be accessed from a Secure, Unprivileged context."]
+    #[inline(always)]
+    pub fn set_su(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+    }
+    #[doc = "If 1, PIO1 can be accessed from a Secure, Privileged context."]
+    #[inline(always)]
+    pub const fn sp(&self) -> bool {
+        let val = (self.0 >> 3usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, PIO1 can be accessed from a Secure, Privileged context."]
+    #[inline(always)]
+    pub fn set_sp(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
+    }
+    #[doc = "If 1, PIO1 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn core0(&self) -> bool {
+        let val = (self.0 >> 4usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, PIO1 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_core0(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
+    }
+    #[doc = "If 1, PIO1 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn core1(&self) -> bool {
+        let val = (self.0 >> 5usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, PIO1 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_core1(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
+    }
+    #[doc = "If 1, PIO1 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn dma(&self) -> bool {
+        let val = (self.0 >> 6usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, PIO1 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_dma(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
+    }
+    #[doc = "If 1, PIO1 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn dbg(&self) -> bool {
+        let val = (self.0 >> 7usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, PIO1 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_dbg(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
+    }
+}
+impl Default for Pio1 {
+    #[inline(always)]
+    fn default() -> Pio1 {
+        Pio1(0)
+    }
+}
+#[doc = "Control whether debugger, DMA, core 0 and core 1 can access PIO2, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Pio2(pub u32);
+impl Pio2 {
+    #[doc = "If 1, and NSP is also set, PIO2 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."]
+    #[inline(always)]
+    pub const fn nsu(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, and NSP is also set, PIO2 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."]
+    #[inline(always)]
+    pub fn set_nsu(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[doc = "If 1, PIO2 can be accessed from a Non-secure, Privileged context."]
+    #[inline(always)]
+    pub const fn nsp(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, PIO2 can be accessed from a Non-secure, Privileged context."]
+    #[inline(always)]
+    pub fn set_nsp(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+    #[doc = "If 1, and SP is also set, PIO2 can be accessed from a Secure, Unprivileged context."]
+    #[inline(always)]
+    pub const fn su(&self) -> bool {
+        let val = (self.0 >> 2usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, and SP is also set, PIO2 can be accessed from a Secure, Unprivileged context."]
+    #[inline(always)]
+    pub fn set_su(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+    }
+    #[doc = "If 1, PIO2 can be accessed from a Secure, Privileged context."]
+    #[inline(always)]
+    pub const fn sp(&self) -> bool {
+        let val = (self.0 >> 3usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, PIO2 can be accessed from a Secure, Privileged context."]
+    #[inline(always)]
+    pub fn set_sp(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
+    }
+    #[doc = "If 1, PIO2 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn core0(&self) -> bool {
+        let val = (self.0 >> 4usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, PIO2 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_core0(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
+    }
+    #[doc = "If 1, PIO2 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn core1(&self) -> bool {
+        let val = (self.0 >> 5usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, PIO2 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_core1(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
+    }
+    #[doc = "If 1, PIO2 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn dma(&self) -> bool {
+        let val = (self.0 >> 6usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, PIO2 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_dma(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
+    }
+    #[doc = "If 1, PIO2 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn dbg(&self) -> bool {
+        let val = (self.0 >> 7usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, PIO2 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_dbg(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
+    }
+}
+impl Default for Pio2 {
+    #[inline(always)]
+    fn default() -> Pio2 {
+        Pio2(0)
+    }
+}
+#[doc = "Control whether debugger, DMA, core 0 and core 1 can access PLL_SYS, and at what security/privilege levels they can do so. Defaults to Secure, Privileged processor or debug access only. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct PllSys(pub u32);
+impl PllSys {
+    #[doc = "If 1, and NSP is also set, PLL_SYS can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."]
+    #[inline(always)]
+    pub const fn nsu(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, and NSP is also set, PLL_SYS can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."]
+    #[inline(always)]
+    pub fn set_nsu(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[doc = "If 1, PLL_SYS can be accessed from a Non-secure, Privileged context."]
+    #[inline(always)]
+    pub const fn nsp(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, PLL_SYS can be accessed from a Non-secure, Privileged context."]
+    #[inline(always)]
+    pub fn set_nsp(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+    #[doc = "If 1, and SP is also set, PLL_SYS can be accessed from a Secure, Unprivileged context."]
+    #[inline(always)]
+    pub const fn su(&self) -> bool {
+        let val = (self.0 >> 2usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, and SP is also set, PLL_SYS can be accessed from a Secure, Unprivileged context."]
+    #[inline(always)]
+    pub fn set_su(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+    }
+    #[doc = "If 1, PLL_SYS can be accessed from a Secure, Privileged context."]
+    #[inline(always)]
+    pub const fn sp(&self) -> bool {
+        let val = (self.0 >> 3usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, PLL_SYS can be accessed from a Secure, Privileged context."]
+    #[inline(always)]
+    pub fn set_sp(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
+    }
+    #[doc = "If 1, PLL_SYS can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn core0(&self) -> bool {
+        let val = (self.0 >> 4usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, PLL_SYS can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_core0(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
+    }
+    #[doc = "If 1, PLL_SYS can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn core1(&self) -> bool {
+        let val = (self.0 >> 5usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, PLL_SYS can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_core1(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
+    }
+    #[doc = "If 1, PLL_SYS can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn dma(&self) -> bool {
+        let val = (self.0 >> 6usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, PLL_SYS can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_dma(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
+    }
+    #[doc = "If 1, PLL_SYS can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn dbg(&self) -> bool {
+        let val = (self.0 >> 7usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, PLL_SYS can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_dbg(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
+    }
+}
+impl Default for PllSys {
+    #[inline(always)]
+    fn default() -> PllSys {
+        PllSys(0)
+    }
+}
+#[doc = "Control whether debugger, DMA, core 0 and core 1 can access PLL_USB, and at what security/privilege levels they can do so. Defaults to Secure, Privileged processor or debug access only. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct PllUsb(pub u32);
+impl PllUsb {
+    #[doc = "If 1, and NSP is also set, PLL_USB can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."]
+    #[inline(always)]
+    pub const fn nsu(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, and NSP is also set, PLL_USB can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."]
+    #[inline(always)]
+    pub fn set_nsu(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[doc = "If 1, PLL_USB can be accessed from a Non-secure, Privileged context."]
+    #[inline(always)]
+    pub const fn nsp(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, PLL_USB can be accessed from a Non-secure, Privileged context."]
+    #[inline(always)]
+    pub fn set_nsp(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+    #[doc = "If 1, and SP is also set, PLL_USB can be accessed from a Secure, Unprivileged context."]
+    #[inline(always)]
+    pub const fn su(&self) -> bool {
+        let val = (self.0 >> 2usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, and SP is also set, PLL_USB can be accessed from a Secure, Unprivileged context."]
+    #[inline(always)]
+    pub fn set_su(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+    }
+    #[doc = "If 1, PLL_USB can be accessed from a Secure, Privileged context."]
+    #[inline(always)]
+    pub const fn sp(&self) -> bool {
+        let val = (self.0 >> 3usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, PLL_USB can be accessed from a Secure, Privileged context."]
+    #[inline(always)]
+    pub fn set_sp(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
+    }
+    #[doc = "If 1, PLL_USB can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn core0(&self) -> bool {
+        let val = (self.0 >> 4usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, PLL_USB can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_core0(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
+    }
+    #[doc = "If 1, PLL_USB can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn core1(&self) -> bool {
+        let val = (self.0 >> 5usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, PLL_USB can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_core1(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
+    }
+    #[doc = "If 1, PLL_USB can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn dma(&self) -> bool {
+        let val = (self.0 >> 6usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, PLL_USB can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_dma(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
+    }
+    #[doc = "If 1, PLL_USB can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn dbg(&self) -> bool {
+        let val = (self.0 >> 7usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, PLL_USB can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_dbg(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
+    }
+}
+impl Default for PllUsb {
+    #[inline(always)]
+    fn default() -> PllUsb {
+        PllUsb(0)
+    }
+}
+#[doc = "Control whether debugger, DMA, core 0 and core 1 can access POWMAN, and at what security/privilege levels they can do so. Defaults to Secure, Privileged processor or debug access only. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Powman(pub u32);
+impl Powman {
+    #[doc = "If 1, and NSP is also set, POWMAN can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."]
+    #[inline(always)]
+    pub const fn nsu(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, and NSP is also set, POWMAN can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."]
+    #[inline(always)]
+    pub fn set_nsu(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[doc = "If 1, POWMAN can be accessed from a Non-secure, Privileged context."]
+    #[inline(always)]
+    pub const fn nsp(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, POWMAN can be accessed from a Non-secure, Privileged context."]
+    #[inline(always)]
+    pub fn set_nsp(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+    #[doc = "If 1, and SP is also set, POWMAN can be accessed from a Secure, Unprivileged context."]
+    #[inline(always)]
+    pub const fn su(&self) -> bool {
+        let val = (self.0 >> 2usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, and SP is also set, POWMAN can be accessed from a Secure, Unprivileged context."]
+    #[inline(always)]
+    pub fn set_su(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+    }
+    #[doc = "If 1, POWMAN can be accessed from a Secure, Privileged context."]
+    #[inline(always)]
+    pub const fn sp(&self) -> bool {
+        let val = (self.0 >> 3usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, POWMAN can be accessed from a Secure, Privileged context."]
+    #[inline(always)]
+    pub fn set_sp(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
+    }
+    #[doc = "If 1, POWMAN can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn core0(&self) -> bool {
+        let val = (self.0 >> 4usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, POWMAN can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_core0(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
+    }
+    #[doc = "If 1, POWMAN can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn core1(&self) -> bool {
+        let val = (self.0 >> 5usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, POWMAN can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_core1(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
+    }
+    #[doc = "If 1, POWMAN can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn dma(&self) -> bool {
+        let val = (self.0 >> 6usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, POWMAN can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_dma(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
+    }
+    #[doc = "If 1, POWMAN can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn dbg(&self) -> bool {
+        let val = (self.0 >> 7usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, POWMAN can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_dbg(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
+    }
+}
+impl Default for Powman {
+    #[inline(always)]
+    fn default() -> Powman {
+        Powman(0)
+    }
+}
+#[doc = "Control whether debugger, DMA, core 0 and core 1 can access PWM, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Pwm(pub u32);
+impl Pwm {
+    #[doc = "If 1, and NSP is also set, PWM can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."]
+    #[inline(always)]
+    pub const fn nsu(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, and NSP is also set, PWM can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."]
+    #[inline(always)]
+    pub fn set_nsu(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[doc = "If 1, PWM can be accessed from a Non-secure, Privileged context."]
+    #[inline(always)]
+    pub const fn nsp(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, PWM can be accessed from a Non-secure, Privileged context."]
+    #[inline(always)]
+    pub fn set_nsp(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+    #[doc = "If 1, and SP is also set, PWM can be accessed from a Secure, Unprivileged context."]
+    #[inline(always)]
+    pub const fn su(&self) -> bool {
+        let val = (self.0 >> 2usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, and SP is also set, PWM can be accessed from a Secure, Unprivileged context."]
+    #[inline(always)]
+    pub fn set_su(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+    }
+    #[doc = "If 1, PWM can be accessed from a Secure, Privileged context."]
+    #[inline(always)]
+    pub const fn sp(&self) -> bool {
+        let val = (self.0 >> 3usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, PWM can be accessed from a Secure, Privileged context."]
+    #[inline(always)]
+    pub fn set_sp(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
+    }
+    #[doc = "If 1, PWM can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn core0(&self) -> bool {
+        let val = (self.0 >> 4usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, PWM can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_core0(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
+    }
+    #[doc = "If 1, PWM can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn core1(&self) -> bool {
+        let val = (self.0 >> 5usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, PWM can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_core1(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
+    }
+    #[doc = "If 1, PWM can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn dma(&self) -> bool {
+        let val = (self.0 >> 6usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, PWM can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_dma(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
+    }
+    #[doc = "If 1, PWM can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn dbg(&self) -> bool {
+        let val = (self.0 >> 7usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, PWM can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_dbg(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
+    }
+}
+impl Default for Pwm {
+    #[inline(always)]
+    fn default() -> Pwm {
+        Pwm(0)
+    }
+}
+#[doc = "Control whether debugger, DMA, core 0 and core 1 can access RESETS, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Resets(pub u32);
+impl Resets {
+    #[doc = "If 1, and NSP is also set, RESETS can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."]
+    #[inline(always)]
+    pub const fn nsu(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, and NSP is also set, RESETS can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."]
+    #[inline(always)]
+    pub fn set_nsu(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[doc = "If 1, RESETS can be accessed from a Non-secure, Privileged context."]
+    #[inline(always)]
+    pub const fn nsp(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, RESETS can be accessed from a Non-secure, Privileged context."]
+    #[inline(always)]
+    pub fn set_nsp(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+    #[doc = "If 1, and SP is also set, RESETS can be accessed from a Secure, Unprivileged context."]
+    #[inline(always)]
+    pub const fn su(&self) -> bool {
+        let val = (self.0 >> 2usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, and SP is also set, RESETS can be accessed from a Secure, Unprivileged context."]
+    #[inline(always)]
+    pub fn set_su(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+    }
+    #[doc = "If 1, RESETS can be accessed from a Secure, Privileged context."]
+    #[inline(always)]
+    pub const fn sp(&self) -> bool {
+        let val = (self.0 >> 3usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, RESETS can be accessed from a Secure, Privileged context."]
+    #[inline(always)]
+    pub fn set_sp(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
+    }
+    #[doc = "If 1, RESETS can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn core0(&self) -> bool {
+        let val = (self.0 >> 4usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, RESETS can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_core0(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
+    }
+    #[doc = "If 1, RESETS can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn core1(&self) -> bool {
+        let val = (self.0 >> 5usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, RESETS can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_core1(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
+    }
+    #[doc = "If 1, RESETS can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn dma(&self) -> bool {
+        let val = (self.0 >> 6usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, RESETS can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_dma(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
+    }
+    #[doc = "If 1, RESETS can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn dbg(&self) -> bool {
+        let val = (self.0 >> 7usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, RESETS can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_dbg(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
+    }
+}
+impl Default for Resets {
+    #[inline(always)]
+    fn default() -> Resets {
+        Resets(0)
+    }
+}
+#[doc = "Control whether debugger, DMA, core 0 and core 1 can access ROM, and at what security/privilege levels they can do so. Defaults to fully open access. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Rom(pub u32);
+impl Rom {
+    #[doc = "If 1, and NSP is also set, ROM can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."]
+    #[inline(always)]
+    pub const fn nsu(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, and NSP is also set, ROM can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."]
+    #[inline(always)]
+    pub fn set_nsu(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[doc = "If 1, ROM can be accessed from a Non-secure, Privileged context."]
+    #[inline(always)]
+    pub const fn nsp(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, ROM can be accessed from a Non-secure, Privileged context."]
+    #[inline(always)]
+    pub fn set_nsp(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+    #[doc = "If 1, and SP is also set, ROM can be accessed from a Secure, Unprivileged context."]
+    #[inline(always)]
+    pub const fn su(&self) -> bool {
+        let val = (self.0 >> 2usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, and SP is also set, ROM can be accessed from a Secure, Unprivileged context."]
+    #[inline(always)]
+    pub fn set_su(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+    }
+    #[doc = "If 1, ROM can be accessed from a Secure, Privileged context."]
+    #[inline(always)]
+    pub const fn sp(&self) -> bool {
+        let val = (self.0 >> 3usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, ROM can be accessed from a Secure, Privileged context."]
+    #[inline(always)]
+    pub fn set_sp(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
+    }
+    #[doc = "If 1, ROM can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn core0(&self) -> bool {
+        let val = (self.0 >> 4usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, ROM can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_core0(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
+    }
+    #[doc = "If 1, ROM can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn core1(&self) -> bool {
+        let val = (self.0 >> 5usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, ROM can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_core1(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
+    }
+    #[doc = "If 1, ROM can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn dma(&self) -> bool {
+        let val = (self.0 >> 6usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, ROM can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_dma(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
+    }
+    #[doc = "If 1, ROM can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn dbg(&self) -> bool {
+        let val = (self.0 >> 7usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, ROM can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_dbg(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
+    }
+}
+impl Default for Rom {
+    #[inline(always)]
+    fn default() -> Rom {
+        Rom(0)
+    }
+}
+#[doc = "Control whether debugger, DMA, core 0 and core 1 can access ROSC, and at what security/privilege levels they can do so. Defaults to Secure, Privileged processor or debug access only. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Rosc(pub u32);
+impl Rosc {
+    #[doc = "If 1, and NSP is also set, ROSC can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."]
+    #[inline(always)]
+    pub const fn nsu(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, and NSP is also set, ROSC can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."]
+    #[inline(always)]
+    pub fn set_nsu(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[doc = "If 1, ROSC can be accessed from a Non-secure, Privileged context."]
+    #[inline(always)]
+    pub const fn nsp(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, ROSC can be accessed from a Non-secure, Privileged context."]
+    #[inline(always)]
+    pub fn set_nsp(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+    #[doc = "If 1, and SP is also set, ROSC can be accessed from a Secure, Unprivileged context."]
+    #[inline(always)]
+    pub const fn su(&self) -> bool {
+        let val = (self.0 >> 2usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, and SP is also set, ROSC can be accessed from a Secure, Unprivileged context."]
+    #[inline(always)]
+    pub fn set_su(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+    }
+    #[doc = "If 1, ROSC can be accessed from a Secure, Privileged context."]
+    #[inline(always)]
+    pub const fn sp(&self) -> bool {
+        let val = (self.0 >> 3usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, ROSC can be accessed from a Secure, Privileged context."]
+    #[inline(always)]
+    pub fn set_sp(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
+    }
+    #[doc = "If 1, ROSC can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn core0(&self) -> bool {
+        let val = (self.0 >> 4usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, ROSC can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_core0(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
+    }
+    #[doc = "If 1, ROSC can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn core1(&self) -> bool {
+        let val = (self.0 >> 5usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, ROSC can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_core1(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
+    }
+    #[doc = "If 1, ROSC can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn dma(&self) -> bool {
+        let val = (self.0 >> 6usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, ROSC can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_dma(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
+    }
+    #[doc = "If 1, ROSC can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn dbg(&self) -> bool {
+        let val = (self.0 >> 7usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, ROSC can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_dbg(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
+    }
+}
+impl Default for Rosc {
+    #[inline(always)]
+    fn default() -> Rosc {
+        Rosc(0)
+    }
+}
+#[doc = "Control whether debugger, DMA, core 0 and core 1 can access RSM, and at what security/privilege levels they can do so. Defaults to Secure, Privileged processor or debug access only. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Rsm(pub u32);
+impl Rsm {
+    #[doc = "If 1, and NSP is also set, RSM can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."]
+    #[inline(always)]
+    pub const fn nsu(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, and NSP is also set, RSM can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."]
+    #[inline(always)]
+    pub fn set_nsu(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[doc = "If 1, RSM can be accessed from a Non-secure, Privileged context."]
+    #[inline(always)]
+    pub const fn nsp(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, RSM can be accessed from a Non-secure, Privileged context."]
+    #[inline(always)]
+    pub fn set_nsp(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+    #[doc = "If 1, and SP is also set, RSM can be accessed from a Secure, Unprivileged context."]
+    #[inline(always)]
+    pub const fn su(&self) -> bool {
+        let val = (self.0 >> 2usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, and SP is also set, RSM can be accessed from a Secure, Unprivileged context."]
+    #[inline(always)]
+    pub fn set_su(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+    }
+    #[doc = "If 1, RSM can be accessed from a Secure, Privileged context."]
+    #[inline(always)]
+    pub const fn sp(&self) -> bool {
+        let val = (self.0 >> 3usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, RSM can be accessed from a Secure, Privileged context."]
+    #[inline(always)]
+    pub fn set_sp(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
+    }
+    #[doc = "If 1, RSM can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn core0(&self) -> bool {
+        let val = (self.0 >> 4usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, RSM can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_core0(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
+    }
+    #[doc = "If 1, RSM can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn core1(&self) -> bool {
+        let val = (self.0 >> 5usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, RSM can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_core1(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
+    }
+    #[doc = "If 1, RSM can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn dma(&self) -> bool {
+        let val = (self.0 >> 6usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, RSM can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_dma(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
+    }
+    #[doc = "If 1, RSM can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn dbg(&self) -> bool {
+        let val = (self.0 >> 7usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, RSM can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_dbg(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
+    }
+}
+impl Default for Rsm {
+    #[inline(always)]
+    fn default() -> Rsm {
+        Rsm(0)
+    }
+}
+#[doc = "Control whether debugger, DMA, core 0 and core 1 can access SHA256, and at what security/privilege levels they can do so. Defaults to Secure, Privileged access only. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Sha256(pub u32);
+impl Sha256 {
+    #[doc = "If 1, and NSP is also set, SHA256 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."]
+    #[inline(always)]
+    pub const fn nsu(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, and NSP is also set, SHA256 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."]
+    #[inline(always)]
+    pub fn set_nsu(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[doc = "If 1, SHA256 can be accessed from a Non-secure, Privileged context."]
+    #[inline(always)]
+    pub const fn nsp(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, SHA256 can be accessed from a Non-secure, Privileged context."]
+    #[inline(always)]
+    pub fn set_nsp(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+    #[doc = "If 1, and SP is also set, SHA256 can be accessed from a Secure, Unprivileged context."]
+    #[inline(always)]
+    pub const fn su(&self) -> bool {
+        let val = (self.0 >> 2usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, and SP is also set, SHA256 can be accessed from a Secure, Unprivileged context."]
+    #[inline(always)]
+    pub fn set_su(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+    }
+    #[doc = "If 1, SHA256 can be accessed from a Secure, Privileged context."]
+    #[inline(always)]
+    pub const fn sp(&self) -> bool {
+        let val = (self.0 >> 3usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, SHA256 can be accessed from a Secure, Privileged context."]
+    #[inline(always)]
+    pub fn set_sp(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
+    }
+    #[doc = "If 1, SHA256 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn core0(&self) -> bool {
+        let val = (self.0 >> 4usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, SHA256 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_core0(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
+    }
+    #[doc = "If 1, SHA256 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn core1(&self) -> bool {
+        let val = (self.0 >> 5usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, SHA256 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_core1(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
+    }
+    #[doc = "If 1, SHA256 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn dma(&self) -> bool {
+        let val = (self.0 >> 6usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, SHA256 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_dma(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
+    }
+    #[doc = "If 1, SHA256 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn dbg(&self) -> bool {
+        let val = (self.0 >> 7usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, SHA256 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_dbg(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
+    }
+}
+impl Default for Sha256 {
+    #[inline(always)]
+    fn default() -> Sha256 {
+        Sha256(0)
+    }
+}
+#[doc = "Control whether debugger, DMA, core 0 and core 1 can access SPI0, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Spi0(pub u32);
+impl Spi0 {
+    #[doc = "If 1, and NSP is also set, SPI0 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."]
+    #[inline(always)]
+    pub const fn nsu(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, and NSP is also set, SPI0 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."]
+    #[inline(always)]
+    pub fn set_nsu(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[doc = "If 1, SPI0 can be accessed from a Non-secure, Privileged context."]
+    #[inline(always)]
+    pub const fn nsp(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, SPI0 can be accessed from a Non-secure, Privileged context."]
+    #[inline(always)]
+    pub fn set_nsp(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+    #[doc = "If 1, and SP is also set, SPI0 can be accessed from a Secure, Unprivileged context."]
+    #[inline(always)]
+    pub const fn su(&self) -> bool {
+        let val = (self.0 >> 2usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, and SP is also set, SPI0 can be accessed from a Secure, Unprivileged context."]
+    #[inline(always)]
+    pub fn set_su(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+    }
+    #[doc = "If 1, SPI0 can be accessed from a Secure, Privileged context."]
+    #[inline(always)]
+    pub const fn sp(&self) -> bool {
+        let val = (self.0 >> 3usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, SPI0 can be accessed from a Secure, Privileged context."]
+    #[inline(always)]
+    pub fn set_sp(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
+    }
+    #[doc = "If 1, SPI0 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn core0(&self) -> bool {
+        let val = (self.0 >> 4usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, SPI0 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_core0(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
+    }
+    #[doc = "If 1, SPI0 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn core1(&self) -> bool {
+        let val = (self.0 >> 5usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, SPI0 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_core1(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
+    }
+    #[doc = "If 1, SPI0 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn dma(&self) -> bool {
+        let val = (self.0 >> 6usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, SPI0 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_dma(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
+    }
+    #[doc = "If 1, SPI0 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn dbg(&self) -> bool {
+        let val = (self.0 >> 7usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, SPI0 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_dbg(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
+    }
+}
+impl Default for Spi0 {
+    #[inline(always)]
+    fn default() -> Spi0 {
+        Spi0(0)
+    }
+}
+#[doc = "Control whether debugger, DMA, core 0 and core 1 can access SPI1, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Spi1(pub u32);
+impl Spi1 {
+    #[doc = "If 1, and NSP is also set, SPI1 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."]
+    #[inline(always)]
+    pub const fn nsu(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, and NSP is also set, SPI1 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."]
+    #[inline(always)]
+    pub fn set_nsu(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[doc = "If 1, SPI1 can be accessed from a Non-secure, Privileged context."]
+    #[inline(always)]
+    pub const fn nsp(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, SPI1 can be accessed from a Non-secure, Privileged context."]
+    #[inline(always)]
+    pub fn set_nsp(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+    #[doc = "If 1, and SP is also set, SPI1 can be accessed from a Secure, Unprivileged context."]
+    #[inline(always)]
+    pub const fn su(&self) -> bool {
+        let val = (self.0 >> 2usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, and SP is also set, SPI1 can be accessed from a Secure, Unprivileged context."]
+    #[inline(always)]
+    pub fn set_su(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+    }
+    #[doc = "If 1, SPI1 can be accessed from a Secure, Privileged context."]
+    #[inline(always)]
+    pub const fn sp(&self) -> bool {
+        let val = (self.0 >> 3usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, SPI1 can be accessed from a Secure, Privileged context."]
+    #[inline(always)]
+    pub fn set_sp(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
+    }
+    #[doc = "If 1, SPI1 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn core0(&self) -> bool {
+        let val = (self.0 >> 4usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, SPI1 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_core0(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
+    }
+    #[doc = "If 1, SPI1 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn core1(&self) -> bool {
+        let val = (self.0 >> 5usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, SPI1 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_core1(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
+    }
+    #[doc = "If 1, SPI1 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn dma(&self) -> bool {
+        let val = (self.0 >> 6usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, SPI1 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_dma(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
+    }
+    #[doc = "If 1, SPI1 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn dbg(&self) -> bool {
+        let val = (self.0 >> 7usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, SPI1 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_dbg(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
+    }
+}
+impl Default for Spi1 {
+    #[inline(always)]
+    fn default() -> Spi1 {
+        Spi1(0)
+    }
+}
+#[doc = "Control whether debugger, DMA, core 0 and core 1 can access SRAM0, and at what security/privilege levels they can do so. Defaults to fully open access. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Sram0(pub u32);
+impl Sram0 {
+    #[doc = "If 1, and NSP is also set, SRAM0 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."]
+    #[inline(always)]
+    pub const fn nsu(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, and NSP is also set, SRAM0 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."]
+    #[inline(always)]
+    pub fn set_nsu(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[doc = "If 1, SRAM0 can be accessed from a Non-secure, Privileged context."]
+    #[inline(always)]
+    pub const fn nsp(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, SRAM0 can be accessed from a Non-secure, Privileged context."]
+    #[inline(always)]
+    pub fn set_nsp(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+    #[doc = "If 1, and SP is also set, SRAM0 can be accessed from a Secure, Unprivileged context."]
+    #[inline(always)]
+    pub const fn su(&self) -> bool {
+        let val = (self.0 >> 2usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, and SP is also set, SRAM0 can be accessed from a Secure, Unprivileged context."]
+    #[inline(always)]
+    pub fn set_su(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+    }
+    #[doc = "If 1, SRAM0 can be accessed from a Secure, Privileged context."]
+    #[inline(always)]
+    pub const fn sp(&self) -> bool {
+        let val = (self.0 >> 3usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, SRAM0 can be accessed from a Secure, Privileged context."]
+    #[inline(always)]
+    pub fn set_sp(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
+    }
+    #[doc = "If 1, SRAM0 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn core0(&self) -> bool {
+        let val = (self.0 >> 4usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, SRAM0 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_core0(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
+    }
+    #[doc = "If 1, SRAM0 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn core1(&self) -> bool {
+        let val = (self.0 >> 5usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, SRAM0 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_core1(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
+    }
+    #[doc = "If 1, SRAM0 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn dma(&self) -> bool {
+        let val = (self.0 >> 6usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, SRAM0 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_dma(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
+    }
+    #[doc = "If 1, SRAM0 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn dbg(&self) -> bool {
+        let val = (self.0 >> 7usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, SRAM0 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_dbg(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
+    }
+}
+impl Default for Sram0 {
+    #[inline(always)]
+    fn default() -> Sram0 {
+        Sram0(0)
+    }
+}
+#[doc = "Control whether debugger, DMA, core 0 and core 1 can access SRAM1, and at what security/privilege levels they can do so. Defaults to fully open access. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Sram1(pub u32);
+impl Sram1 {
+    #[doc = "If 1, and NSP is also set, SRAM1 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."]
+    #[inline(always)]
+    pub const fn nsu(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, and NSP is also set, SRAM1 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."]
+    #[inline(always)]
+    pub fn set_nsu(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[doc = "If 1, SRAM1 can be accessed from a Non-secure, Privileged context."]
+    #[inline(always)]
+    pub const fn nsp(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, SRAM1 can be accessed from a Non-secure, Privileged context."]
+    #[inline(always)]
+    pub fn set_nsp(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+    #[doc = "If 1, and SP is also set, SRAM1 can be accessed from a Secure, Unprivileged context."]
+    #[inline(always)]
+    pub const fn su(&self) -> bool {
+        let val = (self.0 >> 2usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, and SP is also set, SRAM1 can be accessed from a Secure, Unprivileged context."]
+    #[inline(always)]
+    pub fn set_su(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+    }
+    #[doc = "If 1, SRAM1 can be accessed from a Secure, Privileged context."]
+    #[inline(always)]
+    pub const fn sp(&self) -> bool {
+        let val = (self.0 >> 3usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, SRAM1 can be accessed from a Secure, Privileged context."]
+    #[inline(always)]
+    pub fn set_sp(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
+    }
+    #[doc = "If 1, SRAM1 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn core0(&self) -> bool {
+        let val = (self.0 >> 4usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, SRAM1 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_core0(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
+    }
+    #[doc = "If 1, SRAM1 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn core1(&self) -> bool {
+        let val = (self.0 >> 5usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, SRAM1 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_core1(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
+    }
+    #[doc = "If 1, SRAM1 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn dma(&self) -> bool {
+        let val = (self.0 >> 6usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, SRAM1 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_dma(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
+    }
+    #[doc = "If 1, SRAM1 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn dbg(&self) -> bool {
+        let val = (self.0 >> 7usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, SRAM1 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_dbg(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
+    }
+}
+impl Default for Sram1 {
+    #[inline(always)]
+    fn default() -> Sram1 {
+        Sram1(0)
+    }
+}
+#[doc = "Control whether debugger, DMA, core 0 and core 1 can access SRAM2, and at what security/privilege levels they can do so. Defaults to fully open access. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Sram2(pub u32);
+impl Sram2 {
+    #[doc = "If 1, and NSP is also set, SRAM2 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."]
+    #[inline(always)]
+    pub const fn nsu(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, and NSP is also set, SRAM2 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."]
+    #[inline(always)]
+    pub fn set_nsu(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[doc = "If 1, SRAM2 can be accessed from a Non-secure, Privileged context."]
+    #[inline(always)]
+    pub const fn nsp(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, SRAM2 can be accessed from a Non-secure, Privileged context."]
+    #[inline(always)]
+    pub fn set_nsp(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+    #[doc = "If 1, and SP is also set, SRAM2 can be accessed from a Secure, Unprivileged context."]
+    #[inline(always)]
+    pub const fn su(&self) -> bool {
+        let val = (self.0 >> 2usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, and SP is also set, SRAM2 can be accessed from a Secure, Unprivileged context."]
+    #[inline(always)]
+    pub fn set_su(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+    }
+    #[doc = "If 1, SRAM2 can be accessed from a Secure, Privileged context."]
+    #[inline(always)]
+    pub const fn sp(&self) -> bool {
+        let val = (self.0 >> 3usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, SRAM2 can be accessed from a Secure, Privileged context."]
+    #[inline(always)]
+    pub fn set_sp(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
+    }
+    #[doc = "If 1, SRAM2 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn core0(&self) -> bool {
+        let val = (self.0 >> 4usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, SRAM2 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_core0(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
+    }
+    #[doc = "If 1, SRAM2 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn core1(&self) -> bool {
+        let val = (self.0 >> 5usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, SRAM2 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_core1(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
+    }
+    #[doc = "If 1, SRAM2 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn dma(&self) -> bool {
+        let val = (self.0 >> 6usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, SRAM2 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_dma(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
+    }
+    #[doc = "If 1, SRAM2 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn dbg(&self) -> bool {
+        let val = (self.0 >> 7usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, SRAM2 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_dbg(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
+    }
+}
+impl Default for Sram2 {
+    #[inline(always)]
+    fn default() -> Sram2 {
+        Sram2(0)
+    }
+}
+#[doc = "Control whether debugger, DMA, core 0 and core 1 can access SRAM3, and at what security/privilege levels they can do so. Defaults to fully open access. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Sram3(pub u32);
+impl Sram3 {
+    #[doc = "If 1, and NSP is also set, SRAM3 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."]
+    #[inline(always)]
+    pub const fn nsu(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, and NSP is also set, SRAM3 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."]
+    #[inline(always)]
+    pub fn set_nsu(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[doc = "If 1, SRAM3 can be accessed from a Non-secure, Privileged context."]
+    #[inline(always)]
+    pub const fn nsp(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, SRAM3 can be accessed from a Non-secure, Privileged context."]
+    #[inline(always)]
+    pub fn set_nsp(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+    #[doc = "If 1, and SP is also set, SRAM3 can be accessed from a Secure, Unprivileged context."]
+    #[inline(always)]
+    pub const fn su(&self) -> bool {
+        let val = (self.0 >> 2usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, and SP is also set, SRAM3 can be accessed from a Secure, Unprivileged context."]
+    #[inline(always)]
+    pub fn set_su(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+    }
+    #[doc = "If 1, SRAM3 can be accessed from a Secure, Privileged context."]
+    #[inline(always)]
+    pub const fn sp(&self) -> bool {
+        let val = (self.0 >> 3usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, SRAM3 can be accessed from a Secure, Privileged context."]
+    #[inline(always)]
+    pub fn set_sp(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
+    }
+    #[doc = "If 1, SRAM3 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn core0(&self) -> bool {
+        let val = (self.0 >> 4usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, SRAM3 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_core0(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
+    }
+    #[doc = "If 1, SRAM3 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn core1(&self) -> bool {
+        let val = (self.0 >> 5usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, SRAM3 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_core1(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
+    }
+    #[doc = "If 1, SRAM3 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn dma(&self) -> bool {
+        let val = (self.0 >> 6usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, SRAM3 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_dma(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
+    }
+    #[doc = "If 1, SRAM3 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn dbg(&self) -> bool {
+        let val = (self.0 >> 7usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, SRAM3 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_dbg(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
+    }
+}
+impl Default for Sram3 {
+    #[inline(always)]
+    fn default() -> Sram3 {
+        Sram3(0)
+    }
+}
+#[doc = "Control whether debugger, DMA, core 0 and core 1 can access SRAM4, and at what security/privilege levels they can do so. Defaults to fully open access. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Sram4(pub u32);
+impl Sram4 {
+    #[doc = "If 1, and NSP is also set, SRAM4 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."]
+    #[inline(always)]
+    pub const fn nsu(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, and NSP is also set, SRAM4 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."]
+    #[inline(always)]
+    pub fn set_nsu(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[doc = "If 1, SRAM4 can be accessed from a Non-secure, Privileged context."]
+    #[inline(always)]
+    pub const fn nsp(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, SRAM4 can be accessed from a Non-secure, Privileged context."]
+    #[inline(always)]
+    pub fn set_nsp(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+    #[doc = "If 1, and SP is also set, SRAM4 can be accessed from a Secure, Unprivileged context."]
+    #[inline(always)]
+    pub const fn su(&self) -> bool {
+        let val = (self.0 >> 2usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, and SP is also set, SRAM4 can be accessed from a Secure, Unprivileged context."]
+    #[inline(always)]
+    pub fn set_su(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+    }
+    #[doc = "If 1, SRAM4 can be accessed from a Secure, Privileged context."]
+    #[inline(always)]
+    pub const fn sp(&self) -> bool {
+        let val = (self.0 >> 3usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, SRAM4 can be accessed from a Secure, Privileged context."]
+    #[inline(always)]
+    pub fn set_sp(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
+    }
+    #[doc = "If 1, SRAM4 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn core0(&self) -> bool {
+        let val = (self.0 >> 4usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, SRAM4 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_core0(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
+    }
+    #[doc = "If 1, SRAM4 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn core1(&self) -> bool {
+        let val = (self.0 >> 5usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, SRAM4 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_core1(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
+    }
+    #[doc = "If 1, SRAM4 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn dma(&self) -> bool {
+        let val = (self.0 >> 6usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, SRAM4 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_dma(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
+    }
+    #[doc = "If 1, SRAM4 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn dbg(&self) -> bool {
+        let val = (self.0 >> 7usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, SRAM4 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_dbg(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
+    }
+}
+impl Default for Sram4 {
+    #[inline(always)]
+    fn default() -> Sram4 {
+        Sram4(0)
+    }
+}
+#[doc = "Control whether debugger, DMA, core 0 and core 1 can access SRAM5, and at what security/privilege levels they can do so. Defaults to fully open access. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Sram5(pub u32);
+impl Sram5 {
+    #[doc = "If 1, and NSP is also set, SRAM5 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."]
+    #[inline(always)]
+    pub const fn nsu(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, and NSP is also set, SRAM5 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."]
+    #[inline(always)]
+    pub fn set_nsu(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[doc = "If 1, SRAM5 can be accessed from a Non-secure, Privileged context."]
+    #[inline(always)]
+    pub const fn nsp(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, SRAM5 can be accessed from a Non-secure, Privileged context."]
+    #[inline(always)]
+    pub fn set_nsp(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+    #[doc = "If 1, and SP is also set, SRAM5 can be accessed from a Secure, Unprivileged context."]
+    #[inline(always)]
+    pub const fn su(&self) -> bool {
+        let val = (self.0 >> 2usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, and SP is also set, SRAM5 can be accessed from a Secure, Unprivileged context."]
+    #[inline(always)]
+    pub fn set_su(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+    }
+    #[doc = "If 1, SRAM5 can be accessed from a Secure, Privileged context."]
+    #[inline(always)]
+    pub const fn sp(&self) -> bool {
+        let val = (self.0 >> 3usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, SRAM5 can be accessed from a Secure, Privileged context."]
+    #[inline(always)]
+    pub fn set_sp(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
+    }
+    #[doc = "If 1, SRAM5 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn core0(&self) -> bool {
+        let val = (self.0 >> 4usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, SRAM5 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_core0(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
+    }
+    #[doc = "If 1, SRAM5 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn core1(&self) -> bool {
+        let val = (self.0 >> 5usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, SRAM5 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_core1(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
+    }
+    #[doc = "If 1, SRAM5 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn dma(&self) -> bool {
+        let val = (self.0 >> 6usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, SRAM5 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_dma(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
+    }
+    #[doc = "If 1, SRAM5 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn dbg(&self) -> bool {
+        let val = (self.0 >> 7usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, SRAM5 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_dbg(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
+    }
+}
+impl Default for Sram5 {
+    #[inline(always)]
+    fn default() -> Sram5 {
+        Sram5(0)
+    }
+}
+#[doc = "Control whether debugger, DMA, core 0 and core 1 can access SRAM6, and at what security/privilege levels they can do so. Defaults to fully open access. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Sram6(pub u32);
+impl Sram6 {
+    #[doc = "If 1, and NSP is also set, SRAM6 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."]
+    #[inline(always)]
+    pub const fn nsu(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, and NSP is also set, SRAM6 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."]
+    #[inline(always)]
+    pub fn set_nsu(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[doc = "If 1, SRAM6 can be accessed from a Non-secure, Privileged context."]
+    #[inline(always)]
+    pub const fn nsp(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, SRAM6 can be accessed from a Non-secure, Privileged context."]
+    #[inline(always)]
+    pub fn set_nsp(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+    #[doc = "If 1, and SP is also set, SRAM6 can be accessed from a Secure, Unprivileged context."]
+    #[inline(always)]
+    pub const fn su(&self) -> bool {
+        let val = (self.0 >> 2usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, and SP is also set, SRAM6 can be accessed from a Secure, Unprivileged context."]
+    #[inline(always)]
+    pub fn set_su(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+    }
+    #[doc = "If 1, SRAM6 can be accessed from a Secure, Privileged context."]
+    #[inline(always)]
+    pub const fn sp(&self) -> bool {
+        let val = (self.0 >> 3usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, SRAM6 can be accessed from a Secure, Privileged context."]
+    #[inline(always)]
+    pub fn set_sp(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
+    }
+    #[doc = "If 1, SRAM6 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn core0(&self) -> bool {
+        let val = (self.0 >> 4usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, SRAM6 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_core0(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
+    }
+    #[doc = "If 1, SRAM6 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn core1(&self) -> bool {
+        let val = (self.0 >> 5usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, SRAM6 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_core1(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
+    }
+    #[doc = "If 1, SRAM6 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn dma(&self) -> bool {
+        let val = (self.0 >> 6usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, SRAM6 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_dma(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
+    }
+    #[doc = "If 1, SRAM6 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn dbg(&self) -> bool {
+        let val = (self.0 >> 7usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, SRAM6 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_dbg(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
+    }
+}
+impl Default for Sram6 {
+    #[inline(always)]
+    fn default() -> Sram6 {
+        Sram6(0)
+    }
+}
+#[doc = "Control whether debugger, DMA, core 0 and core 1 can access SRAM7, and at what security/privilege levels they can do so. Defaults to fully open access. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Sram7(pub u32);
+impl Sram7 {
+    #[doc = "If 1, and NSP is also set, SRAM7 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."]
+    #[inline(always)]
+    pub const fn nsu(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, and NSP is also set, SRAM7 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."]
+    #[inline(always)]
+    pub fn set_nsu(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[doc = "If 1, SRAM7 can be accessed from a Non-secure, Privileged context."]
+    #[inline(always)]
+    pub const fn nsp(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, SRAM7 can be accessed from a Non-secure, Privileged context."]
+    #[inline(always)]
+    pub fn set_nsp(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+    #[doc = "If 1, and SP is also set, SRAM7 can be accessed from a Secure, Unprivileged context."]
+    #[inline(always)]
+    pub const fn su(&self) -> bool {
+        let val = (self.0 >> 2usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, and SP is also set, SRAM7 can be accessed from a Secure, Unprivileged context."]
+    #[inline(always)]
+    pub fn set_su(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+    }
+    #[doc = "If 1, SRAM7 can be accessed from a Secure, Privileged context."]
+    #[inline(always)]
+    pub const fn sp(&self) -> bool {
+        let val = (self.0 >> 3usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, SRAM7 can be accessed from a Secure, Privileged context."]
+    #[inline(always)]
+    pub fn set_sp(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
+    }
+    #[doc = "If 1, SRAM7 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn core0(&self) -> bool {
+        let val = (self.0 >> 4usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, SRAM7 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_core0(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
+    }
+    #[doc = "If 1, SRAM7 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn core1(&self) -> bool {
+        let val = (self.0 >> 5usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, SRAM7 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_core1(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
+    }
+    #[doc = "If 1, SRAM7 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn dma(&self) -> bool {
+        let val = (self.0 >> 6usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, SRAM7 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_dma(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
+    }
+    #[doc = "If 1, SRAM7 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn dbg(&self) -> bool {
+        let val = (self.0 >> 7usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, SRAM7 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_dbg(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
+    }
+}
+impl Default for Sram7 {
+    #[inline(always)]
+    fn default() -> Sram7 {
+        Sram7(0)
+    }
+}
+#[doc = "Control whether debugger, DMA, core 0 and core 1 can access SRAM8, and at what security/privilege levels they can do so. Defaults to fully open access. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Sram8(pub u32);
+impl Sram8 {
+    #[doc = "If 1, and NSP is also set, SRAM8 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."]
+    #[inline(always)]
+    pub const fn nsu(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, and NSP is also set, SRAM8 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."]
+    #[inline(always)]
+    pub fn set_nsu(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[doc = "If 1, SRAM8 can be accessed from a Non-secure, Privileged context."]
+    #[inline(always)]
+    pub const fn nsp(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, SRAM8 can be accessed from a Non-secure, Privileged context."]
+    #[inline(always)]
+    pub fn set_nsp(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+    #[doc = "If 1, and SP is also set, SRAM8 can be accessed from a Secure, Unprivileged context."]
+    #[inline(always)]
+    pub const fn su(&self) -> bool {
+        let val = (self.0 >> 2usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, and SP is also set, SRAM8 can be accessed from a Secure, Unprivileged context."]
+    #[inline(always)]
+    pub fn set_su(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+    }
+    #[doc = "If 1, SRAM8 can be accessed from a Secure, Privileged context."]
+    #[inline(always)]
+    pub const fn sp(&self) -> bool {
+        let val = (self.0 >> 3usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, SRAM8 can be accessed from a Secure, Privileged context."]
+    #[inline(always)]
+    pub fn set_sp(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
+    }
+    #[doc = "If 1, SRAM8 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn core0(&self) -> bool {
+        let val = (self.0 >> 4usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, SRAM8 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_core0(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
+    }
+    #[doc = "If 1, SRAM8 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn core1(&self) -> bool {
+        let val = (self.0 >> 5usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, SRAM8 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_core1(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
+    }
+    #[doc = "If 1, SRAM8 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn dma(&self) -> bool {
+        let val = (self.0 >> 6usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, SRAM8 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_dma(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
+    }
+    #[doc = "If 1, SRAM8 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn dbg(&self) -> bool {
+        let val = (self.0 >> 7usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, SRAM8 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_dbg(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
+    }
+}
+impl Default for Sram8 {
+    #[inline(always)]
+    fn default() -> Sram8 {
+        Sram8(0)
+    }
+}
+#[doc = "Control whether debugger, DMA, core 0 and core 1 can access SRAM9, and at what security/privilege levels they can do so. Defaults to fully open access. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Sram9(pub u32);
+impl Sram9 {
+    #[doc = "If 1, and NSP is also set, SRAM9 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."]
+    #[inline(always)]
+    pub const fn nsu(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, and NSP is also set, SRAM9 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."]
+    #[inline(always)]
+    pub fn set_nsu(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[doc = "If 1, SRAM9 can be accessed from a Non-secure, Privileged context."]
+    #[inline(always)]
+    pub const fn nsp(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, SRAM9 can be accessed from a Non-secure, Privileged context."]
+    #[inline(always)]
+    pub fn set_nsp(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+    #[doc = "If 1, and SP is also set, SRAM9 can be accessed from a Secure, Unprivileged context."]
+    #[inline(always)]
+    pub const fn su(&self) -> bool {
+        let val = (self.0 >> 2usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, and SP is also set, SRAM9 can be accessed from a Secure, Unprivileged context."]
+    #[inline(always)]
+    pub fn set_su(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+    }
+    #[doc = "If 1, SRAM9 can be accessed from a Secure, Privileged context."]
+    #[inline(always)]
+    pub const fn sp(&self) -> bool {
+        let val = (self.0 >> 3usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, SRAM9 can be accessed from a Secure, Privileged context."]
+    #[inline(always)]
+    pub fn set_sp(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
+    }
+    #[doc = "If 1, SRAM9 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn core0(&self) -> bool {
+        let val = (self.0 >> 4usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, SRAM9 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_core0(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
+    }
+    #[doc = "If 1, SRAM9 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn core1(&self) -> bool {
+        let val = (self.0 >> 5usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, SRAM9 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_core1(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
+    }
+    #[doc = "If 1, SRAM9 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn dma(&self) -> bool {
+        let val = (self.0 >> 6usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, SRAM9 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_dma(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
+    }
+    #[doc = "If 1, SRAM9 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn dbg(&self) -> bool {
+        let val = (self.0 >> 7usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, SRAM9 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_dbg(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
+    }
+}
+impl Default for Sram9 {
+    #[inline(always)]
+    fn default() -> Sram9 {
+        Sram9(0)
+    }
+}
+#[doc = "Control whether debugger, DMA, core 0 and core 1 can access SYSCFG, and at what security/privilege levels they can do so. Defaults to Secure, Privileged processor or debug access only. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Syscfg(pub u32);
+impl Syscfg {
+    #[doc = "If 1, and NSP is also set, SYSCFG can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."]
+    #[inline(always)]
+    pub const fn nsu(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, and NSP is also set, SYSCFG can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."]
+    #[inline(always)]
+    pub fn set_nsu(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[doc = "If 1, SYSCFG can be accessed from a Non-secure, Privileged context."]
+    #[inline(always)]
+    pub const fn nsp(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, SYSCFG can be accessed from a Non-secure, Privileged context."]
+    #[inline(always)]
+    pub fn set_nsp(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+    #[doc = "If 1, and SP is also set, SYSCFG can be accessed from a Secure, Unprivileged context."]
+    #[inline(always)]
+    pub const fn su(&self) -> bool {
+        let val = (self.0 >> 2usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, and SP is also set, SYSCFG can be accessed from a Secure, Unprivileged context."]
+    #[inline(always)]
+    pub fn set_su(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+    }
+    #[doc = "If 1, SYSCFG can be accessed from a Secure, Privileged context."]
+    #[inline(always)]
+    pub const fn sp(&self) -> bool {
+        let val = (self.0 >> 3usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, SYSCFG can be accessed from a Secure, Privileged context."]
+    #[inline(always)]
+    pub fn set_sp(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
+    }
+    #[doc = "If 1, SYSCFG can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn core0(&self) -> bool {
+        let val = (self.0 >> 4usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, SYSCFG can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_core0(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
+    }
+    #[doc = "If 1, SYSCFG can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn core1(&self) -> bool {
+        let val = (self.0 >> 5usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, SYSCFG can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_core1(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
+    }
+    #[doc = "If 1, SYSCFG can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn dma(&self) -> bool {
+        let val = (self.0 >> 6usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, SYSCFG can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_dma(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
+    }
+    #[doc = "If 1, SYSCFG can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn dbg(&self) -> bool {
+        let val = (self.0 >> 7usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, SYSCFG can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_dbg(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
+    }
+}
+impl Default for Syscfg {
+    #[inline(always)]
+    fn default() -> Syscfg {
+        Syscfg(0)
+    }
+}
+#[doc = "Control whether debugger, DMA, core 0 and core 1 can access SYSINFO, and at what security/privilege levels they can do so. Defaults to fully open access. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Sysinfo(pub u32);
+impl Sysinfo {
+    #[doc = "If 1, and NSP is also set, SYSINFO can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."]
+    #[inline(always)]
+    pub const fn nsu(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, and NSP is also set, SYSINFO can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."]
+    #[inline(always)]
+    pub fn set_nsu(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[doc = "If 1, SYSINFO can be accessed from a Non-secure, Privileged context."]
+    #[inline(always)]
+    pub const fn nsp(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, SYSINFO can be accessed from a Non-secure, Privileged context."]
+    #[inline(always)]
+    pub fn set_nsp(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+    #[doc = "If 1, and SP is also set, SYSINFO can be accessed from a Secure, Unprivileged context."]
+    #[inline(always)]
+    pub const fn su(&self) -> bool {
+        let val = (self.0 >> 2usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, and SP is also set, SYSINFO can be accessed from a Secure, Unprivileged context."]
+    #[inline(always)]
+    pub fn set_su(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+    }
+    #[doc = "If 1, SYSINFO can be accessed from a Secure, Privileged context."]
+    #[inline(always)]
+    pub const fn sp(&self) -> bool {
+        let val = (self.0 >> 3usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, SYSINFO can be accessed from a Secure, Privileged context."]
+    #[inline(always)]
+    pub fn set_sp(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
+    }
+    #[doc = "If 1, SYSINFO can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn core0(&self) -> bool {
+        let val = (self.0 >> 4usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, SYSINFO can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_core0(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
+    }
+    #[doc = "If 1, SYSINFO can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn core1(&self) -> bool {
+        let val = (self.0 >> 5usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, SYSINFO can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_core1(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
+    }
+    #[doc = "If 1, SYSINFO can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn dma(&self) -> bool {
+        let val = (self.0 >> 6usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, SYSINFO can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_dma(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
+    }
+    #[doc = "If 1, SYSINFO can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn dbg(&self) -> bool {
+        let val = (self.0 >> 7usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, SYSINFO can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_dbg(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
+    }
+}
+impl Default for Sysinfo {
+    #[inline(always)]
+    fn default() -> Sysinfo {
+        Sysinfo(0)
+    }
+}
+#[doc = "Control whether debugger, DMA, core 0 and core 1 can access TBMAN, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Tbman(pub u32);
+impl Tbman {
+    #[doc = "If 1, and NSP is also set, TBMAN can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."]
+    #[inline(always)]
+    pub const fn nsu(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, and NSP is also set, TBMAN can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."]
+    #[inline(always)]
+    pub fn set_nsu(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[doc = "If 1, TBMAN can be accessed from a Non-secure, Privileged context."]
+    #[inline(always)]
+    pub const fn nsp(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, TBMAN can be accessed from a Non-secure, Privileged context."]
+    #[inline(always)]
+    pub fn set_nsp(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+    #[doc = "If 1, and SP is also set, TBMAN can be accessed from a Secure, Unprivileged context."]
+    #[inline(always)]
+    pub const fn su(&self) -> bool {
+        let val = (self.0 >> 2usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, and SP is also set, TBMAN can be accessed from a Secure, Unprivileged context."]
+    #[inline(always)]
+    pub fn set_su(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+    }
+    #[doc = "If 1, TBMAN can be accessed from a Secure, Privileged context."]
+    #[inline(always)]
+    pub const fn sp(&self) -> bool {
+        let val = (self.0 >> 3usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, TBMAN can be accessed from a Secure, Privileged context."]
+    #[inline(always)]
+    pub fn set_sp(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
+    }
+    #[doc = "If 1, TBMAN can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn core0(&self) -> bool {
+        let val = (self.0 >> 4usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, TBMAN can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_core0(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
+    }
+    #[doc = "If 1, TBMAN can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn core1(&self) -> bool {
+        let val = (self.0 >> 5usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, TBMAN can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_core1(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
+    }
+    #[doc = "If 1, TBMAN can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn dma(&self) -> bool {
+        let val = (self.0 >> 6usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, TBMAN can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_dma(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
+    }
+    #[doc = "If 1, TBMAN can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn dbg(&self) -> bool {
+        let val = (self.0 >> 7usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, TBMAN can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_dbg(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
+    }
+}
+impl Default for Tbman {
+    #[inline(always)]
+    fn default() -> Tbman {
+        Tbman(0)
+    }
+}
+#[doc = "Control whether debugger, DMA, core 0 and core 1 can access TICKS, and at what security/privilege levels they can do so. Defaults to Secure, Privileged processor or debug access only. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Ticks(pub u32);
+impl Ticks {
+    #[doc = "If 1, and NSP is also set, TICKS can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."]
+    #[inline(always)]
+    pub const fn nsu(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, and NSP is also set, TICKS can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."]
+    #[inline(always)]
+    pub fn set_nsu(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[doc = "If 1, TICKS can be accessed from a Non-secure, Privileged context."]
+    #[inline(always)]
+    pub const fn nsp(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, TICKS can be accessed from a Non-secure, Privileged context."]
+    #[inline(always)]
+    pub fn set_nsp(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+    #[doc = "If 1, and SP is also set, TICKS can be accessed from a Secure, Unprivileged context."]
+    #[inline(always)]
+    pub const fn su(&self) -> bool {
+        let val = (self.0 >> 2usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, and SP is also set, TICKS can be accessed from a Secure, Unprivileged context."]
+    #[inline(always)]
+    pub fn set_su(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+    }
+    #[doc = "If 1, TICKS can be accessed from a Secure, Privileged context."]
+    #[inline(always)]
+    pub const fn sp(&self) -> bool {
+        let val = (self.0 >> 3usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, TICKS can be accessed from a Secure, Privileged context."]
+    #[inline(always)]
+    pub fn set_sp(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
+    }
+    #[doc = "If 1, TICKS can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn core0(&self) -> bool {
+        let val = (self.0 >> 4usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, TICKS can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_core0(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
+    }
+    #[doc = "If 1, TICKS can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn core1(&self) -> bool {
+        let val = (self.0 >> 5usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, TICKS can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_core1(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
+    }
+    #[doc = "If 1, TICKS can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn dma(&self) -> bool {
+        let val = (self.0 >> 6usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, TICKS can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_dma(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
+    }
+    #[doc = "If 1, TICKS can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn dbg(&self) -> bool {
+        let val = (self.0 >> 7usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, TICKS can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_dbg(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
+    }
+}
+impl Default for Ticks {
+    #[inline(always)]
+    fn default() -> Ticks {
+        Ticks(0)
+    }
+}
+#[doc = "Control whether debugger, DMA, core 0 and core 1 can access TIMER0, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Timer0(pub u32);
+impl Timer0 {
+    #[doc = "If 1, and NSP is also set, TIMER0 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."]
+    #[inline(always)]
+    pub const fn nsu(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, and NSP is also set, TIMER0 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."]
+    #[inline(always)]
+    pub fn set_nsu(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[doc = "If 1, TIMER0 can be accessed from a Non-secure, Privileged context."]
+    #[inline(always)]
+    pub const fn nsp(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, TIMER0 can be accessed from a Non-secure, Privileged context."]
+    #[inline(always)]
+    pub fn set_nsp(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+    #[doc = "If 1, and SP is also set, TIMER0 can be accessed from a Secure, Unprivileged context."]
+    #[inline(always)]
+    pub const fn su(&self) -> bool {
+        let val = (self.0 >> 2usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, and SP is also set, TIMER0 can be accessed from a Secure, Unprivileged context."]
+    #[inline(always)]
+    pub fn set_su(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+    }
+    #[doc = "If 1, TIMER0 can be accessed from a Secure, Privileged context."]
+    #[inline(always)]
+    pub const fn sp(&self) -> bool {
+        let val = (self.0 >> 3usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, TIMER0 can be accessed from a Secure, Privileged context."]
+    #[inline(always)]
+    pub fn set_sp(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
+    }
+    #[doc = "If 1, TIMER0 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn core0(&self) -> bool {
+        let val = (self.0 >> 4usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, TIMER0 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_core0(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
+    }
+    #[doc = "If 1, TIMER0 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn core1(&self) -> bool {
+        let val = (self.0 >> 5usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, TIMER0 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_core1(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
+    }
+    #[doc = "If 1, TIMER0 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn dma(&self) -> bool {
+        let val = (self.0 >> 6usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, TIMER0 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_dma(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
+    }
+    #[doc = "If 1, TIMER0 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn dbg(&self) -> bool {
+        let val = (self.0 >> 7usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, TIMER0 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_dbg(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
+    }
+}
+impl Default for Timer0 {
+    #[inline(always)]
+    fn default() -> Timer0 {
+        Timer0(0)
+    }
+}
+#[doc = "Control whether debugger, DMA, core 0 and core 1 can access TIMER1, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Timer1(pub u32);
+impl Timer1 {
+    #[doc = "If 1, and NSP is also set, TIMER1 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."]
+    #[inline(always)]
+    pub const fn nsu(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, and NSP is also set, TIMER1 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."]
+    #[inline(always)]
+    pub fn set_nsu(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[doc = "If 1, TIMER1 can be accessed from a Non-secure, Privileged context."]
+    #[inline(always)]
+    pub const fn nsp(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, TIMER1 can be accessed from a Non-secure, Privileged context."]
+    #[inline(always)]
+    pub fn set_nsp(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+    #[doc = "If 1, and SP is also set, TIMER1 can be accessed from a Secure, Unprivileged context."]
+    #[inline(always)]
+    pub const fn su(&self) -> bool {
+        let val = (self.0 >> 2usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, and SP is also set, TIMER1 can be accessed from a Secure, Unprivileged context."]
+    #[inline(always)]
+    pub fn set_su(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+    }
+    #[doc = "If 1, TIMER1 can be accessed from a Secure, Privileged context."]
+    #[inline(always)]
+    pub const fn sp(&self) -> bool {
+        let val = (self.0 >> 3usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, TIMER1 can be accessed from a Secure, Privileged context."]
+    #[inline(always)]
+    pub fn set_sp(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
+    }
+    #[doc = "If 1, TIMER1 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn core0(&self) -> bool {
+        let val = (self.0 >> 4usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, TIMER1 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_core0(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
+    }
+    #[doc = "If 1, TIMER1 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn core1(&self) -> bool {
+        let val = (self.0 >> 5usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, TIMER1 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_core1(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
+    }
+    #[doc = "If 1, TIMER1 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn dma(&self) -> bool {
+        let val = (self.0 >> 6usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, TIMER1 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_dma(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
+    }
+    #[doc = "If 1, TIMER1 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn dbg(&self) -> bool {
+        let val = (self.0 >> 7usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, TIMER1 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_dbg(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
+    }
+}
+impl Default for Timer1 {
+    #[inline(always)]
+    fn default() -> Timer1 {
+        Timer1(0)
+    }
+}
+#[doc = "Control whether debugger, DMA, core 0 and core 1 can access TRNG, and at what security/privilege levels they can do so. Defaults to Secure, Privileged processor or debug access only. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Trng(pub u32);
+impl Trng {
+    #[doc = "If 1, and NSP is also set, TRNG can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."]
+    #[inline(always)]
+    pub const fn nsu(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, and NSP is also set, TRNG can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."]
+    #[inline(always)]
+    pub fn set_nsu(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[doc = "If 1, TRNG can be accessed from a Non-secure, Privileged context."]
+    #[inline(always)]
+    pub const fn nsp(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, TRNG can be accessed from a Non-secure, Privileged context."]
+    #[inline(always)]
+    pub fn set_nsp(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+    #[doc = "If 1, and SP is also set, TRNG can be accessed from a Secure, Unprivileged context."]
+    #[inline(always)]
+    pub const fn su(&self) -> bool {
+        let val = (self.0 >> 2usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, and SP is also set, TRNG can be accessed from a Secure, Unprivileged context."]
+    #[inline(always)]
+    pub fn set_su(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+    }
+    #[doc = "If 1, TRNG can be accessed from a Secure, Privileged context."]
+    #[inline(always)]
+    pub const fn sp(&self) -> bool {
+        let val = (self.0 >> 3usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, TRNG can be accessed from a Secure, Privileged context."]
+    #[inline(always)]
+    pub fn set_sp(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
+    }
+    #[doc = "If 1, TRNG can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn core0(&self) -> bool {
+        let val = (self.0 >> 4usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, TRNG can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_core0(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
+    }
+    #[doc = "If 1, TRNG can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn core1(&self) -> bool {
+        let val = (self.0 >> 5usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, TRNG can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_core1(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
+    }
+    #[doc = "If 1, TRNG can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn dma(&self) -> bool {
+        let val = (self.0 >> 6usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, TRNG can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_dma(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
+    }
+    #[doc = "If 1, TRNG can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn dbg(&self) -> bool {
+        let val = (self.0 >> 7usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, TRNG can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_dbg(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
+    }
+}
+impl Default for Trng {
+    #[inline(always)]
+    fn default() -> Trng {
+        Trng(0)
+    }
+}
+#[doc = "Control whether debugger, DMA, core 0 and core 1 can access UART0, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Uart0(pub u32);
+impl Uart0 {
+    #[doc = "If 1, and NSP is also set, UART0 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."]
+    #[inline(always)]
+    pub const fn nsu(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, and NSP is also set, UART0 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."]
+    #[inline(always)]
+    pub fn set_nsu(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[doc = "If 1, UART0 can be accessed from a Non-secure, Privileged context."]
+    #[inline(always)]
+    pub const fn nsp(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, UART0 can be accessed from a Non-secure, Privileged context."]
+    #[inline(always)]
+    pub fn set_nsp(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+    #[doc = "If 1, and SP is also set, UART0 can be accessed from a Secure, Unprivileged context."]
+    #[inline(always)]
+    pub const fn su(&self) -> bool {
+        let val = (self.0 >> 2usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, and SP is also set, UART0 can be accessed from a Secure, Unprivileged context."]
+    #[inline(always)]
+    pub fn set_su(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+    }
+    #[doc = "If 1, UART0 can be accessed from a Secure, Privileged context."]
+    #[inline(always)]
+    pub const fn sp(&self) -> bool {
+        let val = (self.0 >> 3usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, UART0 can be accessed from a Secure, Privileged context."]
+    #[inline(always)]
+    pub fn set_sp(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
+    }
+    #[doc = "If 1, UART0 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn core0(&self) -> bool {
+        let val = (self.0 >> 4usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, UART0 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_core0(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
+    }
+    #[doc = "If 1, UART0 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn core1(&self) -> bool {
+        let val = (self.0 >> 5usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, UART0 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_core1(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
+    }
+    #[doc = "If 1, UART0 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn dma(&self) -> bool {
+        let val = (self.0 >> 6usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, UART0 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_dma(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
+    }
+    #[doc = "If 1, UART0 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn dbg(&self) -> bool {
+        let val = (self.0 >> 7usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, UART0 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_dbg(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
+    }
+}
+impl Default for Uart0 {
+    #[inline(always)]
+    fn default() -> Uart0 {
+        Uart0(0)
+    }
+}
+#[doc = "Control whether debugger, DMA, core 0 and core 1 can access UART1, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Uart1(pub u32);
+impl Uart1 {
+    #[doc = "If 1, and NSP is also set, UART1 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."]
+    #[inline(always)]
+    pub const fn nsu(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, and NSP is also set, UART1 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."]
+    #[inline(always)]
+    pub fn set_nsu(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[doc = "If 1, UART1 can be accessed from a Non-secure, Privileged context."]
+    #[inline(always)]
+    pub const fn nsp(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, UART1 can be accessed from a Non-secure, Privileged context."]
+    #[inline(always)]
+    pub fn set_nsp(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+    #[doc = "If 1, and SP is also set, UART1 can be accessed from a Secure, Unprivileged context."]
+    #[inline(always)]
+    pub const fn su(&self) -> bool {
+        let val = (self.0 >> 2usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, and SP is also set, UART1 can be accessed from a Secure, Unprivileged context."]
+    #[inline(always)]
+    pub fn set_su(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+    }
+    #[doc = "If 1, UART1 can be accessed from a Secure, Privileged context."]
+    #[inline(always)]
+    pub const fn sp(&self) -> bool {
+        let val = (self.0 >> 3usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, UART1 can be accessed from a Secure, Privileged context."]
+    #[inline(always)]
+    pub fn set_sp(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
+    }
+    #[doc = "If 1, UART1 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn core0(&self) -> bool {
+        let val = (self.0 >> 4usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, UART1 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_core0(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
+    }
+    #[doc = "If 1, UART1 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn core1(&self) -> bool {
+        let val = (self.0 >> 5usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, UART1 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_core1(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
+    }
+    #[doc = "If 1, UART1 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn dma(&self) -> bool {
+        let val = (self.0 >> 6usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, UART1 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_dma(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
+    }
+    #[doc = "If 1, UART1 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn dbg(&self) -> bool {
+        let val = (self.0 >> 7usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, UART1 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_dbg(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
+    }
+}
+impl Default for Uart1 {
+    #[inline(always)]
+    fn default() -> Uart1 {
+        Uart1(0)
+    }
+}
+#[doc = "Control whether debugger, DMA, core 0 and core 1 can access USBCTRL, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Usbctrl(pub u32);
+impl Usbctrl {
+    #[doc = "If 1, and NSP is also set, USBCTRL can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."]
+    #[inline(always)]
+    pub const fn nsu(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, and NSP is also set, USBCTRL can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."]
+    #[inline(always)]
+    pub fn set_nsu(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[doc = "If 1, USBCTRL can be accessed from a Non-secure, Privileged context."]
+    #[inline(always)]
+    pub const fn nsp(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, USBCTRL can be accessed from a Non-secure, Privileged context."]
+    #[inline(always)]
+    pub fn set_nsp(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+    #[doc = "If 1, and SP is also set, USBCTRL can be accessed from a Secure, Unprivileged context."]
+    #[inline(always)]
+    pub const fn su(&self) -> bool {
+        let val = (self.0 >> 2usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, and SP is also set, USBCTRL can be accessed from a Secure, Unprivileged context."]
+    #[inline(always)]
+    pub fn set_su(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+    }
+    #[doc = "If 1, USBCTRL can be accessed from a Secure, Privileged context."]
+    #[inline(always)]
+    pub const fn sp(&self) -> bool {
+        let val = (self.0 >> 3usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, USBCTRL can be accessed from a Secure, Privileged context."]
+    #[inline(always)]
+    pub fn set_sp(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
+    }
+    #[doc = "If 1, USBCTRL can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn core0(&self) -> bool {
+        let val = (self.0 >> 4usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, USBCTRL can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_core0(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
+    }
+    #[doc = "If 1, USBCTRL can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn core1(&self) -> bool {
+        let val = (self.0 >> 5usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, USBCTRL can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_core1(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
+    }
+    #[doc = "If 1, USBCTRL can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn dma(&self) -> bool {
+        let val = (self.0 >> 6usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, USBCTRL can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_dma(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
+    }
+    #[doc = "If 1, USBCTRL can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn dbg(&self) -> bool {
+        let val = (self.0 >> 7usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, USBCTRL can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_dbg(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
+    }
+}
+impl Default for Usbctrl {
+    #[inline(always)]
+    fn default() -> Usbctrl {
+        Usbctrl(0)
+    }
+}
+#[doc = "Control whether debugger, DMA, core 0 and core 1 can access WATCHDOG, and at what security/privilege levels they can do so. Defaults to Secure, Privileged processor or debug access only. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Watchdog(pub u32);
+impl Watchdog {
+    #[doc = "If 1, and NSP is also set, WATCHDOG can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."]
+    #[inline(always)]
+    pub const fn nsu(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, and NSP is also set, WATCHDOG can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."]
+    #[inline(always)]
+    pub fn set_nsu(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[doc = "If 1, WATCHDOG can be accessed from a Non-secure, Privileged context."]
+    #[inline(always)]
+    pub const fn nsp(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, WATCHDOG can be accessed from a Non-secure, Privileged context."]
+    #[inline(always)]
+    pub fn set_nsp(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+    #[doc = "If 1, and SP is also set, WATCHDOG can be accessed from a Secure, Unprivileged context."]
+    #[inline(always)]
+    pub const fn su(&self) -> bool {
+        let val = (self.0 >> 2usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, and SP is also set, WATCHDOG can be accessed from a Secure, Unprivileged context."]
+    #[inline(always)]
+    pub fn set_su(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+    }
+    #[doc = "If 1, WATCHDOG can be accessed from a Secure, Privileged context."]
+    #[inline(always)]
+    pub const fn sp(&self) -> bool {
+        let val = (self.0 >> 3usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, WATCHDOG can be accessed from a Secure, Privileged context."]
+    #[inline(always)]
+    pub fn set_sp(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
+    }
+    #[doc = "If 1, WATCHDOG can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn core0(&self) -> bool {
+        let val = (self.0 >> 4usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, WATCHDOG can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_core0(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
+    }
+    #[doc = "If 1, WATCHDOG can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn core1(&self) -> bool {
+        let val = (self.0 >> 5usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, WATCHDOG can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_core1(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
+    }
+    #[doc = "If 1, WATCHDOG can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn dma(&self) -> bool {
+        let val = (self.0 >> 6usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, WATCHDOG can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_dma(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
+    }
+    #[doc = "If 1, WATCHDOG can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn dbg(&self) -> bool {
+        let val = (self.0 >> 7usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, WATCHDOG can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_dbg(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
+    }
+}
+impl Default for Watchdog {
+    #[inline(always)]
+    fn default() -> Watchdog {
+        Watchdog(0)
+    }
+}
+#[doc = "Control whether debugger, DMA, core 0 and core 1 can access XIP_AUX, and at what security/privilege levels they can do so. Defaults to Secure, Privileged access only. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct XipAux(pub u32);
+impl XipAux {
+    #[doc = "If 1, and NSP is also set, XIP_AUX can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."]
+    #[inline(always)]
+    pub const fn nsu(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, and NSP is also set, XIP_AUX can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."]
+    #[inline(always)]
+    pub fn set_nsu(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[doc = "If 1, XIP_AUX can be accessed from a Non-secure, Privileged context."]
+    #[inline(always)]
+    pub const fn nsp(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, XIP_AUX can be accessed from a Non-secure, Privileged context."]
+    #[inline(always)]
+    pub fn set_nsp(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+    #[doc = "If 1, and SP is also set, XIP_AUX can be accessed from a Secure, Unprivileged context."]
+    #[inline(always)]
+    pub const fn su(&self) -> bool {
+        let val = (self.0 >> 2usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, and SP is also set, XIP_AUX can be accessed from a Secure, Unprivileged context."]
+    #[inline(always)]
+    pub fn set_su(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+    }
+    #[doc = "If 1, XIP_AUX can be accessed from a Secure, Privileged context."]
+    #[inline(always)]
+    pub const fn sp(&self) -> bool {
+        let val = (self.0 >> 3usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, XIP_AUX can be accessed from a Secure, Privileged context."]
+    #[inline(always)]
+    pub fn set_sp(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
+    }
+    #[doc = "If 1, XIP_AUX can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn core0(&self) -> bool {
+        let val = (self.0 >> 4usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, XIP_AUX can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_core0(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
+    }
+    #[doc = "If 1, XIP_AUX can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn core1(&self) -> bool {
+        let val = (self.0 >> 5usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, XIP_AUX can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_core1(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
+    }
+    #[doc = "If 1, XIP_AUX can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn dma(&self) -> bool {
+        let val = (self.0 >> 6usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, XIP_AUX can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_dma(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
+    }
+    #[doc = "If 1, XIP_AUX can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn dbg(&self) -> bool {
+        let val = (self.0 >> 7usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, XIP_AUX can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_dbg(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
+    }
+}
+impl Default for XipAux {
+    #[inline(always)]
+    fn default() -> XipAux {
+        XipAux(0)
+    }
+}
+#[doc = "Control whether debugger, DMA, core 0 and core 1 can access XIP_CTRL, and at what security/privilege levels they can do so. Defaults to Secure, Privileged processor or debug access only. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct XipCtrl(pub u32);
+impl XipCtrl {
+    #[doc = "If 1, and NSP is also set, XIP_CTRL can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."]
+    #[inline(always)]
+    pub const fn nsu(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, and NSP is also set, XIP_CTRL can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."]
+    #[inline(always)]
+    pub fn set_nsu(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[doc = "If 1, XIP_CTRL can be accessed from a Non-secure, Privileged context."]
+    #[inline(always)]
+    pub const fn nsp(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, XIP_CTRL can be accessed from a Non-secure, Privileged context."]
+    #[inline(always)]
+    pub fn set_nsp(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+    #[doc = "If 1, and SP is also set, XIP_CTRL can be accessed from a Secure, Unprivileged context."]
+    #[inline(always)]
+    pub const fn su(&self) -> bool {
+        let val = (self.0 >> 2usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, and SP is also set, XIP_CTRL can be accessed from a Secure, Unprivileged context."]
+    #[inline(always)]
+    pub fn set_su(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+    }
+    #[doc = "If 1, XIP_CTRL can be accessed from a Secure, Privileged context."]
+    #[inline(always)]
+    pub const fn sp(&self) -> bool {
+        let val = (self.0 >> 3usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, XIP_CTRL can be accessed from a Secure, Privileged context."]
+    #[inline(always)]
+    pub fn set_sp(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
+    }
+    #[doc = "If 1, XIP_CTRL can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn core0(&self) -> bool {
+        let val = (self.0 >> 4usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, XIP_CTRL can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_core0(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
+    }
+    #[doc = "If 1, XIP_CTRL can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn core1(&self) -> bool {
+        let val = (self.0 >> 5usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, XIP_CTRL can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_core1(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
+    }
+    #[doc = "If 1, XIP_CTRL can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn dma(&self) -> bool {
+        let val = (self.0 >> 6usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, XIP_CTRL can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_dma(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
+    }
+    #[doc = "If 1, XIP_CTRL can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn dbg(&self) -> bool {
+        let val = (self.0 >> 7usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, XIP_CTRL can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_dbg(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
+    }
+}
+impl Default for XipCtrl {
+    #[inline(always)]
+    fn default() -> XipCtrl {
+        XipCtrl(0)
+    }
+}
+#[doc = "Control whether debugger, DMA, core 0 and core 1 can access XIP_MAIN, and at what security/privilege levels they can do so. Defaults to fully open access. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct XipMain(pub u32);
+impl XipMain {
+    #[doc = "If 1, and NSP is also set, XIP_MAIN can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."]
+    #[inline(always)]
+    pub const fn nsu(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, and NSP is also set, XIP_MAIN can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."]
+    #[inline(always)]
+    pub fn set_nsu(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[doc = "If 1, XIP_MAIN can be accessed from a Non-secure, Privileged context."]
+    #[inline(always)]
+    pub const fn nsp(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, XIP_MAIN can be accessed from a Non-secure, Privileged context."]
+    #[inline(always)]
+    pub fn set_nsp(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+    #[doc = "If 1, and SP is also set, XIP_MAIN can be accessed from a Secure, Unprivileged context."]
+    #[inline(always)]
+    pub const fn su(&self) -> bool {
+        let val = (self.0 >> 2usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, and SP is also set, XIP_MAIN can be accessed from a Secure, Unprivileged context."]
+    #[inline(always)]
+    pub fn set_su(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+    }
+    #[doc = "If 1, XIP_MAIN can be accessed from a Secure, Privileged context."]
+    #[inline(always)]
+    pub const fn sp(&self) -> bool {
+        let val = (self.0 >> 3usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, XIP_MAIN can be accessed from a Secure, Privileged context."]
+    #[inline(always)]
+    pub fn set_sp(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
+    }
+    #[doc = "If 1, XIP_MAIN can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn core0(&self) -> bool {
+        let val = (self.0 >> 4usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, XIP_MAIN can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_core0(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
+    }
+    #[doc = "If 1, XIP_MAIN can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn core1(&self) -> bool {
+        let val = (self.0 >> 5usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, XIP_MAIN can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_core1(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
+    }
+    #[doc = "If 1, XIP_MAIN can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn dma(&self) -> bool {
+        let val = (self.0 >> 6usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, XIP_MAIN can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_dma(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
+    }
+    #[doc = "If 1, XIP_MAIN can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn dbg(&self) -> bool {
+        let val = (self.0 >> 7usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, XIP_MAIN can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_dbg(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
+    }
+}
+impl Default for XipMain {
+    #[inline(always)]
+    fn default() -> XipMain {
+        XipMain(0)
+    }
+}
+#[doc = "Control whether debugger, DMA, core 0 and core 1 can access XIP_QMI, and at what security/privilege levels they can do so. Defaults to Secure, Privileged processor or debug access only. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct XipQmi(pub u32);
+impl XipQmi {
+    #[doc = "If 1, and NSP is also set, XIP_QMI can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."]
+    #[inline(always)]
+    pub const fn nsu(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, and NSP is also set, XIP_QMI can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."]
+    #[inline(always)]
+    pub fn set_nsu(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[doc = "If 1, XIP_QMI can be accessed from a Non-secure, Privileged context."]
+    #[inline(always)]
+    pub const fn nsp(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, XIP_QMI can be accessed from a Non-secure, Privileged context."]
+    #[inline(always)]
+    pub fn set_nsp(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+    #[doc = "If 1, and SP is also set, XIP_QMI can be accessed from a Secure, Unprivileged context."]
+    #[inline(always)]
+    pub const fn su(&self) -> bool {
+        let val = (self.0 >> 2usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, and SP is also set, XIP_QMI can be accessed from a Secure, Unprivileged context."]
+    #[inline(always)]
+    pub fn set_su(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+    }
+    #[doc = "If 1, XIP_QMI can be accessed from a Secure, Privileged context."]
+    #[inline(always)]
+    pub const fn sp(&self) -> bool {
+        let val = (self.0 >> 3usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, XIP_QMI can be accessed from a Secure, Privileged context."]
+    #[inline(always)]
+    pub fn set_sp(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
+    }
+    #[doc = "If 1, XIP_QMI can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn core0(&self) -> bool {
+        let val = (self.0 >> 4usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, XIP_QMI can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_core0(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
+    }
+    #[doc = "If 1, XIP_QMI can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn core1(&self) -> bool {
+        let val = (self.0 >> 5usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, XIP_QMI can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_core1(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
+    }
+    #[doc = "If 1, XIP_QMI can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn dma(&self) -> bool {
+        let val = (self.0 >> 6usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, XIP_QMI can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_dma(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
+    }
+    #[doc = "If 1, XIP_QMI can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn dbg(&self) -> bool {
+        let val = (self.0 >> 7usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, XIP_QMI can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_dbg(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
+    }
+}
+impl Default for XipQmi {
+    #[inline(always)]
+    fn default() -> XipQmi {
+        XipQmi(0)
+    }
+}
+#[doc = "Control whether debugger, DMA, core 0 and core 1 can access XOSC, and at what security/privilege levels they can do so. Defaults to Secure, Privileged processor or debug access only. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Xosc(pub u32);
+impl Xosc {
+    #[doc = "If 1, and NSP is also set, XOSC can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."]
+    #[inline(always)]
+    pub const fn nsu(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, and NSP is also set, XOSC can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."]
+    #[inline(always)]
+    pub fn set_nsu(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[doc = "If 1, XOSC can be accessed from a Non-secure, Privileged context."]
+    #[inline(always)]
+    pub const fn nsp(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, XOSC can be accessed from a Non-secure, Privileged context."]
+    #[inline(always)]
+    pub fn set_nsp(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+    #[doc = "If 1, and SP is also set, XOSC can be accessed from a Secure, Unprivileged context."]
+    #[inline(always)]
+    pub const fn su(&self) -> bool {
+        let val = (self.0 >> 2usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, and SP is also set, XOSC can be accessed from a Secure, Unprivileged context."]
+    #[inline(always)]
+    pub fn set_su(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+    }
+    #[doc = "If 1, XOSC can be accessed from a Secure, Privileged context."]
+    #[inline(always)]
+    pub const fn sp(&self) -> bool {
+        let val = (self.0 >> 3usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, XOSC can be accessed from a Secure, Privileged context."]
+    #[inline(always)]
+    pub fn set_sp(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
+    }
+    #[doc = "If 1, XOSC can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn core0(&self) -> bool {
+        let val = (self.0 >> 4usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, XOSC can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_core0(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
+    }
+    #[doc = "If 1, XOSC can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn core1(&self) -> bool {
+        let val = (self.0 >> 5usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, XOSC can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_core1(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
+    }
+    #[doc = "If 1, XOSC can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn dma(&self) -> bool {
+        let val = (self.0 >> 6usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, XOSC can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_dma(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
+    }
+    #[doc = "If 1, XOSC can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub const fn dbg(&self) -> bool {
+        let val = (self.0 >> 7usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, XOSC can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
+    #[inline(always)]
+    pub fn set_dbg(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
+    }
+}
+impl Default for Xosc {
+    #[inline(always)]
+    fn default() -> Xosc {
+        Xosc(0)
+    }
+}
diff --git a/src/rp2350/adc.rs b/src/rp2350/adc.rs
new file mode 100644
index 00000000..1027f21b
--- /dev/null
+++ b/src/rp2350/adc.rs
@@ -0,0 +1,63 @@
+#[doc = "Control and data interface to SAR ADC"]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Adc {
+    ptr: *mut u8,
+}
+unsafe impl Send for Adc {}
+unsafe impl Sync for Adc {}
+impl Adc {
+    #[inline(always)]
+    pub const unsafe fn from_ptr(ptr: *mut ()) -> Self {
+        Self { ptr: ptr as _ }
+    }
+    #[inline(always)]
+    pub const fn as_ptr(&self) -> *mut () {
+        self.ptr as _
+    }
+    #[doc = "ADC Control and Status"]
+    #[inline(always)]
+    pub const fn cs(self) -> crate::common::Reg<regs::Cs, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(0usize) as _) }
+    }
+    #[doc = "Result of most recent ADC conversion"]
+    #[inline(always)]
+    pub const fn result(self) -> crate::common::Reg<regs::Result, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(4usize) as _) }
+    }
+    #[doc = "FIFO control and status"]
+    #[inline(always)]
+    pub const fn fcs(self) -> crate::common::Reg<regs::Fcs, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(8usize) as _) }
+    }
+    #[doc = "Conversion result FIFO"]
+    #[inline(always)]
+    pub const fn fifo(self) -> crate::common::Reg<regs::Fifo, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(12usize) as _) }
+    }
+    #[doc = "Clock divider. If non-zero, CS_START_MANY will start conversions at regular intervals rather than back-to-back. The divider is reset when either of these fields are written. Total period is 1 + INT + FRAC / 256"]
+    #[inline(always)]
+    pub const fn div(self) -> crate::common::Reg<regs::Div, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(16usize) as _) }
+    }
+    #[doc = "Raw Interrupts"]
+    #[inline(always)]
+    pub const fn intr(self) -> crate::common::Reg<regs::Int, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(20usize) as _) }
+    }
+    #[doc = "Interrupt Enable"]
+    #[inline(always)]
+    pub const fn inte(self) -> crate::common::Reg<regs::Int, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(24usize) as _) }
+    }
+    #[doc = "Interrupt Force"]
+    #[inline(always)]
+    pub const fn intf(self) -> crate::common::Reg<regs::Int, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(28usize) as _) }
+    }
+    #[doc = "Interrupt status after masking & forcing"]
+    #[inline(always)]
+    pub const fn ints(self) -> crate::common::Reg<regs::Int, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(32usize) as _) }
+    }
+}
+pub mod regs;
diff --git a/src/rp2350/adc/regs.rs b/src/rp2350/adc/regs.rs
new file mode 100644
index 00000000..0cf02134
--- /dev/null
+++ b/src/rp2350/adc/regs.rs
@@ -0,0 +1,339 @@
+#[doc = "ADC Control and Status"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Cs(pub u32);
+impl Cs {
+    #[doc = "Power on ADC and enable its clock. 1 - enabled. 0 - disabled."]
+    #[inline(always)]
+    pub const fn en(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Power on ADC and enable its clock. 1 - enabled. 0 - disabled."]
+    #[inline(always)]
+    pub fn set_en(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[doc = "Power on temperature sensor. 1 - enabled. 0 - disabled."]
+    #[inline(always)]
+    pub const fn ts_en(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Power on temperature sensor. 1 - enabled. 0 - disabled."]
+    #[inline(always)]
+    pub fn set_ts_en(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+    #[doc = "Start a single conversion. Self-clearing. Ignored if start_many is asserted."]
+    #[inline(always)]
+    pub const fn start_once(&self) -> bool {
+        let val = (self.0 >> 2usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Start a single conversion. Self-clearing. Ignored if start_many is asserted."]
+    #[inline(always)]
+    pub fn set_start_once(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+    }
+    #[doc = "Continuously perform conversions whilst this bit is 1. A new conversion will start immediately after the previous finishes."]
+    #[inline(always)]
+    pub const fn start_many(&self) -> bool {
+        let val = (self.0 >> 3usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Continuously perform conversions whilst this bit is 1. A new conversion will start immediately after the previous finishes."]
+    #[inline(always)]
+    pub fn set_start_many(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
+    }
+    #[doc = "1 if the ADC is ready to start a new conversion. Implies any previous conversion has completed. 0 whilst conversion in progress."]
+    #[inline(always)]
+    pub const fn ready(&self) -> bool {
+        let val = (self.0 >> 8usize) & 0x01;
+        val != 0
+    }
+    #[doc = "1 if the ADC is ready to start a new conversion. Implies any previous conversion has completed. 0 whilst conversion in progress."]
+    #[inline(always)]
+    pub fn set_ready(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
+    }
+    #[doc = "The most recent ADC conversion encountered an error; result is undefined or noisy."]
+    #[inline(always)]
+    pub const fn err(&self) -> bool {
+        let val = (self.0 >> 9usize) & 0x01;
+        val != 0
+    }
+    #[doc = "The most recent ADC conversion encountered an error; result is undefined or noisy."]
+    #[inline(always)]
+    pub fn set_err(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
+    }
+    #[doc = "Some past ADC conversion encountered an error. Write 1 to clear."]
+    #[inline(always)]
+    pub const fn err_sticky(&self) -> bool {
+        let val = (self.0 >> 10usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Some past ADC conversion encountered an error. Write 1 to clear."]
+    #[inline(always)]
+    pub fn set_err_sticky(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize);
+    }
+    #[doc = "Select analog mux input. Updated automatically in round-robin mode. This is corrected for the package option so only ADC channels which are bonded are available, and in the correct order"]
+    #[inline(always)]
+    pub const fn ainsel(&self) -> u8 {
+        let val = (self.0 >> 12usize) & 0x0f;
+        val as u8
+    }
+    #[doc = "Select analog mux input. Updated automatically in round-robin mode. This is corrected for the package option so only ADC channels which are bonded are available, and in the correct order"]
+    #[inline(always)]
+    pub fn set_ainsel(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x0f << 12usize)) | (((val as u32) & 0x0f) << 12usize);
+    }
+    #[doc = "Round-robin sampling. 1 bit per channel. Set all bits to 0 to disable. Otherwise, the ADC will cycle through each enabled channel in a round-robin fashion. The first channel to be sampled will be the one currently indicated by AINSEL. AINSEL will be updated after each conversion with the newly-selected channel."]
+    #[inline(always)]
+    pub const fn rrobin(&self) -> u16 {
+        let val = (self.0 >> 16usize) & 0x01ff;
+        val as u16
+    }
+    #[doc = "Round-robin sampling. 1 bit per channel. Set all bits to 0 to disable. Otherwise, the ADC will cycle through each enabled channel in a round-robin fashion. The first channel to be sampled will be the one currently indicated by AINSEL. AINSEL will be updated after each conversion with the newly-selected channel."]
+    #[inline(always)]
+    pub fn set_rrobin(&mut self, val: u16) {
+        self.0 = (self.0 & !(0x01ff << 16usize)) | (((val as u32) & 0x01ff) << 16usize);
+    }
+}
+impl Default for Cs {
+    #[inline(always)]
+    fn default() -> Cs {
+        Cs(0)
+    }
+}
+#[doc = "Clock divider. If non-zero, CS_START_MANY will start conversions at regular intervals rather than back-to-back. The divider is reset when either of these fields are written. Total period is 1 + INT + FRAC / 256"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Div(pub u32);
+impl Div {
+    #[doc = "Fractional part of clock divisor. First-order delta-sigma."]
+    #[inline(always)]
+    pub const fn frac(&self) -> u8 {
+        let val = (self.0 >> 0usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Fractional part of clock divisor. First-order delta-sigma."]
+    #[inline(always)]
+    pub fn set_frac(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize);
+    }
+    #[doc = "Integer part of clock divisor."]
+    #[inline(always)]
+    pub const fn int(&self) -> u16 {
+        let val = (self.0 >> 8usize) & 0xffff;
+        val as u16
+    }
+    #[doc = "Integer part of clock divisor."]
+    #[inline(always)]
+    pub fn set_int(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 8usize)) | (((val as u32) & 0xffff) << 8usize);
+    }
+}
+impl Default for Div {
+    #[inline(always)]
+    fn default() -> Div {
+        Div(0)
+    }
+}
+#[doc = "FIFO control and status"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Fcs(pub u32);
+impl Fcs {
+    #[doc = "If 1: write result to the FIFO after each conversion."]
+    #[inline(always)]
+    pub const fn en(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1: write result to the FIFO after each conversion."]
+    #[inline(always)]
+    pub fn set_en(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[doc = "If 1: FIFO results are right-shifted to be one byte in size. Enables DMA to byte buffers."]
+    #[inline(always)]
+    pub const fn shift(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1: FIFO results are right-shifted to be one byte in size. Enables DMA to byte buffers."]
+    #[inline(always)]
+    pub fn set_shift(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+    #[doc = "If 1: conversion error bit appears in the FIFO alongside the result"]
+    #[inline(always)]
+    pub const fn err(&self) -> bool {
+        let val = (self.0 >> 2usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1: conversion error bit appears in the FIFO alongside the result"]
+    #[inline(always)]
+    pub fn set_err(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+    }
+    #[doc = "If 1: assert DMA requests when FIFO contains data"]
+    #[inline(always)]
+    pub const fn dreq_en(&self) -> bool {
+        let val = (self.0 >> 3usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1: assert DMA requests when FIFO contains data"]
+    #[inline(always)]
+    pub fn set_dreq_en(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
+    }
+    #[inline(always)]
+    pub const fn empty(&self) -> bool {
+        let val = (self.0 >> 8usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_empty(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
+    }
+    #[inline(always)]
+    pub const fn full(&self) -> bool {
+        let val = (self.0 >> 9usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_full(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
+    }
+    #[doc = "1 if the FIFO has been underflowed. Write 1 to clear."]
+    #[inline(always)]
+    pub const fn under(&self) -> bool {
+        let val = (self.0 >> 10usize) & 0x01;
+        val != 0
+    }
+    #[doc = "1 if the FIFO has been underflowed. Write 1 to clear."]
+    #[inline(always)]
+    pub fn set_under(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize);
+    }
+    #[doc = "1 if the FIFO has been overflowed. Write 1 to clear."]
+    #[inline(always)]
+    pub const fn over(&self) -> bool {
+        let val = (self.0 >> 11usize) & 0x01;
+        val != 0
+    }
+    #[doc = "1 if the FIFO has been overflowed. Write 1 to clear."]
+    #[inline(always)]
+    pub fn set_over(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
+    }
+    #[doc = "The number of conversion results currently waiting in the FIFO"]
+    #[inline(always)]
+    pub const fn level(&self) -> u8 {
+        let val = (self.0 >> 16usize) & 0x0f;
+        val as u8
+    }
+    #[doc = "The number of conversion results currently waiting in the FIFO"]
+    #[inline(always)]
+    pub fn set_level(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x0f << 16usize)) | (((val as u32) & 0x0f) << 16usize);
+    }
+    #[doc = "DREQ/IRQ asserted when level >= threshold"]
+    #[inline(always)]
+    pub const fn thresh(&self) -> u8 {
+        let val = (self.0 >> 24usize) & 0x0f;
+        val as u8
+    }
+    #[doc = "DREQ/IRQ asserted when level >= threshold"]
+    #[inline(always)]
+    pub fn set_thresh(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x0f << 24usize)) | (((val as u32) & 0x0f) << 24usize);
+    }
+}
+impl Default for Fcs {
+    #[inline(always)]
+    fn default() -> Fcs {
+        Fcs(0)
+    }
+}
+#[doc = "Conversion result FIFO"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Fifo(pub u32);
+impl Fifo {
+    #[inline(always)]
+    pub const fn val(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0x0fff;
+        val as u16
+    }
+    #[inline(always)]
+    pub fn set_val(&mut self, val: u16) {
+        self.0 = (self.0 & !(0x0fff << 0usize)) | (((val as u32) & 0x0fff) << 0usize);
+    }
+    #[doc = "1 if this particular sample experienced a conversion error. Remains in the same location if the sample is shifted."]
+    #[inline(always)]
+    pub const fn err(&self) -> bool {
+        let val = (self.0 >> 15usize) & 0x01;
+        val != 0
+    }
+    #[doc = "1 if this particular sample experienced a conversion error. Remains in the same location if the sample is shifted."]
+    #[inline(always)]
+    pub fn set_err(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize);
+    }
+}
+impl Default for Fifo {
+    #[inline(always)]
+    fn default() -> Fifo {
+        Fifo(0)
+    }
+}
+#[doc = "Interrupt Enable"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Int(pub u32);
+impl Int {
+    #[doc = "Triggered when the sample FIFO reaches a certain level. This level can be programmed via the FCS_THRESH field."]
+    #[inline(always)]
+    pub const fn fifo(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Triggered when the sample FIFO reaches a certain level. This level can be programmed via the FCS_THRESH field."]
+    #[inline(always)]
+    pub fn set_fifo(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+}
+impl Default for Int {
+    #[inline(always)]
+    fn default() -> Int {
+        Int(0)
+    }
+}
+#[doc = "Result of most recent ADC conversion"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Result(pub u32);
+impl Result {
+    #[inline(always)]
+    pub const fn result(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0x0fff;
+        val as u16
+    }
+    #[inline(always)]
+    pub fn set_result(&mut self, val: u16) {
+        self.0 = (self.0 & !(0x0fff << 0usize)) | (((val as u32) & 0x0fff) << 0usize);
+    }
+}
+impl Default for Result {
+    #[inline(always)]
+    fn default() -> Result {
+        Result(0)
+    }
+}
diff --git a/src/rp2350/bootram.rs b/src/rp2350/bootram.rs
new file mode 100644
index 00000000..814cd79e
--- /dev/null
+++ b/src/rp2350/bootram.rs
@@ -0,0 +1,73 @@
+#[doc = "Additional registers mapped adjacent to the bootram, for use by the bootrom."]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Bootram {
+    ptr: *mut u8,
+}
+unsafe impl Send for Bootram {}
+unsafe impl Sync for Bootram {}
+impl Bootram {
+    #[inline(always)]
+    pub const unsafe fn from_ptr(ptr: *mut ()) -> Self {
+        Self { ptr: ptr as _ }
+    }
+    #[inline(always)]
+    pub const fn as_ptr(&self) -> *mut () {
+        self.ptr as _
+    }
+    #[doc = "This registers always ORs writes into its current contents. Once a bit is set, it can only be cleared by a reset."]
+    #[inline(always)]
+    pub const fn write_once0(self) -> crate::common::Reg<u32, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(2048usize) as _) }
+    }
+    #[doc = "This registers always ORs writes into its current contents. Once a bit is set, it can only be cleared by a reset."]
+    #[inline(always)]
+    pub const fn write_once1(self) -> crate::common::Reg<u32, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(2052usize) as _) }
+    }
+    #[doc = "Bootlock status register. 1=unclaimed, 0=claimed. These locks function identically to the SIO spinlocks, but are reserved for bootrom use."]
+    #[inline(always)]
+    pub const fn bootlock_stat(self) -> crate::common::Reg<regs::BootlockStat, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(2056usize) as _) }
+    }
+    #[doc = "Read to claim and check. Write to unclaim. The value returned on successful claim is 1 << n, and on failed claim is zero."]
+    #[inline(always)]
+    pub const fn bootlock0(self) -> crate::common::Reg<u32, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(2060usize) as _) }
+    }
+    #[doc = "Read to claim and check. Write to unclaim. The value returned on successful claim is 1 << n, and on failed claim is zero."]
+    #[inline(always)]
+    pub const fn bootlock1(self) -> crate::common::Reg<u32, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(2064usize) as _) }
+    }
+    #[doc = "Read to claim and check. Write to unclaim. The value returned on successful claim is 1 << n, and on failed claim is zero."]
+    #[inline(always)]
+    pub const fn bootlock2(self) -> crate::common::Reg<u32, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(2068usize) as _) }
+    }
+    #[doc = "Read to claim and check. Write to unclaim. The value returned on successful claim is 1 << n, and on failed claim is zero."]
+    #[inline(always)]
+    pub const fn bootlock3(self) -> crate::common::Reg<u32, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(2072usize) as _) }
+    }
+    #[doc = "Read to claim and check. Write to unclaim. The value returned on successful claim is 1 << n, and on failed claim is zero."]
+    #[inline(always)]
+    pub const fn bootlock4(self) -> crate::common::Reg<u32, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(2076usize) as _) }
+    }
+    #[doc = "Read to claim and check. Write to unclaim. The value returned on successful claim is 1 << n, and on failed claim is zero."]
+    #[inline(always)]
+    pub const fn bootlock5(self) -> crate::common::Reg<u32, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(2080usize) as _) }
+    }
+    #[doc = "Read to claim and check. Write to unclaim. The value returned on successful claim is 1 << n, and on failed claim is zero."]
+    #[inline(always)]
+    pub const fn bootlock6(self) -> crate::common::Reg<u32, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(2084usize) as _) }
+    }
+    #[doc = "Read to claim and check. Write to unclaim. The value returned on successful claim is 1 << n, and on failed claim is zero."]
+    #[inline(always)]
+    pub const fn bootlock7(self) -> crate::common::Reg<u32, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(2088usize) as _) }
+    }
+}
+pub mod regs;
diff --git a/src/rp2350/bootram/regs.rs b/src/rp2350/bootram/regs.rs
new file mode 100644
index 00000000..590f7eb7
--- /dev/null
+++ b/src/rp2350/bootram/regs.rs
@@ -0,0 +1,21 @@
+#[doc = "Bootlock status register. 1=unclaimed, 0=claimed. These locks function identically to the SIO spinlocks, but are reserved for bootrom use."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct BootlockStat(pub u32);
+impl BootlockStat {
+    #[inline(always)]
+    pub const fn bootlock_stat(&self) -> u8 {
+        let val = (self.0 >> 0usize) & 0xff;
+        val as u8
+    }
+    #[inline(always)]
+    pub fn set_bootlock_stat(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize);
+    }
+}
+impl Default for BootlockStat {
+    #[inline(always)]
+    fn default() -> BootlockStat {
+        BootlockStat(0)
+    }
+}
diff --git a/src/rp2350/busctrl.rs b/src/rp2350/busctrl.rs
new file mode 100644
index 00000000..851d4575
--- /dev/null
+++ b/src/rp2350/busctrl.rs
@@ -0,0 +1,48 @@
+#[doc = "Register block for busfabric control signals and performance counters"]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Busctrl {
+    ptr: *mut u8,
+}
+unsafe impl Send for Busctrl {}
+unsafe impl Sync for Busctrl {}
+impl Busctrl {
+    #[inline(always)]
+    pub const unsafe fn from_ptr(ptr: *mut ()) -> Self {
+        Self { ptr: ptr as _ }
+    }
+    #[inline(always)]
+    pub const fn as_ptr(&self) -> *mut () {
+        self.ptr as _
+    }
+    #[doc = "Set the priority of each master for bus arbitration."]
+    #[inline(always)]
+    pub const fn bus_priority(self) -> crate::common::Reg<regs::BusPriority, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(0usize) as _) }
+    }
+    #[doc = "Bus priority acknowledge"]
+    #[inline(always)]
+    pub const fn bus_priority_ack(
+        self,
+    ) -> crate::common::Reg<regs::BusPriorityAck, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(4usize) as _) }
+    }
+    #[doc = "Enable the performance counters. If 0, the performance counters do not increment. This can be used to precisely start/stop event sampling around the profiled section of code. The performance counters are initially disabled, to save energy."]
+    #[inline(always)]
+    pub const fn perfctr_en(self) -> crate::common::Reg<regs::PerfctrEn, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(8usize) as _) }
+    }
+    #[doc = "Bus fabric performance counter 0"]
+    #[inline(always)]
+    pub const fn perfctr(self, n: usize) -> crate::common::Reg<regs::Perfctr, crate::common::RW> {
+        assert!(n < 4usize);
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(12usize + n * 8usize) as _) }
+    }
+    #[doc = "Bus fabric performance event select for PERFCTR0"]
+    #[inline(always)]
+    pub const fn perfsel(self, n: usize) -> crate::common::Reg<regs::Perfsel, crate::common::RW> {
+        assert!(n < 4usize);
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(16usize + n * 8usize) as _) }
+    }
+}
+pub mod regs;
+pub mod vals;
diff --git a/src/rp2350/busctrl/regs.rs b/src/rp2350/busctrl/regs.rs
new file mode 100644
index 00000000..bc2801bd
--- /dev/null
+++ b/src/rp2350/busctrl/regs.rs
@@ -0,0 +1,146 @@
+#[doc = "Set the priority of each master for bus arbitration."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct BusPriority(pub u32);
+impl BusPriority {
+    #[doc = "0 - low priority, 1 - high priority"]
+    #[inline(always)]
+    pub const fn proc0(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "0 - low priority, 1 - high priority"]
+    #[inline(always)]
+    pub fn set_proc0(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[doc = "0 - low priority, 1 - high priority"]
+    #[inline(always)]
+    pub const fn proc1(&self) -> bool {
+        let val = (self.0 >> 4usize) & 0x01;
+        val != 0
+    }
+    #[doc = "0 - low priority, 1 - high priority"]
+    #[inline(always)]
+    pub fn set_proc1(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
+    }
+    #[doc = "0 - low priority, 1 - high priority"]
+    #[inline(always)]
+    pub const fn dma_r(&self) -> bool {
+        let val = (self.0 >> 8usize) & 0x01;
+        val != 0
+    }
+    #[doc = "0 - low priority, 1 - high priority"]
+    #[inline(always)]
+    pub fn set_dma_r(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
+    }
+    #[doc = "0 - low priority, 1 - high priority"]
+    #[inline(always)]
+    pub const fn dma_w(&self) -> bool {
+        let val = (self.0 >> 12usize) & 0x01;
+        val != 0
+    }
+    #[doc = "0 - low priority, 1 - high priority"]
+    #[inline(always)]
+    pub fn set_dma_w(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
+    }
+}
+impl Default for BusPriority {
+    #[inline(always)]
+    fn default() -> BusPriority {
+        BusPriority(0)
+    }
+}
+#[doc = "Bus priority acknowledge"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct BusPriorityAck(pub u32);
+impl BusPriorityAck {
+    #[doc = "Goes to 1 once all arbiters have registered the new global priority levels. Arbiters update their local priority when servicing a new nonsequential access. In normal circumstances this will happen almost immediately."]
+    #[inline(always)]
+    pub const fn bus_priority_ack(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Goes to 1 once all arbiters have registered the new global priority levels. Arbiters update their local priority when servicing a new nonsequential access. In normal circumstances this will happen almost immediately."]
+    #[inline(always)]
+    pub fn set_bus_priority_ack(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+}
+impl Default for BusPriorityAck {
+    #[inline(always)]
+    fn default() -> BusPriorityAck {
+        BusPriorityAck(0)
+    }
+}
+#[doc = "Bus fabric performance counter 1"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Perfctr(pub u32);
+impl Perfctr {
+    #[doc = "Busfabric saturating performance counter 1 Count some event signal from the busfabric arbiters, if PERFCTR_EN is set. Write any value to clear. Select an event to count using PERFSEL1"]
+    #[inline(always)]
+    pub const fn perfctr(&self) -> u32 {
+        let val = (self.0 >> 0usize) & 0x00ff_ffff;
+        val as u32
+    }
+    #[doc = "Busfabric saturating performance counter 1 Count some event signal from the busfabric arbiters, if PERFCTR_EN is set. Write any value to clear. Select an event to count using PERFSEL1"]
+    #[inline(always)]
+    pub fn set_perfctr(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize);
+    }
+}
+impl Default for Perfctr {
+    #[inline(always)]
+    fn default() -> Perfctr {
+        Perfctr(0)
+    }
+}
+#[doc = "Enable the performance counters. If 0, the performance counters do not increment. This can be used to precisely start/stop event sampling around the profiled section of code. The performance counters are initially disabled, to save energy."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct PerfctrEn(pub u32);
+impl PerfctrEn {
+    #[inline(always)]
+    pub const fn perfctr_en(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_perfctr_en(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+}
+impl Default for PerfctrEn {
+    #[inline(always)]
+    fn default() -> PerfctrEn {
+        PerfctrEn(0)
+    }
+}
+#[doc = "Bus fabric performance event select for PERFCTR0"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Perfsel(pub u32);
+impl Perfsel {
+    #[doc = "Select an event for PERFCTR0. For each downstream port of the main crossbar, four events are available: ACCESS, an access took place; ACCESS_CONTESTED, an access took place that previously stalled due to contention from other masters; STALL_DOWNSTREAM, count cycles where any master stalled due to a stall on the downstream bus; STALL_UPSTREAM, count cycles where any master stalled for any reason, including contention from other masters."]
+    #[inline(always)]
+    pub const fn perfsel(&self) -> super::vals::Perfsel {
+        let val = (self.0 >> 0usize) & 0x7f;
+        super::vals::Perfsel::from_bits(val as u8)
+    }
+    #[doc = "Select an event for PERFCTR0. For each downstream port of the main crossbar, four events are available: ACCESS, an access took place; ACCESS_CONTESTED, an access took place that previously stalled due to contention from other masters; STALL_DOWNSTREAM, count cycles where any master stalled due to a stall on the downstream bus; STALL_UPSTREAM, count cycles where any master stalled for any reason, including contention from other masters."]
+    #[inline(always)]
+    pub fn set_perfsel(&mut self, val: super::vals::Perfsel) {
+        self.0 = (self.0 & !(0x7f << 0usize)) | (((val.to_bits() as u32) & 0x7f) << 0usize);
+    }
+}
+impl Default for Perfsel {
+    #[inline(always)]
+    fn default() -> Perfsel {
+        Perfsel(0)
+    }
+}
diff --git a/src/rp2350/busctrl/vals.rs b/src/rp2350/busctrl/vals.rs
new file mode 100644
index 00000000..ea550a97
--- /dev/null
+++ b/src/rp2350/busctrl/vals.rs
@@ -0,0 +1,154 @@
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Perfsel {
+    SIOB_PROC1_STALL_UPSTREAM = 0,
+    SIOB_PROC1_STALL_DOWNSTREAM = 0x01,
+    SIOB_PROC1_ACCESS_CONTESTED = 0x02,
+    SIOB_PROC1_ACCESS = 0x03,
+    SIOB_PROC0_STALL_UPSTREAM = 0x04,
+    SIOB_PROC0_STALL_DOWNSTREAM = 0x05,
+    SIOB_PROC0_ACCESS_CONTESTED = 0x06,
+    SIOB_PROC0_ACCESS = 0x07,
+    APB_STALL_UPSTREAM = 0x08,
+    APB_STALL_DOWNSTREAM = 0x09,
+    APB_ACCESS_CONTESTED = 0x0a,
+    APB_ACCESS = 0x0b,
+    FASTPERI_STALL_UPSTREAM = 0x0c,
+    FASTPERI_STALL_DOWNSTREAM = 0x0d,
+    FASTPERI_ACCESS_CONTESTED = 0x0e,
+    FASTPERI_ACCESS = 0x0f,
+    SRAM9_STALL_UPSTREAM = 0x10,
+    SRAM9_STALL_DOWNSTREAM = 0x11,
+    SRAM9_ACCESS_CONTESTED = 0x12,
+    SRAM9_ACCESS = 0x13,
+    SRAM8_STALL_UPSTREAM = 0x14,
+    SRAM8_STALL_DOWNSTREAM = 0x15,
+    SRAM8_ACCESS_CONTESTED = 0x16,
+    SRAM8_ACCESS = 0x17,
+    SRAM7_STALL_UPSTREAM = 0x18,
+    SRAM7_STALL_DOWNSTREAM = 0x19,
+    SRAM7_ACCESS_CONTESTED = 0x1a,
+    SRAM7_ACCESS = 0x1b,
+    SRAM6_STALL_UPSTREAM = 0x1c,
+    SRAM6_STALL_DOWNSTREAM = 0x1d,
+    SRAM6_ACCESS_CONTESTED = 0x1e,
+    SRAM6_ACCESS = 0x1f,
+    SRAM5_STALL_UPSTREAM = 0x20,
+    SRAM5_STALL_DOWNSTREAM = 0x21,
+    SRAM5_ACCESS_CONTESTED = 0x22,
+    SRAM5_ACCESS = 0x23,
+    SRAM4_STALL_UPSTREAM = 0x24,
+    SRAM4_STALL_DOWNSTREAM = 0x25,
+    SRAM4_ACCESS_CONTESTED = 0x26,
+    SRAM4_ACCESS = 0x27,
+    SRAM3_STALL_UPSTREAM = 0x28,
+    SRAM3_STALL_DOWNSTREAM = 0x29,
+    SRAM3_ACCESS_CONTESTED = 0x2a,
+    SRAM3_ACCESS = 0x2b,
+    SRAM2_STALL_UPSTREAM = 0x2c,
+    SRAM2_STALL_DOWNSTREAM = 0x2d,
+    SRAM2_ACCESS_CONTESTED = 0x2e,
+    SRAM2_ACCESS = 0x2f,
+    SRAM1_STALL_UPSTREAM = 0x30,
+    SRAM1_STALL_DOWNSTREAM = 0x31,
+    SRAM1_ACCESS_CONTESTED = 0x32,
+    SRAM1_ACCESS = 0x33,
+    SRAM0_STALL_UPSTREAM = 0x34,
+    SRAM0_STALL_DOWNSTREAM = 0x35,
+    SRAM0_ACCESS_CONTESTED = 0x36,
+    SRAM0_ACCESS = 0x37,
+    XIP_MAIN1_STALL_UPSTREAM = 0x38,
+    XIP_MAIN1_STALL_DOWNSTREAM = 0x39,
+    XIP_MAIN1_ACCESS_CONTESTED = 0x3a,
+    XIP_MAIN1_ACCESS = 0x3b,
+    XIP_MAIN0_STALL_UPSTREAM = 0x3c,
+    XIP_MAIN0_STALL_DOWNSTREAM = 0x3d,
+    XIP_MAIN0_ACCESS_CONTESTED = 0x3e,
+    XIP_MAIN0_ACCESS = 0x3f,
+    ROM_STALL_UPSTREAM = 0x40,
+    ROM_STALL_DOWNSTREAM = 0x41,
+    ROM_ACCESS_CONTESTED = 0x42,
+    ROM_ACCESS = 0x43,
+    _RESERVED_44 = 0x44,
+    _RESERVED_45 = 0x45,
+    _RESERVED_46 = 0x46,
+    _RESERVED_47 = 0x47,
+    _RESERVED_48 = 0x48,
+    _RESERVED_49 = 0x49,
+    _RESERVED_4a = 0x4a,
+    _RESERVED_4b = 0x4b,
+    _RESERVED_4c = 0x4c,
+    _RESERVED_4d = 0x4d,
+    _RESERVED_4e = 0x4e,
+    _RESERVED_4f = 0x4f,
+    _RESERVED_50 = 0x50,
+    _RESERVED_51 = 0x51,
+    _RESERVED_52 = 0x52,
+    _RESERVED_53 = 0x53,
+    _RESERVED_54 = 0x54,
+    _RESERVED_55 = 0x55,
+    _RESERVED_56 = 0x56,
+    _RESERVED_57 = 0x57,
+    _RESERVED_58 = 0x58,
+    _RESERVED_59 = 0x59,
+    _RESERVED_5a = 0x5a,
+    _RESERVED_5b = 0x5b,
+    _RESERVED_5c = 0x5c,
+    _RESERVED_5d = 0x5d,
+    _RESERVED_5e = 0x5e,
+    _RESERVED_5f = 0x5f,
+    _RESERVED_60 = 0x60,
+    _RESERVED_61 = 0x61,
+    _RESERVED_62 = 0x62,
+    _RESERVED_63 = 0x63,
+    _RESERVED_64 = 0x64,
+    _RESERVED_65 = 0x65,
+    _RESERVED_66 = 0x66,
+    _RESERVED_67 = 0x67,
+    _RESERVED_68 = 0x68,
+    _RESERVED_69 = 0x69,
+    _RESERVED_6a = 0x6a,
+    _RESERVED_6b = 0x6b,
+    _RESERVED_6c = 0x6c,
+    _RESERVED_6d = 0x6d,
+    _RESERVED_6e = 0x6e,
+    _RESERVED_6f = 0x6f,
+    _RESERVED_70 = 0x70,
+    _RESERVED_71 = 0x71,
+    _RESERVED_72 = 0x72,
+    _RESERVED_73 = 0x73,
+    _RESERVED_74 = 0x74,
+    _RESERVED_75 = 0x75,
+    _RESERVED_76 = 0x76,
+    _RESERVED_77 = 0x77,
+    _RESERVED_78 = 0x78,
+    _RESERVED_79 = 0x79,
+    _RESERVED_7a = 0x7a,
+    _RESERVED_7b = 0x7b,
+    _RESERVED_7c = 0x7c,
+    _RESERVED_7d = 0x7d,
+    _RESERVED_7e = 0x7e,
+    _RESERVED_7f = 0x7f,
+}
+impl Perfsel {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Perfsel {
+        unsafe { core::mem::transmute(val & 0x7f) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Perfsel {
+    #[inline(always)]
+    fn from(val: u8) -> Perfsel {
+        Perfsel::from_bits(val)
+    }
+}
+impl From<Perfsel> for u8 {
+    #[inline(always)]
+    fn from(val: Perfsel) -> u8 {
+        Perfsel::to_bits(val)
+    }
+}
diff --git a/src/rp2350/clocks.rs b/src/rp2350/clocks.rs
new file mode 100644
index 00000000..7a6b4841
--- /dev/null
+++ b/src/rp2350/clocks.rs
@@ -0,0 +1,260 @@
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Clocks {
+    ptr: *mut u8,
+}
+unsafe impl Send for Clocks {}
+unsafe impl Sync for Clocks {}
+impl Clocks {
+    #[inline(always)]
+    pub const unsafe fn from_ptr(ptr: *mut ()) -> Self {
+        Self { ptr: ptr as _ }
+    }
+    #[inline(always)]
+    pub const fn as_ptr(&self) -> *mut () {
+        self.ptr as _
+    }
+    #[doc = "Clock control, can be changed on-the-fly (except for auxsrc)"]
+    #[inline(always)]
+    pub const fn clk_gpout_ctrl(
+        self,
+        n: usize,
+    ) -> crate::common::Reg<regs::ClkGpoutCtrl, crate::common::RW> {
+        assert!(n < 4usize);
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(0usize + n * 12usize) as _) }
+    }
+    #[inline(always)]
+    pub const fn clk_gpout_div(
+        self,
+        n: usize,
+    ) -> crate::common::Reg<regs::ClkGpoutDiv, crate::common::RW> {
+        assert!(n < 4usize);
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(4usize + n * 12usize) as _) }
+    }
+    #[doc = "Indicates which src is currently selected (one-hot)"]
+    #[inline(always)]
+    pub const fn clk_gpout_selected(
+        self,
+        n: usize,
+    ) -> crate::common::Reg<regs::ClkGpout0selected, crate::common::RW> {
+        assert!(n < 4usize);
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(8usize + n * 12usize) as _) }
+    }
+    #[doc = "Clock control, can be changed on-the-fly (except for auxsrc)"]
+    #[inline(always)]
+    pub const fn clk_ref_ctrl(self) -> crate::common::Reg<regs::ClkRefCtrl, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(48usize) as _) }
+    }
+    #[inline(always)]
+    pub const fn clk_ref_div(self) -> crate::common::Reg<regs::ClkRefDiv, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(52usize) as _) }
+    }
+    #[doc = "Indicates which src is currently selected (one-hot)"]
+    #[inline(always)]
+    pub const fn clk_ref_selected(
+        self,
+    ) -> crate::common::Reg<regs::ClkRefSelected, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(56usize) as _) }
+    }
+    #[doc = "Clock control, can be changed on-the-fly (except for auxsrc)"]
+    #[inline(always)]
+    pub const fn clk_sys_ctrl(self) -> crate::common::Reg<regs::ClkSysCtrl, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(60usize) as _) }
+    }
+    #[inline(always)]
+    pub const fn clk_sys_div(self) -> crate::common::Reg<regs::ClkSysDiv, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(64usize) as _) }
+    }
+    #[doc = "Indicates which src is currently selected (one-hot)"]
+    #[inline(always)]
+    pub const fn clk_sys_selected(
+        self,
+    ) -> crate::common::Reg<regs::ClkSysSelected, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(68usize) as _) }
+    }
+    #[doc = "Clock control, can be changed on-the-fly (except for auxsrc)"]
+    #[inline(always)]
+    pub const fn clk_peri_ctrl(self) -> crate::common::Reg<regs::ClkPeriCtrl, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(72usize) as _) }
+    }
+    #[inline(always)]
+    pub const fn clk_peri_div(self) -> crate::common::Reg<regs::ClkPeriDiv, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(76usize) as _) }
+    }
+    #[doc = "Indicates which src is currently selected (one-hot)"]
+    #[inline(always)]
+    pub const fn clk_peri_selected(
+        self,
+    ) -> crate::common::Reg<regs::ClkPeriSelected, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(80usize) as _) }
+    }
+    #[doc = "Clock control, can be changed on-the-fly (except for auxsrc)"]
+    #[inline(always)]
+    pub const fn clk_hstx_ctrl(self) -> crate::common::Reg<regs::ClkHstxCtrl, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(84usize) as _) }
+    }
+    #[inline(always)]
+    pub const fn clk_hstx_div(self) -> crate::common::Reg<regs::ClkHstxDiv, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(88usize) as _) }
+    }
+    #[doc = "Indicates which src is currently selected (one-hot)"]
+    #[inline(always)]
+    pub const fn clk_hstx_selected(
+        self,
+    ) -> crate::common::Reg<regs::ClkHstxSelected, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(92usize) as _) }
+    }
+    #[doc = "Clock control, can be changed on-the-fly (except for auxsrc)"]
+    #[inline(always)]
+    pub const fn clk_usb_ctrl(self) -> crate::common::Reg<regs::ClkUsbCtrl, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(96usize) as _) }
+    }
+    #[inline(always)]
+    pub const fn clk_usb_div(self) -> crate::common::Reg<regs::ClkUsbDiv, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(100usize) as _) }
+    }
+    #[doc = "Indicates which src is currently selected (one-hot)"]
+    #[inline(always)]
+    pub const fn clk_usb_selected(
+        self,
+    ) -> crate::common::Reg<regs::ClkUsbSelected, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(104usize) as _) }
+    }
+    #[doc = "Clock control, can be changed on-the-fly (except for auxsrc)"]
+    #[inline(always)]
+    pub const fn clk_adc_ctrl(self) -> crate::common::Reg<regs::ClkAdcCtrl, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(108usize) as _) }
+    }
+    #[inline(always)]
+    pub const fn clk_adc_div(self) -> crate::common::Reg<regs::ClkAdcDiv, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(112usize) as _) }
+    }
+    #[doc = "Indicates which src is currently selected (one-hot)"]
+    #[inline(always)]
+    pub const fn clk_adc_selected(
+        self,
+    ) -> crate::common::Reg<regs::ClkAdcSelected, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(116usize) as _) }
+    }
+    #[inline(always)]
+    pub const fn dftclk_xosc_ctrl(
+        self,
+    ) -> crate::common::Reg<regs::DftclkXoscCtrl, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(120usize) as _) }
+    }
+    #[inline(always)]
+    pub const fn dftclk_rosc_ctrl(
+        self,
+    ) -> crate::common::Reg<regs::DftclkRoscCtrl, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(124usize) as _) }
+    }
+    #[inline(always)]
+    pub const fn dftclk_lposc_ctrl(
+        self,
+    ) -> crate::common::Reg<regs::DftclkLposcCtrl, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(128usize) as _) }
+    }
+    #[inline(always)]
+    pub const fn clk_sys_resus_ctrl(
+        self,
+    ) -> crate::common::Reg<regs::ClkSysResusCtrl, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(132usize) as _) }
+    }
+    #[inline(always)]
+    pub const fn clk_sys_resus_status(
+        self,
+    ) -> crate::common::Reg<regs::ClkSysResusStatus, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(136usize) as _) }
+    }
+    #[doc = "Reference clock frequency in kHz"]
+    #[inline(always)]
+    pub const fn fc0_ref_khz(self) -> crate::common::Reg<regs::Fc0refKhz, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(140usize) as _) }
+    }
+    #[doc = "Minimum pass frequency in kHz. This is optional. Set to 0 if you are not using the pass/fail flags"]
+    #[inline(always)]
+    pub const fn fc0_min_khz(self) -> crate::common::Reg<regs::Fc0minKhz, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(144usize) as _) }
+    }
+    #[doc = "Maximum pass frequency in kHz. This is optional. Set to 0x1ffffff if you are not using the pass/fail flags"]
+    #[inline(always)]
+    pub const fn fc0_max_khz(self) -> crate::common::Reg<regs::Fc0maxKhz, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(148usize) as _) }
+    }
+    #[doc = "Delays the start of frequency counting to allow the mux to settle Delay is measured in multiples of the reference clock period"]
+    #[inline(always)]
+    pub const fn fc0_delay(self) -> crate::common::Reg<regs::Fc0delay, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(152usize) as _) }
+    }
+    #[doc = "The test interval is 0.98us * 2**interval, but let's call it 1us * 2**interval The default gives a test interval of 250us"]
+    #[inline(always)]
+    pub const fn fc0_interval(self) -> crate::common::Reg<regs::Fc0interval, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(156usize) as _) }
+    }
+    #[doc = "Clock sent to frequency counter, set to 0 when not required Writing to this register initiates the frequency count"]
+    #[inline(always)]
+    pub const fn fc0_src(self) -> crate::common::Reg<regs::Fc0src, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(160usize) as _) }
+    }
+    #[doc = "Frequency counter status"]
+    #[inline(always)]
+    pub const fn fc0_status(self) -> crate::common::Reg<regs::Fc0status, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(164usize) as _) }
+    }
+    #[doc = "Result of frequency measurement, only valid when status_done=1"]
+    #[inline(always)]
+    pub const fn fc0_result(self) -> crate::common::Reg<regs::Fc0result, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(168usize) as _) }
+    }
+    #[doc = "enable clock in wake mode"]
+    #[inline(always)]
+    pub const fn wake_en0(self) -> crate::common::Reg<regs::WakeEn0, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(172usize) as _) }
+    }
+    #[doc = "enable clock in wake mode"]
+    #[inline(always)]
+    pub const fn wake_en1(self) -> crate::common::Reg<regs::WakeEn1, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(176usize) as _) }
+    }
+    #[doc = "enable clock in sleep mode"]
+    #[inline(always)]
+    pub const fn sleep_en0(self) -> crate::common::Reg<regs::SleepEn0, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(180usize) as _) }
+    }
+    #[doc = "enable clock in sleep mode"]
+    #[inline(always)]
+    pub const fn sleep_en1(self) -> crate::common::Reg<regs::SleepEn1, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(184usize) as _) }
+    }
+    #[doc = "indicates the state of the clock enable"]
+    #[inline(always)]
+    pub const fn enabled0(self) -> crate::common::Reg<regs::Enabled0, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(188usize) as _) }
+    }
+    #[doc = "indicates the state of the clock enable"]
+    #[inline(always)]
+    pub const fn enabled1(self) -> crate::common::Reg<regs::Enabled1, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(192usize) as _) }
+    }
+    #[doc = "Raw Interrupts"]
+    #[inline(always)]
+    pub const fn intr(self) -> crate::common::Reg<regs::Int, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(196usize) as _) }
+    }
+    #[doc = "Interrupt Enable"]
+    #[inline(always)]
+    pub const fn inte(self) -> crate::common::Reg<regs::Int, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(200usize) as _) }
+    }
+    #[doc = "Interrupt Force"]
+    #[inline(always)]
+    pub const fn intf(self) -> crate::common::Reg<regs::Int, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(204usize) as _) }
+    }
+    #[doc = "Interrupt status after masking & forcing"]
+    #[inline(always)]
+    pub const fn ints(self) -> crate::common::Reg<regs::Int, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(208usize) as _) }
+    }
+}
+pub mod regs;
+pub mod vals;
diff --git a/src/rp2350/clocks/regs.rs b/src/rp2350/clocks/regs.rs
new file mode 100644
index 00000000..83df4a8d
--- /dev/null
+++ b/src/rp2350/clocks/regs.rs
@@ -0,0 +1,3040 @@
+#[doc = "Clock control, can be changed on-the-fly (except for auxsrc)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct ClkAdcCtrl(pub u32);
+impl ClkAdcCtrl {
+    #[doc = "Selects the auxiliary clock source, will glitch when switching"]
+    #[inline(always)]
+    pub const fn auxsrc(&self) -> super::vals::ClkAdcCtrlAuxsrc {
+        let val = (self.0 >> 5usize) & 0x07;
+        super::vals::ClkAdcCtrlAuxsrc::from_bits(val as u8)
+    }
+    #[doc = "Selects the auxiliary clock source, will glitch when switching"]
+    #[inline(always)]
+    pub fn set_auxsrc(&mut self, val: super::vals::ClkAdcCtrlAuxsrc) {
+        self.0 = (self.0 & !(0x07 << 5usize)) | (((val.to_bits() as u32) & 0x07) << 5usize);
+    }
+    #[doc = "Asynchronously kills the clock generator, enable must be set low before deasserting kill"]
+    #[inline(always)]
+    pub const fn kill(&self) -> bool {
+        let val = (self.0 >> 10usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Asynchronously kills the clock generator, enable must be set low before deasserting kill"]
+    #[inline(always)]
+    pub fn set_kill(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize);
+    }
+    #[doc = "Starts and stops the clock generator cleanly"]
+    #[inline(always)]
+    pub const fn enable(&self) -> bool {
+        let val = (self.0 >> 11usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Starts and stops the clock generator cleanly"]
+    #[inline(always)]
+    pub fn set_enable(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
+    }
+    #[doc = "This delays the enable signal by up to 3 cycles of the input clock This must be set before the clock is enabled to have any effect"]
+    #[inline(always)]
+    pub const fn phase(&self) -> u8 {
+        let val = (self.0 >> 16usize) & 0x03;
+        val as u8
+    }
+    #[doc = "This delays the enable signal by up to 3 cycles of the input clock This must be set before the clock is enabled to have any effect"]
+    #[inline(always)]
+    pub fn set_phase(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x03 << 16usize)) | (((val as u32) & 0x03) << 16usize);
+    }
+    #[doc = "An edge on this signal shifts the phase of the output by 1 cycle of the input clock This can be done at any time"]
+    #[inline(always)]
+    pub const fn nudge(&self) -> bool {
+        let val = (self.0 >> 20usize) & 0x01;
+        val != 0
+    }
+    #[doc = "An edge on this signal shifts the phase of the output by 1 cycle of the input clock This can be done at any time"]
+    #[inline(always)]
+    pub fn set_nudge(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize);
+    }
+    #[doc = "clock generator is enabled"]
+    #[inline(always)]
+    pub const fn enabled(&self) -> bool {
+        let val = (self.0 >> 28usize) & 0x01;
+        val != 0
+    }
+    #[doc = "clock generator is enabled"]
+    #[inline(always)]
+    pub fn set_enabled(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 28usize)) | (((val as u32) & 0x01) << 28usize);
+    }
+}
+impl Default for ClkAdcCtrl {
+    #[inline(always)]
+    fn default() -> ClkAdcCtrl {
+        ClkAdcCtrl(0)
+    }
+}
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct ClkAdcDiv(pub u32);
+impl ClkAdcDiv {
+    #[doc = "Integer part of clock divisor, 0 -> max+1, can be changed on-the-fly"]
+    #[inline(always)]
+    pub const fn int(&self) -> u8 {
+        let val = (self.0 >> 16usize) & 0x0f;
+        val as u8
+    }
+    #[doc = "Integer part of clock divisor, 0 -> max+1, can be changed on-the-fly"]
+    #[inline(always)]
+    pub fn set_int(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x0f << 16usize)) | (((val as u32) & 0x0f) << 16usize);
+    }
+}
+impl Default for ClkAdcDiv {
+    #[inline(always)]
+    fn default() -> ClkAdcDiv {
+        ClkAdcDiv(0)
+    }
+}
+#[doc = "Indicates which src is currently selected (one-hot)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct ClkAdcSelected(pub u32);
+impl ClkAdcSelected {
+    #[doc = "This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1."]
+    #[inline(always)]
+    pub const fn clk_adc_selected(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1."]
+    #[inline(always)]
+    pub fn set_clk_adc_selected(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+}
+impl Default for ClkAdcSelected {
+    #[inline(always)]
+    fn default() -> ClkAdcSelected {
+        ClkAdcSelected(0)
+    }
+}
+#[doc = "Indicates which src is currently selected (one-hot)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct ClkGpout0selected(pub u32);
+impl ClkGpout0selected {
+    #[doc = "This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1."]
+    #[inline(always)]
+    pub const fn clk_gpout0_selected(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1."]
+    #[inline(always)]
+    pub fn set_clk_gpout0_selected(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+}
+impl Default for ClkGpout0selected {
+    #[inline(always)]
+    fn default() -> ClkGpout0selected {
+        ClkGpout0selected(0)
+    }
+}
+#[doc = "Indicates which src is currently selected (one-hot)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct ClkGpout1selected(pub u32);
+impl ClkGpout1selected {
+    #[doc = "This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1."]
+    #[inline(always)]
+    pub const fn clk_gpout1_selected(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1."]
+    #[inline(always)]
+    pub fn set_clk_gpout1_selected(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+}
+impl Default for ClkGpout1selected {
+    #[inline(always)]
+    fn default() -> ClkGpout1selected {
+        ClkGpout1selected(0)
+    }
+}
+#[doc = "Indicates which src is currently selected (one-hot)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct ClkGpout2selected(pub u32);
+impl ClkGpout2selected {
+    #[doc = "This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1."]
+    #[inline(always)]
+    pub const fn clk_gpout2_selected(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1."]
+    #[inline(always)]
+    pub fn set_clk_gpout2_selected(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+}
+impl Default for ClkGpout2selected {
+    #[inline(always)]
+    fn default() -> ClkGpout2selected {
+        ClkGpout2selected(0)
+    }
+}
+#[doc = "Indicates which src is currently selected (one-hot)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct ClkGpout3selected(pub u32);
+impl ClkGpout3selected {
+    #[doc = "This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1."]
+    #[inline(always)]
+    pub const fn clk_gpout3_selected(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1."]
+    #[inline(always)]
+    pub fn set_clk_gpout3_selected(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+}
+impl Default for ClkGpout3selected {
+    #[inline(always)]
+    fn default() -> ClkGpout3selected {
+        ClkGpout3selected(0)
+    }
+}
+#[doc = "Clock control, can be changed on-the-fly (except for auxsrc)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct ClkGpoutCtrl(pub u32);
+impl ClkGpoutCtrl {
+    #[doc = "Selects the auxiliary clock source, will glitch when switching"]
+    #[inline(always)]
+    pub const fn auxsrc(&self) -> super::vals::ClkGpoutCtrlAuxsrc {
+        let val = (self.0 >> 5usize) & 0x0f;
+        super::vals::ClkGpoutCtrlAuxsrc::from_bits(val as u8)
+    }
+    #[doc = "Selects the auxiliary clock source, will glitch when switching"]
+    #[inline(always)]
+    pub fn set_auxsrc(&mut self, val: super::vals::ClkGpoutCtrlAuxsrc) {
+        self.0 = (self.0 & !(0x0f << 5usize)) | (((val.to_bits() as u32) & 0x0f) << 5usize);
+    }
+    #[doc = "Asynchronously kills the clock generator, enable must be set low before deasserting kill"]
+    #[inline(always)]
+    pub const fn kill(&self) -> bool {
+        let val = (self.0 >> 10usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Asynchronously kills the clock generator, enable must be set low before deasserting kill"]
+    #[inline(always)]
+    pub fn set_kill(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize);
+    }
+    #[doc = "Starts and stops the clock generator cleanly"]
+    #[inline(always)]
+    pub const fn enable(&self) -> bool {
+        let val = (self.0 >> 11usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Starts and stops the clock generator cleanly"]
+    #[inline(always)]
+    pub fn set_enable(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
+    }
+    #[doc = "Enables duty cycle correction for odd divisors, can be changed on-the-fly"]
+    #[inline(always)]
+    pub const fn dc50(&self) -> bool {
+        let val = (self.0 >> 12usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Enables duty cycle correction for odd divisors, can be changed on-the-fly"]
+    #[inline(always)]
+    pub fn set_dc50(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
+    }
+    #[doc = "This delays the enable signal by up to 3 cycles of the input clock This must be set before the clock is enabled to have any effect"]
+    #[inline(always)]
+    pub const fn phase(&self) -> u8 {
+        let val = (self.0 >> 16usize) & 0x03;
+        val as u8
+    }
+    #[doc = "This delays the enable signal by up to 3 cycles of the input clock This must be set before the clock is enabled to have any effect"]
+    #[inline(always)]
+    pub fn set_phase(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x03 << 16usize)) | (((val as u32) & 0x03) << 16usize);
+    }
+    #[doc = "An edge on this signal shifts the phase of the output by 1 cycle of the input clock This can be done at any time"]
+    #[inline(always)]
+    pub const fn nudge(&self) -> bool {
+        let val = (self.0 >> 20usize) & 0x01;
+        val != 0
+    }
+    #[doc = "An edge on this signal shifts the phase of the output by 1 cycle of the input clock This can be done at any time"]
+    #[inline(always)]
+    pub fn set_nudge(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize);
+    }
+    #[doc = "clock generator is enabled"]
+    #[inline(always)]
+    pub const fn enabled(&self) -> bool {
+        let val = (self.0 >> 28usize) & 0x01;
+        val != 0
+    }
+    #[doc = "clock generator is enabled"]
+    #[inline(always)]
+    pub fn set_enabled(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 28usize)) | (((val as u32) & 0x01) << 28usize);
+    }
+}
+impl Default for ClkGpoutCtrl {
+    #[inline(always)]
+    fn default() -> ClkGpoutCtrl {
+        ClkGpoutCtrl(0)
+    }
+}
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct ClkGpoutDiv(pub u32);
+impl ClkGpoutDiv {
+    #[doc = "Fractional component of the divisor, can be changed on-the-fly"]
+    #[inline(always)]
+    pub const fn frac(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0xffff;
+        val as u16
+    }
+    #[doc = "Fractional component of the divisor, can be changed on-the-fly"]
+    #[inline(always)]
+    pub fn set_frac(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+    }
+    #[doc = "Integer part of clock divisor, 0 -> max+1, can be changed on-the-fly"]
+    #[inline(always)]
+    pub const fn int(&self) -> u16 {
+        let val = (self.0 >> 16usize) & 0xffff;
+        val as u16
+    }
+    #[doc = "Integer part of clock divisor, 0 -> max+1, can be changed on-the-fly"]
+    #[inline(always)]
+    pub fn set_int(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 16usize)) | (((val as u32) & 0xffff) << 16usize);
+    }
+}
+impl Default for ClkGpoutDiv {
+    #[inline(always)]
+    fn default() -> ClkGpoutDiv {
+        ClkGpoutDiv(0)
+    }
+}
+#[doc = "Clock control, can be changed on-the-fly (except for auxsrc)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct ClkHstxCtrl(pub u32);
+impl ClkHstxCtrl {
+    #[doc = "Selects the auxiliary clock source, will glitch when switching"]
+    #[inline(always)]
+    pub const fn auxsrc(&self) -> super::vals::ClkHstxCtrlAuxsrc {
+        let val = (self.0 >> 5usize) & 0x07;
+        super::vals::ClkHstxCtrlAuxsrc::from_bits(val as u8)
+    }
+    #[doc = "Selects the auxiliary clock source, will glitch when switching"]
+    #[inline(always)]
+    pub fn set_auxsrc(&mut self, val: super::vals::ClkHstxCtrlAuxsrc) {
+        self.0 = (self.0 & !(0x07 << 5usize)) | (((val.to_bits() as u32) & 0x07) << 5usize);
+    }
+    #[doc = "Asynchronously kills the clock generator, enable must be set low before deasserting kill"]
+    #[inline(always)]
+    pub const fn kill(&self) -> bool {
+        let val = (self.0 >> 10usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Asynchronously kills the clock generator, enable must be set low before deasserting kill"]
+    #[inline(always)]
+    pub fn set_kill(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize);
+    }
+    #[doc = "Starts and stops the clock generator cleanly"]
+    #[inline(always)]
+    pub const fn enable(&self) -> bool {
+        let val = (self.0 >> 11usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Starts and stops the clock generator cleanly"]
+    #[inline(always)]
+    pub fn set_enable(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
+    }
+    #[doc = "This delays the enable signal by up to 3 cycles of the input clock This must be set before the clock is enabled to have any effect"]
+    #[inline(always)]
+    pub const fn phase(&self) -> u8 {
+        let val = (self.0 >> 16usize) & 0x03;
+        val as u8
+    }
+    #[doc = "This delays the enable signal by up to 3 cycles of the input clock This must be set before the clock is enabled to have any effect"]
+    #[inline(always)]
+    pub fn set_phase(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x03 << 16usize)) | (((val as u32) & 0x03) << 16usize);
+    }
+    #[doc = "An edge on this signal shifts the phase of the output by 1 cycle of the input clock This can be done at any time"]
+    #[inline(always)]
+    pub const fn nudge(&self) -> bool {
+        let val = (self.0 >> 20usize) & 0x01;
+        val != 0
+    }
+    #[doc = "An edge on this signal shifts the phase of the output by 1 cycle of the input clock This can be done at any time"]
+    #[inline(always)]
+    pub fn set_nudge(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize);
+    }
+    #[doc = "clock generator is enabled"]
+    #[inline(always)]
+    pub const fn enabled(&self) -> bool {
+        let val = (self.0 >> 28usize) & 0x01;
+        val != 0
+    }
+    #[doc = "clock generator is enabled"]
+    #[inline(always)]
+    pub fn set_enabled(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 28usize)) | (((val as u32) & 0x01) << 28usize);
+    }
+}
+impl Default for ClkHstxCtrl {
+    #[inline(always)]
+    fn default() -> ClkHstxCtrl {
+        ClkHstxCtrl(0)
+    }
+}
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct ClkHstxDiv(pub u32);
+impl ClkHstxDiv {
+    #[doc = "Integer part of clock divisor, 0 -> max+1, can be changed on-the-fly"]
+    #[inline(always)]
+    pub const fn int(&self) -> u8 {
+        let val = (self.0 >> 16usize) & 0x03;
+        val as u8
+    }
+    #[doc = "Integer part of clock divisor, 0 -> max+1, can be changed on-the-fly"]
+    #[inline(always)]
+    pub fn set_int(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x03 << 16usize)) | (((val as u32) & 0x03) << 16usize);
+    }
+}
+impl Default for ClkHstxDiv {
+    #[inline(always)]
+    fn default() -> ClkHstxDiv {
+        ClkHstxDiv(0)
+    }
+}
+#[doc = "Indicates which src is currently selected (one-hot)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct ClkHstxSelected(pub u32);
+impl ClkHstxSelected {
+    #[doc = "This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1."]
+    #[inline(always)]
+    pub const fn clk_hstx_selected(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1."]
+    #[inline(always)]
+    pub fn set_clk_hstx_selected(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+}
+impl Default for ClkHstxSelected {
+    #[inline(always)]
+    fn default() -> ClkHstxSelected {
+        ClkHstxSelected(0)
+    }
+}
+#[doc = "Clock control, can be changed on-the-fly (except for auxsrc)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct ClkPeriCtrl(pub u32);
+impl ClkPeriCtrl {
+    #[doc = "Selects the auxiliary clock source, will glitch when switching"]
+    #[inline(always)]
+    pub const fn auxsrc(&self) -> super::vals::ClkPeriCtrlAuxsrc {
+        let val = (self.0 >> 5usize) & 0x07;
+        super::vals::ClkPeriCtrlAuxsrc::from_bits(val as u8)
+    }
+    #[doc = "Selects the auxiliary clock source, will glitch when switching"]
+    #[inline(always)]
+    pub fn set_auxsrc(&mut self, val: super::vals::ClkPeriCtrlAuxsrc) {
+        self.0 = (self.0 & !(0x07 << 5usize)) | (((val.to_bits() as u32) & 0x07) << 5usize);
+    }
+    #[doc = "Asynchronously kills the clock generator, enable must be set low before deasserting kill"]
+    #[inline(always)]
+    pub const fn kill(&self) -> bool {
+        let val = (self.0 >> 10usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Asynchronously kills the clock generator, enable must be set low before deasserting kill"]
+    #[inline(always)]
+    pub fn set_kill(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize);
+    }
+    #[doc = "Starts and stops the clock generator cleanly"]
+    #[inline(always)]
+    pub const fn enable(&self) -> bool {
+        let val = (self.0 >> 11usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Starts and stops the clock generator cleanly"]
+    #[inline(always)]
+    pub fn set_enable(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
+    }
+    #[doc = "clock generator is enabled"]
+    #[inline(always)]
+    pub const fn enabled(&self) -> bool {
+        let val = (self.0 >> 28usize) & 0x01;
+        val != 0
+    }
+    #[doc = "clock generator is enabled"]
+    #[inline(always)]
+    pub fn set_enabled(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 28usize)) | (((val as u32) & 0x01) << 28usize);
+    }
+}
+impl Default for ClkPeriCtrl {
+    #[inline(always)]
+    fn default() -> ClkPeriCtrl {
+        ClkPeriCtrl(0)
+    }
+}
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct ClkPeriDiv(pub u32);
+impl ClkPeriDiv {
+    #[doc = "Integer part of clock divisor, 0 -> max+1, can be changed on-the-fly"]
+    #[inline(always)]
+    pub const fn int(&self) -> u8 {
+        let val = (self.0 >> 16usize) & 0x03;
+        val as u8
+    }
+    #[doc = "Integer part of clock divisor, 0 -> max+1, can be changed on-the-fly"]
+    #[inline(always)]
+    pub fn set_int(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x03 << 16usize)) | (((val as u32) & 0x03) << 16usize);
+    }
+}
+impl Default for ClkPeriDiv {
+    #[inline(always)]
+    fn default() -> ClkPeriDiv {
+        ClkPeriDiv(0)
+    }
+}
+#[doc = "Indicates which src is currently selected (one-hot)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct ClkPeriSelected(pub u32);
+impl ClkPeriSelected {
+    #[doc = "This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1."]
+    #[inline(always)]
+    pub const fn clk_peri_selected(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1."]
+    #[inline(always)]
+    pub fn set_clk_peri_selected(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+}
+impl Default for ClkPeriSelected {
+    #[inline(always)]
+    fn default() -> ClkPeriSelected {
+        ClkPeriSelected(0)
+    }
+}
+#[doc = "Clock control, can be changed on-the-fly (except for auxsrc)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct ClkRefCtrl(pub u32);
+impl ClkRefCtrl {
+    #[doc = "Selects the clock source glitchlessly, can be changed on-the-fly"]
+    #[inline(always)]
+    pub const fn src(&self) -> super::vals::ClkRefCtrlSrc {
+        let val = (self.0 >> 0usize) & 0x03;
+        super::vals::ClkRefCtrlSrc::from_bits(val as u8)
+    }
+    #[doc = "Selects the clock source glitchlessly, can be changed on-the-fly"]
+    #[inline(always)]
+    pub fn set_src(&mut self, val: super::vals::ClkRefCtrlSrc) {
+        self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize);
+    }
+    #[doc = "Selects the auxiliary clock source, will glitch when switching"]
+    #[inline(always)]
+    pub const fn auxsrc(&self) -> super::vals::ClkRefCtrlAuxsrc {
+        let val = (self.0 >> 5usize) & 0x03;
+        super::vals::ClkRefCtrlAuxsrc::from_bits(val as u8)
+    }
+    #[doc = "Selects the auxiliary clock source, will glitch when switching"]
+    #[inline(always)]
+    pub fn set_auxsrc(&mut self, val: super::vals::ClkRefCtrlAuxsrc) {
+        self.0 = (self.0 & !(0x03 << 5usize)) | (((val.to_bits() as u32) & 0x03) << 5usize);
+    }
+}
+impl Default for ClkRefCtrl {
+    #[inline(always)]
+    fn default() -> ClkRefCtrl {
+        ClkRefCtrl(0)
+    }
+}
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct ClkRefDiv(pub u32);
+impl ClkRefDiv {
+    #[doc = "Integer part of clock divisor, 0 -> max+1, can be changed on-the-fly"]
+    #[inline(always)]
+    pub const fn int(&self) -> u8 {
+        let val = (self.0 >> 16usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Integer part of clock divisor, 0 -> max+1, can be changed on-the-fly"]
+    #[inline(always)]
+    pub fn set_int(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize);
+    }
+}
+impl Default for ClkRefDiv {
+    #[inline(always)]
+    fn default() -> ClkRefDiv {
+        ClkRefDiv(0)
+    }
+}
+#[doc = "Indicates which src is currently selected (one-hot)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct ClkRefSelected(pub u32);
+impl ClkRefSelected {
+    #[doc = "The glitchless multiplexer does not switch instantaneously (to avoid glitches), so software should poll this register to wait for the switch to complete. This register contains one decoded bit for each of the clock sources enumerated in the CTRL SRC field. At most one of these bits will be set at any time, indicating that clock is currently present at the output of the glitchless mux. Whilst switching is in progress, this register may briefly show all-0s."]
+    #[inline(always)]
+    pub const fn clk_ref_selected(&self) -> u8 {
+        let val = (self.0 >> 0usize) & 0x0f;
+        val as u8
+    }
+    #[doc = "The glitchless multiplexer does not switch instantaneously (to avoid glitches), so software should poll this register to wait for the switch to complete. This register contains one decoded bit for each of the clock sources enumerated in the CTRL SRC field. At most one of these bits will be set at any time, indicating that clock is currently present at the output of the glitchless mux. Whilst switching is in progress, this register may briefly show all-0s."]
+    #[inline(always)]
+    pub fn set_clk_ref_selected(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize);
+    }
+}
+impl Default for ClkRefSelected {
+    #[inline(always)]
+    fn default() -> ClkRefSelected {
+        ClkRefSelected(0)
+    }
+}
+#[doc = "Clock control, can be changed on-the-fly (except for auxsrc)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct ClkSysCtrl(pub u32);
+impl ClkSysCtrl {
+    #[doc = "Selects the clock source glitchlessly, can be changed on-the-fly"]
+    #[inline(always)]
+    pub const fn src(&self) -> super::vals::ClkSysCtrlSrc {
+        let val = (self.0 >> 0usize) & 0x01;
+        super::vals::ClkSysCtrlSrc::from_bits(val as u8)
+    }
+    #[doc = "Selects the clock source glitchlessly, can be changed on-the-fly"]
+    #[inline(always)]
+    pub fn set_src(&mut self, val: super::vals::ClkSysCtrlSrc) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val.to_bits() as u32) & 0x01) << 0usize);
+    }
+    #[doc = "Selects the auxiliary clock source, will glitch when switching"]
+    #[inline(always)]
+    pub const fn auxsrc(&self) -> super::vals::ClkSysCtrlAuxsrc {
+        let val = (self.0 >> 5usize) & 0x07;
+        super::vals::ClkSysCtrlAuxsrc::from_bits(val as u8)
+    }
+    #[doc = "Selects the auxiliary clock source, will glitch when switching"]
+    #[inline(always)]
+    pub fn set_auxsrc(&mut self, val: super::vals::ClkSysCtrlAuxsrc) {
+        self.0 = (self.0 & !(0x07 << 5usize)) | (((val.to_bits() as u32) & 0x07) << 5usize);
+    }
+}
+impl Default for ClkSysCtrl {
+    #[inline(always)]
+    fn default() -> ClkSysCtrl {
+        ClkSysCtrl(0)
+    }
+}
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct ClkSysDiv(pub u32);
+impl ClkSysDiv {
+    #[doc = "Fractional component of the divisor, can be changed on-the-fly"]
+    #[inline(always)]
+    pub const fn frac(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0xffff;
+        val as u16
+    }
+    #[doc = "Fractional component of the divisor, can be changed on-the-fly"]
+    #[inline(always)]
+    pub fn set_frac(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+    }
+    #[doc = "Integer part of clock divisor, 0 -> max+1, can be changed on-the-fly"]
+    #[inline(always)]
+    pub const fn int(&self) -> u16 {
+        let val = (self.0 >> 16usize) & 0xffff;
+        val as u16
+    }
+    #[doc = "Integer part of clock divisor, 0 -> max+1, can be changed on-the-fly"]
+    #[inline(always)]
+    pub fn set_int(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 16usize)) | (((val as u32) & 0xffff) << 16usize);
+    }
+}
+impl Default for ClkSysDiv {
+    #[inline(always)]
+    fn default() -> ClkSysDiv {
+        ClkSysDiv(0)
+    }
+}
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct ClkSysResusCtrl(pub u32);
+impl ClkSysResusCtrl {
+    #[doc = "This is expressed as a number of clk_ref cycles and must be >= 2x clk_ref_freq/min_clk_tst_freq"]
+    #[inline(always)]
+    pub const fn timeout(&self) -> u8 {
+        let val = (self.0 >> 0usize) & 0xff;
+        val as u8
+    }
+    #[doc = "This is expressed as a number of clk_ref cycles and must be >= 2x clk_ref_freq/min_clk_tst_freq"]
+    #[inline(always)]
+    pub fn set_timeout(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize);
+    }
+    #[doc = "Enable resus"]
+    #[inline(always)]
+    pub const fn enable(&self) -> bool {
+        let val = (self.0 >> 8usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Enable resus"]
+    #[inline(always)]
+    pub fn set_enable(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
+    }
+    #[doc = "Force a resus, for test purposes only"]
+    #[inline(always)]
+    pub const fn frce(&self) -> bool {
+        let val = (self.0 >> 12usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Force a resus, for test purposes only"]
+    #[inline(always)]
+    pub fn set_frce(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
+    }
+    #[doc = "For clearing the resus after the fault that triggered it has been corrected"]
+    #[inline(always)]
+    pub const fn clear(&self) -> bool {
+        let val = (self.0 >> 16usize) & 0x01;
+        val != 0
+    }
+    #[doc = "For clearing the resus after the fault that triggered it has been corrected"]
+    #[inline(always)]
+    pub fn set_clear(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
+    }
+}
+impl Default for ClkSysResusCtrl {
+    #[inline(always)]
+    fn default() -> ClkSysResusCtrl {
+        ClkSysResusCtrl(0)
+    }
+}
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct ClkSysResusStatus(pub u32);
+impl ClkSysResusStatus {
+    #[doc = "Clock has been resuscitated, correct the error then send ctrl_clear=1"]
+    #[inline(always)]
+    pub const fn resussed(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Clock has been resuscitated, correct the error then send ctrl_clear=1"]
+    #[inline(always)]
+    pub fn set_resussed(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+}
+impl Default for ClkSysResusStatus {
+    #[inline(always)]
+    fn default() -> ClkSysResusStatus {
+        ClkSysResusStatus(0)
+    }
+}
+#[doc = "Indicates which src is currently selected (one-hot)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct ClkSysSelected(pub u32);
+impl ClkSysSelected {
+    #[doc = "The glitchless multiplexer does not switch instantaneously (to avoid glitches), so software should poll this register to wait for the switch to complete. This register contains one decoded bit for each of the clock sources enumerated in the CTRL SRC field. At most one of these bits will be set at any time, indicating that clock is currently present at the output of the glitchless mux. Whilst switching is in progress, this register may briefly show all-0s."]
+    #[inline(always)]
+    pub const fn clk_sys_selected(&self) -> u8 {
+        let val = (self.0 >> 0usize) & 0x03;
+        val as u8
+    }
+    #[doc = "The glitchless multiplexer does not switch instantaneously (to avoid glitches), so software should poll this register to wait for the switch to complete. This register contains one decoded bit for each of the clock sources enumerated in the CTRL SRC field. At most one of these bits will be set at any time, indicating that clock is currently present at the output of the glitchless mux. Whilst switching is in progress, this register may briefly show all-0s."]
+    #[inline(always)]
+    pub fn set_clk_sys_selected(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x03 << 0usize)) | (((val as u32) & 0x03) << 0usize);
+    }
+}
+impl Default for ClkSysSelected {
+    #[inline(always)]
+    fn default() -> ClkSysSelected {
+        ClkSysSelected(0)
+    }
+}
+#[doc = "Clock control, can be changed on-the-fly (except for auxsrc)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct ClkUsbCtrl(pub u32);
+impl ClkUsbCtrl {
+    #[doc = "Selects the auxiliary clock source, will glitch when switching"]
+    #[inline(always)]
+    pub const fn auxsrc(&self) -> super::vals::ClkUsbCtrlAuxsrc {
+        let val = (self.0 >> 5usize) & 0x07;
+        super::vals::ClkUsbCtrlAuxsrc::from_bits(val as u8)
+    }
+    #[doc = "Selects the auxiliary clock source, will glitch when switching"]
+    #[inline(always)]
+    pub fn set_auxsrc(&mut self, val: super::vals::ClkUsbCtrlAuxsrc) {
+        self.0 = (self.0 & !(0x07 << 5usize)) | (((val.to_bits() as u32) & 0x07) << 5usize);
+    }
+    #[doc = "Asynchronously kills the clock generator, enable must be set low before deasserting kill"]
+    #[inline(always)]
+    pub const fn kill(&self) -> bool {
+        let val = (self.0 >> 10usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Asynchronously kills the clock generator, enable must be set low before deasserting kill"]
+    #[inline(always)]
+    pub fn set_kill(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize);
+    }
+    #[doc = "Starts and stops the clock generator cleanly"]
+    #[inline(always)]
+    pub const fn enable(&self) -> bool {
+        let val = (self.0 >> 11usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Starts and stops the clock generator cleanly"]
+    #[inline(always)]
+    pub fn set_enable(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
+    }
+    #[doc = "This delays the enable signal by up to 3 cycles of the input clock This must be set before the clock is enabled to have any effect"]
+    #[inline(always)]
+    pub const fn phase(&self) -> u8 {
+        let val = (self.0 >> 16usize) & 0x03;
+        val as u8
+    }
+    #[doc = "This delays the enable signal by up to 3 cycles of the input clock This must be set before the clock is enabled to have any effect"]
+    #[inline(always)]
+    pub fn set_phase(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x03 << 16usize)) | (((val as u32) & 0x03) << 16usize);
+    }
+    #[doc = "An edge on this signal shifts the phase of the output by 1 cycle of the input clock This can be done at any time"]
+    #[inline(always)]
+    pub const fn nudge(&self) -> bool {
+        let val = (self.0 >> 20usize) & 0x01;
+        val != 0
+    }
+    #[doc = "An edge on this signal shifts the phase of the output by 1 cycle of the input clock This can be done at any time"]
+    #[inline(always)]
+    pub fn set_nudge(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize);
+    }
+    #[doc = "clock generator is enabled"]
+    #[inline(always)]
+    pub const fn enabled(&self) -> bool {
+        let val = (self.0 >> 28usize) & 0x01;
+        val != 0
+    }
+    #[doc = "clock generator is enabled"]
+    #[inline(always)]
+    pub fn set_enabled(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 28usize)) | (((val as u32) & 0x01) << 28usize);
+    }
+}
+impl Default for ClkUsbCtrl {
+    #[inline(always)]
+    fn default() -> ClkUsbCtrl {
+        ClkUsbCtrl(0)
+    }
+}
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct ClkUsbDiv(pub u32);
+impl ClkUsbDiv {
+    #[doc = "Integer part of clock divisor, 0 -> max+1, can be changed on-the-fly"]
+    #[inline(always)]
+    pub const fn int(&self) -> u8 {
+        let val = (self.0 >> 16usize) & 0x0f;
+        val as u8
+    }
+    #[doc = "Integer part of clock divisor, 0 -> max+1, can be changed on-the-fly"]
+    #[inline(always)]
+    pub fn set_int(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x0f << 16usize)) | (((val as u32) & 0x0f) << 16usize);
+    }
+}
+impl Default for ClkUsbDiv {
+    #[inline(always)]
+    fn default() -> ClkUsbDiv {
+        ClkUsbDiv(0)
+    }
+}
+#[doc = "Indicates which src is currently selected (one-hot)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct ClkUsbSelected(pub u32);
+impl ClkUsbSelected {
+    #[doc = "This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1."]
+    #[inline(always)]
+    pub const fn clk_usb_selected(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1."]
+    #[inline(always)]
+    pub fn set_clk_usb_selected(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+}
+impl Default for ClkUsbSelected {
+    #[inline(always)]
+    fn default() -> ClkUsbSelected {
+        ClkUsbSelected(0)
+    }
+}
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct DftclkLposcCtrl(pub u32);
+impl DftclkLposcCtrl {
+    #[inline(always)]
+    pub const fn src(&self) -> super::vals::DftclkLposcCtrlSrc {
+        let val = (self.0 >> 0usize) & 0x03;
+        super::vals::DftclkLposcCtrlSrc::from_bits(val as u8)
+    }
+    #[inline(always)]
+    pub fn set_src(&mut self, val: super::vals::DftclkLposcCtrlSrc) {
+        self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize);
+    }
+}
+impl Default for DftclkLposcCtrl {
+    #[inline(always)]
+    fn default() -> DftclkLposcCtrl {
+        DftclkLposcCtrl(0)
+    }
+}
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct DftclkRoscCtrl(pub u32);
+impl DftclkRoscCtrl {
+    #[inline(always)]
+    pub const fn src(&self) -> super::vals::DftclkRoscCtrlSrc {
+        let val = (self.0 >> 0usize) & 0x03;
+        super::vals::DftclkRoscCtrlSrc::from_bits(val as u8)
+    }
+    #[inline(always)]
+    pub fn set_src(&mut self, val: super::vals::DftclkRoscCtrlSrc) {
+        self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize);
+    }
+}
+impl Default for DftclkRoscCtrl {
+    #[inline(always)]
+    fn default() -> DftclkRoscCtrl {
+        DftclkRoscCtrl(0)
+    }
+}
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct DftclkXoscCtrl(pub u32);
+impl DftclkXoscCtrl {
+    #[inline(always)]
+    pub const fn src(&self) -> super::vals::DftclkXoscCtrlSrc {
+        let val = (self.0 >> 0usize) & 0x03;
+        super::vals::DftclkXoscCtrlSrc::from_bits(val as u8)
+    }
+    #[inline(always)]
+    pub fn set_src(&mut self, val: super::vals::DftclkXoscCtrlSrc) {
+        self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize);
+    }
+}
+impl Default for DftclkXoscCtrl {
+    #[inline(always)]
+    fn default() -> DftclkXoscCtrl {
+        DftclkXoscCtrl(0)
+    }
+}
+#[doc = "indicates the state of the clock enable"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Enabled0(pub u32);
+impl Enabled0 {
+    #[inline(always)]
+    pub const fn clk_sys_clocks(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_clk_sys_clocks(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[inline(always)]
+    pub const fn clk_sys_accessctrl(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_clk_sys_accessctrl(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+    #[inline(always)]
+    pub const fn clk_adc(&self) -> bool {
+        let val = (self.0 >> 2usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_clk_adc(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+    }
+    #[inline(always)]
+    pub const fn clk_sys_adc(&self) -> bool {
+        let val = (self.0 >> 3usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_clk_sys_adc(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
+    }
+    #[inline(always)]
+    pub const fn clk_sys_bootram(&self) -> bool {
+        let val = (self.0 >> 4usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_clk_sys_bootram(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
+    }
+    #[inline(always)]
+    pub const fn clk_sys_busctrl(&self) -> bool {
+        let val = (self.0 >> 5usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_clk_sys_busctrl(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
+    }
+    #[inline(always)]
+    pub const fn clk_sys_busfabric(&self) -> bool {
+        let val = (self.0 >> 6usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_clk_sys_busfabric(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
+    }
+    #[inline(always)]
+    pub const fn clk_sys_dma(&self) -> bool {
+        let val = (self.0 >> 7usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_clk_sys_dma(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
+    }
+    #[inline(always)]
+    pub const fn clk_sys_glitch_detector(&self) -> bool {
+        let val = (self.0 >> 8usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_clk_sys_glitch_detector(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
+    }
+    #[inline(always)]
+    pub const fn clk_hstx(&self) -> bool {
+        let val = (self.0 >> 9usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_clk_hstx(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
+    }
+    #[inline(always)]
+    pub const fn clk_sys_hstx(&self) -> bool {
+        let val = (self.0 >> 10usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_clk_sys_hstx(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize);
+    }
+    #[inline(always)]
+    pub const fn clk_sys_i2c0(&self) -> bool {
+        let val = (self.0 >> 11usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_clk_sys_i2c0(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
+    }
+    #[inline(always)]
+    pub const fn clk_sys_i2c1(&self) -> bool {
+        let val = (self.0 >> 12usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_clk_sys_i2c1(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
+    }
+    #[inline(always)]
+    pub const fn clk_sys_io(&self) -> bool {
+        let val = (self.0 >> 13usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_clk_sys_io(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize);
+    }
+    #[inline(always)]
+    pub const fn clk_sys_jtag(&self) -> bool {
+        let val = (self.0 >> 14usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_clk_sys_jtag(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize);
+    }
+    #[inline(always)]
+    pub const fn clk_ref_otp(&self) -> bool {
+        let val = (self.0 >> 15usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_clk_ref_otp(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize);
+    }
+    #[inline(always)]
+    pub const fn clk_sys_otp(&self) -> bool {
+        let val = (self.0 >> 16usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_clk_sys_otp(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
+    }
+    #[inline(always)]
+    pub const fn clk_sys_pads(&self) -> bool {
+        let val = (self.0 >> 17usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_clk_sys_pads(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
+    }
+    #[inline(always)]
+    pub const fn clk_sys_pio0(&self) -> bool {
+        let val = (self.0 >> 18usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_clk_sys_pio0(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize);
+    }
+    #[inline(always)]
+    pub const fn clk_sys_pio1(&self) -> bool {
+        let val = (self.0 >> 19usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_clk_sys_pio1(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize);
+    }
+    #[inline(always)]
+    pub const fn clk_sys_pio2(&self) -> bool {
+        let val = (self.0 >> 20usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_clk_sys_pio2(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize);
+    }
+    #[inline(always)]
+    pub const fn clk_sys_pll_sys(&self) -> bool {
+        let val = (self.0 >> 21usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_clk_sys_pll_sys(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 21usize)) | (((val as u32) & 0x01) << 21usize);
+    }
+    #[inline(always)]
+    pub const fn clk_sys_pll_usb(&self) -> bool {
+        let val = (self.0 >> 22usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_clk_sys_pll_usb(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 22usize)) | (((val as u32) & 0x01) << 22usize);
+    }
+    #[inline(always)]
+    pub const fn clk_ref_powman(&self) -> bool {
+        let val = (self.0 >> 23usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_clk_ref_powman(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 23usize)) | (((val as u32) & 0x01) << 23usize);
+    }
+    #[inline(always)]
+    pub const fn clk_sys_powman(&self) -> bool {
+        let val = (self.0 >> 24usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_clk_sys_powman(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 24usize)) | (((val as u32) & 0x01) << 24usize);
+    }
+    #[inline(always)]
+    pub const fn clk_sys_pwm(&self) -> bool {
+        let val = (self.0 >> 25usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_clk_sys_pwm(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 25usize)) | (((val as u32) & 0x01) << 25usize);
+    }
+    #[inline(always)]
+    pub const fn clk_sys_resets(&self) -> bool {
+        let val = (self.0 >> 26usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_clk_sys_resets(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 26usize)) | (((val as u32) & 0x01) << 26usize);
+    }
+    #[inline(always)]
+    pub const fn clk_sys_rom(&self) -> bool {
+        let val = (self.0 >> 27usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_clk_sys_rom(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 27usize)) | (((val as u32) & 0x01) << 27usize);
+    }
+    #[inline(always)]
+    pub const fn clk_sys_rosc(&self) -> bool {
+        let val = (self.0 >> 28usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_clk_sys_rosc(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 28usize)) | (((val as u32) & 0x01) << 28usize);
+    }
+    #[inline(always)]
+    pub const fn clk_sys_psm(&self) -> bool {
+        let val = (self.0 >> 29usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_clk_sys_psm(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 29usize)) | (((val as u32) & 0x01) << 29usize);
+    }
+    #[inline(always)]
+    pub const fn clk_sys_sha256(&self) -> bool {
+        let val = (self.0 >> 30usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_clk_sys_sha256(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 30usize)) | (((val as u32) & 0x01) << 30usize);
+    }
+    #[inline(always)]
+    pub const fn clk_sys_sio(&self) -> bool {
+        let val = (self.0 >> 31usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_clk_sys_sio(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 31usize)) | (((val as u32) & 0x01) << 31usize);
+    }
+}
+impl Default for Enabled0 {
+    #[inline(always)]
+    fn default() -> Enabled0 {
+        Enabled0(0)
+    }
+}
+#[doc = "indicates the state of the clock enable"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Enabled1(pub u32);
+impl Enabled1 {
+    #[inline(always)]
+    pub const fn clk_peri_spi0(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_clk_peri_spi0(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[inline(always)]
+    pub const fn clk_sys_spi0(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_clk_sys_spi0(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+    #[inline(always)]
+    pub const fn clk_peri_spi1(&self) -> bool {
+        let val = (self.0 >> 2usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_clk_peri_spi1(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+    }
+    #[inline(always)]
+    pub const fn clk_sys_spi1(&self) -> bool {
+        let val = (self.0 >> 3usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_clk_sys_spi1(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
+    }
+    #[inline(always)]
+    pub const fn clk_sys_sram0(&self) -> bool {
+        let val = (self.0 >> 4usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_clk_sys_sram0(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
+    }
+    #[inline(always)]
+    pub const fn clk_sys_sram1(&self) -> bool {
+        let val = (self.0 >> 5usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_clk_sys_sram1(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
+    }
+    #[inline(always)]
+    pub const fn clk_sys_sram2(&self) -> bool {
+        let val = (self.0 >> 6usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_clk_sys_sram2(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
+    }
+    #[inline(always)]
+    pub const fn clk_sys_sram3(&self) -> bool {
+        let val = (self.0 >> 7usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_clk_sys_sram3(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
+    }
+    #[inline(always)]
+    pub const fn clk_sys_sram4(&self) -> bool {
+        let val = (self.0 >> 8usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_clk_sys_sram4(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
+    }
+    #[inline(always)]
+    pub const fn clk_sys_sram5(&self) -> bool {
+        let val = (self.0 >> 9usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_clk_sys_sram5(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
+    }
+    #[inline(always)]
+    pub const fn clk_sys_sram6(&self) -> bool {
+        let val = (self.0 >> 10usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_clk_sys_sram6(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize);
+    }
+    #[inline(always)]
+    pub const fn clk_sys_sram7(&self) -> bool {
+        let val = (self.0 >> 11usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_clk_sys_sram7(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
+    }
+    #[inline(always)]
+    pub const fn clk_sys_sram8(&self) -> bool {
+        let val = (self.0 >> 12usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_clk_sys_sram8(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
+    }
+    #[inline(always)]
+    pub const fn clk_sys_sram9(&self) -> bool {
+        let val = (self.0 >> 13usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_clk_sys_sram9(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize);
+    }
+    #[inline(always)]
+    pub const fn clk_sys_syscfg(&self) -> bool {
+        let val = (self.0 >> 14usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_clk_sys_syscfg(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize);
+    }
+    #[inline(always)]
+    pub const fn clk_sys_sysinfo(&self) -> bool {
+        let val = (self.0 >> 15usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_clk_sys_sysinfo(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize);
+    }
+    #[inline(always)]
+    pub const fn clk_sys_tbman(&self) -> bool {
+        let val = (self.0 >> 16usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_clk_sys_tbman(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
+    }
+    #[inline(always)]
+    pub const fn clk_ref_ticks(&self) -> bool {
+        let val = (self.0 >> 17usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_clk_ref_ticks(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
+    }
+    #[inline(always)]
+    pub const fn clk_sys_ticks(&self) -> bool {
+        let val = (self.0 >> 18usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_clk_sys_ticks(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize);
+    }
+    #[inline(always)]
+    pub const fn clk_sys_timer0(&self) -> bool {
+        let val = (self.0 >> 19usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_clk_sys_timer0(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize);
+    }
+    #[inline(always)]
+    pub const fn clk_sys_timer1(&self) -> bool {
+        let val = (self.0 >> 20usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_clk_sys_timer1(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize);
+    }
+    #[inline(always)]
+    pub const fn clk_sys_trng(&self) -> bool {
+        let val = (self.0 >> 21usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_clk_sys_trng(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 21usize)) | (((val as u32) & 0x01) << 21usize);
+    }
+    #[inline(always)]
+    pub const fn clk_peri_uart0(&self) -> bool {
+        let val = (self.0 >> 22usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_clk_peri_uart0(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 22usize)) | (((val as u32) & 0x01) << 22usize);
+    }
+    #[inline(always)]
+    pub const fn clk_sys_uart0(&self) -> bool {
+        let val = (self.0 >> 23usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_clk_sys_uart0(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 23usize)) | (((val as u32) & 0x01) << 23usize);
+    }
+    #[inline(always)]
+    pub const fn clk_peri_uart1(&self) -> bool {
+        let val = (self.0 >> 24usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_clk_peri_uart1(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 24usize)) | (((val as u32) & 0x01) << 24usize);
+    }
+    #[inline(always)]
+    pub const fn clk_sys_uart1(&self) -> bool {
+        let val = (self.0 >> 25usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_clk_sys_uart1(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 25usize)) | (((val as u32) & 0x01) << 25usize);
+    }
+    #[inline(always)]
+    pub const fn clk_sys_usbctrl(&self) -> bool {
+        let val = (self.0 >> 26usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_clk_sys_usbctrl(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 26usize)) | (((val as u32) & 0x01) << 26usize);
+    }
+    #[inline(always)]
+    pub const fn clk_usb(&self) -> bool {
+        let val = (self.0 >> 27usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_clk_usb(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 27usize)) | (((val as u32) & 0x01) << 27usize);
+    }
+    #[inline(always)]
+    pub const fn clk_sys_watchdog(&self) -> bool {
+        let val = (self.0 >> 28usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_clk_sys_watchdog(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 28usize)) | (((val as u32) & 0x01) << 28usize);
+    }
+    #[inline(always)]
+    pub const fn clk_sys_xip(&self) -> bool {
+        let val = (self.0 >> 29usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_clk_sys_xip(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 29usize)) | (((val as u32) & 0x01) << 29usize);
+    }
+    #[inline(always)]
+    pub const fn clk_sys_xosc(&self) -> bool {
+        let val = (self.0 >> 30usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_clk_sys_xosc(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 30usize)) | (((val as u32) & 0x01) << 30usize);
+    }
+}
+impl Default for Enabled1 {
+    #[inline(always)]
+    fn default() -> Enabled1 {
+        Enabled1(0)
+    }
+}
+#[doc = "Delays the start of frequency counting to allow the mux to settle Delay is measured in multiples of the reference clock period"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Fc0delay(pub u32);
+impl Fc0delay {
+    #[inline(always)]
+    pub const fn fc0_delay(&self) -> u8 {
+        let val = (self.0 >> 0usize) & 0x07;
+        val as u8
+    }
+    #[inline(always)]
+    pub fn set_fc0_delay(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x07 << 0usize)) | (((val as u32) & 0x07) << 0usize);
+    }
+}
+impl Default for Fc0delay {
+    #[inline(always)]
+    fn default() -> Fc0delay {
+        Fc0delay(0)
+    }
+}
+#[doc = "The test interval is 0.98us * 2**interval, but let's call it 1us * 2**interval The default gives a test interval of 250us"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Fc0interval(pub u32);
+impl Fc0interval {
+    #[inline(always)]
+    pub const fn fc0_interval(&self) -> u8 {
+        let val = (self.0 >> 0usize) & 0x0f;
+        val as u8
+    }
+    #[inline(always)]
+    pub fn set_fc0_interval(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize);
+    }
+}
+impl Default for Fc0interval {
+    #[inline(always)]
+    fn default() -> Fc0interval {
+        Fc0interval(0)
+    }
+}
+#[doc = "Maximum pass frequency in kHz. This is optional. Set to 0x1ffffff if you are not using the pass/fail flags"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Fc0maxKhz(pub u32);
+impl Fc0maxKhz {
+    #[inline(always)]
+    pub const fn fc0_max_khz(&self) -> u32 {
+        let val = (self.0 >> 0usize) & 0x01ff_ffff;
+        val as u32
+    }
+    #[inline(always)]
+    pub fn set_fc0_max_khz(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x01ff_ffff << 0usize)) | (((val as u32) & 0x01ff_ffff) << 0usize);
+    }
+}
+impl Default for Fc0maxKhz {
+    #[inline(always)]
+    fn default() -> Fc0maxKhz {
+        Fc0maxKhz(0)
+    }
+}
+#[doc = "Minimum pass frequency in kHz. This is optional. Set to 0 if you are not using the pass/fail flags"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Fc0minKhz(pub u32);
+impl Fc0minKhz {
+    #[inline(always)]
+    pub const fn fc0_min_khz(&self) -> u32 {
+        let val = (self.0 >> 0usize) & 0x01ff_ffff;
+        val as u32
+    }
+    #[inline(always)]
+    pub fn set_fc0_min_khz(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x01ff_ffff << 0usize)) | (((val as u32) & 0x01ff_ffff) << 0usize);
+    }
+}
+impl Default for Fc0minKhz {
+    #[inline(always)]
+    fn default() -> Fc0minKhz {
+        Fc0minKhz(0)
+    }
+}
+#[doc = "Reference clock frequency in kHz"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Fc0refKhz(pub u32);
+impl Fc0refKhz {
+    #[inline(always)]
+    pub const fn fc0_ref_khz(&self) -> u32 {
+        let val = (self.0 >> 0usize) & 0x000f_ffff;
+        val as u32
+    }
+    #[inline(always)]
+    pub fn set_fc0_ref_khz(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x000f_ffff << 0usize)) | (((val as u32) & 0x000f_ffff) << 0usize);
+    }
+}
+impl Default for Fc0refKhz {
+    #[inline(always)]
+    fn default() -> Fc0refKhz {
+        Fc0refKhz(0)
+    }
+}
+#[doc = "Result of frequency measurement, only valid when status_done=1"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Fc0result(pub u32);
+impl Fc0result {
+    #[inline(always)]
+    pub const fn frac(&self) -> u8 {
+        let val = (self.0 >> 0usize) & 0x1f;
+        val as u8
+    }
+    #[inline(always)]
+    pub fn set_frac(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x1f << 0usize)) | (((val as u32) & 0x1f) << 0usize);
+    }
+    #[inline(always)]
+    pub const fn khz(&self) -> u32 {
+        let val = (self.0 >> 5usize) & 0x01ff_ffff;
+        val as u32
+    }
+    #[inline(always)]
+    pub fn set_khz(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x01ff_ffff << 5usize)) | (((val as u32) & 0x01ff_ffff) << 5usize);
+    }
+}
+impl Default for Fc0result {
+    #[inline(always)]
+    fn default() -> Fc0result {
+        Fc0result(0)
+    }
+}
+#[doc = "Clock sent to frequency counter, set to 0 when not required Writing to this register initiates the frequency count"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Fc0src(pub u32);
+impl Fc0src {
+    #[inline(always)]
+    pub const fn fc0_src(&self) -> super::vals::Fc0src {
+        let val = (self.0 >> 0usize) & 0xff;
+        super::vals::Fc0src::from_bits(val as u8)
+    }
+    #[inline(always)]
+    pub fn set_fc0_src(&mut self, val: super::vals::Fc0src) {
+        self.0 = (self.0 & !(0xff << 0usize)) | (((val.to_bits() as u32) & 0xff) << 0usize);
+    }
+}
+impl Default for Fc0src {
+    #[inline(always)]
+    fn default() -> Fc0src {
+        Fc0src(0)
+    }
+}
+#[doc = "Frequency counter status"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Fc0status(pub u32);
+impl Fc0status {
+    #[doc = "Test passed"]
+    #[inline(always)]
+    pub const fn pass(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Test passed"]
+    #[inline(always)]
+    pub fn set_pass(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[doc = "Test complete"]
+    #[inline(always)]
+    pub const fn done(&self) -> bool {
+        let val = (self.0 >> 4usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Test complete"]
+    #[inline(always)]
+    pub fn set_done(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
+    }
+    #[doc = "Test running"]
+    #[inline(always)]
+    pub const fn running(&self) -> bool {
+        let val = (self.0 >> 8usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Test running"]
+    #[inline(always)]
+    pub fn set_running(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
+    }
+    #[doc = "Waiting for test clock to start"]
+    #[inline(always)]
+    pub const fn waiting(&self) -> bool {
+        let val = (self.0 >> 12usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Waiting for test clock to start"]
+    #[inline(always)]
+    pub fn set_waiting(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
+    }
+    #[doc = "Test failed"]
+    #[inline(always)]
+    pub const fn fail(&self) -> bool {
+        let val = (self.0 >> 16usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Test failed"]
+    #[inline(always)]
+    pub fn set_fail(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
+    }
+    #[doc = "Test clock slower than expected, only valid when status_done=1"]
+    #[inline(always)]
+    pub const fn slow(&self) -> bool {
+        let val = (self.0 >> 20usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Test clock slower than expected, only valid when status_done=1"]
+    #[inline(always)]
+    pub fn set_slow(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize);
+    }
+    #[doc = "Test clock faster than expected, only valid when status_done=1"]
+    #[inline(always)]
+    pub const fn fast(&self) -> bool {
+        let val = (self.0 >> 24usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Test clock faster than expected, only valid when status_done=1"]
+    #[inline(always)]
+    pub fn set_fast(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 24usize)) | (((val as u32) & 0x01) << 24usize);
+    }
+    #[doc = "Test clock stopped during test"]
+    #[inline(always)]
+    pub const fn died(&self) -> bool {
+        let val = (self.0 >> 28usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Test clock stopped during test"]
+    #[inline(always)]
+    pub fn set_died(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 28usize)) | (((val as u32) & 0x01) << 28usize);
+    }
+}
+impl Default for Fc0status {
+    #[inline(always)]
+    fn default() -> Fc0status {
+        Fc0status(0)
+    }
+}
+#[doc = "Interrupt Force"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Int(pub u32);
+impl Int {
+    #[inline(always)]
+    pub const fn clk_sys_resus(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_clk_sys_resus(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+}
+impl Default for Int {
+    #[inline(always)]
+    fn default() -> Int {
+        Int(0)
+    }
+}
+#[doc = "enable clock in sleep mode"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct SleepEn0(pub u32);
+impl SleepEn0 {
+    #[inline(always)]
+    pub const fn clk_sys_clocks(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_clk_sys_clocks(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[inline(always)]
+    pub const fn clk_sys_accessctrl(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_clk_sys_accessctrl(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+    #[inline(always)]
+    pub const fn clk_adc(&self) -> bool {
+        let val = (self.0 >> 2usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_clk_adc(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+    }
+    #[inline(always)]
+    pub const fn clk_sys_adc(&self) -> bool {
+        let val = (self.0 >> 3usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_clk_sys_adc(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
+    }
+    #[inline(always)]
+    pub const fn clk_sys_bootram(&self) -> bool {
+        let val = (self.0 >> 4usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_clk_sys_bootram(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
+    }
+    #[inline(always)]
+    pub const fn clk_sys_busctrl(&self) -> bool {
+        let val = (self.0 >> 5usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_clk_sys_busctrl(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
+    }
+    #[inline(always)]
+    pub const fn clk_sys_busfabric(&self) -> bool {
+        let val = (self.0 >> 6usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_clk_sys_busfabric(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
+    }
+    #[inline(always)]
+    pub const fn clk_sys_dma(&self) -> bool {
+        let val = (self.0 >> 7usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_clk_sys_dma(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
+    }
+    #[inline(always)]
+    pub const fn clk_sys_glitch_detector(&self) -> bool {
+        let val = (self.0 >> 8usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_clk_sys_glitch_detector(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
+    }
+    #[inline(always)]
+    pub const fn clk_hstx(&self) -> bool {
+        let val = (self.0 >> 9usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_clk_hstx(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
+    }
+    #[inline(always)]
+    pub const fn clk_sys_hstx(&self) -> bool {
+        let val = (self.0 >> 10usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_clk_sys_hstx(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize);
+    }
+    #[inline(always)]
+    pub const fn clk_sys_i2c0(&self) -> bool {
+        let val = (self.0 >> 11usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_clk_sys_i2c0(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
+    }
+    #[inline(always)]
+    pub const fn clk_sys_i2c1(&self) -> bool {
+        let val = (self.0 >> 12usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_clk_sys_i2c1(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
+    }
+    #[inline(always)]
+    pub const fn clk_sys_io(&self) -> bool {
+        let val = (self.0 >> 13usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_clk_sys_io(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize);
+    }
+    #[inline(always)]
+    pub const fn clk_sys_jtag(&self) -> bool {
+        let val = (self.0 >> 14usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_clk_sys_jtag(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize);
+    }
+    #[inline(always)]
+    pub const fn clk_ref_otp(&self) -> bool {
+        let val = (self.0 >> 15usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_clk_ref_otp(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize);
+    }
+    #[inline(always)]
+    pub const fn clk_sys_otp(&self) -> bool {
+        let val = (self.0 >> 16usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_clk_sys_otp(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
+    }
+    #[inline(always)]
+    pub const fn clk_sys_pads(&self) -> bool {
+        let val = (self.0 >> 17usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_clk_sys_pads(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
+    }
+    #[inline(always)]
+    pub const fn clk_sys_pio0(&self) -> bool {
+        let val = (self.0 >> 18usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_clk_sys_pio0(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize);
+    }
+    #[inline(always)]
+    pub const fn clk_sys_pio1(&self) -> bool {
+        let val = (self.0 >> 19usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_clk_sys_pio1(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize);
+    }
+    #[inline(always)]
+    pub const fn clk_sys_pio2(&self) -> bool {
+        let val = (self.0 >> 20usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_clk_sys_pio2(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize);
+    }
+    #[inline(always)]
+    pub const fn clk_sys_pll_sys(&self) -> bool {
+        let val = (self.0 >> 21usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_clk_sys_pll_sys(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 21usize)) | (((val as u32) & 0x01) << 21usize);
+    }
+    #[inline(always)]
+    pub const fn clk_sys_pll_usb(&self) -> bool {
+        let val = (self.0 >> 22usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_clk_sys_pll_usb(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 22usize)) | (((val as u32) & 0x01) << 22usize);
+    }
+    #[inline(always)]
+    pub const fn clk_ref_powman(&self) -> bool {
+        let val = (self.0 >> 23usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_clk_ref_powman(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 23usize)) | (((val as u32) & 0x01) << 23usize);
+    }
+    #[inline(always)]
+    pub const fn clk_sys_powman(&self) -> bool {
+        let val = (self.0 >> 24usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_clk_sys_powman(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 24usize)) | (((val as u32) & 0x01) << 24usize);
+    }
+    #[inline(always)]
+    pub const fn clk_sys_pwm(&self) -> bool {
+        let val = (self.0 >> 25usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_clk_sys_pwm(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 25usize)) | (((val as u32) & 0x01) << 25usize);
+    }
+    #[inline(always)]
+    pub const fn clk_sys_resets(&self) -> bool {
+        let val = (self.0 >> 26usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_clk_sys_resets(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 26usize)) | (((val as u32) & 0x01) << 26usize);
+    }
+    #[inline(always)]
+    pub const fn clk_sys_rom(&self) -> bool {
+        let val = (self.0 >> 27usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_clk_sys_rom(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 27usize)) | (((val as u32) & 0x01) << 27usize);
+    }
+    #[inline(always)]
+    pub const fn clk_sys_rosc(&self) -> bool {
+        let val = (self.0 >> 28usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_clk_sys_rosc(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 28usize)) | (((val as u32) & 0x01) << 28usize);
+    }
+    #[inline(always)]
+    pub const fn clk_sys_psm(&self) -> bool {
+        let val = (self.0 >> 29usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_clk_sys_psm(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 29usize)) | (((val as u32) & 0x01) << 29usize);
+    }
+    #[inline(always)]
+    pub const fn clk_sys_sha256(&self) -> bool {
+        let val = (self.0 >> 30usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_clk_sys_sha256(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 30usize)) | (((val as u32) & 0x01) << 30usize);
+    }
+    #[inline(always)]
+    pub const fn clk_sys_sio(&self) -> bool {
+        let val = (self.0 >> 31usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_clk_sys_sio(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 31usize)) | (((val as u32) & 0x01) << 31usize);
+    }
+}
+impl Default for SleepEn0 {
+    #[inline(always)]
+    fn default() -> SleepEn0 {
+        SleepEn0(0)
+    }
+}
+#[doc = "enable clock in sleep mode"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct SleepEn1(pub u32);
+impl SleepEn1 {
+    #[inline(always)]
+    pub const fn clk_peri_spi0(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_clk_peri_spi0(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[inline(always)]
+    pub const fn clk_sys_spi0(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_clk_sys_spi0(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+    #[inline(always)]
+    pub const fn clk_peri_spi1(&self) -> bool {
+        let val = (self.0 >> 2usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_clk_peri_spi1(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+    }
+    #[inline(always)]
+    pub const fn clk_sys_spi1(&self) -> bool {
+        let val = (self.0 >> 3usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_clk_sys_spi1(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
+    }
+    #[inline(always)]
+    pub const fn clk_sys_sram0(&self) -> bool {
+        let val = (self.0 >> 4usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_clk_sys_sram0(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
+    }
+    #[inline(always)]
+    pub const fn clk_sys_sram1(&self) -> bool {
+        let val = (self.0 >> 5usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_clk_sys_sram1(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
+    }
+    #[inline(always)]
+    pub const fn clk_sys_sram2(&self) -> bool {
+        let val = (self.0 >> 6usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_clk_sys_sram2(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
+    }
+    #[inline(always)]
+    pub const fn clk_sys_sram3(&self) -> bool {
+        let val = (self.0 >> 7usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_clk_sys_sram3(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
+    }
+    #[inline(always)]
+    pub const fn clk_sys_sram4(&self) -> bool {
+        let val = (self.0 >> 8usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_clk_sys_sram4(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
+    }
+    #[inline(always)]
+    pub const fn clk_sys_sram5(&self) -> bool {
+        let val = (self.0 >> 9usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_clk_sys_sram5(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
+    }
+    #[inline(always)]
+    pub const fn clk_sys_sram6(&self) -> bool {
+        let val = (self.0 >> 10usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_clk_sys_sram6(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize);
+    }
+    #[inline(always)]
+    pub const fn clk_sys_sram7(&self) -> bool {
+        let val = (self.0 >> 11usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_clk_sys_sram7(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
+    }
+    #[inline(always)]
+    pub const fn clk_sys_sram8(&self) -> bool {
+        let val = (self.0 >> 12usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_clk_sys_sram8(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
+    }
+    #[inline(always)]
+    pub const fn clk_sys_sram9(&self) -> bool {
+        let val = (self.0 >> 13usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_clk_sys_sram9(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize);
+    }
+    #[inline(always)]
+    pub const fn clk_sys_syscfg(&self) -> bool {
+        let val = (self.0 >> 14usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_clk_sys_syscfg(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize);
+    }
+    #[inline(always)]
+    pub const fn clk_sys_sysinfo(&self) -> bool {
+        let val = (self.0 >> 15usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_clk_sys_sysinfo(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize);
+    }
+    #[inline(always)]
+    pub const fn clk_sys_tbman(&self) -> bool {
+        let val = (self.0 >> 16usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_clk_sys_tbman(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
+    }
+    #[inline(always)]
+    pub const fn clk_ref_ticks(&self) -> bool {
+        let val = (self.0 >> 17usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_clk_ref_ticks(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
+    }
+    #[inline(always)]
+    pub const fn clk_sys_ticks(&self) -> bool {
+        let val = (self.0 >> 18usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_clk_sys_ticks(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize);
+    }
+    #[inline(always)]
+    pub const fn clk_sys_timer0(&self) -> bool {
+        let val = (self.0 >> 19usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_clk_sys_timer0(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize);
+    }
+    #[inline(always)]
+    pub const fn clk_sys_timer1(&self) -> bool {
+        let val = (self.0 >> 20usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_clk_sys_timer1(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize);
+    }
+    #[inline(always)]
+    pub const fn clk_sys_trng(&self) -> bool {
+        let val = (self.0 >> 21usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_clk_sys_trng(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 21usize)) | (((val as u32) & 0x01) << 21usize);
+    }
+    #[inline(always)]
+    pub const fn clk_peri_uart0(&self) -> bool {
+        let val = (self.0 >> 22usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_clk_peri_uart0(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 22usize)) | (((val as u32) & 0x01) << 22usize);
+    }
+    #[inline(always)]
+    pub const fn clk_sys_uart0(&self) -> bool {
+        let val = (self.0 >> 23usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_clk_sys_uart0(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 23usize)) | (((val as u32) & 0x01) << 23usize);
+    }
+    #[inline(always)]
+    pub const fn clk_peri_uart1(&self) -> bool {
+        let val = (self.0 >> 24usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_clk_peri_uart1(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 24usize)) | (((val as u32) & 0x01) << 24usize);
+    }
+    #[inline(always)]
+    pub const fn clk_sys_uart1(&self) -> bool {
+        let val = (self.0 >> 25usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_clk_sys_uart1(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 25usize)) | (((val as u32) & 0x01) << 25usize);
+    }
+    #[inline(always)]
+    pub const fn clk_sys_usbctrl(&self) -> bool {
+        let val = (self.0 >> 26usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_clk_sys_usbctrl(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 26usize)) | (((val as u32) & 0x01) << 26usize);
+    }
+    #[inline(always)]
+    pub const fn clk_usb(&self) -> bool {
+        let val = (self.0 >> 27usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_clk_usb(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 27usize)) | (((val as u32) & 0x01) << 27usize);
+    }
+    #[inline(always)]
+    pub const fn clk_sys_watchdog(&self) -> bool {
+        let val = (self.0 >> 28usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_clk_sys_watchdog(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 28usize)) | (((val as u32) & 0x01) << 28usize);
+    }
+    #[inline(always)]
+    pub const fn clk_sys_xip(&self) -> bool {
+        let val = (self.0 >> 29usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_clk_sys_xip(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 29usize)) | (((val as u32) & 0x01) << 29usize);
+    }
+    #[inline(always)]
+    pub const fn clk_sys_xosc(&self) -> bool {
+        let val = (self.0 >> 30usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_clk_sys_xosc(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 30usize)) | (((val as u32) & 0x01) << 30usize);
+    }
+}
+impl Default for SleepEn1 {
+    #[inline(always)]
+    fn default() -> SleepEn1 {
+        SleepEn1(0)
+    }
+}
+#[doc = "enable clock in wake mode"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct WakeEn0(pub u32);
+impl WakeEn0 {
+    #[inline(always)]
+    pub const fn clk_sys_clocks(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_clk_sys_clocks(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[inline(always)]
+    pub const fn clk_sys_accessctrl(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_clk_sys_accessctrl(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+    #[inline(always)]
+    pub const fn clk_adc(&self) -> bool {
+        let val = (self.0 >> 2usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_clk_adc(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+    }
+    #[inline(always)]
+    pub const fn clk_sys_adc(&self) -> bool {
+        let val = (self.0 >> 3usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_clk_sys_adc(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
+    }
+    #[inline(always)]
+    pub const fn clk_sys_bootram(&self) -> bool {
+        let val = (self.0 >> 4usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_clk_sys_bootram(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
+    }
+    #[inline(always)]
+    pub const fn clk_sys_busctrl(&self) -> bool {
+        let val = (self.0 >> 5usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_clk_sys_busctrl(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
+    }
+    #[inline(always)]
+    pub const fn clk_sys_busfabric(&self) -> bool {
+        let val = (self.0 >> 6usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_clk_sys_busfabric(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
+    }
+    #[inline(always)]
+    pub const fn clk_sys_dma(&self) -> bool {
+        let val = (self.0 >> 7usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_clk_sys_dma(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
+    }
+    #[inline(always)]
+    pub const fn clk_sys_glitch_detector(&self) -> bool {
+        let val = (self.0 >> 8usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_clk_sys_glitch_detector(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
+    }
+    #[inline(always)]
+    pub const fn clk_hstx(&self) -> bool {
+        let val = (self.0 >> 9usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_clk_hstx(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
+    }
+    #[inline(always)]
+    pub const fn clk_sys_hstx(&self) -> bool {
+        let val = (self.0 >> 10usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_clk_sys_hstx(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize);
+    }
+    #[inline(always)]
+    pub const fn clk_sys_i2c0(&self) -> bool {
+        let val = (self.0 >> 11usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_clk_sys_i2c0(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
+    }
+    #[inline(always)]
+    pub const fn clk_sys_i2c1(&self) -> bool {
+        let val = (self.0 >> 12usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_clk_sys_i2c1(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
+    }
+    #[inline(always)]
+    pub const fn clk_sys_io(&self) -> bool {
+        let val = (self.0 >> 13usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_clk_sys_io(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize);
+    }
+    #[inline(always)]
+    pub const fn clk_sys_jtag(&self) -> bool {
+        let val = (self.0 >> 14usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_clk_sys_jtag(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize);
+    }
+    #[inline(always)]
+    pub const fn clk_ref_otp(&self) -> bool {
+        let val = (self.0 >> 15usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_clk_ref_otp(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize);
+    }
+    #[inline(always)]
+    pub const fn clk_sys_otp(&self) -> bool {
+        let val = (self.0 >> 16usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_clk_sys_otp(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
+    }
+    #[inline(always)]
+    pub const fn clk_sys_pads(&self) -> bool {
+        let val = (self.0 >> 17usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_clk_sys_pads(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
+    }
+    #[inline(always)]
+    pub const fn clk_sys_pio0(&self) -> bool {
+        let val = (self.0 >> 18usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_clk_sys_pio0(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize);
+    }
+    #[inline(always)]
+    pub const fn clk_sys_pio1(&self) -> bool {
+        let val = (self.0 >> 19usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_clk_sys_pio1(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize);
+    }
+    #[inline(always)]
+    pub const fn clk_sys_pio2(&self) -> bool {
+        let val = (self.0 >> 20usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_clk_sys_pio2(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize);
+    }
+    #[inline(always)]
+    pub const fn clk_sys_pll_sys(&self) -> bool {
+        let val = (self.0 >> 21usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_clk_sys_pll_sys(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 21usize)) | (((val as u32) & 0x01) << 21usize);
+    }
+    #[inline(always)]
+    pub const fn clk_sys_pll_usb(&self) -> bool {
+        let val = (self.0 >> 22usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_clk_sys_pll_usb(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 22usize)) | (((val as u32) & 0x01) << 22usize);
+    }
+    #[inline(always)]
+    pub const fn clk_ref_powman(&self) -> bool {
+        let val = (self.0 >> 23usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_clk_ref_powman(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 23usize)) | (((val as u32) & 0x01) << 23usize);
+    }
+    #[inline(always)]
+    pub const fn clk_sys_powman(&self) -> bool {
+        let val = (self.0 >> 24usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_clk_sys_powman(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 24usize)) | (((val as u32) & 0x01) << 24usize);
+    }
+    #[inline(always)]
+    pub const fn clk_sys_pwm(&self) -> bool {
+        let val = (self.0 >> 25usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_clk_sys_pwm(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 25usize)) | (((val as u32) & 0x01) << 25usize);
+    }
+    #[inline(always)]
+    pub const fn clk_sys_resets(&self) -> bool {
+        let val = (self.0 >> 26usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_clk_sys_resets(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 26usize)) | (((val as u32) & 0x01) << 26usize);
+    }
+    #[inline(always)]
+    pub const fn clk_sys_rom(&self) -> bool {
+        let val = (self.0 >> 27usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_clk_sys_rom(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 27usize)) | (((val as u32) & 0x01) << 27usize);
+    }
+    #[inline(always)]
+    pub const fn clk_sys_rosc(&self) -> bool {
+        let val = (self.0 >> 28usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_clk_sys_rosc(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 28usize)) | (((val as u32) & 0x01) << 28usize);
+    }
+    #[inline(always)]
+    pub const fn clk_sys_psm(&self) -> bool {
+        let val = (self.0 >> 29usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_clk_sys_psm(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 29usize)) | (((val as u32) & 0x01) << 29usize);
+    }
+    #[inline(always)]
+    pub const fn clk_sys_sha256(&self) -> bool {
+        let val = (self.0 >> 30usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_clk_sys_sha256(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 30usize)) | (((val as u32) & 0x01) << 30usize);
+    }
+    #[inline(always)]
+    pub const fn clk_sys_sio(&self) -> bool {
+        let val = (self.0 >> 31usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_clk_sys_sio(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 31usize)) | (((val as u32) & 0x01) << 31usize);
+    }
+}
+impl Default for WakeEn0 {
+    #[inline(always)]
+    fn default() -> WakeEn0 {
+        WakeEn0(0)
+    }
+}
+#[doc = "enable clock in wake mode"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct WakeEn1(pub u32);
+impl WakeEn1 {
+    #[inline(always)]
+    pub const fn clk_peri_spi0(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_clk_peri_spi0(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[inline(always)]
+    pub const fn clk_sys_spi0(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_clk_sys_spi0(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+    #[inline(always)]
+    pub const fn clk_peri_spi1(&self) -> bool {
+        let val = (self.0 >> 2usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_clk_peri_spi1(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+    }
+    #[inline(always)]
+    pub const fn clk_sys_spi1(&self) -> bool {
+        let val = (self.0 >> 3usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_clk_sys_spi1(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
+    }
+    #[inline(always)]
+    pub const fn clk_sys_sram0(&self) -> bool {
+        let val = (self.0 >> 4usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_clk_sys_sram0(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
+    }
+    #[inline(always)]
+    pub const fn clk_sys_sram1(&self) -> bool {
+        let val = (self.0 >> 5usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_clk_sys_sram1(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
+    }
+    #[inline(always)]
+    pub const fn clk_sys_sram2(&self) -> bool {
+        let val = (self.0 >> 6usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_clk_sys_sram2(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
+    }
+    #[inline(always)]
+    pub const fn clk_sys_sram3(&self) -> bool {
+        let val = (self.0 >> 7usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_clk_sys_sram3(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
+    }
+    #[inline(always)]
+    pub const fn clk_sys_sram4(&self) -> bool {
+        let val = (self.0 >> 8usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_clk_sys_sram4(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
+    }
+    #[inline(always)]
+    pub const fn clk_sys_sram5(&self) -> bool {
+        let val = (self.0 >> 9usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_clk_sys_sram5(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
+    }
+    #[inline(always)]
+    pub const fn clk_sys_sram6(&self) -> bool {
+        let val = (self.0 >> 10usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_clk_sys_sram6(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize);
+    }
+    #[inline(always)]
+    pub const fn clk_sys_sram7(&self) -> bool {
+        let val = (self.0 >> 11usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_clk_sys_sram7(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
+    }
+    #[inline(always)]
+    pub const fn clk_sys_sram8(&self) -> bool {
+        let val = (self.0 >> 12usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_clk_sys_sram8(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
+    }
+    #[inline(always)]
+    pub const fn clk_sys_sram9(&self) -> bool {
+        let val = (self.0 >> 13usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_clk_sys_sram9(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize);
+    }
+    #[inline(always)]
+    pub const fn clk_sys_syscfg(&self) -> bool {
+        let val = (self.0 >> 14usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_clk_sys_syscfg(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize);
+    }
+    #[inline(always)]
+    pub const fn clk_sys_sysinfo(&self) -> bool {
+        let val = (self.0 >> 15usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_clk_sys_sysinfo(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize);
+    }
+    #[inline(always)]
+    pub const fn clk_sys_tbman(&self) -> bool {
+        let val = (self.0 >> 16usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_clk_sys_tbman(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
+    }
+    #[inline(always)]
+    pub const fn clk_ref_ticks(&self) -> bool {
+        let val = (self.0 >> 17usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_clk_ref_ticks(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
+    }
+    #[inline(always)]
+    pub const fn clk_sys_ticks(&self) -> bool {
+        let val = (self.0 >> 18usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_clk_sys_ticks(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize);
+    }
+    #[inline(always)]
+    pub const fn clk_sys_timer0(&self) -> bool {
+        let val = (self.0 >> 19usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_clk_sys_timer0(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize);
+    }
+    #[inline(always)]
+    pub const fn clk_sys_timer1(&self) -> bool {
+        let val = (self.0 >> 20usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_clk_sys_timer1(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize);
+    }
+    #[inline(always)]
+    pub const fn clk_sys_trng(&self) -> bool {
+        let val = (self.0 >> 21usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_clk_sys_trng(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 21usize)) | (((val as u32) & 0x01) << 21usize);
+    }
+    #[inline(always)]
+    pub const fn clk_peri_uart0(&self) -> bool {
+        let val = (self.0 >> 22usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_clk_peri_uart0(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 22usize)) | (((val as u32) & 0x01) << 22usize);
+    }
+    #[inline(always)]
+    pub const fn clk_sys_uart0(&self) -> bool {
+        let val = (self.0 >> 23usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_clk_sys_uart0(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 23usize)) | (((val as u32) & 0x01) << 23usize);
+    }
+    #[inline(always)]
+    pub const fn clk_peri_uart1(&self) -> bool {
+        let val = (self.0 >> 24usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_clk_peri_uart1(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 24usize)) | (((val as u32) & 0x01) << 24usize);
+    }
+    #[inline(always)]
+    pub const fn clk_sys_uart1(&self) -> bool {
+        let val = (self.0 >> 25usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_clk_sys_uart1(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 25usize)) | (((val as u32) & 0x01) << 25usize);
+    }
+    #[inline(always)]
+    pub const fn clk_sys_usbctrl(&self) -> bool {
+        let val = (self.0 >> 26usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_clk_sys_usbctrl(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 26usize)) | (((val as u32) & 0x01) << 26usize);
+    }
+    #[inline(always)]
+    pub const fn clk_usb(&self) -> bool {
+        let val = (self.0 >> 27usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_clk_usb(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 27usize)) | (((val as u32) & 0x01) << 27usize);
+    }
+    #[inline(always)]
+    pub const fn clk_sys_watchdog(&self) -> bool {
+        let val = (self.0 >> 28usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_clk_sys_watchdog(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 28usize)) | (((val as u32) & 0x01) << 28usize);
+    }
+    #[inline(always)]
+    pub const fn clk_sys_xip(&self) -> bool {
+        let val = (self.0 >> 29usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_clk_sys_xip(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 29usize)) | (((val as u32) & 0x01) << 29usize);
+    }
+    #[inline(always)]
+    pub const fn clk_sys_xosc(&self) -> bool {
+        let val = (self.0 >> 30usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_clk_sys_xosc(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 30usize)) | (((val as u32) & 0x01) << 30usize);
+    }
+}
+impl Default for WakeEn1 {
+    #[inline(always)]
+    fn default() -> WakeEn1 {
+        WakeEn1(0)
+    }
+}
diff --git a/src/rp2350/clocks/vals.rs b/src/rp2350/clocks/vals.rs
new file mode 100644
index 00000000..de6752eb
--- /dev/null
+++ b/src/rp2350/clocks/vals.rs
@@ -0,0 +1,672 @@
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum ClkAdcCtrlAuxsrc {
+    CLKSRC_PLL_USB = 0,
+    CLKSRC_PLL_SYS = 0x01,
+    ROSC_CLKSRC_PH = 0x02,
+    XOSC_CLKSRC = 0x03,
+    CLKSRC_GPIN0 = 0x04,
+    CLKSRC_GPIN1 = 0x05,
+    _RESERVED_6 = 0x06,
+    _RESERVED_7 = 0x07,
+}
+impl ClkAdcCtrlAuxsrc {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> ClkAdcCtrlAuxsrc {
+        unsafe { core::mem::transmute(val & 0x07) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for ClkAdcCtrlAuxsrc {
+    #[inline(always)]
+    fn from(val: u8) -> ClkAdcCtrlAuxsrc {
+        ClkAdcCtrlAuxsrc::from_bits(val)
+    }
+}
+impl From<ClkAdcCtrlAuxsrc> for u8 {
+    #[inline(always)]
+    fn from(val: ClkAdcCtrlAuxsrc) -> u8 {
+        ClkAdcCtrlAuxsrc::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum ClkGpoutCtrlAuxsrc {
+    CLKSRC_PLL_SYS = 0,
+    CLKSRC_GPIN0 = 0x01,
+    CLKSRC_GPIN1 = 0x02,
+    CLKSRC_PLL_USB = 0x03,
+    CLKSRC_PLL_USB_PRIMARY_REF_OPCG = 0x04,
+    ROSC_CLKSRC = 0x05,
+    XOSC_CLKSRC = 0x06,
+    LPOSC_CLKSRC = 0x07,
+    CLK_SYS = 0x08,
+    CLK_USB = 0x09,
+    CLK_ADC = 0x0a,
+    CLK_REF = 0x0b,
+    CLK_PERI = 0x0c,
+    CLK_HSTX = 0x0d,
+    OTP_CLK2FC = 0x0e,
+    _RESERVED_f = 0x0f,
+}
+impl ClkGpoutCtrlAuxsrc {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> ClkGpoutCtrlAuxsrc {
+        unsafe { core::mem::transmute(val & 0x0f) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for ClkGpoutCtrlAuxsrc {
+    #[inline(always)]
+    fn from(val: u8) -> ClkGpoutCtrlAuxsrc {
+        ClkGpoutCtrlAuxsrc::from_bits(val)
+    }
+}
+impl From<ClkGpoutCtrlAuxsrc> for u8 {
+    #[inline(always)]
+    fn from(val: ClkGpoutCtrlAuxsrc) -> u8 {
+        ClkGpoutCtrlAuxsrc::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum ClkHstxCtrlAuxsrc {
+    CLK_SYS = 0,
+    CLKSRC_PLL_SYS = 0x01,
+    CLKSRC_PLL_USB = 0x02,
+    CLKSRC_GPIN0 = 0x03,
+    CLKSRC_GPIN1 = 0x04,
+    _RESERVED_5 = 0x05,
+    _RESERVED_6 = 0x06,
+    _RESERVED_7 = 0x07,
+}
+impl ClkHstxCtrlAuxsrc {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> ClkHstxCtrlAuxsrc {
+        unsafe { core::mem::transmute(val & 0x07) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for ClkHstxCtrlAuxsrc {
+    #[inline(always)]
+    fn from(val: u8) -> ClkHstxCtrlAuxsrc {
+        ClkHstxCtrlAuxsrc::from_bits(val)
+    }
+}
+impl From<ClkHstxCtrlAuxsrc> for u8 {
+    #[inline(always)]
+    fn from(val: ClkHstxCtrlAuxsrc) -> u8 {
+        ClkHstxCtrlAuxsrc::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum ClkPeriCtrlAuxsrc {
+    CLK_SYS = 0,
+    CLKSRC_PLL_SYS = 0x01,
+    CLKSRC_PLL_USB = 0x02,
+    ROSC_CLKSRC_PH = 0x03,
+    XOSC_CLKSRC = 0x04,
+    CLKSRC_GPIN0 = 0x05,
+    CLKSRC_GPIN1 = 0x06,
+    _RESERVED_7 = 0x07,
+}
+impl ClkPeriCtrlAuxsrc {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> ClkPeriCtrlAuxsrc {
+        unsafe { core::mem::transmute(val & 0x07) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for ClkPeriCtrlAuxsrc {
+    #[inline(always)]
+    fn from(val: u8) -> ClkPeriCtrlAuxsrc {
+        ClkPeriCtrlAuxsrc::from_bits(val)
+    }
+}
+impl From<ClkPeriCtrlAuxsrc> for u8 {
+    #[inline(always)]
+    fn from(val: ClkPeriCtrlAuxsrc) -> u8 {
+        ClkPeriCtrlAuxsrc::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum ClkRefCtrlAuxsrc {
+    CLKSRC_PLL_USB = 0,
+    CLKSRC_GPIN0 = 0x01,
+    CLKSRC_GPIN1 = 0x02,
+    CLKSRC_PLL_USB_PRIMARY_REF_OPCG = 0x03,
+}
+impl ClkRefCtrlAuxsrc {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> ClkRefCtrlAuxsrc {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for ClkRefCtrlAuxsrc {
+    #[inline(always)]
+    fn from(val: u8) -> ClkRefCtrlAuxsrc {
+        ClkRefCtrlAuxsrc::from_bits(val)
+    }
+}
+impl From<ClkRefCtrlAuxsrc> for u8 {
+    #[inline(always)]
+    fn from(val: ClkRefCtrlAuxsrc) -> u8 {
+        ClkRefCtrlAuxsrc::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum ClkRefCtrlSrc {
+    ROSC_CLKSRC_PH = 0,
+    CLKSRC_CLK_REF_AUX = 0x01,
+    XOSC_CLKSRC = 0x02,
+    LPOSC_CLKSRC = 0x03,
+}
+impl ClkRefCtrlSrc {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> ClkRefCtrlSrc {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for ClkRefCtrlSrc {
+    #[inline(always)]
+    fn from(val: u8) -> ClkRefCtrlSrc {
+        ClkRefCtrlSrc::from_bits(val)
+    }
+}
+impl From<ClkRefCtrlSrc> for u8 {
+    #[inline(always)]
+    fn from(val: ClkRefCtrlSrc) -> u8 {
+        ClkRefCtrlSrc::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum ClkSysCtrlAuxsrc {
+    CLKSRC_PLL_SYS = 0,
+    CLKSRC_PLL_USB = 0x01,
+    ROSC_CLKSRC = 0x02,
+    XOSC_CLKSRC = 0x03,
+    CLKSRC_GPIN0 = 0x04,
+    CLKSRC_GPIN1 = 0x05,
+    _RESERVED_6 = 0x06,
+    _RESERVED_7 = 0x07,
+}
+impl ClkSysCtrlAuxsrc {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> ClkSysCtrlAuxsrc {
+        unsafe { core::mem::transmute(val & 0x07) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for ClkSysCtrlAuxsrc {
+    #[inline(always)]
+    fn from(val: u8) -> ClkSysCtrlAuxsrc {
+        ClkSysCtrlAuxsrc::from_bits(val)
+    }
+}
+impl From<ClkSysCtrlAuxsrc> for u8 {
+    #[inline(always)]
+    fn from(val: ClkSysCtrlAuxsrc) -> u8 {
+        ClkSysCtrlAuxsrc::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum ClkSysCtrlSrc {
+    CLK_REF = 0,
+    CLKSRC_CLK_SYS_AUX = 0x01,
+}
+impl ClkSysCtrlSrc {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> ClkSysCtrlSrc {
+        unsafe { core::mem::transmute(val & 0x01) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for ClkSysCtrlSrc {
+    #[inline(always)]
+    fn from(val: u8) -> ClkSysCtrlSrc {
+        ClkSysCtrlSrc::from_bits(val)
+    }
+}
+impl From<ClkSysCtrlSrc> for u8 {
+    #[inline(always)]
+    fn from(val: ClkSysCtrlSrc) -> u8 {
+        ClkSysCtrlSrc::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum ClkUsbCtrlAuxsrc {
+    CLKSRC_PLL_USB = 0,
+    CLKSRC_PLL_SYS = 0x01,
+    ROSC_CLKSRC_PH = 0x02,
+    XOSC_CLKSRC = 0x03,
+    CLKSRC_GPIN0 = 0x04,
+    CLKSRC_GPIN1 = 0x05,
+    _RESERVED_6 = 0x06,
+    _RESERVED_7 = 0x07,
+}
+impl ClkUsbCtrlAuxsrc {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> ClkUsbCtrlAuxsrc {
+        unsafe { core::mem::transmute(val & 0x07) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for ClkUsbCtrlAuxsrc {
+    #[inline(always)]
+    fn from(val: u8) -> ClkUsbCtrlAuxsrc {
+        ClkUsbCtrlAuxsrc::from_bits(val)
+    }
+}
+impl From<ClkUsbCtrlAuxsrc> for u8 {
+    #[inline(always)]
+    fn from(val: ClkUsbCtrlAuxsrc) -> u8 {
+        ClkUsbCtrlAuxsrc::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum DftclkLposcCtrlSrc {
+    NULL = 0,
+    CLKSRC_PLL_USB_PRIMARY_LPOSC = 0x01,
+    CLKSRC_GPIN1 = 0x02,
+    _RESERVED_3 = 0x03,
+}
+impl DftclkLposcCtrlSrc {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> DftclkLposcCtrlSrc {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for DftclkLposcCtrlSrc {
+    #[inline(always)]
+    fn from(val: u8) -> DftclkLposcCtrlSrc {
+        DftclkLposcCtrlSrc::from_bits(val)
+    }
+}
+impl From<DftclkLposcCtrlSrc> for u8 {
+    #[inline(always)]
+    fn from(val: DftclkLposcCtrlSrc) -> u8 {
+        DftclkLposcCtrlSrc::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum DftclkRoscCtrlSrc {
+    NULL = 0,
+    CLKSRC_PLL_SYS_PRIMARY_ROSC = 0x01,
+    CLKSRC_GPIN1 = 0x02,
+    _RESERVED_3 = 0x03,
+}
+impl DftclkRoscCtrlSrc {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> DftclkRoscCtrlSrc {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for DftclkRoscCtrlSrc {
+    #[inline(always)]
+    fn from(val: u8) -> DftclkRoscCtrlSrc {
+        DftclkRoscCtrlSrc::from_bits(val)
+    }
+}
+impl From<DftclkRoscCtrlSrc> for u8 {
+    #[inline(always)]
+    fn from(val: DftclkRoscCtrlSrc) -> u8 {
+        DftclkRoscCtrlSrc::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum DftclkXoscCtrlSrc {
+    NULL = 0,
+    CLKSRC_PLL_USB_PRIMARY = 0x01,
+    CLKSRC_GPIN0 = 0x02,
+    _RESERVED_3 = 0x03,
+}
+impl DftclkXoscCtrlSrc {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> DftclkXoscCtrlSrc {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for DftclkXoscCtrlSrc {
+    #[inline(always)]
+    fn from(val: u8) -> DftclkXoscCtrlSrc {
+        DftclkXoscCtrlSrc::from_bits(val)
+    }
+}
+impl From<DftclkXoscCtrlSrc> for u8 {
+    #[inline(always)]
+    fn from(val: DftclkXoscCtrlSrc) -> u8 {
+        DftclkXoscCtrlSrc::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Fc0src {
+    NULL = 0,
+    PLL_SYS_CLKSRC_PRIMARY = 0x01,
+    PLL_USB_CLKSRC_PRIMARY = 0x02,
+    ROSC_CLKSRC = 0x03,
+    ROSC_CLKSRC_PH = 0x04,
+    XOSC_CLKSRC = 0x05,
+    CLKSRC_GPIN0 = 0x06,
+    CLKSRC_GPIN1 = 0x07,
+    CLK_REF = 0x08,
+    CLK_SYS = 0x09,
+    CLK_PERI = 0x0a,
+    CLK_USB = 0x0b,
+    CLK_ADC = 0x0c,
+    CLK_HSTX = 0x0d,
+    LPOSC_CLKSRC = 0x0e,
+    OTP_CLK2FC = 0x0f,
+    PLL_USB_CLKSRC_PRIMARY_DFT = 0x10,
+    _RESERVED_11 = 0x11,
+    _RESERVED_12 = 0x12,
+    _RESERVED_13 = 0x13,
+    _RESERVED_14 = 0x14,
+    _RESERVED_15 = 0x15,
+    _RESERVED_16 = 0x16,
+    _RESERVED_17 = 0x17,
+    _RESERVED_18 = 0x18,
+    _RESERVED_19 = 0x19,
+    _RESERVED_1a = 0x1a,
+    _RESERVED_1b = 0x1b,
+    _RESERVED_1c = 0x1c,
+    _RESERVED_1d = 0x1d,
+    _RESERVED_1e = 0x1e,
+    _RESERVED_1f = 0x1f,
+    _RESERVED_20 = 0x20,
+    _RESERVED_21 = 0x21,
+    _RESERVED_22 = 0x22,
+    _RESERVED_23 = 0x23,
+    _RESERVED_24 = 0x24,
+    _RESERVED_25 = 0x25,
+    _RESERVED_26 = 0x26,
+    _RESERVED_27 = 0x27,
+    _RESERVED_28 = 0x28,
+    _RESERVED_29 = 0x29,
+    _RESERVED_2a = 0x2a,
+    _RESERVED_2b = 0x2b,
+    _RESERVED_2c = 0x2c,
+    _RESERVED_2d = 0x2d,
+    _RESERVED_2e = 0x2e,
+    _RESERVED_2f = 0x2f,
+    _RESERVED_30 = 0x30,
+    _RESERVED_31 = 0x31,
+    _RESERVED_32 = 0x32,
+    _RESERVED_33 = 0x33,
+    _RESERVED_34 = 0x34,
+    _RESERVED_35 = 0x35,
+    _RESERVED_36 = 0x36,
+    _RESERVED_37 = 0x37,
+    _RESERVED_38 = 0x38,
+    _RESERVED_39 = 0x39,
+    _RESERVED_3a = 0x3a,
+    _RESERVED_3b = 0x3b,
+    _RESERVED_3c = 0x3c,
+    _RESERVED_3d = 0x3d,
+    _RESERVED_3e = 0x3e,
+    _RESERVED_3f = 0x3f,
+    _RESERVED_40 = 0x40,
+    _RESERVED_41 = 0x41,
+    _RESERVED_42 = 0x42,
+    _RESERVED_43 = 0x43,
+    _RESERVED_44 = 0x44,
+    _RESERVED_45 = 0x45,
+    _RESERVED_46 = 0x46,
+    _RESERVED_47 = 0x47,
+    _RESERVED_48 = 0x48,
+    _RESERVED_49 = 0x49,
+    _RESERVED_4a = 0x4a,
+    _RESERVED_4b = 0x4b,
+    _RESERVED_4c = 0x4c,
+    _RESERVED_4d = 0x4d,
+    _RESERVED_4e = 0x4e,
+    _RESERVED_4f = 0x4f,
+    _RESERVED_50 = 0x50,
+    _RESERVED_51 = 0x51,
+    _RESERVED_52 = 0x52,
+    _RESERVED_53 = 0x53,
+    _RESERVED_54 = 0x54,
+    _RESERVED_55 = 0x55,
+    _RESERVED_56 = 0x56,
+    _RESERVED_57 = 0x57,
+    _RESERVED_58 = 0x58,
+    _RESERVED_59 = 0x59,
+    _RESERVED_5a = 0x5a,
+    _RESERVED_5b = 0x5b,
+    _RESERVED_5c = 0x5c,
+    _RESERVED_5d = 0x5d,
+    _RESERVED_5e = 0x5e,
+    _RESERVED_5f = 0x5f,
+    _RESERVED_60 = 0x60,
+    _RESERVED_61 = 0x61,
+    _RESERVED_62 = 0x62,
+    _RESERVED_63 = 0x63,
+    _RESERVED_64 = 0x64,
+    _RESERVED_65 = 0x65,
+    _RESERVED_66 = 0x66,
+    _RESERVED_67 = 0x67,
+    _RESERVED_68 = 0x68,
+    _RESERVED_69 = 0x69,
+    _RESERVED_6a = 0x6a,
+    _RESERVED_6b = 0x6b,
+    _RESERVED_6c = 0x6c,
+    _RESERVED_6d = 0x6d,
+    _RESERVED_6e = 0x6e,
+    _RESERVED_6f = 0x6f,
+    _RESERVED_70 = 0x70,
+    _RESERVED_71 = 0x71,
+    _RESERVED_72 = 0x72,
+    _RESERVED_73 = 0x73,
+    _RESERVED_74 = 0x74,
+    _RESERVED_75 = 0x75,
+    _RESERVED_76 = 0x76,
+    _RESERVED_77 = 0x77,
+    _RESERVED_78 = 0x78,
+    _RESERVED_79 = 0x79,
+    _RESERVED_7a = 0x7a,
+    _RESERVED_7b = 0x7b,
+    _RESERVED_7c = 0x7c,
+    _RESERVED_7d = 0x7d,
+    _RESERVED_7e = 0x7e,
+    _RESERVED_7f = 0x7f,
+    _RESERVED_80 = 0x80,
+    _RESERVED_81 = 0x81,
+    _RESERVED_82 = 0x82,
+    _RESERVED_83 = 0x83,
+    _RESERVED_84 = 0x84,
+    _RESERVED_85 = 0x85,
+    _RESERVED_86 = 0x86,
+    _RESERVED_87 = 0x87,
+    _RESERVED_88 = 0x88,
+    _RESERVED_89 = 0x89,
+    _RESERVED_8a = 0x8a,
+    _RESERVED_8b = 0x8b,
+    _RESERVED_8c = 0x8c,
+    _RESERVED_8d = 0x8d,
+    _RESERVED_8e = 0x8e,
+    _RESERVED_8f = 0x8f,
+    _RESERVED_90 = 0x90,
+    _RESERVED_91 = 0x91,
+    _RESERVED_92 = 0x92,
+    _RESERVED_93 = 0x93,
+    _RESERVED_94 = 0x94,
+    _RESERVED_95 = 0x95,
+    _RESERVED_96 = 0x96,
+    _RESERVED_97 = 0x97,
+    _RESERVED_98 = 0x98,
+    _RESERVED_99 = 0x99,
+    _RESERVED_9a = 0x9a,
+    _RESERVED_9b = 0x9b,
+    _RESERVED_9c = 0x9c,
+    _RESERVED_9d = 0x9d,
+    _RESERVED_9e = 0x9e,
+    _RESERVED_9f = 0x9f,
+    _RESERVED_a0 = 0xa0,
+    _RESERVED_a1 = 0xa1,
+    _RESERVED_a2 = 0xa2,
+    _RESERVED_a3 = 0xa3,
+    _RESERVED_a4 = 0xa4,
+    _RESERVED_a5 = 0xa5,
+    _RESERVED_a6 = 0xa6,
+    _RESERVED_a7 = 0xa7,
+    _RESERVED_a8 = 0xa8,
+    _RESERVED_a9 = 0xa9,
+    _RESERVED_aa = 0xaa,
+    _RESERVED_ab = 0xab,
+    _RESERVED_ac = 0xac,
+    _RESERVED_ad = 0xad,
+    _RESERVED_ae = 0xae,
+    _RESERVED_af = 0xaf,
+    _RESERVED_b0 = 0xb0,
+    _RESERVED_b1 = 0xb1,
+    _RESERVED_b2 = 0xb2,
+    _RESERVED_b3 = 0xb3,
+    _RESERVED_b4 = 0xb4,
+    _RESERVED_b5 = 0xb5,
+    _RESERVED_b6 = 0xb6,
+    _RESERVED_b7 = 0xb7,
+    _RESERVED_b8 = 0xb8,
+    _RESERVED_b9 = 0xb9,
+    _RESERVED_ba = 0xba,
+    _RESERVED_bb = 0xbb,
+    _RESERVED_bc = 0xbc,
+    _RESERVED_bd = 0xbd,
+    _RESERVED_be = 0xbe,
+    _RESERVED_bf = 0xbf,
+    _RESERVED_c0 = 0xc0,
+    _RESERVED_c1 = 0xc1,
+    _RESERVED_c2 = 0xc2,
+    _RESERVED_c3 = 0xc3,
+    _RESERVED_c4 = 0xc4,
+    _RESERVED_c5 = 0xc5,
+    _RESERVED_c6 = 0xc6,
+    _RESERVED_c7 = 0xc7,
+    _RESERVED_c8 = 0xc8,
+    _RESERVED_c9 = 0xc9,
+    _RESERVED_ca = 0xca,
+    _RESERVED_cb = 0xcb,
+    _RESERVED_cc = 0xcc,
+    _RESERVED_cd = 0xcd,
+    _RESERVED_ce = 0xce,
+    _RESERVED_cf = 0xcf,
+    _RESERVED_d0 = 0xd0,
+    _RESERVED_d1 = 0xd1,
+    _RESERVED_d2 = 0xd2,
+    _RESERVED_d3 = 0xd3,
+    _RESERVED_d4 = 0xd4,
+    _RESERVED_d5 = 0xd5,
+    _RESERVED_d6 = 0xd6,
+    _RESERVED_d7 = 0xd7,
+    _RESERVED_d8 = 0xd8,
+    _RESERVED_d9 = 0xd9,
+    _RESERVED_da = 0xda,
+    _RESERVED_db = 0xdb,
+    _RESERVED_dc = 0xdc,
+    _RESERVED_dd = 0xdd,
+    _RESERVED_de = 0xde,
+    _RESERVED_df = 0xdf,
+    _RESERVED_e0 = 0xe0,
+    _RESERVED_e1 = 0xe1,
+    _RESERVED_e2 = 0xe2,
+    _RESERVED_e3 = 0xe3,
+    _RESERVED_e4 = 0xe4,
+    _RESERVED_e5 = 0xe5,
+    _RESERVED_e6 = 0xe6,
+    _RESERVED_e7 = 0xe7,
+    _RESERVED_e8 = 0xe8,
+    _RESERVED_e9 = 0xe9,
+    _RESERVED_ea = 0xea,
+    _RESERVED_eb = 0xeb,
+    _RESERVED_ec = 0xec,
+    _RESERVED_ed = 0xed,
+    _RESERVED_ee = 0xee,
+    _RESERVED_ef = 0xef,
+    _RESERVED_f0 = 0xf0,
+    _RESERVED_f1 = 0xf1,
+    _RESERVED_f2 = 0xf2,
+    _RESERVED_f3 = 0xf3,
+    _RESERVED_f4 = 0xf4,
+    _RESERVED_f5 = 0xf5,
+    _RESERVED_f6 = 0xf6,
+    _RESERVED_f7 = 0xf7,
+    _RESERVED_f8 = 0xf8,
+    _RESERVED_f9 = 0xf9,
+    _RESERVED_fa = 0xfa,
+    _RESERVED_fb = 0xfb,
+    _RESERVED_fc = 0xfc,
+    _RESERVED_fd = 0xfd,
+    _RESERVED_fe = 0xfe,
+    _RESERVED_ff = 0xff,
+}
+impl Fc0src {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Fc0src {
+        unsafe { core::mem::transmute(val & 0xff) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Fc0src {
+    #[inline(always)]
+    fn from(val: u8) -> Fc0src {
+        Fc0src::from_bits(val)
+    }
+}
+impl From<Fc0src> for u8 {
+    #[inline(always)]
+    fn from(val: Fc0src) -> u8 {
+        Fc0src::to_bits(val)
+    }
+}
diff --git a/src/rp2350/common.rs b/src/rp2350/common.rs
new file mode 100644
index 00000000..d978ddba
--- /dev/null
+++ b/src/rp2350/common.rs
@@ -0,0 +1,68 @@
+use core::marker::PhantomData;
+#[derive(Copy, Clone, PartialEq, Eq)]
+pub struct RW;
+#[derive(Copy, Clone, PartialEq, Eq)]
+pub struct R;
+#[derive(Copy, Clone, PartialEq, Eq)]
+pub struct W;
+mod sealed;
+pub trait Access: sealed::Access + Copy {}
+impl Access for R {}
+impl Access for W {}
+impl Access for RW {}
+pub trait Read: Access {}
+impl Read for RW {}
+impl Read for R {}
+pub trait Write: Access {}
+impl Write for RW {}
+impl Write for W {}
+#[derive(Copy, Clone, PartialEq, Eq)]
+pub struct Reg<T: Copy, A: Access> {
+    ptr: *mut u8,
+    phantom: PhantomData<*mut (T, A)>,
+}
+unsafe impl<T: Copy, A: Access> Send for Reg<T, A> {}
+unsafe impl<T: Copy, A: Access> Sync for Reg<T, A> {}
+impl<T: Copy, A: Access> Reg<T, A> {
+    #[inline(always)]
+    pub const unsafe fn from_ptr(ptr: *mut T) -> Self {
+        Self {
+            ptr: ptr as _,
+            phantom: PhantomData,
+        }
+    }
+    #[inline(always)]
+    pub const fn as_ptr(&self) -> *mut T {
+        self.ptr as _
+    }
+}
+impl<T: Copy, A: Read> Reg<T, A> {
+    #[inline(always)]
+    pub fn read(&self) -> T {
+        unsafe { (self.ptr as *mut T).read_volatile() }
+    }
+}
+impl<T: Copy, A: Write> Reg<T, A> {
+    #[inline(always)]
+    pub fn write_value(&self, val: T) {
+        unsafe { (self.ptr as *mut T).write_volatile(val) }
+    }
+}
+impl<T: Default + Copy, A: Write> Reg<T, A> {
+    #[inline(always)]
+    pub fn write<R>(&self, f: impl FnOnce(&mut T) -> R) -> R {
+        let mut val = Default::default();
+        let res = f(&mut val);
+        self.write_value(val);
+        res
+    }
+}
+impl<T: Copy, A: Read + Write> Reg<T, A> {
+    #[inline(always)]
+    pub fn modify<R>(&self, f: impl FnOnce(&mut T) -> R) -> R {
+        let mut val = self.read();
+        let res = f(&mut val);
+        self.write_value(val);
+        res
+    }
+}
diff --git a/src/rp2350/common/sealed.rs b/src/rp2350/common/sealed.rs
new file mode 100644
index 00000000..ca8ba207
--- /dev/null
+++ b/src/rp2350/common/sealed.rs
@@ -0,0 +1,5 @@
+use super::*;
+pub trait Access {}
+impl Access for R {}
+impl Access for W {}
+impl Access for RW {}
diff --git a/src/rp2350/coresight_trace.rs b/src/rp2350/coresight_trace.rs
new file mode 100644
index 00000000..fa01ad9c
--- /dev/null
+++ b/src/rp2350/coresight_trace.rs
@@ -0,0 +1,28 @@
+#[doc = "Coresight block - RP specific registers"]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct CoresightTrace {
+    ptr: *mut u8,
+}
+unsafe impl Send for CoresightTrace {}
+unsafe impl Sync for CoresightTrace {}
+impl CoresightTrace {
+    #[inline(always)]
+    pub const unsafe fn from_ptr(ptr: *mut ()) -> Self {
+        Self { ptr: ptr as _ }
+    }
+    #[inline(always)]
+    pub const fn as_ptr(&self) -> *mut () {
+        self.ptr as _
+    }
+    #[doc = "Control and status register"]
+    #[inline(always)]
+    pub const fn ctrl_status(self) -> crate::common::Reg<regs::CtrlStatus, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(0usize) as _) }
+    }
+    #[doc = "FIFO for trace data captured from the TPIU"]
+    #[inline(always)]
+    pub const fn trace_capture_fifo(self) -> crate::common::Reg<u32, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(4usize) as _) }
+    }
+}
+pub mod regs;
diff --git a/src/rp2350/coresight_trace/regs.rs b/src/rp2350/coresight_trace/regs.rs
new file mode 100644
index 00000000..b10bea3c
--- /dev/null
+++ b/src/rp2350/coresight_trace/regs.rs
@@ -0,0 +1,34 @@
+#[doc = "Control and status register"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct CtrlStatus(pub u32);
+impl CtrlStatus {
+    #[doc = "Set to 1 to continuously hold the trace FIFO in a flushed state and prevent overflow. Before clearing this flag, configure and start a DMA channel with the correct DREQ for the TRACE_CAPTURE_FIFO register. Clear this flag to begin sampling trace data, and set once again once the trace capture buffer is full. You must configure the TPIU in order to generate trace packets to be captured, as well as components like the ETM further upstream to generate the event stream propagated to the TPIU."]
+    #[inline(always)]
+    pub const fn trace_capture_fifo_flush(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Set to 1 to continuously hold the trace FIFO in a flushed state and prevent overflow. Before clearing this flag, configure and start a DMA channel with the correct DREQ for the TRACE_CAPTURE_FIFO register. Clear this flag to begin sampling trace data, and set once again once the trace capture buffer is full. You must configure the TPIU in order to generate trace packets to be captured, as well as components like the ETM further upstream to generate the event stream propagated to the TPIU."]
+    #[inline(always)]
+    pub fn set_trace_capture_fifo_flush(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[doc = "This status flag is set high when trace data has been dropped due to the FIFO being full at the point trace data was sampled. Write 1 to acknowledge and clear the bit."]
+    #[inline(always)]
+    pub const fn trace_capture_fifo_overflow(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[doc = "This status flag is set high when trace data has been dropped due to the FIFO being full at the point trace data was sampled. Write 1 to acknowledge and clear the bit."]
+    #[inline(always)]
+    pub fn set_trace_capture_fifo_overflow(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+}
+impl Default for CtrlStatus {
+    #[inline(always)]
+    fn default() -> CtrlStatus {
+        CtrlStatus(0)
+    }
+}
diff --git a/src/rp2350/dma.rs b/src/rp2350/dma.rs
new file mode 100644
index 00000000..1cbad01d
--- /dev/null
+++ b/src/rp2350/dma.rs
@@ -0,0 +1,438 @@
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Channel {
+    ptr: *mut u8,
+}
+unsafe impl Send for Channel {}
+unsafe impl Sync for Channel {}
+impl Channel {
+    #[inline(always)]
+    pub const unsafe fn from_ptr(ptr: *mut ()) -> Self {
+        Self { ptr: ptr as _ }
+    }
+    #[inline(always)]
+    pub const fn as_ptr(&self) -> *mut () {
+        self.ptr as _
+    }
+    #[doc = "DMA Channel 1 Read Address pointer"]
+    #[inline(always)]
+    pub const fn read_addr(self) -> crate::common::Reg<u32, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(0usize) as _) }
+    }
+    #[doc = "DMA Channel 1 Write Address pointer"]
+    #[inline(always)]
+    pub const fn write_addr(self) -> crate::common::Reg<u32, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(4usize) as _) }
+    }
+    #[doc = "DMA Channel 1 Transfer Count"]
+    #[inline(always)]
+    pub const fn trans_count(self) -> crate::common::Reg<regs::Ch1transCount, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(8usize) as _) }
+    }
+    #[doc = "DMA Channel 1 Control and Status"]
+    #[inline(always)]
+    pub const fn ctrl_trig(self) -> crate::common::Reg<regs::CtrlTrig, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(12usize) as _) }
+    }
+    #[doc = "Alias for channel 1 CTRL register"]
+    #[inline(always)]
+    pub const fn al1_ctrl(self) -> crate::common::Reg<u32, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(16usize) as _) }
+    }
+    #[doc = "Alias for channel 1 READ_ADDR register"]
+    #[inline(always)]
+    pub const fn al1_read_addr(self) -> crate::common::Reg<u32, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(20usize) as _) }
+    }
+    #[doc = "Alias for channel 1 WRITE_ADDR register"]
+    #[inline(always)]
+    pub const fn al1_write_addr(self) -> crate::common::Reg<u32, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(24usize) as _) }
+    }
+    #[doc = "Alias for channel 1 TRANS_COUNT register This is a trigger register (0xc). Writing a nonzero value will reload the channel counter and start the channel."]
+    #[inline(always)]
+    pub const fn al1_trans_count_trig(self) -> crate::common::Reg<u32, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(28usize) as _) }
+    }
+    #[doc = "Alias for channel 1 CTRL register"]
+    #[inline(always)]
+    pub const fn al2_ctrl(self) -> crate::common::Reg<u32, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(32usize) as _) }
+    }
+    #[doc = "Alias for channel 1 TRANS_COUNT register"]
+    #[inline(always)]
+    pub const fn al2_trans_count(self) -> crate::common::Reg<u32, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(36usize) as _) }
+    }
+    #[doc = "Alias for channel 1 READ_ADDR register"]
+    #[inline(always)]
+    pub const fn al2_read_addr(self) -> crate::common::Reg<u32, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(40usize) as _) }
+    }
+    #[doc = "Alias for channel 1 WRITE_ADDR register This is a trigger register (0xc). Writing a nonzero value will reload the channel counter and start the channel."]
+    #[inline(always)]
+    pub const fn al2_write_addr_trig(self) -> crate::common::Reg<u32, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(44usize) as _) }
+    }
+    #[doc = "Alias for channel 1 CTRL register"]
+    #[inline(always)]
+    pub const fn al3_ctrl(self) -> crate::common::Reg<u32, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(48usize) as _) }
+    }
+    #[doc = "Alias for channel 1 WRITE_ADDR register"]
+    #[inline(always)]
+    pub const fn al3_write_addr(self) -> crate::common::Reg<u32, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(52usize) as _) }
+    }
+    #[doc = "Alias for channel 1 TRANS_COUNT register"]
+    #[inline(always)]
+    pub const fn al3_trans_count(self) -> crate::common::Reg<u32, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(56usize) as _) }
+    }
+    #[doc = "Alias for channel 1 READ_ADDR register This is a trigger register (0xc). Writing a nonzero value will reload the channel counter and start the channel."]
+    #[inline(always)]
+    pub const fn al3_read_addr_trig(self) -> crate::common::Reg<u32, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(60usize) as _) }
+    }
+    #[doc = "Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake."]
+    #[inline(always)]
+    pub const fn dbg_ctdreq(self) -> crate::common::Reg<regs::DbgCtdreq, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(2048usize) as _) }
+    }
+    #[doc = "Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer"]
+    #[inline(always)]
+    pub const fn dbg_tcr(self) -> crate::common::Reg<u32, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(2052usize) as _) }
+    }
+}
+#[doc = "DMA with separate read and write masters"]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Dma {
+    ptr: *mut u8,
+}
+unsafe impl Send for Dma {}
+unsafe impl Sync for Dma {}
+impl Dma {
+    #[inline(always)]
+    pub const unsafe fn from_ptr(ptr: *mut ()) -> Self {
+        Self { ptr: ptr as _ }
+    }
+    #[inline(always)]
+    pub const fn as_ptr(&self) -> *mut () {
+        self.ptr as _
+    }
+    #[inline(always)]
+    pub const fn ch(self, n: usize) -> Channel {
+        assert!(n < 16usize);
+        unsafe { Channel::from_ptr(self.ptr.add(0usize + n * 64usize) as _) }
+    }
+    #[doc = "Interrupt Status (raw)"]
+    #[inline(always)]
+    pub const fn intr(self) -> crate::common::Reg<regs::Intr, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(1024usize) as _) }
+    }
+    #[doc = "Interrupt Enables for IRQ 0"]
+    #[inline(always)]
+    pub const fn inte0(self) -> crate::common::Reg<regs::Inte0, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(1028usize) as _) }
+    }
+    #[doc = "Force Interrupts"]
+    #[inline(always)]
+    pub const fn intf0(self) -> crate::common::Reg<regs::Intf0, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(1032usize) as _) }
+    }
+    #[doc = "Interrupt Status for IRQ 0"]
+    #[inline(always)]
+    pub const fn ints0(self) -> crate::common::Reg<regs::Ints0, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(1036usize) as _) }
+    }
+    #[doc = "Interrupt Status (raw)"]
+    #[inline(always)]
+    pub const fn intr1(self) -> crate::common::Reg<regs::Intr1, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(1040usize) as _) }
+    }
+    #[doc = "Interrupt Enables for IRQ 1"]
+    #[inline(always)]
+    pub const fn inte1(self) -> crate::common::Reg<regs::Inte1, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(1044usize) as _) }
+    }
+    #[doc = "Force Interrupts"]
+    #[inline(always)]
+    pub const fn intf1(self) -> crate::common::Reg<regs::Intf1, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(1048usize) as _) }
+    }
+    #[doc = "Interrupt Status for IRQ 1"]
+    #[inline(always)]
+    pub const fn ints1(self) -> crate::common::Reg<regs::Ints1, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(1052usize) as _) }
+    }
+    #[doc = "Interrupt Status (raw)"]
+    #[inline(always)]
+    pub const fn intr2(self) -> crate::common::Reg<regs::Intr2, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(1056usize) as _) }
+    }
+    #[doc = "Interrupt Enables for IRQ 2"]
+    #[inline(always)]
+    pub const fn inte2(self) -> crate::common::Reg<regs::Inte2, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(1060usize) as _) }
+    }
+    #[doc = "Force Interrupts"]
+    #[inline(always)]
+    pub const fn intf2(self) -> crate::common::Reg<regs::Intf2, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(1064usize) as _) }
+    }
+    #[doc = "Interrupt Status for IRQ 2"]
+    #[inline(always)]
+    pub const fn ints2(self) -> crate::common::Reg<regs::Ints2, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(1068usize) as _) }
+    }
+    #[doc = "Interrupt Status (raw)"]
+    #[inline(always)]
+    pub const fn intr3(self) -> crate::common::Reg<regs::Intr3, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(1072usize) as _) }
+    }
+    #[doc = "Interrupt Enables for IRQ 3"]
+    #[inline(always)]
+    pub const fn inte3(self) -> crate::common::Reg<regs::Inte3, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(1076usize) as _) }
+    }
+    #[doc = "Force Interrupts"]
+    #[inline(always)]
+    pub const fn intf3(self) -> crate::common::Reg<regs::Intf3, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(1080usize) as _) }
+    }
+    #[doc = "Interrupt Status for IRQ 3"]
+    #[inline(always)]
+    pub const fn ints3(self) -> crate::common::Reg<regs::Ints3, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(1084usize) as _) }
+    }
+    #[doc = "Pacing (X/Y) fractional timer The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less."]
+    #[inline(always)]
+    pub const fn timer(self, n: usize) -> crate::common::Reg<regs::Timer, crate::common::RW> {
+        assert!(n < 4usize);
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(1088usize + n * 4usize) as _) }
+    }
+    #[doc = "Trigger one or more channels simultaneously"]
+    #[inline(always)]
+    pub const fn multi_chan_trigger(
+        self,
+    ) -> crate::common::Reg<regs::MultiChanTrigger, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(1104usize) as _) }
+    }
+    #[doc = "Sniffer Control"]
+    #[inline(always)]
+    pub const fn sniff_ctrl(self) -> crate::common::Reg<regs::SniffCtrl, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(1108usize) as _) }
+    }
+    #[doc = "Data accumulator for sniff hardware"]
+    #[inline(always)]
+    pub const fn sniff_data(self) -> crate::common::Reg<u32, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(1112usize) as _) }
+    }
+    #[doc = "Debug RAF, WAF, TDF levels"]
+    #[inline(always)]
+    pub const fn fifo_levels(self) -> crate::common::Reg<regs::FifoLevels, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(1120usize) as _) }
+    }
+    #[doc = "Abort an in-progress transfer sequence on one or more channels"]
+    #[inline(always)]
+    pub const fn chan_abort(self) -> crate::common::Reg<regs::ChanAbort, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(1124usize) as _) }
+    }
+    #[doc = "The number of channels this DMA instance is equipped with. This DMA supports up to 16 hardware channels, but can be configured with as few as one, to minimise silicon area."]
+    #[inline(always)]
+    pub const fn n_channels(self) -> crate::common::Reg<regs::Nchannels, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(1128usize) as _) }
+    }
+    #[doc = "Security configuration for channel 0. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. This register automatically locks down (becomes read-only) once software starts to configure the channel. This register is world-readable, but is writable only from a Secure, Privileged context."]
+    #[inline(always)]
+    pub const fn seccfg_ch0(self) -> crate::common::Reg<regs::SeccfgCh0, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(1152usize) as _) }
+    }
+    #[doc = "Security configuration for channel 1. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. This register automatically locks down (becomes read-only) once software starts to configure the channel. This register is world-readable, but is writable only from a Secure, Privileged context."]
+    #[inline(always)]
+    pub const fn seccfg_ch1(self) -> crate::common::Reg<regs::SeccfgCh1, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(1156usize) as _) }
+    }
+    #[doc = "Security configuration for channel 2. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. This register automatically locks down (becomes read-only) once software starts to configure the channel. This register is world-readable, but is writable only from a Secure, Privileged context."]
+    #[inline(always)]
+    pub const fn seccfg_ch2(self) -> crate::common::Reg<regs::SeccfgCh2, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(1160usize) as _) }
+    }
+    #[doc = "Security configuration for channel 3. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. This register automatically locks down (becomes read-only) once software starts to configure the channel. This register is world-readable, but is writable only from a Secure, Privileged context."]
+    #[inline(always)]
+    pub const fn seccfg_ch3(self) -> crate::common::Reg<regs::SeccfgCh3, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(1164usize) as _) }
+    }
+    #[doc = "Security configuration for channel 4. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. This register automatically locks down (becomes read-only) once software starts to configure the channel. This register is world-readable, but is writable only from a Secure, Privileged context."]
+    #[inline(always)]
+    pub const fn seccfg_ch4(self) -> crate::common::Reg<regs::SeccfgCh4, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(1168usize) as _) }
+    }
+    #[doc = "Security configuration for channel 5. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. This register automatically locks down (becomes read-only) once software starts to configure the channel. This register is world-readable, but is writable only from a Secure, Privileged context."]
+    #[inline(always)]
+    pub const fn seccfg_ch5(self) -> crate::common::Reg<regs::SeccfgCh5, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(1172usize) as _) }
+    }
+    #[doc = "Security configuration for channel 6. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. This register automatically locks down (becomes read-only) once software starts to configure the channel. This register is world-readable, but is writable only from a Secure, Privileged context."]
+    #[inline(always)]
+    pub const fn seccfg_ch6(self) -> crate::common::Reg<regs::SeccfgCh6, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(1176usize) as _) }
+    }
+    #[doc = "Security configuration for channel 7. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. This register automatically locks down (becomes read-only) once software starts to configure the channel. This register is world-readable, but is writable only from a Secure, Privileged context."]
+    #[inline(always)]
+    pub const fn seccfg_ch7(self) -> crate::common::Reg<regs::SeccfgCh7, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(1180usize) as _) }
+    }
+    #[doc = "Security configuration for channel 8. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. This register automatically locks down (becomes read-only) once software starts to configure the channel. This register is world-readable, but is writable only from a Secure, Privileged context."]
+    #[inline(always)]
+    pub const fn seccfg_ch8(self) -> crate::common::Reg<regs::SeccfgCh8, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(1184usize) as _) }
+    }
+    #[doc = "Security configuration for channel 9. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. This register automatically locks down (becomes read-only) once software starts to configure the channel. This register is world-readable, but is writable only from a Secure, Privileged context."]
+    #[inline(always)]
+    pub const fn seccfg_ch9(self) -> crate::common::Reg<regs::SeccfgCh9, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(1188usize) as _) }
+    }
+    #[doc = "Security configuration for channel 10. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. This register automatically locks down (becomes read-only) once software starts to configure the channel. This register is world-readable, but is writable only from a Secure, Privileged context."]
+    #[inline(always)]
+    pub const fn seccfg_ch10(self) -> crate::common::Reg<regs::SeccfgCh10, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(1192usize) as _) }
+    }
+    #[doc = "Security configuration for channel 11. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. This register automatically locks down (becomes read-only) once software starts to configure the channel. This register is world-readable, but is writable only from a Secure, Privileged context."]
+    #[inline(always)]
+    pub const fn seccfg_ch11(self) -> crate::common::Reg<regs::SeccfgCh11, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(1196usize) as _) }
+    }
+    #[doc = "Security configuration for channel 12. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. This register automatically locks down (becomes read-only) once software starts to configure the channel. This register is world-readable, but is writable only from a Secure, Privileged context."]
+    #[inline(always)]
+    pub const fn seccfg_ch12(self) -> crate::common::Reg<regs::SeccfgCh12, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(1200usize) as _) }
+    }
+    #[doc = "Security configuration for channel 13. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. This register automatically locks down (becomes read-only) once software starts to configure the channel. This register is world-readable, but is writable only from a Secure, Privileged context."]
+    #[inline(always)]
+    pub const fn seccfg_ch13(self) -> crate::common::Reg<regs::SeccfgCh13, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(1204usize) as _) }
+    }
+    #[doc = "Security configuration for channel 14. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. This register automatically locks down (becomes read-only) once software starts to configure the channel. This register is world-readable, but is writable only from a Secure, Privileged context."]
+    #[inline(always)]
+    pub const fn seccfg_ch14(self) -> crate::common::Reg<regs::SeccfgCh14, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(1208usize) as _) }
+    }
+    #[doc = "Security configuration for channel 15. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. This register automatically locks down (becomes read-only) once software starts to configure the channel. This register is world-readable, but is writable only from a Secure, Privileged context."]
+    #[inline(always)]
+    pub const fn seccfg_ch15(self) -> crate::common::Reg<regs::SeccfgCh15, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(1212usize) as _) }
+    }
+    #[doc = "Security configuration for IRQ 0. Control whether the IRQ permits configuration by Non-secure/Unprivileged contexts, and whether it can observe Secure/Privileged channel interrupt flags."]
+    #[inline(always)]
+    pub const fn seccfg_irq0(self) -> crate::common::Reg<regs::SeccfgIrq0, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(1216usize) as _) }
+    }
+    #[doc = "Security configuration for IRQ 1. Control whether the IRQ permits configuration by Non-secure/Unprivileged contexts, and whether it can observe Secure/Privileged channel interrupt flags."]
+    #[inline(always)]
+    pub const fn seccfg_irq1(self) -> crate::common::Reg<regs::SeccfgIrq1, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(1220usize) as _) }
+    }
+    #[doc = "Security configuration for IRQ 2. Control whether the IRQ permits configuration by Non-secure/Unprivileged contexts, and whether it can observe Secure/Privileged channel interrupt flags."]
+    #[inline(always)]
+    pub const fn seccfg_irq2(self) -> crate::common::Reg<regs::SeccfgIrq2, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(1224usize) as _) }
+    }
+    #[doc = "Security configuration for IRQ 3. Control whether the IRQ permits configuration by Non-secure/Unprivileged contexts, and whether it can observe Secure/Privileged channel interrupt flags."]
+    #[inline(always)]
+    pub const fn seccfg_irq3(self) -> crate::common::Reg<regs::SeccfgIrq3, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(1228usize) as _) }
+    }
+    #[doc = "Miscellaneous security configuration"]
+    #[inline(always)]
+    pub const fn seccfg_misc(self) -> crate::common::Reg<regs::SeccfgMisc, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(1232usize) as _) }
+    }
+    #[doc = "Control register for DMA MPU. Accessible only from a Privileged context."]
+    #[inline(always)]
+    pub const fn mpu_ctrl(self) -> crate::common::Reg<regs::MpuCtrl, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(1280usize) as _) }
+    }
+    #[doc = "Base address register for MPU region 0. Writable only from a Secure, Privileged context."]
+    #[inline(always)]
+    pub const fn mpu_bar0(self) -> crate::common::Reg<regs::MpuBar0, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(1284usize) as _) }
+    }
+    #[doc = "Limit address register for MPU region 0. Writable only from a Secure, Privileged context, with the exception of the P bit."]
+    #[inline(always)]
+    pub const fn mpu_lar0(self) -> crate::common::Reg<regs::MpuLar0, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(1288usize) as _) }
+    }
+    #[doc = "Base address register for MPU region 1. Writable only from a Secure, Privileged context."]
+    #[inline(always)]
+    pub const fn mpu_bar1(self) -> crate::common::Reg<regs::MpuBar1, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(1292usize) as _) }
+    }
+    #[doc = "Limit address register for MPU region 1. Writable only from a Secure, Privileged context, with the exception of the P bit."]
+    #[inline(always)]
+    pub const fn mpu_lar1(self) -> crate::common::Reg<regs::MpuLar1, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(1296usize) as _) }
+    }
+    #[doc = "Base address register for MPU region 2. Writable only from a Secure, Privileged context."]
+    #[inline(always)]
+    pub const fn mpu_bar2(self) -> crate::common::Reg<regs::MpuBar2, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(1300usize) as _) }
+    }
+    #[doc = "Limit address register for MPU region 2. Writable only from a Secure, Privileged context, with the exception of the P bit."]
+    #[inline(always)]
+    pub const fn mpu_lar2(self) -> crate::common::Reg<regs::MpuLar2, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(1304usize) as _) }
+    }
+    #[doc = "Base address register for MPU region 3. Writable only from a Secure, Privileged context."]
+    #[inline(always)]
+    pub const fn mpu_bar3(self) -> crate::common::Reg<regs::MpuBar3, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(1308usize) as _) }
+    }
+    #[doc = "Limit address register for MPU region 3. Writable only from a Secure, Privileged context, with the exception of the P bit."]
+    #[inline(always)]
+    pub const fn mpu_lar3(self) -> crate::common::Reg<regs::MpuLar3, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(1312usize) as _) }
+    }
+    #[doc = "Base address register for MPU region 4. Writable only from a Secure, Privileged context."]
+    #[inline(always)]
+    pub const fn mpu_bar4(self) -> crate::common::Reg<regs::MpuBar4, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(1316usize) as _) }
+    }
+    #[doc = "Limit address register for MPU region 4. Writable only from a Secure, Privileged context, with the exception of the P bit."]
+    #[inline(always)]
+    pub const fn mpu_lar4(self) -> crate::common::Reg<regs::MpuLar4, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(1320usize) as _) }
+    }
+    #[doc = "Base address register for MPU region 5. Writable only from a Secure, Privileged context."]
+    #[inline(always)]
+    pub const fn mpu_bar5(self) -> crate::common::Reg<regs::MpuBar5, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(1324usize) as _) }
+    }
+    #[doc = "Limit address register for MPU region 5. Writable only from a Secure, Privileged context, with the exception of the P bit."]
+    #[inline(always)]
+    pub const fn mpu_lar5(self) -> crate::common::Reg<regs::MpuLar5, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(1328usize) as _) }
+    }
+    #[doc = "Base address register for MPU region 6. Writable only from a Secure, Privileged context."]
+    #[inline(always)]
+    pub const fn mpu_bar6(self) -> crate::common::Reg<regs::MpuBar6, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(1332usize) as _) }
+    }
+    #[doc = "Limit address register for MPU region 6. Writable only from a Secure, Privileged context, with the exception of the P bit."]
+    #[inline(always)]
+    pub const fn mpu_lar6(self) -> crate::common::Reg<regs::MpuLar6, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(1336usize) as _) }
+    }
+    #[doc = "Base address register for MPU region 7. Writable only from a Secure, Privileged context."]
+    #[inline(always)]
+    pub const fn mpu_bar7(self) -> crate::common::Reg<regs::MpuBar7, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(1340usize) as _) }
+    }
+    #[doc = "Limit address register for MPU region 7. Writable only from a Secure, Privileged context, with the exception of the P bit."]
+    #[inline(always)]
+    pub const fn mpu_lar7(self) -> crate::common::Reg<regs::MpuLar7, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(1344usize) as _) }
+    }
+}
+pub mod regs;
+pub mod vals;
diff --git a/src/rp2350/dma/regs.rs b/src/rp2350/dma/regs.rs
new file mode 100644
index 00000000..aa139d00
--- /dev/null
+++ b/src/rp2350/dma/regs.rs
@@ -0,0 +1,3020 @@
+#[doc = "DMA Channel 0 Transfer Count"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Ch0transCount(pub u32);
+impl Ch0transCount {
+    #[doc = "28-bit transfer count (256 million transfers maximum). Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD."]
+    #[inline(always)]
+    pub const fn count(&self) -> u32 {
+        let val = (self.0 >> 0usize) & 0x0fff_ffff;
+        val as u32
+    }
+    #[doc = "28-bit transfer count (256 million transfers maximum). Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD."]
+    #[inline(always)]
+    pub fn set_count(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x0fff_ffff << 0usize)) | (((val as u32) & 0x0fff_ffff) << 0usize);
+    }
+    #[doc = "When MODE is 0x0, the transfer count decrements with each transfer until 0, and then the channel triggers the next channel indicated by CTRL_CHAIN_TO. When MODE is 0x1, the transfer count decrements with each transfer until 0, and then the channel re-triggers itself, in addition to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an endless ring-buffer DMA with periodic interrupts. When MODE is 0xf, the transfer count does not decrement. The DMA channel performs an endless sequence of transfers, never triggering other channels or raising interrupts, until an ABORT is raised. All other values are reserved."]
+    #[inline(always)]
+    pub const fn mode(&self) -> super::vals::Ch0transCountMode {
+        let val = (self.0 >> 28usize) & 0x0f;
+        super::vals::Ch0transCountMode::from_bits(val as u8)
+    }
+    #[doc = "When MODE is 0x0, the transfer count decrements with each transfer until 0, and then the channel triggers the next channel indicated by CTRL_CHAIN_TO. When MODE is 0x1, the transfer count decrements with each transfer until 0, and then the channel re-triggers itself, in addition to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an endless ring-buffer DMA with periodic interrupts. When MODE is 0xf, the transfer count does not decrement. The DMA channel performs an endless sequence of transfers, never triggering other channels or raising interrupts, until an ABORT is raised. All other values are reserved."]
+    #[inline(always)]
+    pub fn set_mode(&mut self, val: super::vals::Ch0transCountMode) {
+        self.0 = (self.0 & !(0x0f << 28usize)) | (((val.to_bits() as u32) & 0x0f) << 28usize);
+    }
+}
+impl Default for Ch0transCount {
+    #[inline(always)]
+    fn default() -> Ch0transCount {
+        Ch0transCount(0)
+    }
+}
+#[doc = "DMA Channel 10 Transfer Count"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Ch10transCount(pub u32);
+impl Ch10transCount {
+    #[doc = "28-bit transfer count (256 million transfers maximum). Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD."]
+    #[inline(always)]
+    pub const fn count(&self) -> u32 {
+        let val = (self.0 >> 0usize) & 0x0fff_ffff;
+        val as u32
+    }
+    #[doc = "28-bit transfer count (256 million transfers maximum). Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD."]
+    #[inline(always)]
+    pub fn set_count(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x0fff_ffff << 0usize)) | (((val as u32) & 0x0fff_ffff) << 0usize);
+    }
+    #[doc = "When MODE is 0x0, the transfer count decrements with each transfer until 0, and then the channel triggers the next channel indicated by CTRL_CHAIN_TO. When MODE is 0x1, the transfer count decrements with each transfer until 0, and then the channel re-triggers itself, in addition to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an endless ring-buffer DMA with periodic interrupts. When MODE is 0xf, the transfer count does not decrement. The DMA channel performs an endless sequence of transfers, never triggering other channels or raising interrupts, until an ABORT is raised. All other values are reserved."]
+    #[inline(always)]
+    pub const fn mode(&self) -> super::vals::Ch10transCountMode {
+        let val = (self.0 >> 28usize) & 0x0f;
+        super::vals::Ch10transCountMode::from_bits(val as u8)
+    }
+    #[doc = "When MODE is 0x0, the transfer count decrements with each transfer until 0, and then the channel triggers the next channel indicated by CTRL_CHAIN_TO. When MODE is 0x1, the transfer count decrements with each transfer until 0, and then the channel re-triggers itself, in addition to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an endless ring-buffer DMA with periodic interrupts. When MODE is 0xf, the transfer count does not decrement. The DMA channel performs an endless sequence of transfers, never triggering other channels or raising interrupts, until an ABORT is raised. All other values are reserved."]
+    #[inline(always)]
+    pub fn set_mode(&mut self, val: super::vals::Ch10transCountMode) {
+        self.0 = (self.0 & !(0x0f << 28usize)) | (((val.to_bits() as u32) & 0x0f) << 28usize);
+    }
+}
+impl Default for Ch10transCount {
+    #[inline(always)]
+    fn default() -> Ch10transCount {
+        Ch10transCount(0)
+    }
+}
+#[doc = "DMA Channel 11 Transfer Count"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Ch11transCount(pub u32);
+impl Ch11transCount {
+    #[doc = "28-bit transfer count (256 million transfers maximum). Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD."]
+    #[inline(always)]
+    pub const fn count(&self) -> u32 {
+        let val = (self.0 >> 0usize) & 0x0fff_ffff;
+        val as u32
+    }
+    #[doc = "28-bit transfer count (256 million transfers maximum). Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD."]
+    #[inline(always)]
+    pub fn set_count(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x0fff_ffff << 0usize)) | (((val as u32) & 0x0fff_ffff) << 0usize);
+    }
+    #[doc = "When MODE is 0x0, the transfer count decrements with each transfer until 0, and then the channel triggers the next channel indicated by CTRL_CHAIN_TO. When MODE is 0x1, the transfer count decrements with each transfer until 0, and then the channel re-triggers itself, in addition to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an endless ring-buffer DMA with periodic interrupts. When MODE is 0xf, the transfer count does not decrement. The DMA channel performs an endless sequence of transfers, never triggering other channels or raising interrupts, until an ABORT is raised. All other values are reserved."]
+    #[inline(always)]
+    pub const fn mode(&self) -> super::vals::Ch11transCountMode {
+        let val = (self.0 >> 28usize) & 0x0f;
+        super::vals::Ch11transCountMode::from_bits(val as u8)
+    }
+    #[doc = "When MODE is 0x0, the transfer count decrements with each transfer until 0, and then the channel triggers the next channel indicated by CTRL_CHAIN_TO. When MODE is 0x1, the transfer count decrements with each transfer until 0, and then the channel re-triggers itself, in addition to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an endless ring-buffer DMA with periodic interrupts. When MODE is 0xf, the transfer count does not decrement. The DMA channel performs an endless sequence of transfers, never triggering other channels or raising interrupts, until an ABORT is raised. All other values are reserved."]
+    #[inline(always)]
+    pub fn set_mode(&mut self, val: super::vals::Ch11transCountMode) {
+        self.0 = (self.0 & !(0x0f << 28usize)) | (((val.to_bits() as u32) & 0x0f) << 28usize);
+    }
+}
+impl Default for Ch11transCount {
+    #[inline(always)]
+    fn default() -> Ch11transCount {
+        Ch11transCount(0)
+    }
+}
+#[doc = "DMA Channel 12 Transfer Count"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Ch12transCount(pub u32);
+impl Ch12transCount {
+    #[doc = "28-bit transfer count (256 million transfers maximum). Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD."]
+    #[inline(always)]
+    pub const fn count(&self) -> u32 {
+        let val = (self.0 >> 0usize) & 0x0fff_ffff;
+        val as u32
+    }
+    #[doc = "28-bit transfer count (256 million transfers maximum). Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD."]
+    #[inline(always)]
+    pub fn set_count(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x0fff_ffff << 0usize)) | (((val as u32) & 0x0fff_ffff) << 0usize);
+    }
+    #[doc = "When MODE is 0x0, the transfer count decrements with each transfer until 0, and then the channel triggers the next channel indicated by CTRL_CHAIN_TO. When MODE is 0x1, the transfer count decrements with each transfer until 0, and then the channel re-triggers itself, in addition to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an endless ring-buffer DMA with periodic interrupts. When MODE is 0xf, the transfer count does not decrement. The DMA channel performs an endless sequence of transfers, never triggering other channels or raising interrupts, until an ABORT is raised. All other values are reserved."]
+    #[inline(always)]
+    pub const fn mode(&self) -> super::vals::Ch12transCountMode {
+        let val = (self.0 >> 28usize) & 0x0f;
+        super::vals::Ch12transCountMode::from_bits(val as u8)
+    }
+    #[doc = "When MODE is 0x0, the transfer count decrements with each transfer until 0, and then the channel triggers the next channel indicated by CTRL_CHAIN_TO. When MODE is 0x1, the transfer count decrements with each transfer until 0, and then the channel re-triggers itself, in addition to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an endless ring-buffer DMA with periodic interrupts. When MODE is 0xf, the transfer count does not decrement. The DMA channel performs an endless sequence of transfers, never triggering other channels or raising interrupts, until an ABORT is raised. All other values are reserved."]
+    #[inline(always)]
+    pub fn set_mode(&mut self, val: super::vals::Ch12transCountMode) {
+        self.0 = (self.0 & !(0x0f << 28usize)) | (((val.to_bits() as u32) & 0x0f) << 28usize);
+    }
+}
+impl Default for Ch12transCount {
+    #[inline(always)]
+    fn default() -> Ch12transCount {
+        Ch12transCount(0)
+    }
+}
+#[doc = "DMA Channel 13 Transfer Count"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Ch13transCount(pub u32);
+impl Ch13transCount {
+    #[doc = "28-bit transfer count (256 million transfers maximum). Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD."]
+    #[inline(always)]
+    pub const fn count(&self) -> u32 {
+        let val = (self.0 >> 0usize) & 0x0fff_ffff;
+        val as u32
+    }
+    #[doc = "28-bit transfer count (256 million transfers maximum). Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD."]
+    #[inline(always)]
+    pub fn set_count(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x0fff_ffff << 0usize)) | (((val as u32) & 0x0fff_ffff) << 0usize);
+    }
+    #[doc = "When MODE is 0x0, the transfer count decrements with each transfer until 0, and then the channel triggers the next channel indicated by CTRL_CHAIN_TO. When MODE is 0x1, the transfer count decrements with each transfer until 0, and then the channel re-triggers itself, in addition to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an endless ring-buffer DMA with periodic interrupts. When MODE is 0xf, the transfer count does not decrement. The DMA channel performs an endless sequence of transfers, never triggering other channels or raising interrupts, until an ABORT is raised. All other values are reserved."]
+    #[inline(always)]
+    pub const fn mode(&self) -> super::vals::Ch13transCountMode {
+        let val = (self.0 >> 28usize) & 0x0f;
+        super::vals::Ch13transCountMode::from_bits(val as u8)
+    }
+    #[doc = "When MODE is 0x0, the transfer count decrements with each transfer until 0, and then the channel triggers the next channel indicated by CTRL_CHAIN_TO. When MODE is 0x1, the transfer count decrements with each transfer until 0, and then the channel re-triggers itself, in addition to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an endless ring-buffer DMA with periodic interrupts. When MODE is 0xf, the transfer count does not decrement. The DMA channel performs an endless sequence of transfers, never triggering other channels or raising interrupts, until an ABORT is raised. All other values are reserved."]
+    #[inline(always)]
+    pub fn set_mode(&mut self, val: super::vals::Ch13transCountMode) {
+        self.0 = (self.0 & !(0x0f << 28usize)) | (((val.to_bits() as u32) & 0x0f) << 28usize);
+    }
+}
+impl Default for Ch13transCount {
+    #[inline(always)]
+    fn default() -> Ch13transCount {
+        Ch13transCount(0)
+    }
+}
+#[doc = "DMA Channel 14 Transfer Count"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Ch14transCount(pub u32);
+impl Ch14transCount {
+    #[doc = "28-bit transfer count (256 million transfers maximum). Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD."]
+    #[inline(always)]
+    pub const fn count(&self) -> u32 {
+        let val = (self.0 >> 0usize) & 0x0fff_ffff;
+        val as u32
+    }
+    #[doc = "28-bit transfer count (256 million transfers maximum). Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD."]
+    #[inline(always)]
+    pub fn set_count(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x0fff_ffff << 0usize)) | (((val as u32) & 0x0fff_ffff) << 0usize);
+    }
+    #[doc = "When MODE is 0x0, the transfer count decrements with each transfer until 0, and then the channel triggers the next channel indicated by CTRL_CHAIN_TO. When MODE is 0x1, the transfer count decrements with each transfer until 0, and then the channel re-triggers itself, in addition to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an endless ring-buffer DMA with periodic interrupts. When MODE is 0xf, the transfer count does not decrement. The DMA channel performs an endless sequence of transfers, never triggering other channels or raising interrupts, until an ABORT is raised. All other values are reserved."]
+    #[inline(always)]
+    pub const fn mode(&self) -> super::vals::Ch14transCountMode {
+        let val = (self.0 >> 28usize) & 0x0f;
+        super::vals::Ch14transCountMode::from_bits(val as u8)
+    }
+    #[doc = "When MODE is 0x0, the transfer count decrements with each transfer until 0, and then the channel triggers the next channel indicated by CTRL_CHAIN_TO. When MODE is 0x1, the transfer count decrements with each transfer until 0, and then the channel re-triggers itself, in addition to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an endless ring-buffer DMA with periodic interrupts. When MODE is 0xf, the transfer count does not decrement. The DMA channel performs an endless sequence of transfers, never triggering other channels or raising interrupts, until an ABORT is raised. All other values are reserved."]
+    #[inline(always)]
+    pub fn set_mode(&mut self, val: super::vals::Ch14transCountMode) {
+        self.0 = (self.0 & !(0x0f << 28usize)) | (((val.to_bits() as u32) & 0x0f) << 28usize);
+    }
+}
+impl Default for Ch14transCount {
+    #[inline(always)]
+    fn default() -> Ch14transCount {
+        Ch14transCount(0)
+    }
+}
+#[doc = "DMA Channel 15 Transfer Count"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Ch15transCount(pub u32);
+impl Ch15transCount {
+    #[doc = "28-bit transfer count (256 million transfers maximum). Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD."]
+    #[inline(always)]
+    pub const fn count(&self) -> u32 {
+        let val = (self.0 >> 0usize) & 0x0fff_ffff;
+        val as u32
+    }
+    #[doc = "28-bit transfer count (256 million transfers maximum). Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD."]
+    #[inline(always)]
+    pub fn set_count(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x0fff_ffff << 0usize)) | (((val as u32) & 0x0fff_ffff) << 0usize);
+    }
+    #[doc = "When MODE is 0x0, the transfer count decrements with each transfer until 0, and then the channel triggers the next channel indicated by CTRL_CHAIN_TO. When MODE is 0x1, the transfer count decrements with each transfer until 0, and then the channel re-triggers itself, in addition to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an endless ring-buffer DMA with periodic interrupts. When MODE is 0xf, the transfer count does not decrement. The DMA channel performs an endless sequence of transfers, never triggering other channels or raising interrupts, until an ABORT is raised. All other values are reserved."]
+    #[inline(always)]
+    pub const fn mode(&self) -> super::vals::Ch15transCountMode {
+        let val = (self.0 >> 28usize) & 0x0f;
+        super::vals::Ch15transCountMode::from_bits(val as u8)
+    }
+    #[doc = "When MODE is 0x0, the transfer count decrements with each transfer until 0, and then the channel triggers the next channel indicated by CTRL_CHAIN_TO. When MODE is 0x1, the transfer count decrements with each transfer until 0, and then the channel re-triggers itself, in addition to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an endless ring-buffer DMA with periodic interrupts. When MODE is 0xf, the transfer count does not decrement. The DMA channel performs an endless sequence of transfers, never triggering other channels or raising interrupts, until an ABORT is raised. All other values are reserved."]
+    #[inline(always)]
+    pub fn set_mode(&mut self, val: super::vals::Ch15transCountMode) {
+        self.0 = (self.0 & !(0x0f << 28usize)) | (((val.to_bits() as u32) & 0x0f) << 28usize);
+    }
+}
+impl Default for Ch15transCount {
+    #[inline(always)]
+    fn default() -> Ch15transCount {
+        Ch15transCount(0)
+    }
+}
+#[doc = "DMA Channel 1 Transfer Count"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Ch1transCount(pub u32);
+impl Ch1transCount {
+    #[doc = "28-bit transfer count (256 million transfers maximum). Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD."]
+    #[inline(always)]
+    pub const fn count(&self) -> u32 {
+        let val = (self.0 >> 0usize) & 0x0fff_ffff;
+        val as u32
+    }
+    #[doc = "28-bit transfer count (256 million transfers maximum). Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD."]
+    #[inline(always)]
+    pub fn set_count(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x0fff_ffff << 0usize)) | (((val as u32) & 0x0fff_ffff) << 0usize);
+    }
+    #[doc = "When MODE is 0x0, the transfer count decrements with each transfer until 0, and then the channel triggers the next channel indicated by CTRL_CHAIN_TO. When MODE is 0x1, the transfer count decrements with each transfer until 0, and then the channel re-triggers itself, in addition to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an endless ring-buffer DMA with periodic interrupts. When MODE is 0xf, the transfer count does not decrement. The DMA channel performs an endless sequence of transfers, never triggering other channels or raising interrupts, until an ABORT is raised. All other values are reserved."]
+    #[inline(always)]
+    pub const fn mode(&self) -> super::vals::Ch1transCountMode {
+        let val = (self.0 >> 28usize) & 0x0f;
+        super::vals::Ch1transCountMode::from_bits(val as u8)
+    }
+    #[doc = "When MODE is 0x0, the transfer count decrements with each transfer until 0, and then the channel triggers the next channel indicated by CTRL_CHAIN_TO. When MODE is 0x1, the transfer count decrements with each transfer until 0, and then the channel re-triggers itself, in addition to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an endless ring-buffer DMA with periodic interrupts. When MODE is 0xf, the transfer count does not decrement. The DMA channel performs an endless sequence of transfers, never triggering other channels or raising interrupts, until an ABORT is raised. All other values are reserved."]
+    #[inline(always)]
+    pub fn set_mode(&mut self, val: super::vals::Ch1transCountMode) {
+        self.0 = (self.0 & !(0x0f << 28usize)) | (((val.to_bits() as u32) & 0x0f) << 28usize);
+    }
+}
+impl Default for Ch1transCount {
+    #[inline(always)]
+    fn default() -> Ch1transCount {
+        Ch1transCount(0)
+    }
+}
+#[doc = "DMA Channel 2 Transfer Count"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Ch2transCount(pub u32);
+impl Ch2transCount {
+    #[doc = "28-bit transfer count (256 million transfers maximum). Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD."]
+    #[inline(always)]
+    pub const fn count(&self) -> u32 {
+        let val = (self.0 >> 0usize) & 0x0fff_ffff;
+        val as u32
+    }
+    #[doc = "28-bit transfer count (256 million transfers maximum). Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD."]
+    #[inline(always)]
+    pub fn set_count(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x0fff_ffff << 0usize)) | (((val as u32) & 0x0fff_ffff) << 0usize);
+    }
+    #[doc = "When MODE is 0x0, the transfer count decrements with each transfer until 0, and then the channel triggers the next channel indicated by CTRL_CHAIN_TO. When MODE is 0x1, the transfer count decrements with each transfer until 0, and then the channel re-triggers itself, in addition to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an endless ring-buffer DMA with periodic interrupts. When MODE is 0xf, the transfer count does not decrement. The DMA channel performs an endless sequence of transfers, never triggering other channels or raising interrupts, until an ABORT is raised. All other values are reserved."]
+    #[inline(always)]
+    pub const fn mode(&self) -> super::vals::Ch2transCountMode {
+        let val = (self.0 >> 28usize) & 0x0f;
+        super::vals::Ch2transCountMode::from_bits(val as u8)
+    }
+    #[doc = "When MODE is 0x0, the transfer count decrements with each transfer until 0, and then the channel triggers the next channel indicated by CTRL_CHAIN_TO. When MODE is 0x1, the transfer count decrements with each transfer until 0, and then the channel re-triggers itself, in addition to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an endless ring-buffer DMA with periodic interrupts. When MODE is 0xf, the transfer count does not decrement. The DMA channel performs an endless sequence of transfers, never triggering other channels or raising interrupts, until an ABORT is raised. All other values are reserved."]
+    #[inline(always)]
+    pub fn set_mode(&mut self, val: super::vals::Ch2transCountMode) {
+        self.0 = (self.0 & !(0x0f << 28usize)) | (((val.to_bits() as u32) & 0x0f) << 28usize);
+    }
+}
+impl Default for Ch2transCount {
+    #[inline(always)]
+    fn default() -> Ch2transCount {
+        Ch2transCount(0)
+    }
+}
+#[doc = "DMA Channel 3 Transfer Count"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Ch3transCount(pub u32);
+impl Ch3transCount {
+    #[doc = "28-bit transfer count (256 million transfers maximum). Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD."]
+    #[inline(always)]
+    pub const fn count(&self) -> u32 {
+        let val = (self.0 >> 0usize) & 0x0fff_ffff;
+        val as u32
+    }
+    #[doc = "28-bit transfer count (256 million transfers maximum). Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD."]
+    #[inline(always)]
+    pub fn set_count(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x0fff_ffff << 0usize)) | (((val as u32) & 0x0fff_ffff) << 0usize);
+    }
+    #[doc = "When MODE is 0x0, the transfer count decrements with each transfer until 0, and then the channel triggers the next channel indicated by CTRL_CHAIN_TO. When MODE is 0x1, the transfer count decrements with each transfer until 0, and then the channel re-triggers itself, in addition to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an endless ring-buffer DMA with periodic interrupts. When MODE is 0xf, the transfer count does not decrement. The DMA channel performs an endless sequence of transfers, never triggering other channels or raising interrupts, until an ABORT is raised. All other values are reserved."]
+    #[inline(always)]
+    pub const fn mode(&self) -> super::vals::Ch3transCountMode {
+        let val = (self.0 >> 28usize) & 0x0f;
+        super::vals::Ch3transCountMode::from_bits(val as u8)
+    }
+    #[doc = "When MODE is 0x0, the transfer count decrements with each transfer until 0, and then the channel triggers the next channel indicated by CTRL_CHAIN_TO. When MODE is 0x1, the transfer count decrements with each transfer until 0, and then the channel re-triggers itself, in addition to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an endless ring-buffer DMA with periodic interrupts. When MODE is 0xf, the transfer count does not decrement. The DMA channel performs an endless sequence of transfers, never triggering other channels or raising interrupts, until an ABORT is raised. All other values are reserved."]
+    #[inline(always)]
+    pub fn set_mode(&mut self, val: super::vals::Ch3transCountMode) {
+        self.0 = (self.0 & !(0x0f << 28usize)) | (((val.to_bits() as u32) & 0x0f) << 28usize);
+    }
+}
+impl Default for Ch3transCount {
+    #[inline(always)]
+    fn default() -> Ch3transCount {
+        Ch3transCount(0)
+    }
+}
+#[doc = "DMA Channel 4 Transfer Count"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Ch4transCount(pub u32);
+impl Ch4transCount {
+    #[doc = "28-bit transfer count (256 million transfers maximum). Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD."]
+    #[inline(always)]
+    pub const fn count(&self) -> u32 {
+        let val = (self.0 >> 0usize) & 0x0fff_ffff;
+        val as u32
+    }
+    #[doc = "28-bit transfer count (256 million transfers maximum). Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD."]
+    #[inline(always)]
+    pub fn set_count(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x0fff_ffff << 0usize)) | (((val as u32) & 0x0fff_ffff) << 0usize);
+    }
+    #[doc = "When MODE is 0x0, the transfer count decrements with each transfer until 0, and then the channel triggers the next channel indicated by CTRL_CHAIN_TO. When MODE is 0x1, the transfer count decrements with each transfer until 0, and then the channel re-triggers itself, in addition to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an endless ring-buffer DMA with periodic interrupts. When MODE is 0xf, the transfer count does not decrement. The DMA channel performs an endless sequence of transfers, never triggering other channels or raising interrupts, until an ABORT is raised. All other values are reserved."]
+    #[inline(always)]
+    pub const fn mode(&self) -> super::vals::Ch4transCountMode {
+        let val = (self.0 >> 28usize) & 0x0f;
+        super::vals::Ch4transCountMode::from_bits(val as u8)
+    }
+    #[doc = "When MODE is 0x0, the transfer count decrements with each transfer until 0, and then the channel triggers the next channel indicated by CTRL_CHAIN_TO. When MODE is 0x1, the transfer count decrements with each transfer until 0, and then the channel re-triggers itself, in addition to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an endless ring-buffer DMA with periodic interrupts. When MODE is 0xf, the transfer count does not decrement. The DMA channel performs an endless sequence of transfers, never triggering other channels or raising interrupts, until an ABORT is raised. All other values are reserved."]
+    #[inline(always)]
+    pub fn set_mode(&mut self, val: super::vals::Ch4transCountMode) {
+        self.0 = (self.0 & !(0x0f << 28usize)) | (((val.to_bits() as u32) & 0x0f) << 28usize);
+    }
+}
+impl Default for Ch4transCount {
+    #[inline(always)]
+    fn default() -> Ch4transCount {
+        Ch4transCount(0)
+    }
+}
+#[doc = "DMA Channel 5 Transfer Count"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Ch5transCount(pub u32);
+impl Ch5transCount {
+    #[doc = "28-bit transfer count (256 million transfers maximum). Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD."]
+    #[inline(always)]
+    pub const fn count(&self) -> u32 {
+        let val = (self.0 >> 0usize) & 0x0fff_ffff;
+        val as u32
+    }
+    #[doc = "28-bit transfer count (256 million transfers maximum). Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD."]
+    #[inline(always)]
+    pub fn set_count(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x0fff_ffff << 0usize)) | (((val as u32) & 0x0fff_ffff) << 0usize);
+    }
+    #[doc = "When MODE is 0x0, the transfer count decrements with each transfer until 0, and then the channel triggers the next channel indicated by CTRL_CHAIN_TO. When MODE is 0x1, the transfer count decrements with each transfer until 0, and then the channel re-triggers itself, in addition to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an endless ring-buffer DMA with periodic interrupts. When MODE is 0xf, the transfer count does not decrement. The DMA channel performs an endless sequence of transfers, never triggering other channels or raising interrupts, until an ABORT is raised. All other values are reserved."]
+    #[inline(always)]
+    pub const fn mode(&self) -> super::vals::Ch5transCountMode {
+        let val = (self.0 >> 28usize) & 0x0f;
+        super::vals::Ch5transCountMode::from_bits(val as u8)
+    }
+    #[doc = "When MODE is 0x0, the transfer count decrements with each transfer until 0, and then the channel triggers the next channel indicated by CTRL_CHAIN_TO. When MODE is 0x1, the transfer count decrements with each transfer until 0, and then the channel re-triggers itself, in addition to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an endless ring-buffer DMA with periodic interrupts. When MODE is 0xf, the transfer count does not decrement. The DMA channel performs an endless sequence of transfers, never triggering other channels or raising interrupts, until an ABORT is raised. All other values are reserved."]
+    #[inline(always)]
+    pub fn set_mode(&mut self, val: super::vals::Ch5transCountMode) {
+        self.0 = (self.0 & !(0x0f << 28usize)) | (((val.to_bits() as u32) & 0x0f) << 28usize);
+    }
+}
+impl Default for Ch5transCount {
+    #[inline(always)]
+    fn default() -> Ch5transCount {
+        Ch5transCount(0)
+    }
+}
+#[doc = "DMA Channel 6 Transfer Count"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Ch6transCount(pub u32);
+impl Ch6transCount {
+    #[doc = "28-bit transfer count (256 million transfers maximum). Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD."]
+    #[inline(always)]
+    pub const fn count(&self) -> u32 {
+        let val = (self.0 >> 0usize) & 0x0fff_ffff;
+        val as u32
+    }
+    #[doc = "28-bit transfer count (256 million transfers maximum). Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD."]
+    #[inline(always)]
+    pub fn set_count(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x0fff_ffff << 0usize)) | (((val as u32) & 0x0fff_ffff) << 0usize);
+    }
+    #[doc = "When MODE is 0x0, the transfer count decrements with each transfer until 0, and then the channel triggers the next channel indicated by CTRL_CHAIN_TO. When MODE is 0x1, the transfer count decrements with each transfer until 0, and then the channel re-triggers itself, in addition to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an endless ring-buffer DMA with periodic interrupts. When MODE is 0xf, the transfer count does not decrement. The DMA channel performs an endless sequence of transfers, never triggering other channels or raising interrupts, until an ABORT is raised. All other values are reserved."]
+    #[inline(always)]
+    pub const fn mode(&self) -> super::vals::Ch6transCountMode {
+        let val = (self.0 >> 28usize) & 0x0f;
+        super::vals::Ch6transCountMode::from_bits(val as u8)
+    }
+    #[doc = "When MODE is 0x0, the transfer count decrements with each transfer until 0, and then the channel triggers the next channel indicated by CTRL_CHAIN_TO. When MODE is 0x1, the transfer count decrements with each transfer until 0, and then the channel re-triggers itself, in addition to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an endless ring-buffer DMA with periodic interrupts. When MODE is 0xf, the transfer count does not decrement. The DMA channel performs an endless sequence of transfers, never triggering other channels or raising interrupts, until an ABORT is raised. All other values are reserved."]
+    #[inline(always)]
+    pub fn set_mode(&mut self, val: super::vals::Ch6transCountMode) {
+        self.0 = (self.0 & !(0x0f << 28usize)) | (((val.to_bits() as u32) & 0x0f) << 28usize);
+    }
+}
+impl Default for Ch6transCount {
+    #[inline(always)]
+    fn default() -> Ch6transCount {
+        Ch6transCount(0)
+    }
+}
+#[doc = "DMA Channel 7 Transfer Count"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Ch7transCount(pub u32);
+impl Ch7transCount {
+    #[doc = "28-bit transfer count (256 million transfers maximum). Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD."]
+    #[inline(always)]
+    pub const fn count(&self) -> u32 {
+        let val = (self.0 >> 0usize) & 0x0fff_ffff;
+        val as u32
+    }
+    #[doc = "28-bit transfer count (256 million transfers maximum). Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD."]
+    #[inline(always)]
+    pub fn set_count(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x0fff_ffff << 0usize)) | (((val as u32) & 0x0fff_ffff) << 0usize);
+    }
+    #[doc = "When MODE is 0x0, the transfer count decrements with each transfer until 0, and then the channel triggers the next channel indicated by CTRL_CHAIN_TO. When MODE is 0x1, the transfer count decrements with each transfer until 0, and then the channel re-triggers itself, in addition to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an endless ring-buffer DMA with periodic interrupts. When MODE is 0xf, the transfer count does not decrement. The DMA channel performs an endless sequence of transfers, never triggering other channels or raising interrupts, until an ABORT is raised. All other values are reserved."]
+    #[inline(always)]
+    pub const fn mode(&self) -> super::vals::Ch7transCountMode {
+        let val = (self.0 >> 28usize) & 0x0f;
+        super::vals::Ch7transCountMode::from_bits(val as u8)
+    }
+    #[doc = "When MODE is 0x0, the transfer count decrements with each transfer until 0, and then the channel triggers the next channel indicated by CTRL_CHAIN_TO. When MODE is 0x1, the transfer count decrements with each transfer until 0, and then the channel re-triggers itself, in addition to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an endless ring-buffer DMA with periodic interrupts. When MODE is 0xf, the transfer count does not decrement. The DMA channel performs an endless sequence of transfers, never triggering other channels or raising interrupts, until an ABORT is raised. All other values are reserved."]
+    #[inline(always)]
+    pub fn set_mode(&mut self, val: super::vals::Ch7transCountMode) {
+        self.0 = (self.0 & !(0x0f << 28usize)) | (((val.to_bits() as u32) & 0x0f) << 28usize);
+    }
+}
+impl Default for Ch7transCount {
+    #[inline(always)]
+    fn default() -> Ch7transCount {
+        Ch7transCount(0)
+    }
+}
+#[doc = "DMA Channel 8 Transfer Count"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Ch8transCount(pub u32);
+impl Ch8transCount {
+    #[doc = "28-bit transfer count (256 million transfers maximum). Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD."]
+    #[inline(always)]
+    pub const fn count(&self) -> u32 {
+        let val = (self.0 >> 0usize) & 0x0fff_ffff;
+        val as u32
+    }
+    #[doc = "28-bit transfer count (256 million transfers maximum). Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD."]
+    #[inline(always)]
+    pub fn set_count(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x0fff_ffff << 0usize)) | (((val as u32) & 0x0fff_ffff) << 0usize);
+    }
+    #[doc = "When MODE is 0x0, the transfer count decrements with each transfer until 0, and then the channel triggers the next channel indicated by CTRL_CHAIN_TO. When MODE is 0x1, the transfer count decrements with each transfer until 0, and then the channel re-triggers itself, in addition to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an endless ring-buffer DMA with periodic interrupts. When MODE is 0xf, the transfer count does not decrement. The DMA channel performs an endless sequence of transfers, never triggering other channels or raising interrupts, until an ABORT is raised. All other values are reserved."]
+    #[inline(always)]
+    pub const fn mode(&self) -> super::vals::Ch8transCountMode {
+        let val = (self.0 >> 28usize) & 0x0f;
+        super::vals::Ch8transCountMode::from_bits(val as u8)
+    }
+    #[doc = "When MODE is 0x0, the transfer count decrements with each transfer until 0, and then the channel triggers the next channel indicated by CTRL_CHAIN_TO. When MODE is 0x1, the transfer count decrements with each transfer until 0, and then the channel re-triggers itself, in addition to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an endless ring-buffer DMA with periodic interrupts. When MODE is 0xf, the transfer count does not decrement. The DMA channel performs an endless sequence of transfers, never triggering other channels or raising interrupts, until an ABORT is raised. All other values are reserved."]
+    #[inline(always)]
+    pub fn set_mode(&mut self, val: super::vals::Ch8transCountMode) {
+        self.0 = (self.0 & !(0x0f << 28usize)) | (((val.to_bits() as u32) & 0x0f) << 28usize);
+    }
+}
+impl Default for Ch8transCount {
+    #[inline(always)]
+    fn default() -> Ch8transCount {
+        Ch8transCount(0)
+    }
+}
+#[doc = "DMA Channel 9 Transfer Count"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Ch9transCount(pub u32);
+impl Ch9transCount {
+    #[doc = "28-bit transfer count (256 million transfers maximum). Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD."]
+    #[inline(always)]
+    pub const fn count(&self) -> u32 {
+        let val = (self.0 >> 0usize) & 0x0fff_ffff;
+        val as u32
+    }
+    #[doc = "28-bit transfer count (256 million transfers maximum). Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD."]
+    #[inline(always)]
+    pub fn set_count(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x0fff_ffff << 0usize)) | (((val as u32) & 0x0fff_ffff) << 0usize);
+    }
+    #[doc = "When MODE is 0x0, the transfer count decrements with each transfer until 0, and then the channel triggers the next channel indicated by CTRL_CHAIN_TO. When MODE is 0x1, the transfer count decrements with each transfer until 0, and then the channel re-triggers itself, in addition to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an endless ring-buffer DMA with periodic interrupts. When MODE is 0xf, the transfer count does not decrement. The DMA channel performs an endless sequence of transfers, never triggering other channels or raising interrupts, until an ABORT is raised. All other values are reserved."]
+    #[inline(always)]
+    pub const fn mode(&self) -> super::vals::Ch9transCountMode {
+        let val = (self.0 >> 28usize) & 0x0f;
+        super::vals::Ch9transCountMode::from_bits(val as u8)
+    }
+    #[doc = "When MODE is 0x0, the transfer count decrements with each transfer until 0, and then the channel triggers the next channel indicated by CTRL_CHAIN_TO. When MODE is 0x1, the transfer count decrements with each transfer until 0, and then the channel re-triggers itself, in addition to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an endless ring-buffer DMA with periodic interrupts. When MODE is 0xf, the transfer count does not decrement. The DMA channel performs an endless sequence of transfers, never triggering other channels or raising interrupts, until an ABORT is raised. All other values are reserved."]
+    #[inline(always)]
+    pub fn set_mode(&mut self, val: super::vals::Ch9transCountMode) {
+        self.0 = (self.0 & !(0x0f << 28usize)) | (((val.to_bits() as u32) & 0x0f) << 28usize);
+    }
+}
+impl Default for Ch9transCount {
+    #[inline(always)]
+    fn default() -> Ch9transCount {
+        Ch9transCount(0)
+    }
+}
+#[doc = "Abort an in-progress transfer sequence on one or more channels"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct ChanAbort(pub u32);
+impl ChanAbort {
+    #[doc = "Each bit corresponds to a channel. Writing a 1 aborts whatever transfer sequence is in progress on that channel. The bit will remain high until any in-flight transfers have been flushed through the address and data FIFOs. After writing, this register must be polled until it returns all-zero. Until this point, it is unsafe to restart the channel."]
+    #[inline(always)]
+    pub const fn chan_abort(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0xffff;
+        val as u16
+    }
+    #[doc = "Each bit corresponds to a channel. Writing a 1 aborts whatever transfer sequence is in progress on that channel. The bit will remain high until any in-flight transfers have been flushed through the address and data FIFOs. After writing, this register must be polled until it returns all-zero. Until this point, it is unsafe to restart the channel."]
+    #[inline(always)]
+    pub fn set_chan_abort(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+    }
+}
+impl Default for ChanAbort {
+    #[inline(always)]
+    fn default() -> ChanAbort {
+        ChanAbort(0)
+    }
+}
+#[doc = "DMA Channel 13 Control and Status"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct CtrlTrig(pub u32);
+impl CtrlTrig {
+    #[doc = "DMA Channel Enable. When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)"]
+    #[inline(always)]
+    pub const fn en(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "DMA Channel Enable. When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)"]
+    #[inline(always)]
+    pub fn set_en(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[doc = "HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput."]
+    #[inline(always)]
+    pub const fn high_priority(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[doc = "HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput."]
+    #[inline(always)]
+    pub fn set_high_priority(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+    #[doc = "Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer."]
+    #[inline(always)]
+    pub const fn data_size(&self) -> super::vals::DataSize {
+        let val = (self.0 >> 2usize) & 0x03;
+        super::vals::DataSize::from_bits(val as u8)
+    }
+    #[doc = "Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer."]
+    #[inline(always)]
+    pub fn set_data_size(&mut self, val: super::vals::DataSize) {
+        self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize);
+    }
+    #[doc = "If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. Generally this should be disabled for peripheral-to-memory transfers."]
+    #[inline(always)]
+    pub const fn incr_read(&self) -> bool {
+        let val = (self.0 >> 4usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. Generally this should be disabled for peripheral-to-memory transfers."]
+    #[inline(always)]
+    pub fn set_incr_read(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
+    }
+    #[doc = "If 1, and INCR_READ is 1, the read address is decremented rather than incremented with each transfer. If 1, and INCR_READ is 0, this otherwise-unused combination causes the read address to be incremented by twice the transfer size, i.e. skipping over alternate addresses."]
+    #[inline(always)]
+    pub const fn incr_read_rev(&self) -> bool {
+        let val = (self.0 >> 5usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, and INCR_READ is 1, the read address is decremented rather than incremented with each transfer. If 1, and INCR_READ is 0, this otherwise-unused combination causes the read address to be incremented by twice the transfer size, i.e. skipping over alternate addresses."]
+    #[inline(always)]
+    pub fn set_incr_read_rev(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
+    }
+    #[doc = "If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. Generally this should be disabled for memory-to-peripheral transfers."]
+    #[inline(always)]
+    pub const fn incr_write(&self) -> bool {
+        let val = (self.0 >> 6usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. Generally this should be disabled for memory-to-peripheral transfers."]
+    #[inline(always)]
+    pub fn set_incr_write(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
+    }
+    #[doc = "If 1, and INCR_WRITE is 1, the write address is decremented rather than incremented with each transfer. If 1, and INCR_WRITE is 0, this otherwise-unused combination causes the write address to be incremented by twice the transfer size, i.e. skipping over alternate addresses."]
+    #[inline(always)]
+    pub const fn incr_write_rev(&self) -> bool {
+        let val = (self.0 >> 7usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, and INCR_WRITE is 1, the write address is decremented rather than incremented with each transfer. If 1, and INCR_WRITE is 0, this otherwise-unused combination causes the write address to be incremented by twice the transfer size, i.e. skipping over alternate addresses."]
+    #[inline(always)]
+    pub fn set_incr_write_rev(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
+    }
+    #[doc = "Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL."]
+    #[inline(always)]
+    pub const fn ring_size(&self) -> u8 {
+        let val = (self.0 >> 8usize) & 0x0f;
+        val as u8
+    }
+    #[doc = "Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL."]
+    #[inline(always)]
+    pub fn set_ring_size(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x0f << 8usize)) | (((val as u32) & 0x0f) << 8usize);
+    }
+    #[doc = "Select whether RING_SIZE applies to read or write addresses. If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped."]
+    #[inline(always)]
+    pub const fn ring_sel(&self) -> bool {
+        let val = (self.0 >> 12usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Select whether RING_SIZE applies to read or write addresses. If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped."]
+    #[inline(always)]
+    pub fn set_ring_sel(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
+    }
+    #[doc = "When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. Note this field resets to 0, so channels 1 and above will chain to channel 0 by default. Set this field to avoid this behaviour."]
+    #[inline(always)]
+    pub const fn chain_to(&self) -> u8 {
+        let val = (self.0 >> 13usize) & 0x0f;
+        val as u8
+    }
+    #[doc = "When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. Note this field resets to 0, so channels 1 and above will chain to channel 0 by default. Set this field to avoid this behaviour."]
+    #[inline(always)]
+    pub fn set_chain_to(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x0f << 13usize)) | (((val as u32) & 0x0f) << 13usize);
+    }
+    #[doc = "Select a Transfer Request signal. The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). 0x0 to 0x3a -> select DREQ n as TREQ"]
+    #[inline(always)]
+    pub const fn treq_sel(&self) -> super::vals::TreqSel {
+        let val = (self.0 >> 17usize) & 0x3f;
+        super::vals::TreqSel::from_bits(val as u8)
+    }
+    #[doc = "Select a Transfer Request signal. The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). 0x0 to 0x3a -> select DREQ n as TREQ"]
+    #[inline(always)]
+    pub fn set_treq_sel(&mut self, val: super::vals::TreqSel) {
+        self.0 = (self.0 & !(0x3f << 17usize)) | (((val.to_bits() as u32) & 0x3f) << 17usize);
+    }
+    #[doc = "In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks."]
+    #[inline(always)]
+    pub const fn irq_quiet(&self) -> bool {
+        let val = (self.0 >> 23usize) & 0x01;
+        val != 0
+    }
+    #[doc = "In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks."]
+    #[inline(always)]
+    pub fn set_irq_quiet(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 23usize)) | (((val as u32) & 0x01) << 23usize);
+    }
+    #[doc = "Apply byte-swap transformation to DMA data. For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order."]
+    #[inline(always)]
+    pub const fn bswap(&self) -> bool {
+        let val = (self.0 >> 24usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Apply byte-swap transformation to DMA data. For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order."]
+    #[inline(always)]
+    pub fn set_bswap(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 24usize)) | (((val as u32) & 0x01) << 24usize);
+    }
+    #[doc = "If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. This allows checksum to be enabled or disabled on a per-control- block basis."]
+    #[inline(always)]
+    pub const fn sniff_en(&self) -> bool {
+        let val = (self.0 >> 25usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. This allows checksum to be enabled or disabled on a per-control- block basis."]
+    #[inline(always)]
+    pub fn set_sniff_en(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 25usize)) | (((val as u32) & 0x01) << 25usize);
+    }
+    #[doc = "This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused. To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT."]
+    #[inline(always)]
+    pub const fn busy(&self) -> bool {
+        let val = (self.0 >> 26usize) & 0x01;
+        val != 0
+    }
+    #[doc = "This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused. To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT."]
+    #[inline(always)]
+    pub fn set_busy(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 26usize)) | (((val as u32) & 0x01) << 26usize);
+    }
+    #[doc = "If 1, the channel received a write bus error. Write one to clear. WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)"]
+    #[inline(always)]
+    pub const fn write_error(&self) -> bool {
+        let val = (self.0 >> 29usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, the channel received a write bus error. Write one to clear. WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)"]
+    #[inline(always)]
+    pub fn set_write_error(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 29usize)) | (((val as u32) & 0x01) << 29usize);
+    }
+    #[doc = "If 1, the channel received a read bus error. Write one to clear. READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)"]
+    #[inline(always)]
+    pub const fn read_error(&self) -> bool {
+        let val = (self.0 >> 30usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, the channel received a read bus error. Write one to clear. READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)"]
+    #[inline(always)]
+    pub fn set_read_error(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 30usize)) | (((val as u32) & 0x01) << 30usize);
+    }
+    #[doc = "Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag."]
+    #[inline(always)]
+    pub const fn ahb_error(&self) -> bool {
+        let val = (self.0 >> 31usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag."]
+    #[inline(always)]
+    pub fn set_ahb_error(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 31usize)) | (((val as u32) & 0x01) << 31usize);
+    }
+}
+impl Default for CtrlTrig {
+    #[inline(always)]
+    fn default() -> CtrlTrig {
+        CtrlTrig(0)
+    }
+}
+#[doc = "Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct DbgCtdreq(pub u32);
+impl DbgCtdreq {
+    #[inline(always)]
+    pub const fn dbg_ctdreq(&self) -> u8 {
+        let val = (self.0 >> 0usize) & 0x3f;
+        val as u8
+    }
+    #[inline(always)]
+    pub fn set_dbg_ctdreq(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x3f << 0usize)) | (((val as u32) & 0x3f) << 0usize);
+    }
+}
+impl Default for DbgCtdreq {
+    #[inline(always)]
+    fn default() -> DbgCtdreq {
+        DbgCtdreq(0)
+    }
+}
+#[doc = "Debug RAF, WAF, TDF levels"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct FifoLevels(pub u32);
+impl FifoLevels {
+    #[doc = "Current Transfer-Data-FIFO fill level"]
+    #[inline(always)]
+    pub const fn tdf_lvl(&self) -> u8 {
+        let val = (self.0 >> 0usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Current Transfer-Data-FIFO fill level"]
+    #[inline(always)]
+    pub fn set_tdf_lvl(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize);
+    }
+    #[doc = "Current Write-Address-FIFO fill level"]
+    #[inline(always)]
+    pub const fn waf_lvl(&self) -> u8 {
+        let val = (self.0 >> 8usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Current Write-Address-FIFO fill level"]
+    #[inline(always)]
+    pub fn set_waf_lvl(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize);
+    }
+    #[doc = "Current Read-Address-FIFO fill level"]
+    #[inline(always)]
+    pub const fn raf_lvl(&self) -> u8 {
+        let val = (self.0 >> 16usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Current Read-Address-FIFO fill level"]
+    #[inline(always)]
+    pub fn set_raf_lvl(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize);
+    }
+}
+impl Default for FifoLevels {
+    #[inline(always)]
+    fn default() -> FifoLevels {
+        FifoLevels(0)
+    }
+}
+#[doc = "Interrupt Enables for IRQ 0"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Inte0(pub u32);
+impl Inte0 {
+    #[doc = "Set bit n to pass interrupts from channel n to DMA IRQ 0. Note this bit has no effect if the channel security/privilege level, defined by SECCFG_CHx, is greater than the IRQ security/privilege defined by SECCFG_IRQ0."]
+    #[inline(always)]
+    pub const fn inte0(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0xffff;
+        val as u16
+    }
+    #[doc = "Set bit n to pass interrupts from channel n to DMA IRQ 0. Note this bit has no effect if the channel security/privilege level, defined by SECCFG_CHx, is greater than the IRQ security/privilege defined by SECCFG_IRQ0."]
+    #[inline(always)]
+    pub fn set_inte0(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+    }
+}
+impl Default for Inte0 {
+    #[inline(always)]
+    fn default() -> Inte0 {
+        Inte0(0)
+    }
+}
+#[doc = "Interrupt Enables for IRQ 1"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Inte1(pub u32);
+impl Inte1 {
+    #[doc = "Set bit n to pass interrupts from channel n to DMA IRQ 1. Note this bit has no effect if the channel security/privilege level, defined by SECCFG_CHx, is greater than the IRQ security/privilege defined by SECCFG_IRQ1."]
+    #[inline(always)]
+    pub const fn inte1(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0xffff;
+        val as u16
+    }
+    #[doc = "Set bit n to pass interrupts from channel n to DMA IRQ 1. Note this bit has no effect if the channel security/privilege level, defined by SECCFG_CHx, is greater than the IRQ security/privilege defined by SECCFG_IRQ1."]
+    #[inline(always)]
+    pub fn set_inte1(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+    }
+}
+impl Default for Inte1 {
+    #[inline(always)]
+    fn default() -> Inte1 {
+        Inte1(0)
+    }
+}
+#[doc = "Interrupt Enables for IRQ 2"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Inte2(pub u32);
+impl Inte2 {
+    #[doc = "Set bit n to pass interrupts from channel n to DMA IRQ 2. Note this bit has no effect if the channel security/privilege level, defined by SECCFG_CHx, is greater than the IRQ security/privilege defined by SECCFG_IRQ2."]
+    #[inline(always)]
+    pub const fn inte2(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0xffff;
+        val as u16
+    }
+    #[doc = "Set bit n to pass interrupts from channel n to DMA IRQ 2. Note this bit has no effect if the channel security/privilege level, defined by SECCFG_CHx, is greater than the IRQ security/privilege defined by SECCFG_IRQ2."]
+    #[inline(always)]
+    pub fn set_inte2(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+    }
+}
+impl Default for Inte2 {
+    #[inline(always)]
+    fn default() -> Inte2 {
+        Inte2(0)
+    }
+}
+#[doc = "Interrupt Enables for IRQ 3"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Inte3(pub u32);
+impl Inte3 {
+    #[doc = "Set bit n to pass interrupts from channel n to DMA IRQ 3. Note this bit has no effect if the channel security/privilege level, defined by SECCFG_CHx, is greater than the IRQ security/privilege defined by SECCFG_IRQ3."]
+    #[inline(always)]
+    pub const fn inte3(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0xffff;
+        val as u16
+    }
+    #[doc = "Set bit n to pass interrupts from channel n to DMA IRQ 3. Note this bit has no effect if the channel security/privilege level, defined by SECCFG_CHx, is greater than the IRQ security/privilege defined by SECCFG_IRQ3."]
+    #[inline(always)]
+    pub fn set_inte3(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+    }
+}
+impl Default for Inte3 {
+    #[inline(always)]
+    fn default() -> Inte3 {
+        Inte3(0)
+    }
+}
+#[doc = "Force Interrupts"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Intf0(pub u32);
+impl Intf0 {
+    #[doc = "Write 1s to force the corresponding bits in INTS0. The interrupt remains asserted until INTF0 is cleared."]
+    #[inline(always)]
+    pub const fn intf0(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0xffff;
+        val as u16
+    }
+    #[doc = "Write 1s to force the corresponding bits in INTS0. The interrupt remains asserted until INTF0 is cleared."]
+    #[inline(always)]
+    pub fn set_intf0(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+    }
+}
+impl Default for Intf0 {
+    #[inline(always)]
+    fn default() -> Intf0 {
+        Intf0(0)
+    }
+}
+#[doc = "Force Interrupts"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Intf1(pub u32);
+impl Intf1 {
+    #[doc = "Write 1s to force the corresponding bits in INTS1. The interrupt remains asserted until INTF1 is cleared."]
+    #[inline(always)]
+    pub const fn intf1(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0xffff;
+        val as u16
+    }
+    #[doc = "Write 1s to force the corresponding bits in INTS1. The interrupt remains asserted until INTF1 is cleared."]
+    #[inline(always)]
+    pub fn set_intf1(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+    }
+}
+impl Default for Intf1 {
+    #[inline(always)]
+    fn default() -> Intf1 {
+        Intf1(0)
+    }
+}
+#[doc = "Force Interrupts"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Intf2(pub u32);
+impl Intf2 {
+    #[doc = "Write 1s to force the corresponding bits in INTS2. The interrupt remains asserted until INTF2 is cleared."]
+    #[inline(always)]
+    pub const fn intf2(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0xffff;
+        val as u16
+    }
+    #[doc = "Write 1s to force the corresponding bits in INTS2. The interrupt remains asserted until INTF2 is cleared."]
+    #[inline(always)]
+    pub fn set_intf2(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+    }
+}
+impl Default for Intf2 {
+    #[inline(always)]
+    fn default() -> Intf2 {
+        Intf2(0)
+    }
+}
+#[doc = "Force Interrupts"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Intf3(pub u32);
+impl Intf3 {
+    #[doc = "Write 1s to force the corresponding bits in INTS3. The interrupt remains asserted until INTF3 is cleared."]
+    #[inline(always)]
+    pub const fn intf3(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0xffff;
+        val as u16
+    }
+    #[doc = "Write 1s to force the corresponding bits in INTS3. The interrupt remains asserted until INTF3 is cleared."]
+    #[inline(always)]
+    pub fn set_intf3(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+    }
+}
+impl Default for Intf3 {
+    #[inline(always)]
+    fn default() -> Intf3 {
+        Intf3(0)
+    }
+}
+#[doc = "Interrupt Status (raw)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Intr(pub u32);
+impl Intr {
+    #[doc = "Raw interrupt status for DMA Channels 0..15. Bit n corresponds to channel n. Ignores any masking or forcing. Channel interrupts can be cleared by writing a bit mask to INTR or INTS0/1/2/3. Channel interrupts can be routed to either of four system-level IRQs based on INTE0, INTE1, INTE2 and INTE3. The multiple system-level interrupts might be used to allow NVIC IRQ preemption for more time-critical channels, to spread IRQ load across different cores, or to target IRQs to different security domains. It is also valid to ignore the multiple IRQs, and just use INTE0/INTS0/IRQ 0. If this register is accessed at a security/privilege level less than that of a given channel (as defined by that channel's SECCFG_CHx register), then that channel's interrupt status will read as 0, ignore writes."]
+    #[inline(always)]
+    pub const fn intr(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0xffff;
+        val as u16
+    }
+    #[doc = "Raw interrupt status for DMA Channels 0..15. Bit n corresponds to channel n. Ignores any masking or forcing. Channel interrupts can be cleared by writing a bit mask to INTR or INTS0/1/2/3. Channel interrupts can be routed to either of four system-level IRQs based on INTE0, INTE1, INTE2 and INTE3. The multiple system-level interrupts might be used to allow NVIC IRQ preemption for more time-critical channels, to spread IRQ load across different cores, or to target IRQs to different security domains. It is also valid to ignore the multiple IRQs, and just use INTE0/INTS0/IRQ 0. If this register is accessed at a security/privilege level less than that of a given channel (as defined by that channel's SECCFG_CHx register), then that channel's interrupt status will read as 0, ignore writes."]
+    #[inline(always)]
+    pub fn set_intr(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+    }
+}
+impl Default for Intr {
+    #[inline(always)]
+    fn default() -> Intr {
+        Intr(0)
+    }
+}
+#[doc = "Interrupt Status (raw)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Intr1(pub u32);
+impl Intr1 {
+    #[doc = "Raw interrupt status for DMA Channels 0..15. Bit n corresponds to channel n. Ignores any masking or forcing. Channel interrupts can be cleared by writing a bit mask to INTR or INTS0/1/2/3. Channel interrupts can be routed to either of four system-level IRQs based on INTE0, INTE1, INTE2 and INTE3. The multiple system-level interrupts might be used to allow NVIC IRQ preemption for more time-critical channels, to spread IRQ load across different cores, or to target IRQs to different security domains. It is also valid to ignore the multiple IRQs, and just use INTE0/INTS0/IRQ 0. If this register is accessed at a security/privilege level less than that of a given channel (as defined by that channel's SECCFG_CHx register), then that channel's interrupt status will read as 0, ignore writes."]
+    #[inline(always)]
+    pub const fn intr1(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0xffff;
+        val as u16
+    }
+    #[doc = "Raw interrupt status for DMA Channels 0..15. Bit n corresponds to channel n. Ignores any masking or forcing. Channel interrupts can be cleared by writing a bit mask to INTR or INTS0/1/2/3. Channel interrupts can be routed to either of four system-level IRQs based on INTE0, INTE1, INTE2 and INTE3. The multiple system-level interrupts might be used to allow NVIC IRQ preemption for more time-critical channels, to spread IRQ load across different cores, or to target IRQs to different security domains. It is also valid to ignore the multiple IRQs, and just use INTE0/INTS0/IRQ 0. If this register is accessed at a security/privilege level less than that of a given channel (as defined by that channel's SECCFG_CHx register), then that channel's interrupt status will read as 0, ignore writes."]
+    #[inline(always)]
+    pub fn set_intr1(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+    }
+}
+impl Default for Intr1 {
+    #[inline(always)]
+    fn default() -> Intr1 {
+        Intr1(0)
+    }
+}
+#[doc = "Interrupt Status (raw)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Intr2(pub u32);
+impl Intr2 {
+    #[doc = "Raw interrupt status for DMA Channels 0..15. Bit n corresponds to channel n. Ignores any masking or forcing. Channel interrupts can be cleared by writing a bit mask to INTR or INTS0/1/2/3. Channel interrupts can be routed to either of four system-level IRQs based on INTE0, INTE1, INTE2 and INTE3. The multiple system-level interrupts might be used to allow NVIC IRQ preemption for more time-critical channels, to spread IRQ load across different cores, or to target IRQs to different security domains. It is also valid to ignore the multiple IRQs, and just use INTE0/INTS0/IRQ 0. If this register is accessed at a security/privilege level less than that of a given channel (as defined by that channel's SECCFG_CHx register), then that channel's interrupt status will read as 0, ignore writes."]
+    #[inline(always)]
+    pub const fn intr2(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0xffff;
+        val as u16
+    }
+    #[doc = "Raw interrupt status for DMA Channels 0..15. Bit n corresponds to channel n. Ignores any masking or forcing. Channel interrupts can be cleared by writing a bit mask to INTR or INTS0/1/2/3. Channel interrupts can be routed to either of four system-level IRQs based on INTE0, INTE1, INTE2 and INTE3. The multiple system-level interrupts might be used to allow NVIC IRQ preemption for more time-critical channels, to spread IRQ load across different cores, or to target IRQs to different security domains. It is also valid to ignore the multiple IRQs, and just use INTE0/INTS0/IRQ 0. If this register is accessed at a security/privilege level less than that of a given channel (as defined by that channel's SECCFG_CHx register), then that channel's interrupt status will read as 0, ignore writes."]
+    #[inline(always)]
+    pub fn set_intr2(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+    }
+}
+impl Default for Intr2 {
+    #[inline(always)]
+    fn default() -> Intr2 {
+        Intr2(0)
+    }
+}
+#[doc = "Interrupt Status (raw)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Intr3(pub u32);
+impl Intr3 {
+    #[doc = "Raw interrupt status for DMA Channels 0..15. Bit n corresponds to channel n. Ignores any masking or forcing. Channel interrupts can be cleared by writing a bit mask to INTR or INTS0/1/2/3. Channel interrupts can be routed to either of four system-level IRQs based on INTE0, INTE1, INTE2 and INTE3. The multiple system-level interrupts might be used to allow NVIC IRQ preemption for more time-critical channels, to spread IRQ load across different cores, or to target IRQs to different security domains. It is also valid to ignore the multiple IRQs, and just use INTE0/INTS0/IRQ 0. If this register is accessed at a security/privilege level less than that of a given channel (as defined by that channel's SECCFG_CHx register), then that channel's interrupt status will read as 0, ignore writes."]
+    #[inline(always)]
+    pub const fn intr3(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0xffff;
+        val as u16
+    }
+    #[doc = "Raw interrupt status for DMA Channels 0..15. Bit n corresponds to channel n. Ignores any masking or forcing. Channel interrupts can be cleared by writing a bit mask to INTR or INTS0/1/2/3. Channel interrupts can be routed to either of four system-level IRQs based on INTE0, INTE1, INTE2 and INTE3. The multiple system-level interrupts might be used to allow NVIC IRQ preemption for more time-critical channels, to spread IRQ load across different cores, or to target IRQs to different security domains. It is also valid to ignore the multiple IRQs, and just use INTE0/INTS0/IRQ 0. If this register is accessed at a security/privilege level less than that of a given channel (as defined by that channel's SECCFG_CHx register), then that channel's interrupt status will read as 0, ignore writes."]
+    #[inline(always)]
+    pub fn set_intr3(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+    }
+}
+impl Default for Intr3 {
+    #[inline(always)]
+    fn default() -> Intr3 {
+        Intr3(0)
+    }
+}
+#[doc = "Interrupt Status for IRQ 0"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Ints0(pub u32);
+impl Ints0 {
+    #[doc = "Indicates active channel interrupt requests which are currently causing IRQ 0 to be asserted. Channel interrupts can be cleared by writing a bit mask here. Channels with a security/privilege (SECCFG_CHx) greater SECCFG_IRQ0) read as 0 in this register, and ignore writes."]
+    #[inline(always)]
+    pub const fn ints0(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0xffff;
+        val as u16
+    }
+    #[doc = "Indicates active channel interrupt requests which are currently causing IRQ 0 to be asserted. Channel interrupts can be cleared by writing a bit mask here. Channels with a security/privilege (SECCFG_CHx) greater SECCFG_IRQ0) read as 0 in this register, and ignore writes."]
+    #[inline(always)]
+    pub fn set_ints0(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+    }
+}
+impl Default for Ints0 {
+    #[inline(always)]
+    fn default() -> Ints0 {
+        Ints0(0)
+    }
+}
+#[doc = "Interrupt Status for IRQ 1"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Ints1(pub u32);
+impl Ints1 {
+    #[doc = "Indicates active channel interrupt requests which are currently causing IRQ 1 to be asserted. Channel interrupts can be cleared by writing a bit mask here. Channels with a security/privilege (SECCFG_CHx) greater SECCFG_IRQ1) read as 0 in this register, and ignore writes."]
+    #[inline(always)]
+    pub const fn ints1(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0xffff;
+        val as u16
+    }
+    #[doc = "Indicates active channel interrupt requests which are currently causing IRQ 1 to be asserted. Channel interrupts can be cleared by writing a bit mask here. Channels with a security/privilege (SECCFG_CHx) greater SECCFG_IRQ1) read as 0 in this register, and ignore writes."]
+    #[inline(always)]
+    pub fn set_ints1(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+    }
+}
+impl Default for Ints1 {
+    #[inline(always)]
+    fn default() -> Ints1 {
+        Ints1(0)
+    }
+}
+#[doc = "Interrupt Status for IRQ 2"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Ints2(pub u32);
+impl Ints2 {
+    #[doc = "Indicates active channel interrupt requests which are currently causing IRQ 2 to be asserted. Channel interrupts can be cleared by writing a bit mask here. Channels with a security/privilege (SECCFG_CHx) greater SECCFG_IRQ2) read as 0 in this register, and ignore writes."]
+    #[inline(always)]
+    pub const fn ints2(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0xffff;
+        val as u16
+    }
+    #[doc = "Indicates active channel interrupt requests which are currently causing IRQ 2 to be asserted. Channel interrupts can be cleared by writing a bit mask here. Channels with a security/privilege (SECCFG_CHx) greater SECCFG_IRQ2) read as 0 in this register, and ignore writes."]
+    #[inline(always)]
+    pub fn set_ints2(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+    }
+}
+impl Default for Ints2 {
+    #[inline(always)]
+    fn default() -> Ints2 {
+        Ints2(0)
+    }
+}
+#[doc = "Interrupt Status for IRQ 3"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Ints3(pub u32);
+impl Ints3 {
+    #[doc = "Indicates active channel interrupt requests which are currently causing IRQ 3 to be asserted. Channel interrupts can be cleared by writing a bit mask here. Channels with a security/privilege (SECCFG_CHx) greater SECCFG_IRQ3) read as 0 in this register, and ignore writes."]
+    #[inline(always)]
+    pub const fn ints3(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0xffff;
+        val as u16
+    }
+    #[doc = "Indicates active channel interrupt requests which are currently causing IRQ 3 to be asserted. Channel interrupts can be cleared by writing a bit mask here. Channels with a security/privilege (SECCFG_CHx) greater SECCFG_IRQ3) read as 0 in this register, and ignore writes."]
+    #[inline(always)]
+    pub fn set_ints3(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+    }
+}
+impl Default for Ints3 {
+    #[inline(always)]
+    fn default() -> Ints3 {
+        Ints3(0)
+    }
+}
+#[doc = "Base address register for MPU region 0. Writable only from a Secure, Privileged context."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct MpuBar0(pub u32);
+impl MpuBar0 {
+    #[doc = "This MPU region matches addresses where addr\\[31:5\\] (the 27 most significant bits) are greater than or equal to BAR_ADDR, and less than or equal to LAR_ADDR. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context."]
+    #[inline(always)]
+    pub const fn addr(&self) -> u32 {
+        let val = (self.0 >> 5usize) & 0x07ff_ffff;
+        val as u32
+    }
+    #[doc = "This MPU region matches addresses where addr\\[31:5\\] (the 27 most significant bits) are greater than or equal to BAR_ADDR, and less than or equal to LAR_ADDR. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context."]
+    #[inline(always)]
+    pub fn set_addr(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x07ff_ffff << 5usize)) | (((val as u32) & 0x07ff_ffff) << 5usize);
+    }
+}
+impl Default for MpuBar0 {
+    #[inline(always)]
+    fn default() -> MpuBar0 {
+        MpuBar0(0)
+    }
+}
+#[doc = "Base address register for MPU region 1. Writable only from a Secure, Privileged context."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct MpuBar1(pub u32);
+impl MpuBar1 {
+    #[doc = "This MPU region matches addresses where addr\\[31:5\\] (the 27 most significant bits) are greater than or equal to BAR_ADDR, and less than or equal to LAR_ADDR. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context."]
+    #[inline(always)]
+    pub const fn addr(&self) -> u32 {
+        let val = (self.0 >> 5usize) & 0x07ff_ffff;
+        val as u32
+    }
+    #[doc = "This MPU region matches addresses where addr\\[31:5\\] (the 27 most significant bits) are greater than or equal to BAR_ADDR, and less than or equal to LAR_ADDR. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context."]
+    #[inline(always)]
+    pub fn set_addr(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x07ff_ffff << 5usize)) | (((val as u32) & 0x07ff_ffff) << 5usize);
+    }
+}
+impl Default for MpuBar1 {
+    #[inline(always)]
+    fn default() -> MpuBar1 {
+        MpuBar1(0)
+    }
+}
+#[doc = "Base address register for MPU region 2. Writable only from a Secure, Privileged context."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct MpuBar2(pub u32);
+impl MpuBar2 {
+    #[doc = "This MPU region matches addresses where addr\\[31:5\\] (the 27 most significant bits) are greater than or equal to BAR_ADDR, and less than or equal to LAR_ADDR. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context."]
+    #[inline(always)]
+    pub const fn addr(&self) -> u32 {
+        let val = (self.0 >> 5usize) & 0x07ff_ffff;
+        val as u32
+    }
+    #[doc = "This MPU region matches addresses where addr\\[31:5\\] (the 27 most significant bits) are greater than or equal to BAR_ADDR, and less than or equal to LAR_ADDR. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context."]
+    #[inline(always)]
+    pub fn set_addr(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x07ff_ffff << 5usize)) | (((val as u32) & 0x07ff_ffff) << 5usize);
+    }
+}
+impl Default for MpuBar2 {
+    #[inline(always)]
+    fn default() -> MpuBar2 {
+        MpuBar2(0)
+    }
+}
+#[doc = "Base address register for MPU region 3. Writable only from a Secure, Privileged context."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct MpuBar3(pub u32);
+impl MpuBar3 {
+    #[doc = "This MPU region matches addresses where addr\\[31:5\\] (the 27 most significant bits) are greater than or equal to BAR_ADDR, and less than or equal to LAR_ADDR. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context."]
+    #[inline(always)]
+    pub const fn addr(&self) -> u32 {
+        let val = (self.0 >> 5usize) & 0x07ff_ffff;
+        val as u32
+    }
+    #[doc = "This MPU region matches addresses where addr\\[31:5\\] (the 27 most significant bits) are greater than or equal to BAR_ADDR, and less than or equal to LAR_ADDR. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context."]
+    #[inline(always)]
+    pub fn set_addr(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x07ff_ffff << 5usize)) | (((val as u32) & 0x07ff_ffff) << 5usize);
+    }
+}
+impl Default for MpuBar3 {
+    #[inline(always)]
+    fn default() -> MpuBar3 {
+        MpuBar3(0)
+    }
+}
+#[doc = "Base address register for MPU region 4. Writable only from a Secure, Privileged context."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct MpuBar4(pub u32);
+impl MpuBar4 {
+    #[doc = "This MPU region matches addresses where addr\\[31:5\\] (the 27 most significant bits) are greater than or equal to BAR_ADDR, and less than or equal to LAR_ADDR. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context."]
+    #[inline(always)]
+    pub const fn addr(&self) -> u32 {
+        let val = (self.0 >> 5usize) & 0x07ff_ffff;
+        val as u32
+    }
+    #[doc = "This MPU region matches addresses where addr\\[31:5\\] (the 27 most significant bits) are greater than or equal to BAR_ADDR, and less than or equal to LAR_ADDR. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context."]
+    #[inline(always)]
+    pub fn set_addr(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x07ff_ffff << 5usize)) | (((val as u32) & 0x07ff_ffff) << 5usize);
+    }
+}
+impl Default for MpuBar4 {
+    #[inline(always)]
+    fn default() -> MpuBar4 {
+        MpuBar4(0)
+    }
+}
+#[doc = "Base address register for MPU region 5. Writable only from a Secure, Privileged context."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct MpuBar5(pub u32);
+impl MpuBar5 {
+    #[doc = "This MPU region matches addresses where addr\\[31:5\\] (the 27 most significant bits) are greater than or equal to BAR_ADDR, and less than or equal to LAR_ADDR. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context."]
+    #[inline(always)]
+    pub const fn addr(&self) -> u32 {
+        let val = (self.0 >> 5usize) & 0x07ff_ffff;
+        val as u32
+    }
+    #[doc = "This MPU region matches addresses where addr\\[31:5\\] (the 27 most significant bits) are greater than or equal to BAR_ADDR, and less than or equal to LAR_ADDR. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context."]
+    #[inline(always)]
+    pub fn set_addr(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x07ff_ffff << 5usize)) | (((val as u32) & 0x07ff_ffff) << 5usize);
+    }
+}
+impl Default for MpuBar5 {
+    #[inline(always)]
+    fn default() -> MpuBar5 {
+        MpuBar5(0)
+    }
+}
+#[doc = "Base address register for MPU region 6. Writable only from a Secure, Privileged context."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct MpuBar6(pub u32);
+impl MpuBar6 {
+    #[doc = "This MPU region matches addresses where addr\\[31:5\\] (the 27 most significant bits) are greater than or equal to BAR_ADDR, and less than or equal to LAR_ADDR. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context."]
+    #[inline(always)]
+    pub const fn addr(&self) -> u32 {
+        let val = (self.0 >> 5usize) & 0x07ff_ffff;
+        val as u32
+    }
+    #[doc = "This MPU region matches addresses where addr\\[31:5\\] (the 27 most significant bits) are greater than or equal to BAR_ADDR, and less than or equal to LAR_ADDR. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context."]
+    #[inline(always)]
+    pub fn set_addr(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x07ff_ffff << 5usize)) | (((val as u32) & 0x07ff_ffff) << 5usize);
+    }
+}
+impl Default for MpuBar6 {
+    #[inline(always)]
+    fn default() -> MpuBar6 {
+        MpuBar6(0)
+    }
+}
+#[doc = "Base address register for MPU region 7. Writable only from a Secure, Privileged context."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct MpuBar7(pub u32);
+impl MpuBar7 {
+    #[doc = "This MPU region matches addresses where addr\\[31:5\\] (the 27 most significant bits) are greater than or equal to BAR_ADDR, and less than or equal to LAR_ADDR. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context."]
+    #[inline(always)]
+    pub const fn addr(&self) -> u32 {
+        let val = (self.0 >> 5usize) & 0x07ff_ffff;
+        val as u32
+    }
+    #[doc = "This MPU region matches addresses where addr\\[31:5\\] (the 27 most significant bits) are greater than or equal to BAR_ADDR, and less than or equal to LAR_ADDR. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context."]
+    #[inline(always)]
+    pub fn set_addr(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x07ff_ffff << 5usize)) | (((val as u32) & 0x07ff_ffff) << 5usize);
+    }
+}
+impl Default for MpuBar7 {
+    #[inline(always)]
+    fn default() -> MpuBar7 {
+        MpuBar7(0)
+    }
+}
+#[doc = "Control register for DMA MPU. Accessible only from a Privileged context."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct MpuCtrl(pub u32);
+impl MpuCtrl {
+    #[doc = "Determine whether an address not covered by an active MPU region is Privileged (1) or Unprivileged (0)"]
+    #[inline(always)]
+    pub const fn p(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Determine whether an address not covered by an active MPU region is Privileged (1) or Unprivileged (0)"]
+    #[inline(always)]
+    pub fn set_p(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+    #[doc = "Determine whether an address not covered by an active MPU region is Secure (1) or Non-secure (0)"]
+    #[inline(always)]
+    pub const fn s(&self) -> bool {
+        let val = (self.0 >> 2usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Determine whether an address not covered by an active MPU region is Secure (1) or Non-secure (0)"]
+    #[inline(always)]
+    pub fn set_s(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+    }
+    #[doc = "By default, when a region's S bit is clear, Non-secure-Privileged reads can see the region's base address and limit address. Set this bit to make the addresses appear as 0 to Non-secure reads, even when the region is Non-secure, to avoid leaking information about the processor SAU map."]
+    #[inline(always)]
+    pub const fn ns_hide_addr(&self) -> bool {
+        let val = (self.0 >> 3usize) & 0x01;
+        val != 0
+    }
+    #[doc = "By default, when a region's S bit is clear, Non-secure-Privileged reads can see the region's base address and limit address. Set this bit to make the addresses appear as 0 to Non-secure reads, even when the region is Non-secure, to avoid leaking information about the processor SAU map."]
+    #[inline(always)]
+    pub fn set_ns_hide_addr(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
+    }
+}
+impl Default for MpuCtrl {
+    #[inline(always)]
+    fn default() -> MpuCtrl {
+        MpuCtrl(0)
+    }
+}
+#[doc = "Limit address register for MPU region 0. Writable only from a Secure, Privileged context, with the exception of the P bit."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct MpuLar0(pub u32);
+impl MpuLar0 {
+    #[doc = "Region enable. If 1, any address within range specified by the base address (BAR_ADDR) and limit address (LAR_ADDR) has the attributes specified by S and P."]
+    #[inline(always)]
+    pub const fn en(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Region enable. If 1, any address within range specified by the base address (BAR_ADDR) and limit address (LAR_ADDR) has the attributes specified by S and P."]
+    #[inline(always)]
+    pub fn set_en(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[doc = "Determines the Privileged/Unprivileged (=1/0) status of addresses matching this region, if this region is enabled. Writable from any Privileged context, if and only if the S bit is clear. Otherwise, writable only from a Secure, Privileged context."]
+    #[inline(always)]
+    pub const fn p(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Determines the Privileged/Unprivileged (=1/0) status of addresses matching this region, if this region is enabled. Writable from any Privileged context, if and only if the S bit is clear. Otherwise, writable only from a Secure, Privileged context."]
+    #[inline(always)]
+    pub fn set_p(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+    #[doc = "Determines the Secure/Non-secure (=1/0) status of addresses matching this region, if this region is enabled."]
+    #[inline(always)]
+    pub const fn s(&self) -> bool {
+        let val = (self.0 >> 2usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Determines the Secure/Non-secure (=1/0) status of addresses matching this region, if this region is enabled."]
+    #[inline(always)]
+    pub fn set_s(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+    }
+    #[doc = "Limit address bits 31:5. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context."]
+    #[inline(always)]
+    pub const fn addr(&self) -> u32 {
+        let val = (self.0 >> 5usize) & 0x07ff_ffff;
+        val as u32
+    }
+    #[doc = "Limit address bits 31:5. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context."]
+    #[inline(always)]
+    pub fn set_addr(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x07ff_ffff << 5usize)) | (((val as u32) & 0x07ff_ffff) << 5usize);
+    }
+}
+impl Default for MpuLar0 {
+    #[inline(always)]
+    fn default() -> MpuLar0 {
+        MpuLar0(0)
+    }
+}
+#[doc = "Limit address register for MPU region 1. Writable only from a Secure, Privileged context, with the exception of the P bit."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct MpuLar1(pub u32);
+impl MpuLar1 {
+    #[doc = "Region enable. If 1, any address within range specified by the base address (BAR_ADDR) and limit address (LAR_ADDR) has the attributes specified by S and P."]
+    #[inline(always)]
+    pub const fn en(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Region enable. If 1, any address within range specified by the base address (BAR_ADDR) and limit address (LAR_ADDR) has the attributes specified by S and P."]
+    #[inline(always)]
+    pub fn set_en(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[doc = "Determines the Privileged/Unprivileged (=1/0) status of addresses matching this region, if this region is enabled. Writable from any Privileged context, if and only if the S bit is clear. Otherwise, writable only from a Secure, Privileged context."]
+    #[inline(always)]
+    pub const fn p(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Determines the Privileged/Unprivileged (=1/0) status of addresses matching this region, if this region is enabled. Writable from any Privileged context, if and only if the S bit is clear. Otherwise, writable only from a Secure, Privileged context."]
+    #[inline(always)]
+    pub fn set_p(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+    #[doc = "Determines the Secure/Non-secure (=1/0) status of addresses matching this region, if this region is enabled."]
+    #[inline(always)]
+    pub const fn s(&self) -> bool {
+        let val = (self.0 >> 2usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Determines the Secure/Non-secure (=1/0) status of addresses matching this region, if this region is enabled."]
+    #[inline(always)]
+    pub fn set_s(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+    }
+    #[doc = "Limit address bits 31:5. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context."]
+    #[inline(always)]
+    pub const fn addr(&self) -> u32 {
+        let val = (self.0 >> 5usize) & 0x07ff_ffff;
+        val as u32
+    }
+    #[doc = "Limit address bits 31:5. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context."]
+    #[inline(always)]
+    pub fn set_addr(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x07ff_ffff << 5usize)) | (((val as u32) & 0x07ff_ffff) << 5usize);
+    }
+}
+impl Default for MpuLar1 {
+    #[inline(always)]
+    fn default() -> MpuLar1 {
+        MpuLar1(0)
+    }
+}
+#[doc = "Limit address register for MPU region 2. Writable only from a Secure, Privileged context, with the exception of the P bit."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct MpuLar2(pub u32);
+impl MpuLar2 {
+    #[doc = "Region enable. If 1, any address within range specified by the base address (BAR_ADDR) and limit address (LAR_ADDR) has the attributes specified by S and P."]
+    #[inline(always)]
+    pub const fn en(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Region enable. If 1, any address within range specified by the base address (BAR_ADDR) and limit address (LAR_ADDR) has the attributes specified by S and P."]
+    #[inline(always)]
+    pub fn set_en(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[doc = "Determines the Privileged/Unprivileged (=1/0) status of addresses matching this region, if this region is enabled. Writable from any Privileged context, if and only if the S bit is clear. Otherwise, writable only from a Secure, Privileged context."]
+    #[inline(always)]
+    pub const fn p(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Determines the Privileged/Unprivileged (=1/0) status of addresses matching this region, if this region is enabled. Writable from any Privileged context, if and only if the S bit is clear. Otherwise, writable only from a Secure, Privileged context."]
+    #[inline(always)]
+    pub fn set_p(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+    #[doc = "Determines the Secure/Non-secure (=1/0) status of addresses matching this region, if this region is enabled."]
+    #[inline(always)]
+    pub const fn s(&self) -> bool {
+        let val = (self.0 >> 2usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Determines the Secure/Non-secure (=1/0) status of addresses matching this region, if this region is enabled."]
+    #[inline(always)]
+    pub fn set_s(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+    }
+    #[doc = "Limit address bits 31:5. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context."]
+    #[inline(always)]
+    pub const fn addr(&self) -> u32 {
+        let val = (self.0 >> 5usize) & 0x07ff_ffff;
+        val as u32
+    }
+    #[doc = "Limit address bits 31:5. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context."]
+    #[inline(always)]
+    pub fn set_addr(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x07ff_ffff << 5usize)) | (((val as u32) & 0x07ff_ffff) << 5usize);
+    }
+}
+impl Default for MpuLar2 {
+    #[inline(always)]
+    fn default() -> MpuLar2 {
+        MpuLar2(0)
+    }
+}
+#[doc = "Limit address register for MPU region 3. Writable only from a Secure, Privileged context, with the exception of the P bit."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct MpuLar3(pub u32);
+impl MpuLar3 {
+    #[doc = "Region enable. If 1, any address within range specified by the base address (BAR_ADDR) and limit address (LAR_ADDR) has the attributes specified by S and P."]
+    #[inline(always)]
+    pub const fn en(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Region enable. If 1, any address within range specified by the base address (BAR_ADDR) and limit address (LAR_ADDR) has the attributes specified by S and P."]
+    #[inline(always)]
+    pub fn set_en(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[doc = "Determines the Privileged/Unprivileged (=1/0) status of addresses matching this region, if this region is enabled. Writable from any Privileged context, if and only if the S bit is clear. Otherwise, writable only from a Secure, Privileged context."]
+    #[inline(always)]
+    pub const fn p(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Determines the Privileged/Unprivileged (=1/0) status of addresses matching this region, if this region is enabled. Writable from any Privileged context, if and only if the S bit is clear. Otherwise, writable only from a Secure, Privileged context."]
+    #[inline(always)]
+    pub fn set_p(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+    #[doc = "Determines the Secure/Non-secure (=1/0) status of addresses matching this region, if this region is enabled."]
+    #[inline(always)]
+    pub const fn s(&self) -> bool {
+        let val = (self.0 >> 2usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Determines the Secure/Non-secure (=1/0) status of addresses matching this region, if this region is enabled."]
+    #[inline(always)]
+    pub fn set_s(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+    }
+    #[doc = "Limit address bits 31:5. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context."]
+    #[inline(always)]
+    pub const fn addr(&self) -> u32 {
+        let val = (self.0 >> 5usize) & 0x07ff_ffff;
+        val as u32
+    }
+    #[doc = "Limit address bits 31:5. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context."]
+    #[inline(always)]
+    pub fn set_addr(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x07ff_ffff << 5usize)) | (((val as u32) & 0x07ff_ffff) << 5usize);
+    }
+}
+impl Default for MpuLar3 {
+    #[inline(always)]
+    fn default() -> MpuLar3 {
+        MpuLar3(0)
+    }
+}
+#[doc = "Limit address register for MPU region 4. Writable only from a Secure, Privileged context, with the exception of the P bit."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct MpuLar4(pub u32);
+impl MpuLar4 {
+    #[doc = "Region enable. If 1, any address within range specified by the base address (BAR_ADDR) and limit address (LAR_ADDR) has the attributes specified by S and P."]
+    #[inline(always)]
+    pub const fn en(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Region enable. If 1, any address within range specified by the base address (BAR_ADDR) and limit address (LAR_ADDR) has the attributes specified by S and P."]
+    #[inline(always)]
+    pub fn set_en(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[doc = "Determines the Privileged/Unprivileged (=1/0) status of addresses matching this region, if this region is enabled. Writable from any Privileged context, if and only if the S bit is clear. Otherwise, writable only from a Secure, Privileged context."]
+    #[inline(always)]
+    pub const fn p(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Determines the Privileged/Unprivileged (=1/0) status of addresses matching this region, if this region is enabled. Writable from any Privileged context, if and only if the S bit is clear. Otherwise, writable only from a Secure, Privileged context."]
+    #[inline(always)]
+    pub fn set_p(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+    #[doc = "Determines the Secure/Non-secure (=1/0) status of addresses matching this region, if this region is enabled."]
+    #[inline(always)]
+    pub const fn s(&self) -> bool {
+        let val = (self.0 >> 2usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Determines the Secure/Non-secure (=1/0) status of addresses matching this region, if this region is enabled."]
+    #[inline(always)]
+    pub fn set_s(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+    }
+    #[doc = "Limit address bits 31:5. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context."]
+    #[inline(always)]
+    pub const fn addr(&self) -> u32 {
+        let val = (self.0 >> 5usize) & 0x07ff_ffff;
+        val as u32
+    }
+    #[doc = "Limit address bits 31:5. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context."]
+    #[inline(always)]
+    pub fn set_addr(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x07ff_ffff << 5usize)) | (((val as u32) & 0x07ff_ffff) << 5usize);
+    }
+}
+impl Default for MpuLar4 {
+    #[inline(always)]
+    fn default() -> MpuLar4 {
+        MpuLar4(0)
+    }
+}
+#[doc = "Limit address register for MPU region 5. Writable only from a Secure, Privileged context, with the exception of the P bit."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct MpuLar5(pub u32);
+impl MpuLar5 {
+    #[doc = "Region enable. If 1, any address within range specified by the base address (BAR_ADDR) and limit address (LAR_ADDR) has the attributes specified by S and P."]
+    #[inline(always)]
+    pub const fn en(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Region enable. If 1, any address within range specified by the base address (BAR_ADDR) and limit address (LAR_ADDR) has the attributes specified by S and P."]
+    #[inline(always)]
+    pub fn set_en(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[doc = "Determines the Privileged/Unprivileged (=1/0) status of addresses matching this region, if this region is enabled. Writable from any Privileged context, if and only if the S bit is clear. Otherwise, writable only from a Secure, Privileged context."]
+    #[inline(always)]
+    pub const fn p(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Determines the Privileged/Unprivileged (=1/0) status of addresses matching this region, if this region is enabled. Writable from any Privileged context, if and only if the S bit is clear. Otherwise, writable only from a Secure, Privileged context."]
+    #[inline(always)]
+    pub fn set_p(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+    #[doc = "Determines the Secure/Non-secure (=1/0) status of addresses matching this region, if this region is enabled."]
+    #[inline(always)]
+    pub const fn s(&self) -> bool {
+        let val = (self.0 >> 2usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Determines the Secure/Non-secure (=1/0) status of addresses matching this region, if this region is enabled."]
+    #[inline(always)]
+    pub fn set_s(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+    }
+    #[doc = "Limit address bits 31:5. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context."]
+    #[inline(always)]
+    pub const fn addr(&self) -> u32 {
+        let val = (self.0 >> 5usize) & 0x07ff_ffff;
+        val as u32
+    }
+    #[doc = "Limit address bits 31:5. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context."]
+    #[inline(always)]
+    pub fn set_addr(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x07ff_ffff << 5usize)) | (((val as u32) & 0x07ff_ffff) << 5usize);
+    }
+}
+impl Default for MpuLar5 {
+    #[inline(always)]
+    fn default() -> MpuLar5 {
+        MpuLar5(0)
+    }
+}
+#[doc = "Limit address register for MPU region 6. Writable only from a Secure, Privileged context, with the exception of the P bit."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct MpuLar6(pub u32);
+impl MpuLar6 {
+    #[doc = "Region enable. If 1, any address within range specified by the base address (BAR_ADDR) and limit address (LAR_ADDR) has the attributes specified by S and P."]
+    #[inline(always)]
+    pub const fn en(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Region enable. If 1, any address within range specified by the base address (BAR_ADDR) and limit address (LAR_ADDR) has the attributes specified by S and P."]
+    #[inline(always)]
+    pub fn set_en(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[doc = "Determines the Privileged/Unprivileged (=1/0) status of addresses matching this region, if this region is enabled. Writable from any Privileged context, if and only if the S bit is clear. Otherwise, writable only from a Secure, Privileged context."]
+    #[inline(always)]
+    pub const fn p(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Determines the Privileged/Unprivileged (=1/0) status of addresses matching this region, if this region is enabled. Writable from any Privileged context, if and only if the S bit is clear. Otherwise, writable only from a Secure, Privileged context."]
+    #[inline(always)]
+    pub fn set_p(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+    #[doc = "Determines the Secure/Non-secure (=1/0) status of addresses matching this region, if this region is enabled."]
+    #[inline(always)]
+    pub const fn s(&self) -> bool {
+        let val = (self.0 >> 2usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Determines the Secure/Non-secure (=1/0) status of addresses matching this region, if this region is enabled."]
+    #[inline(always)]
+    pub fn set_s(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+    }
+    #[doc = "Limit address bits 31:5. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context."]
+    #[inline(always)]
+    pub const fn addr(&self) -> u32 {
+        let val = (self.0 >> 5usize) & 0x07ff_ffff;
+        val as u32
+    }
+    #[doc = "Limit address bits 31:5. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context."]
+    #[inline(always)]
+    pub fn set_addr(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x07ff_ffff << 5usize)) | (((val as u32) & 0x07ff_ffff) << 5usize);
+    }
+}
+impl Default for MpuLar6 {
+    #[inline(always)]
+    fn default() -> MpuLar6 {
+        MpuLar6(0)
+    }
+}
+#[doc = "Limit address register for MPU region 7. Writable only from a Secure, Privileged context, with the exception of the P bit."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct MpuLar7(pub u32);
+impl MpuLar7 {
+    #[doc = "Region enable. If 1, any address within range specified by the base address (BAR_ADDR) and limit address (LAR_ADDR) has the attributes specified by S and P."]
+    #[inline(always)]
+    pub const fn en(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Region enable. If 1, any address within range specified by the base address (BAR_ADDR) and limit address (LAR_ADDR) has the attributes specified by S and P."]
+    #[inline(always)]
+    pub fn set_en(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[doc = "Determines the Privileged/Unprivileged (=1/0) status of addresses matching this region, if this region is enabled. Writable from any Privileged context, if and only if the S bit is clear. Otherwise, writable only from a Secure, Privileged context."]
+    #[inline(always)]
+    pub const fn p(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Determines the Privileged/Unprivileged (=1/0) status of addresses matching this region, if this region is enabled. Writable from any Privileged context, if and only if the S bit is clear. Otherwise, writable only from a Secure, Privileged context."]
+    #[inline(always)]
+    pub fn set_p(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+    #[doc = "Determines the Secure/Non-secure (=1/0) status of addresses matching this region, if this region is enabled."]
+    #[inline(always)]
+    pub const fn s(&self) -> bool {
+        let val = (self.0 >> 2usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Determines the Secure/Non-secure (=1/0) status of addresses matching this region, if this region is enabled."]
+    #[inline(always)]
+    pub fn set_s(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+    }
+    #[doc = "Limit address bits 31:5. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context."]
+    #[inline(always)]
+    pub const fn addr(&self) -> u32 {
+        let val = (self.0 >> 5usize) & 0x07ff_ffff;
+        val as u32
+    }
+    #[doc = "Limit address bits 31:5. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context."]
+    #[inline(always)]
+    pub fn set_addr(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x07ff_ffff << 5usize)) | (((val as u32) & 0x07ff_ffff) << 5usize);
+    }
+}
+impl Default for MpuLar7 {
+    #[inline(always)]
+    fn default() -> MpuLar7 {
+        MpuLar7(0)
+    }
+}
+#[doc = "Trigger one or more channels simultaneously"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct MultiChanTrigger(pub u32);
+impl MultiChanTrigger {
+    #[doc = "Each bit in this register corresponds to a DMA channel. Writing a 1 to the relevant bit is the same as writing to that channel's trigger register; the channel will start if it is currently enabled and not already busy."]
+    #[inline(always)]
+    pub const fn multi_chan_trigger(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0xffff;
+        val as u16
+    }
+    #[doc = "Each bit in this register corresponds to a DMA channel. Writing a 1 to the relevant bit is the same as writing to that channel's trigger register; the channel will start if it is currently enabled and not already busy."]
+    #[inline(always)]
+    pub fn set_multi_chan_trigger(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+    }
+}
+impl Default for MultiChanTrigger {
+    #[inline(always)]
+    fn default() -> MultiChanTrigger {
+        MultiChanTrigger(0)
+    }
+}
+#[doc = "The number of channels this DMA instance is equipped with. This DMA supports up to 16 hardware channels, but can be configured with as few as one, to minimise silicon area."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Nchannels(pub u32);
+impl Nchannels {
+    #[inline(always)]
+    pub const fn n_channels(&self) -> u8 {
+        let val = (self.0 >> 0usize) & 0x1f;
+        val as u8
+    }
+    #[inline(always)]
+    pub fn set_n_channels(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x1f << 0usize)) | (((val as u32) & 0x1f) << 0usize);
+    }
+}
+impl Default for Nchannels {
+    #[inline(always)]
+    fn default() -> Nchannels {
+        Nchannels(0)
+    }
+}
+#[doc = "Security configuration for channel 0. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. This register automatically locks down (becomes read-only) once software starts to configure the channel. This register is world-readable, but is writable only from a Secure, Privileged context."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct SeccfgCh0(pub u32);
+impl SeccfgCh0 {
+    #[doc = "Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level."]
+    #[inline(always)]
+    pub const fn p(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level."]
+    #[inline(always)]
+    pub fn set_p(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[doc = "Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. If 1, this channel is controllable only from a Secure context."]
+    #[inline(always)]
+    pub const fn s(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. If 1, this channel is controllable only from a Secure context."]
+    #[inline(always)]
+    pub fn set_s(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+    #[doc = "LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. Once its LOCK bit is set, this register becomes read-only. A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit."]
+    #[inline(always)]
+    pub const fn lock(&self) -> bool {
+        let val = (self.0 >> 2usize) & 0x01;
+        val != 0
+    }
+    #[doc = "LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. Once its LOCK bit is set, this register becomes read-only. A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit."]
+    #[inline(always)]
+    pub fn set_lock(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+    }
+}
+impl Default for SeccfgCh0 {
+    #[inline(always)]
+    fn default() -> SeccfgCh0 {
+        SeccfgCh0(0)
+    }
+}
+#[doc = "Security configuration for channel 1. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. This register automatically locks down (becomes read-only) once software starts to configure the channel. This register is world-readable, but is writable only from a Secure, Privileged context."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct SeccfgCh1(pub u32);
+impl SeccfgCh1 {
+    #[doc = "Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level."]
+    #[inline(always)]
+    pub const fn p(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level."]
+    #[inline(always)]
+    pub fn set_p(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[doc = "Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. If 1, this channel is controllable only from a Secure context."]
+    #[inline(always)]
+    pub const fn s(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. If 1, this channel is controllable only from a Secure context."]
+    #[inline(always)]
+    pub fn set_s(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+    #[doc = "LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. Once its LOCK bit is set, this register becomes read-only. A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit."]
+    #[inline(always)]
+    pub const fn lock(&self) -> bool {
+        let val = (self.0 >> 2usize) & 0x01;
+        val != 0
+    }
+    #[doc = "LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. Once its LOCK bit is set, this register becomes read-only. A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit."]
+    #[inline(always)]
+    pub fn set_lock(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+    }
+}
+impl Default for SeccfgCh1 {
+    #[inline(always)]
+    fn default() -> SeccfgCh1 {
+        SeccfgCh1(0)
+    }
+}
+#[doc = "Security configuration for channel 10. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. This register automatically locks down (becomes read-only) once software starts to configure the channel. This register is world-readable, but is writable only from a Secure, Privileged context."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct SeccfgCh10(pub u32);
+impl SeccfgCh10 {
+    #[doc = "Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level."]
+    #[inline(always)]
+    pub const fn p(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level."]
+    #[inline(always)]
+    pub fn set_p(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[doc = "Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. If 1, this channel is controllable only from a Secure context."]
+    #[inline(always)]
+    pub const fn s(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. If 1, this channel is controllable only from a Secure context."]
+    #[inline(always)]
+    pub fn set_s(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+    #[doc = "LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. Once its LOCK bit is set, this register becomes read-only. A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit."]
+    #[inline(always)]
+    pub const fn lock(&self) -> bool {
+        let val = (self.0 >> 2usize) & 0x01;
+        val != 0
+    }
+    #[doc = "LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. Once its LOCK bit is set, this register becomes read-only. A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit."]
+    #[inline(always)]
+    pub fn set_lock(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+    }
+}
+impl Default for SeccfgCh10 {
+    #[inline(always)]
+    fn default() -> SeccfgCh10 {
+        SeccfgCh10(0)
+    }
+}
+#[doc = "Security configuration for channel 11. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. This register automatically locks down (becomes read-only) once software starts to configure the channel. This register is world-readable, but is writable only from a Secure, Privileged context."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct SeccfgCh11(pub u32);
+impl SeccfgCh11 {
+    #[doc = "Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level."]
+    #[inline(always)]
+    pub const fn p(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level."]
+    #[inline(always)]
+    pub fn set_p(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[doc = "Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. If 1, this channel is controllable only from a Secure context."]
+    #[inline(always)]
+    pub const fn s(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. If 1, this channel is controllable only from a Secure context."]
+    #[inline(always)]
+    pub fn set_s(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+    #[doc = "LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. Once its LOCK bit is set, this register becomes read-only. A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit."]
+    #[inline(always)]
+    pub const fn lock(&self) -> bool {
+        let val = (self.0 >> 2usize) & 0x01;
+        val != 0
+    }
+    #[doc = "LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. Once its LOCK bit is set, this register becomes read-only. A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit."]
+    #[inline(always)]
+    pub fn set_lock(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+    }
+}
+impl Default for SeccfgCh11 {
+    #[inline(always)]
+    fn default() -> SeccfgCh11 {
+        SeccfgCh11(0)
+    }
+}
+#[doc = "Security configuration for channel 12. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. This register automatically locks down (becomes read-only) once software starts to configure the channel. This register is world-readable, but is writable only from a Secure, Privileged context."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct SeccfgCh12(pub u32);
+impl SeccfgCh12 {
+    #[doc = "Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level."]
+    #[inline(always)]
+    pub const fn p(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level."]
+    #[inline(always)]
+    pub fn set_p(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[doc = "Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. If 1, this channel is controllable only from a Secure context."]
+    #[inline(always)]
+    pub const fn s(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. If 1, this channel is controllable only from a Secure context."]
+    #[inline(always)]
+    pub fn set_s(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+    #[doc = "LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. Once its LOCK bit is set, this register becomes read-only. A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit."]
+    #[inline(always)]
+    pub const fn lock(&self) -> bool {
+        let val = (self.0 >> 2usize) & 0x01;
+        val != 0
+    }
+    #[doc = "LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. Once its LOCK bit is set, this register becomes read-only. A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit."]
+    #[inline(always)]
+    pub fn set_lock(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+    }
+}
+impl Default for SeccfgCh12 {
+    #[inline(always)]
+    fn default() -> SeccfgCh12 {
+        SeccfgCh12(0)
+    }
+}
+#[doc = "Security configuration for channel 13. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. This register automatically locks down (becomes read-only) once software starts to configure the channel. This register is world-readable, but is writable only from a Secure, Privileged context."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct SeccfgCh13(pub u32);
+impl SeccfgCh13 {
+    #[doc = "Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level."]
+    #[inline(always)]
+    pub const fn p(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level."]
+    #[inline(always)]
+    pub fn set_p(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[doc = "Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. If 1, this channel is controllable only from a Secure context."]
+    #[inline(always)]
+    pub const fn s(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. If 1, this channel is controllable only from a Secure context."]
+    #[inline(always)]
+    pub fn set_s(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+    #[doc = "LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. Once its LOCK bit is set, this register becomes read-only. A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit."]
+    #[inline(always)]
+    pub const fn lock(&self) -> bool {
+        let val = (self.0 >> 2usize) & 0x01;
+        val != 0
+    }
+    #[doc = "LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. Once its LOCK bit is set, this register becomes read-only. A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit."]
+    #[inline(always)]
+    pub fn set_lock(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+    }
+}
+impl Default for SeccfgCh13 {
+    #[inline(always)]
+    fn default() -> SeccfgCh13 {
+        SeccfgCh13(0)
+    }
+}
+#[doc = "Security configuration for channel 14. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. This register automatically locks down (becomes read-only) once software starts to configure the channel. This register is world-readable, but is writable only from a Secure, Privileged context."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct SeccfgCh14(pub u32);
+impl SeccfgCh14 {
+    #[doc = "Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level."]
+    #[inline(always)]
+    pub const fn p(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level."]
+    #[inline(always)]
+    pub fn set_p(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[doc = "Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. If 1, this channel is controllable only from a Secure context."]
+    #[inline(always)]
+    pub const fn s(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. If 1, this channel is controllable only from a Secure context."]
+    #[inline(always)]
+    pub fn set_s(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+    #[doc = "LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. Once its LOCK bit is set, this register becomes read-only. A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit."]
+    #[inline(always)]
+    pub const fn lock(&self) -> bool {
+        let val = (self.0 >> 2usize) & 0x01;
+        val != 0
+    }
+    #[doc = "LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. Once its LOCK bit is set, this register becomes read-only. A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit."]
+    #[inline(always)]
+    pub fn set_lock(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+    }
+}
+impl Default for SeccfgCh14 {
+    #[inline(always)]
+    fn default() -> SeccfgCh14 {
+        SeccfgCh14(0)
+    }
+}
+#[doc = "Security configuration for channel 15. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. This register automatically locks down (becomes read-only) once software starts to configure the channel. This register is world-readable, but is writable only from a Secure, Privileged context."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct SeccfgCh15(pub u32);
+impl SeccfgCh15 {
+    #[doc = "Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level."]
+    #[inline(always)]
+    pub const fn p(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level."]
+    #[inline(always)]
+    pub fn set_p(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[doc = "Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. If 1, this channel is controllable only from a Secure context."]
+    #[inline(always)]
+    pub const fn s(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. If 1, this channel is controllable only from a Secure context."]
+    #[inline(always)]
+    pub fn set_s(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+    #[doc = "LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. Once its LOCK bit is set, this register becomes read-only. A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit."]
+    #[inline(always)]
+    pub const fn lock(&self) -> bool {
+        let val = (self.0 >> 2usize) & 0x01;
+        val != 0
+    }
+    #[doc = "LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. Once its LOCK bit is set, this register becomes read-only. A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit."]
+    #[inline(always)]
+    pub fn set_lock(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+    }
+}
+impl Default for SeccfgCh15 {
+    #[inline(always)]
+    fn default() -> SeccfgCh15 {
+        SeccfgCh15(0)
+    }
+}
+#[doc = "Security configuration for channel 2. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. This register automatically locks down (becomes read-only) once software starts to configure the channel. This register is world-readable, but is writable only from a Secure, Privileged context."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct SeccfgCh2(pub u32);
+impl SeccfgCh2 {
+    #[doc = "Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level."]
+    #[inline(always)]
+    pub const fn p(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level."]
+    #[inline(always)]
+    pub fn set_p(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[doc = "Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. If 1, this channel is controllable only from a Secure context."]
+    #[inline(always)]
+    pub const fn s(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. If 1, this channel is controllable only from a Secure context."]
+    #[inline(always)]
+    pub fn set_s(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+    #[doc = "LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. Once its LOCK bit is set, this register becomes read-only. A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit."]
+    #[inline(always)]
+    pub const fn lock(&self) -> bool {
+        let val = (self.0 >> 2usize) & 0x01;
+        val != 0
+    }
+    #[doc = "LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. Once its LOCK bit is set, this register becomes read-only. A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit."]
+    #[inline(always)]
+    pub fn set_lock(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+    }
+}
+impl Default for SeccfgCh2 {
+    #[inline(always)]
+    fn default() -> SeccfgCh2 {
+        SeccfgCh2(0)
+    }
+}
+#[doc = "Security configuration for channel 3. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. This register automatically locks down (becomes read-only) once software starts to configure the channel. This register is world-readable, but is writable only from a Secure, Privileged context."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct SeccfgCh3(pub u32);
+impl SeccfgCh3 {
+    #[doc = "Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level."]
+    #[inline(always)]
+    pub const fn p(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level."]
+    #[inline(always)]
+    pub fn set_p(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[doc = "Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. If 1, this channel is controllable only from a Secure context."]
+    #[inline(always)]
+    pub const fn s(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. If 1, this channel is controllable only from a Secure context."]
+    #[inline(always)]
+    pub fn set_s(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+    #[doc = "LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. Once its LOCK bit is set, this register becomes read-only. A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit."]
+    #[inline(always)]
+    pub const fn lock(&self) -> bool {
+        let val = (self.0 >> 2usize) & 0x01;
+        val != 0
+    }
+    #[doc = "LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. Once its LOCK bit is set, this register becomes read-only. A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit."]
+    #[inline(always)]
+    pub fn set_lock(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+    }
+}
+impl Default for SeccfgCh3 {
+    #[inline(always)]
+    fn default() -> SeccfgCh3 {
+        SeccfgCh3(0)
+    }
+}
+#[doc = "Security configuration for channel 4. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. This register automatically locks down (becomes read-only) once software starts to configure the channel. This register is world-readable, but is writable only from a Secure, Privileged context."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct SeccfgCh4(pub u32);
+impl SeccfgCh4 {
+    #[doc = "Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level."]
+    #[inline(always)]
+    pub const fn p(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level."]
+    #[inline(always)]
+    pub fn set_p(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[doc = "Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. If 1, this channel is controllable only from a Secure context."]
+    #[inline(always)]
+    pub const fn s(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. If 1, this channel is controllable only from a Secure context."]
+    #[inline(always)]
+    pub fn set_s(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+    #[doc = "LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. Once its LOCK bit is set, this register becomes read-only. A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit."]
+    #[inline(always)]
+    pub const fn lock(&self) -> bool {
+        let val = (self.0 >> 2usize) & 0x01;
+        val != 0
+    }
+    #[doc = "LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. Once its LOCK bit is set, this register becomes read-only. A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit."]
+    #[inline(always)]
+    pub fn set_lock(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+    }
+}
+impl Default for SeccfgCh4 {
+    #[inline(always)]
+    fn default() -> SeccfgCh4 {
+        SeccfgCh4(0)
+    }
+}
+#[doc = "Security configuration for channel 5. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. This register automatically locks down (becomes read-only) once software starts to configure the channel. This register is world-readable, but is writable only from a Secure, Privileged context."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct SeccfgCh5(pub u32);
+impl SeccfgCh5 {
+    #[doc = "Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level."]
+    #[inline(always)]
+    pub const fn p(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level."]
+    #[inline(always)]
+    pub fn set_p(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[doc = "Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. If 1, this channel is controllable only from a Secure context."]
+    #[inline(always)]
+    pub const fn s(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. If 1, this channel is controllable only from a Secure context."]
+    #[inline(always)]
+    pub fn set_s(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+    #[doc = "LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. Once its LOCK bit is set, this register becomes read-only. A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit."]
+    #[inline(always)]
+    pub const fn lock(&self) -> bool {
+        let val = (self.0 >> 2usize) & 0x01;
+        val != 0
+    }
+    #[doc = "LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. Once its LOCK bit is set, this register becomes read-only. A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit."]
+    #[inline(always)]
+    pub fn set_lock(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+    }
+}
+impl Default for SeccfgCh5 {
+    #[inline(always)]
+    fn default() -> SeccfgCh5 {
+        SeccfgCh5(0)
+    }
+}
+#[doc = "Security configuration for channel 6. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. This register automatically locks down (becomes read-only) once software starts to configure the channel. This register is world-readable, but is writable only from a Secure, Privileged context."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct SeccfgCh6(pub u32);
+impl SeccfgCh6 {
+    #[doc = "Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level."]
+    #[inline(always)]
+    pub const fn p(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level."]
+    #[inline(always)]
+    pub fn set_p(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[doc = "Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. If 1, this channel is controllable only from a Secure context."]
+    #[inline(always)]
+    pub const fn s(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. If 1, this channel is controllable only from a Secure context."]
+    #[inline(always)]
+    pub fn set_s(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+    #[doc = "LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. Once its LOCK bit is set, this register becomes read-only. A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit."]
+    #[inline(always)]
+    pub const fn lock(&self) -> bool {
+        let val = (self.0 >> 2usize) & 0x01;
+        val != 0
+    }
+    #[doc = "LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. Once its LOCK bit is set, this register becomes read-only. A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit."]
+    #[inline(always)]
+    pub fn set_lock(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+    }
+}
+impl Default for SeccfgCh6 {
+    #[inline(always)]
+    fn default() -> SeccfgCh6 {
+        SeccfgCh6(0)
+    }
+}
+#[doc = "Security configuration for channel 7. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. This register automatically locks down (becomes read-only) once software starts to configure the channel. This register is world-readable, but is writable only from a Secure, Privileged context."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct SeccfgCh7(pub u32);
+impl SeccfgCh7 {
+    #[doc = "Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level."]
+    #[inline(always)]
+    pub const fn p(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level."]
+    #[inline(always)]
+    pub fn set_p(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[doc = "Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. If 1, this channel is controllable only from a Secure context."]
+    #[inline(always)]
+    pub const fn s(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. If 1, this channel is controllable only from a Secure context."]
+    #[inline(always)]
+    pub fn set_s(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+    #[doc = "LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. Once its LOCK bit is set, this register becomes read-only. A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit."]
+    #[inline(always)]
+    pub const fn lock(&self) -> bool {
+        let val = (self.0 >> 2usize) & 0x01;
+        val != 0
+    }
+    #[doc = "LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. Once its LOCK bit is set, this register becomes read-only. A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit."]
+    #[inline(always)]
+    pub fn set_lock(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+    }
+}
+impl Default for SeccfgCh7 {
+    #[inline(always)]
+    fn default() -> SeccfgCh7 {
+        SeccfgCh7(0)
+    }
+}
+#[doc = "Security configuration for channel 8. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. This register automatically locks down (becomes read-only) once software starts to configure the channel. This register is world-readable, but is writable only from a Secure, Privileged context."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct SeccfgCh8(pub u32);
+impl SeccfgCh8 {
+    #[doc = "Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level."]
+    #[inline(always)]
+    pub const fn p(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level."]
+    #[inline(always)]
+    pub fn set_p(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[doc = "Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. If 1, this channel is controllable only from a Secure context."]
+    #[inline(always)]
+    pub const fn s(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. If 1, this channel is controllable only from a Secure context."]
+    #[inline(always)]
+    pub fn set_s(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+    #[doc = "LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. Once its LOCK bit is set, this register becomes read-only. A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit."]
+    #[inline(always)]
+    pub const fn lock(&self) -> bool {
+        let val = (self.0 >> 2usize) & 0x01;
+        val != 0
+    }
+    #[doc = "LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. Once its LOCK bit is set, this register becomes read-only. A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit."]
+    #[inline(always)]
+    pub fn set_lock(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+    }
+}
+impl Default for SeccfgCh8 {
+    #[inline(always)]
+    fn default() -> SeccfgCh8 {
+        SeccfgCh8(0)
+    }
+}
+#[doc = "Security configuration for channel 9. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. This register automatically locks down (becomes read-only) once software starts to configure the channel. This register is world-readable, but is writable only from a Secure, Privileged context."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct SeccfgCh9(pub u32);
+impl SeccfgCh9 {
+    #[doc = "Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level."]
+    #[inline(always)]
+    pub const fn p(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level."]
+    #[inline(always)]
+    pub fn set_p(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[doc = "Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. If 1, this channel is controllable only from a Secure context."]
+    #[inline(always)]
+    pub const fn s(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. If 1, this channel is controllable only from a Secure context."]
+    #[inline(always)]
+    pub fn set_s(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+    #[doc = "LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. Once its LOCK bit is set, this register becomes read-only. A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit."]
+    #[inline(always)]
+    pub const fn lock(&self) -> bool {
+        let val = (self.0 >> 2usize) & 0x01;
+        val != 0
+    }
+    #[doc = "LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. Once its LOCK bit is set, this register becomes read-only. A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit."]
+    #[inline(always)]
+    pub fn set_lock(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+    }
+}
+impl Default for SeccfgCh9 {
+    #[inline(always)]
+    fn default() -> SeccfgCh9 {
+        SeccfgCh9(0)
+    }
+}
+#[doc = "Security configuration for IRQ 0. Control whether the IRQ permits configuration by Non-secure/Unprivileged contexts, and whether it can observe Secure/Privileged channel interrupt flags."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct SeccfgIrq0(pub u32);
+impl SeccfgIrq0 {
+    #[doc = "Privileged IRQ. If 1, this IRQ's control registers can only be accessed from a Privileged context. If 0, this IRQ's control registers can be accessed from an Unprivileged context, but Privileged channels (as per SECCFG_CHx) are masked from the IRQ status, and this IRQ's registers can not be used to acknowledge the channel interrupts of Privileged channels."]
+    #[inline(always)]
+    pub const fn p(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Privileged IRQ. If 1, this IRQ's control registers can only be accessed from a Privileged context. If 0, this IRQ's control registers can be accessed from an Unprivileged context, but Privileged channels (as per SECCFG_CHx) are masked from the IRQ status, and this IRQ's registers can not be used to acknowledge the channel interrupts of Privileged channels."]
+    #[inline(always)]
+    pub fn set_p(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[doc = "Secure IRQ. If 1, this IRQ's control registers can only be accessed from a Secure context. If 0, this IRQ's control registers can be accessed from a Non-secure context, but Secure channels (as per SECCFG_CHx) are masked from the IRQ status, and this IRQ's registers can not be used to acknowledge the channel interrupts of Secure channels."]
+    #[inline(always)]
+    pub const fn s(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Secure IRQ. If 1, this IRQ's control registers can only be accessed from a Secure context. If 0, this IRQ's control registers can be accessed from a Non-secure context, but Secure channels (as per SECCFG_CHx) are masked from the IRQ status, and this IRQ's registers can not be used to acknowledge the channel interrupts of Secure channels."]
+    #[inline(always)]
+    pub fn set_s(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+}
+impl Default for SeccfgIrq0 {
+    #[inline(always)]
+    fn default() -> SeccfgIrq0 {
+        SeccfgIrq0(0)
+    }
+}
+#[doc = "Security configuration for IRQ 1. Control whether the IRQ permits configuration by Non-secure/Unprivileged contexts, and whether it can observe Secure/Privileged channel interrupt flags."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct SeccfgIrq1(pub u32);
+impl SeccfgIrq1 {
+    #[doc = "Privileged IRQ. If 1, this IRQ's control registers can only be accessed from a Privileged context. If 0, this IRQ's control registers can be accessed from an Unprivileged context, but Privileged channels (as per SECCFG_CHx) are masked from the IRQ status, and this IRQ's registers can not be used to acknowledge the channel interrupts of Privileged channels."]
+    #[inline(always)]
+    pub const fn p(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Privileged IRQ. If 1, this IRQ's control registers can only be accessed from a Privileged context. If 0, this IRQ's control registers can be accessed from an Unprivileged context, but Privileged channels (as per SECCFG_CHx) are masked from the IRQ status, and this IRQ's registers can not be used to acknowledge the channel interrupts of Privileged channels."]
+    #[inline(always)]
+    pub fn set_p(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[doc = "Secure IRQ. If 1, this IRQ's control registers can only be accessed from a Secure context. If 0, this IRQ's control registers can be accessed from a Non-secure context, but Secure channels (as per SECCFG_CHx) are masked from the IRQ status, and this IRQ's registers can not be used to acknowledge the channel interrupts of Secure channels."]
+    #[inline(always)]
+    pub const fn s(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Secure IRQ. If 1, this IRQ's control registers can only be accessed from a Secure context. If 0, this IRQ's control registers can be accessed from a Non-secure context, but Secure channels (as per SECCFG_CHx) are masked from the IRQ status, and this IRQ's registers can not be used to acknowledge the channel interrupts of Secure channels."]
+    #[inline(always)]
+    pub fn set_s(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+}
+impl Default for SeccfgIrq1 {
+    #[inline(always)]
+    fn default() -> SeccfgIrq1 {
+        SeccfgIrq1(0)
+    }
+}
+#[doc = "Security configuration for IRQ 2. Control whether the IRQ permits configuration by Non-secure/Unprivileged contexts, and whether it can observe Secure/Privileged channel interrupt flags."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct SeccfgIrq2(pub u32);
+impl SeccfgIrq2 {
+    #[doc = "Privileged IRQ. If 1, this IRQ's control registers can only be accessed from a Privileged context. If 0, this IRQ's control registers can be accessed from an Unprivileged context, but Privileged channels (as per SECCFG_CHx) are masked from the IRQ status, and this IRQ's registers can not be used to acknowledge the channel interrupts of Privileged channels."]
+    #[inline(always)]
+    pub const fn p(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Privileged IRQ. If 1, this IRQ's control registers can only be accessed from a Privileged context. If 0, this IRQ's control registers can be accessed from an Unprivileged context, but Privileged channels (as per SECCFG_CHx) are masked from the IRQ status, and this IRQ's registers can not be used to acknowledge the channel interrupts of Privileged channels."]
+    #[inline(always)]
+    pub fn set_p(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[doc = "Secure IRQ. If 1, this IRQ's control registers can only be accessed from a Secure context. If 0, this IRQ's control registers can be accessed from a Non-secure context, but Secure channels (as per SECCFG_CHx) are masked from the IRQ status, and this IRQ's registers can not be used to acknowledge the channel interrupts of Secure channels."]
+    #[inline(always)]
+    pub const fn s(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Secure IRQ. If 1, this IRQ's control registers can only be accessed from a Secure context. If 0, this IRQ's control registers can be accessed from a Non-secure context, but Secure channels (as per SECCFG_CHx) are masked from the IRQ status, and this IRQ's registers can not be used to acknowledge the channel interrupts of Secure channels."]
+    #[inline(always)]
+    pub fn set_s(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+}
+impl Default for SeccfgIrq2 {
+    #[inline(always)]
+    fn default() -> SeccfgIrq2 {
+        SeccfgIrq2(0)
+    }
+}
+#[doc = "Security configuration for IRQ 3. Control whether the IRQ permits configuration by Non-secure/Unprivileged contexts, and whether it can observe Secure/Privileged channel interrupt flags."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct SeccfgIrq3(pub u32);
+impl SeccfgIrq3 {
+    #[doc = "Privileged IRQ. If 1, this IRQ's control registers can only be accessed from a Privileged context. If 0, this IRQ's control registers can be accessed from an Unprivileged context, but Privileged channels (as per SECCFG_CHx) are masked from the IRQ status, and this IRQ's registers can not be used to acknowledge the channel interrupts of Privileged channels."]
+    #[inline(always)]
+    pub const fn p(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Privileged IRQ. If 1, this IRQ's control registers can only be accessed from a Privileged context. If 0, this IRQ's control registers can be accessed from an Unprivileged context, but Privileged channels (as per SECCFG_CHx) are masked from the IRQ status, and this IRQ's registers can not be used to acknowledge the channel interrupts of Privileged channels."]
+    #[inline(always)]
+    pub fn set_p(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[doc = "Secure IRQ. If 1, this IRQ's control registers can only be accessed from a Secure context. If 0, this IRQ's control registers can be accessed from a Non-secure context, but Secure channels (as per SECCFG_CHx) are masked from the IRQ status, and this IRQ's registers can not be used to acknowledge the channel interrupts of Secure channels."]
+    #[inline(always)]
+    pub const fn s(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Secure IRQ. If 1, this IRQ's control registers can only be accessed from a Secure context. If 0, this IRQ's control registers can be accessed from a Non-secure context, but Secure channels (as per SECCFG_CHx) are masked from the IRQ status, and this IRQ's registers can not be used to acknowledge the channel interrupts of Secure channels."]
+    #[inline(always)]
+    pub fn set_s(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+}
+impl Default for SeccfgIrq3 {
+    #[inline(always)]
+    fn default() -> SeccfgIrq3 {
+        SeccfgIrq3(0)
+    }
+}
+#[doc = "Miscellaneous security configuration"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct SeccfgMisc(pub u32);
+impl SeccfgMisc {
+    #[doc = "If 1, the sniffer can see data transfers from Privileged channels, and can itself only be accessed from a privileged context, or from a Secure context when SNIFF_S is 0. If 0, the sniffer can be accessed from either a Privileged or Unprivileged context (with sufficient security level) but can not see transfers from Privileged channels."]
+    #[inline(always)]
+    pub const fn sniff_p(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, the sniffer can see data transfers from Privileged channels, and can itself only be accessed from a privileged context, or from a Secure context when SNIFF_S is 0. If 0, the sniffer can be accessed from either a Privileged or Unprivileged context (with sufficient security level) but can not see transfers from Privileged channels."]
+    #[inline(always)]
+    pub fn set_sniff_p(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[doc = "If 1, the sniffer can see data transfers from Secure channels, and can itself only be accessed from a Secure context. If 0, the sniffer can be accessed from either a Secure or Non-secure context, but can not see data transfers of Secure channels."]
+    #[inline(always)]
+    pub const fn sniff_s(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, the sniffer can see data transfers from Secure channels, and can itself only be accessed from a Secure context. If 0, the sniffer can be accessed from either a Secure or Non-secure context, but can not see data transfers of Secure channels."]
+    #[inline(always)]
+    pub fn set_sniff_s(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+    #[doc = "If 1, the TIMER0 register is only accessible from a Privileged (or more Secure) context, and timer DREQ 0 is only visible to Privileged (or more Secure) channels."]
+    #[inline(always)]
+    pub const fn timer0_p(&self) -> bool {
+        let val = (self.0 >> 2usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, the TIMER0 register is only accessible from a Privileged (or more Secure) context, and timer DREQ 0 is only visible to Privileged (or more Secure) channels."]
+    #[inline(always)]
+    pub fn set_timer0_p(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+    }
+    #[doc = "If 1, the TIMER0 register is only accessible from a Secure context, and timer DREQ 0 is only visible to Secure channels."]
+    #[inline(always)]
+    pub const fn timer0_s(&self) -> bool {
+        let val = (self.0 >> 3usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, the TIMER0 register is only accessible from a Secure context, and timer DREQ 0 is only visible to Secure channels."]
+    #[inline(always)]
+    pub fn set_timer0_s(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
+    }
+    #[doc = "If 1, the TIMER1 register is only accessible from a Privileged (or more Secure) context, and timer DREQ 1 is only visible to Privileged (or more Secure) channels."]
+    #[inline(always)]
+    pub const fn timer1_p(&self) -> bool {
+        let val = (self.0 >> 4usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, the TIMER1 register is only accessible from a Privileged (or more Secure) context, and timer DREQ 1 is only visible to Privileged (or more Secure) channels."]
+    #[inline(always)]
+    pub fn set_timer1_p(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
+    }
+    #[doc = "If 1, the TIMER1 register is only accessible from a Secure context, and timer DREQ 1 is only visible to Secure channels."]
+    #[inline(always)]
+    pub const fn timer1_s(&self) -> bool {
+        let val = (self.0 >> 5usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, the TIMER1 register is only accessible from a Secure context, and timer DREQ 1 is only visible to Secure channels."]
+    #[inline(always)]
+    pub fn set_timer1_s(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
+    }
+    #[doc = "If 1, the TIMER2 register is only accessible from a Privileged (or more Secure) context, and timer DREQ 2 is only visible to Privileged (or more Secure) channels."]
+    #[inline(always)]
+    pub const fn timer2_p(&self) -> bool {
+        let val = (self.0 >> 6usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, the TIMER2 register is only accessible from a Privileged (or more Secure) context, and timer DREQ 2 is only visible to Privileged (or more Secure) channels."]
+    #[inline(always)]
+    pub fn set_timer2_p(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
+    }
+    #[doc = "If 1, the TIMER2 register is only accessible from a Secure context, and timer DREQ 2 is only visible to Secure channels."]
+    #[inline(always)]
+    pub const fn timer2_s(&self) -> bool {
+        let val = (self.0 >> 7usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, the TIMER2 register is only accessible from a Secure context, and timer DREQ 2 is only visible to Secure channels."]
+    #[inline(always)]
+    pub fn set_timer2_s(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
+    }
+    #[doc = "If 1, the TIMER3 register is only accessible from a Privileged (or more Secure) context, and timer DREQ 3 is only visible to Privileged (or more Secure) channels."]
+    #[inline(always)]
+    pub const fn timer3_p(&self) -> bool {
+        let val = (self.0 >> 8usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, the TIMER3 register is only accessible from a Privileged (or more Secure) context, and timer DREQ 3 is only visible to Privileged (or more Secure) channels."]
+    #[inline(always)]
+    pub fn set_timer3_p(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
+    }
+    #[doc = "If 1, the TIMER3 register is only accessible from a Secure context, and timer DREQ 3 is only visible to Secure channels."]
+    #[inline(always)]
+    pub const fn timer3_s(&self) -> bool {
+        let val = (self.0 >> 9usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, the TIMER3 register is only accessible from a Secure context, and timer DREQ 3 is only visible to Secure channels."]
+    #[inline(always)]
+    pub fn set_timer3_s(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
+    }
+}
+impl Default for SeccfgMisc {
+    #[inline(always)]
+    fn default() -> SeccfgMisc {
+        SeccfgMisc(0)
+    }
+}
+#[doc = "Sniffer Control"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct SniffCtrl(pub u32);
+impl SniffCtrl {
+    #[doc = "Enable sniffer"]
+    #[inline(always)]
+    pub const fn en(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Enable sniffer"]
+    #[inline(always)]
+    pub fn set_en(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[doc = "DMA channel for Sniffer to observe"]
+    #[inline(always)]
+    pub const fn dmach(&self) -> u8 {
+        let val = (self.0 >> 1usize) & 0x0f;
+        val as u8
+    }
+    #[doc = "DMA channel for Sniffer to observe"]
+    #[inline(always)]
+    pub fn set_dmach(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x0f << 1usize)) | (((val as u32) & 0x0f) << 1usize);
+    }
+    #[inline(always)]
+    pub const fn calc(&self) -> super::vals::Calc {
+        let val = (self.0 >> 5usize) & 0x0f;
+        super::vals::Calc::from_bits(val as u8)
+    }
+    #[inline(always)]
+    pub fn set_calc(&mut self, val: super::vals::Calc) {
+        self.0 = (self.0 & !(0x0f << 5usize)) | (((val.to_bits() as u32) & 0x0f) << 5usize);
+    }
+    #[doc = "Locally perform a byte reverse on the sniffed data, before feeding into checksum. Note that the sniff hardware is downstream of the DMA channel byteswap performed in the read master: if channel CTRL_BSWAP and SNIFF_CTRL_BSWAP are both enabled, their effects cancel from the sniffer's point of view."]
+    #[inline(always)]
+    pub const fn bswap(&self) -> bool {
+        let val = (self.0 >> 9usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Locally perform a byte reverse on the sniffed data, before feeding into checksum. Note that the sniff hardware is downstream of the DMA channel byteswap performed in the read master: if channel CTRL_BSWAP and SNIFF_CTRL_BSWAP are both enabled, their effects cancel from the sniffer's point of view."]
+    #[inline(always)]
+    pub fn set_bswap(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
+    }
+    #[doc = "If set, the result appears bit-reversed when read. This does not affect the way the checksum is calculated; the result is transformed on-the-fly between the result register and the bus."]
+    #[inline(always)]
+    pub const fn out_rev(&self) -> bool {
+        let val = (self.0 >> 10usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If set, the result appears bit-reversed when read. This does not affect the way the checksum is calculated; the result is transformed on-the-fly between the result register and the bus."]
+    #[inline(always)]
+    pub fn set_out_rev(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize);
+    }
+    #[doc = "If set, the result appears inverted (bitwise complement) when read. This does not affect the way the checksum is calculated; the result is transformed on-the-fly between the result register and the bus."]
+    #[inline(always)]
+    pub const fn out_inv(&self) -> bool {
+        let val = (self.0 >> 11usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If set, the result appears inverted (bitwise complement) when read. This does not affect the way the checksum is calculated; the result is transformed on-the-fly between the result register and the bus."]
+    #[inline(always)]
+    pub fn set_out_inv(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
+    }
+}
+impl Default for SniffCtrl {
+    #[inline(always)]
+    fn default() -> SniffCtrl {
+        SniffCtrl(0)
+    }
+}
+#[doc = "Pacing (X/Y) fractional timer The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Timer(pub u32);
+impl Timer {
+    #[doc = "Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer."]
+    #[inline(always)]
+    pub const fn y(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0xffff;
+        val as u16
+    }
+    #[doc = "Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer."]
+    #[inline(always)]
+    pub fn set_y(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+    }
+    #[doc = "Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer."]
+    #[inline(always)]
+    pub const fn x(&self) -> u16 {
+        let val = (self.0 >> 16usize) & 0xffff;
+        val as u16
+    }
+    #[doc = "Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer."]
+    #[inline(always)]
+    pub fn set_x(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 16usize)) | (((val as u32) & 0xffff) << 16usize);
+    }
+}
+impl Default for Timer {
+    #[inline(always)]
+    fn default() -> Timer {
+        Timer(0)
+    }
+}
diff --git a/src/rp2350/dma/vals.rs b/src/rp2350/dma/vals.rs
new file mode 100644
index 00000000..f655aa23
--- /dev/null
+++ b/src/rp2350/dma/vals.rs
@@ -0,0 +1,900 @@
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Calc {
+    #[doc = "Calculate a CRC-32 (IEEE802.3 polynomial)"]
+    CRC32 = 0,
+    #[doc = "Calculate a CRC-32 (IEEE802.3 polynomial) with bit reversed data"]
+    CRC32R = 0x01,
+    #[doc = "Calculate a CRC-16-CCITT"]
+    CRC16 = 0x02,
+    #[doc = "Calculate a CRC-16-CCITT with bit reversed data"]
+    CRC16R = 0x03,
+    _RESERVED_4 = 0x04,
+    _RESERVED_5 = 0x05,
+    _RESERVED_6 = 0x06,
+    _RESERVED_7 = 0x07,
+    _RESERVED_8 = 0x08,
+    _RESERVED_9 = 0x09,
+    _RESERVED_a = 0x0a,
+    _RESERVED_b = 0x0b,
+    _RESERVED_c = 0x0c,
+    _RESERVED_d = 0x0d,
+    #[doc = "XOR reduction over all data. == 1 if the total 1 population count is odd."]
+    EVEN = 0x0e,
+    #[doc = "Calculate a simple 32-bit checksum (addition with a 32 bit accumulator)"]
+    SUM = 0x0f,
+}
+impl Calc {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Calc {
+        unsafe { core::mem::transmute(val & 0x0f) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Calc {
+    #[inline(always)]
+    fn from(val: u8) -> Calc {
+        Calc::from_bits(val)
+    }
+}
+impl From<Calc> for u8 {
+    #[inline(always)]
+    fn from(val: Calc) -> u8 {
+        Calc::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Ch0transCountMode {
+    NORMAL = 0,
+    TRIGGER_SELF = 0x01,
+    _RESERVED_2 = 0x02,
+    _RESERVED_3 = 0x03,
+    _RESERVED_4 = 0x04,
+    _RESERVED_5 = 0x05,
+    _RESERVED_6 = 0x06,
+    _RESERVED_7 = 0x07,
+    _RESERVED_8 = 0x08,
+    _RESERVED_9 = 0x09,
+    _RESERVED_a = 0x0a,
+    _RESERVED_b = 0x0b,
+    _RESERVED_c = 0x0c,
+    _RESERVED_d = 0x0d,
+    _RESERVED_e = 0x0e,
+    ENDLESS = 0x0f,
+}
+impl Ch0transCountMode {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Ch0transCountMode {
+        unsafe { core::mem::transmute(val & 0x0f) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Ch0transCountMode {
+    #[inline(always)]
+    fn from(val: u8) -> Ch0transCountMode {
+        Ch0transCountMode::from_bits(val)
+    }
+}
+impl From<Ch0transCountMode> for u8 {
+    #[inline(always)]
+    fn from(val: Ch0transCountMode) -> u8 {
+        Ch0transCountMode::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Ch10transCountMode {
+    NORMAL = 0,
+    TRIGGER_SELF = 0x01,
+    _RESERVED_2 = 0x02,
+    _RESERVED_3 = 0x03,
+    _RESERVED_4 = 0x04,
+    _RESERVED_5 = 0x05,
+    _RESERVED_6 = 0x06,
+    _RESERVED_7 = 0x07,
+    _RESERVED_8 = 0x08,
+    _RESERVED_9 = 0x09,
+    _RESERVED_a = 0x0a,
+    _RESERVED_b = 0x0b,
+    _RESERVED_c = 0x0c,
+    _RESERVED_d = 0x0d,
+    _RESERVED_e = 0x0e,
+    ENDLESS = 0x0f,
+}
+impl Ch10transCountMode {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Ch10transCountMode {
+        unsafe { core::mem::transmute(val & 0x0f) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Ch10transCountMode {
+    #[inline(always)]
+    fn from(val: u8) -> Ch10transCountMode {
+        Ch10transCountMode::from_bits(val)
+    }
+}
+impl From<Ch10transCountMode> for u8 {
+    #[inline(always)]
+    fn from(val: Ch10transCountMode) -> u8 {
+        Ch10transCountMode::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Ch11transCountMode {
+    NORMAL = 0,
+    TRIGGER_SELF = 0x01,
+    _RESERVED_2 = 0x02,
+    _RESERVED_3 = 0x03,
+    _RESERVED_4 = 0x04,
+    _RESERVED_5 = 0x05,
+    _RESERVED_6 = 0x06,
+    _RESERVED_7 = 0x07,
+    _RESERVED_8 = 0x08,
+    _RESERVED_9 = 0x09,
+    _RESERVED_a = 0x0a,
+    _RESERVED_b = 0x0b,
+    _RESERVED_c = 0x0c,
+    _RESERVED_d = 0x0d,
+    _RESERVED_e = 0x0e,
+    ENDLESS = 0x0f,
+}
+impl Ch11transCountMode {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Ch11transCountMode {
+        unsafe { core::mem::transmute(val & 0x0f) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Ch11transCountMode {
+    #[inline(always)]
+    fn from(val: u8) -> Ch11transCountMode {
+        Ch11transCountMode::from_bits(val)
+    }
+}
+impl From<Ch11transCountMode> for u8 {
+    #[inline(always)]
+    fn from(val: Ch11transCountMode) -> u8 {
+        Ch11transCountMode::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Ch12transCountMode {
+    NORMAL = 0,
+    TRIGGER_SELF = 0x01,
+    _RESERVED_2 = 0x02,
+    _RESERVED_3 = 0x03,
+    _RESERVED_4 = 0x04,
+    _RESERVED_5 = 0x05,
+    _RESERVED_6 = 0x06,
+    _RESERVED_7 = 0x07,
+    _RESERVED_8 = 0x08,
+    _RESERVED_9 = 0x09,
+    _RESERVED_a = 0x0a,
+    _RESERVED_b = 0x0b,
+    _RESERVED_c = 0x0c,
+    _RESERVED_d = 0x0d,
+    _RESERVED_e = 0x0e,
+    ENDLESS = 0x0f,
+}
+impl Ch12transCountMode {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Ch12transCountMode {
+        unsafe { core::mem::transmute(val & 0x0f) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Ch12transCountMode {
+    #[inline(always)]
+    fn from(val: u8) -> Ch12transCountMode {
+        Ch12transCountMode::from_bits(val)
+    }
+}
+impl From<Ch12transCountMode> for u8 {
+    #[inline(always)]
+    fn from(val: Ch12transCountMode) -> u8 {
+        Ch12transCountMode::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Ch13transCountMode {
+    NORMAL = 0,
+    TRIGGER_SELF = 0x01,
+    _RESERVED_2 = 0x02,
+    _RESERVED_3 = 0x03,
+    _RESERVED_4 = 0x04,
+    _RESERVED_5 = 0x05,
+    _RESERVED_6 = 0x06,
+    _RESERVED_7 = 0x07,
+    _RESERVED_8 = 0x08,
+    _RESERVED_9 = 0x09,
+    _RESERVED_a = 0x0a,
+    _RESERVED_b = 0x0b,
+    _RESERVED_c = 0x0c,
+    _RESERVED_d = 0x0d,
+    _RESERVED_e = 0x0e,
+    ENDLESS = 0x0f,
+}
+impl Ch13transCountMode {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Ch13transCountMode {
+        unsafe { core::mem::transmute(val & 0x0f) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Ch13transCountMode {
+    #[inline(always)]
+    fn from(val: u8) -> Ch13transCountMode {
+        Ch13transCountMode::from_bits(val)
+    }
+}
+impl From<Ch13transCountMode> for u8 {
+    #[inline(always)]
+    fn from(val: Ch13transCountMode) -> u8 {
+        Ch13transCountMode::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Ch14transCountMode {
+    NORMAL = 0,
+    TRIGGER_SELF = 0x01,
+    _RESERVED_2 = 0x02,
+    _RESERVED_3 = 0x03,
+    _RESERVED_4 = 0x04,
+    _RESERVED_5 = 0x05,
+    _RESERVED_6 = 0x06,
+    _RESERVED_7 = 0x07,
+    _RESERVED_8 = 0x08,
+    _RESERVED_9 = 0x09,
+    _RESERVED_a = 0x0a,
+    _RESERVED_b = 0x0b,
+    _RESERVED_c = 0x0c,
+    _RESERVED_d = 0x0d,
+    _RESERVED_e = 0x0e,
+    ENDLESS = 0x0f,
+}
+impl Ch14transCountMode {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Ch14transCountMode {
+        unsafe { core::mem::transmute(val & 0x0f) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Ch14transCountMode {
+    #[inline(always)]
+    fn from(val: u8) -> Ch14transCountMode {
+        Ch14transCountMode::from_bits(val)
+    }
+}
+impl From<Ch14transCountMode> for u8 {
+    #[inline(always)]
+    fn from(val: Ch14transCountMode) -> u8 {
+        Ch14transCountMode::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Ch15transCountMode {
+    NORMAL = 0,
+    TRIGGER_SELF = 0x01,
+    _RESERVED_2 = 0x02,
+    _RESERVED_3 = 0x03,
+    _RESERVED_4 = 0x04,
+    _RESERVED_5 = 0x05,
+    _RESERVED_6 = 0x06,
+    _RESERVED_7 = 0x07,
+    _RESERVED_8 = 0x08,
+    _RESERVED_9 = 0x09,
+    _RESERVED_a = 0x0a,
+    _RESERVED_b = 0x0b,
+    _RESERVED_c = 0x0c,
+    _RESERVED_d = 0x0d,
+    _RESERVED_e = 0x0e,
+    ENDLESS = 0x0f,
+}
+impl Ch15transCountMode {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Ch15transCountMode {
+        unsafe { core::mem::transmute(val & 0x0f) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Ch15transCountMode {
+    #[inline(always)]
+    fn from(val: u8) -> Ch15transCountMode {
+        Ch15transCountMode::from_bits(val)
+    }
+}
+impl From<Ch15transCountMode> for u8 {
+    #[inline(always)]
+    fn from(val: Ch15transCountMode) -> u8 {
+        Ch15transCountMode::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Ch1transCountMode {
+    NORMAL = 0,
+    TRIGGER_SELF = 0x01,
+    _RESERVED_2 = 0x02,
+    _RESERVED_3 = 0x03,
+    _RESERVED_4 = 0x04,
+    _RESERVED_5 = 0x05,
+    _RESERVED_6 = 0x06,
+    _RESERVED_7 = 0x07,
+    _RESERVED_8 = 0x08,
+    _RESERVED_9 = 0x09,
+    _RESERVED_a = 0x0a,
+    _RESERVED_b = 0x0b,
+    _RESERVED_c = 0x0c,
+    _RESERVED_d = 0x0d,
+    _RESERVED_e = 0x0e,
+    ENDLESS = 0x0f,
+}
+impl Ch1transCountMode {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Ch1transCountMode {
+        unsafe { core::mem::transmute(val & 0x0f) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Ch1transCountMode {
+    #[inline(always)]
+    fn from(val: u8) -> Ch1transCountMode {
+        Ch1transCountMode::from_bits(val)
+    }
+}
+impl From<Ch1transCountMode> for u8 {
+    #[inline(always)]
+    fn from(val: Ch1transCountMode) -> u8 {
+        Ch1transCountMode::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Ch2transCountMode {
+    NORMAL = 0,
+    TRIGGER_SELF = 0x01,
+    _RESERVED_2 = 0x02,
+    _RESERVED_3 = 0x03,
+    _RESERVED_4 = 0x04,
+    _RESERVED_5 = 0x05,
+    _RESERVED_6 = 0x06,
+    _RESERVED_7 = 0x07,
+    _RESERVED_8 = 0x08,
+    _RESERVED_9 = 0x09,
+    _RESERVED_a = 0x0a,
+    _RESERVED_b = 0x0b,
+    _RESERVED_c = 0x0c,
+    _RESERVED_d = 0x0d,
+    _RESERVED_e = 0x0e,
+    ENDLESS = 0x0f,
+}
+impl Ch2transCountMode {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Ch2transCountMode {
+        unsafe { core::mem::transmute(val & 0x0f) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Ch2transCountMode {
+    #[inline(always)]
+    fn from(val: u8) -> Ch2transCountMode {
+        Ch2transCountMode::from_bits(val)
+    }
+}
+impl From<Ch2transCountMode> for u8 {
+    #[inline(always)]
+    fn from(val: Ch2transCountMode) -> u8 {
+        Ch2transCountMode::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Ch3transCountMode {
+    NORMAL = 0,
+    TRIGGER_SELF = 0x01,
+    _RESERVED_2 = 0x02,
+    _RESERVED_3 = 0x03,
+    _RESERVED_4 = 0x04,
+    _RESERVED_5 = 0x05,
+    _RESERVED_6 = 0x06,
+    _RESERVED_7 = 0x07,
+    _RESERVED_8 = 0x08,
+    _RESERVED_9 = 0x09,
+    _RESERVED_a = 0x0a,
+    _RESERVED_b = 0x0b,
+    _RESERVED_c = 0x0c,
+    _RESERVED_d = 0x0d,
+    _RESERVED_e = 0x0e,
+    ENDLESS = 0x0f,
+}
+impl Ch3transCountMode {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Ch3transCountMode {
+        unsafe { core::mem::transmute(val & 0x0f) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Ch3transCountMode {
+    #[inline(always)]
+    fn from(val: u8) -> Ch3transCountMode {
+        Ch3transCountMode::from_bits(val)
+    }
+}
+impl From<Ch3transCountMode> for u8 {
+    #[inline(always)]
+    fn from(val: Ch3transCountMode) -> u8 {
+        Ch3transCountMode::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Ch4transCountMode {
+    NORMAL = 0,
+    TRIGGER_SELF = 0x01,
+    _RESERVED_2 = 0x02,
+    _RESERVED_3 = 0x03,
+    _RESERVED_4 = 0x04,
+    _RESERVED_5 = 0x05,
+    _RESERVED_6 = 0x06,
+    _RESERVED_7 = 0x07,
+    _RESERVED_8 = 0x08,
+    _RESERVED_9 = 0x09,
+    _RESERVED_a = 0x0a,
+    _RESERVED_b = 0x0b,
+    _RESERVED_c = 0x0c,
+    _RESERVED_d = 0x0d,
+    _RESERVED_e = 0x0e,
+    ENDLESS = 0x0f,
+}
+impl Ch4transCountMode {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Ch4transCountMode {
+        unsafe { core::mem::transmute(val & 0x0f) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Ch4transCountMode {
+    #[inline(always)]
+    fn from(val: u8) -> Ch4transCountMode {
+        Ch4transCountMode::from_bits(val)
+    }
+}
+impl From<Ch4transCountMode> for u8 {
+    #[inline(always)]
+    fn from(val: Ch4transCountMode) -> u8 {
+        Ch4transCountMode::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Ch5transCountMode {
+    NORMAL = 0,
+    TRIGGER_SELF = 0x01,
+    _RESERVED_2 = 0x02,
+    _RESERVED_3 = 0x03,
+    _RESERVED_4 = 0x04,
+    _RESERVED_5 = 0x05,
+    _RESERVED_6 = 0x06,
+    _RESERVED_7 = 0x07,
+    _RESERVED_8 = 0x08,
+    _RESERVED_9 = 0x09,
+    _RESERVED_a = 0x0a,
+    _RESERVED_b = 0x0b,
+    _RESERVED_c = 0x0c,
+    _RESERVED_d = 0x0d,
+    _RESERVED_e = 0x0e,
+    ENDLESS = 0x0f,
+}
+impl Ch5transCountMode {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Ch5transCountMode {
+        unsafe { core::mem::transmute(val & 0x0f) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Ch5transCountMode {
+    #[inline(always)]
+    fn from(val: u8) -> Ch5transCountMode {
+        Ch5transCountMode::from_bits(val)
+    }
+}
+impl From<Ch5transCountMode> for u8 {
+    #[inline(always)]
+    fn from(val: Ch5transCountMode) -> u8 {
+        Ch5transCountMode::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Ch6transCountMode {
+    NORMAL = 0,
+    TRIGGER_SELF = 0x01,
+    _RESERVED_2 = 0x02,
+    _RESERVED_3 = 0x03,
+    _RESERVED_4 = 0x04,
+    _RESERVED_5 = 0x05,
+    _RESERVED_6 = 0x06,
+    _RESERVED_7 = 0x07,
+    _RESERVED_8 = 0x08,
+    _RESERVED_9 = 0x09,
+    _RESERVED_a = 0x0a,
+    _RESERVED_b = 0x0b,
+    _RESERVED_c = 0x0c,
+    _RESERVED_d = 0x0d,
+    _RESERVED_e = 0x0e,
+    ENDLESS = 0x0f,
+}
+impl Ch6transCountMode {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Ch6transCountMode {
+        unsafe { core::mem::transmute(val & 0x0f) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Ch6transCountMode {
+    #[inline(always)]
+    fn from(val: u8) -> Ch6transCountMode {
+        Ch6transCountMode::from_bits(val)
+    }
+}
+impl From<Ch6transCountMode> for u8 {
+    #[inline(always)]
+    fn from(val: Ch6transCountMode) -> u8 {
+        Ch6transCountMode::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Ch7transCountMode {
+    NORMAL = 0,
+    TRIGGER_SELF = 0x01,
+    _RESERVED_2 = 0x02,
+    _RESERVED_3 = 0x03,
+    _RESERVED_4 = 0x04,
+    _RESERVED_5 = 0x05,
+    _RESERVED_6 = 0x06,
+    _RESERVED_7 = 0x07,
+    _RESERVED_8 = 0x08,
+    _RESERVED_9 = 0x09,
+    _RESERVED_a = 0x0a,
+    _RESERVED_b = 0x0b,
+    _RESERVED_c = 0x0c,
+    _RESERVED_d = 0x0d,
+    _RESERVED_e = 0x0e,
+    ENDLESS = 0x0f,
+}
+impl Ch7transCountMode {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Ch7transCountMode {
+        unsafe { core::mem::transmute(val & 0x0f) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Ch7transCountMode {
+    #[inline(always)]
+    fn from(val: u8) -> Ch7transCountMode {
+        Ch7transCountMode::from_bits(val)
+    }
+}
+impl From<Ch7transCountMode> for u8 {
+    #[inline(always)]
+    fn from(val: Ch7transCountMode) -> u8 {
+        Ch7transCountMode::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Ch8transCountMode {
+    NORMAL = 0,
+    TRIGGER_SELF = 0x01,
+    _RESERVED_2 = 0x02,
+    _RESERVED_3 = 0x03,
+    _RESERVED_4 = 0x04,
+    _RESERVED_5 = 0x05,
+    _RESERVED_6 = 0x06,
+    _RESERVED_7 = 0x07,
+    _RESERVED_8 = 0x08,
+    _RESERVED_9 = 0x09,
+    _RESERVED_a = 0x0a,
+    _RESERVED_b = 0x0b,
+    _RESERVED_c = 0x0c,
+    _RESERVED_d = 0x0d,
+    _RESERVED_e = 0x0e,
+    ENDLESS = 0x0f,
+}
+impl Ch8transCountMode {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Ch8transCountMode {
+        unsafe { core::mem::transmute(val & 0x0f) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Ch8transCountMode {
+    #[inline(always)]
+    fn from(val: u8) -> Ch8transCountMode {
+        Ch8transCountMode::from_bits(val)
+    }
+}
+impl From<Ch8transCountMode> for u8 {
+    #[inline(always)]
+    fn from(val: Ch8transCountMode) -> u8 {
+        Ch8transCountMode::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Ch9transCountMode {
+    NORMAL = 0,
+    TRIGGER_SELF = 0x01,
+    _RESERVED_2 = 0x02,
+    _RESERVED_3 = 0x03,
+    _RESERVED_4 = 0x04,
+    _RESERVED_5 = 0x05,
+    _RESERVED_6 = 0x06,
+    _RESERVED_7 = 0x07,
+    _RESERVED_8 = 0x08,
+    _RESERVED_9 = 0x09,
+    _RESERVED_a = 0x0a,
+    _RESERVED_b = 0x0b,
+    _RESERVED_c = 0x0c,
+    _RESERVED_d = 0x0d,
+    _RESERVED_e = 0x0e,
+    ENDLESS = 0x0f,
+}
+impl Ch9transCountMode {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Ch9transCountMode {
+        unsafe { core::mem::transmute(val & 0x0f) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Ch9transCountMode {
+    #[inline(always)]
+    fn from(val: u8) -> Ch9transCountMode {
+        Ch9transCountMode::from_bits(val)
+    }
+}
+impl From<Ch9transCountMode> for u8 {
+    #[inline(always)]
+    fn from(val: Ch9transCountMode) -> u8 {
+        Ch9transCountMode::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum DataSize {
+    SIZE_BYTE = 0,
+    SIZE_HALFWORD = 0x01,
+    SIZE_WORD = 0x02,
+    _RESERVED_3 = 0x03,
+}
+impl DataSize {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> DataSize {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for DataSize {
+    #[inline(always)]
+    fn from(val: u8) -> DataSize {
+        DataSize::from_bits(val)
+    }
+}
+impl From<DataSize> for u8 {
+    #[inline(always)]
+    fn from(val: DataSize) -> u8 {
+        DataSize::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum TreqSel {
+    #[doc = "Select PIO0's TX FIFO 0 as TREQ"]
+    PIO0_TX0 = 0,
+    #[doc = "Select PIO0's TX FIFO 1 as TREQ"]
+    PIO0_TX1 = 0x01,
+    #[doc = "Select PIO0's TX FIFO 2 as TREQ"]
+    PIO0_TX2 = 0x02,
+    #[doc = "Select PIO0's TX FIFO 3 as TREQ"]
+    PIO0_TX3 = 0x03,
+    #[doc = "Select PIO0's RX FIFO 0 as TREQ"]
+    PIO0_RX0 = 0x04,
+    #[doc = "Select PIO0's RX FIFO 1 as TREQ"]
+    PIO0_RX1 = 0x05,
+    #[doc = "Select PIO0's RX FIFO 2 as TREQ"]
+    PIO0_RX2 = 0x06,
+    #[doc = "Select PIO0's RX FIFO 3 as TREQ"]
+    PIO0_RX3 = 0x07,
+    #[doc = "Select PIO1's TX FIFO 0 as TREQ"]
+    PIO1_TX0 = 0x08,
+    #[doc = "Select PIO1's TX FIFO 1 as TREQ"]
+    PIO1_TX1 = 0x09,
+    #[doc = "Select PIO1's TX FIFO 2 as TREQ"]
+    PIO1_TX2 = 0x0a,
+    #[doc = "Select PIO1's TX FIFO 3 as TREQ"]
+    PIO1_TX3 = 0x0b,
+    #[doc = "Select PIO1's RX FIFO 0 as TREQ"]
+    PIO1_RX0 = 0x0c,
+    #[doc = "Select PIO1's RX FIFO 1 as TREQ"]
+    PIO1_RX1 = 0x0d,
+    #[doc = "Select PIO1's RX FIFO 2 as TREQ"]
+    PIO1_RX2 = 0x0e,
+    #[doc = "Select PIO1's RX FIFO 3 as TREQ"]
+    PIO1_RX3 = 0x0f,
+    #[doc = "Select PIO2's TX FIFO 0 as TREQ"]
+    PIO2_TX0 = 0x10,
+    #[doc = "Select PIO2's TX FIFO 1 as TREQ"]
+    PIO2_TX1 = 0x11,
+    #[doc = "Select PIO2's TX FIFO 2 as TREQ"]
+    PIO2_TX2 = 0x12,
+    #[doc = "Select PIO2's TX FIFO 3 as TREQ"]
+    PIO2_TX3 = 0x13,
+    #[doc = "Select PIO2's RX FIFO 0 as TREQ"]
+    PIO2_RX0 = 0x14,
+    #[doc = "Select PIO2's RX FIFO 1 as TREQ"]
+    PIO2_RX1 = 0x15,
+    #[doc = "Select PIO2's RX FIFO 2 as TREQ"]
+    PIO2_RX2 = 0x16,
+    #[doc = "Select PIO2's RX FIFO 3 as TREQ"]
+    PIO2_RX3 = 0x17,
+    #[doc = "Select SPI0's TX FIFO as TREQ"]
+    SPI0_TX = 0x18,
+    #[doc = "Select SPI0's RX FIFO as TREQ"]
+    SPI0_RX = 0x19,
+    #[doc = "Select SPI1's TX FIFO as TREQ"]
+    SPI1_TX = 0x1a,
+    #[doc = "Select SPI1's RX FIFO as TREQ"]
+    SPI1_RX = 0x1b,
+    #[doc = "Select UART0's TX FIFO as TREQ"]
+    UART0_TX = 0x1c,
+    #[doc = "Select UART0's RX FIFO as TREQ"]
+    UART0_RX = 0x1d,
+    #[doc = "Select UART1's TX FIFO as TREQ"]
+    UART1_TX = 0x1e,
+    #[doc = "Select UART1's RX FIFO as TREQ"]
+    UART1_RX = 0x1f,
+    #[doc = "Select PWM Counter 0's Wrap Value as TREQ"]
+    PWM_WRAP0 = 0x20,
+    #[doc = "Select PWM Counter 1's Wrap Value as TREQ"]
+    PWM_WRAP1 = 0x21,
+    #[doc = "Select PWM Counter 2's Wrap Value as TREQ"]
+    PWM_WRAP2 = 0x22,
+    #[doc = "Select PWM Counter 3's Wrap Value as TREQ"]
+    PWM_WRAP3 = 0x23,
+    #[doc = "Select PWM Counter 4's Wrap Value as TREQ"]
+    PWM_WRAP4 = 0x24,
+    #[doc = "Select PWM Counter 5's Wrap Value as TREQ"]
+    PWM_WRAP5 = 0x25,
+    #[doc = "Select PWM Counter 6's Wrap Value as TREQ"]
+    PWM_WRAP6 = 0x26,
+    #[doc = "Select PWM Counter 7's Wrap Value as TREQ"]
+    PWM_WRAP7 = 0x27,
+    #[doc = "Select PWM Counter 8's Wrap Value as TREQ"]
+    PWM_WRAP8 = 0x28,
+    #[doc = "Select PWM Counter 9's Wrap Value as TREQ"]
+    PWM_WRAP9 = 0x29,
+    #[doc = "Select PWM Counter 0's Wrap Value as TREQ"]
+    PWM_WRAP10 = 0x2a,
+    #[doc = "Select PWM Counter 1's Wrap Value as TREQ"]
+    PWM_WRAP11 = 0x2b,
+    #[doc = "Select I2C0's TX FIFO as TREQ"]
+    I2C0_TX = 0x2c,
+    #[doc = "Select I2C0's RX FIFO as TREQ"]
+    I2C0_RX = 0x2d,
+    #[doc = "Select I2C1's TX FIFO as TREQ"]
+    I2C1_TX = 0x2e,
+    #[doc = "Select I2C1's RX FIFO as TREQ"]
+    I2C1_RX = 0x2f,
+    #[doc = "Select the ADC as TREQ"]
+    ADC = 0x30,
+    #[doc = "Select the XIP Streaming FIFO as TREQ"]
+    XIP_STREAM = 0x31,
+    #[doc = "Select XIP_QMITX as TREQ"]
+    XIP_QMITX = 0x32,
+    #[doc = "Select XIP_QMIRX as TREQ"]
+    XIP_QMIRX = 0x33,
+    #[doc = "Select HSTX as TREQ"]
+    HSTX = 0x34,
+    #[doc = "Select CORESIGHT as TREQ"]
+    CORESIGHT = 0x35,
+    #[doc = "Select SHA256 as TREQ"]
+    SHA256 = 0x36,
+    _RESERVED_37 = 0x37,
+    _RESERVED_38 = 0x38,
+    _RESERVED_39 = 0x39,
+    _RESERVED_3a = 0x3a,
+    #[doc = "Select Timer 0 as TREQ"]
+    TIMER0 = 0x3b,
+    #[doc = "Select Timer 1 as TREQ"]
+    TIMER1 = 0x3c,
+    #[doc = "Select Timer 2 as TREQ (Optional)"]
+    TIMER2 = 0x3d,
+    #[doc = "Select Timer 3 as TREQ (Optional)"]
+    TIMER3 = 0x3e,
+    #[doc = "Permanent request, for unpaced transfers."]
+    PERMANENT = 0x3f,
+}
+impl TreqSel {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> TreqSel {
+        unsafe { core::mem::transmute(val & 0x3f) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for TreqSel {
+    #[inline(always)]
+    fn from(val: u8) -> TreqSel {
+        TreqSel::from_bits(val)
+    }
+}
+impl From<TreqSel> for u8 {
+    #[inline(always)]
+    fn from(val: TreqSel) -> u8 {
+        TreqSel::to_bits(val)
+    }
+}
diff --git a/src/rp2350/eppb.rs b/src/rp2350/eppb.rs
new file mode 100644
index 00000000..cfca571c
--- /dev/null
+++ b/src/rp2350/eppb.rs
@@ -0,0 +1,33 @@
+#[doc = "Cortex-M33 EPPB vendor register block for RP2350"]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Eppb {
+    ptr: *mut u8,
+}
+unsafe impl Send for Eppb {}
+unsafe impl Sync for Eppb {}
+impl Eppb {
+    #[inline(always)]
+    pub const unsafe fn from_ptr(ptr: *mut ()) -> Self {
+        Self { ptr: ptr as _ }
+    }
+    #[inline(always)]
+    pub const fn as_ptr(&self) -> *mut () {
+        self.ptr as _
+    }
+    #[doc = "NMI mask for IRQs 0 through 31. This register is core-local, and is reset by a processor warm reset."]
+    #[inline(always)]
+    pub const fn nmi_mask0(self) -> crate::common::Reg<u32, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(0usize) as _) }
+    }
+    #[doc = "NMI mask for IRQs 0 though 51. This register is core-local, and is reset by a processor warm reset."]
+    #[inline(always)]
+    pub const fn nmi_mask1(self) -> crate::common::Reg<regs::NmiMask1, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(4usize) as _) }
+    }
+    #[doc = "Nonstandard sleep control register"]
+    #[inline(always)]
+    pub const fn sleepctrl(self) -> crate::common::Reg<regs::Sleepctrl, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(8usize) as _) }
+    }
+}
+pub mod regs;
diff --git a/src/rp2350/eppb/regs.rs b/src/rp2350/eppb/regs.rs
new file mode 100644
index 00000000..de383233
--- /dev/null
+++ b/src/rp2350/eppb/regs.rs
@@ -0,0 +1,66 @@
+#[doc = "NMI mask for IRQs 0 though 51. This register is core-local, and is reset by a processor warm reset."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct NmiMask1(pub u32);
+impl NmiMask1 {
+    #[inline(always)]
+    pub const fn nmi_mask1(&self) -> u32 {
+        let val = (self.0 >> 0usize) & 0x000f_ffff;
+        val as u32
+    }
+    #[inline(always)]
+    pub fn set_nmi_mask1(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x000f_ffff << 0usize)) | (((val as u32) & 0x000f_ffff) << 0usize);
+    }
+}
+impl Default for NmiMask1 {
+    #[inline(always)]
+    fn default() -> NmiMask1 {
+        NmiMask1(0)
+    }
+}
+#[doc = "Nonstandard sleep control register"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Sleepctrl(pub u32);
+impl Sleepctrl {
+    #[doc = "By default, any processor sleep will deassert the system-level clock request. Reenabling the clocks incurs 5 cycles of additional latency on wakeup. Setting LIGHT_SLEEP to 1 keeps the clock request asserted during a normal sleep (Arm SCR.SLEEPDEEP = 0), for faster wakeup. Processor deep sleep (Arm SCR.SLEEPDEEP = 1) is not affected, and will always deassert the system-level clock request."]
+    #[inline(always)]
+    pub const fn light_sleep(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "By default, any processor sleep will deassert the system-level clock request. Reenabling the clocks incurs 5 cycles of additional latency on wakeup. Setting LIGHT_SLEEP to 1 keeps the clock request asserted during a normal sleep (Arm SCR.SLEEPDEEP = 0), for faster wakeup. Processor deep sleep (Arm SCR.SLEEPDEEP = 1) is not affected, and will always deassert the system-level clock request."]
+    #[inline(always)]
+    pub fn set_light_sleep(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[doc = "Request that the next processor deep sleep is a WIC sleep. After setting this bit, before sleeping, poll WICENACK to ensure the processor interrupt controller has acknowledged the change."]
+    #[inline(always)]
+    pub const fn wicenreq(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Request that the next processor deep sleep is a WIC sleep. After setting this bit, before sleeping, poll WICENACK to ensure the processor interrupt controller has acknowledged the change."]
+    #[inline(always)]
+    pub fn set_wicenreq(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+    #[doc = "Status signal from the processor's interrupt controller. Changes to WICENREQ are eventually reflected in WICENACK."]
+    #[inline(always)]
+    pub const fn wicenack(&self) -> bool {
+        let val = (self.0 >> 2usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Status signal from the processor's interrupt controller. Changes to WICENREQ are eventually reflected in WICENACK."]
+    #[inline(always)]
+    pub fn set_wicenack(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+    }
+}
+impl Default for Sleepctrl {
+    #[inline(always)]
+    fn default() -> Sleepctrl {
+        Sleepctrl(0)
+    }
+}
diff --git a/src/rp2350/glitch_detector.rs b/src/rp2350/glitch_detector.rs
new file mode 100644
index 00000000..7508e406
--- /dev/null
+++ b/src/rp2350/glitch_detector.rs
@@ -0,0 +1,47 @@
+#[doc = "Glitch detector controls"]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct GlitchDetector {
+    ptr: *mut u8,
+}
+unsafe impl Send for GlitchDetector {}
+unsafe impl Sync for GlitchDetector {}
+impl GlitchDetector {
+    #[inline(always)]
+    pub const unsafe fn from_ptr(ptr: *mut ()) -> Self {
+        Self { ptr: ptr as _ }
+    }
+    #[inline(always)]
+    pub const fn as_ptr(&self) -> *mut () {
+        self.ptr as _
+    }
+    #[doc = "Forcibly arm the glitch detectors, if they are not already armed by OTP. When armed, any individual detector trigger will cause a restart of the switched core power domain's power-on reset state machine. Glitch detector triggers are recorded accumulatively in TRIG_STATUS. If the system is reset by a glitch detector trigger, this is recorded in POWMAN_CHIP_RESET. This register is Secure read/write only."]
+    #[inline(always)]
+    pub const fn arm(self) -> crate::common::Reg<regs::Arm, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(0usize) as _) }
+    }
+    #[inline(always)]
+    pub const fn disarm(self) -> crate::common::Reg<regs::Disarm, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(4usize) as _) }
+    }
+    #[doc = "Adjust the sensitivity of glitch detectors to values other than their OTP-provided defaults. This register is Secure read/write only."]
+    #[inline(always)]
+    pub const fn sensitivity(self) -> crate::common::Reg<regs::Sensitivity, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(8usize) as _) }
+    }
+    #[inline(always)]
+    pub const fn lock(self) -> crate::common::Reg<regs::Lock, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(12usize) as _) }
+    }
+    #[doc = "Set when a detector output triggers. Write-1-clear. (May immediately return high if the detector remains in a failed state. Detectors can only be cleared by a full reset of the switched core power domain.) This register is Secure read/write only."]
+    #[inline(always)]
+    pub const fn trig_status(self) -> crate::common::Reg<regs::TrigStatus, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(16usize) as _) }
+    }
+    #[doc = "Simulate the firing of one or more detectors. Writing ones to this register will set the matching bits in STATUS_TRIG. If the glitch detectors are currently armed, writing ones will also immediately reset the switched core power domain, and set the reset reason latches in POWMAN_CHIP_RESET to indicate a glitch detector resets. This register is Secure read/write only."]
+    #[inline(always)]
+    pub const fn trig_force(self) -> crate::common::Reg<regs::TrigForce, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(20usize) as _) }
+    }
+}
+pub mod regs;
+pub mod vals;
diff --git a/src/rp2350/glitch_detector/regs.rs b/src/rp2350/glitch_detector/regs.rs
new file mode 100644
index 00000000..3b1abedc
--- /dev/null
+++ b/src/rp2350/glitch_detector/regs.rs
@@ -0,0 +1,243 @@
+#[doc = "Forcibly arm the glitch detectors, if they are not already armed by OTP. When armed, any individual detector trigger will cause a restart of the switched core power domain's power-on reset state machine. Glitch detector triggers are recorded accumulatively in TRIG_STATUS. If the system is reset by a glitch detector trigger, this is recorded in POWMAN_CHIP_RESET. This register is Secure read/write only."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Arm(pub u32);
+impl Arm {
+    #[inline(always)]
+    pub const fn arm(&self) -> super::vals::Arm {
+        let val = (self.0 >> 0usize) & 0xffff;
+        super::vals::Arm::from_bits(val as u16)
+    }
+    #[inline(always)]
+    pub fn set_arm(&mut self, val: super::vals::Arm) {
+        self.0 = (self.0 & !(0xffff << 0usize)) | (((val.to_bits() as u32) & 0xffff) << 0usize);
+    }
+}
+impl Default for Arm {
+    #[inline(always)]
+    fn default() -> Arm {
+        Arm(0)
+    }
+}
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Disarm(pub u32);
+impl Disarm {
+    #[doc = "Forcibly disarm the glitch detectors, if they are armed by OTP. Ignored if ARM is YES. This register is Secure read/write only."]
+    #[inline(always)]
+    pub const fn disarm(&self) -> super::vals::Disarm {
+        let val = (self.0 >> 0usize) & 0xffff;
+        super::vals::Disarm::from_bits(val as u16)
+    }
+    #[doc = "Forcibly disarm the glitch detectors, if they are armed by OTP. Ignored if ARM is YES. This register is Secure read/write only."]
+    #[inline(always)]
+    pub fn set_disarm(&mut self, val: super::vals::Disarm) {
+        self.0 = (self.0 & !(0xffff << 0usize)) | (((val.to_bits() as u32) & 0xffff) << 0usize);
+    }
+}
+impl Default for Disarm {
+    #[inline(always)]
+    fn default() -> Disarm {
+        Disarm(0)
+    }
+}
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Lock(pub u32);
+impl Lock {
+    #[doc = "Write any nonzero value to disable writes to ARM, DISARM, SENSITIVITY and LOCK. This register is Secure read/write only."]
+    #[inline(always)]
+    pub const fn lock(&self) -> u8 {
+        let val = (self.0 >> 0usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Write any nonzero value to disable writes to ARM, DISARM, SENSITIVITY and LOCK. This register is Secure read/write only."]
+    #[inline(always)]
+    pub fn set_lock(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize);
+    }
+}
+impl Default for Lock {
+    #[inline(always)]
+    fn default() -> Lock {
+        Lock(0)
+    }
+}
+#[doc = "Adjust the sensitivity of glitch detectors to values other than their OTP-provided defaults. This register is Secure read/write only."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Sensitivity(pub u32);
+impl Sensitivity {
+    #[doc = "Set sensitivity for detector 0. Higher values are more sensitive."]
+    #[inline(always)]
+    pub const fn det0(&self) -> u8 {
+        let val = (self.0 >> 0usize) & 0x03;
+        val as u8
+    }
+    #[doc = "Set sensitivity for detector 0. Higher values are more sensitive."]
+    #[inline(always)]
+    pub fn set_det0(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x03 << 0usize)) | (((val as u32) & 0x03) << 0usize);
+    }
+    #[doc = "Set sensitivity for detector 1. Higher values are more sensitive."]
+    #[inline(always)]
+    pub const fn det1(&self) -> u8 {
+        let val = (self.0 >> 2usize) & 0x03;
+        val as u8
+    }
+    #[doc = "Set sensitivity for detector 1. Higher values are more sensitive."]
+    #[inline(always)]
+    pub fn set_det1(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x03 << 2usize)) | (((val as u32) & 0x03) << 2usize);
+    }
+    #[doc = "Set sensitivity for detector 2. Higher values are more sensitive."]
+    #[inline(always)]
+    pub const fn det2(&self) -> u8 {
+        let val = (self.0 >> 4usize) & 0x03;
+        val as u8
+    }
+    #[doc = "Set sensitivity for detector 2. Higher values are more sensitive."]
+    #[inline(always)]
+    pub fn set_det2(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x03 << 4usize)) | (((val as u32) & 0x03) << 4usize);
+    }
+    #[doc = "Set sensitivity for detector 3. Higher values are more sensitive."]
+    #[inline(always)]
+    pub const fn det3(&self) -> u8 {
+        let val = (self.0 >> 6usize) & 0x03;
+        val as u8
+    }
+    #[doc = "Set sensitivity for detector 3. Higher values are more sensitive."]
+    #[inline(always)]
+    pub fn set_det3(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x03 << 6usize)) | (((val as u32) & 0x03) << 6usize);
+    }
+    #[doc = "Must be the inverse of DET0, else the default value is used."]
+    #[inline(always)]
+    pub const fn det0_inv(&self) -> u8 {
+        let val = (self.0 >> 8usize) & 0x03;
+        val as u8
+    }
+    #[doc = "Must be the inverse of DET0, else the default value is used."]
+    #[inline(always)]
+    pub fn set_det0_inv(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x03 << 8usize)) | (((val as u32) & 0x03) << 8usize);
+    }
+    #[doc = "Must be the inverse of DET1, else the default value is used."]
+    #[inline(always)]
+    pub const fn det1_inv(&self) -> u8 {
+        let val = (self.0 >> 10usize) & 0x03;
+        val as u8
+    }
+    #[doc = "Must be the inverse of DET1, else the default value is used."]
+    #[inline(always)]
+    pub fn set_det1_inv(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x03 << 10usize)) | (((val as u32) & 0x03) << 10usize);
+    }
+    #[doc = "Must be the inverse of DET2, else the default value is used."]
+    #[inline(always)]
+    pub const fn det2_inv(&self) -> u8 {
+        let val = (self.0 >> 12usize) & 0x03;
+        val as u8
+    }
+    #[doc = "Must be the inverse of DET2, else the default value is used."]
+    #[inline(always)]
+    pub fn set_det2_inv(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x03 << 12usize)) | (((val as u32) & 0x03) << 12usize);
+    }
+    #[doc = "Must be the inverse of DET3, else the default value is used."]
+    #[inline(always)]
+    pub const fn det3_inv(&self) -> u8 {
+        let val = (self.0 >> 14usize) & 0x03;
+        val as u8
+    }
+    #[doc = "Must be the inverse of DET3, else the default value is used."]
+    #[inline(always)]
+    pub fn set_det3_inv(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x03 << 14usize)) | (((val as u32) & 0x03) << 14usize);
+    }
+    #[inline(always)]
+    pub const fn default(&self) -> super::vals::Default {
+        let val = (self.0 >> 24usize) & 0xff;
+        super::vals::Default::from_bits(val as u8)
+    }
+    #[inline(always)]
+    pub fn set_default(&mut self, val: super::vals::Default) {
+        self.0 = (self.0 & !(0xff << 24usize)) | (((val.to_bits() as u32) & 0xff) << 24usize);
+    }
+}
+impl Default for Sensitivity {
+    #[inline(always)]
+    fn default() -> Sensitivity {
+        Sensitivity(0)
+    }
+}
+#[doc = "Simulate the firing of one or more detectors. Writing ones to this register will set the matching bits in STATUS_TRIG. If the glitch detectors are currently armed, writing ones will also immediately reset the switched core power domain, and set the reset reason latches in POWMAN_CHIP_RESET to indicate a glitch detector resets. This register is Secure read/write only."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct TrigForce(pub u32);
+impl TrigForce {
+    #[inline(always)]
+    pub const fn trig_force(&self) -> u8 {
+        let val = (self.0 >> 0usize) & 0x0f;
+        val as u8
+    }
+    #[inline(always)]
+    pub fn set_trig_force(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize);
+    }
+}
+impl Default for TrigForce {
+    #[inline(always)]
+    fn default() -> TrigForce {
+        TrigForce(0)
+    }
+}
+#[doc = "Set when a detector output triggers. Write-1-clear. (May immediately return high if the detector remains in a failed state. Detectors can only be cleared by a full reset of the switched core power domain.) This register is Secure read/write only."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct TrigStatus(pub u32);
+impl TrigStatus {
+    #[inline(always)]
+    pub const fn det0(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_det0(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[inline(always)]
+    pub const fn det1(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_det1(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+    #[inline(always)]
+    pub const fn det2(&self) -> bool {
+        let val = (self.0 >> 2usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_det2(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+    }
+    #[inline(always)]
+    pub const fn det3(&self) -> bool {
+        let val = (self.0 >> 3usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_det3(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
+    }
+}
+impl Default for TrigStatus {
+    #[inline(always)]
+    fn default() -> TrigStatus {
+        TrigStatus(0)
+    }
+}
diff --git a/src/rp2350/glitch_detector/vals.rs b/src/rp2350/glitch_detector/vals.rs
new file mode 100644
index 00000000..244acffc
--- /dev/null
+++ b/src/rp2350/glitch_detector/vals.rs
@@ -0,0 +1,87 @@
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub struct Arm(pub u16);
+impl Arm {
+    #[doc = "Force the glitch detectors to be armed. (Any value other than ARM_NO counts as YES)"]
+    pub const YES: Self = Self(0);
+    #[doc = "Do not force the glitch detectors to be armed"]
+    pub const NO: Self = Self(0x5bad);
+}
+impl Arm {
+    pub const fn from_bits(val: u16) -> Arm {
+        Self(val & 0xffff)
+    }
+    pub const fn to_bits(self) -> u16 {
+        self.0
+    }
+}
+impl From<u16> for Arm {
+    #[inline(always)]
+    fn from(val: u16) -> Arm {
+        Arm::from_bits(val)
+    }
+}
+impl From<Arm> for u16 {
+    #[inline(always)]
+    fn from(val: Arm) -> u16 {
+        Arm::to_bits(val)
+    }
+}
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub struct Default(pub u8);
+impl Default {
+    #[doc = "Use the default sensitivity configured in OTP for all detectors. (Any value other than DEFAULT_NO counts as YES)"]
+    pub const YES: Self = Self(0);
+    #[doc = "Do not use the default sensitivity configured in OTP. Instead use the value from this register."]
+    pub const NO: Self = Self(0xde);
+}
+impl Default {
+    pub const fn from_bits(val: u8) -> Default {
+        Self(val & 0xff)
+    }
+    pub const fn to_bits(self) -> u8 {
+        self.0
+    }
+}
+impl From<u8> for Default {
+    #[inline(always)]
+    fn from(val: u8) -> Default {
+        Default::from_bits(val)
+    }
+}
+impl From<Default> for u8 {
+    #[inline(always)]
+    fn from(val: Default) -> u8 {
+        Default::to_bits(val)
+    }
+}
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub struct Disarm(pub u16);
+impl Disarm {
+    #[doc = "Do not disarm the glitch detectors. (Any value other than DISARM_YES counts as NO)"]
+    pub const NO: Self = Self(0);
+    #[doc = "Disarm the glitch detectors"]
+    pub const YES: Self = Self(0xdcaf);
+}
+impl Disarm {
+    pub const fn from_bits(val: u16) -> Disarm {
+        Self(val & 0xffff)
+    }
+    pub const fn to_bits(self) -> u16 {
+        self.0
+    }
+}
+impl From<u16> for Disarm {
+    #[inline(always)]
+    fn from(val: u16) -> Disarm {
+        Disarm::from_bits(val)
+    }
+}
+impl From<Disarm> for u16 {
+    #[inline(always)]
+    fn from(val: Disarm) -> u16 {
+        Disarm::to_bits(val)
+    }
+}
diff --git a/src/rp2350/hstx_ctrl.rs b/src/rp2350/hstx_ctrl.rs
new file mode 100644
index 00000000..f24d2caf
--- /dev/null
+++ b/src/rp2350/hstx_ctrl.rs
@@ -0,0 +1,72 @@
+#[doc = "Control interface to HSTX. For FIFO write access and status, see the HSTX_FIFO register block."]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct HstxCtrl {
+    ptr: *mut u8,
+}
+unsafe impl Send for HstxCtrl {}
+unsafe impl Sync for HstxCtrl {}
+impl HstxCtrl {
+    #[inline(always)]
+    pub const unsafe fn from_ptr(ptr: *mut ()) -> Self {
+        Self { ptr: ptr as _ }
+    }
+    #[inline(always)]
+    pub const fn as_ptr(&self) -> *mut () {
+        self.ptr as _
+    }
+    #[inline(always)]
+    pub const fn csr(self) -> crate::common::Reg<regs::Csr, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(0usize) as _) }
+    }
+    #[doc = "Data control register for output bit 0"]
+    #[inline(always)]
+    pub const fn bit0(self) -> crate::common::Reg<regs::Bit0, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(4usize) as _) }
+    }
+    #[doc = "Data control register for output bit 1"]
+    #[inline(always)]
+    pub const fn bit1(self) -> crate::common::Reg<regs::Bit1, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(8usize) as _) }
+    }
+    #[doc = "Data control register for output bit 2"]
+    #[inline(always)]
+    pub const fn bit2(self) -> crate::common::Reg<regs::Bit2, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(12usize) as _) }
+    }
+    #[doc = "Data control register for output bit 3"]
+    #[inline(always)]
+    pub const fn bit3(self) -> crate::common::Reg<regs::Bit3, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(16usize) as _) }
+    }
+    #[doc = "Data control register for output bit 4"]
+    #[inline(always)]
+    pub const fn bit4(self) -> crate::common::Reg<regs::Bit4, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(20usize) as _) }
+    }
+    #[doc = "Data control register for output bit 5"]
+    #[inline(always)]
+    pub const fn bit5(self) -> crate::common::Reg<regs::Bit5, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(24usize) as _) }
+    }
+    #[doc = "Data control register for output bit 6"]
+    #[inline(always)]
+    pub const fn bit6(self) -> crate::common::Reg<regs::Bit6, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(28usize) as _) }
+    }
+    #[doc = "Data control register for output bit 7"]
+    #[inline(always)]
+    pub const fn bit7(self) -> crate::common::Reg<regs::Bit7, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(32usize) as _) }
+    }
+    #[doc = "Configure the optional shifter inside the command expander"]
+    #[inline(always)]
+    pub const fn expand_shift(self) -> crate::common::Reg<regs::ExpandShift, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(36usize) as _) }
+    }
+    #[doc = "Configure the optional TMDS encoder inside the command expander"]
+    #[inline(always)]
+    pub const fn expand_tmds(self) -> crate::common::Reg<regs::ExpandTmds, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(40usize) as _) }
+    }
+}
+pub mod regs;
diff --git a/src/rp2350/hstx_ctrl/regs.rs b/src/rp2350/hstx_ctrl/regs.rs
new file mode 100644
index 00000000..19e4a0bb
--- /dev/null
+++ b/src/rp2350/hstx_ctrl/regs.rs
@@ -0,0 +1,681 @@
+#[doc = "Data control register for output bit 0"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Bit0(pub u32);
+impl Bit0 {
+    #[doc = "Shift register data bit select for the first half of the HSTX clock cycle"]
+    #[inline(always)]
+    pub const fn sel_p(&self) -> u8 {
+        let val = (self.0 >> 0usize) & 0x1f;
+        val as u8
+    }
+    #[doc = "Shift register data bit select for the first half of the HSTX clock cycle"]
+    #[inline(always)]
+    pub fn set_sel_p(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x1f << 0usize)) | (((val as u32) & 0x1f) << 0usize);
+    }
+    #[doc = "Shift register data bit select for the second half of the HSTX clock cycle"]
+    #[inline(always)]
+    pub const fn sel_n(&self) -> u8 {
+        let val = (self.0 >> 8usize) & 0x1f;
+        val as u8
+    }
+    #[doc = "Shift register data bit select for the second half of the HSTX clock cycle"]
+    #[inline(always)]
+    pub fn set_sel_n(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x1f << 8usize)) | (((val as u32) & 0x1f) << 8usize);
+    }
+    #[doc = "Invert this data output (logical NOT)"]
+    #[inline(always)]
+    pub const fn inv(&self) -> bool {
+        let val = (self.0 >> 16usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Invert this data output (logical NOT)"]
+    #[inline(always)]
+    pub fn set_inv(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
+    }
+    #[doc = "Connect this output to the generated clock, rather than the data shift register. SEL_P and SEL_N are ignored if this bit is set, but INV can still be set to generate an antiphase clock."]
+    #[inline(always)]
+    pub const fn clk(&self) -> bool {
+        let val = (self.0 >> 17usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Connect this output to the generated clock, rather than the data shift register. SEL_P and SEL_N are ignored if this bit is set, but INV can still be set to generate an antiphase clock."]
+    #[inline(always)]
+    pub fn set_clk(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
+    }
+}
+impl Default for Bit0 {
+    #[inline(always)]
+    fn default() -> Bit0 {
+        Bit0(0)
+    }
+}
+#[doc = "Data control register for output bit 1"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Bit1(pub u32);
+impl Bit1 {
+    #[doc = "Shift register data bit select for the first half of the HSTX clock cycle"]
+    #[inline(always)]
+    pub const fn sel_p(&self) -> u8 {
+        let val = (self.0 >> 0usize) & 0x1f;
+        val as u8
+    }
+    #[doc = "Shift register data bit select for the first half of the HSTX clock cycle"]
+    #[inline(always)]
+    pub fn set_sel_p(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x1f << 0usize)) | (((val as u32) & 0x1f) << 0usize);
+    }
+    #[doc = "Shift register data bit select for the second half of the HSTX clock cycle"]
+    #[inline(always)]
+    pub const fn sel_n(&self) -> u8 {
+        let val = (self.0 >> 8usize) & 0x1f;
+        val as u8
+    }
+    #[doc = "Shift register data bit select for the second half of the HSTX clock cycle"]
+    #[inline(always)]
+    pub fn set_sel_n(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x1f << 8usize)) | (((val as u32) & 0x1f) << 8usize);
+    }
+    #[doc = "Invert this data output (logical NOT)"]
+    #[inline(always)]
+    pub const fn inv(&self) -> bool {
+        let val = (self.0 >> 16usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Invert this data output (logical NOT)"]
+    #[inline(always)]
+    pub fn set_inv(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
+    }
+    #[doc = "Connect this output to the generated clock, rather than the data shift register. SEL_P and SEL_N are ignored if this bit is set, but INV can still be set to generate an antiphase clock."]
+    #[inline(always)]
+    pub const fn clk(&self) -> bool {
+        let val = (self.0 >> 17usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Connect this output to the generated clock, rather than the data shift register. SEL_P and SEL_N are ignored if this bit is set, but INV can still be set to generate an antiphase clock."]
+    #[inline(always)]
+    pub fn set_clk(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
+    }
+}
+impl Default for Bit1 {
+    #[inline(always)]
+    fn default() -> Bit1 {
+        Bit1(0)
+    }
+}
+#[doc = "Data control register for output bit 2"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Bit2(pub u32);
+impl Bit2 {
+    #[doc = "Shift register data bit select for the first half of the HSTX clock cycle"]
+    #[inline(always)]
+    pub const fn sel_p(&self) -> u8 {
+        let val = (self.0 >> 0usize) & 0x1f;
+        val as u8
+    }
+    #[doc = "Shift register data bit select for the first half of the HSTX clock cycle"]
+    #[inline(always)]
+    pub fn set_sel_p(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x1f << 0usize)) | (((val as u32) & 0x1f) << 0usize);
+    }
+    #[doc = "Shift register data bit select for the second half of the HSTX clock cycle"]
+    #[inline(always)]
+    pub const fn sel_n(&self) -> u8 {
+        let val = (self.0 >> 8usize) & 0x1f;
+        val as u8
+    }
+    #[doc = "Shift register data bit select for the second half of the HSTX clock cycle"]
+    #[inline(always)]
+    pub fn set_sel_n(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x1f << 8usize)) | (((val as u32) & 0x1f) << 8usize);
+    }
+    #[doc = "Invert this data output (logical NOT)"]
+    #[inline(always)]
+    pub const fn inv(&self) -> bool {
+        let val = (self.0 >> 16usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Invert this data output (logical NOT)"]
+    #[inline(always)]
+    pub fn set_inv(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
+    }
+    #[doc = "Connect this output to the generated clock, rather than the data shift register. SEL_P and SEL_N are ignored if this bit is set, but INV can still be set to generate an antiphase clock."]
+    #[inline(always)]
+    pub const fn clk(&self) -> bool {
+        let val = (self.0 >> 17usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Connect this output to the generated clock, rather than the data shift register. SEL_P and SEL_N are ignored if this bit is set, but INV can still be set to generate an antiphase clock."]
+    #[inline(always)]
+    pub fn set_clk(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
+    }
+}
+impl Default for Bit2 {
+    #[inline(always)]
+    fn default() -> Bit2 {
+        Bit2(0)
+    }
+}
+#[doc = "Data control register for output bit 3"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Bit3(pub u32);
+impl Bit3 {
+    #[doc = "Shift register data bit select for the first half of the HSTX clock cycle"]
+    #[inline(always)]
+    pub const fn sel_p(&self) -> u8 {
+        let val = (self.0 >> 0usize) & 0x1f;
+        val as u8
+    }
+    #[doc = "Shift register data bit select for the first half of the HSTX clock cycle"]
+    #[inline(always)]
+    pub fn set_sel_p(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x1f << 0usize)) | (((val as u32) & 0x1f) << 0usize);
+    }
+    #[doc = "Shift register data bit select for the second half of the HSTX clock cycle"]
+    #[inline(always)]
+    pub const fn sel_n(&self) -> u8 {
+        let val = (self.0 >> 8usize) & 0x1f;
+        val as u8
+    }
+    #[doc = "Shift register data bit select for the second half of the HSTX clock cycle"]
+    #[inline(always)]
+    pub fn set_sel_n(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x1f << 8usize)) | (((val as u32) & 0x1f) << 8usize);
+    }
+    #[doc = "Invert this data output (logical NOT)"]
+    #[inline(always)]
+    pub const fn inv(&self) -> bool {
+        let val = (self.0 >> 16usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Invert this data output (logical NOT)"]
+    #[inline(always)]
+    pub fn set_inv(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
+    }
+    #[doc = "Connect this output to the generated clock, rather than the data shift register. SEL_P and SEL_N are ignored if this bit is set, but INV can still be set to generate an antiphase clock."]
+    #[inline(always)]
+    pub const fn clk(&self) -> bool {
+        let val = (self.0 >> 17usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Connect this output to the generated clock, rather than the data shift register. SEL_P and SEL_N are ignored if this bit is set, but INV can still be set to generate an antiphase clock."]
+    #[inline(always)]
+    pub fn set_clk(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
+    }
+}
+impl Default for Bit3 {
+    #[inline(always)]
+    fn default() -> Bit3 {
+        Bit3(0)
+    }
+}
+#[doc = "Data control register for output bit 4"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Bit4(pub u32);
+impl Bit4 {
+    #[doc = "Shift register data bit select for the first half of the HSTX clock cycle"]
+    #[inline(always)]
+    pub const fn sel_p(&self) -> u8 {
+        let val = (self.0 >> 0usize) & 0x1f;
+        val as u8
+    }
+    #[doc = "Shift register data bit select for the first half of the HSTX clock cycle"]
+    #[inline(always)]
+    pub fn set_sel_p(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x1f << 0usize)) | (((val as u32) & 0x1f) << 0usize);
+    }
+    #[doc = "Shift register data bit select for the second half of the HSTX clock cycle"]
+    #[inline(always)]
+    pub const fn sel_n(&self) -> u8 {
+        let val = (self.0 >> 8usize) & 0x1f;
+        val as u8
+    }
+    #[doc = "Shift register data bit select for the second half of the HSTX clock cycle"]
+    #[inline(always)]
+    pub fn set_sel_n(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x1f << 8usize)) | (((val as u32) & 0x1f) << 8usize);
+    }
+    #[doc = "Invert this data output (logical NOT)"]
+    #[inline(always)]
+    pub const fn inv(&self) -> bool {
+        let val = (self.0 >> 16usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Invert this data output (logical NOT)"]
+    #[inline(always)]
+    pub fn set_inv(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
+    }
+    #[doc = "Connect this output to the generated clock, rather than the data shift register. SEL_P and SEL_N are ignored if this bit is set, but INV can still be set to generate an antiphase clock."]
+    #[inline(always)]
+    pub const fn clk(&self) -> bool {
+        let val = (self.0 >> 17usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Connect this output to the generated clock, rather than the data shift register. SEL_P and SEL_N are ignored if this bit is set, but INV can still be set to generate an antiphase clock."]
+    #[inline(always)]
+    pub fn set_clk(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
+    }
+}
+impl Default for Bit4 {
+    #[inline(always)]
+    fn default() -> Bit4 {
+        Bit4(0)
+    }
+}
+#[doc = "Data control register for output bit 5"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Bit5(pub u32);
+impl Bit5 {
+    #[doc = "Shift register data bit select for the first half of the HSTX clock cycle"]
+    #[inline(always)]
+    pub const fn sel_p(&self) -> u8 {
+        let val = (self.0 >> 0usize) & 0x1f;
+        val as u8
+    }
+    #[doc = "Shift register data bit select for the first half of the HSTX clock cycle"]
+    #[inline(always)]
+    pub fn set_sel_p(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x1f << 0usize)) | (((val as u32) & 0x1f) << 0usize);
+    }
+    #[doc = "Shift register data bit select for the second half of the HSTX clock cycle"]
+    #[inline(always)]
+    pub const fn sel_n(&self) -> u8 {
+        let val = (self.0 >> 8usize) & 0x1f;
+        val as u8
+    }
+    #[doc = "Shift register data bit select for the second half of the HSTX clock cycle"]
+    #[inline(always)]
+    pub fn set_sel_n(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x1f << 8usize)) | (((val as u32) & 0x1f) << 8usize);
+    }
+    #[doc = "Invert this data output (logical NOT)"]
+    #[inline(always)]
+    pub const fn inv(&self) -> bool {
+        let val = (self.0 >> 16usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Invert this data output (logical NOT)"]
+    #[inline(always)]
+    pub fn set_inv(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
+    }
+    #[doc = "Connect this output to the generated clock, rather than the data shift register. SEL_P and SEL_N are ignored if this bit is set, but INV can still be set to generate an antiphase clock."]
+    #[inline(always)]
+    pub const fn clk(&self) -> bool {
+        let val = (self.0 >> 17usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Connect this output to the generated clock, rather than the data shift register. SEL_P and SEL_N are ignored if this bit is set, but INV can still be set to generate an antiphase clock."]
+    #[inline(always)]
+    pub fn set_clk(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
+    }
+}
+impl Default for Bit5 {
+    #[inline(always)]
+    fn default() -> Bit5 {
+        Bit5(0)
+    }
+}
+#[doc = "Data control register for output bit 6"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Bit6(pub u32);
+impl Bit6 {
+    #[doc = "Shift register data bit select for the first half of the HSTX clock cycle"]
+    #[inline(always)]
+    pub const fn sel_p(&self) -> u8 {
+        let val = (self.0 >> 0usize) & 0x1f;
+        val as u8
+    }
+    #[doc = "Shift register data bit select for the first half of the HSTX clock cycle"]
+    #[inline(always)]
+    pub fn set_sel_p(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x1f << 0usize)) | (((val as u32) & 0x1f) << 0usize);
+    }
+    #[doc = "Shift register data bit select for the second half of the HSTX clock cycle"]
+    #[inline(always)]
+    pub const fn sel_n(&self) -> u8 {
+        let val = (self.0 >> 8usize) & 0x1f;
+        val as u8
+    }
+    #[doc = "Shift register data bit select for the second half of the HSTX clock cycle"]
+    #[inline(always)]
+    pub fn set_sel_n(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x1f << 8usize)) | (((val as u32) & 0x1f) << 8usize);
+    }
+    #[doc = "Invert this data output (logical NOT)"]
+    #[inline(always)]
+    pub const fn inv(&self) -> bool {
+        let val = (self.0 >> 16usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Invert this data output (logical NOT)"]
+    #[inline(always)]
+    pub fn set_inv(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
+    }
+    #[doc = "Connect this output to the generated clock, rather than the data shift register. SEL_P and SEL_N are ignored if this bit is set, but INV can still be set to generate an antiphase clock."]
+    #[inline(always)]
+    pub const fn clk(&self) -> bool {
+        let val = (self.0 >> 17usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Connect this output to the generated clock, rather than the data shift register. SEL_P and SEL_N are ignored if this bit is set, but INV can still be set to generate an antiphase clock."]
+    #[inline(always)]
+    pub fn set_clk(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
+    }
+}
+impl Default for Bit6 {
+    #[inline(always)]
+    fn default() -> Bit6 {
+        Bit6(0)
+    }
+}
+#[doc = "Data control register for output bit 7"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Bit7(pub u32);
+impl Bit7 {
+    #[doc = "Shift register data bit select for the first half of the HSTX clock cycle"]
+    #[inline(always)]
+    pub const fn sel_p(&self) -> u8 {
+        let val = (self.0 >> 0usize) & 0x1f;
+        val as u8
+    }
+    #[doc = "Shift register data bit select for the first half of the HSTX clock cycle"]
+    #[inline(always)]
+    pub fn set_sel_p(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x1f << 0usize)) | (((val as u32) & 0x1f) << 0usize);
+    }
+    #[doc = "Shift register data bit select for the second half of the HSTX clock cycle"]
+    #[inline(always)]
+    pub const fn sel_n(&self) -> u8 {
+        let val = (self.0 >> 8usize) & 0x1f;
+        val as u8
+    }
+    #[doc = "Shift register data bit select for the second half of the HSTX clock cycle"]
+    #[inline(always)]
+    pub fn set_sel_n(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x1f << 8usize)) | (((val as u32) & 0x1f) << 8usize);
+    }
+    #[doc = "Invert this data output (logical NOT)"]
+    #[inline(always)]
+    pub const fn inv(&self) -> bool {
+        let val = (self.0 >> 16usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Invert this data output (logical NOT)"]
+    #[inline(always)]
+    pub fn set_inv(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
+    }
+    #[doc = "Connect this output to the generated clock, rather than the data shift register. SEL_P and SEL_N are ignored if this bit is set, but INV can still be set to generate an antiphase clock."]
+    #[inline(always)]
+    pub const fn clk(&self) -> bool {
+        let val = (self.0 >> 17usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Connect this output to the generated clock, rather than the data shift register. SEL_P and SEL_N are ignored if this bit is set, but INV can still be set to generate an antiphase clock."]
+    #[inline(always)]
+    pub fn set_clk(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
+    }
+}
+impl Default for Bit7 {
+    #[inline(always)]
+    fn default() -> Bit7 {
+        Bit7(0)
+    }
+}
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Csr(pub u32);
+impl Csr {
+    #[doc = "When EN is 1, the HSTX will shift out data as it appears in the FIFO. As long as there is data, the HSTX shift register will shift once per clock cycle, and the frequency of popping from the FIFO is determined by the ratio of SHIFT and SHIFT_THRESH. When EN is 0, the FIFO is not popped. The shift counter and clock generator are also reset to their initial state for as long as EN is low. Note the initial phase of the clock generator can be configured by the CLKPHASE field. Once the HSTX is enabled again, and data is pushed to the FIFO, the generated clock's first rising edge will be one half-period after the first data is launched."]
+    #[inline(always)]
+    pub const fn en(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "When EN is 1, the HSTX will shift out data as it appears in the FIFO. As long as there is data, the HSTX shift register will shift once per clock cycle, and the frequency of popping from the FIFO is determined by the ratio of SHIFT and SHIFT_THRESH. When EN is 0, the FIFO is not popped. The shift counter and clock generator are also reset to their initial state for as long as EN is low. Note the initial phase of the clock generator can be configured by the CLKPHASE field. Once the HSTX is enabled again, and data is pushed to the FIFO, the generated clock's first rising edge will be one half-period after the first data is launched."]
+    #[inline(always)]
+    pub fn set_en(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[doc = "Enable the command expander. When 0, raw FIFO data is passed directly to the output shift register. When 1, the command expander can perform simple operations such as run length decoding on data between the FIFO and the shift register. Do not change CXPD_EN whilst EN is set. It's safe to set CXPD_EN simultaneously with setting EN."]
+    #[inline(always)]
+    pub const fn expand_en(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Enable the command expander. When 0, raw FIFO data is passed directly to the output shift register. When 1, the command expander can perform simple operations such as run length decoding on data between the FIFO and the shift register. Do not change CXPD_EN whilst EN is set. It's safe to set CXPD_EN simultaneously with setting EN."]
+    #[inline(always)]
+    pub fn set_expand_en(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+    #[doc = "Enable the PIO-to-HSTX 1:1 connection. The HSTX must be clocked *directly* from the system clock (not just from some other clock source of the same frequency) for this synchronous interface to function correctly. When COUPLED_MODE is set, BITx_SEL_P and SEL_N indices 24 through 31 will select bits from the 8-bit PIO-to-HSTX path, rather than shifter bits. Indices of 0 through 23 will still index the shift register as normal. The PIO outputs connected to the PIO-to-HSTX bus are those same outputs that would appear on the HSTX-capable pins if those pins' FUNCSELs were set to PIO instead of HSTX. For example, if HSTX is on GPIOs 12 through 19, then PIO outputs 12 through 19 are connected to the HSTX when coupled mode is engaged."]
+    #[inline(always)]
+    pub const fn coupled_mode(&self) -> bool {
+        let val = (self.0 >> 4usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Enable the PIO-to-HSTX 1:1 connection. The HSTX must be clocked *directly* from the system clock (not just from some other clock source of the same frequency) for this synchronous interface to function correctly. When COUPLED_MODE is set, BITx_SEL_P and SEL_N indices 24 through 31 will select bits from the 8-bit PIO-to-HSTX path, rather than shifter bits. Indices of 0 through 23 will still index the shift register as normal. The PIO outputs connected to the PIO-to-HSTX bus are those same outputs that would appear on the HSTX-capable pins if those pins' FUNCSELs were set to PIO instead of HSTX. For example, if HSTX is on GPIOs 12 through 19, then PIO outputs 12 through 19 are connected to the HSTX when coupled mode is engaged."]
+    #[inline(always)]
+    pub fn set_coupled_mode(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
+    }
+    #[doc = "Select which PIO to use for coupled mode operation."]
+    #[inline(always)]
+    pub const fn coupled_sel(&self) -> u8 {
+        let val = (self.0 >> 5usize) & 0x03;
+        val as u8
+    }
+    #[doc = "Select which PIO to use for coupled mode operation."]
+    #[inline(always)]
+    pub fn set_coupled_sel(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x03 << 5usize)) | (((val as u32) & 0x03) << 5usize);
+    }
+    #[doc = "How many bits to right-rotate the shift register by each cycle. The use of a rotate rather than a shift allows left shifts to be emulated, by subtracting the left-shift amount from 32. It also allows data to be repeated, when the product of SHIFT and N_SHIFTS is greater than 32."]
+    #[inline(always)]
+    pub const fn shift(&self) -> u8 {
+        let val = (self.0 >> 8usize) & 0x1f;
+        val as u8
+    }
+    #[doc = "How many bits to right-rotate the shift register by each cycle. The use of a rotate rather than a shift allows left shifts to be emulated, by subtracting the left-shift amount from 32. It also allows data to be repeated, when the product of SHIFT and N_SHIFTS is greater than 32."]
+    #[inline(always)]
+    pub fn set_shift(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x1f << 8usize)) | (((val as u32) & 0x1f) << 8usize);
+    }
+    #[doc = "Number of times to shift the shift register before refilling it from the FIFO. (A count of how many times it has been shifted, *not* the total shift distance.) A register value of 0 means shift 32 times."]
+    #[inline(always)]
+    pub const fn n_shifts(&self) -> u8 {
+        let val = (self.0 >> 16usize) & 0x1f;
+        val as u8
+    }
+    #[doc = "Number of times to shift the shift register before refilling it from the FIFO. (A count of how many times it has been shifted, *not* the total shift distance.) A register value of 0 means shift 32 times."]
+    #[inline(always)]
+    pub fn set_n_shifts(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x1f << 16usize)) | (((val as u32) & 0x1f) << 16usize);
+    }
+    #[doc = "Set the initial phase of the generated clock. A CLKPHASE of 0 means the clock is initially low, and the first rising edge occurs after one half period of the generated clock (i.e. CLKDIV/2 cycles of clk_hstx). Incrementing CLKPHASE by 1 will advance the initial clock phase by one half clk_hstx period. For example, if CLKDIV=2 and CLKPHASE=1: * The clock will be initially low * The first rising edge will be 0.5 clk_hstx cycles after asserting first data * The first falling edge will be 1.5 clk_hstx cycles after asserting first data This configuration would be suitable for serialising at a bit rate of clk_hstx with a centre-aligned DDR clock. When the HSTX is halted by clearing CSR_EN, the clock generator will return to its initial phase as configured by the CLKPHASE field. Note CLKPHASE must be strictly less than double the value of CLKDIV (one full period), else its operation is undefined."]
+    #[inline(always)]
+    pub const fn clkphase(&self) -> u8 {
+        let val = (self.0 >> 24usize) & 0x0f;
+        val as u8
+    }
+    #[doc = "Set the initial phase of the generated clock. A CLKPHASE of 0 means the clock is initially low, and the first rising edge occurs after one half period of the generated clock (i.e. CLKDIV/2 cycles of clk_hstx). Incrementing CLKPHASE by 1 will advance the initial clock phase by one half clk_hstx period. For example, if CLKDIV=2 and CLKPHASE=1: * The clock will be initially low * The first rising edge will be 0.5 clk_hstx cycles after asserting first data * The first falling edge will be 1.5 clk_hstx cycles after asserting first data This configuration would be suitable for serialising at a bit rate of clk_hstx with a centre-aligned DDR clock. When the HSTX is halted by clearing CSR_EN, the clock generator will return to its initial phase as configured by the CLKPHASE field. Note CLKPHASE must be strictly less than double the value of CLKDIV (one full period), else its operation is undefined."]
+    #[inline(always)]
+    pub fn set_clkphase(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x0f << 24usize)) | (((val as u32) & 0x0f) << 24usize);
+    }
+    #[doc = "Clock period of the generated clock, measured in HSTX clock cycles. Can be odd or even. The generated clock advances only on cycles where the shift register shifts. For example, a clkdiv of 5 would generate a complete output clock period for every 5 HSTX clocks (or every 10 half-clocks). A CLKDIV value of 0 is mapped to a period of 16 HSTX clock cycles."]
+    #[inline(always)]
+    pub const fn clkdiv(&self) -> u8 {
+        let val = (self.0 >> 28usize) & 0x0f;
+        val as u8
+    }
+    #[doc = "Clock period of the generated clock, measured in HSTX clock cycles. Can be odd or even. The generated clock advances only on cycles where the shift register shifts. For example, a clkdiv of 5 would generate a complete output clock period for every 5 HSTX clocks (or every 10 half-clocks). A CLKDIV value of 0 is mapped to a period of 16 HSTX clock cycles."]
+    #[inline(always)]
+    pub fn set_clkdiv(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x0f << 28usize)) | (((val as u32) & 0x0f) << 28usize);
+    }
+}
+impl Default for Csr {
+    #[inline(always)]
+    fn default() -> Csr {
+        Csr(0)
+    }
+}
+#[doc = "Configure the optional shifter inside the command expander"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct ExpandShift(pub u32);
+impl ExpandShift {
+    #[doc = "How many bits to right-rotate the shift register by each time data is pushed to the output shifter, when the current command is a raw data command."]
+    #[inline(always)]
+    pub const fn raw_shift(&self) -> u8 {
+        let val = (self.0 >> 0usize) & 0x1f;
+        val as u8
+    }
+    #[doc = "How many bits to right-rotate the shift register by each time data is pushed to the output shifter, when the current command is a raw data command."]
+    #[inline(always)]
+    pub fn set_raw_shift(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x1f << 0usize)) | (((val as u32) & 0x1f) << 0usize);
+    }
+    #[doc = "Number of times to consume from the shift register before refilling it from the FIFO, when the current command is a raw data command. A register value of 0 means shift 32 times."]
+    #[inline(always)]
+    pub const fn raw_n_shifts(&self) -> u8 {
+        let val = (self.0 >> 8usize) & 0x1f;
+        val as u8
+    }
+    #[doc = "Number of times to consume from the shift register before refilling it from the FIFO, when the current command is a raw data command. A register value of 0 means shift 32 times."]
+    #[inline(always)]
+    pub fn set_raw_n_shifts(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x1f << 8usize)) | (((val as u32) & 0x1f) << 8usize);
+    }
+    #[doc = "How many bits to right-rotate the shift register by each time data is pushed to the output shifter, when the current command is an encoded data command (e.g. TMDS)."]
+    #[inline(always)]
+    pub const fn enc_shift(&self) -> u8 {
+        let val = (self.0 >> 16usize) & 0x1f;
+        val as u8
+    }
+    #[doc = "How many bits to right-rotate the shift register by each time data is pushed to the output shifter, when the current command is an encoded data command (e.g. TMDS)."]
+    #[inline(always)]
+    pub fn set_enc_shift(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x1f << 16usize)) | (((val as u32) & 0x1f) << 16usize);
+    }
+    #[doc = "Number of times to consume from the shift register before refilling it from the FIFO, when the current command is an encoded data command (e.g. TMDS). A register value of 0 means shift 32 times."]
+    #[inline(always)]
+    pub const fn enc_n_shifts(&self) -> u8 {
+        let val = (self.0 >> 24usize) & 0x1f;
+        val as u8
+    }
+    #[doc = "Number of times to consume from the shift register before refilling it from the FIFO, when the current command is an encoded data command (e.g. TMDS). A register value of 0 means shift 32 times."]
+    #[inline(always)]
+    pub fn set_enc_n_shifts(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x1f << 24usize)) | (((val as u32) & 0x1f) << 24usize);
+    }
+}
+impl Default for ExpandShift {
+    #[inline(always)]
+    fn default() -> ExpandShift {
+        ExpandShift(0)
+    }
+}
+#[doc = "Configure the optional TMDS encoder inside the command expander"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct ExpandTmds(pub u32);
+impl ExpandTmds {
+    #[doc = "Right-rotate applied to the current shifter data before the lane 0 TMDS encoder."]
+    #[inline(always)]
+    pub const fn l0_rot(&self) -> u8 {
+        let val = (self.0 >> 0usize) & 0x1f;
+        val as u8
+    }
+    #[doc = "Right-rotate applied to the current shifter data before the lane 0 TMDS encoder."]
+    #[inline(always)]
+    pub fn set_l0_rot(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x1f << 0usize)) | (((val as u32) & 0x1f) << 0usize);
+    }
+    #[doc = "Number of valid data bits for the lane 0 TMDS encoder, starting from bit 7 of the rotated data. Field values of 0 -> 7 encode counts of 1 -> 8 bits."]
+    #[inline(always)]
+    pub const fn l0_nbits(&self) -> u8 {
+        let val = (self.0 >> 5usize) & 0x07;
+        val as u8
+    }
+    #[doc = "Number of valid data bits for the lane 0 TMDS encoder, starting from bit 7 of the rotated data. Field values of 0 -> 7 encode counts of 1 -> 8 bits."]
+    #[inline(always)]
+    pub fn set_l0_nbits(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x07 << 5usize)) | (((val as u32) & 0x07) << 5usize);
+    }
+    #[doc = "Right-rotate applied to the current shifter data before the lane 1 TMDS encoder."]
+    #[inline(always)]
+    pub const fn l1_rot(&self) -> u8 {
+        let val = (self.0 >> 8usize) & 0x1f;
+        val as u8
+    }
+    #[doc = "Right-rotate applied to the current shifter data before the lane 1 TMDS encoder."]
+    #[inline(always)]
+    pub fn set_l1_rot(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x1f << 8usize)) | (((val as u32) & 0x1f) << 8usize);
+    }
+    #[doc = "Number of valid data bits for the lane 1 TMDS encoder, starting from bit 7 of the rotated data. Field values of 0 -> 7 encode counts of 1 -> 8 bits."]
+    #[inline(always)]
+    pub const fn l1_nbits(&self) -> u8 {
+        let val = (self.0 >> 13usize) & 0x07;
+        val as u8
+    }
+    #[doc = "Number of valid data bits for the lane 1 TMDS encoder, starting from bit 7 of the rotated data. Field values of 0 -> 7 encode counts of 1 -> 8 bits."]
+    #[inline(always)]
+    pub fn set_l1_nbits(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x07 << 13usize)) | (((val as u32) & 0x07) << 13usize);
+    }
+    #[doc = "Right-rotate applied to the current shifter data before the lane 2 TMDS encoder."]
+    #[inline(always)]
+    pub const fn l2_rot(&self) -> u8 {
+        let val = (self.0 >> 16usize) & 0x1f;
+        val as u8
+    }
+    #[doc = "Right-rotate applied to the current shifter data before the lane 2 TMDS encoder."]
+    #[inline(always)]
+    pub fn set_l2_rot(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x1f << 16usize)) | (((val as u32) & 0x1f) << 16usize);
+    }
+    #[doc = "Number of valid data bits for the lane 2 TMDS encoder, starting from bit 7 of the rotated data. Field values of 0 -> 7 encode counts of 1 -> 8 bits."]
+    #[inline(always)]
+    pub const fn l2_nbits(&self) -> u8 {
+        let val = (self.0 >> 21usize) & 0x07;
+        val as u8
+    }
+    #[doc = "Number of valid data bits for the lane 2 TMDS encoder, starting from bit 7 of the rotated data. Field values of 0 -> 7 encode counts of 1 -> 8 bits."]
+    #[inline(always)]
+    pub fn set_l2_nbits(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x07 << 21usize)) | (((val as u32) & 0x07) << 21usize);
+    }
+}
+impl Default for ExpandTmds {
+    #[inline(always)]
+    fn default() -> ExpandTmds {
+        ExpandTmds(0)
+    }
+}
diff --git a/src/rp2350/hstx_fifo.rs b/src/rp2350/hstx_fifo.rs
new file mode 100644
index 00000000..c7108751
--- /dev/null
+++ b/src/rp2350/hstx_fifo.rs
@@ -0,0 +1,28 @@
+#[doc = "FIFO status and write access for HSTX"]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct HstxFifo {
+    ptr: *mut u8,
+}
+unsafe impl Send for HstxFifo {}
+unsafe impl Sync for HstxFifo {}
+impl HstxFifo {
+    #[inline(always)]
+    pub const unsafe fn from_ptr(ptr: *mut ()) -> Self {
+        Self { ptr: ptr as _ }
+    }
+    #[inline(always)]
+    pub const fn as_ptr(&self) -> *mut () {
+        self.ptr as _
+    }
+    #[doc = "FIFO status"]
+    #[inline(always)]
+    pub const fn stat(self) -> crate::common::Reg<regs::Stat, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(0usize) as _) }
+    }
+    #[doc = "Write access to FIFO"]
+    #[inline(always)]
+    pub const fn fifo(self) -> crate::common::Reg<u32, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(4usize) as _) }
+    }
+}
+pub mod regs;
diff --git a/src/rp2350/hstx_fifo/regs.rs b/src/rp2350/hstx_fifo/regs.rs
new file mode 100644
index 00000000..fe6ede8d
--- /dev/null
+++ b/src/rp2350/hstx_fifo/regs.rs
@@ -0,0 +1,50 @@
+#[doc = "FIFO status"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Stat(pub u32);
+impl Stat {
+    #[inline(always)]
+    pub const fn level(&self) -> u8 {
+        let val = (self.0 >> 0usize) & 0xff;
+        val as u8
+    }
+    #[inline(always)]
+    pub fn set_level(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize);
+    }
+    #[inline(always)]
+    pub const fn full(&self) -> bool {
+        let val = (self.0 >> 8usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_full(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
+    }
+    #[inline(always)]
+    pub const fn empty(&self) -> bool {
+        let val = (self.0 >> 9usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_empty(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
+    }
+    #[doc = "FIFO was written when full. Write 1 to clear."]
+    #[inline(always)]
+    pub const fn wof(&self) -> bool {
+        let val = (self.0 >> 10usize) & 0x01;
+        val != 0
+    }
+    #[doc = "FIFO was written when full. Write 1 to clear."]
+    #[inline(always)]
+    pub fn set_wof(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize);
+    }
+}
+impl Default for Stat {
+    #[inline(always)]
+    fn default() -> Stat {
+        Stat(0)
+    }
+}
diff --git a/src/rp2350/i2c.rs b/src/rp2350/i2c.rs
new file mode 100644
index 00000000..c752f5d1
--- /dev/null
+++ b/src/rp2350/i2c.rs
@@ -0,0 +1,253 @@
+#[doc = "DW_apb_i2c address block List of configuration constants for the Synopsys I2C hardware (you may see references to these in I2C register header; these are *fixed* values, set at hardware design time): IC_ULTRA_FAST_MODE ................ 0x0 IC_UFM_TBUF_CNT_DEFAULT ........... 0x8 IC_UFM_SCL_LOW_COUNT .............. 0x0008 IC_UFM_SCL_HIGH_COUNT ............. 0x0006 IC_TX_TL .......................... 0x0 IC_TX_CMD_BLOCK ................... 0x1 IC_HAS_DMA ........................ 0x1 IC_HAS_ASYNC_FIFO ................. 0x0 IC_SMBUS_ARP ...................... 0x0 IC_FIRST_DATA_BYTE_STATUS ......... 0x1 IC_INTR_IO ........................ 0x1 IC_MASTER_MODE .................... 0x1 IC_DEFAULT_ACK_GENERAL_CALL ....... 0x1 IC_INTR_POL ....................... 0x1 IC_OPTIONAL_SAR ................... 0x0 IC_DEFAULT_TAR_SLAVE_ADDR ......... 0x055 IC_DEFAULT_SLAVE_ADDR ............. 0x055 IC_DEFAULT_HS_SPKLEN .............. 0x1 IC_FS_SCL_HIGH_COUNT .............. 0x0006 IC_HS_SCL_LOW_COUNT ............... 0x0008 IC_DEVICE_ID_VALUE ................ 0x0 IC_10BITADDR_MASTER ............... 0x0 IC_CLK_FREQ_OPTIMIZATION .......... 0x0 IC_DEFAULT_FS_SPKLEN .............. 0x7 IC_ADD_ENCODED_PARAMS ............. 0x0 IC_DEFAULT_SDA_HOLD ............... 0x000001 IC_DEFAULT_SDA_SETUP .............. 0x64 IC_AVOID_RX_FIFO_FLUSH_ON_TX_ABRT . 0x0 IC_CLOCK_PERIOD ................... 100 IC_EMPTYFIFO_HOLD_MASTER_EN ....... 1 IC_RESTART_EN ..................... 0x1 IC_TX_CMD_BLOCK_DEFAULT ........... 0x0 IC_BUS_CLEAR_FEATURE .............. 0x0 IC_CAP_LOADING .................... 100 IC_FS_SCL_LOW_COUNT ............... 0x000d APB_DATA_WIDTH .................... 32 IC_SDA_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff IC_SLV_DATA_NACK_ONLY ............. 0x1 IC_10BITADDR_SLAVE ................ 0x0 IC_CLK_TYPE ....................... 0x0 IC_SMBUS_UDID_MSB ................. 0x0 IC_SMBUS_SUSPEND_ALERT ............ 0x0 IC_HS_SCL_HIGH_COUNT .............. 0x0006 IC_SLV_RESTART_DET_EN ............. 0x1 IC_SMBUS .......................... 0x0 IC_OPTIONAL_SAR_DEFAULT ........... 0x0 IC_PERSISTANT_SLV_ADDR_DEFAULT .... 0x0 IC_USE_COUNTS ..................... 0x0 IC_RX_BUFFER_DEPTH ................ 16 IC_SCL_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff IC_RX_FULL_HLD_BUS_EN ............. 0x1 IC_SLAVE_DISABLE .................. 0x1 IC_RX_TL .......................... 0x0 IC_DEVICE_ID ...................... 0x0 IC_HC_COUNT_VALUES ................ 0x0 I2C_DYNAMIC_TAR_UPDATE ............ 0 IC_SMBUS_CLK_LOW_MEXT_DEFAULT ..... 0xffffffff IC_SMBUS_CLK_LOW_SEXT_DEFAULT ..... 0xffffffff IC_HS_MASTER_CODE ................. 0x1 IC_SMBUS_RST_IDLE_CNT_DEFAULT ..... 0xffff IC_SMBUS_UDID_LSB_DEFAULT ......... 0xffffffff IC_SS_SCL_HIGH_COUNT .............. 0x0028 IC_SS_SCL_LOW_COUNT ............... 0x002f IC_MAX_SPEED_MODE ................. 0x2 IC_STAT_FOR_CLK_STRETCH ........... 0x0 IC_STOP_DET_IF_MASTER_ACTIVE ...... 0x0 IC_DEFAULT_UFM_SPKLEN ............. 0x1 IC_TX_BUFFER_DEPTH ................ 16"]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct I2c {
+    ptr: *mut u8,
+}
+unsafe impl Send for I2c {}
+unsafe impl Sync for I2c {}
+impl I2c {
+    #[inline(always)]
+    pub const unsafe fn from_ptr(ptr: *mut ()) -> Self {
+        Self { ptr: ptr as _ }
+    }
+    #[inline(always)]
+    pub const fn as_ptr(&self) -> *mut () {
+        self.ptr as _
+    }
+    #[doc = "I2C Control Register. This register can be written only when the DW_apb_i2c is disabled, which corresponds to the IC_ENABLE\\[0\\] register being set to 0. Writes at other times have no effect. Read/Write Access: - bit 10 is read only. - bit 11 is read only - bit 16 is read only - bit 17 is read only - bits 18 and 19 are read only."]
+    #[inline(always)]
+    pub const fn ic_con(self) -> crate::common::Reg<regs::IcCon, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(0usize) as _) }
+    }
+    #[doc = "I2C Target Address Register This register is 12 bits wide, and bits 31:12 are reserved. This register can be written to only when IC_ENABLE\\[0\\] is set to 0. Note: If the software or application is aware that the DW_apb_i2c is not using the TAR address for the pending commands in the Tx FIFO, then it is possible to update the TAR address even while the Tx FIFO has entries (IC_STATUS\\[2\\]= 0). - It is not necessary to perform any write to this register if DW_apb_i2c is enabled as an I2C slave only."]
+    #[inline(always)]
+    pub const fn ic_tar(self) -> crate::common::Reg<regs::IcTar, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(4usize) as _) }
+    }
+    #[doc = "I2C Slave Address Register"]
+    #[inline(always)]
+    pub const fn ic_sar(self) -> crate::common::Reg<regs::IcSar, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(8usize) as _) }
+    }
+    #[doc = "I2C Rx/Tx Data Buffer and Command Register; this is the register the CPU writes to when filling the TX FIFO and the CPU reads from when retrieving bytes from RX FIFO. The size of the register changes as follows: Write: - 11 bits when IC_EMPTYFIFO_HOLD_MASTER_EN=1 - 9 bits when IC_EMPTYFIFO_HOLD_MASTER_EN=0 Read: - 12 bits when IC_FIRST_DATA_BYTE_STATUS = 1 - 8 bits when IC_FIRST_DATA_BYTE_STATUS = 0 Note: In order for the DW_apb_i2c to continue acknowledging reads, a read command should be written for every byte that is to be received; otherwise the DW_apb_i2c will stop acknowledging."]
+    #[inline(always)]
+    pub const fn ic_data_cmd(self) -> crate::common::Reg<regs::IcDataCmd, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(16usize) as _) }
+    }
+    #[doc = "Standard Speed I2C Clock SCL High Count Register"]
+    #[inline(always)]
+    pub const fn ic_ss_scl_hcnt(self) -> crate::common::Reg<regs::IcSsSclHcnt, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(20usize) as _) }
+    }
+    #[doc = "Standard Speed I2C Clock SCL Low Count Register"]
+    #[inline(always)]
+    pub const fn ic_ss_scl_lcnt(self) -> crate::common::Reg<regs::IcSsSclLcnt, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(24usize) as _) }
+    }
+    #[doc = "Fast Mode or Fast Mode Plus I2C Clock SCL High Count Register"]
+    #[inline(always)]
+    pub const fn ic_fs_scl_hcnt(self) -> crate::common::Reg<regs::IcFsSclHcnt, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(28usize) as _) }
+    }
+    #[doc = "Fast Mode or Fast Mode Plus I2C Clock SCL Low Count Register"]
+    #[inline(always)]
+    pub const fn ic_fs_scl_lcnt(self) -> crate::common::Reg<regs::IcFsSclLcnt, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(32usize) as _) }
+    }
+    #[doc = "I2C Interrupt Status Register Each bit in this register has a corresponding mask bit in the IC_INTR_MASK register. These bits are cleared by reading the matching interrupt clear register. The unmasked raw versions of these bits are available in the IC_RAW_INTR_STAT register."]
+    #[inline(always)]
+    pub const fn ic_intr_stat(self) -> crate::common::Reg<regs::IcIntrStat, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(44usize) as _) }
+    }
+    #[doc = "I2C Interrupt Mask Register. These bits mask their corresponding interrupt status bits. This register is active low; a value of 0 masks the interrupt, whereas a value of 1 unmasks the interrupt."]
+    #[inline(always)]
+    pub const fn ic_intr_mask(self) -> crate::common::Reg<regs::IcIntrMask, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(48usize) as _) }
+    }
+    #[doc = "I2C Raw Interrupt Status Register Unlike the IC_INTR_STAT register, these bits are not masked so they always show the true status of the DW_apb_i2c."]
+    #[inline(always)]
+    pub const fn ic_raw_intr_stat(
+        self,
+    ) -> crate::common::Reg<regs::IcRawIntrStat, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(52usize) as _) }
+    }
+    #[doc = "I2C Receive FIFO Threshold Register"]
+    #[inline(always)]
+    pub const fn ic_rx_tl(self) -> crate::common::Reg<regs::IcRxTl, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(56usize) as _) }
+    }
+    #[doc = "I2C Transmit FIFO Threshold Register"]
+    #[inline(always)]
+    pub const fn ic_tx_tl(self) -> crate::common::Reg<regs::IcTxTl, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(60usize) as _) }
+    }
+    #[doc = "Clear Combined and Individual Interrupt Register"]
+    #[inline(always)]
+    pub const fn ic_clr_intr(self) -> crate::common::Reg<regs::IcClrIntr, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(64usize) as _) }
+    }
+    #[doc = "Clear RX_UNDER Interrupt Register"]
+    #[inline(always)]
+    pub const fn ic_clr_rx_under(
+        self,
+    ) -> crate::common::Reg<regs::IcClrRxUnder, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(68usize) as _) }
+    }
+    #[doc = "Clear RX_OVER Interrupt Register"]
+    #[inline(always)]
+    pub const fn ic_clr_rx_over(self) -> crate::common::Reg<regs::IcClrRxOver, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(72usize) as _) }
+    }
+    #[doc = "Clear TX_OVER Interrupt Register"]
+    #[inline(always)]
+    pub const fn ic_clr_tx_over(self) -> crate::common::Reg<regs::IcClrTxOver, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(76usize) as _) }
+    }
+    #[doc = "Clear RD_REQ Interrupt Register"]
+    #[inline(always)]
+    pub const fn ic_clr_rd_req(self) -> crate::common::Reg<regs::IcClrRdReq, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(80usize) as _) }
+    }
+    #[doc = "Clear TX_ABRT Interrupt Register"]
+    #[inline(always)]
+    pub const fn ic_clr_tx_abrt(self) -> crate::common::Reg<regs::IcClrTxAbrt, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(84usize) as _) }
+    }
+    #[doc = "Clear RX_DONE Interrupt Register"]
+    #[inline(always)]
+    pub const fn ic_clr_rx_done(self) -> crate::common::Reg<regs::IcClrRxDone, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(88usize) as _) }
+    }
+    #[doc = "Clear ACTIVITY Interrupt Register"]
+    #[inline(always)]
+    pub const fn ic_clr_activity(
+        self,
+    ) -> crate::common::Reg<regs::IcClrActivity, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(92usize) as _) }
+    }
+    #[doc = "Clear STOP_DET Interrupt Register"]
+    #[inline(always)]
+    pub const fn ic_clr_stop_det(
+        self,
+    ) -> crate::common::Reg<regs::IcClrStopDet, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(96usize) as _) }
+    }
+    #[doc = "Clear START_DET Interrupt Register"]
+    #[inline(always)]
+    pub const fn ic_clr_start_det(
+        self,
+    ) -> crate::common::Reg<regs::IcClrStartDet, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(100usize) as _) }
+    }
+    #[doc = "Clear GEN_CALL Interrupt Register"]
+    #[inline(always)]
+    pub const fn ic_clr_gen_call(
+        self,
+    ) -> crate::common::Reg<regs::IcClrGenCall, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(104usize) as _) }
+    }
+    #[doc = "I2C Enable Register"]
+    #[inline(always)]
+    pub const fn ic_enable(self) -> crate::common::Reg<regs::IcEnable, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(108usize) as _) }
+    }
+    #[doc = "I2C Status Register This is a read-only register used to indicate the current transfer status and FIFO status. The status register may be read at any time. None of the bits in this register request an interrupt. When the I2C is disabled by writing 0 in bit 0 of the IC_ENABLE register: - Bits 1 and 2 are set to 1 - Bits 3 and 10 are set to 0 When the master or slave state machines goes to idle and ic_en=0: - Bits 5 and 6 are set to 0"]
+    #[inline(always)]
+    pub const fn ic_status(self) -> crate::common::Reg<regs::IcStatus, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(112usize) as _) }
+    }
+    #[doc = "I2C Transmit FIFO Level Register This register contains the number of valid data entries in the transmit FIFO buffer. It is cleared whenever: - The I2C is disabled - There is a transmit abort - that is, TX_ABRT bit is set in the IC_RAW_INTR_STAT register - The slave bulk transmit mode is aborted The register increments whenever data is placed into the transmit FIFO and decrements when data is taken from the transmit FIFO."]
+    #[inline(always)]
+    pub const fn ic_txflr(self) -> crate::common::Reg<regs::IcTxflr, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(116usize) as _) }
+    }
+    #[doc = "I2C Receive FIFO Level Register This register contains the number of valid data entries in the receive FIFO buffer. It is cleared whenever: - The I2C is disabled - Whenever there is a transmit abort caused by any of the events tracked in IC_TX_ABRT_SOURCE The register increments whenever data is placed into the receive FIFO and decrements when data is taken from the receive FIFO."]
+    #[inline(always)]
+    pub const fn ic_rxflr(self) -> crate::common::Reg<regs::IcRxflr, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(120usize) as _) }
+    }
+    #[doc = "I2C SDA Hold Time Length Register The bits \\[15:0\\] of this register are used to control the hold time of SDA during transmit in both slave and master mode (after SCL goes from HIGH to LOW). The bits \\[23:16\\] of this register are used to extend the SDA transition (if any) whenever SCL is HIGH in the receiver in either master or slave mode. Writes to this register succeed only when IC_ENABLE\\[0\\]=0. The values in this register are in units of ic_clk period. The value programmed in IC_SDA_TX_HOLD must be greater than the minimum hold time in each mode (one cycle in master mode, seven cycles in slave mode) for the value to be implemented. The programmed SDA hold time during transmit (IC_SDA_TX_HOLD) cannot exceed at any time the duration of the low part of scl. Therefore the programmed value cannot be larger than N_SCL_LOW-2, where N_SCL_LOW is the duration of the low part of the scl period measured in ic_clk cycles."]
+    #[inline(always)]
+    pub const fn ic_sda_hold(self) -> crate::common::Reg<regs::IcSdaHold, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(124usize) as _) }
+    }
+    #[doc = "I2C Transmit Abort Source Register This register has 32 bits that indicate the source of the TX_ABRT bit. Except for Bit 9, this register is cleared whenever the IC_CLR_TX_ABRT register or the IC_CLR_INTR register is read. To clear Bit 9, the source of the ABRT_SBYTE_NORSTRT must be fixed first; RESTART must be enabled (IC_CON\\[5\\]=1), the SPECIAL bit must be cleared (IC_TAR\\[11\\]), or the GC_OR_START bit must be cleared (IC_TAR\\[10\\]). Once the source of the ABRT_SBYTE_NORSTRT is fixed, then this bit can be cleared in the same manner as other bits in this register. If the source of the ABRT_SBYTE_NORSTRT is not fixed before attempting to clear this bit, Bit 9 clears for one cycle and is then re-asserted."]
+    #[inline(always)]
+    pub const fn ic_tx_abrt_source(
+        self,
+    ) -> crate::common::Reg<regs::IcTxAbrtSource, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(128usize) as _) }
+    }
+    #[doc = "Generate Slave Data NACK Register The register is used to generate a NACK for the data part of a transfer when DW_apb_i2c is acting as a slave-receiver. This register only exists when the IC_SLV_DATA_NACK_ONLY parameter is set to 1. When this parameter disabled, this register does not exist and writing to the register's address has no effect. A write can occur on this register if both of the following conditions are met: - DW_apb_i2c is disabled (IC_ENABLE\\[0\\] = 0) - Slave part is inactive (IC_STATUS\\[6\\] = 0) Note: The IC_STATUS\\[6\\] is a register read-back location for the internal slv_activity signal; the user should poll this before writing the ic_slv_data_nack_only bit."]
+    #[inline(always)]
+    pub const fn ic_slv_data_nack_only(
+        self,
+    ) -> crate::common::Reg<regs::IcSlvDataNackOnly, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(132usize) as _) }
+    }
+    #[doc = "DMA Control Register The register is used to enable the DMA Controller interface operation. There is a separate bit for transmit and receive. This can be programmed regardless of the state of IC_ENABLE."]
+    #[inline(always)]
+    pub const fn ic_dma_cr(self) -> crate::common::Reg<regs::IcDmaCr, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(136usize) as _) }
+    }
+    #[doc = "DMA Transmit Data Level Register"]
+    #[inline(always)]
+    pub const fn ic_dma_tdlr(self) -> crate::common::Reg<regs::IcDmaTdlr, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(140usize) as _) }
+    }
+    #[doc = "I2C Receive Data Level Register"]
+    #[inline(always)]
+    pub const fn ic_dma_rdlr(self) -> crate::common::Reg<regs::IcDmaRdlr, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(144usize) as _) }
+    }
+    #[doc = "I2C SDA Setup Register This register controls the amount of time delay (in terms of number of ic_clk clock periods) introduced in the rising edge of SCL - relative to SDA changing - when DW_apb_i2c services a read request in a slave-transmitter operation. The relevant I2C requirement is tSU:DAT (note 4) as detailed in the I2C Bus Specification. This register must be programmed with a value equal to or greater than 2. Writes to this register succeed only when IC_ENABLE\\[0\\] = 0. Note: The length of setup time is calculated using \\[(IC_SDA_SETUP - 1) * (ic_clk_period)\\], so if the user requires 10 ic_clk periods of setup time, they should program a value of 11. The IC_SDA_SETUP register is only used by the DW_apb_i2c when operating as a slave transmitter."]
+    #[inline(always)]
+    pub const fn ic_sda_setup(self) -> crate::common::Reg<regs::IcSdaSetup, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(148usize) as _) }
+    }
+    #[doc = "I2C ACK General Call Register The register controls whether DW_apb_i2c responds with a ACK or NACK when it receives an I2C General Call address. This register is applicable only when the DW_apb_i2c is in slave mode."]
+    #[inline(always)]
+    pub const fn ic_ack_general_call(
+        self,
+    ) -> crate::common::Reg<regs::IcAckGeneralCall, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(152usize) as _) }
+    }
+    #[doc = "I2C Enable Status Register The register is used to report the DW_apb_i2c hardware status when the IC_ENABLE\\[0\\] register is set from 1 to 0; that is, when DW_apb_i2c is disabled. If IC_ENABLE\\[0\\] has been set to 1, bits 2:1 are forced to 0, and bit 0 is forced to 1. If IC_ENABLE\\[0\\] has been set to 0, bits 2:1 is only be valid as soon as bit 0 is read as '0'. Note: When IC_ENABLE\\[0\\] has been set to 0, a delay occurs for bit 0 to be read as 0 because disabling the DW_apb_i2c depends on I2C bus activities."]
+    #[inline(always)]
+    pub const fn ic_enable_status(
+        self,
+    ) -> crate::common::Reg<regs::IcEnableStatus, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(156usize) as _) }
+    }
+    #[doc = "I2C SS, FS or FM+ spike suppression limit This register is used to store the duration, measured in ic_clk cycles, of the longest spike that is filtered out by the spike suppression logic when the component is operating in SS, FS or FM+ modes. The relevant I2C requirement is tSP (table 4) as detailed in the I2C Bus Specification. This register must be programmed with a minimum value of 1."]
+    #[inline(always)]
+    pub const fn ic_fs_spklen(self) -> crate::common::Reg<regs::IcFsSpklen, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(160usize) as _) }
+    }
+    #[doc = "Clear RESTART_DET Interrupt Register"]
+    #[inline(always)]
+    pub const fn ic_clr_restart_det(
+        self,
+    ) -> crate::common::Reg<regs::IcClrRestartDet, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(168usize) as _) }
+    }
+    #[doc = "Component Parameter Register 1 Note This register is not implemented and therefore reads as 0. If it was implemented it would be a constant read-only register that contains encoded information about the component's parameter settings. Fields shown below are the settings for those parameters"]
+    #[inline(always)]
+    pub const fn ic_comp_param_1(
+        self,
+    ) -> crate::common::Reg<regs::IcCompParam1, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(244usize) as _) }
+    }
+    #[doc = "I2C Component Version Register"]
+    #[inline(always)]
+    pub const fn ic_comp_version(self) -> crate::common::Reg<u32, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(248usize) as _) }
+    }
+    #[doc = "I2C Component Type Register"]
+    #[inline(always)]
+    pub const fn ic_comp_type(self) -> crate::common::Reg<u32, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(252usize) as _) }
+    }
+}
+pub mod regs;
+pub mod vals;
diff --git a/src/rp2350/i2c/regs.rs b/src/rp2350/i2c/regs.rs
new file mode 100644
index 00000000..523318fe
--- /dev/null
+++ b/src/rp2350/i2c/regs.rs
@@ -0,0 +1,1877 @@
+#[doc = "I2C ACK General Call Register The register controls whether DW_apb_i2c responds with a ACK or NACK when it receives an I2C General Call address. This register is applicable only when the DW_apb_i2c is in slave mode."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct IcAckGeneralCall(pub u32);
+impl IcAckGeneralCall {
+    #[doc = "ACK General Call. When set to 1, DW_apb_i2c responds with a ACK (by asserting ic_data_oe) when it receives a General Call. Otherwise, DW_apb_i2c responds with a NACK (by negating ic_data_oe)."]
+    #[inline(always)]
+    pub const fn ack_gen_call(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "ACK General Call. When set to 1, DW_apb_i2c responds with a ACK (by asserting ic_data_oe) when it receives a General Call. Otherwise, DW_apb_i2c responds with a NACK (by negating ic_data_oe)."]
+    #[inline(always)]
+    pub fn set_ack_gen_call(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+}
+impl Default for IcAckGeneralCall {
+    #[inline(always)]
+    fn default() -> IcAckGeneralCall {
+        IcAckGeneralCall(0)
+    }
+}
+#[doc = "Clear ACTIVITY Interrupt Register"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct IcClrActivity(pub u32);
+impl IcClrActivity {
+    #[doc = "Reading this register clears the ACTIVITY interrupt if the I2C is not active anymore. If the I2C module is still active on the bus, the ACTIVITY interrupt bit continues to be set. It is automatically cleared by hardware if the module is disabled and if there is no further activity on the bus. The value read from this register to get status of the ACTIVITY interrupt (bit 8) of the IC_RAW_INTR_STAT register. Reset value: 0x0"]
+    #[inline(always)]
+    pub const fn clr_activity(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Reading this register clears the ACTIVITY interrupt if the I2C is not active anymore. If the I2C module is still active on the bus, the ACTIVITY interrupt bit continues to be set. It is automatically cleared by hardware if the module is disabled and if there is no further activity on the bus. The value read from this register to get status of the ACTIVITY interrupt (bit 8) of the IC_RAW_INTR_STAT register. Reset value: 0x0"]
+    #[inline(always)]
+    pub fn set_clr_activity(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+}
+impl Default for IcClrActivity {
+    #[inline(always)]
+    fn default() -> IcClrActivity {
+        IcClrActivity(0)
+    }
+}
+#[doc = "Clear GEN_CALL Interrupt Register"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct IcClrGenCall(pub u32);
+impl IcClrGenCall {
+    #[doc = "Read this register to clear the GEN_CALL interrupt (bit 11) of IC_RAW_INTR_STAT register. Reset value: 0x0"]
+    #[inline(always)]
+    pub const fn clr_gen_call(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Read this register to clear the GEN_CALL interrupt (bit 11) of IC_RAW_INTR_STAT register. Reset value: 0x0"]
+    #[inline(always)]
+    pub fn set_clr_gen_call(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+}
+impl Default for IcClrGenCall {
+    #[inline(always)]
+    fn default() -> IcClrGenCall {
+        IcClrGenCall(0)
+    }
+}
+#[doc = "Clear Combined and Individual Interrupt Register"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct IcClrIntr(pub u32);
+impl IcClrIntr {
+    #[doc = "Read this register to clear the combined interrupt, all individual interrupts, and the IC_TX_ABRT_SOURCE register. This bit does not clear hardware clearable interrupts but software clearable interrupts. Refer to Bit 9 of the IC_TX_ABRT_SOURCE register for an exception to clearing IC_TX_ABRT_SOURCE. Reset value: 0x0"]
+    #[inline(always)]
+    pub const fn clr_intr(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Read this register to clear the combined interrupt, all individual interrupts, and the IC_TX_ABRT_SOURCE register. This bit does not clear hardware clearable interrupts but software clearable interrupts. Refer to Bit 9 of the IC_TX_ABRT_SOURCE register for an exception to clearing IC_TX_ABRT_SOURCE. Reset value: 0x0"]
+    #[inline(always)]
+    pub fn set_clr_intr(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+}
+impl Default for IcClrIntr {
+    #[inline(always)]
+    fn default() -> IcClrIntr {
+        IcClrIntr(0)
+    }
+}
+#[doc = "Clear RD_REQ Interrupt Register"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct IcClrRdReq(pub u32);
+impl IcClrRdReq {
+    #[doc = "Read this register to clear the RD_REQ interrupt (bit 5) of the IC_RAW_INTR_STAT register. Reset value: 0x0"]
+    #[inline(always)]
+    pub const fn clr_rd_req(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Read this register to clear the RD_REQ interrupt (bit 5) of the IC_RAW_INTR_STAT register. Reset value: 0x0"]
+    #[inline(always)]
+    pub fn set_clr_rd_req(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+}
+impl Default for IcClrRdReq {
+    #[inline(always)]
+    fn default() -> IcClrRdReq {
+        IcClrRdReq(0)
+    }
+}
+#[doc = "Clear RESTART_DET Interrupt Register"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct IcClrRestartDet(pub u32);
+impl IcClrRestartDet {
+    #[doc = "Read this register to clear the RESTART_DET interrupt (bit 12) of IC_RAW_INTR_STAT register. Reset value: 0x0"]
+    #[inline(always)]
+    pub const fn clr_restart_det(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Read this register to clear the RESTART_DET interrupt (bit 12) of IC_RAW_INTR_STAT register. Reset value: 0x0"]
+    #[inline(always)]
+    pub fn set_clr_restart_det(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+}
+impl Default for IcClrRestartDet {
+    #[inline(always)]
+    fn default() -> IcClrRestartDet {
+        IcClrRestartDet(0)
+    }
+}
+#[doc = "Clear RX_DONE Interrupt Register"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct IcClrRxDone(pub u32);
+impl IcClrRxDone {
+    #[doc = "Read this register to clear the RX_DONE interrupt (bit 7) of the IC_RAW_INTR_STAT register. Reset value: 0x0"]
+    #[inline(always)]
+    pub const fn clr_rx_done(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Read this register to clear the RX_DONE interrupt (bit 7) of the IC_RAW_INTR_STAT register. Reset value: 0x0"]
+    #[inline(always)]
+    pub fn set_clr_rx_done(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+}
+impl Default for IcClrRxDone {
+    #[inline(always)]
+    fn default() -> IcClrRxDone {
+        IcClrRxDone(0)
+    }
+}
+#[doc = "Clear RX_OVER Interrupt Register"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct IcClrRxOver(pub u32);
+impl IcClrRxOver {
+    #[doc = "Read this register to clear the RX_OVER interrupt (bit 1) of the IC_RAW_INTR_STAT register. Reset value: 0x0"]
+    #[inline(always)]
+    pub const fn clr_rx_over(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Read this register to clear the RX_OVER interrupt (bit 1) of the IC_RAW_INTR_STAT register. Reset value: 0x0"]
+    #[inline(always)]
+    pub fn set_clr_rx_over(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+}
+impl Default for IcClrRxOver {
+    #[inline(always)]
+    fn default() -> IcClrRxOver {
+        IcClrRxOver(0)
+    }
+}
+#[doc = "Clear RX_UNDER Interrupt Register"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct IcClrRxUnder(pub u32);
+impl IcClrRxUnder {
+    #[doc = "Read this register to clear the RX_UNDER interrupt (bit 0) of the IC_RAW_INTR_STAT register. Reset value: 0x0"]
+    #[inline(always)]
+    pub const fn clr_rx_under(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Read this register to clear the RX_UNDER interrupt (bit 0) of the IC_RAW_INTR_STAT register. Reset value: 0x0"]
+    #[inline(always)]
+    pub fn set_clr_rx_under(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+}
+impl Default for IcClrRxUnder {
+    #[inline(always)]
+    fn default() -> IcClrRxUnder {
+        IcClrRxUnder(0)
+    }
+}
+#[doc = "Clear START_DET Interrupt Register"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct IcClrStartDet(pub u32);
+impl IcClrStartDet {
+    #[doc = "Read this register to clear the START_DET interrupt (bit 10) of the IC_RAW_INTR_STAT register. Reset value: 0x0"]
+    #[inline(always)]
+    pub const fn clr_start_det(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Read this register to clear the START_DET interrupt (bit 10) of the IC_RAW_INTR_STAT register. Reset value: 0x0"]
+    #[inline(always)]
+    pub fn set_clr_start_det(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+}
+impl Default for IcClrStartDet {
+    #[inline(always)]
+    fn default() -> IcClrStartDet {
+        IcClrStartDet(0)
+    }
+}
+#[doc = "Clear STOP_DET Interrupt Register"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct IcClrStopDet(pub u32);
+impl IcClrStopDet {
+    #[doc = "Read this register to clear the STOP_DET interrupt (bit 9) of the IC_RAW_INTR_STAT register. Reset value: 0x0"]
+    #[inline(always)]
+    pub const fn clr_stop_det(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Read this register to clear the STOP_DET interrupt (bit 9) of the IC_RAW_INTR_STAT register. Reset value: 0x0"]
+    #[inline(always)]
+    pub fn set_clr_stop_det(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+}
+impl Default for IcClrStopDet {
+    #[inline(always)]
+    fn default() -> IcClrStopDet {
+        IcClrStopDet(0)
+    }
+}
+#[doc = "Clear TX_ABRT Interrupt Register"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct IcClrTxAbrt(pub u32);
+impl IcClrTxAbrt {
+    #[doc = "Read this register to clear the TX_ABRT interrupt (bit 6) of the IC_RAW_INTR_STAT register, and the IC_TX_ABRT_SOURCE register. This also releases the TX FIFO from the flushed/reset state, allowing more writes to the TX FIFO. Refer to Bit 9 of the IC_TX_ABRT_SOURCE register for an exception to clearing IC_TX_ABRT_SOURCE. Reset value: 0x0"]
+    #[inline(always)]
+    pub const fn clr_tx_abrt(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Read this register to clear the TX_ABRT interrupt (bit 6) of the IC_RAW_INTR_STAT register, and the IC_TX_ABRT_SOURCE register. This also releases the TX FIFO from the flushed/reset state, allowing more writes to the TX FIFO. Refer to Bit 9 of the IC_TX_ABRT_SOURCE register for an exception to clearing IC_TX_ABRT_SOURCE. Reset value: 0x0"]
+    #[inline(always)]
+    pub fn set_clr_tx_abrt(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+}
+impl Default for IcClrTxAbrt {
+    #[inline(always)]
+    fn default() -> IcClrTxAbrt {
+        IcClrTxAbrt(0)
+    }
+}
+#[doc = "Clear TX_OVER Interrupt Register"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct IcClrTxOver(pub u32);
+impl IcClrTxOver {
+    #[doc = "Read this register to clear the TX_OVER interrupt (bit 3) of the IC_RAW_INTR_STAT register. Reset value: 0x0"]
+    #[inline(always)]
+    pub const fn clr_tx_over(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Read this register to clear the TX_OVER interrupt (bit 3) of the IC_RAW_INTR_STAT register. Reset value: 0x0"]
+    #[inline(always)]
+    pub fn set_clr_tx_over(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+}
+impl Default for IcClrTxOver {
+    #[inline(always)]
+    fn default() -> IcClrTxOver {
+        IcClrTxOver(0)
+    }
+}
+#[doc = "Component Parameter Register 1 Note This register is not implemented and therefore reads as 0. If it was implemented it would be a constant read-only register that contains encoded information about the component's parameter settings. Fields shown below are the settings for those parameters"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct IcCompParam1(pub u32);
+impl IcCompParam1 {
+    #[doc = "APB data bus width is 32 bits"]
+    #[inline(always)]
+    pub const fn apb_data_width(&self) -> u8 {
+        let val = (self.0 >> 0usize) & 0x03;
+        val as u8
+    }
+    #[doc = "APB data bus width is 32 bits"]
+    #[inline(always)]
+    pub fn set_apb_data_width(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x03 << 0usize)) | (((val as u32) & 0x03) << 0usize);
+    }
+    #[doc = "MAX SPEED MODE = FAST MODE"]
+    #[inline(always)]
+    pub const fn max_speed_mode(&self) -> u8 {
+        let val = (self.0 >> 2usize) & 0x03;
+        val as u8
+    }
+    #[doc = "MAX SPEED MODE = FAST MODE"]
+    #[inline(always)]
+    pub fn set_max_speed_mode(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x03 << 2usize)) | (((val as u32) & 0x03) << 2usize);
+    }
+    #[doc = "Programmable count values for each mode."]
+    #[inline(always)]
+    pub const fn hc_count_values(&self) -> bool {
+        let val = (self.0 >> 4usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Programmable count values for each mode."]
+    #[inline(always)]
+    pub fn set_hc_count_values(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
+    }
+    #[doc = "COMBINED Interrupt outputs"]
+    #[inline(always)]
+    pub const fn intr_io(&self) -> bool {
+        let val = (self.0 >> 5usize) & 0x01;
+        val != 0
+    }
+    #[doc = "COMBINED Interrupt outputs"]
+    #[inline(always)]
+    pub fn set_intr_io(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
+    }
+    #[doc = "DMA handshaking signals are enabled"]
+    #[inline(always)]
+    pub const fn has_dma(&self) -> bool {
+        let val = (self.0 >> 6usize) & 0x01;
+        val != 0
+    }
+    #[doc = "DMA handshaking signals are enabled"]
+    #[inline(always)]
+    pub fn set_has_dma(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
+    }
+    #[doc = "Encoded parameters not visible"]
+    #[inline(always)]
+    pub const fn add_encoded_params(&self) -> bool {
+        let val = (self.0 >> 7usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Encoded parameters not visible"]
+    #[inline(always)]
+    pub fn set_add_encoded_params(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
+    }
+    #[doc = "RX Buffer Depth = 16"]
+    #[inline(always)]
+    pub const fn rx_buffer_depth(&self) -> u8 {
+        let val = (self.0 >> 8usize) & 0xff;
+        val as u8
+    }
+    #[doc = "RX Buffer Depth = 16"]
+    #[inline(always)]
+    pub fn set_rx_buffer_depth(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize);
+    }
+    #[doc = "TX Buffer Depth = 16"]
+    #[inline(always)]
+    pub const fn tx_buffer_depth(&self) -> u8 {
+        let val = (self.0 >> 16usize) & 0xff;
+        val as u8
+    }
+    #[doc = "TX Buffer Depth = 16"]
+    #[inline(always)]
+    pub fn set_tx_buffer_depth(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize);
+    }
+}
+impl Default for IcCompParam1 {
+    #[inline(always)]
+    fn default() -> IcCompParam1 {
+        IcCompParam1(0)
+    }
+}
+#[doc = "I2C Control Register. This register can be written only when the DW_apb_i2c is disabled, which corresponds to the IC_ENABLE\\[0\\] register being set to 0. Writes at other times have no effect. Read/Write Access: - bit 10 is read only. - bit 11 is read only - bit 16 is read only - bit 17 is read only - bits 18 and 19 are read only."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct IcCon(pub u32);
+impl IcCon {
+    #[doc = "This bit controls whether the DW_apb_i2c master is enabled. NOTE: Software should ensure that if this bit is written with '1' then bit 6 should also be written with a '1'."]
+    #[inline(always)]
+    pub const fn master_mode(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "This bit controls whether the DW_apb_i2c master is enabled. NOTE: Software should ensure that if this bit is written with '1' then bit 6 should also be written with a '1'."]
+    #[inline(always)]
+    pub fn set_master_mode(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[doc = "These bits control at which speed the DW_apb_i2c operates; its setting is relevant only if one is operating the DW_apb_i2c in master mode. Hardware protects against illegal values being programmed by software. These bits must be programmed appropriately for slave mode also, as it is used to capture correct value of spike filter as per the speed mode. This register should be programmed only with a value in the range of 1 to IC_MAX_SPEED_MODE; otherwise, hardware updates this register with the value of IC_MAX_SPEED_MODE. 1: standard mode (100 kbit/s) 2: fast mode (<=400 kbit/s) or fast mode plus (<=1000Kbit/s) 3: high speed mode (3.4 Mbit/s) Note: This field is not applicable when IC_ULTRA_FAST_MODE=1"]
+    #[inline(always)]
+    pub const fn speed(&self) -> super::vals::Speed {
+        let val = (self.0 >> 1usize) & 0x03;
+        super::vals::Speed::from_bits(val as u8)
+    }
+    #[doc = "These bits control at which speed the DW_apb_i2c operates; its setting is relevant only if one is operating the DW_apb_i2c in master mode. Hardware protects against illegal values being programmed by software. These bits must be programmed appropriately for slave mode also, as it is used to capture correct value of spike filter as per the speed mode. This register should be programmed only with a value in the range of 1 to IC_MAX_SPEED_MODE; otherwise, hardware updates this register with the value of IC_MAX_SPEED_MODE. 1: standard mode (100 kbit/s) 2: fast mode (<=400 kbit/s) or fast mode plus (<=1000Kbit/s) 3: high speed mode (3.4 Mbit/s) Note: This field is not applicable when IC_ULTRA_FAST_MODE=1"]
+    #[inline(always)]
+    pub fn set_speed(&mut self, val: super::vals::Speed) {
+        self.0 = (self.0 & !(0x03 << 1usize)) | (((val.to_bits() as u32) & 0x03) << 1usize);
+    }
+    #[doc = "When acting as a slave, this bit controls whether the DW_apb_i2c responds to 7- or 10-bit addresses. - 0: 7-bit addressing. The DW_apb_i2c ignores transactions that involve 10-bit addressing; for 7-bit addressing, only the lower 7 bits of the IC_SAR register are compared. - 1: 10-bit addressing. The DW_apb_i2c responds to only 10-bit addressing transfers that match the full 10 bits of the IC_SAR register."]
+    #[inline(always)]
+    pub const fn ic_10bitaddr_slave(&self) -> bool {
+        let val = (self.0 >> 3usize) & 0x01;
+        val != 0
+    }
+    #[doc = "When acting as a slave, this bit controls whether the DW_apb_i2c responds to 7- or 10-bit addresses. - 0: 7-bit addressing. The DW_apb_i2c ignores transactions that involve 10-bit addressing; for 7-bit addressing, only the lower 7 bits of the IC_SAR register are compared. - 1: 10-bit addressing. The DW_apb_i2c responds to only 10-bit addressing transfers that match the full 10 bits of the IC_SAR register."]
+    #[inline(always)]
+    pub fn set_ic_10bitaddr_slave(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
+    }
+    #[doc = "Controls whether the DW_apb_i2c starts its transfers in 7- or 10-bit addressing mode when acting as a master. - 0: 7-bit addressing - 1: 10-bit addressing"]
+    #[inline(always)]
+    pub const fn ic_10bitaddr_master(&self) -> bool {
+        let val = (self.0 >> 4usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Controls whether the DW_apb_i2c starts its transfers in 7- or 10-bit addressing mode when acting as a master. - 0: 7-bit addressing - 1: 10-bit addressing"]
+    #[inline(always)]
+    pub fn set_ic_10bitaddr_master(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
+    }
+    #[doc = "Determines whether RESTART conditions may be sent when acting as a master. Some older slaves do not support handling RESTART conditions; however, RESTART conditions are used in several DW_apb_i2c operations. When RESTART is disabled, the master is prohibited from performing the following functions: - Sending a START BYTE - Performing any high-speed mode operation - High-speed mode operation - Performing direction changes in combined format mode - Performing a read operation with a 10-bit address By replacing RESTART condition followed by a STOP and a subsequent START condition, split operations are broken down into multiple DW_apb_i2c transfers. If the above operations are performed, it will result in setting bit 6 (TX_ABRT) of the IC_RAW_INTR_STAT register. Reset value: ENABLED"]
+    #[inline(always)]
+    pub const fn ic_restart_en(&self) -> bool {
+        let val = (self.0 >> 5usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Determines whether RESTART conditions may be sent when acting as a master. Some older slaves do not support handling RESTART conditions; however, RESTART conditions are used in several DW_apb_i2c operations. When RESTART is disabled, the master is prohibited from performing the following functions: - Sending a START BYTE - Performing any high-speed mode operation - High-speed mode operation - Performing direction changes in combined format mode - Performing a read operation with a 10-bit address By replacing RESTART condition followed by a STOP and a subsequent START condition, split operations are broken down into multiple DW_apb_i2c transfers. If the above operations are performed, it will result in setting bit 6 (TX_ABRT) of the IC_RAW_INTR_STAT register. Reset value: ENABLED"]
+    #[inline(always)]
+    pub fn set_ic_restart_en(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
+    }
+    #[doc = "This bit controls whether I2C has its slave disabled, which means once the presetn signal is applied, then this bit is set and the slave is disabled. If this bit is set (slave is disabled), DW_apb_i2c functions only as a master and does not perform any action that requires a slave. NOTE: Software should ensure that if this bit is written with 0, then bit 0 should also be written with a 0."]
+    #[inline(always)]
+    pub const fn ic_slave_disable(&self) -> bool {
+        let val = (self.0 >> 6usize) & 0x01;
+        val != 0
+    }
+    #[doc = "This bit controls whether I2C has its slave disabled, which means once the presetn signal is applied, then this bit is set and the slave is disabled. If this bit is set (slave is disabled), DW_apb_i2c functions only as a master and does not perform any action that requires a slave. NOTE: Software should ensure that if this bit is written with 0, then bit 0 should also be written with a 0."]
+    #[inline(always)]
+    pub fn set_ic_slave_disable(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
+    }
+    #[doc = "In slave mode: - 1'b1: issues the STOP_DET interrupt only when it is addressed. - 1'b0: issues the STOP_DET irrespective of whether it's addressed or not. Reset value: 0x0 NOTE: During a general call address, this slave does not issue the STOP_DET interrupt if STOP_DET_IF_ADDRESSED = 1'b1, even if the slave responds to the general call address by generating ACK. The STOP_DET interrupt is generated only when the transmitted address matches the slave address (SAR)."]
+    #[inline(always)]
+    pub const fn stop_det_ifaddressed(&self) -> bool {
+        let val = (self.0 >> 7usize) & 0x01;
+        val != 0
+    }
+    #[doc = "In slave mode: - 1'b1: issues the STOP_DET interrupt only when it is addressed. - 1'b0: issues the STOP_DET irrespective of whether it's addressed or not. Reset value: 0x0 NOTE: During a general call address, this slave does not issue the STOP_DET interrupt if STOP_DET_IF_ADDRESSED = 1'b1, even if the slave responds to the general call address by generating ACK. The STOP_DET interrupt is generated only when the transmitted address matches the slave address (SAR)."]
+    #[inline(always)]
+    pub fn set_stop_det_ifaddressed(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
+    }
+    #[doc = "This bit controls the generation of the TX_EMPTY interrupt, as described in the IC_RAW_INTR_STAT register. Reset value: 0x0."]
+    #[inline(always)]
+    pub const fn tx_empty_ctrl(&self) -> bool {
+        let val = (self.0 >> 8usize) & 0x01;
+        val != 0
+    }
+    #[doc = "This bit controls the generation of the TX_EMPTY interrupt, as described in the IC_RAW_INTR_STAT register. Reset value: 0x0."]
+    #[inline(always)]
+    pub fn set_tx_empty_ctrl(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
+    }
+    #[doc = "This bit controls whether DW_apb_i2c should hold the bus when the Rx FIFO is physically full to its RX_BUFFER_DEPTH, as described in the IC_RX_FULL_HLD_BUS_EN parameter. Reset value: 0x0."]
+    #[inline(always)]
+    pub const fn rx_fifo_full_hld_ctrl(&self) -> bool {
+        let val = (self.0 >> 9usize) & 0x01;
+        val != 0
+    }
+    #[doc = "This bit controls whether DW_apb_i2c should hold the bus when the Rx FIFO is physically full to its RX_BUFFER_DEPTH, as described in the IC_RX_FULL_HLD_BUS_EN parameter. Reset value: 0x0."]
+    #[inline(always)]
+    pub fn set_rx_fifo_full_hld_ctrl(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
+    }
+    #[doc = "Master issues the STOP_DET interrupt irrespective of whether master is active or not"]
+    #[inline(always)]
+    pub const fn stop_det_if_master_active(&self) -> bool {
+        let val = (self.0 >> 10usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Master issues the STOP_DET interrupt irrespective of whether master is active or not"]
+    #[inline(always)]
+    pub fn set_stop_det_if_master_active(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize);
+    }
+}
+impl Default for IcCon {
+    #[inline(always)]
+    fn default() -> IcCon {
+        IcCon(0)
+    }
+}
+#[doc = "I2C Rx/Tx Data Buffer and Command Register; this is the register the CPU writes to when filling the TX FIFO and the CPU reads from when retrieving bytes from RX FIFO. The size of the register changes as follows: Write: - 11 bits when IC_EMPTYFIFO_HOLD_MASTER_EN=1 - 9 bits when IC_EMPTYFIFO_HOLD_MASTER_EN=0 Read: - 12 bits when IC_FIRST_DATA_BYTE_STATUS = 1 - 8 bits when IC_FIRST_DATA_BYTE_STATUS = 0 Note: In order for the DW_apb_i2c to continue acknowledging reads, a read command should be written for every byte that is to be received; otherwise the DW_apb_i2c will stop acknowledging."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct IcDataCmd(pub u32);
+impl IcDataCmd {
+    #[doc = "This register contains the data to be transmitted or received on the I2C bus. If you are writing to this register and want to perform a read, bits 7:0 (DAT) are ignored by the DW_apb_i2c. However, when you read this register, these bits return the value of data received on the DW_apb_i2c interface. Reset value: 0x0"]
+    #[inline(always)]
+    pub const fn dat(&self) -> u8 {
+        let val = (self.0 >> 0usize) & 0xff;
+        val as u8
+    }
+    #[doc = "This register contains the data to be transmitted or received on the I2C bus. If you are writing to this register and want to perform a read, bits 7:0 (DAT) are ignored by the DW_apb_i2c. However, when you read this register, these bits return the value of data received on the DW_apb_i2c interface. Reset value: 0x0"]
+    #[inline(always)]
+    pub fn set_dat(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize);
+    }
+    #[doc = "This bit controls whether a read or a write is performed. This bit does not control the direction when the DW_apb_i2con acts as a slave. It controls only the direction when it acts as a master. When a command is entered in the TX FIFO, this bit distinguishes the write and read commands. In slave-receiver mode, this bit is a 'don't care' because writes to this register are not required. In slave-transmitter mode, a '0' indicates that the data in IC_DATA_CMD is to be transmitted. When programming this bit, you should remember the following: attempting to perform a read operation after a General Call command has been sent results in a TX_ABRT interrupt (bit 6 of the IC_RAW_INTR_STAT register), unless bit 11 (SPECIAL) in the IC_TAR register has been cleared. If a '1' is written to this bit after receiving a RD_REQ interrupt, then a TX_ABRT interrupt occurs. Reset value: 0x0"]
+    #[inline(always)]
+    pub const fn cmd(&self) -> bool {
+        let val = (self.0 >> 8usize) & 0x01;
+        val != 0
+    }
+    #[doc = "This bit controls whether a read or a write is performed. This bit does not control the direction when the DW_apb_i2con acts as a slave. It controls only the direction when it acts as a master. When a command is entered in the TX FIFO, this bit distinguishes the write and read commands. In slave-receiver mode, this bit is a 'don't care' because writes to this register are not required. In slave-transmitter mode, a '0' indicates that the data in IC_DATA_CMD is to be transmitted. When programming this bit, you should remember the following: attempting to perform a read operation after a General Call command has been sent results in a TX_ABRT interrupt (bit 6 of the IC_RAW_INTR_STAT register), unless bit 11 (SPECIAL) in the IC_TAR register has been cleared. If a '1' is written to this bit after receiving a RD_REQ interrupt, then a TX_ABRT interrupt occurs. Reset value: 0x0"]
+    #[inline(always)]
+    pub fn set_cmd(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
+    }
+    #[doc = "This bit controls whether a STOP is issued after the byte is sent or received. - 1 - STOP is issued after this byte, regardless of whether or not the Tx FIFO is empty. If the Tx FIFO is not empty, the master immediately tries to start a new transfer by issuing a START and arbitrating for the bus. - 0 - STOP is not issued after this byte, regardless of whether or not the Tx FIFO is empty. If the Tx FIFO is not empty, the master continues the current transfer by sending/receiving data bytes according to the value of the CMD bit. If the Tx FIFO is empty, the master holds the SCL line low and stalls the bus until a new command is available in the Tx FIFO. Reset value: 0x0"]
+    #[inline(always)]
+    pub const fn stop(&self) -> bool {
+        let val = (self.0 >> 9usize) & 0x01;
+        val != 0
+    }
+    #[doc = "This bit controls whether a STOP is issued after the byte is sent or received. - 1 - STOP is issued after this byte, regardless of whether or not the Tx FIFO is empty. If the Tx FIFO is not empty, the master immediately tries to start a new transfer by issuing a START and arbitrating for the bus. - 0 - STOP is not issued after this byte, regardless of whether or not the Tx FIFO is empty. If the Tx FIFO is not empty, the master continues the current transfer by sending/receiving data bytes according to the value of the CMD bit. If the Tx FIFO is empty, the master holds the SCL line low and stalls the bus until a new command is available in the Tx FIFO. Reset value: 0x0"]
+    #[inline(always)]
+    pub fn set_stop(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
+    }
+    #[doc = "This bit controls whether a RESTART is issued before the byte is sent or received. 1 - If IC_RESTART_EN is 1, a RESTART is issued before the data is sent/received (according to the value of CMD), regardless of whether or not the transfer direction is changing from the previous command; if IC_RESTART_EN is 0, a STOP followed by a START is issued instead. 0 - If IC_RESTART_EN is 1, a RESTART is issued only if the transfer direction is changing from the previous command; if IC_RESTART_EN is 0, a STOP followed by a START is issued instead. Reset value: 0x0"]
+    #[inline(always)]
+    pub const fn restart(&self) -> bool {
+        let val = (self.0 >> 10usize) & 0x01;
+        val != 0
+    }
+    #[doc = "This bit controls whether a RESTART is issued before the byte is sent or received. 1 - If IC_RESTART_EN is 1, a RESTART is issued before the data is sent/received (according to the value of CMD), regardless of whether or not the transfer direction is changing from the previous command; if IC_RESTART_EN is 0, a STOP followed by a START is issued instead. 0 - If IC_RESTART_EN is 1, a RESTART is issued only if the transfer direction is changing from the previous command; if IC_RESTART_EN is 0, a STOP followed by a START is issued instead. Reset value: 0x0"]
+    #[inline(always)]
+    pub fn set_restart(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize);
+    }
+    #[doc = "Indicates the first data byte received after the address phase for receive transfer in Master receiver or Slave receiver mode. Reset value : 0x0 NOTE: In case of APB_DATA_WIDTH=8, 1. The user has to perform two APB Reads to IC_DATA_CMD in order to get status on 11 bit. 2. In order to read the 11 bit, the user has to perform the first data byte read \\[7:0\\] (offset 0x10) and then perform the second read \\[15:8\\] (offset 0x11) in order to know the status of 11 bit (whether the data received in previous read is a first data byte or not). 3. The 11th bit is an optional read field, user can ignore 2nd byte read \\[15:8\\] (offset 0x11) if not interested in FIRST_DATA_BYTE status."]
+    #[inline(always)]
+    pub const fn first_data_byte(&self) -> bool {
+        let val = (self.0 >> 11usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Indicates the first data byte received after the address phase for receive transfer in Master receiver or Slave receiver mode. Reset value : 0x0 NOTE: In case of APB_DATA_WIDTH=8, 1. The user has to perform two APB Reads to IC_DATA_CMD in order to get status on 11 bit. 2. In order to read the 11 bit, the user has to perform the first data byte read \\[7:0\\] (offset 0x10) and then perform the second read \\[15:8\\] (offset 0x11) in order to know the status of 11 bit (whether the data received in previous read is a first data byte or not). 3. The 11th bit is an optional read field, user can ignore 2nd byte read \\[15:8\\] (offset 0x11) if not interested in FIRST_DATA_BYTE status."]
+    #[inline(always)]
+    pub fn set_first_data_byte(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
+    }
+}
+impl Default for IcDataCmd {
+    #[inline(always)]
+    fn default() -> IcDataCmd {
+        IcDataCmd(0)
+    }
+}
+#[doc = "DMA Control Register The register is used to enable the DMA Controller interface operation. There is a separate bit for transmit and receive. This can be programmed regardless of the state of IC_ENABLE."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct IcDmaCr(pub u32);
+impl IcDmaCr {
+    #[doc = "Receive DMA Enable. This bit enables/disables the receive FIFO DMA channel. Reset value: 0x0"]
+    #[inline(always)]
+    pub const fn rdmae(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Receive DMA Enable. This bit enables/disables the receive FIFO DMA channel. Reset value: 0x0"]
+    #[inline(always)]
+    pub fn set_rdmae(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[doc = "Transmit DMA Enable. This bit enables/disables the transmit FIFO DMA channel. Reset value: 0x0"]
+    #[inline(always)]
+    pub const fn tdmae(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Transmit DMA Enable. This bit enables/disables the transmit FIFO DMA channel. Reset value: 0x0"]
+    #[inline(always)]
+    pub fn set_tdmae(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+}
+impl Default for IcDmaCr {
+    #[inline(always)]
+    fn default() -> IcDmaCr {
+        IcDmaCr(0)
+    }
+}
+#[doc = "I2C Receive Data Level Register"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct IcDmaRdlr(pub u32);
+impl IcDmaRdlr {
+    #[doc = "Receive Data Level. This bit field controls the level at which a DMA request is made by the receive logic. The watermark level = DMARDL+1; that is, dma_rx_req is generated when the number of valid data entries in the receive FIFO is equal to or more than this field value + 1, and RDMAE =1. For instance, when DMARDL is 0, then dma_rx_req is asserted when 1 or more data entries are present in the receive FIFO. Reset value: 0x0"]
+    #[inline(always)]
+    pub const fn dmardl(&self) -> u8 {
+        let val = (self.0 >> 0usize) & 0x0f;
+        val as u8
+    }
+    #[doc = "Receive Data Level. This bit field controls the level at which a DMA request is made by the receive logic. The watermark level = DMARDL+1; that is, dma_rx_req is generated when the number of valid data entries in the receive FIFO is equal to or more than this field value + 1, and RDMAE =1. For instance, when DMARDL is 0, then dma_rx_req is asserted when 1 or more data entries are present in the receive FIFO. Reset value: 0x0"]
+    #[inline(always)]
+    pub fn set_dmardl(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize);
+    }
+}
+impl Default for IcDmaRdlr {
+    #[inline(always)]
+    fn default() -> IcDmaRdlr {
+        IcDmaRdlr(0)
+    }
+}
+#[doc = "DMA Transmit Data Level Register"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct IcDmaTdlr(pub u32);
+impl IcDmaTdlr {
+    #[doc = "Transmit Data Level. This bit field controls the level at which a DMA request is made by the transmit logic. It is equal to the watermark level; that is, the dma_tx_req signal is generated when the number of valid data entries in the transmit FIFO is equal to or below this field value, and TDMAE = 1. Reset value: 0x0"]
+    #[inline(always)]
+    pub const fn dmatdl(&self) -> u8 {
+        let val = (self.0 >> 0usize) & 0x0f;
+        val as u8
+    }
+    #[doc = "Transmit Data Level. This bit field controls the level at which a DMA request is made by the transmit logic. It is equal to the watermark level; that is, the dma_tx_req signal is generated when the number of valid data entries in the transmit FIFO is equal to or below this field value, and TDMAE = 1. Reset value: 0x0"]
+    #[inline(always)]
+    pub fn set_dmatdl(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize);
+    }
+}
+impl Default for IcDmaTdlr {
+    #[inline(always)]
+    fn default() -> IcDmaTdlr {
+        IcDmaTdlr(0)
+    }
+}
+#[doc = "I2C Enable Register"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct IcEnable(pub u32);
+impl IcEnable {
+    #[doc = "Controls whether the DW_apb_i2c is enabled. - 0: Disables DW_apb_i2c (TX and RX FIFOs are held in an erased state) - 1: Enables DW_apb_i2c Software can disable DW_apb_i2c while it is active. However, it is important that care be taken to ensure that DW_apb_i2c is disabled properly. A recommended procedure is described in 'Disabling DW_apb_i2c'. When DW_apb_i2c is disabled, the following occurs: - The TX FIFO and RX FIFO get flushed. - Status bits in the IC_INTR_STAT register are still active until DW_apb_i2c goes into IDLE state. If the module is transmitting, it stops as well as deletes the contents of the transmit buffer after the current transfer is complete. If the module is receiving, the DW_apb_i2c stops the current transfer at the end of the current byte and does not acknowledge the transfer. In systems with asynchronous pclk and ic_clk when IC_CLK_TYPE parameter set to asynchronous (1), there is a two ic_clk delay when enabling or disabling the DW_apb_i2c. For a detailed description on how to disable DW_apb_i2c, refer to 'Disabling DW_apb_i2c' Reset value: 0x0"]
+    #[inline(always)]
+    pub const fn enable(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Controls whether the DW_apb_i2c is enabled. - 0: Disables DW_apb_i2c (TX and RX FIFOs are held in an erased state) - 1: Enables DW_apb_i2c Software can disable DW_apb_i2c while it is active. However, it is important that care be taken to ensure that DW_apb_i2c is disabled properly. A recommended procedure is described in 'Disabling DW_apb_i2c'. When DW_apb_i2c is disabled, the following occurs: - The TX FIFO and RX FIFO get flushed. - Status bits in the IC_INTR_STAT register are still active until DW_apb_i2c goes into IDLE state. If the module is transmitting, it stops as well as deletes the contents of the transmit buffer after the current transfer is complete. If the module is receiving, the DW_apb_i2c stops the current transfer at the end of the current byte and does not acknowledge the transfer. In systems with asynchronous pclk and ic_clk when IC_CLK_TYPE parameter set to asynchronous (1), there is a two ic_clk delay when enabling or disabling the DW_apb_i2c. For a detailed description on how to disable DW_apb_i2c, refer to 'Disabling DW_apb_i2c' Reset value: 0x0"]
+    #[inline(always)]
+    pub fn set_enable(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[doc = "When set, the controller initiates the transfer abort. - 0: ABORT not initiated or ABORT done - 1: ABORT operation in progress The software can abort the I2C transfer in master mode by setting this bit. The software can set this bit only when ENABLE is already set; otherwise, the controller ignores any write to ABORT bit. The software cannot clear the ABORT bit once set. In response to an ABORT, the controller issues a STOP and flushes the Tx FIFO after completing the current transfer, then sets the TX_ABORT interrupt after the abort operation. The ABORT bit is cleared automatically after the abort operation. For a detailed description on how to abort I2C transfers, refer to 'Aborting I2C Transfers'. Reset value: 0x0"]
+    #[inline(always)]
+    pub const fn abort(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[doc = "When set, the controller initiates the transfer abort. - 0: ABORT not initiated or ABORT done - 1: ABORT operation in progress The software can abort the I2C transfer in master mode by setting this bit. The software can set this bit only when ENABLE is already set; otherwise, the controller ignores any write to ABORT bit. The software cannot clear the ABORT bit once set. In response to an ABORT, the controller issues a STOP and flushes the Tx FIFO after completing the current transfer, then sets the TX_ABORT interrupt after the abort operation. The ABORT bit is cleared automatically after the abort operation. For a detailed description on how to abort I2C transfers, refer to 'Aborting I2C Transfers'. Reset value: 0x0"]
+    #[inline(always)]
+    pub fn set_abort(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+    #[doc = "In Master mode: - 1'b1: Blocks the transmission of data on I2C bus even if Tx FIFO has data to transmit. - 1'b0: The transmission of data starts on I2C bus automatically, as soon as the first data is available in the Tx FIFO. Note: To block the execution of Master commands, set the TX_CMD_BLOCK bit only when Tx FIFO is empty (IC_STATUS\\[2\\]==1) and Master is in Idle state (IC_STATUS\\[5\\] == 0). Any further commands put in the Tx FIFO are not executed until TX_CMD_BLOCK bit is unset. Reset value: IC_TX_CMD_BLOCK_DEFAULT"]
+    #[inline(always)]
+    pub const fn tx_cmd_block(&self) -> bool {
+        let val = (self.0 >> 2usize) & 0x01;
+        val != 0
+    }
+    #[doc = "In Master mode: - 1'b1: Blocks the transmission of data on I2C bus even if Tx FIFO has data to transmit. - 1'b0: The transmission of data starts on I2C bus automatically, as soon as the first data is available in the Tx FIFO. Note: To block the execution of Master commands, set the TX_CMD_BLOCK bit only when Tx FIFO is empty (IC_STATUS\\[2\\]==1) and Master is in Idle state (IC_STATUS\\[5\\] == 0). Any further commands put in the Tx FIFO are not executed until TX_CMD_BLOCK bit is unset. Reset value: IC_TX_CMD_BLOCK_DEFAULT"]
+    #[inline(always)]
+    pub fn set_tx_cmd_block(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+    }
+}
+impl Default for IcEnable {
+    #[inline(always)]
+    fn default() -> IcEnable {
+        IcEnable(0)
+    }
+}
+#[doc = "I2C Enable Status Register The register is used to report the DW_apb_i2c hardware status when the IC_ENABLE\\[0\\] register is set from 1 to 0; that is, when DW_apb_i2c is disabled. If IC_ENABLE\\[0\\] has been set to 1, bits 2:1 are forced to 0, and bit 0 is forced to 1. If IC_ENABLE\\[0\\] has been set to 0, bits 2:1 is only be valid as soon as bit 0 is read as '0'. Note: When IC_ENABLE\\[0\\] has been set to 0, a delay occurs for bit 0 to be read as 0 because disabling the DW_apb_i2c depends on I2C bus activities."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct IcEnableStatus(pub u32);
+impl IcEnableStatus {
+    #[doc = "ic_en Status. This bit always reflects the value driven on the output port ic_en. - When read as 1, DW_apb_i2c is deemed to be in an enabled state. - When read as 0, DW_apb_i2c is deemed completely inactive. Note: The CPU can safely read this bit anytime. When this bit is read as 0, the CPU can safely read SLV_RX_DATA_LOST (bit 2) and SLV_DISABLED_WHILE_BUSY (bit 1). Reset value: 0x0"]
+    #[inline(always)]
+    pub const fn ic_en(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "ic_en Status. This bit always reflects the value driven on the output port ic_en. - When read as 1, DW_apb_i2c is deemed to be in an enabled state. - When read as 0, DW_apb_i2c is deemed completely inactive. Note: The CPU can safely read this bit anytime. When this bit is read as 0, the CPU can safely read SLV_RX_DATA_LOST (bit 2) and SLV_DISABLED_WHILE_BUSY (bit 1). Reset value: 0x0"]
+    #[inline(always)]
+    pub fn set_ic_en(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[doc = "Slave Disabled While Busy (Transmit, Receive). This bit indicates if a potential or active Slave operation has been aborted due to the setting bit 0 of the IC_ENABLE register from 1 to 0. This bit is set when the CPU writes a 0 to the IC_ENABLE register while: (a) DW_apb_i2c is receiving the address byte of the Slave-Transmitter operation from a remote master; OR, (b) address and data bytes of the Slave-Receiver operation from a remote master. When read as 1, DW_apb_i2c is deemed to have forced a NACK during any part of an I2C transfer, irrespective of whether the I2C address matches the slave address set in DW_apb_i2c (IC_SAR register) OR if the transfer is completed before IC_ENABLE is set to 0 but has not taken effect. Note: If the remote I2C master terminates the transfer with a STOP condition before the DW_apb_i2c has a chance to NACK a transfer, and IC_ENABLE\\[0\\] has been set to 0, then this bit will also be set to 1. When read as 0, DW_apb_i2c is deemed to have been disabled when there is master activity, or when the I2C bus is idle. Note: The CPU can safely read this bit when IC_EN (bit 0) is read as 0. Reset value: 0x0"]
+    #[inline(always)]
+    pub const fn slv_disabled_while_busy(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Slave Disabled While Busy (Transmit, Receive). This bit indicates if a potential or active Slave operation has been aborted due to the setting bit 0 of the IC_ENABLE register from 1 to 0. This bit is set when the CPU writes a 0 to the IC_ENABLE register while: (a) DW_apb_i2c is receiving the address byte of the Slave-Transmitter operation from a remote master; OR, (b) address and data bytes of the Slave-Receiver operation from a remote master. When read as 1, DW_apb_i2c is deemed to have forced a NACK during any part of an I2C transfer, irrespective of whether the I2C address matches the slave address set in DW_apb_i2c (IC_SAR register) OR if the transfer is completed before IC_ENABLE is set to 0 but has not taken effect. Note: If the remote I2C master terminates the transfer with a STOP condition before the DW_apb_i2c has a chance to NACK a transfer, and IC_ENABLE\\[0\\] has been set to 0, then this bit will also be set to 1. When read as 0, DW_apb_i2c is deemed to have been disabled when there is master activity, or when the I2C bus is idle. Note: The CPU can safely read this bit when IC_EN (bit 0) is read as 0. Reset value: 0x0"]
+    #[inline(always)]
+    pub fn set_slv_disabled_while_busy(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+    #[doc = "Slave Received Data Lost. This bit indicates if a Slave-Receiver operation has been aborted with at least one data byte received from an I2C transfer due to the setting bit 0 of IC_ENABLE from 1 to 0. When read as 1, DW_apb_i2c is deemed to have been actively engaged in an aborted I2C transfer (with matching address) and the data phase of the I2C transfer has been entered, even though a data byte has been responded with a NACK. Note: If the remote I2C master terminates the transfer with a STOP condition before the DW_apb_i2c has a chance to NACK a transfer, and IC_ENABLE\\[0\\] has been set to 0, then this bit is also set to 1. When read as 0, DW_apb_i2c is deemed to have been disabled without being actively involved in the data phase of a Slave-Receiver transfer. Note: The CPU can safely read this bit when IC_EN (bit 0) is read as 0. Reset value: 0x0"]
+    #[inline(always)]
+    pub const fn slv_rx_data_lost(&self) -> bool {
+        let val = (self.0 >> 2usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Slave Received Data Lost. This bit indicates if a Slave-Receiver operation has been aborted with at least one data byte received from an I2C transfer due to the setting bit 0 of IC_ENABLE from 1 to 0. When read as 1, DW_apb_i2c is deemed to have been actively engaged in an aborted I2C transfer (with matching address) and the data phase of the I2C transfer has been entered, even though a data byte has been responded with a NACK. Note: If the remote I2C master terminates the transfer with a STOP condition before the DW_apb_i2c has a chance to NACK a transfer, and IC_ENABLE\\[0\\] has been set to 0, then this bit is also set to 1. When read as 0, DW_apb_i2c is deemed to have been disabled without being actively involved in the data phase of a Slave-Receiver transfer. Note: The CPU can safely read this bit when IC_EN (bit 0) is read as 0. Reset value: 0x0"]
+    #[inline(always)]
+    pub fn set_slv_rx_data_lost(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+    }
+}
+impl Default for IcEnableStatus {
+    #[inline(always)]
+    fn default() -> IcEnableStatus {
+        IcEnableStatus(0)
+    }
+}
+#[doc = "Fast Mode or Fast Mode Plus I2C Clock SCL High Count Register"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct IcFsSclHcnt(pub u32);
+impl IcFsSclHcnt {
+    #[doc = "This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock high-period count for fast mode or fast mode plus. It is used in high-speed mode to send the Master Code and START BYTE or General CALL. For more information, refer to 'IC_CLK Frequency Configuration'. This register goes away and becomes read-only returning 0s if IC_MAX_SPEED_MODE = standard. This register can be written only when the I2C interface is disabled, which corresponds to the IC_ENABLE\\[0\\] register being set to 0. Writes at other times have no effect. The minimum valid value is 6; hardware prevents values less than this being written, and if attempted results in 6 being set. For designs with APB_DATA_WIDTH == 8 the order of programming is important to ensure the correct operation of the DW_apb_i2c. The lower byte must be programmed first. Then the upper byte is programmed."]
+    #[inline(always)]
+    pub const fn ic_fs_scl_hcnt(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0xffff;
+        val as u16
+    }
+    #[doc = "This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock high-period count for fast mode or fast mode plus. It is used in high-speed mode to send the Master Code and START BYTE or General CALL. For more information, refer to 'IC_CLK Frequency Configuration'. This register goes away and becomes read-only returning 0s if IC_MAX_SPEED_MODE = standard. This register can be written only when the I2C interface is disabled, which corresponds to the IC_ENABLE\\[0\\] register being set to 0. Writes at other times have no effect. The minimum valid value is 6; hardware prevents values less than this being written, and if attempted results in 6 being set. For designs with APB_DATA_WIDTH == 8 the order of programming is important to ensure the correct operation of the DW_apb_i2c. The lower byte must be programmed first. Then the upper byte is programmed."]
+    #[inline(always)]
+    pub fn set_ic_fs_scl_hcnt(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+    }
+}
+impl Default for IcFsSclHcnt {
+    #[inline(always)]
+    fn default() -> IcFsSclHcnt {
+        IcFsSclHcnt(0)
+    }
+}
+#[doc = "Fast Mode or Fast Mode Plus I2C Clock SCL Low Count Register"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct IcFsSclLcnt(pub u32);
+impl IcFsSclLcnt {
+    #[doc = "This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock low period count for fast speed. It is used in high-speed mode to send the Master Code and START BYTE or General CALL. For more information, refer to 'IC_CLK Frequency Configuration'. This register goes away and becomes read-only returning 0s if IC_MAX_SPEED_MODE = standard. This register can be written only when the I2C interface is disabled, which corresponds to the IC_ENABLE\\[0\\] register being set to 0. Writes at other times have no effect. The minimum valid value is 8; hardware prevents values less than this being written, and if attempted results in 8 being set. For designs with APB_DATA_WIDTH = 8 the order of programming is important to ensure the correct operation of the DW_apb_i2c. The lower byte must be programmed first. Then the upper byte is programmed. If the value is less than 8 then the count value gets changed to 8."]
+    #[inline(always)]
+    pub const fn ic_fs_scl_lcnt(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0xffff;
+        val as u16
+    }
+    #[doc = "This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock low period count for fast speed. It is used in high-speed mode to send the Master Code and START BYTE or General CALL. For more information, refer to 'IC_CLK Frequency Configuration'. This register goes away and becomes read-only returning 0s if IC_MAX_SPEED_MODE = standard. This register can be written only when the I2C interface is disabled, which corresponds to the IC_ENABLE\\[0\\] register being set to 0. Writes at other times have no effect. The minimum valid value is 8; hardware prevents values less than this being written, and if attempted results in 8 being set. For designs with APB_DATA_WIDTH = 8 the order of programming is important to ensure the correct operation of the DW_apb_i2c. The lower byte must be programmed first. Then the upper byte is programmed. If the value is less than 8 then the count value gets changed to 8."]
+    #[inline(always)]
+    pub fn set_ic_fs_scl_lcnt(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+    }
+}
+impl Default for IcFsSclLcnt {
+    #[inline(always)]
+    fn default() -> IcFsSclLcnt {
+        IcFsSclLcnt(0)
+    }
+}
+#[doc = "I2C SS, FS or FM+ spike suppression limit This register is used to store the duration, measured in ic_clk cycles, of the longest spike that is filtered out by the spike suppression logic when the component is operating in SS, FS or FM+ modes. The relevant I2C requirement is tSP (table 4) as detailed in the I2C Bus Specification. This register must be programmed with a minimum value of 1."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct IcFsSpklen(pub u32);
+impl IcFsSpklen {
+    #[doc = "This register must be set before any I2C bus transaction can take place to ensure stable operation. This register sets the duration, measured in ic_clk cycles, of the longest spike in the SCL or SDA lines that will be filtered out by the spike suppression logic. This register can be written only when the I2C interface is disabled which corresponds to the IC_ENABLE\\[0\\] register being set to 0. Writes at other times have no effect. The minimum valid value is 1; hardware prevents values less than this being written, and if attempted results in 1 being set. or more information, refer to 'Spike Suppression'."]
+    #[inline(always)]
+    pub const fn ic_fs_spklen(&self) -> u8 {
+        let val = (self.0 >> 0usize) & 0xff;
+        val as u8
+    }
+    #[doc = "This register must be set before any I2C bus transaction can take place to ensure stable operation. This register sets the duration, measured in ic_clk cycles, of the longest spike in the SCL or SDA lines that will be filtered out by the spike suppression logic. This register can be written only when the I2C interface is disabled which corresponds to the IC_ENABLE\\[0\\] register being set to 0. Writes at other times have no effect. The minimum valid value is 1; hardware prevents values less than this being written, and if attempted results in 1 being set. or more information, refer to 'Spike Suppression'."]
+    #[inline(always)]
+    pub fn set_ic_fs_spklen(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize);
+    }
+}
+impl Default for IcFsSpklen {
+    #[inline(always)]
+    fn default() -> IcFsSpklen {
+        IcFsSpklen(0)
+    }
+}
+#[doc = "I2C Interrupt Mask Register. These bits mask their corresponding interrupt status bits. This register is active low; a value of 0 masks the interrupt, whereas a value of 1 unmasks the interrupt."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct IcIntrMask(pub u32);
+impl IcIntrMask {
+    #[doc = "This bit masks the R_RX_UNDER interrupt in IC_INTR_STAT register. Reset value: 0x1"]
+    #[inline(always)]
+    pub const fn m_rx_under(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "This bit masks the R_RX_UNDER interrupt in IC_INTR_STAT register. Reset value: 0x1"]
+    #[inline(always)]
+    pub fn set_m_rx_under(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[doc = "This bit masks the R_RX_OVER interrupt in IC_INTR_STAT register. Reset value: 0x1"]
+    #[inline(always)]
+    pub const fn m_rx_over(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[doc = "This bit masks the R_RX_OVER interrupt in IC_INTR_STAT register. Reset value: 0x1"]
+    #[inline(always)]
+    pub fn set_m_rx_over(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+    #[doc = "This bit masks the R_RX_FULL interrupt in IC_INTR_STAT register. Reset value: 0x1"]
+    #[inline(always)]
+    pub const fn m_rx_full(&self) -> bool {
+        let val = (self.0 >> 2usize) & 0x01;
+        val != 0
+    }
+    #[doc = "This bit masks the R_RX_FULL interrupt in IC_INTR_STAT register. Reset value: 0x1"]
+    #[inline(always)]
+    pub fn set_m_rx_full(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+    }
+    #[doc = "This bit masks the R_TX_OVER interrupt in IC_INTR_STAT register. Reset value: 0x1"]
+    #[inline(always)]
+    pub const fn m_tx_over(&self) -> bool {
+        let val = (self.0 >> 3usize) & 0x01;
+        val != 0
+    }
+    #[doc = "This bit masks the R_TX_OVER interrupt in IC_INTR_STAT register. Reset value: 0x1"]
+    #[inline(always)]
+    pub fn set_m_tx_over(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
+    }
+    #[doc = "This bit masks the R_TX_EMPTY interrupt in IC_INTR_STAT register. Reset value: 0x1"]
+    #[inline(always)]
+    pub const fn m_tx_empty(&self) -> bool {
+        let val = (self.0 >> 4usize) & 0x01;
+        val != 0
+    }
+    #[doc = "This bit masks the R_TX_EMPTY interrupt in IC_INTR_STAT register. Reset value: 0x1"]
+    #[inline(always)]
+    pub fn set_m_tx_empty(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
+    }
+    #[doc = "This bit masks the R_RD_REQ interrupt in IC_INTR_STAT register. Reset value: 0x1"]
+    #[inline(always)]
+    pub const fn m_rd_req(&self) -> bool {
+        let val = (self.0 >> 5usize) & 0x01;
+        val != 0
+    }
+    #[doc = "This bit masks the R_RD_REQ interrupt in IC_INTR_STAT register. Reset value: 0x1"]
+    #[inline(always)]
+    pub fn set_m_rd_req(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
+    }
+    #[doc = "This bit masks the R_TX_ABRT interrupt in IC_INTR_STAT register. Reset value: 0x1"]
+    #[inline(always)]
+    pub const fn m_tx_abrt(&self) -> bool {
+        let val = (self.0 >> 6usize) & 0x01;
+        val != 0
+    }
+    #[doc = "This bit masks the R_TX_ABRT interrupt in IC_INTR_STAT register. Reset value: 0x1"]
+    #[inline(always)]
+    pub fn set_m_tx_abrt(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
+    }
+    #[doc = "This bit masks the R_RX_DONE interrupt in IC_INTR_STAT register. Reset value: 0x1"]
+    #[inline(always)]
+    pub const fn m_rx_done(&self) -> bool {
+        let val = (self.0 >> 7usize) & 0x01;
+        val != 0
+    }
+    #[doc = "This bit masks the R_RX_DONE interrupt in IC_INTR_STAT register. Reset value: 0x1"]
+    #[inline(always)]
+    pub fn set_m_rx_done(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
+    }
+    #[doc = "This bit masks the R_ACTIVITY interrupt in IC_INTR_STAT register. Reset value: 0x0"]
+    #[inline(always)]
+    pub const fn m_activity(&self) -> bool {
+        let val = (self.0 >> 8usize) & 0x01;
+        val != 0
+    }
+    #[doc = "This bit masks the R_ACTIVITY interrupt in IC_INTR_STAT register. Reset value: 0x0"]
+    #[inline(always)]
+    pub fn set_m_activity(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
+    }
+    #[doc = "This bit masks the R_STOP_DET interrupt in IC_INTR_STAT register. Reset value: 0x0"]
+    #[inline(always)]
+    pub const fn m_stop_det(&self) -> bool {
+        let val = (self.0 >> 9usize) & 0x01;
+        val != 0
+    }
+    #[doc = "This bit masks the R_STOP_DET interrupt in IC_INTR_STAT register. Reset value: 0x0"]
+    #[inline(always)]
+    pub fn set_m_stop_det(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
+    }
+    #[doc = "This bit masks the R_START_DET interrupt in IC_INTR_STAT register. Reset value: 0x0"]
+    #[inline(always)]
+    pub const fn m_start_det(&self) -> bool {
+        let val = (self.0 >> 10usize) & 0x01;
+        val != 0
+    }
+    #[doc = "This bit masks the R_START_DET interrupt in IC_INTR_STAT register. Reset value: 0x0"]
+    #[inline(always)]
+    pub fn set_m_start_det(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize);
+    }
+    #[doc = "This bit masks the R_GEN_CALL interrupt in IC_INTR_STAT register. Reset value: 0x1"]
+    #[inline(always)]
+    pub const fn m_gen_call(&self) -> bool {
+        let val = (self.0 >> 11usize) & 0x01;
+        val != 0
+    }
+    #[doc = "This bit masks the R_GEN_CALL interrupt in IC_INTR_STAT register. Reset value: 0x1"]
+    #[inline(always)]
+    pub fn set_m_gen_call(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
+    }
+    #[doc = "This bit masks the R_RESTART_DET interrupt in IC_INTR_STAT register. Reset value: 0x0"]
+    #[inline(always)]
+    pub const fn m_restart_det(&self) -> bool {
+        let val = (self.0 >> 12usize) & 0x01;
+        val != 0
+    }
+    #[doc = "This bit masks the R_RESTART_DET interrupt in IC_INTR_STAT register. Reset value: 0x0"]
+    #[inline(always)]
+    pub fn set_m_restart_det(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
+    }
+}
+impl Default for IcIntrMask {
+    #[inline(always)]
+    fn default() -> IcIntrMask {
+        IcIntrMask(0)
+    }
+}
+#[doc = "I2C Interrupt Status Register Each bit in this register has a corresponding mask bit in the IC_INTR_MASK register. These bits are cleared by reading the matching interrupt clear register. The unmasked raw versions of these bits are available in the IC_RAW_INTR_STAT register."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct IcIntrStat(pub u32);
+impl IcIntrStat {
+    #[doc = "See IC_RAW_INTR_STAT for a detailed description of R_RX_UNDER bit. Reset value: 0x0"]
+    #[inline(always)]
+    pub const fn r_rx_under(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "See IC_RAW_INTR_STAT for a detailed description of R_RX_UNDER bit. Reset value: 0x0"]
+    #[inline(always)]
+    pub fn set_r_rx_under(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[doc = "See IC_RAW_INTR_STAT for a detailed description of R_RX_OVER bit. Reset value: 0x0"]
+    #[inline(always)]
+    pub const fn r_rx_over(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[doc = "See IC_RAW_INTR_STAT for a detailed description of R_RX_OVER bit. Reset value: 0x0"]
+    #[inline(always)]
+    pub fn set_r_rx_over(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+    #[doc = "See IC_RAW_INTR_STAT for a detailed description of R_RX_FULL bit. Reset value: 0x0"]
+    #[inline(always)]
+    pub const fn r_rx_full(&self) -> bool {
+        let val = (self.0 >> 2usize) & 0x01;
+        val != 0
+    }
+    #[doc = "See IC_RAW_INTR_STAT for a detailed description of R_RX_FULL bit. Reset value: 0x0"]
+    #[inline(always)]
+    pub fn set_r_rx_full(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+    }
+    #[doc = "See IC_RAW_INTR_STAT for a detailed description of R_TX_OVER bit. Reset value: 0x0"]
+    #[inline(always)]
+    pub const fn r_tx_over(&self) -> bool {
+        let val = (self.0 >> 3usize) & 0x01;
+        val != 0
+    }
+    #[doc = "See IC_RAW_INTR_STAT for a detailed description of R_TX_OVER bit. Reset value: 0x0"]
+    #[inline(always)]
+    pub fn set_r_tx_over(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
+    }
+    #[doc = "See IC_RAW_INTR_STAT for a detailed description of R_TX_EMPTY bit. Reset value: 0x0"]
+    #[inline(always)]
+    pub const fn r_tx_empty(&self) -> bool {
+        let val = (self.0 >> 4usize) & 0x01;
+        val != 0
+    }
+    #[doc = "See IC_RAW_INTR_STAT for a detailed description of R_TX_EMPTY bit. Reset value: 0x0"]
+    #[inline(always)]
+    pub fn set_r_tx_empty(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
+    }
+    #[doc = "See IC_RAW_INTR_STAT for a detailed description of R_RD_REQ bit. Reset value: 0x0"]
+    #[inline(always)]
+    pub const fn r_rd_req(&self) -> bool {
+        let val = (self.0 >> 5usize) & 0x01;
+        val != 0
+    }
+    #[doc = "See IC_RAW_INTR_STAT for a detailed description of R_RD_REQ bit. Reset value: 0x0"]
+    #[inline(always)]
+    pub fn set_r_rd_req(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
+    }
+    #[doc = "See IC_RAW_INTR_STAT for a detailed description of R_TX_ABRT bit. Reset value: 0x0"]
+    #[inline(always)]
+    pub const fn r_tx_abrt(&self) -> bool {
+        let val = (self.0 >> 6usize) & 0x01;
+        val != 0
+    }
+    #[doc = "See IC_RAW_INTR_STAT for a detailed description of R_TX_ABRT bit. Reset value: 0x0"]
+    #[inline(always)]
+    pub fn set_r_tx_abrt(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
+    }
+    #[doc = "See IC_RAW_INTR_STAT for a detailed description of R_RX_DONE bit. Reset value: 0x0"]
+    #[inline(always)]
+    pub const fn r_rx_done(&self) -> bool {
+        let val = (self.0 >> 7usize) & 0x01;
+        val != 0
+    }
+    #[doc = "See IC_RAW_INTR_STAT for a detailed description of R_RX_DONE bit. Reset value: 0x0"]
+    #[inline(always)]
+    pub fn set_r_rx_done(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
+    }
+    #[doc = "See IC_RAW_INTR_STAT for a detailed description of R_ACTIVITY bit. Reset value: 0x0"]
+    #[inline(always)]
+    pub const fn r_activity(&self) -> bool {
+        let val = (self.0 >> 8usize) & 0x01;
+        val != 0
+    }
+    #[doc = "See IC_RAW_INTR_STAT for a detailed description of R_ACTIVITY bit. Reset value: 0x0"]
+    #[inline(always)]
+    pub fn set_r_activity(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
+    }
+    #[doc = "See IC_RAW_INTR_STAT for a detailed description of R_STOP_DET bit. Reset value: 0x0"]
+    #[inline(always)]
+    pub const fn r_stop_det(&self) -> bool {
+        let val = (self.0 >> 9usize) & 0x01;
+        val != 0
+    }
+    #[doc = "See IC_RAW_INTR_STAT for a detailed description of R_STOP_DET bit. Reset value: 0x0"]
+    #[inline(always)]
+    pub fn set_r_stop_det(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
+    }
+    #[doc = "See IC_RAW_INTR_STAT for a detailed description of R_START_DET bit. Reset value: 0x0"]
+    #[inline(always)]
+    pub const fn r_start_det(&self) -> bool {
+        let val = (self.0 >> 10usize) & 0x01;
+        val != 0
+    }
+    #[doc = "See IC_RAW_INTR_STAT for a detailed description of R_START_DET bit. Reset value: 0x0"]
+    #[inline(always)]
+    pub fn set_r_start_det(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize);
+    }
+    #[doc = "See IC_RAW_INTR_STAT for a detailed description of R_GEN_CALL bit. Reset value: 0x0"]
+    #[inline(always)]
+    pub const fn r_gen_call(&self) -> bool {
+        let val = (self.0 >> 11usize) & 0x01;
+        val != 0
+    }
+    #[doc = "See IC_RAW_INTR_STAT for a detailed description of R_GEN_CALL bit. Reset value: 0x0"]
+    #[inline(always)]
+    pub fn set_r_gen_call(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
+    }
+    #[doc = "See IC_RAW_INTR_STAT for a detailed description of R_RESTART_DET bit. Reset value: 0x0"]
+    #[inline(always)]
+    pub const fn r_restart_det(&self) -> bool {
+        let val = (self.0 >> 12usize) & 0x01;
+        val != 0
+    }
+    #[doc = "See IC_RAW_INTR_STAT for a detailed description of R_RESTART_DET bit. Reset value: 0x0"]
+    #[inline(always)]
+    pub fn set_r_restart_det(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
+    }
+}
+impl Default for IcIntrStat {
+    #[inline(always)]
+    fn default() -> IcIntrStat {
+        IcIntrStat(0)
+    }
+}
+#[doc = "I2C Raw Interrupt Status Register Unlike the IC_INTR_STAT register, these bits are not masked so they always show the true status of the DW_apb_i2c."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct IcRawIntrStat(pub u32);
+impl IcRawIntrStat {
+    #[doc = "Set if the processor attempts to read the receive buffer when it is empty by reading from the IC_DATA_CMD register. If the module is disabled (IC_ENABLE\\[0\\]=0), this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared. Reset value: 0x0"]
+    #[inline(always)]
+    pub const fn rx_under(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Set if the processor attempts to read the receive buffer when it is empty by reading from the IC_DATA_CMD register. If the module is disabled (IC_ENABLE\\[0\\]=0), this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared. Reset value: 0x0"]
+    #[inline(always)]
+    pub fn set_rx_under(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[doc = "Set if the receive buffer is completely filled to IC_RX_BUFFER_DEPTH and an additional byte is received from an external I2C device. The DW_apb_i2c acknowledges this, but any data bytes received after the FIFO is full are lost. If the module is disabled (IC_ENABLE\\[0\\]=0), this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared. Note: If bit 9 of the IC_CON register (RX_FIFO_FULL_HLD_CTRL) is programmed to HIGH, then the RX_OVER interrupt never occurs, because the Rx FIFO never overflows. Reset value: 0x0"]
+    #[inline(always)]
+    pub const fn rx_over(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Set if the receive buffer is completely filled to IC_RX_BUFFER_DEPTH and an additional byte is received from an external I2C device. The DW_apb_i2c acknowledges this, but any data bytes received after the FIFO is full are lost. If the module is disabled (IC_ENABLE\\[0\\]=0), this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared. Note: If bit 9 of the IC_CON register (RX_FIFO_FULL_HLD_CTRL) is programmed to HIGH, then the RX_OVER interrupt never occurs, because the Rx FIFO never overflows. Reset value: 0x0"]
+    #[inline(always)]
+    pub fn set_rx_over(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+    #[doc = "Set when the receive buffer reaches or goes above the RX_TL threshold in the IC_RX_TL register. It is automatically cleared by hardware when buffer level goes below the threshold. If the module is disabled (IC_ENABLE\\[0\\]=0), the RX FIFO is flushed and held in reset; therefore the RX FIFO is not full. So this bit is cleared once the IC_ENABLE bit 0 is programmed with a 0, regardless of the activity that continues. Reset value: 0x0"]
+    #[inline(always)]
+    pub const fn rx_full(&self) -> bool {
+        let val = (self.0 >> 2usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Set when the receive buffer reaches or goes above the RX_TL threshold in the IC_RX_TL register. It is automatically cleared by hardware when buffer level goes below the threshold. If the module is disabled (IC_ENABLE\\[0\\]=0), the RX FIFO is flushed and held in reset; therefore the RX FIFO is not full. So this bit is cleared once the IC_ENABLE bit 0 is programmed with a 0, regardless of the activity that continues. Reset value: 0x0"]
+    #[inline(always)]
+    pub fn set_rx_full(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+    }
+    #[doc = "Set during transmit if the transmit buffer is filled to IC_TX_BUFFER_DEPTH and the processor attempts to issue another I2C command by writing to the IC_DATA_CMD register. When the module is disabled, this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared. Reset value: 0x0"]
+    #[inline(always)]
+    pub const fn tx_over(&self) -> bool {
+        let val = (self.0 >> 3usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Set during transmit if the transmit buffer is filled to IC_TX_BUFFER_DEPTH and the processor attempts to issue another I2C command by writing to the IC_DATA_CMD register. When the module is disabled, this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared. Reset value: 0x0"]
+    #[inline(always)]
+    pub fn set_tx_over(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
+    }
+    #[doc = "The behavior of the TX_EMPTY interrupt status differs based on the TX_EMPTY_CTRL selection in the IC_CON register. - When TX_EMPTY_CTRL = 0: This bit is set to 1 when the transmit buffer is at or below the threshold value set in the IC_TX_TL register. - When TX_EMPTY_CTRL = 1: This bit is set to 1 when the transmit buffer is at or below the threshold value set in the IC_TX_TL register and the transmission of the address/data from the internal shift register for the most recently popped command is completed. It is automatically cleared by hardware when the buffer level goes above the threshold. When IC_ENABLE\\[0\\] is set to 0, the TX FIFO is flushed and held in reset. There the TX FIFO looks like it has no data within it, so this bit is set to 1, provided there is activity in the master or slave state machines. When there is no longer any activity, then with ic_en=0, this bit is set to 0. Reset value: 0x0."]
+    #[inline(always)]
+    pub const fn tx_empty(&self) -> bool {
+        let val = (self.0 >> 4usize) & 0x01;
+        val != 0
+    }
+    #[doc = "The behavior of the TX_EMPTY interrupt status differs based on the TX_EMPTY_CTRL selection in the IC_CON register. - When TX_EMPTY_CTRL = 0: This bit is set to 1 when the transmit buffer is at or below the threshold value set in the IC_TX_TL register. - When TX_EMPTY_CTRL = 1: This bit is set to 1 when the transmit buffer is at or below the threshold value set in the IC_TX_TL register and the transmission of the address/data from the internal shift register for the most recently popped command is completed. It is automatically cleared by hardware when the buffer level goes above the threshold. When IC_ENABLE\\[0\\] is set to 0, the TX FIFO is flushed and held in reset. There the TX FIFO looks like it has no data within it, so this bit is set to 1, provided there is activity in the master or slave state machines. When there is no longer any activity, then with ic_en=0, this bit is set to 0. Reset value: 0x0."]
+    #[inline(always)]
+    pub fn set_tx_empty(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
+    }
+    #[doc = "This bit is set to 1 when DW_apb_i2c is acting as a slave and another I2C master is attempting to read data from DW_apb_i2c. The DW_apb_i2c holds the I2C bus in a wait state (SCL=0) until this interrupt is serviced, which means that the slave has been addressed by a remote master that is asking for data to be transferred. The processor must respond to this interrupt and then write the requested data to the IC_DATA_CMD register. This bit is set to 0 just after the processor reads the IC_CLR_RD_REQ register. Reset value: 0x0"]
+    #[inline(always)]
+    pub const fn rd_req(&self) -> bool {
+        let val = (self.0 >> 5usize) & 0x01;
+        val != 0
+    }
+    #[doc = "This bit is set to 1 when DW_apb_i2c is acting as a slave and another I2C master is attempting to read data from DW_apb_i2c. The DW_apb_i2c holds the I2C bus in a wait state (SCL=0) until this interrupt is serviced, which means that the slave has been addressed by a remote master that is asking for data to be transferred. The processor must respond to this interrupt and then write the requested data to the IC_DATA_CMD register. This bit is set to 0 just after the processor reads the IC_CLR_RD_REQ register. Reset value: 0x0"]
+    #[inline(always)]
+    pub fn set_rd_req(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
+    }
+    #[doc = "This bit indicates if DW_apb_i2c, as an I2C transmitter, is unable to complete the intended actions on the contents of the transmit FIFO. This situation can occur both as an I2C master or an I2C slave, and is referred to as a 'transmit abort'. When this bit is set to 1, the IC_TX_ABRT_SOURCE register indicates the reason why the transmit abort takes places. Note: The DW_apb_i2c flushes/resets/empties the TX_FIFO and RX_FIFO whenever there is a transmit abort caused by any of the events tracked by the IC_TX_ABRT_SOURCE register. The FIFOs remains in this flushed state until the register IC_CLR_TX_ABRT is read. Once this read is performed, the Tx FIFO is then ready to accept more data bytes from the APB interface. Reset value: 0x0"]
+    #[inline(always)]
+    pub const fn tx_abrt(&self) -> bool {
+        let val = (self.0 >> 6usize) & 0x01;
+        val != 0
+    }
+    #[doc = "This bit indicates if DW_apb_i2c, as an I2C transmitter, is unable to complete the intended actions on the contents of the transmit FIFO. This situation can occur both as an I2C master or an I2C slave, and is referred to as a 'transmit abort'. When this bit is set to 1, the IC_TX_ABRT_SOURCE register indicates the reason why the transmit abort takes places. Note: The DW_apb_i2c flushes/resets/empties the TX_FIFO and RX_FIFO whenever there is a transmit abort caused by any of the events tracked by the IC_TX_ABRT_SOURCE register. The FIFOs remains in this flushed state until the register IC_CLR_TX_ABRT is read. Once this read is performed, the Tx FIFO is then ready to accept more data bytes from the APB interface. Reset value: 0x0"]
+    #[inline(always)]
+    pub fn set_tx_abrt(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
+    }
+    #[doc = "When the DW_apb_i2c is acting as a slave-transmitter, this bit is set to 1 if the master does not acknowledge a transmitted byte. This occurs on the last byte of the transmission, indicating that the transmission is done. Reset value: 0x0"]
+    #[inline(always)]
+    pub const fn rx_done(&self) -> bool {
+        let val = (self.0 >> 7usize) & 0x01;
+        val != 0
+    }
+    #[doc = "When the DW_apb_i2c is acting as a slave-transmitter, this bit is set to 1 if the master does not acknowledge a transmitted byte. This occurs on the last byte of the transmission, indicating that the transmission is done. Reset value: 0x0"]
+    #[inline(always)]
+    pub fn set_rx_done(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
+    }
+    #[doc = "This bit captures DW_apb_i2c activity and stays set until it is cleared. There are four ways to clear it: - Disabling the DW_apb_i2c - Reading the IC_CLR_ACTIVITY register - Reading the IC_CLR_INTR register - System reset Once this bit is set, it stays set unless one of the four methods is used to clear it. Even if the DW_apb_i2c module is idle, this bit remains set until cleared, indicating that there was activity on the bus. Reset value: 0x0"]
+    #[inline(always)]
+    pub const fn activity(&self) -> bool {
+        let val = (self.0 >> 8usize) & 0x01;
+        val != 0
+    }
+    #[doc = "This bit captures DW_apb_i2c activity and stays set until it is cleared. There are four ways to clear it: - Disabling the DW_apb_i2c - Reading the IC_CLR_ACTIVITY register - Reading the IC_CLR_INTR register - System reset Once this bit is set, it stays set unless one of the four methods is used to clear it. Even if the DW_apb_i2c module is idle, this bit remains set until cleared, indicating that there was activity on the bus. Reset value: 0x0"]
+    #[inline(always)]
+    pub fn set_activity(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
+    }
+    #[doc = "Indicates whether a STOP condition has occurred on the I2C interface regardless of whether DW_apb_i2c is operating in slave or master mode. In Slave Mode: - If IC_CON\\[7\\]=1'b1 (STOP_DET_IFADDRESSED), the STOP_DET interrupt will be issued only if slave is addressed. Note: During a general call address, this slave does not issue a STOP_DET interrupt if STOP_DET_IF_ADDRESSED=1'b1, even if the slave responds to the general call address by generating ACK. The STOP_DET interrupt is generated only when the transmitted address matches the slave address (SAR). - If IC_CON\\[7\\]=1'b0 (STOP_DET_IFADDRESSED), the STOP_DET interrupt is issued irrespective of whether it is being addressed. In Master Mode: - If IC_CON\\[10\\]=1'b1 (STOP_DET_IF_MASTER_ACTIVE),the STOP_DET interrupt will be issued only if Master is active. - If IC_CON\\[10\\]=1'b0 (STOP_DET_IFADDRESSED),the STOP_DET interrupt will be issued irrespective of whether master is active or not. Reset value: 0x0"]
+    #[inline(always)]
+    pub const fn stop_det(&self) -> bool {
+        let val = (self.0 >> 9usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Indicates whether a STOP condition has occurred on the I2C interface regardless of whether DW_apb_i2c is operating in slave or master mode. In Slave Mode: - If IC_CON\\[7\\]=1'b1 (STOP_DET_IFADDRESSED), the STOP_DET interrupt will be issued only if slave is addressed. Note: During a general call address, this slave does not issue a STOP_DET interrupt if STOP_DET_IF_ADDRESSED=1'b1, even if the slave responds to the general call address by generating ACK. The STOP_DET interrupt is generated only when the transmitted address matches the slave address (SAR). - If IC_CON\\[7\\]=1'b0 (STOP_DET_IFADDRESSED), the STOP_DET interrupt is issued irrespective of whether it is being addressed. In Master Mode: - If IC_CON\\[10\\]=1'b1 (STOP_DET_IF_MASTER_ACTIVE),the STOP_DET interrupt will be issued only if Master is active. - If IC_CON\\[10\\]=1'b0 (STOP_DET_IFADDRESSED),the STOP_DET interrupt will be issued irrespective of whether master is active or not. Reset value: 0x0"]
+    #[inline(always)]
+    pub fn set_stop_det(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
+    }
+    #[doc = "Indicates whether a START or RESTART condition has occurred on the I2C interface regardless of whether DW_apb_i2c is operating in slave or master mode. Reset value: 0x0"]
+    #[inline(always)]
+    pub const fn start_det(&self) -> bool {
+        let val = (self.0 >> 10usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Indicates whether a START or RESTART condition has occurred on the I2C interface regardless of whether DW_apb_i2c is operating in slave or master mode. Reset value: 0x0"]
+    #[inline(always)]
+    pub fn set_start_det(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize);
+    }
+    #[doc = "Set only when a General Call address is received and it is acknowledged. It stays set until it is cleared either by disabling DW_apb_i2c or when the CPU reads bit 0 of the IC_CLR_GEN_CALL register. DW_apb_i2c stores the received data in the Rx buffer. Reset value: 0x0"]
+    #[inline(always)]
+    pub const fn gen_call(&self) -> bool {
+        let val = (self.0 >> 11usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Set only when a General Call address is received and it is acknowledged. It stays set until it is cleared either by disabling DW_apb_i2c or when the CPU reads bit 0 of the IC_CLR_GEN_CALL register. DW_apb_i2c stores the received data in the Rx buffer. Reset value: 0x0"]
+    #[inline(always)]
+    pub fn set_gen_call(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
+    }
+    #[doc = "Indicates whether a RESTART condition has occurred on the I2C interface when DW_apb_i2c is operating in Slave mode and the slave is being addressed. Enabled only when IC_SLV_RESTART_DET_EN=1. Note: However, in high-speed mode or during a START BYTE transfer, the RESTART comes before the address field as per the I2C protocol. In this case, the slave is not the addressed slave when the RESTART is issued, therefore DW_apb_i2c does not generate the RESTART_DET interrupt. Reset value: 0x0"]
+    #[inline(always)]
+    pub const fn restart_det(&self) -> bool {
+        let val = (self.0 >> 12usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Indicates whether a RESTART condition has occurred on the I2C interface when DW_apb_i2c is operating in Slave mode and the slave is being addressed. Enabled only when IC_SLV_RESTART_DET_EN=1. Note: However, in high-speed mode or during a START BYTE transfer, the RESTART comes before the address field as per the I2C protocol. In this case, the slave is not the addressed slave when the RESTART is issued, therefore DW_apb_i2c does not generate the RESTART_DET interrupt. Reset value: 0x0"]
+    #[inline(always)]
+    pub fn set_restart_det(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
+    }
+}
+impl Default for IcRawIntrStat {
+    #[inline(always)]
+    fn default() -> IcRawIntrStat {
+        IcRawIntrStat(0)
+    }
+}
+#[doc = "I2C Receive FIFO Threshold Register"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct IcRxTl(pub u32);
+impl IcRxTl {
+    #[doc = "Receive FIFO Threshold Level. Controls the level of entries (or above) that triggers the RX_FULL interrupt (bit 2 in IC_RAW_INTR_STAT register). The valid range is 0-255, with the additional restriction that hardware does not allow this value to be set to a value larger than the depth of the buffer. If an attempt is made to do that, the actual value set will be the maximum depth of the buffer. A value of 0 sets the threshold for 1 entry, and a value of 255 sets the threshold for 256 entries."]
+    #[inline(always)]
+    pub const fn rx_tl(&self) -> u8 {
+        let val = (self.0 >> 0usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Receive FIFO Threshold Level. Controls the level of entries (or above) that triggers the RX_FULL interrupt (bit 2 in IC_RAW_INTR_STAT register). The valid range is 0-255, with the additional restriction that hardware does not allow this value to be set to a value larger than the depth of the buffer. If an attempt is made to do that, the actual value set will be the maximum depth of the buffer. A value of 0 sets the threshold for 1 entry, and a value of 255 sets the threshold for 256 entries."]
+    #[inline(always)]
+    pub fn set_rx_tl(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize);
+    }
+}
+impl Default for IcRxTl {
+    #[inline(always)]
+    fn default() -> IcRxTl {
+        IcRxTl(0)
+    }
+}
+#[doc = "I2C Receive FIFO Level Register This register contains the number of valid data entries in the receive FIFO buffer. It is cleared whenever: - The I2C is disabled - Whenever there is a transmit abort caused by any of the events tracked in IC_TX_ABRT_SOURCE The register increments whenever data is placed into the receive FIFO and decrements when data is taken from the receive FIFO."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct IcRxflr(pub u32);
+impl IcRxflr {
+    #[doc = "Receive FIFO Level. Contains the number of valid data entries in the receive FIFO. Reset value: 0x0"]
+    #[inline(always)]
+    pub const fn rxflr(&self) -> u8 {
+        let val = (self.0 >> 0usize) & 0x1f;
+        val as u8
+    }
+    #[doc = "Receive FIFO Level. Contains the number of valid data entries in the receive FIFO. Reset value: 0x0"]
+    #[inline(always)]
+    pub fn set_rxflr(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x1f << 0usize)) | (((val as u32) & 0x1f) << 0usize);
+    }
+}
+impl Default for IcRxflr {
+    #[inline(always)]
+    fn default() -> IcRxflr {
+        IcRxflr(0)
+    }
+}
+#[doc = "I2C Slave Address Register"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct IcSar(pub u32);
+impl IcSar {
+    #[doc = "The IC_SAR holds the slave address when the I2C is operating as a slave. For 7-bit addressing, only IC_SAR\\[6:0\\] is used. This register can be written only when the I2C interface is disabled, which corresponds to the IC_ENABLE\\[0\\] register being set to 0. Writes at other times have no effect. Note: The default values cannot be any of the reserved address locations: that is, 0x00 to 0x07, or 0x78 to 0x7f. The correct operation of the device is not guaranteed if you program the IC_SAR or IC_TAR to a reserved value. Refer to <<table_I2C_firstbyte_bit_defs>> for a complete list of these reserved values."]
+    #[inline(always)]
+    pub const fn ic_sar(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0x03ff;
+        val as u16
+    }
+    #[doc = "The IC_SAR holds the slave address when the I2C is operating as a slave. For 7-bit addressing, only IC_SAR\\[6:0\\] is used. This register can be written only when the I2C interface is disabled, which corresponds to the IC_ENABLE\\[0\\] register being set to 0. Writes at other times have no effect. Note: The default values cannot be any of the reserved address locations: that is, 0x00 to 0x07, or 0x78 to 0x7f. The correct operation of the device is not guaranteed if you program the IC_SAR or IC_TAR to a reserved value. Refer to <<table_I2C_firstbyte_bit_defs>> for a complete list of these reserved values."]
+    #[inline(always)]
+    pub fn set_ic_sar(&mut self, val: u16) {
+        self.0 = (self.0 & !(0x03ff << 0usize)) | (((val as u32) & 0x03ff) << 0usize);
+    }
+}
+impl Default for IcSar {
+    #[inline(always)]
+    fn default() -> IcSar {
+        IcSar(0)
+    }
+}
+#[doc = "I2C SDA Hold Time Length Register The bits \\[15:0\\] of this register are used to control the hold time of SDA during transmit in both slave and master mode (after SCL goes from HIGH to LOW). The bits \\[23:16\\] of this register are used to extend the SDA transition (if any) whenever SCL is HIGH in the receiver in either master or slave mode. Writes to this register succeed only when IC_ENABLE\\[0\\]=0. The values in this register are in units of ic_clk period. The value programmed in IC_SDA_TX_HOLD must be greater than the minimum hold time in each mode (one cycle in master mode, seven cycles in slave mode) for the value to be implemented. The programmed SDA hold time during transmit (IC_SDA_TX_HOLD) cannot exceed at any time the duration of the low part of scl. Therefore the programmed value cannot be larger than N_SCL_LOW-2, where N_SCL_LOW is the duration of the low part of the scl period measured in ic_clk cycles."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct IcSdaHold(pub u32);
+impl IcSdaHold {
+    #[doc = "Sets the required SDA hold time in units of ic_clk period, when DW_apb_i2c acts as a transmitter. Reset value: IC_DEFAULT_SDA_HOLD\\[15:0\\]."]
+    #[inline(always)]
+    pub const fn ic_sda_tx_hold(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0xffff;
+        val as u16
+    }
+    #[doc = "Sets the required SDA hold time in units of ic_clk period, when DW_apb_i2c acts as a transmitter. Reset value: IC_DEFAULT_SDA_HOLD\\[15:0\\]."]
+    #[inline(always)]
+    pub fn set_ic_sda_tx_hold(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+    }
+    #[doc = "Sets the required SDA hold time in units of ic_clk period, when DW_apb_i2c acts as a receiver. Reset value: IC_DEFAULT_SDA_HOLD\\[23:16\\]."]
+    #[inline(always)]
+    pub const fn ic_sda_rx_hold(&self) -> u8 {
+        let val = (self.0 >> 16usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Sets the required SDA hold time in units of ic_clk period, when DW_apb_i2c acts as a receiver. Reset value: IC_DEFAULT_SDA_HOLD\\[23:16\\]."]
+    #[inline(always)]
+    pub fn set_ic_sda_rx_hold(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize);
+    }
+}
+impl Default for IcSdaHold {
+    #[inline(always)]
+    fn default() -> IcSdaHold {
+        IcSdaHold(0)
+    }
+}
+#[doc = "I2C SDA Setup Register This register controls the amount of time delay (in terms of number of ic_clk clock periods) introduced in the rising edge of SCL - relative to SDA changing - when DW_apb_i2c services a read request in a slave-transmitter operation. The relevant I2C requirement is tSU:DAT (note 4) as detailed in the I2C Bus Specification. This register must be programmed with a value equal to or greater than 2. Writes to this register succeed only when IC_ENABLE\\[0\\] = 0. Note: The length of setup time is calculated using \\[(IC_SDA_SETUP - 1) * (ic_clk_period)\\], so if the user requires 10 ic_clk periods of setup time, they should program a value of 11. The IC_SDA_SETUP register is only used by the DW_apb_i2c when operating as a slave transmitter."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct IcSdaSetup(pub u32);
+impl IcSdaSetup {
+    #[doc = "SDA Setup. It is recommended that if the required delay is 1000ns, then for an ic_clk frequency of 10 MHz, IC_SDA_SETUP should be programmed to a value of 11. IC_SDA_SETUP must be programmed with a minimum value of 2."]
+    #[inline(always)]
+    pub const fn sda_setup(&self) -> u8 {
+        let val = (self.0 >> 0usize) & 0xff;
+        val as u8
+    }
+    #[doc = "SDA Setup. It is recommended that if the required delay is 1000ns, then for an ic_clk frequency of 10 MHz, IC_SDA_SETUP should be programmed to a value of 11. IC_SDA_SETUP must be programmed with a minimum value of 2."]
+    #[inline(always)]
+    pub fn set_sda_setup(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize);
+    }
+}
+impl Default for IcSdaSetup {
+    #[inline(always)]
+    fn default() -> IcSdaSetup {
+        IcSdaSetup(0)
+    }
+}
+#[doc = "Generate Slave Data NACK Register The register is used to generate a NACK for the data part of a transfer when DW_apb_i2c is acting as a slave-receiver. This register only exists when the IC_SLV_DATA_NACK_ONLY parameter is set to 1. When this parameter disabled, this register does not exist and writing to the register's address has no effect. A write can occur on this register if both of the following conditions are met: - DW_apb_i2c is disabled (IC_ENABLE\\[0\\] = 0) - Slave part is inactive (IC_STATUS\\[6\\] = 0) Note: The IC_STATUS\\[6\\] is a register read-back location for the internal slv_activity signal; the user should poll this before writing the ic_slv_data_nack_only bit."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct IcSlvDataNackOnly(pub u32);
+impl IcSlvDataNackOnly {
+    #[doc = "Generate NACK. This NACK generation only occurs when DW_apb_i2c is a slave-receiver. If this register is set to a value of 1, it can only generate a NACK after a data byte is received; hence, the data transfer is aborted and the data received is not pushed to the receive buffer. When the register is set to a value of 0, it generates NACK/ACK, depending on normal criteria. - 1: generate NACK after data byte received - 0: generate NACK/ACK normally Reset value: 0x0"]
+    #[inline(always)]
+    pub const fn nack(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Generate NACK. This NACK generation only occurs when DW_apb_i2c is a slave-receiver. If this register is set to a value of 1, it can only generate a NACK after a data byte is received; hence, the data transfer is aborted and the data received is not pushed to the receive buffer. When the register is set to a value of 0, it generates NACK/ACK, depending on normal criteria. - 1: generate NACK after data byte received - 0: generate NACK/ACK normally Reset value: 0x0"]
+    #[inline(always)]
+    pub fn set_nack(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+}
+impl Default for IcSlvDataNackOnly {
+    #[inline(always)]
+    fn default() -> IcSlvDataNackOnly {
+        IcSlvDataNackOnly(0)
+    }
+}
+#[doc = "Standard Speed I2C Clock SCL High Count Register"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct IcSsSclHcnt(pub u32);
+impl IcSsSclHcnt {
+    #[doc = "This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock high-period count for standard speed. For more information, refer to 'IC_CLK Frequency Configuration'. This register can be written only when the I2C interface is disabled which corresponds to the IC_ENABLE\\[0\\] register being set to 0. Writes at other times have no effect. The minimum valid value is 6; hardware prevents values less than this being written, and if attempted results in 6 being set. For designs with APB_DATA_WIDTH = 8, the order of programming is important to ensure the correct operation of the DW_apb_i2c. The lower byte must be programmed first. Then the upper byte is programmed. NOTE: This register must not be programmed to a value higher than 65525, because DW_apb_i2c uses a 16-bit counter to flag an I2C bus idle condition when this counter reaches a value of IC_SS_SCL_HCNT + 10."]
+    #[inline(always)]
+    pub const fn ic_ss_scl_hcnt(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0xffff;
+        val as u16
+    }
+    #[doc = "This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock high-period count for standard speed. For more information, refer to 'IC_CLK Frequency Configuration'. This register can be written only when the I2C interface is disabled which corresponds to the IC_ENABLE\\[0\\] register being set to 0. Writes at other times have no effect. The minimum valid value is 6; hardware prevents values less than this being written, and if attempted results in 6 being set. For designs with APB_DATA_WIDTH = 8, the order of programming is important to ensure the correct operation of the DW_apb_i2c. The lower byte must be programmed first. Then the upper byte is programmed. NOTE: This register must not be programmed to a value higher than 65525, because DW_apb_i2c uses a 16-bit counter to flag an I2C bus idle condition when this counter reaches a value of IC_SS_SCL_HCNT + 10."]
+    #[inline(always)]
+    pub fn set_ic_ss_scl_hcnt(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+    }
+}
+impl Default for IcSsSclHcnt {
+    #[inline(always)]
+    fn default() -> IcSsSclHcnt {
+        IcSsSclHcnt(0)
+    }
+}
+#[doc = "Standard Speed I2C Clock SCL Low Count Register"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct IcSsSclLcnt(pub u32);
+impl IcSsSclLcnt {
+    #[doc = "This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock low period count for standard speed. For more information, refer to 'IC_CLK Frequency Configuration' This register can be written only when the I2C interface is disabled which corresponds to the IC_ENABLE\\[0\\] register being set to 0. Writes at other times have no effect. The minimum valid value is 8; hardware prevents values less than this being written, and if attempted, results in 8 being set. For designs with APB_DATA_WIDTH = 8, the order of programming is important to ensure the correct operation of DW_apb_i2c. The lower byte must be programmed first, and then the upper byte is programmed."]
+    #[inline(always)]
+    pub const fn ic_ss_scl_lcnt(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0xffff;
+        val as u16
+    }
+    #[doc = "This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock low period count for standard speed. For more information, refer to 'IC_CLK Frequency Configuration' This register can be written only when the I2C interface is disabled which corresponds to the IC_ENABLE\\[0\\] register being set to 0. Writes at other times have no effect. The minimum valid value is 8; hardware prevents values less than this being written, and if attempted, results in 8 being set. For designs with APB_DATA_WIDTH = 8, the order of programming is important to ensure the correct operation of DW_apb_i2c. The lower byte must be programmed first, and then the upper byte is programmed."]
+    #[inline(always)]
+    pub fn set_ic_ss_scl_lcnt(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+    }
+}
+impl Default for IcSsSclLcnt {
+    #[inline(always)]
+    fn default() -> IcSsSclLcnt {
+        IcSsSclLcnt(0)
+    }
+}
+#[doc = "I2C Status Register This is a read-only register used to indicate the current transfer status and FIFO status. The status register may be read at any time. None of the bits in this register request an interrupt. When the I2C is disabled by writing 0 in bit 0 of the IC_ENABLE register: - Bits 1 and 2 are set to 1 - Bits 3 and 10 are set to 0 When the master or slave state machines goes to idle and ic_en=0: - Bits 5 and 6 are set to 0"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct IcStatus(pub u32);
+impl IcStatus {
+    #[doc = "I2C Activity Status. Reset value: 0x0"]
+    #[inline(always)]
+    pub const fn activity(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "I2C Activity Status. Reset value: 0x0"]
+    #[inline(always)]
+    pub fn set_activity(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[doc = "Transmit FIFO Not Full. Set when the transmit FIFO contains one or more empty locations, and is cleared when the FIFO is full. - 0: Transmit FIFO is full - 1: Transmit FIFO is not full Reset value: 0x1"]
+    #[inline(always)]
+    pub const fn tfnf(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Transmit FIFO Not Full. Set when the transmit FIFO contains one or more empty locations, and is cleared when the FIFO is full. - 0: Transmit FIFO is full - 1: Transmit FIFO is not full Reset value: 0x1"]
+    #[inline(always)]
+    pub fn set_tfnf(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+    #[doc = "Transmit FIFO Completely Empty. When the transmit FIFO is completely empty, this bit is set. When it contains one or more valid entries, this bit is cleared. This bit field does not request an interrupt. - 0: Transmit FIFO is not empty - 1: Transmit FIFO is empty Reset value: 0x1"]
+    #[inline(always)]
+    pub const fn tfe(&self) -> bool {
+        let val = (self.0 >> 2usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Transmit FIFO Completely Empty. When the transmit FIFO is completely empty, this bit is set. When it contains one or more valid entries, this bit is cleared. This bit field does not request an interrupt. - 0: Transmit FIFO is not empty - 1: Transmit FIFO is empty Reset value: 0x1"]
+    #[inline(always)]
+    pub fn set_tfe(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+    }
+    #[doc = "Receive FIFO Not Empty. This bit is set when the receive FIFO contains one or more entries; it is cleared when the receive FIFO is empty. - 0: Receive FIFO is empty - 1: Receive FIFO is not empty Reset value: 0x0"]
+    #[inline(always)]
+    pub const fn rfne(&self) -> bool {
+        let val = (self.0 >> 3usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Receive FIFO Not Empty. This bit is set when the receive FIFO contains one or more entries; it is cleared when the receive FIFO is empty. - 0: Receive FIFO is empty - 1: Receive FIFO is not empty Reset value: 0x0"]
+    #[inline(always)]
+    pub fn set_rfne(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
+    }
+    #[doc = "Receive FIFO Completely Full. When the receive FIFO is completely full, this bit is set. When the receive FIFO contains one or more empty location, this bit is cleared. - 0: Receive FIFO is not full - 1: Receive FIFO is full Reset value: 0x0"]
+    #[inline(always)]
+    pub const fn rff(&self) -> bool {
+        let val = (self.0 >> 4usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Receive FIFO Completely Full. When the receive FIFO is completely full, this bit is set. When the receive FIFO contains one or more empty location, this bit is cleared. - 0: Receive FIFO is not full - 1: Receive FIFO is full Reset value: 0x0"]
+    #[inline(always)]
+    pub fn set_rff(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
+    }
+    #[doc = "Master FSM Activity Status. When the Master Finite State Machine (FSM) is not in the IDLE state, this bit is set. - 0: Master FSM is in IDLE state so the Master part of DW_apb_i2c is not Active - 1: Master FSM is not in IDLE state so the Master part of DW_apb_i2c is Active Note: IC_STATUS\\[0\\]-that is, ACTIVITY bit-is the OR of SLV_ACTIVITY and MST_ACTIVITY bits. Reset value: 0x0"]
+    #[inline(always)]
+    pub const fn mst_activity(&self) -> bool {
+        let val = (self.0 >> 5usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Master FSM Activity Status. When the Master Finite State Machine (FSM) is not in the IDLE state, this bit is set. - 0: Master FSM is in IDLE state so the Master part of DW_apb_i2c is not Active - 1: Master FSM is not in IDLE state so the Master part of DW_apb_i2c is Active Note: IC_STATUS\\[0\\]-that is, ACTIVITY bit-is the OR of SLV_ACTIVITY and MST_ACTIVITY bits. Reset value: 0x0"]
+    #[inline(always)]
+    pub fn set_mst_activity(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
+    }
+    #[doc = "Slave FSM Activity Status. When the Slave Finite State Machine (FSM) is not in the IDLE state, this bit is set. - 0: Slave FSM is in IDLE state so the Slave part of DW_apb_i2c is not Active - 1: Slave FSM is not in IDLE state so the Slave part of DW_apb_i2c is Active Reset value: 0x0"]
+    #[inline(always)]
+    pub const fn slv_activity(&self) -> bool {
+        let val = (self.0 >> 6usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Slave FSM Activity Status. When the Slave Finite State Machine (FSM) is not in the IDLE state, this bit is set. - 0: Slave FSM is in IDLE state so the Slave part of DW_apb_i2c is not Active - 1: Slave FSM is not in IDLE state so the Slave part of DW_apb_i2c is Active Reset value: 0x0"]
+    #[inline(always)]
+    pub fn set_slv_activity(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
+    }
+}
+impl Default for IcStatus {
+    #[inline(always)]
+    fn default() -> IcStatus {
+        IcStatus(0)
+    }
+}
+#[doc = "I2C Target Address Register This register is 12 bits wide, and bits 31:12 are reserved. This register can be written to only when IC_ENABLE\\[0\\] is set to 0. Note: If the software or application is aware that the DW_apb_i2c is not using the TAR address for the pending commands in the Tx FIFO, then it is possible to update the TAR address even while the Tx FIFO has entries (IC_STATUS\\[2\\]= 0). - It is not necessary to perform any write to this register if DW_apb_i2c is enabled as an I2C slave only."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct IcTar(pub u32);
+impl IcTar {
+    #[doc = "This is the target address for any master transaction. When transmitting a General Call, these bits are ignored. To generate a START BYTE, the CPU needs to write only once into these bits. If the IC_TAR and IC_SAR are the same, loopback exists but the FIFOs are shared between master and slave, so full loopback is not feasible. Only one direction loopback mode is supported (simplex), not duplex. A master cannot transmit to itself; it can transmit to only a slave."]
+    #[inline(always)]
+    pub const fn ic_tar(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0x03ff;
+        val as u16
+    }
+    #[doc = "This is the target address for any master transaction. When transmitting a General Call, these bits are ignored. To generate a START BYTE, the CPU needs to write only once into these bits. If the IC_TAR and IC_SAR are the same, loopback exists but the FIFOs are shared between master and slave, so full loopback is not feasible. Only one direction loopback mode is supported (simplex), not duplex. A master cannot transmit to itself; it can transmit to only a slave."]
+    #[inline(always)]
+    pub fn set_ic_tar(&mut self, val: u16) {
+        self.0 = (self.0 & !(0x03ff << 0usize)) | (((val as u32) & 0x03ff) << 0usize);
+    }
+    #[doc = "If bit 11 (SPECIAL) is set to 1 and bit 13(Device-ID) is set to 0, then this bit indicates whether a General Call or START byte command is to be performed by the DW_apb_i2c. - 0: General Call Address - after issuing a General Call, only writes may be performed. Attempting to issue a read command results in setting bit 6 (TX_ABRT) of the IC_RAW_INTR_STAT register. The DW_apb_i2c remains in General Call mode until the SPECIAL bit value (bit 11) is cleared. - 1: START BYTE Reset value: 0x0"]
+    #[inline(always)]
+    pub const fn gc_or_start(&self) -> bool {
+        let val = (self.0 >> 10usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If bit 11 (SPECIAL) is set to 1 and bit 13(Device-ID) is set to 0, then this bit indicates whether a General Call or START byte command is to be performed by the DW_apb_i2c. - 0: General Call Address - after issuing a General Call, only writes may be performed. Attempting to issue a read command results in setting bit 6 (TX_ABRT) of the IC_RAW_INTR_STAT register. The DW_apb_i2c remains in General Call mode until the SPECIAL bit value (bit 11) is cleared. - 1: START BYTE Reset value: 0x0"]
+    #[inline(always)]
+    pub fn set_gc_or_start(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize);
+    }
+    #[doc = "This bit indicates whether software performs a Device-ID or General Call or START BYTE command. - 0: ignore bit 10 GC_OR_START and use IC_TAR normally - 1: perform special I2C command as specified in Device_ID or GC_OR_START bit Reset value: 0x0"]
+    #[inline(always)]
+    pub const fn special(&self) -> bool {
+        let val = (self.0 >> 11usize) & 0x01;
+        val != 0
+    }
+    #[doc = "This bit indicates whether software performs a Device-ID or General Call or START BYTE command. - 0: ignore bit 10 GC_OR_START and use IC_TAR normally - 1: perform special I2C command as specified in Device_ID or GC_OR_START bit Reset value: 0x0"]
+    #[inline(always)]
+    pub fn set_special(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
+    }
+}
+impl Default for IcTar {
+    #[inline(always)]
+    fn default() -> IcTar {
+        IcTar(0)
+    }
+}
+#[doc = "I2C Transmit Abort Source Register This register has 32 bits that indicate the source of the TX_ABRT bit. Except for Bit 9, this register is cleared whenever the IC_CLR_TX_ABRT register or the IC_CLR_INTR register is read. To clear Bit 9, the source of the ABRT_SBYTE_NORSTRT must be fixed first; RESTART must be enabled (IC_CON\\[5\\]=1), the SPECIAL bit must be cleared (IC_TAR\\[11\\]), or the GC_OR_START bit must be cleared (IC_TAR\\[10\\]). Once the source of the ABRT_SBYTE_NORSTRT is fixed, then this bit can be cleared in the same manner as other bits in this register. If the source of the ABRT_SBYTE_NORSTRT is not fixed before attempting to clear this bit, Bit 9 clears for one cycle and is then re-asserted."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct IcTxAbrtSource(pub u32);
+impl IcTxAbrtSource {
+    #[doc = "This field indicates that the Master is in 7-bit addressing mode and the address sent was not acknowledged by any slave. Reset value: 0x0 Role of DW_apb_i2c: Master-Transmitter or Master-Receiver"]
+    #[inline(always)]
+    pub const fn abrt_7b_addr_noack(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "This field indicates that the Master is in 7-bit addressing mode and the address sent was not acknowledged by any slave. Reset value: 0x0 Role of DW_apb_i2c: Master-Transmitter or Master-Receiver"]
+    #[inline(always)]
+    pub fn set_abrt_7b_addr_noack(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[doc = "This field indicates that the Master is in 10-bit address mode and the first 10-bit address byte was not acknowledged by any slave. Reset value: 0x0 Role of DW_apb_i2c: Master-Transmitter or Master-Receiver"]
+    #[inline(always)]
+    pub const fn abrt_10addr1_noack(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[doc = "This field indicates that the Master is in 10-bit address mode and the first 10-bit address byte was not acknowledged by any slave. Reset value: 0x0 Role of DW_apb_i2c: Master-Transmitter or Master-Receiver"]
+    #[inline(always)]
+    pub fn set_abrt_10addr1_noack(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+    #[doc = "This field indicates that the Master is in 10-bit address mode and that the second address byte of the 10-bit address was not acknowledged by any slave. Reset value: 0x0 Role of DW_apb_i2c: Master-Transmitter or Master-Receiver"]
+    #[inline(always)]
+    pub const fn abrt_10addr2_noack(&self) -> bool {
+        let val = (self.0 >> 2usize) & 0x01;
+        val != 0
+    }
+    #[doc = "This field indicates that the Master is in 10-bit address mode and that the second address byte of the 10-bit address was not acknowledged by any slave. Reset value: 0x0 Role of DW_apb_i2c: Master-Transmitter or Master-Receiver"]
+    #[inline(always)]
+    pub fn set_abrt_10addr2_noack(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+    }
+    #[doc = "This field indicates the master-mode only bit. When the master receives an acknowledgement for the address, but when it sends data byte(s) following the address, it did not receive an acknowledge from the remote slave(s). Reset value: 0x0 Role of DW_apb_i2c: Master-Transmitter"]
+    #[inline(always)]
+    pub const fn abrt_txdata_noack(&self) -> bool {
+        let val = (self.0 >> 3usize) & 0x01;
+        val != 0
+    }
+    #[doc = "This field indicates the master-mode only bit. When the master receives an acknowledgement for the address, but when it sends data byte(s) following the address, it did not receive an acknowledge from the remote slave(s). Reset value: 0x0 Role of DW_apb_i2c: Master-Transmitter"]
+    #[inline(always)]
+    pub fn set_abrt_txdata_noack(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
+    }
+    #[doc = "This field indicates that DW_apb_i2c in master mode has sent a General Call and no slave on the bus acknowledged the General Call. Reset value: 0x0 Role of DW_apb_i2c: Master-Transmitter"]
+    #[inline(always)]
+    pub const fn abrt_gcall_noack(&self) -> bool {
+        let val = (self.0 >> 4usize) & 0x01;
+        val != 0
+    }
+    #[doc = "This field indicates that DW_apb_i2c in master mode has sent a General Call and no slave on the bus acknowledged the General Call. Reset value: 0x0 Role of DW_apb_i2c: Master-Transmitter"]
+    #[inline(always)]
+    pub fn set_abrt_gcall_noack(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
+    }
+    #[doc = "This field indicates that DW_apb_i2c in the master mode has sent a General Call but the user programmed the byte following the General Call to be a read from the bus (IC_DATA_CMD\\[9\\] is set to 1). Reset value: 0x0 Role of DW_apb_i2c: Master-Transmitter"]
+    #[inline(always)]
+    pub const fn abrt_gcall_read(&self) -> bool {
+        let val = (self.0 >> 5usize) & 0x01;
+        val != 0
+    }
+    #[doc = "This field indicates that DW_apb_i2c in the master mode has sent a General Call but the user programmed the byte following the General Call to be a read from the bus (IC_DATA_CMD\\[9\\] is set to 1). Reset value: 0x0 Role of DW_apb_i2c: Master-Transmitter"]
+    #[inline(always)]
+    pub fn set_abrt_gcall_read(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
+    }
+    #[doc = "This field indicates that the Master is in High Speed mode and the High Speed Master code was acknowledged (wrong behavior). Reset value: 0x0 Role of DW_apb_i2c: Master"]
+    #[inline(always)]
+    pub const fn abrt_hs_ackdet(&self) -> bool {
+        let val = (self.0 >> 6usize) & 0x01;
+        val != 0
+    }
+    #[doc = "This field indicates that the Master is in High Speed mode and the High Speed Master code was acknowledged (wrong behavior). Reset value: 0x0 Role of DW_apb_i2c: Master"]
+    #[inline(always)]
+    pub fn set_abrt_hs_ackdet(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
+    }
+    #[doc = "This field indicates that the Master has sent a START Byte and the START Byte was acknowledged (wrong behavior). Reset value: 0x0 Role of DW_apb_i2c: Master"]
+    #[inline(always)]
+    pub const fn abrt_sbyte_ackdet(&self) -> bool {
+        let val = (self.0 >> 7usize) & 0x01;
+        val != 0
+    }
+    #[doc = "This field indicates that the Master has sent a START Byte and the START Byte was acknowledged (wrong behavior). Reset value: 0x0 Role of DW_apb_i2c: Master"]
+    #[inline(always)]
+    pub fn set_abrt_sbyte_ackdet(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
+    }
+    #[doc = "This field indicates that the restart is disabled (IC_RESTART_EN bit (IC_CON\\[5\\]) =0) and the user is trying to use the master to transfer data in High Speed mode. Reset value: 0x0 Role of DW_apb_i2c: Master-Transmitter or Master-Receiver"]
+    #[inline(always)]
+    pub const fn abrt_hs_norstrt(&self) -> bool {
+        let val = (self.0 >> 8usize) & 0x01;
+        val != 0
+    }
+    #[doc = "This field indicates that the restart is disabled (IC_RESTART_EN bit (IC_CON\\[5\\]) =0) and the user is trying to use the master to transfer data in High Speed mode. Reset value: 0x0 Role of DW_apb_i2c: Master-Transmitter or Master-Receiver"]
+    #[inline(always)]
+    pub fn set_abrt_hs_norstrt(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
+    }
+    #[doc = "To clear Bit 9, the source of the ABRT_SBYTE_NORSTRT must be fixed first; restart must be enabled (IC_CON\\[5\\]=1), the SPECIAL bit must be cleared (IC_TAR\\[11\\]), or the GC_OR_START bit must be cleared (IC_TAR\\[10\\]). Once the source of the ABRT_SBYTE_NORSTRT is fixed, then this bit can be cleared in the same manner as other bits in this register. If the source of the ABRT_SBYTE_NORSTRT is not fixed before attempting to clear this bit, bit 9 clears for one cycle and then gets reasserted. When this field is set to 1, the restart is disabled (IC_RESTART_EN bit (IC_CON\\[5\\]) =0) and the user is trying to send a START Byte. Reset value: 0x0 Role of DW_apb_i2c: Master"]
+    #[inline(always)]
+    pub const fn abrt_sbyte_norstrt(&self) -> bool {
+        let val = (self.0 >> 9usize) & 0x01;
+        val != 0
+    }
+    #[doc = "To clear Bit 9, the source of the ABRT_SBYTE_NORSTRT must be fixed first; restart must be enabled (IC_CON\\[5\\]=1), the SPECIAL bit must be cleared (IC_TAR\\[11\\]), or the GC_OR_START bit must be cleared (IC_TAR\\[10\\]). Once the source of the ABRT_SBYTE_NORSTRT is fixed, then this bit can be cleared in the same manner as other bits in this register. If the source of the ABRT_SBYTE_NORSTRT is not fixed before attempting to clear this bit, bit 9 clears for one cycle and then gets reasserted. When this field is set to 1, the restart is disabled (IC_RESTART_EN bit (IC_CON\\[5\\]) =0) and the user is trying to send a START Byte. Reset value: 0x0 Role of DW_apb_i2c: Master"]
+    #[inline(always)]
+    pub fn set_abrt_sbyte_norstrt(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
+    }
+    #[doc = "This field indicates that the restart is disabled (IC_RESTART_EN bit (IC_CON\\[5\\]) =0) and the master sends a read command in 10-bit addressing mode. Reset value: 0x0 Role of DW_apb_i2c: Master-Receiver"]
+    #[inline(always)]
+    pub const fn abrt_10b_rd_norstrt(&self) -> bool {
+        let val = (self.0 >> 10usize) & 0x01;
+        val != 0
+    }
+    #[doc = "This field indicates that the restart is disabled (IC_RESTART_EN bit (IC_CON\\[5\\]) =0) and the master sends a read command in 10-bit addressing mode. Reset value: 0x0 Role of DW_apb_i2c: Master-Receiver"]
+    #[inline(always)]
+    pub fn set_abrt_10b_rd_norstrt(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize);
+    }
+    #[doc = "This field indicates that the User tries to initiate a Master operation with the Master mode disabled. Reset value: 0x0 Role of DW_apb_i2c: Master-Transmitter or Master-Receiver"]
+    #[inline(always)]
+    pub const fn abrt_master_dis(&self) -> bool {
+        let val = (self.0 >> 11usize) & 0x01;
+        val != 0
+    }
+    #[doc = "This field indicates that the User tries to initiate a Master operation with the Master mode disabled. Reset value: 0x0 Role of DW_apb_i2c: Master-Transmitter or Master-Receiver"]
+    #[inline(always)]
+    pub fn set_abrt_master_dis(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
+    }
+    #[doc = "This field specifies that the Master has lost arbitration, or if IC_TX_ABRT_SOURCE\\[14\\] is also set, then the slave transmitter has lost arbitration. Reset value: 0x0 Role of DW_apb_i2c: Master-Transmitter or Slave-Transmitter"]
+    #[inline(always)]
+    pub const fn arb_lost(&self) -> bool {
+        let val = (self.0 >> 12usize) & 0x01;
+        val != 0
+    }
+    #[doc = "This field specifies that the Master has lost arbitration, or if IC_TX_ABRT_SOURCE\\[14\\] is also set, then the slave transmitter has lost arbitration. Reset value: 0x0 Role of DW_apb_i2c: Master-Transmitter or Slave-Transmitter"]
+    #[inline(always)]
+    pub fn set_arb_lost(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
+    }
+    #[doc = "This field specifies that the Slave has received a read command and some data exists in the TX FIFO, so the slave issues a TX_ABRT interrupt to flush old data in TX FIFO. Reset value: 0x0 Role of DW_apb_i2c: Slave-Transmitter"]
+    #[inline(always)]
+    pub const fn abrt_slvflush_txfifo(&self) -> bool {
+        let val = (self.0 >> 13usize) & 0x01;
+        val != 0
+    }
+    #[doc = "This field specifies that the Slave has received a read command and some data exists in the TX FIFO, so the slave issues a TX_ABRT interrupt to flush old data in TX FIFO. Reset value: 0x0 Role of DW_apb_i2c: Slave-Transmitter"]
+    #[inline(always)]
+    pub fn set_abrt_slvflush_txfifo(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize);
+    }
+    #[doc = "This field indicates that a Slave has lost the bus while transmitting data to a remote master. IC_TX_ABRT_SOURCE\\[12\\] is set at the same time. Note: Even though the slave never 'owns' the bus, something could go wrong on the bus. This is a fail safe check. For instance, during a data transmission at the low-to-high transition of SCL, if what is on the data bus is not what is supposed to be transmitted, then DW_apb_i2c no longer own the bus. Reset value: 0x0 Role of DW_apb_i2c: Slave-Transmitter"]
+    #[inline(always)]
+    pub const fn abrt_slv_arblost(&self) -> bool {
+        let val = (self.0 >> 14usize) & 0x01;
+        val != 0
+    }
+    #[doc = "This field indicates that a Slave has lost the bus while transmitting data to a remote master. IC_TX_ABRT_SOURCE\\[12\\] is set at the same time. Note: Even though the slave never 'owns' the bus, something could go wrong on the bus. This is a fail safe check. For instance, during a data transmission at the low-to-high transition of SCL, if what is on the data bus is not what is supposed to be transmitted, then DW_apb_i2c no longer own the bus. Reset value: 0x0 Role of DW_apb_i2c: Slave-Transmitter"]
+    #[inline(always)]
+    pub fn set_abrt_slv_arblost(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize);
+    }
+    #[doc = "1: When the processor side responds to a slave mode request for data to be transmitted to a remote master and user writes a 1 in CMD (bit 8) of IC_DATA_CMD register. Reset value: 0x0 Role of DW_apb_i2c: Slave-Transmitter"]
+    #[inline(always)]
+    pub const fn abrt_slvrd_intx(&self) -> bool {
+        let val = (self.0 >> 15usize) & 0x01;
+        val != 0
+    }
+    #[doc = "1: When the processor side responds to a slave mode request for data to be transmitted to a remote master and user writes a 1 in CMD (bit 8) of IC_DATA_CMD register. Reset value: 0x0 Role of DW_apb_i2c: Slave-Transmitter"]
+    #[inline(always)]
+    pub fn set_abrt_slvrd_intx(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize);
+    }
+    #[doc = "This is a master-mode-only bit. Master has detected the transfer abort (IC_ENABLE\\[1\\]) Reset value: 0x0 Role of DW_apb_i2c: Master-Transmitter"]
+    #[inline(always)]
+    pub const fn abrt_user_abrt(&self) -> bool {
+        let val = (self.0 >> 16usize) & 0x01;
+        val != 0
+    }
+    #[doc = "This is a master-mode-only bit. Master has detected the transfer abort (IC_ENABLE\\[1\\]) Reset value: 0x0 Role of DW_apb_i2c: Master-Transmitter"]
+    #[inline(always)]
+    pub fn set_abrt_user_abrt(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
+    }
+    #[doc = "This field indicates the number of Tx FIFO Data Commands which are flushed due to TX_ABRT interrupt. It is cleared whenever I2C is disabled. Reset value: 0x0 Role of DW_apb_i2c: Master-Transmitter or Slave-Transmitter"]
+    #[inline(always)]
+    pub const fn tx_flush_cnt(&self) -> u16 {
+        let val = (self.0 >> 23usize) & 0x01ff;
+        val as u16
+    }
+    #[doc = "This field indicates the number of Tx FIFO Data Commands which are flushed due to TX_ABRT interrupt. It is cleared whenever I2C is disabled. Reset value: 0x0 Role of DW_apb_i2c: Master-Transmitter or Slave-Transmitter"]
+    #[inline(always)]
+    pub fn set_tx_flush_cnt(&mut self, val: u16) {
+        self.0 = (self.0 & !(0x01ff << 23usize)) | (((val as u32) & 0x01ff) << 23usize);
+    }
+}
+impl Default for IcTxAbrtSource {
+    #[inline(always)]
+    fn default() -> IcTxAbrtSource {
+        IcTxAbrtSource(0)
+    }
+}
+#[doc = "I2C Transmit FIFO Threshold Register"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct IcTxTl(pub u32);
+impl IcTxTl {
+    #[doc = "Transmit FIFO Threshold Level. Controls the level of entries (or below) that trigger the TX_EMPTY interrupt (bit 4 in IC_RAW_INTR_STAT register). The valid range is 0-255, with the additional restriction that it may not be set to value larger than the depth of the buffer. If an attempt is made to do that, the actual value set will be the maximum depth of the buffer. A value of 0 sets the threshold for 0 entries, and a value of 255 sets the threshold for 255 entries."]
+    #[inline(always)]
+    pub const fn tx_tl(&self) -> u8 {
+        let val = (self.0 >> 0usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Transmit FIFO Threshold Level. Controls the level of entries (or below) that trigger the TX_EMPTY interrupt (bit 4 in IC_RAW_INTR_STAT register). The valid range is 0-255, with the additional restriction that it may not be set to value larger than the depth of the buffer. If an attempt is made to do that, the actual value set will be the maximum depth of the buffer. A value of 0 sets the threshold for 0 entries, and a value of 255 sets the threshold for 255 entries."]
+    #[inline(always)]
+    pub fn set_tx_tl(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize);
+    }
+}
+impl Default for IcTxTl {
+    #[inline(always)]
+    fn default() -> IcTxTl {
+        IcTxTl(0)
+    }
+}
+#[doc = "I2C Transmit FIFO Level Register This register contains the number of valid data entries in the transmit FIFO buffer. It is cleared whenever: - The I2C is disabled - There is a transmit abort - that is, TX_ABRT bit is set in the IC_RAW_INTR_STAT register - The slave bulk transmit mode is aborted The register increments whenever data is placed into the transmit FIFO and decrements when data is taken from the transmit FIFO."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct IcTxflr(pub u32);
+impl IcTxflr {
+    #[doc = "Transmit FIFO Level. Contains the number of valid data entries in the transmit FIFO. Reset value: 0x0"]
+    #[inline(always)]
+    pub const fn txflr(&self) -> u8 {
+        let val = (self.0 >> 0usize) & 0x1f;
+        val as u8
+    }
+    #[doc = "Transmit FIFO Level. Contains the number of valid data entries in the transmit FIFO. Reset value: 0x0"]
+    #[inline(always)]
+    pub fn set_txflr(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x1f << 0usize)) | (((val as u32) & 0x1f) << 0usize);
+    }
+}
+impl Default for IcTxflr {
+    #[inline(always)]
+    fn default() -> IcTxflr {
+        IcTxflr(0)
+    }
+}
diff --git a/src/rp2350/i2c/vals.rs b/src/rp2350/i2c/vals.rs
new file mode 100644
index 00000000..41e0860e
--- /dev/null
+++ b/src/rp2350/i2c/vals.rs
@@ -0,0 +1,33 @@
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Speed {
+    _RESERVED_0 = 0,
+    #[doc = "Standard Speed mode of operation"]
+    STANDARD = 0x01,
+    #[doc = "Fast or Fast Plus mode of operation"]
+    FAST = 0x02,
+    #[doc = "High Speed mode of operation"]
+    HIGH = 0x03,
+}
+impl Speed {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Speed {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Speed {
+    #[inline(always)]
+    fn from(val: u8) -> Speed {
+        Speed::from_bits(val)
+    }
+}
+impl From<Speed> for u8 {
+    #[inline(always)]
+    fn from(val: Speed) -> u8 {
+        Speed::to_bits(val)
+    }
+}
diff --git a/src/rp2350/io.rs b/src/rp2350/io.rs
new file mode 100644
index 00000000..ad3be7d7
--- /dev/null
+++ b/src/rp2350/io.rs
@@ -0,0 +1,168 @@
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Gpio {
+    ptr: *mut u8,
+}
+unsafe impl Send for Gpio {}
+unsafe impl Sync for Gpio {}
+impl Gpio {
+    #[inline(always)]
+    pub const unsafe fn from_ptr(ptr: *mut ()) -> Self {
+        Self { ptr: ptr as _ }
+    }
+    #[inline(always)]
+    pub const fn as_ptr(&self) -> *mut () {
+        self.ptr as _
+    }
+    #[inline(always)]
+    pub const fn status(self) -> crate::common::Reg<regs::GpioStatus, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(0usize) as _) }
+    }
+    #[inline(always)]
+    pub const fn ctrl(self) -> crate::common::Reg<regs::GpioCtrl, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(4usize) as _) }
+    }
+}
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Int {
+    ptr: *mut u8,
+}
+unsafe impl Send for Int {}
+unsafe impl Sync for Int {}
+impl Int {
+    #[inline(always)]
+    pub const unsafe fn from_ptr(ptr: *mut ()) -> Self {
+        Self { ptr: ptr as _ }
+    }
+    #[inline(always)]
+    pub const fn as_ptr(&self) -> *mut () {
+        self.ptr as _
+    }
+    #[doc = "Interrupt Enable for proc1"]
+    #[inline(always)]
+    pub const fn inte(self, n: usize) -> crate::common::Reg<regs::Int, crate::common::RW> {
+        assert!(n < 6usize);
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(0usize + n * 4usize) as _) }
+    }
+    #[doc = "Interrupt Force for proc1"]
+    #[inline(always)]
+    pub const fn intf(self, n: usize) -> crate::common::Reg<regs::Int, crate::common::RW> {
+        assert!(n < 6usize);
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(24usize + n * 4usize) as _) }
+    }
+    #[doc = "Interrupt status after masking & forcing for proc1"]
+    #[inline(always)]
+    pub const fn ints(self, n: usize) -> crate::common::Reg<regs::Int, crate::common::RW> {
+        assert!(n < 6usize);
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(48usize + n * 4usize) as _) }
+    }
+}
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Io {
+    ptr: *mut u8,
+}
+unsafe impl Send for Io {}
+unsafe impl Sync for Io {}
+impl Io {
+    #[inline(always)]
+    pub const unsafe fn from_ptr(ptr: *mut ()) -> Self {
+        Self { ptr: ptr as _ }
+    }
+    #[inline(always)]
+    pub const fn as_ptr(&self) -> *mut () {
+        self.ptr as _
+    }
+    #[inline(always)]
+    pub const fn gpio(self, n: usize) -> Gpio {
+        assert!(n < 48usize);
+        unsafe { Gpio::from_ptr(self.ptr.add(0usize + n * 8usize) as _) }
+    }
+    #[inline(always)]
+    pub const fn irqsummary_proc0_secure0(
+        self,
+    ) -> crate::common::Reg<regs::IrqsummaryProc0secure0, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(512usize) as _) }
+    }
+    #[inline(always)]
+    pub const fn irqsummary_proc0_secure1(
+        self,
+    ) -> crate::common::Reg<regs::IrqsummaryProc0secure1, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(516usize) as _) }
+    }
+    #[inline(always)]
+    pub const fn irqsummary_proc0_nonsecure0(
+        self,
+    ) -> crate::common::Reg<regs::IrqsummaryProc0nonsecure0, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(520usize) as _) }
+    }
+    #[inline(always)]
+    pub const fn irqsummary_proc0_nonsecure1(
+        self,
+    ) -> crate::common::Reg<regs::IrqsummaryProc0nonsecure1, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(524usize) as _) }
+    }
+    #[inline(always)]
+    pub const fn irqsummary_proc1_secure0(
+        self,
+    ) -> crate::common::Reg<regs::IrqsummaryProc1secure0, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(528usize) as _) }
+    }
+    #[inline(always)]
+    pub const fn irqsummary_proc1_secure1(
+        self,
+    ) -> crate::common::Reg<regs::IrqsummaryProc1secure1, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(532usize) as _) }
+    }
+    #[inline(always)]
+    pub const fn irqsummary_proc1_nonsecure0(
+        self,
+    ) -> crate::common::Reg<regs::IrqsummaryProc1nonsecure0, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(536usize) as _) }
+    }
+    #[inline(always)]
+    pub const fn irqsummary_proc1_nonsecure1(
+        self,
+    ) -> crate::common::Reg<regs::IrqsummaryProc1nonsecure1, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(540usize) as _) }
+    }
+    #[inline(always)]
+    pub const fn irqsummary_dormant_wake_secure0(
+        self,
+    ) -> crate::common::Reg<regs::IrqsummaryDormantWakeSecure0, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(544usize) as _) }
+    }
+    #[inline(always)]
+    pub const fn irqsummary_dormant_wake_secure1(
+        self,
+    ) -> crate::common::Reg<regs::IrqsummaryDormantWakeSecure1, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(548usize) as _) }
+    }
+    #[inline(always)]
+    pub const fn irqsummary_dormant_wake_nonsecure0(
+        self,
+    ) -> crate::common::Reg<regs::IrqsummaryDormantWakeNonsecure0, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(552usize) as _) }
+    }
+    #[inline(always)]
+    pub const fn irqsummary_dormant_wake_nonsecure1(
+        self,
+    ) -> crate::common::Reg<regs::IrqsummaryDormantWakeNonsecure1, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(556usize) as _) }
+    }
+    #[doc = "Raw Interrupts"]
+    #[inline(always)]
+    pub const fn intr(self, n: usize) -> crate::common::Reg<regs::Int, crate::common::RW> {
+        assert!(n < 6usize);
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(560usize + n * 4usize) as _) }
+    }
+    #[inline(always)]
+    pub const fn int_proc(self, n: usize) -> Int {
+        assert!(n < 2usize);
+        unsafe { Int::from_ptr(self.ptr.add(584usize + n * 72usize) as _) }
+    }
+    #[inline(always)]
+    pub const fn int_dormant_wake(self) -> Int {
+        unsafe { Int::from_ptr(self.ptr.add(728usize) as _) }
+    }
+}
+pub mod regs;
+pub mod vals;
diff --git a/src/rp2350/io/regs.rs b/src/rp2350/io/regs.rs
new file mode 100644
index 00000000..c67ddcf6
--- /dev/null
+++ b/src/rp2350/io/regs.rs
@@ -0,0 +1,2901 @@
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct GpioCtrl(pub u32);
+impl GpioCtrl {
+    #[doc = "0-31 -> selects pin function according to the gpio table 31 == NULL"]
+    #[inline(always)]
+    pub const fn funcsel(&self) -> u8 {
+        let val = (self.0 >> 0usize) & 0x1f;
+        val as u8
+    }
+    #[doc = "0-31 -> selects pin function according to the gpio table 31 == NULL"]
+    #[inline(always)]
+    pub fn set_funcsel(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x1f << 0usize)) | (((val as u32) & 0x1f) << 0usize);
+    }
+    #[inline(always)]
+    pub const fn outover(&self) -> super::vals::Outover {
+        let val = (self.0 >> 12usize) & 0x03;
+        super::vals::Outover::from_bits(val as u8)
+    }
+    #[inline(always)]
+    pub fn set_outover(&mut self, val: super::vals::Outover) {
+        self.0 = (self.0 & !(0x03 << 12usize)) | (((val.to_bits() as u32) & 0x03) << 12usize);
+    }
+    #[inline(always)]
+    pub const fn oeover(&self) -> super::vals::Oeover {
+        let val = (self.0 >> 14usize) & 0x03;
+        super::vals::Oeover::from_bits(val as u8)
+    }
+    #[inline(always)]
+    pub fn set_oeover(&mut self, val: super::vals::Oeover) {
+        self.0 = (self.0 & !(0x03 << 14usize)) | (((val.to_bits() as u32) & 0x03) << 14usize);
+    }
+    #[inline(always)]
+    pub const fn inover(&self) -> super::vals::Inover {
+        let val = (self.0 >> 16usize) & 0x03;
+        super::vals::Inover::from_bits(val as u8)
+    }
+    #[inline(always)]
+    pub fn set_inover(&mut self, val: super::vals::Inover) {
+        self.0 = (self.0 & !(0x03 << 16usize)) | (((val.to_bits() as u32) & 0x03) << 16usize);
+    }
+    #[inline(always)]
+    pub const fn irqover(&self) -> super::vals::Irqover {
+        let val = (self.0 >> 28usize) & 0x03;
+        super::vals::Irqover::from_bits(val as u8)
+    }
+    #[inline(always)]
+    pub fn set_irqover(&mut self, val: super::vals::Irqover) {
+        self.0 = (self.0 & !(0x03 << 28usize)) | (((val.to_bits() as u32) & 0x03) << 28usize);
+    }
+}
+impl Default for GpioCtrl {
+    #[inline(always)]
+    fn default() -> GpioCtrl {
+        GpioCtrl(0)
+    }
+}
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct GpioStatus(pub u32);
+impl GpioStatus {
+    #[doc = "output signal to pad after register override is applied"]
+    #[inline(always)]
+    pub const fn outtopad(&self) -> bool {
+        let val = (self.0 >> 9usize) & 0x01;
+        val != 0
+    }
+    #[doc = "output signal to pad after register override is applied"]
+    #[inline(always)]
+    pub fn set_outtopad(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
+    }
+    #[doc = "output enable to pad after register override is applied"]
+    #[inline(always)]
+    pub const fn oetopad(&self) -> bool {
+        let val = (self.0 >> 13usize) & 0x01;
+        val != 0
+    }
+    #[doc = "output enable to pad after register override is applied"]
+    #[inline(always)]
+    pub fn set_oetopad(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize);
+    }
+    #[doc = "input signal from pad, before filtering and override are applied"]
+    #[inline(always)]
+    pub const fn infrompad(&self) -> bool {
+        let val = (self.0 >> 17usize) & 0x01;
+        val != 0
+    }
+    #[doc = "input signal from pad, before filtering and override are applied"]
+    #[inline(always)]
+    pub fn set_infrompad(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
+    }
+    #[doc = "interrupt to processors, after override is applied"]
+    #[inline(always)]
+    pub const fn irqtoproc(&self) -> bool {
+        let val = (self.0 >> 26usize) & 0x01;
+        val != 0
+    }
+    #[doc = "interrupt to processors, after override is applied"]
+    #[inline(always)]
+    pub fn set_irqtoproc(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 26usize)) | (((val as u32) & 0x01) << 26usize);
+    }
+}
+impl Default for GpioStatus {
+    #[inline(always)]
+    fn default() -> GpioStatus {
+        GpioStatus(0)
+    }
+}
+#[doc = "Interrupt Enable for proc1"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Int(pub u32);
+impl Int {
+    #[inline(always)]
+    pub const fn level_low(&self, n: usize) -> bool {
+        assert!(n < 8usize);
+        let offs = 0usize + n * 4usize;
+        let val = (self.0 >> offs) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_level_low(&mut self, n: usize, val: bool) {
+        assert!(n < 8usize);
+        let offs = 0usize + n * 4usize;
+        self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
+    }
+    #[inline(always)]
+    pub const fn level_high(&self, n: usize) -> bool {
+        assert!(n < 8usize);
+        let offs = 1usize + n * 4usize;
+        let val = (self.0 >> offs) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_level_high(&mut self, n: usize, val: bool) {
+        assert!(n < 8usize);
+        let offs = 1usize + n * 4usize;
+        self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
+    }
+    #[inline(always)]
+    pub const fn edge_low(&self, n: usize) -> bool {
+        assert!(n < 8usize);
+        let offs = 2usize + n * 4usize;
+        let val = (self.0 >> offs) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_edge_low(&mut self, n: usize, val: bool) {
+        assert!(n < 8usize);
+        let offs = 2usize + n * 4usize;
+        self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
+    }
+    #[inline(always)]
+    pub const fn edge_high(&self, n: usize) -> bool {
+        assert!(n < 8usize);
+        let offs = 3usize + n * 4usize;
+        let val = (self.0 >> offs) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_edge_high(&mut self, n: usize, val: bool) {
+        assert!(n < 8usize);
+        let offs = 3usize + n * 4usize;
+        self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
+    }
+}
+impl Default for Int {
+    #[inline(always)]
+    fn default() -> Int {
+        Int(0)
+    }
+}
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct IrqsummaryDormantWakeNonsecure0(pub u32);
+impl IrqsummaryDormantWakeNonsecure0 {
+    #[inline(always)]
+    pub const fn gpio0(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio0(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[inline(always)]
+    pub const fn gpio1(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio1(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+    #[inline(always)]
+    pub const fn gpio2(&self) -> bool {
+        let val = (self.0 >> 2usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio2(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+    }
+    #[inline(always)]
+    pub const fn gpio3(&self) -> bool {
+        let val = (self.0 >> 3usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio3(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
+    }
+    #[inline(always)]
+    pub const fn gpio4(&self) -> bool {
+        let val = (self.0 >> 4usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio4(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
+    }
+    #[inline(always)]
+    pub const fn gpio5(&self) -> bool {
+        let val = (self.0 >> 5usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio5(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
+    }
+    #[inline(always)]
+    pub const fn gpio6(&self) -> bool {
+        let val = (self.0 >> 6usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio6(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
+    }
+    #[inline(always)]
+    pub const fn gpio7(&self) -> bool {
+        let val = (self.0 >> 7usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio7(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
+    }
+    #[inline(always)]
+    pub const fn gpio8(&self) -> bool {
+        let val = (self.0 >> 8usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio8(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
+    }
+    #[inline(always)]
+    pub const fn gpio9(&self) -> bool {
+        let val = (self.0 >> 9usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio9(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
+    }
+    #[inline(always)]
+    pub const fn gpio10(&self) -> bool {
+        let val = (self.0 >> 10usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio10(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize);
+    }
+    #[inline(always)]
+    pub const fn gpio11(&self) -> bool {
+        let val = (self.0 >> 11usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio11(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
+    }
+    #[inline(always)]
+    pub const fn gpio12(&self) -> bool {
+        let val = (self.0 >> 12usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio12(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
+    }
+    #[inline(always)]
+    pub const fn gpio13(&self) -> bool {
+        let val = (self.0 >> 13usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio13(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize);
+    }
+    #[inline(always)]
+    pub const fn gpio14(&self) -> bool {
+        let val = (self.0 >> 14usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio14(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize);
+    }
+    #[inline(always)]
+    pub const fn gpio15(&self) -> bool {
+        let val = (self.0 >> 15usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio15(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize);
+    }
+    #[inline(always)]
+    pub const fn gpio16(&self) -> bool {
+        let val = (self.0 >> 16usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio16(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
+    }
+    #[inline(always)]
+    pub const fn gpio17(&self) -> bool {
+        let val = (self.0 >> 17usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio17(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
+    }
+    #[inline(always)]
+    pub const fn gpio18(&self) -> bool {
+        let val = (self.0 >> 18usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio18(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize);
+    }
+    #[inline(always)]
+    pub const fn gpio19(&self) -> bool {
+        let val = (self.0 >> 19usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio19(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize);
+    }
+    #[inline(always)]
+    pub const fn gpio20(&self) -> bool {
+        let val = (self.0 >> 20usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio20(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize);
+    }
+    #[inline(always)]
+    pub const fn gpio21(&self) -> bool {
+        let val = (self.0 >> 21usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio21(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 21usize)) | (((val as u32) & 0x01) << 21usize);
+    }
+    #[inline(always)]
+    pub const fn gpio22(&self) -> bool {
+        let val = (self.0 >> 22usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio22(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 22usize)) | (((val as u32) & 0x01) << 22usize);
+    }
+    #[inline(always)]
+    pub const fn gpio23(&self) -> bool {
+        let val = (self.0 >> 23usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio23(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 23usize)) | (((val as u32) & 0x01) << 23usize);
+    }
+    #[inline(always)]
+    pub const fn gpio24(&self) -> bool {
+        let val = (self.0 >> 24usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio24(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 24usize)) | (((val as u32) & 0x01) << 24usize);
+    }
+    #[inline(always)]
+    pub const fn gpio25(&self) -> bool {
+        let val = (self.0 >> 25usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio25(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 25usize)) | (((val as u32) & 0x01) << 25usize);
+    }
+    #[inline(always)]
+    pub const fn gpio26(&self) -> bool {
+        let val = (self.0 >> 26usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio26(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 26usize)) | (((val as u32) & 0x01) << 26usize);
+    }
+    #[inline(always)]
+    pub const fn gpio27(&self) -> bool {
+        let val = (self.0 >> 27usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio27(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 27usize)) | (((val as u32) & 0x01) << 27usize);
+    }
+    #[inline(always)]
+    pub const fn gpio28(&self) -> bool {
+        let val = (self.0 >> 28usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio28(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 28usize)) | (((val as u32) & 0x01) << 28usize);
+    }
+    #[inline(always)]
+    pub const fn gpio29(&self) -> bool {
+        let val = (self.0 >> 29usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio29(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 29usize)) | (((val as u32) & 0x01) << 29usize);
+    }
+    #[inline(always)]
+    pub const fn gpio30(&self) -> bool {
+        let val = (self.0 >> 30usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio30(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 30usize)) | (((val as u32) & 0x01) << 30usize);
+    }
+    #[inline(always)]
+    pub const fn gpio31(&self) -> bool {
+        let val = (self.0 >> 31usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio31(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 31usize)) | (((val as u32) & 0x01) << 31usize);
+    }
+}
+impl Default for IrqsummaryDormantWakeNonsecure0 {
+    #[inline(always)]
+    fn default() -> IrqsummaryDormantWakeNonsecure0 {
+        IrqsummaryDormantWakeNonsecure0(0)
+    }
+}
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct IrqsummaryDormantWakeNonsecure1(pub u32);
+impl IrqsummaryDormantWakeNonsecure1 {
+    #[inline(always)]
+    pub const fn gpio32(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio32(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[inline(always)]
+    pub const fn gpio33(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio33(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+    #[inline(always)]
+    pub const fn gpio34(&self) -> bool {
+        let val = (self.0 >> 2usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio34(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+    }
+    #[inline(always)]
+    pub const fn gpio35(&self) -> bool {
+        let val = (self.0 >> 3usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio35(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
+    }
+    #[inline(always)]
+    pub const fn gpio36(&self) -> bool {
+        let val = (self.0 >> 4usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio36(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
+    }
+    #[inline(always)]
+    pub const fn gpio37(&self) -> bool {
+        let val = (self.0 >> 5usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio37(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
+    }
+    #[inline(always)]
+    pub const fn gpio38(&self) -> bool {
+        let val = (self.0 >> 6usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio38(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
+    }
+    #[inline(always)]
+    pub const fn gpio39(&self) -> bool {
+        let val = (self.0 >> 7usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio39(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
+    }
+    #[inline(always)]
+    pub const fn gpio40(&self) -> bool {
+        let val = (self.0 >> 8usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio40(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
+    }
+    #[inline(always)]
+    pub const fn gpio41(&self) -> bool {
+        let val = (self.0 >> 9usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio41(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
+    }
+    #[inline(always)]
+    pub const fn gpio42(&self) -> bool {
+        let val = (self.0 >> 10usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio42(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize);
+    }
+    #[inline(always)]
+    pub const fn gpio43(&self) -> bool {
+        let val = (self.0 >> 11usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio43(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
+    }
+    #[inline(always)]
+    pub const fn gpio44(&self) -> bool {
+        let val = (self.0 >> 12usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio44(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
+    }
+    #[inline(always)]
+    pub const fn gpio45(&self) -> bool {
+        let val = (self.0 >> 13usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio45(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize);
+    }
+    #[inline(always)]
+    pub const fn gpio46(&self) -> bool {
+        let val = (self.0 >> 14usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio46(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize);
+    }
+    #[inline(always)]
+    pub const fn gpio47(&self) -> bool {
+        let val = (self.0 >> 15usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio47(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize);
+    }
+}
+impl Default for IrqsummaryDormantWakeNonsecure1 {
+    #[inline(always)]
+    fn default() -> IrqsummaryDormantWakeNonsecure1 {
+        IrqsummaryDormantWakeNonsecure1(0)
+    }
+}
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct IrqsummaryDormantWakeSecure0(pub u32);
+impl IrqsummaryDormantWakeSecure0 {
+    #[inline(always)]
+    pub const fn gpio0(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio0(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[inline(always)]
+    pub const fn gpio1(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio1(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+    #[inline(always)]
+    pub const fn gpio2(&self) -> bool {
+        let val = (self.0 >> 2usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio2(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+    }
+    #[inline(always)]
+    pub const fn gpio3(&self) -> bool {
+        let val = (self.0 >> 3usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio3(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
+    }
+    #[inline(always)]
+    pub const fn gpio4(&self) -> bool {
+        let val = (self.0 >> 4usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio4(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
+    }
+    #[inline(always)]
+    pub const fn gpio5(&self) -> bool {
+        let val = (self.0 >> 5usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio5(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
+    }
+    #[inline(always)]
+    pub const fn gpio6(&self) -> bool {
+        let val = (self.0 >> 6usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio6(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
+    }
+    #[inline(always)]
+    pub const fn gpio7(&self) -> bool {
+        let val = (self.0 >> 7usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio7(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
+    }
+    #[inline(always)]
+    pub const fn gpio8(&self) -> bool {
+        let val = (self.0 >> 8usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio8(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
+    }
+    #[inline(always)]
+    pub const fn gpio9(&self) -> bool {
+        let val = (self.0 >> 9usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio9(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
+    }
+    #[inline(always)]
+    pub const fn gpio10(&self) -> bool {
+        let val = (self.0 >> 10usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio10(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize);
+    }
+    #[inline(always)]
+    pub const fn gpio11(&self) -> bool {
+        let val = (self.0 >> 11usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio11(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
+    }
+    #[inline(always)]
+    pub const fn gpio12(&self) -> bool {
+        let val = (self.0 >> 12usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio12(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
+    }
+    #[inline(always)]
+    pub const fn gpio13(&self) -> bool {
+        let val = (self.0 >> 13usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio13(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize);
+    }
+    #[inline(always)]
+    pub const fn gpio14(&self) -> bool {
+        let val = (self.0 >> 14usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio14(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize);
+    }
+    #[inline(always)]
+    pub const fn gpio15(&self) -> bool {
+        let val = (self.0 >> 15usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio15(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize);
+    }
+    #[inline(always)]
+    pub const fn gpio16(&self) -> bool {
+        let val = (self.0 >> 16usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio16(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
+    }
+    #[inline(always)]
+    pub const fn gpio17(&self) -> bool {
+        let val = (self.0 >> 17usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio17(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
+    }
+    #[inline(always)]
+    pub const fn gpio18(&self) -> bool {
+        let val = (self.0 >> 18usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio18(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize);
+    }
+    #[inline(always)]
+    pub const fn gpio19(&self) -> bool {
+        let val = (self.0 >> 19usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio19(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize);
+    }
+    #[inline(always)]
+    pub const fn gpio20(&self) -> bool {
+        let val = (self.0 >> 20usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio20(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize);
+    }
+    #[inline(always)]
+    pub const fn gpio21(&self) -> bool {
+        let val = (self.0 >> 21usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio21(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 21usize)) | (((val as u32) & 0x01) << 21usize);
+    }
+    #[inline(always)]
+    pub const fn gpio22(&self) -> bool {
+        let val = (self.0 >> 22usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio22(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 22usize)) | (((val as u32) & 0x01) << 22usize);
+    }
+    #[inline(always)]
+    pub const fn gpio23(&self) -> bool {
+        let val = (self.0 >> 23usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio23(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 23usize)) | (((val as u32) & 0x01) << 23usize);
+    }
+    #[inline(always)]
+    pub const fn gpio24(&self) -> bool {
+        let val = (self.0 >> 24usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio24(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 24usize)) | (((val as u32) & 0x01) << 24usize);
+    }
+    #[inline(always)]
+    pub const fn gpio25(&self) -> bool {
+        let val = (self.0 >> 25usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio25(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 25usize)) | (((val as u32) & 0x01) << 25usize);
+    }
+    #[inline(always)]
+    pub const fn gpio26(&self) -> bool {
+        let val = (self.0 >> 26usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio26(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 26usize)) | (((val as u32) & 0x01) << 26usize);
+    }
+    #[inline(always)]
+    pub const fn gpio27(&self) -> bool {
+        let val = (self.0 >> 27usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio27(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 27usize)) | (((val as u32) & 0x01) << 27usize);
+    }
+    #[inline(always)]
+    pub const fn gpio28(&self) -> bool {
+        let val = (self.0 >> 28usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio28(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 28usize)) | (((val as u32) & 0x01) << 28usize);
+    }
+    #[inline(always)]
+    pub const fn gpio29(&self) -> bool {
+        let val = (self.0 >> 29usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio29(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 29usize)) | (((val as u32) & 0x01) << 29usize);
+    }
+    #[inline(always)]
+    pub const fn gpio30(&self) -> bool {
+        let val = (self.0 >> 30usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio30(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 30usize)) | (((val as u32) & 0x01) << 30usize);
+    }
+    #[inline(always)]
+    pub const fn gpio31(&self) -> bool {
+        let val = (self.0 >> 31usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio31(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 31usize)) | (((val as u32) & 0x01) << 31usize);
+    }
+}
+impl Default for IrqsummaryDormantWakeSecure0 {
+    #[inline(always)]
+    fn default() -> IrqsummaryDormantWakeSecure0 {
+        IrqsummaryDormantWakeSecure0(0)
+    }
+}
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct IrqsummaryDormantWakeSecure1(pub u32);
+impl IrqsummaryDormantWakeSecure1 {
+    #[inline(always)]
+    pub const fn gpio32(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio32(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[inline(always)]
+    pub const fn gpio33(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio33(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+    #[inline(always)]
+    pub const fn gpio34(&self) -> bool {
+        let val = (self.0 >> 2usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio34(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+    }
+    #[inline(always)]
+    pub const fn gpio35(&self) -> bool {
+        let val = (self.0 >> 3usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio35(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
+    }
+    #[inline(always)]
+    pub const fn gpio36(&self) -> bool {
+        let val = (self.0 >> 4usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio36(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
+    }
+    #[inline(always)]
+    pub const fn gpio37(&self) -> bool {
+        let val = (self.0 >> 5usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio37(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
+    }
+    #[inline(always)]
+    pub const fn gpio38(&self) -> bool {
+        let val = (self.0 >> 6usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio38(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
+    }
+    #[inline(always)]
+    pub const fn gpio39(&self) -> bool {
+        let val = (self.0 >> 7usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio39(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
+    }
+    #[inline(always)]
+    pub const fn gpio40(&self) -> bool {
+        let val = (self.0 >> 8usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio40(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
+    }
+    #[inline(always)]
+    pub const fn gpio41(&self) -> bool {
+        let val = (self.0 >> 9usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio41(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
+    }
+    #[inline(always)]
+    pub const fn gpio42(&self) -> bool {
+        let val = (self.0 >> 10usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio42(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize);
+    }
+    #[inline(always)]
+    pub const fn gpio43(&self) -> bool {
+        let val = (self.0 >> 11usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio43(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
+    }
+    #[inline(always)]
+    pub const fn gpio44(&self) -> bool {
+        let val = (self.0 >> 12usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio44(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
+    }
+    #[inline(always)]
+    pub const fn gpio45(&self) -> bool {
+        let val = (self.0 >> 13usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio45(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize);
+    }
+    #[inline(always)]
+    pub const fn gpio46(&self) -> bool {
+        let val = (self.0 >> 14usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio46(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize);
+    }
+    #[inline(always)]
+    pub const fn gpio47(&self) -> bool {
+        let val = (self.0 >> 15usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio47(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize);
+    }
+}
+impl Default for IrqsummaryDormantWakeSecure1 {
+    #[inline(always)]
+    fn default() -> IrqsummaryDormantWakeSecure1 {
+        IrqsummaryDormantWakeSecure1(0)
+    }
+}
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct IrqsummaryProc0nonsecure0(pub u32);
+impl IrqsummaryProc0nonsecure0 {
+    #[inline(always)]
+    pub const fn gpio0(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio0(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[inline(always)]
+    pub const fn gpio1(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio1(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+    #[inline(always)]
+    pub const fn gpio2(&self) -> bool {
+        let val = (self.0 >> 2usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio2(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+    }
+    #[inline(always)]
+    pub const fn gpio3(&self) -> bool {
+        let val = (self.0 >> 3usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio3(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
+    }
+    #[inline(always)]
+    pub const fn gpio4(&self) -> bool {
+        let val = (self.0 >> 4usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio4(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
+    }
+    #[inline(always)]
+    pub const fn gpio5(&self) -> bool {
+        let val = (self.0 >> 5usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio5(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
+    }
+    #[inline(always)]
+    pub const fn gpio6(&self) -> bool {
+        let val = (self.0 >> 6usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio6(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
+    }
+    #[inline(always)]
+    pub const fn gpio7(&self) -> bool {
+        let val = (self.0 >> 7usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio7(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
+    }
+    #[inline(always)]
+    pub const fn gpio8(&self) -> bool {
+        let val = (self.0 >> 8usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio8(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
+    }
+    #[inline(always)]
+    pub const fn gpio9(&self) -> bool {
+        let val = (self.0 >> 9usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio9(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
+    }
+    #[inline(always)]
+    pub const fn gpio10(&self) -> bool {
+        let val = (self.0 >> 10usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio10(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize);
+    }
+    #[inline(always)]
+    pub const fn gpio11(&self) -> bool {
+        let val = (self.0 >> 11usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio11(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
+    }
+    #[inline(always)]
+    pub const fn gpio12(&self) -> bool {
+        let val = (self.0 >> 12usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio12(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
+    }
+    #[inline(always)]
+    pub const fn gpio13(&self) -> bool {
+        let val = (self.0 >> 13usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio13(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize);
+    }
+    #[inline(always)]
+    pub const fn gpio14(&self) -> bool {
+        let val = (self.0 >> 14usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio14(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize);
+    }
+    #[inline(always)]
+    pub const fn gpio15(&self) -> bool {
+        let val = (self.0 >> 15usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio15(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize);
+    }
+    #[inline(always)]
+    pub const fn gpio16(&self) -> bool {
+        let val = (self.0 >> 16usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio16(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
+    }
+    #[inline(always)]
+    pub const fn gpio17(&self) -> bool {
+        let val = (self.0 >> 17usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio17(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
+    }
+    #[inline(always)]
+    pub const fn gpio18(&self) -> bool {
+        let val = (self.0 >> 18usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio18(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize);
+    }
+    #[inline(always)]
+    pub const fn gpio19(&self) -> bool {
+        let val = (self.0 >> 19usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio19(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize);
+    }
+    #[inline(always)]
+    pub const fn gpio20(&self) -> bool {
+        let val = (self.0 >> 20usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio20(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize);
+    }
+    #[inline(always)]
+    pub const fn gpio21(&self) -> bool {
+        let val = (self.0 >> 21usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio21(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 21usize)) | (((val as u32) & 0x01) << 21usize);
+    }
+    #[inline(always)]
+    pub const fn gpio22(&self) -> bool {
+        let val = (self.0 >> 22usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio22(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 22usize)) | (((val as u32) & 0x01) << 22usize);
+    }
+    #[inline(always)]
+    pub const fn gpio23(&self) -> bool {
+        let val = (self.0 >> 23usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio23(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 23usize)) | (((val as u32) & 0x01) << 23usize);
+    }
+    #[inline(always)]
+    pub const fn gpio24(&self) -> bool {
+        let val = (self.0 >> 24usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio24(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 24usize)) | (((val as u32) & 0x01) << 24usize);
+    }
+    #[inline(always)]
+    pub const fn gpio25(&self) -> bool {
+        let val = (self.0 >> 25usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio25(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 25usize)) | (((val as u32) & 0x01) << 25usize);
+    }
+    #[inline(always)]
+    pub const fn gpio26(&self) -> bool {
+        let val = (self.0 >> 26usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio26(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 26usize)) | (((val as u32) & 0x01) << 26usize);
+    }
+    #[inline(always)]
+    pub const fn gpio27(&self) -> bool {
+        let val = (self.0 >> 27usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio27(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 27usize)) | (((val as u32) & 0x01) << 27usize);
+    }
+    #[inline(always)]
+    pub const fn gpio28(&self) -> bool {
+        let val = (self.0 >> 28usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio28(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 28usize)) | (((val as u32) & 0x01) << 28usize);
+    }
+    #[inline(always)]
+    pub const fn gpio29(&self) -> bool {
+        let val = (self.0 >> 29usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio29(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 29usize)) | (((val as u32) & 0x01) << 29usize);
+    }
+    #[inline(always)]
+    pub const fn gpio30(&self) -> bool {
+        let val = (self.0 >> 30usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio30(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 30usize)) | (((val as u32) & 0x01) << 30usize);
+    }
+    #[inline(always)]
+    pub const fn gpio31(&self) -> bool {
+        let val = (self.0 >> 31usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio31(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 31usize)) | (((val as u32) & 0x01) << 31usize);
+    }
+}
+impl Default for IrqsummaryProc0nonsecure0 {
+    #[inline(always)]
+    fn default() -> IrqsummaryProc0nonsecure0 {
+        IrqsummaryProc0nonsecure0(0)
+    }
+}
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct IrqsummaryProc0nonsecure1(pub u32);
+impl IrqsummaryProc0nonsecure1 {
+    #[inline(always)]
+    pub const fn gpio32(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio32(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[inline(always)]
+    pub const fn gpio33(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio33(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+    #[inline(always)]
+    pub const fn gpio34(&self) -> bool {
+        let val = (self.0 >> 2usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio34(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+    }
+    #[inline(always)]
+    pub const fn gpio35(&self) -> bool {
+        let val = (self.0 >> 3usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio35(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
+    }
+    #[inline(always)]
+    pub const fn gpio36(&self) -> bool {
+        let val = (self.0 >> 4usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio36(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
+    }
+    #[inline(always)]
+    pub const fn gpio37(&self) -> bool {
+        let val = (self.0 >> 5usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio37(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
+    }
+    #[inline(always)]
+    pub const fn gpio38(&self) -> bool {
+        let val = (self.0 >> 6usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio38(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
+    }
+    #[inline(always)]
+    pub const fn gpio39(&self) -> bool {
+        let val = (self.0 >> 7usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio39(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
+    }
+    #[inline(always)]
+    pub const fn gpio40(&self) -> bool {
+        let val = (self.0 >> 8usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio40(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
+    }
+    #[inline(always)]
+    pub const fn gpio41(&self) -> bool {
+        let val = (self.0 >> 9usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio41(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
+    }
+    #[inline(always)]
+    pub const fn gpio42(&self) -> bool {
+        let val = (self.0 >> 10usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio42(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize);
+    }
+    #[inline(always)]
+    pub const fn gpio43(&self) -> bool {
+        let val = (self.0 >> 11usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio43(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
+    }
+    #[inline(always)]
+    pub const fn gpio44(&self) -> bool {
+        let val = (self.0 >> 12usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio44(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
+    }
+    #[inline(always)]
+    pub const fn gpio45(&self) -> bool {
+        let val = (self.0 >> 13usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio45(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize);
+    }
+    #[inline(always)]
+    pub const fn gpio46(&self) -> bool {
+        let val = (self.0 >> 14usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio46(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize);
+    }
+    #[inline(always)]
+    pub const fn gpio47(&self) -> bool {
+        let val = (self.0 >> 15usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio47(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize);
+    }
+}
+impl Default for IrqsummaryProc0nonsecure1 {
+    #[inline(always)]
+    fn default() -> IrqsummaryProc0nonsecure1 {
+        IrqsummaryProc0nonsecure1(0)
+    }
+}
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct IrqsummaryProc0secure0(pub u32);
+impl IrqsummaryProc0secure0 {
+    #[inline(always)]
+    pub const fn gpio0(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio0(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[inline(always)]
+    pub const fn gpio1(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio1(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+    #[inline(always)]
+    pub const fn gpio2(&self) -> bool {
+        let val = (self.0 >> 2usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio2(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+    }
+    #[inline(always)]
+    pub const fn gpio3(&self) -> bool {
+        let val = (self.0 >> 3usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio3(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
+    }
+    #[inline(always)]
+    pub const fn gpio4(&self) -> bool {
+        let val = (self.0 >> 4usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio4(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
+    }
+    #[inline(always)]
+    pub const fn gpio5(&self) -> bool {
+        let val = (self.0 >> 5usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio5(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
+    }
+    #[inline(always)]
+    pub const fn gpio6(&self) -> bool {
+        let val = (self.0 >> 6usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio6(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
+    }
+    #[inline(always)]
+    pub const fn gpio7(&self) -> bool {
+        let val = (self.0 >> 7usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio7(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
+    }
+    #[inline(always)]
+    pub const fn gpio8(&self) -> bool {
+        let val = (self.0 >> 8usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio8(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
+    }
+    #[inline(always)]
+    pub const fn gpio9(&self) -> bool {
+        let val = (self.0 >> 9usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio9(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
+    }
+    #[inline(always)]
+    pub const fn gpio10(&self) -> bool {
+        let val = (self.0 >> 10usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio10(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize);
+    }
+    #[inline(always)]
+    pub const fn gpio11(&self) -> bool {
+        let val = (self.0 >> 11usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio11(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
+    }
+    #[inline(always)]
+    pub const fn gpio12(&self) -> bool {
+        let val = (self.0 >> 12usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio12(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
+    }
+    #[inline(always)]
+    pub const fn gpio13(&self) -> bool {
+        let val = (self.0 >> 13usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio13(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize);
+    }
+    #[inline(always)]
+    pub const fn gpio14(&self) -> bool {
+        let val = (self.0 >> 14usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio14(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize);
+    }
+    #[inline(always)]
+    pub const fn gpio15(&self) -> bool {
+        let val = (self.0 >> 15usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio15(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize);
+    }
+    #[inline(always)]
+    pub const fn gpio16(&self) -> bool {
+        let val = (self.0 >> 16usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio16(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
+    }
+    #[inline(always)]
+    pub const fn gpio17(&self) -> bool {
+        let val = (self.0 >> 17usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio17(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
+    }
+    #[inline(always)]
+    pub const fn gpio18(&self) -> bool {
+        let val = (self.0 >> 18usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio18(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize);
+    }
+    #[inline(always)]
+    pub const fn gpio19(&self) -> bool {
+        let val = (self.0 >> 19usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio19(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize);
+    }
+    #[inline(always)]
+    pub const fn gpio20(&self) -> bool {
+        let val = (self.0 >> 20usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio20(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize);
+    }
+    #[inline(always)]
+    pub const fn gpio21(&self) -> bool {
+        let val = (self.0 >> 21usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio21(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 21usize)) | (((val as u32) & 0x01) << 21usize);
+    }
+    #[inline(always)]
+    pub const fn gpio22(&self) -> bool {
+        let val = (self.0 >> 22usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio22(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 22usize)) | (((val as u32) & 0x01) << 22usize);
+    }
+    #[inline(always)]
+    pub const fn gpio23(&self) -> bool {
+        let val = (self.0 >> 23usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio23(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 23usize)) | (((val as u32) & 0x01) << 23usize);
+    }
+    #[inline(always)]
+    pub const fn gpio24(&self) -> bool {
+        let val = (self.0 >> 24usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio24(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 24usize)) | (((val as u32) & 0x01) << 24usize);
+    }
+    #[inline(always)]
+    pub const fn gpio25(&self) -> bool {
+        let val = (self.0 >> 25usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio25(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 25usize)) | (((val as u32) & 0x01) << 25usize);
+    }
+    #[inline(always)]
+    pub const fn gpio26(&self) -> bool {
+        let val = (self.0 >> 26usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio26(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 26usize)) | (((val as u32) & 0x01) << 26usize);
+    }
+    #[inline(always)]
+    pub const fn gpio27(&self) -> bool {
+        let val = (self.0 >> 27usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio27(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 27usize)) | (((val as u32) & 0x01) << 27usize);
+    }
+    #[inline(always)]
+    pub const fn gpio28(&self) -> bool {
+        let val = (self.0 >> 28usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio28(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 28usize)) | (((val as u32) & 0x01) << 28usize);
+    }
+    #[inline(always)]
+    pub const fn gpio29(&self) -> bool {
+        let val = (self.0 >> 29usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio29(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 29usize)) | (((val as u32) & 0x01) << 29usize);
+    }
+    #[inline(always)]
+    pub const fn gpio30(&self) -> bool {
+        let val = (self.0 >> 30usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio30(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 30usize)) | (((val as u32) & 0x01) << 30usize);
+    }
+    #[inline(always)]
+    pub const fn gpio31(&self) -> bool {
+        let val = (self.0 >> 31usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio31(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 31usize)) | (((val as u32) & 0x01) << 31usize);
+    }
+}
+impl Default for IrqsummaryProc0secure0 {
+    #[inline(always)]
+    fn default() -> IrqsummaryProc0secure0 {
+        IrqsummaryProc0secure0(0)
+    }
+}
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct IrqsummaryProc0secure1(pub u32);
+impl IrqsummaryProc0secure1 {
+    #[inline(always)]
+    pub const fn gpio32(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio32(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[inline(always)]
+    pub const fn gpio33(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio33(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+    #[inline(always)]
+    pub const fn gpio34(&self) -> bool {
+        let val = (self.0 >> 2usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio34(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+    }
+    #[inline(always)]
+    pub const fn gpio35(&self) -> bool {
+        let val = (self.0 >> 3usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio35(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
+    }
+    #[inline(always)]
+    pub const fn gpio36(&self) -> bool {
+        let val = (self.0 >> 4usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio36(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
+    }
+    #[inline(always)]
+    pub const fn gpio37(&self) -> bool {
+        let val = (self.0 >> 5usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio37(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
+    }
+    #[inline(always)]
+    pub const fn gpio38(&self) -> bool {
+        let val = (self.0 >> 6usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio38(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
+    }
+    #[inline(always)]
+    pub const fn gpio39(&self) -> bool {
+        let val = (self.0 >> 7usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio39(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
+    }
+    #[inline(always)]
+    pub const fn gpio40(&self) -> bool {
+        let val = (self.0 >> 8usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio40(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
+    }
+    #[inline(always)]
+    pub const fn gpio41(&self) -> bool {
+        let val = (self.0 >> 9usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio41(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
+    }
+    #[inline(always)]
+    pub const fn gpio42(&self) -> bool {
+        let val = (self.0 >> 10usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio42(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize);
+    }
+    #[inline(always)]
+    pub const fn gpio43(&self) -> bool {
+        let val = (self.0 >> 11usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio43(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
+    }
+    #[inline(always)]
+    pub const fn gpio44(&self) -> bool {
+        let val = (self.0 >> 12usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio44(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
+    }
+    #[inline(always)]
+    pub const fn gpio45(&self) -> bool {
+        let val = (self.0 >> 13usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio45(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize);
+    }
+    #[inline(always)]
+    pub const fn gpio46(&self) -> bool {
+        let val = (self.0 >> 14usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio46(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize);
+    }
+    #[inline(always)]
+    pub const fn gpio47(&self) -> bool {
+        let val = (self.0 >> 15usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio47(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize);
+    }
+}
+impl Default for IrqsummaryProc0secure1 {
+    #[inline(always)]
+    fn default() -> IrqsummaryProc0secure1 {
+        IrqsummaryProc0secure1(0)
+    }
+}
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct IrqsummaryProc1nonsecure0(pub u32);
+impl IrqsummaryProc1nonsecure0 {
+    #[inline(always)]
+    pub const fn gpio0(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio0(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[inline(always)]
+    pub const fn gpio1(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio1(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+    #[inline(always)]
+    pub const fn gpio2(&self) -> bool {
+        let val = (self.0 >> 2usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio2(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+    }
+    #[inline(always)]
+    pub const fn gpio3(&self) -> bool {
+        let val = (self.0 >> 3usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio3(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
+    }
+    #[inline(always)]
+    pub const fn gpio4(&self) -> bool {
+        let val = (self.0 >> 4usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio4(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
+    }
+    #[inline(always)]
+    pub const fn gpio5(&self) -> bool {
+        let val = (self.0 >> 5usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio5(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
+    }
+    #[inline(always)]
+    pub const fn gpio6(&self) -> bool {
+        let val = (self.0 >> 6usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio6(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
+    }
+    #[inline(always)]
+    pub const fn gpio7(&self) -> bool {
+        let val = (self.0 >> 7usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio7(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
+    }
+    #[inline(always)]
+    pub const fn gpio8(&self) -> bool {
+        let val = (self.0 >> 8usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio8(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
+    }
+    #[inline(always)]
+    pub const fn gpio9(&self) -> bool {
+        let val = (self.0 >> 9usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio9(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
+    }
+    #[inline(always)]
+    pub const fn gpio10(&self) -> bool {
+        let val = (self.0 >> 10usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio10(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize);
+    }
+    #[inline(always)]
+    pub const fn gpio11(&self) -> bool {
+        let val = (self.0 >> 11usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio11(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
+    }
+    #[inline(always)]
+    pub const fn gpio12(&self) -> bool {
+        let val = (self.0 >> 12usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio12(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
+    }
+    #[inline(always)]
+    pub const fn gpio13(&self) -> bool {
+        let val = (self.0 >> 13usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio13(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize);
+    }
+    #[inline(always)]
+    pub const fn gpio14(&self) -> bool {
+        let val = (self.0 >> 14usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio14(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize);
+    }
+    #[inline(always)]
+    pub const fn gpio15(&self) -> bool {
+        let val = (self.0 >> 15usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio15(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize);
+    }
+    #[inline(always)]
+    pub const fn gpio16(&self) -> bool {
+        let val = (self.0 >> 16usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio16(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
+    }
+    #[inline(always)]
+    pub const fn gpio17(&self) -> bool {
+        let val = (self.0 >> 17usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio17(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
+    }
+    #[inline(always)]
+    pub const fn gpio18(&self) -> bool {
+        let val = (self.0 >> 18usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio18(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize);
+    }
+    #[inline(always)]
+    pub const fn gpio19(&self) -> bool {
+        let val = (self.0 >> 19usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio19(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize);
+    }
+    #[inline(always)]
+    pub const fn gpio20(&self) -> bool {
+        let val = (self.0 >> 20usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio20(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize);
+    }
+    #[inline(always)]
+    pub const fn gpio21(&self) -> bool {
+        let val = (self.0 >> 21usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio21(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 21usize)) | (((val as u32) & 0x01) << 21usize);
+    }
+    #[inline(always)]
+    pub const fn gpio22(&self) -> bool {
+        let val = (self.0 >> 22usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio22(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 22usize)) | (((val as u32) & 0x01) << 22usize);
+    }
+    #[inline(always)]
+    pub const fn gpio23(&self) -> bool {
+        let val = (self.0 >> 23usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio23(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 23usize)) | (((val as u32) & 0x01) << 23usize);
+    }
+    #[inline(always)]
+    pub const fn gpio24(&self) -> bool {
+        let val = (self.0 >> 24usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio24(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 24usize)) | (((val as u32) & 0x01) << 24usize);
+    }
+    #[inline(always)]
+    pub const fn gpio25(&self) -> bool {
+        let val = (self.0 >> 25usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio25(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 25usize)) | (((val as u32) & 0x01) << 25usize);
+    }
+    #[inline(always)]
+    pub const fn gpio26(&self) -> bool {
+        let val = (self.0 >> 26usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio26(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 26usize)) | (((val as u32) & 0x01) << 26usize);
+    }
+    #[inline(always)]
+    pub const fn gpio27(&self) -> bool {
+        let val = (self.0 >> 27usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio27(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 27usize)) | (((val as u32) & 0x01) << 27usize);
+    }
+    #[inline(always)]
+    pub const fn gpio28(&self) -> bool {
+        let val = (self.0 >> 28usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio28(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 28usize)) | (((val as u32) & 0x01) << 28usize);
+    }
+    #[inline(always)]
+    pub const fn gpio29(&self) -> bool {
+        let val = (self.0 >> 29usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio29(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 29usize)) | (((val as u32) & 0x01) << 29usize);
+    }
+    #[inline(always)]
+    pub const fn gpio30(&self) -> bool {
+        let val = (self.0 >> 30usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio30(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 30usize)) | (((val as u32) & 0x01) << 30usize);
+    }
+    #[inline(always)]
+    pub const fn gpio31(&self) -> bool {
+        let val = (self.0 >> 31usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio31(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 31usize)) | (((val as u32) & 0x01) << 31usize);
+    }
+}
+impl Default for IrqsummaryProc1nonsecure0 {
+    #[inline(always)]
+    fn default() -> IrqsummaryProc1nonsecure0 {
+        IrqsummaryProc1nonsecure0(0)
+    }
+}
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct IrqsummaryProc1nonsecure1(pub u32);
+impl IrqsummaryProc1nonsecure1 {
+    #[inline(always)]
+    pub const fn gpio32(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio32(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[inline(always)]
+    pub const fn gpio33(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio33(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+    #[inline(always)]
+    pub const fn gpio34(&self) -> bool {
+        let val = (self.0 >> 2usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio34(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+    }
+    #[inline(always)]
+    pub const fn gpio35(&self) -> bool {
+        let val = (self.0 >> 3usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio35(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
+    }
+    #[inline(always)]
+    pub const fn gpio36(&self) -> bool {
+        let val = (self.0 >> 4usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio36(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
+    }
+    #[inline(always)]
+    pub const fn gpio37(&self) -> bool {
+        let val = (self.0 >> 5usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio37(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
+    }
+    #[inline(always)]
+    pub const fn gpio38(&self) -> bool {
+        let val = (self.0 >> 6usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio38(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
+    }
+    #[inline(always)]
+    pub const fn gpio39(&self) -> bool {
+        let val = (self.0 >> 7usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio39(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
+    }
+    #[inline(always)]
+    pub const fn gpio40(&self) -> bool {
+        let val = (self.0 >> 8usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio40(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
+    }
+    #[inline(always)]
+    pub const fn gpio41(&self) -> bool {
+        let val = (self.0 >> 9usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio41(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
+    }
+    #[inline(always)]
+    pub const fn gpio42(&self) -> bool {
+        let val = (self.0 >> 10usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio42(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize);
+    }
+    #[inline(always)]
+    pub const fn gpio43(&self) -> bool {
+        let val = (self.0 >> 11usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio43(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
+    }
+    #[inline(always)]
+    pub const fn gpio44(&self) -> bool {
+        let val = (self.0 >> 12usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio44(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
+    }
+    #[inline(always)]
+    pub const fn gpio45(&self) -> bool {
+        let val = (self.0 >> 13usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio45(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize);
+    }
+    #[inline(always)]
+    pub const fn gpio46(&self) -> bool {
+        let val = (self.0 >> 14usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio46(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize);
+    }
+    #[inline(always)]
+    pub const fn gpio47(&self) -> bool {
+        let val = (self.0 >> 15usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio47(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize);
+    }
+}
+impl Default for IrqsummaryProc1nonsecure1 {
+    #[inline(always)]
+    fn default() -> IrqsummaryProc1nonsecure1 {
+        IrqsummaryProc1nonsecure1(0)
+    }
+}
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct IrqsummaryProc1secure0(pub u32);
+impl IrqsummaryProc1secure0 {
+    #[inline(always)]
+    pub const fn gpio0(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio0(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[inline(always)]
+    pub const fn gpio1(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio1(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+    #[inline(always)]
+    pub const fn gpio2(&self) -> bool {
+        let val = (self.0 >> 2usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio2(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+    }
+    #[inline(always)]
+    pub const fn gpio3(&self) -> bool {
+        let val = (self.0 >> 3usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio3(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
+    }
+    #[inline(always)]
+    pub const fn gpio4(&self) -> bool {
+        let val = (self.0 >> 4usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio4(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
+    }
+    #[inline(always)]
+    pub const fn gpio5(&self) -> bool {
+        let val = (self.0 >> 5usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio5(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
+    }
+    #[inline(always)]
+    pub const fn gpio6(&self) -> bool {
+        let val = (self.0 >> 6usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio6(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
+    }
+    #[inline(always)]
+    pub const fn gpio7(&self) -> bool {
+        let val = (self.0 >> 7usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio7(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
+    }
+    #[inline(always)]
+    pub const fn gpio8(&self) -> bool {
+        let val = (self.0 >> 8usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio8(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
+    }
+    #[inline(always)]
+    pub const fn gpio9(&self) -> bool {
+        let val = (self.0 >> 9usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio9(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
+    }
+    #[inline(always)]
+    pub const fn gpio10(&self) -> bool {
+        let val = (self.0 >> 10usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio10(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize);
+    }
+    #[inline(always)]
+    pub const fn gpio11(&self) -> bool {
+        let val = (self.0 >> 11usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio11(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
+    }
+    #[inline(always)]
+    pub const fn gpio12(&self) -> bool {
+        let val = (self.0 >> 12usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio12(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
+    }
+    #[inline(always)]
+    pub const fn gpio13(&self) -> bool {
+        let val = (self.0 >> 13usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio13(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize);
+    }
+    #[inline(always)]
+    pub const fn gpio14(&self) -> bool {
+        let val = (self.0 >> 14usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio14(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize);
+    }
+    #[inline(always)]
+    pub const fn gpio15(&self) -> bool {
+        let val = (self.0 >> 15usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio15(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize);
+    }
+    #[inline(always)]
+    pub const fn gpio16(&self) -> bool {
+        let val = (self.0 >> 16usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio16(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
+    }
+    #[inline(always)]
+    pub const fn gpio17(&self) -> bool {
+        let val = (self.0 >> 17usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio17(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
+    }
+    #[inline(always)]
+    pub const fn gpio18(&self) -> bool {
+        let val = (self.0 >> 18usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio18(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize);
+    }
+    #[inline(always)]
+    pub const fn gpio19(&self) -> bool {
+        let val = (self.0 >> 19usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio19(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize);
+    }
+    #[inline(always)]
+    pub const fn gpio20(&self) -> bool {
+        let val = (self.0 >> 20usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio20(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize);
+    }
+    #[inline(always)]
+    pub const fn gpio21(&self) -> bool {
+        let val = (self.0 >> 21usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio21(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 21usize)) | (((val as u32) & 0x01) << 21usize);
+    }
+    #[inline(always)]
+    pub const fn gpio22(&self) -> bool {
+        let val = (self.0 >> 22usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio22(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 22usize)) | (((val as u32) & 0x01) << 22usize);
+    }
+    #[inline(always)]
+    pub const fn gpio23(&self) -> bool {
+        let val = (self.0 >> 23usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio23(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 23usize)) | (((val as u32) & 0x01) << 23usize);
+    }
+    #[inline(always)]
+    pub const fn gpio24(&self) -> bool {
+        let val = (self.0 >> 24usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio24(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 24usize)) | (((val as u32) & 0x01) << 24usize);
+    }
+    #[inline(always)]
+    pub const fn gpio25(&self) -> bool {
+        let val = (self.0 >> 25usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio25(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 25usize)) | (((val as u32) & 0x01) << 25usize);
+    }
+    #[inline(always)]
+    pub const fn gpio26(&self) -> bool {
+        let val = (self.0 >> 26usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio26(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 26usize)) | (((val as u32) & 0x01) << 26usize);
+    }
+    #[inline(always)]
+    pub const fn gpio27(&self) -> bool {
+        let val = (self.0 >> 27usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio27(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 27usize)) | (((val as u32) & 0x01) << 27usize);
+    }
+    #[inline(always)]
+    pub const fn gpio28(&self) -> bool {
+        let val = (self.0 >> 28usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio28(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 28usize)) | (((val as u32) & 0x01) << 28usize);
+    }
+    #[inline(always)]
+    pub const fn gpio29(&self) -> bool {
+        let val = (self.0 >> 29usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio29(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 29usize)) | (((val as u32) & 0x01) << 29usize);
+    }
+    #[inline(always)]
+    pub const fn gpio30(&self) -> bool {
+        let val = (self.0 >> 30usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio30(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 30usize)) | (((val as u32) & 0x01) << 30usize);
+    }
+    #[inline(always)]
+    pub const fn gpio31(&self) -> bool {
+        let val = (self.0 >> 31usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio31(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 31usize)) | (((val as u32) & 0x01) << 31usize);
+    }
+}
+impl Default for IrqsummaryProc1secure0 {
+    #[inline(always)]
+    fn default() -> IrqsummaryProc1secure0 {
+        IrqsummaryProc1secure0(0)
+    }
+}
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct IrqsummaryProc1secure1(pub u32);
+impl IrqsummaryProc1secure1 {
+    #[inline(always)]
+    pub const fn gpio32(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio32(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[inline(always)]
+    pub const fn gpio33(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio33(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+    #[inline(always)]
+    pub const fn gpio34(&self) -> bool {
+        let val = (self.0 >> 2usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio34(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+    }
+    #[inline(always)]
+    pub const fn gpio35(&self) -> bool {
+        let val = (self.0 >> 3usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio35(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
+    }
+    #[inline(always)]
+    pub const fn gpio36(&self) -> bool {
+        let val = (self.0 >> 4usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio36(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
+    }
+    #[inline(always)]
+    pub const fn gpio37(&self) -> bool {
+        let val = (self.0 >> 5usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio37(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
+    }
+    #[inline(always)]
+    pub const fn gpio38(&self) -> bool {
+        let val = (self.0 >> 6usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio38(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
+    }
+    #[inline(always)]
+    pub const fn gpio39(&self) -> bool {
+        let val = (self.0 >> 7usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio39(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
+    }
+    #[inline(always)]
+    pub const fn gpio40(&self) -> bool {
+        let val = (self.0 >> 8usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio40(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
+    }
+    #[inline(always)]
+    pub const fn gpio41(&self) -> bool {
+        let val = (self.0 >> 9usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio41(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
+    }
+    #[inline(always)]
+    pub const fn gpio42(&self) -> bool {
+        let val = (self.0 >> 10usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio42(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize);
+    }
+    #[inline(always)]
+    pub const fn gpio43(&self) -> bool {
+        let val = (self.0 >> 11usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio43(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
+    }
+    #[inline(always)]
+    pub const fn gpio44(&self) -> bool {
+        let val = (self.0 >> 12usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio44(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
+    }
+    #[inline(always)]
+    pub const fn gpio45(&self) -> bool {
+        let val = (self.0 >> 13usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio45(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize);
+    }
+    #[inline(always)]
+    pub const fn gpio46(&self) -> bool {
+        let val = (self.0 >> 14usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio46(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize);
+    }
+    #[inline(always)]
+    pub const fn gpio47(&self) -> bool {
+        let val = (self.0 >> 15usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpio47(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize);
+    }
+}
+impl Default for IrqsummaryProc1secure1 {
+    #[inline(always)]
+    fn default() -> IrqsummaryProc1secure1 {
+        IrqsummaryProc1secure1(0)
+    }
+}
diff --git a/src/rp2350/io/vals.rs b/src/rp2350/io/vals.rs
new file mode 100644
index 00000000..49b2970e
--- /dev/null
+++ b/src/rp2350/io/vals.rs
@@ -0,0 +1,2920 @@
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Gpio0ctrlFuncsel {
+    JTAG_TCK = 0,
+    SPI0_RX = 0x01,
+    UART0_TX = 0x02,
+    I2C0_SDA = 0x03,
+    PWM_A_0 = 0x04,
+    SIOB_PROC_0 = 0x05,
+    PIO0_0 = 0x06,
+    PIO1_0 = 0x07,
+    PIO2_0 = 0x08,
+    XIP_SS_N_1 = 0x09,
+    USB_MUXING_OVERCURR_DETECT = 0x0a,
+    _RESERVED_b = 0x0b,
+    _RESERVED_c = 0x0c,
+    _RESERVED_d = 0x0d,
+    _RESERVED_e = 0x0e,
+    _RESERVED_f = 0x0f,
+    _RESERVED_10 = 0x10,
+    _RESERVED_11 = 0x11,
+    _RESERVED_12 = 0x12,
+    _RESERVED_13 = 0x13,
+    _RESERVED_14 = 0x14,
+    _RESERVED_15 = 0x15,
+    _RESERVED_16 = 0x16,
+    _RESERVED_17 = 0x17,
+    _RESERVED_18 = 0x18,
+    _RESERVED_19 = 0x19,
+    _RESERVED_1a = 0x1a,
+    _RESERVED_1b = 0x1b,
+    _RESERVED_1c = 0x1c,
+    _RESERVED_1d = 0x1d,
+    _RESERVED_1e = 0x1e,
+    NULL = 0x1f,
+}
+impl Gpio0ctrlFuncsel {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Gpio0ctrlFuncsel {
+        unsafe { core::mem::transmute(val & 0x1f) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Gpio0ctrlFuncsel {
+    #[inline(always)]
+    fn from(val: u8) -> Gpio0ctrlFuncsel {
+        Gpio0ctrlFuncsel::from_bits(val)
+    }
+}
+impl From<Gpio0ctrlFuncsel> for u8 {
+    #[inline(always)]
+    fn from(val: Gpio0ctrlFuncsel) -> u8 {
+        Gpio0ctrlFuncsel::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Gpio10ctrlFuncsel {
+    _RESERVED_0 = 0,
+    SPI1_SCLK = 0x01,
+    UART1_CTS = 0x02,
+    I2C1_SDA = 0x03,
+    PWM_A_5 = 0x04,
+    SIOB_PROC_10 = 0x05,
+    PIO0_10 = 0x06,
+    PIO1_10 = 0x07,
+    PIO2_10 = 0x08,
+    _RESERVED_9 = 0x09,
+    USB_MUXING_VBUS_DETECT = 0x0a,
+    UART1_TX = 0x0b,
+    _RESERVED_c = 0x0c,
+    _RESERVED_d = 0x0d,
+    _RESERVED_e = 0x0e,
+    _RESERVED_f = 0x0f,
+    _RESERVED_10 = 0x10,
+    _RESERVED_11 = 0x11,
+    _RESERVED_12 = 0x12,
+    _RESERVED_13 = 0x13,
+    _RESERVED_14 = 0x14,
+    _RESERVED_15 = 0x15,
+    _RESERVED_16 = 0x16,
+    _RESERVED_17 = 0x17,
+    _RESERVED_18 = 0x18,
+    _RESERVED_19 = 0x19,
+    _RESERVED_1a = 0x1a,
+    _RESERVED_1b = 0x1b,
+    _RESERVED_1c = 0x1c,
+    _RESERVED_1d = 0x1d,
+    _RESERVED_1e = 0x1e,
+    NULL = 0x1f,
+}
+impl Gpio10ctrlFuncsel {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Gpio10ctrlFuncsel {
+        unsafe { core::mem::transmute(val & 0x1f) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Gpio10ctrlFuncsel {
+    #[inline(always)]
+    fn from(val: u8) -> Gpio10ctrlFuncsel {
+        Gpio10ctrlFuncsel::from_bits(val)
+    }
+}
+impl From<Gpio10ctrlFuncsel> for u8 {
+    #[inline(always)]
+    fn from(val: Gpio10ctrlFuncsel) -> u8 {
+        Gpio10ctrlFuncsel::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Gpio11ctrlFuncsel {
+    _RESERVED_0 = 0,
+    SPI1_TX = 0x01,
+    UART1_RTS = 0x02,
+    I2C1_SCL = 0x03,
+    PWM_B_5 = 0x04,
+    SIOB_PROC_11 = 0x05,
+    PIO0_11 = 0x06,
+    PIO1_11 = 0x07,
+    PIO2_11 = 0x08,
+    _RESERVED_9 = 0x09,
+    USB_MUXING_VBUS_EN = 0x0a,
+    UART1_RX = 0x0b,
+    _RESERVED_c = 0x0c,
+    _RESERVED_d = 0x0d,
+    _RESERVED_e = 0x0e,
+    _RESERVED_f = 0x0f,
+    _RESERVED_10 = 0x10,
+    _RESERVED_11 = 0x11,
+    _RESERVED_12 = 0x12,
+    _RESERVED_13 = 0x13,
+    _RESERVED_14 = 0x14,
+    _RESERVED_15 = 0x15,
+    _RESERVED_16 = 0x16,
+    _RESERVED_17 = 0x17,
+    _RESERVED_18 = 0x18,
+    _RESERVED_19 = 0x19,
+    _RESERVED_1a = 0x1a,
+    _RESERVED_1b = 0x1b,
+    _RESERVED_1c = 0x1c,
+    _RESERVED_1d = 0x1d,
+    _RESERVED_1e = 0x1e,
+    NULL = 0x1f,
+}
+impl Gpio11ctrlFuncsel {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Gpio11ctrlFuncsel {
+        unsafe { core::mem::transmute(val & 0x1f) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Gpio11ctrlFuncsel {
+    #[inline(always)]
+    fn from(val: u8) -> Gpio11ctrlFuncsel {
+        Gpio11ctrlFuncsel::from_bits(val)
+    }
+}
+impl From<Gpio11ctrlFuncsel> for u8 {
+    #[inline(always)]
+    fn from(val: Gpio11ctrlFuncsel) -> u8 {
+        Gpio11ctrlFuncsel::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Gpio12ctrlFuncsel {
+    HSTX_0 = 0,
+    SPI1_RX = 0x01,
+    UART0_TX = 0x02,
+    I2C0_SDA = 0x03,
+    PWM_A_6 = 0x04,
+    SIOB_PROC_12 = 0x05,
+    PIO0_12 = 0x06,
+    PIO1_12 = 0x07,
+    PIO2_12 = 0x08,
+    CLOCKS_GPIN_0 = 0x09,
+    USB_MUXING_OVERCURR_DETECT = 0x0a,
+    _RESERVED_b = 0x0b,
+    _RESERVED_c = 0x0c,
+    _RESERVED_d = 0x0d,
+    _RESERVED_e = 0x0e,
+    _RESERVED_f = 0x0f,
+    _RESERVED_10 = 0x10,
+    _RESERVED_11 = 0x11,
+    _RESERVED_12 = 0x12,
+    _RESERVED_13 = 0x13,
+    _RESERVED_14 = 0x14,
+    _RESERVED_15 = 0x15,
+    _RESERVED_16 = 0x16,
+    _RESERVED_17 = 0x17,
+    _RESERVED_18 = 0x18,
+    _RESERVED_19 = 0x19,
+    _RESERVED_1a = 0x1a,
+    _RESERVED_1b = 0x1b,
+    _RESERVED_1c = 0x1c,
+    _RESERVED_1d = 0x1d,
+    _RESERVED_1e = 0x1e,
+    NULL = 0x1f,
+}
+impl Gpio12ctrlFuncsel {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Gpio12ctrlFuncsel {
+        unsafe { core::mem::transmute(val & 0x1f) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Gpio12ctrlFuncsel {
+    #[inline(always)]
+    fn from(val: u8) -> Gpio12ctrlFuncsel {
+        Gpio12ctrlFuncsel::from_bits(val)
+    }
+}
+impl From<Gpio12ctrlFuncsel> for u8 {
+    #[inline(always)]
+    fn from(val: Gpio12ctrlFuncsel) -> u8 {
+        Gpio12ctrlFuncsel::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Gpio13ctrlFuncsel {
+    HSTX_1 = 0,
+    SPI1_SS_N = 0x01,
+    UART0_RX = 0x02,
+    I2C0_SCL = 0x03,
+    PWM_B_6 = 0x04,
+    SIOB_PROC_13 = 0x05,
+    PIO0_13 = 0x06,
+    PIO1_13 = 0x07,
+    PIO2_13 = 0x08,
+    CLOCKS_GPOUT_0 = 0x09,
+    USB_MUXING_VBUS_DETECT = 0x0a,
+    _RESERVED_b = 0x0b,
+    _RESERVED_c = 0x0c,
+    _RESERVED_d = 0x0d,
+    _RESERVED_e = 0x0e,
+    _RESERVED_f = 0x0f,
+    _RESERVED_10 = 0x10,
+    _RESERVED_11 = 0x11,
+    _RESERVED_12 = 0x12,
+    _RESERVED_13 = 0x13,
+    _RESERVED_14 = 0x14,
+    _RESERVED_15 = 0x15,
+    _RESERVED_16 = 0x16,
+    _RESERVED_17 = 0x17,
+    _RESERVED_18 = 0x18,
+    _RESERVED_19 = 0x19,
+    _RESERVED_1a = 0x1a,
+    _RESERVED_1b = 0x1b,
+    _RESERVED_1c = 0x1c,
+    _RESERVED_1d = 0x1d,
+    _RESERVED_1e = 0x1e,
+    NULL = 0x1f,
+}
+impl Gpio13ctrlFuncsel {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Gpio13ctrlFuncsel {
+        unsafe { core::mem::transmute(val & 0x1f) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Gpio13ctrlFuncsel {
+    #[inline(always)]
+    fn from(val: u8) -> Gpio13ctrlFuncsel {
+        Gpio13ctrlFuncsel::from_bits(val)
+    }
+}
+impl From<Gpio13ctrlFuncsel> for u8 {
+    #[inline(always)]
+    fn from(val: Gpio13ctrlFuncsel) -> u8 {
+        Gpio13ctrlFuncsel::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Gpio14ctrlFuncsel {
+    HSTX_2 = 0,
+    SPI1_SCLK = 0x01,
+    UART0_CTS = 0x02,
+    I2C1_SDA = 0x03,
+    PWM_A_7 = 0x04,
+    SIOB_PROC_14 = 0x05,
+    PIO0_14 = 0x06,
+    PIO1_14 = 0x07,
+    PIO2_14 = 0x08,
+    CLOCKS_GPIN_1 = 0x09,
+    USB_MUXING_VBUS_EN = 0x0a,
+    UART0_TX = 0x0b,
+    _RESERVED_c = 0x0c,
+    _RESERVED_d = 0x0d,
+    _RESERVED_e = 0x0e,
+    _RESERVED_f = 0x0f,
+    _RESERVED_10 = 0x10,
+    _RESERVED_11 = 0x11,
+    _RESERVED_12 = 0x12,
+    _RESERVED_13 = 0x13,
+    _RESERVED_14 = 0x14,
+    _RESERVED_15 = 0x15,
+    _RESERVED_16 = 0x16,
+    _RESERVED_17 = 0x17,
+    _RESERVED_18 = 0x18,
+    _RESERVED_19 = 0x19,
+    _RESERVED_1a = 0x1a,
+    _RESERVED_1b = 0x1b,
+    _RESERVED_1c = 0x1c,
+    _RESERVED_1d = 0x1d,
+    _RESERVED_1e = 0x1e,
+    NULL = 0x1f,
+}
+impl Gpio14ctrlFuncsel {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Gpio14ctrlFuncsel {
+        unsafe { core::mem::transmute(val & 0x1f) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Gpio14ctrlFuncsel {
+    #[inline(always)]
+    fn from(val: u8) -> Gpio14ctrlFuncsel {
+        Gpio14ctrlFuncsel::from_bits(val)
+    }
+}
+impl From<Gpio14ctrlFuncsel> for u8 {
+    #[inline(always)]
+    fn from(val: Gpio14ctrlFuncsel) -> u8 {
+        Gpio14ctrlFuncsel::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Gpio15ctrlFuncsel {
+    HSTX_3 = 0,
+    SPI1_TX = 0x01,
+    UART0_RTS = 0x02,
+    I2C1_SCL = 0x03,
+    PWM_B_7 = 0x04,
+    SIOB_PROC_15 = 0x05,
+    PIO0_15 = 0x06,
+    PIO1_15 = 0x07,
+    PIO2_15 = 0x08,
+    CLOCKS_GPOUT_1 = 0x09,
+    USB_MUXING_OVERCURR_DETECT = 0x0a,
+    UART0_RX = 0x0b,
+    _RESERVED_c = 0x0c,
+    _RESERVED_d = 0x0d,
+    _RESERVED_e = 0x0e,
+    _RESERVED_f = 0x0f,
+    _RESERVED_10 = 0x10,
+    _RESERVED_11 = 0x11,
+    _RESERVED_12 = 0x12,
+    _RESERVED_13 = 0x13,
+    _RESERVED_14 = 0x14,
+    _RESERVED_15 = 0x15,
+    _RESERVED_16 = 0x16,
+    _RESERVED_17 = 0x17,
+    _RESERVED_18 = 0x18,
+    _RESERVED_19 = 0x19,
+    _RESERVED_1a = 0x1a,
+    _RESERVED_1b = 0x1b,
+    _RESERVED_1c = 0x1c,
+    _RESERVED_1d = 0x1d,
+    _RESERVED_1e = 0x1e,
+    NULL = 0x1f,
+}
+impl Gpio15ctrlFuncsel {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Gpio15ctrlFuncsel {
+        unsafe { core::mem::transmute(val & 0x1f) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Gpio15ctrlFuncsel {
+    #[inline(always)]
+    fn from(val: u8) -> Gpio15ctrlFuncsel {
+        Gpio15ctrlFuncsel::from_bits(val)
+    }
+}
+impl From<Gpio15ctrlFuncsel> for u8 {
+    #[inline(always)]
+    fn from(val: Gpio15ctrlFuncsel) -> u8 {
+        Gpio15ctrlFuncsel::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Gpio16ctrlFuncsel {
+    HSTX_4 = 0,
+    SPI0_RX = 0x01,
+    UART0_TX = 0x02,
+    I2C0_SDA = 0x03,
+    PWM_A_0 = 0x04,
+    SIOB_PROC_16 = 0x05,
+    PIO0_16 = 0x06,
+    PIO1_16 = 0x07,
+    PIO2_16 = 0x08,
+    _RESERVED_9 = 0x09,
+    USB_MUXING_VBUS_DETECT = 0x0a,
+    _RESERVED_b = 0x0b,
+    _RESERVED_c = 0x0c,
+    _RESERVED_d = 0x0d,
+    _RESERVED_e = 0x0e,
+    _RESERVED_f = 0x0f,
+    _RESERVED_10 = 0x10,
+    _RESERVED_11 = 0x11,
+    _RESERVED_12 = 0x12,
+    _RESERVED_13 = 0x13,
+    _RESERVED_14 = 0x14,
+    _RESERVED_15 = 0x15,
+    _RESERVED_16 = 0x16,
+    _RESERVED_17 = 0x17,
+    _RESERVED_18 = 0x18,
+    _RESERVED_19 = 0x19,
+    _RESERVED_1a = 0x1a,
+    _RESERVED_1b = 0x1b,
+    _RESERVED_1c = 0x1c,
+    _RESERVED_1d = 0x1d,
+    _RESERVED_1e = 0x1e,
+    NULL = 0x1f,
+}
+impl Gpio16ctrlFuncsel {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Gpio16ctrlFuncsel {
+        unsafe { core::mem::transmute(val & 0x1f) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Gpio16ctrlFuncsel {
+    #[inline(always)]
+    fn from(val: u8) -> Gpio16ctrlFuncsel {
+        Gpio16ctrlFuncsel::from_bits(val)
+    }
+}
+impl From<Gpio16ctrlFuncsel> for u8 {
+    #[inline(always)]
+    fn from(val: Gpio16ctrlFuncsel) -> u8 {
+        Gpio16ctrlFuncsel::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Gpio17ctrlFuncsel {
+    HSTX_5 = 0,
+    SPI0_SS_N = 0x01,
+    UART0_RX = 0x02,
+    I2C0_SCL = 0x03,
+    PWM_B_0 = 0x04,
+    SIOB_PROC_17 = 0x05,
+    PIO0_17 = 0x06,
+    PIO1_17 = 0x07,
+    PIO2_17 = 0x08,
+    _RESERVED_9 = 0x09,
+    USB_MUXING_VBUS_EN = 0x0a,
+    _RESERVED_b = 0x0b,
+    _RESERVED_c = 0x0c,
+    _RESERVED_d = 0x0d,
+    _RESERVED_e = 0x0e,
+    _RESERVED_f = 0x0f,
+    _RESERVED_10 = 0x10,
+    _RESERVED_11 = 0x11,
+    _RESERVED_12 = 0x12,
+    _RESERVED_13 = 0x13,
+    _RESERVED_14 = 0x14,
+    _RESERVED_15 = 0x15,
+    _RESERVED_16 = 0x16,
+    _RESERVED_17 = 0x17,
+    _RESERVED_18 = 0x18,
+    _RESERVED_19 = 0x19,
+    _RESERVED_1a = 0x1a,
+    _RESERVED_1b = 0x1b,
+    _RESERVED_1c = 0x1c,
+    _RESERVED_1d = 0x1d,
+    _RESERVED_1e = 0x1e,
+    NULL = 0x1f,
+}
+impl Gpio17ctrlFuncsel {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Gpio17ctrlFuncsel {
+        unsafe { core::mem::transmute(val & 0x1f) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Gpio17ctrlFuncsel {
+    #[inline(always)]
+    fn from(val: u8) -> Gpio17ctrlFuncsel {
+        Gpio17ctrlFuncsel::from_bits(val)
+    }
+}
+impl From<Gpio17ctrlFuncsel> for u8 {
+    #[inline(always)]
+    fn from(val: Gpio17ctrlFuncsel) -> u8 {
+        Gpio17ctrlFuncsel::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Gpio18ctrlFuncsel {
+    HSTX_6 = 0,
+    SPI0_SCLK = 0x01,
+    UART0_CTS = 0x02,
+    I2C1_SDA = 0x03,
+    PWM_A_1 = 0x04,
+    SIOB_PROC_18 = 0x05,
+    PIO0_18 = 0x06,
+    PIO1_18 = 0x07,
+    PIO2_18 = 0x08,
+    _RESERVED_9 = 0x09,
+    USB_MUXING_OVERCURR_DETECT = 0x0a,
+    UART0_TX = 0x0b,
+    _RESERVED_c = 0x0c,
+    _RESERVED_d = 0x0d,
+    _RESERVED_e = 0x0e,
+    _RESERVED_f = 0x0f,
+    _RESERVED_10 = 0x10,
+    _RESERVED_11 = 0x11,
+    _RESERVED_12 = 0x12,
+    _RESERVED_13 = 0x13,
+    _RESERVED_14 = 0x14,
+    _RESERVED_15 = 0x15,
+    _RESERVED_16 = 0x16,
+    _RESERVED_17 = 0x17,
+    _RESERVED_18 = 0x18,
+    _RESERVED_19 = 0x19,
+    _RESERVED_1a = 0x1a,
+    _RESERVED_1b = 0x1b,
+    _RESERVED_1c = 0x1c,
+    _RESERVED_1d = 0x1d,
+    _RESERVED_1e = 0x1e,
+    NULL = 0x1f,
+}
+impl Gpio18ctrlFuncsel {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Gpio18ctrlFuncsel {
+        unsafe { core::mem::transmute(val & 0x1f) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Gpio18ctrlFuncsel {
+    #[inline(always)]
+    fn from(val: u8) -> Gpio18ctrlFuncsel {
+        Gpio18ctrlFuncsel::from_bits(val)
+    }
+}
+impl From<Gpio18ctrlFuncsel> for u8 {
+    #[inline(always)]
+    fn from(val: Gpio18ctrlFuncsel) -> u8 {
+        Gpio18ctrlFuncsel::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Gpio19ctrlFuncsel {
+    HSTX_7 = 0,
+    SPI0_TX = 0x01,
+    UART0_RTS = 0x02,
+    I2C1_SCL = 0x03,
+    PWM_B_1 = 0x04,
+    SIOB_PROC_19 = 0x05,
+    PIO0_19 = 0x06,
+    PIO1_19 = 0x07,
+    PIO2_19 = 0x08,
+    XIP_SS_N_1 = 0x09,
+    USB_MUXING_VBUS_DETECT = 0x0a,
+    UART0_RX = 0x0b,
+    _RESERVED_c = 0x0c,
+    _RESERVED_d = 0x0d,
+    _RESERVED_e = 0x0e,
+    _RESERVED_f = 0x0f,
+    _RESERVED_10 = 0x10,
+    _RESERVED_11 = 0x11,
+    _RESERVED_12 = 0x12,
+    _RESERVED_13 = 0x13,
+    _RESERVED_14 = 0x14,
+    _RESERVED_15 = 0x15,
+    _RESERVED_16 = 0x16,
+    _RESERVED_17 = 0x17,
+    _RESERVED_18 = 0x18,
+    _RESERVED_19 = 0x19,
+    _RESERVED_1a = 0x1a,
+    _RESERVED_1b = 0x1b,
+    _RESERVED_1c = 0x1c,
+    _RESERVED_1d = 0x1d,
+    _RESERVED_1e = 0x1e,
+    NULL = 0x1f,
+}
+impl Gpio19ctrlFuncsel {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Gpio19ctrlFuncsel {
+        unsafe { core::mem::transmute(val & 0x1f) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Gpio19ctrlFuncsel {
+    #[inline(always)]
+    fn from(val: u8) -> Gpio19ctrlFuncsel {
+        Gpio19ctrlFuncsel::from_bits(val)
+    }
+}
+impl From<Gpio19ctrlFuncsel> for u8 {
+    #[inline(always)]
+    fn from(val: Gpio19ctrlFuncsel) -> u8 {
+        Gpio19ctrlFuncsel::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Gpio1ctrlFuncsel {
+    JTAG_TMS = 0,
+    SPI0_SS_N = 0x01,
+    UART0_RX = 0x02,
+    I2C0_SCL = 0x03,
+    PWM_B_0 = 0x04,
+    SIOB_PROC_1 = 0x05,
+    PIO0_1 = 0x06,
+    PIO1_1 = 0x07,
+    PIO2_1 = 0x08,
+    CORESIGHT_TRACECLK = 0x09,
+    USB_MUXING_VBUS_DETECT = 0x0a,
+    _RESERVED_b = 0x0b,
+    _RESERVED_c = 0x0c,
+    _RESERVED_d = 0x0d,
+    _RESERVED_e = 0x0e,
+    _RESERVED_f = 0x0f,
+    _RESERVED_10 = 0x10,
+    _RESERVED_11 = 0x11,
+    _RESERVED_12 = 0x12,
+    _RESERVED_13 = 0x13,
+    _RESERVED_14 = 0x14,
+    _RESERVED_15 = 0x15,
+    _RESERVED_16 = 0x16,
+    _RESERVED_17 = 0x17,
+    _RESERVED_18 = 0x18,
+    _RESERVED_19 = 0x19,
+    _RESERVED_1a = 0x1a,
+    _RESERVED_1b = 0x1b,
+    _RESERVED_1c = 0x1c,
+    _RESERVED_1d = 0x1d,
+    _RESERVED_1e = 0x1e,
+    NULL = 0x1f,
+}
+impl Gpio1ctrlFuncsel {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Gpio1ctrlFuncsel {
+        unsafe { core::mem::transmute(val & 0x1f) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Gpio1ctrlFuncsel {
+    #[inline(always)]
+    fn from(val: u8) -> Gpio1ctrlFuncsel {
+        Gpio1ctrlFuncsel::from_bits(val)
+    }
+}
+impl From<Gpio1ctrlFuncsel> for u8 {
+    #[inline(always)]
+    fn from(val: Gpio1ctrlFuncsel) -> u8 {
+        Gpio1ctrlFuncsel::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Gpio20ctrlFuncsel {
+    _RESERVED_0 = 0,
+    SPI0_RX = 0x01,
+    UART1_TX = 0x02,
+    I2C0_SDA = 0x03,
+    PWM_A_2 = 0x04,
+    SIOB_PROC_20 = 0x05,
+    PIO0_20 = 0x06,
+    PIO1_20 = 0x07,
+    PIO2_20 = 0x08,
+    CLOCKS_GPIN_0 = 0x09,
+    USB_MUXING_VBUS_EN = 0x0a,
+    _RESERVED_b = 0x0b,
+    _RESERVED_c = 0x0c,
+    _RESERVED_d = 0x0d,
+    _RESERVED_e = 0x0e,
+    _RESERVED_f = 0x0f,
+    _RESERVED_10 = 0x10,
+    _RESERVED_11 = 0x11,
+    _RESERVED_12 = 0x12,
+    _RESERVED_13 = 0x13,
+    _RESERVED_14 = 0x14,
+    _RESERVED_15 = 0x15,
+    _RESERVED_16 = 0x16,
+    _RESERVED_17 = 0x17,
+    _RESERVED_18 = 0x18,
+    _RESERVED_19 = 0x19,
+    _RESERVED_1a = 0x1a,
+    _RESERVED_1b = 0x1b,
+    _RESERVED_1c = 0x1c,
+    _RESERVED_1d = 0x1d,
+    _RESERVED_1e = 0x1e,
+    NULL = 0x1f,
+}
+impl Gpio20ctrlFuncsel {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Gpio20ctrlFuncsel {
+        unsafe { core::mem::transmute(val & 0x1f) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Gpio20ctrlFuncsel {
+    #[inline(always)]
+    fn from(val: u8) -> Gpio20ctrlFuncsel {
+        Gpio20ctrlFuncsel::from_bits(val)
+    }
+}
+impl From<Gpio20ctrlFuncsel> for u8 {
+    #[inline(always)]
+    fn from(val: Gpio20ctrlFuncsel) -> u8 {
+        Gpio20ctrlFuncsel::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Gpio21ctrlFuncsel {
+    _RESERVED_0 = 0,
+    SPI0_SS_N = 0x01,
+    UART1_RX = 0x02,
+    I2C0_SCL = 0x03,
+    PWM_B_2 = 0x04,
+    SIOB_PROC_21 = 0x05,
+    PIO0_21 = 0x06,
+    PIO1_21 = 0x07,
+    PIO2_21 = 0x08,
+    CLOCKS_GPOUT_0 = 0x09,
+    USB_MUXING_OVERCURR_DETECT = 0x0a,
+    _RESERVED_b = 0x0b,
+    _RESERVED_c = 0x0c,
+    _RESERVED_d = 0x0d,
+    _RESERVED_e = 0x0e,
+    _RESERVED_f = 0x0f,
+    _RESERVED_10 = 0x10,
+    _RESERVED_11 = 0x11,
+    _RESERVED_12 = 0x12,
+    _RESERVED_13 = 0x13,
+    _RESERVED_14 = 0x14,
+    _RESERVED_15 = 0x15,
+    _RESERVED_16 = 0x16,
+    _RESERVED_17 = 0x17,
+    _RESERVED_18 = 0x18,
+    _RESERVED_19 = 0x19,
+    _RESERVED_1a = 0x1a,
+    _RESERVED_1b = 0x1b,
+    _RESERVED_1c = 0x1c,
+    _RESERVED_1d = 0x1d,
+    _RESERVED_1e = 0x1e,
+    NULL = 0x1f,
+}
+impl Gpio21ctrlFuncsel {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Gpio21ctrlFuncsel {
+        unsafe { core::mem::transmute(val & 0x1f) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Gpio21ctrlFuncsel {
+    #[inline(always)]
+    fn from(val: u8) -> Gpio21ctrlFuncsel {
+        Gpio21ctrlFuncsel::from_bits(val)
+    }
+}
+impl From<Gpio21ctrlFuncsel> for u8 {
+    #[inline(always)]
+    fn from(val: Gpio21ctrlFuncsel) -> u8 {
+        Gpio21ctrlFuncsel::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Gpio22ctrlFuncsel {
+    _RESERVED_0 = 0,
+    SPI0_SCLK = 0x01,
+    UART1_CTS = 0x02,
+    I2C1_SDA = 0x03,
+    PWM_A_3 = 0x04,
+    SIOB_PROC_22 = 0x05,
+    PIO0_22 = 0x06,
+    PIO1_22 = 0x07,
+    PIO2_22 = 0x08,
+    CLOCKS_GPIN_1 = 0x09,
+    USB_MUXING_VBUS_DETECT = 0x0a,
+    UART1_TX = 0x0b,
+    _RESERVED_c = 0x0c,
+    _RESERVED_d = 0x0d,
+    _RESERVED_e = 0x0e,
+    _RESERVED_f = 0x0f,
+    _RESERVED_10 = 0x10,
+    _RESERVED_11 = 0x11,
+    _RESERVED_12 = 0x12,
+    _RESERVED_13 = 0x13,
+    _RESERVED_14 = 0x14,
+    _RESERVED_15 = 0x15,
+    _RESERVED_16 = 0x16,
+    _RESERVED_17 = 0x17,
+    _RESERVED_18 = 0x18,
+    _RESERVED_19 = 0x19,
+    _RESERVED_1a = 0x1a,
+    _RESERVED_1b = 0x1b,
+    _RESERVED_1c = 0x1c,
+    _RESERVED_1d = 0x1d,
+    _RESERVED_1e = 0x1e,
+    NULL = 0x1f,
+}
+impl Gpio22ctrlFuncsel {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Gpio22ctrlFuncsel {
+        unsafe { core::mem::transmute(val & 0x1f) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Gpio22ctrlFuncsel {
+    #[inline(always)]
+    fn from(val: u8) -> Gpio22ctrlFuncsel {
+        Gpio22ctrlFuncsel::from_bits(val)
+    }
+}
+impl From<Gpio22ctrlFuncsel> for u8 {
+    #[inline(always)]
+    fn from(val: Gpio22ctrlFuncsel) -> u8 {
+        Gpio22ctrlFuncsel::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Gpio23ctrlFuncsel {
+    _RESERVED_0 = 0,
+    SPI0_TX = 0x01,
+    UART1_RTS = 0x02,
+    I2C1_SCL = 0x03,
+    PWM_B_3 = 0x04,
+    SIOB_PROC_23 = 0x05,
+    PIO0_23 = 0x06,
+    PIO1_23 = 0x07,
+    PIO2_23 = 0x08,
+    CLOCKS_GPOUT_1 = 0x09,
+    USB_MUXING_VBUS_EN = 0x0a,
+    UART1_RX = 0x0b,
+    _RESERVED_c = 0x0c,
+    _RESERVED_d = 0x0d,
+    _RESERVED_e = 0x0e,
+    _RESERVED_f = 0x0f,
+    _RESERVED_10 = 0x10,
+    _RESERVED_11 = 0x11,
+    _RESERVED_12 = 0x12,
+    _RESERVED_13 = 0x13,
+    _RESERVED_14 = 0x14,
+    _RESERVED_15 = 0x15,
+    _RESERVED_16 = 0x16,
+    _RESERVED_17 = 0x17,
+    _RESERVED_18 = 0x18,
+    _RESERVED_19 = 0x19,
+    _RESERVED_1a = 0x1a,
+    _RESERVED_1b = 0x1b,
+    _RESERVED_1c = 0x1c,
+    _RESERVED_1d = 0x1d,
+    _RESERVED_1e = 0x1e,
+    NULL = 0x1f,
+}
+impl Gpio23ctrlFuncsel {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Gpio23ctrlFuncsel {
+        unsafe { core::mem::transmute(val & 0x1f) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Gpio23ctrlFuncsel {
+    #[inline(always)]
+    fn from(val: u8) -> Gpio23ctrlFuncsel {
+        Gpio23ctrlFuncsel::from_bits(val)
+    }
+}
+impl From<Gpio23ctrlFuncsel> for u8 {
+    #[inline(always)]
+    fn from(val: Gpio23ctrlFuncsel) -> u8 {
+        Gpio23ctrlFuncsel::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Gpio24ctrlFuncsel {
+    _RESERVED_0 = 0,
+    SPI1_RX = 0x01,
+    UART1_TX = 0x02,
+    I2C0_SDA = 0x03,
+    PWM_A_4 = 0x04,
+    SIOB_PROC_24 = 0x05,
+    PIO0_24 = 0x06,
+    PIO1_24 = 0x07,
+    PIO2_24 = 0x08,
+    CLOCKS_GPOUT_2 = 0x09,
+    USB_MUXING_OVERCURR_DETECT = 0x0a,
+    _RESERVED_b = 0x0b,
+    _RESERVED_c = 0x0c,
+    _RESERVED_d = 0x0d,
+    _RESERVED_e = 0x0e,
+    _RESERVED_f = 0x0f,
+    _RESERVED_10 = 0x10,
+    _RESERVED_11 = 0x11,
+    _RESERVED_12 = 0x12,
+    _RESERVED_13 = 0x13,
+    _RESERVED_14 = 0x14,
+    _RESERVED_15 = 0x15,
+    _RESERVED_16 = 0x16,
+    _RESERVED_17 = 0x17,
+    _RESERVED_18 = 0x18,
+    _RESERVED_19 = 0x19,
+    _RESERVED_1a = 0x1a,
+    _RESERVED_1b = 0x1b,
+    _RESERVED_1c = 0x1c,
+    _RESERVED_1d = 0x1d,
+    _RESERVED_1e = 0x1e,
+    NULL = 0x1f,
+}
+impl Gpio24ctrlFuncsel {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Gpio24ctrlFuncsel {
+        unsafe { core::mem::transmute(val & 0x1f) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Gpio24ctrlFuncsel {
+    #[inline(always)]
+    fn from(val: u8) -> Gpio24ctrlFuncsel {
+        Gpio24ctrlFuncsel::from_bits(val)
+    }
+}
+impl From<Gpio24ctrlFuncsel> for u8 {
+    #[inline(always)]
+    fn from(val: Gpio24ctrlFuncsel) -> u8 {
+        Gpio24ctrlFuncsel::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Gpio25ctrlFuncsel {
+    _RESERVED_0 = 0,
+    SPI1_SS_N = 0x01,
+    UART1_RX = 0x02,
+    I2C0_SCL = 0x03,
+    PWM_B_4 = 0x04,
+    SIOB_PROC_25 = 0x05,
+    PIO0_25 = 0x06,
+    PIO1_25 = 0x07,
+    PIO2_25 = 0x08,
+    CLOCKS_GPOUT_3 = 0x09,
+    USB_MUXING_VBUS_DETECT = 0x0a,
+    _RESERVED_b = 0x0b,
+    _RESERVED_c = 0x0c,
+    _RESERVED_d = 0x0d,
+    _RESERVED_e = 0x0e,
+    _RESERVED_f = 0x0f,
+    _RESERVED_10 = 0x10,
+    _RESERVED_11 = 0x11,
+    _RESERVED_12 = 0x12,
+    _RESERVED_13 = 0x13,
+    _RESERVED_14 = 0x14,
+    _RESERVED_15 = 0x15,
+    _RESERVED_16 = 0x16,
+    _RESERVED_17 = 0x17,
+    _RESERVED_18 = 0x18,
+    _RESERVED_19 = 0x19,
+    _RESERVED_1a = 0x1a,
+    _RESERVED_1b = 0x1b,
+    _RESERVED_1c = 0x1c,
+    _RESERVED_1d = 0x1d,
+    _RESERVED_1e = 0x1e,
+    NULL = 0x1f,
+}
+impl Gpio25ctrlFuncsel {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Gpio25ctrlFuncsel {
+        unsafe { core::mem::transmute(val & 0x1f) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Gpio25ctrlFuncsel {
+    #[inline(always)]
+    fn from(val: u8) -> Gpio25ctrlFuncsel {
+        Gpio25ctrlFuncsel::from_bits(val)
+    }
+}
+impl From<Gpio25ctrlFuncsel> for u8 {
+    #[inline(always)]
+    fn from(val: Gpio25ctrlFuncsel) -> u8 {
+        Gpio25ctrlFuncsel::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Gpio26ctrlFuncsel {
+    _RESERVED_0 = 0,
+    SPI1_SCLK = 0x01,
+    UART1_CTS = 0x02,
+    I2C1_SDA = 0x03,
+    PWM_A_5 = 0x04,
+    SIOB_PROC_26 = 0x05,
+    PIO0_26 = 0x06,
+    PIO1_26 = 0x07,
+    PIO2_26 = 0x08,
+    _RESERVED_9 = 0x09,
+    USB_MUXING_VBUS_EN = 0x0a,
+    UART1_TX = 0x0b,
+    _RESERVED_c = 0x0c,
+    _RESERVED_d = 0x0d,
+    _RESERVED_e = 0x0e,
+    _RESERVED_f = 0x0f,
+    _RESERVED_10 = 0x10,
+    _RESERVED_11 = 0x11,
+    _RESERVED_12 = 0x12,
+    _RESERVED_13 = 0x13,
+    _RESERVED_14 = 0x14,
+    _RESERVED_15 = 0x15,
+    _RESERVED_16 = 0x16,
+    _RESERVED_17 = 0x17,
+    _RESERVED_18 = 0x18,
+    _RESERVED_19 = 0x19,
+    _RESERVED_1a = 0x1a,
+    _RESERVED_1b = 0x1b,
+    _RESERVED_1c = 0x1c,
+    _RESERVED_1d = 0x1d,
+    _RESERVED_1e = 0x1e,
+    NULL = 0x1f,
+}
+impl Gpio26ctrlFuncsel {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Gpio26ctrlFuncsel {
+        unsafe { core::mem::transmute(val & 0x1f) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Gpio26ctrlFuncsel {
+    #[inline(always)]
+    fn from(val: u8) -> Gpio26ctrlFuncsel {
+        Gpio26ctrlFuncsel::from_bits(val)
+    }
+}
+impl From<Gpio26ctrlFuncsel> for u8 {
+    #[inline(always)]
+    fn from(val: Gpio26ctrlFuncsel) -> u8 {
+        Gpio26ctrlFuncsel::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Gpio27ctrlFuncsel {
+    _RESERVED_0 = 0,
+    SPI1_TX = 0x01,
+    UART1_RTS = 0x02,
+    I2C1_SCL = 0x03,
+    PWM_B_5 = 0x04,
+    SIOB_PROC_27 = 0x05,
+    PIO0_27 = 0x06,
+    PIO1_27 = 0x07,
+    PIO2_27 = 0x08,
+    _RESERVED_9 = 0x09,
+    USB_MUXING_OVERCURR_DETECT = 0x0a,
+    UART1_RX = 0x0b,
+    _RESERVED_c = 0x0c,
+    _RESERVED_d = 0x0d,
+    _RESERVED_e = 0x0e,
+    _RESERVED_f = 0x0f,
+    _RESERVED_10 = 0x10,
+    _RESERVED_11 = 0x11,
+    _RESERVED_12 = 0x12,
+    _RESERVED_13 = 0x13,
+    _RESERVED_14 = 0x14,
+    _RESERVED_15 = 0x15,
+    _RESERVED_16 = 0x16,
+    _RESERVED_17 = 0x17,
+    _RESERVED_18 = 0x18,
+    _RESERVED_19 = 0x19,
+    _RESERVED_1a = 0x1a,
+    _RESERVED_1b = 0x1b,
+    _RESERVED_1c = 0x1c,
+    _RESERVED_1d = 0x1d,
+    _RESERVED_1e = 0x1e,
+    NULL = 0x1f,
+}
+impl Gpio27ctrlFuncsel {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Gpio27ctrlFuncsel {
+        unsafe { core::mem::transmute(val & 0x1f) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Gpio27ctrlFuncsel {
+    #[inline(always)]
+    fn from(val: u8) -> Gpio27ctrlFuncsel {
+        Gpio27ctrlFuncsel::from_bits(val)
+    }
+}
+impl From<Gpio27ctrlFuncsel> for u8 {
+    #[inline(always)]
+    fn from(val: Gpio27ctrlFuncsel) -> u8 {
+        Gpio27ctrlFuncsel::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Gpio28ctrlFuncsel {
+    _RESERVED_0 = 0,
+    SPI1_RX = 0x01,
+    UART0_TX = 0x02,
+    I2C0_SDA = 0x03,
+    PWM_A_6 = 0x04,
+    SIOB_PROC_28 = 0x05,
+    PIO0_28 = 0x06,
+    PIO1_28 = 0x07,
+    PIO2_28 = 0x08,
+    _RESERVED_9 = 0x09,
+    USB_MUXING_VBUS_DETECT = 0x0a,
+    _RESERVED_b = 0x0b,
+    _RESERVED_c = 0x0c,
+    _RESERVED_d = 0x0d,
+    _RESERVED_e = 0x0e,
+    _RESERVED_f = 0x0f,
+    _RESERVED_10 = 0x10,
+    _RESERVED_11 = 0x11,
+    _RESERVED_12 = 0x12,
+    _RESERVED_13 = 0x13,
+    _RESERVED_14 = 0x14,
+    _RESERVED_15 = 0x15,
+    _RESERVED_16 = 0x16,
+    _RESERVED_17 = 0x17,
+    _RESERVED_18 = 0x18,
+    _RESERVED_19 = 0x19,
+    _RESERVED_1a = 0x1a,
+    _RESERVED_1b = 0x1b,
+    _RESERVED_1c = 0x1c,
+    _RESERVED_1d = 0x1d,
+    _RESERVED_1e = 0x1e,
+    NULL = 0x1f,
+}
+impl Gpio28ctrlFuncsel {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Gpio28ctrlFuncsel {
+        unsafe { core::mem::transmute(val & 0x1f) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Gpio28ctrlFuncsel {
+    #[inline(always)]
+    fn from(val: u8) -> Gpio28ctrlFuncsel {
+        Gpio28ctrlFuncsel::from_bits(val)
+    }
+}
+impl From<Gpio28ctrlFuncsel> for u8 {
+    #[inline(always)]
+    fn from(val: Gpio28ctrlFuncsel) -> u8 {
+        Gpio28ctrlFuncsel::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Gpio29ctrlFuncsel {
+    _RESERVED_0 = 0,
+    SPI1_SS_N = 0x01,
+    UART0_RX = 0x02,
+    I2C0_SCL = 0x03,
+    PWM_B_6 = 0x04,
+    SIOB_PROC_29 = 0x05,
+    PIO0_29 = 0x06,
+    PIO1_29 = 0x07,
+    PIO2_29 = 0x08,
+    _RESERVED_9 = 0x09,
+    USB_MUXING_VBUS_EN = 0x0a,
+    _RESERVED_b = 0x0b,
+    _RESERVED_c = 0x0c,
+    _RESERVED_d = 0x0d,
+    _RESERVED_e = 0x0e,
+    _RESERVED_f = 0x0f,
+    _RESERVED_10 = 0x10,
+    _RESERVED_11 = 0x11,
+    _RESERVED_12 = 0x12,
+    _RESERVED_13 = 0x13,
+    _RESERVED_14 = 0x14,
+    _RESERVED_15 = 0x15,
+    _RESERVED_16 = 0x16,
+    _RESERVED_17 = 0x17,
+    _RESERVED_18 = 0x18,
+    _RESERVED_19 = 0x19,
+    _RESERVED_1a = 0x1a,
+    _RESERVED_1b = 0x1b,
+    _RESERVED_1c = 0x1c,
+    _RESERVED_1d = 0x1d,
+    _RESERVED_1e = 0x1e,
+    NULL = 0x1f,
+}
+impl Gpio29ctrlFuncsel {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Gpio29ctrlFuncsel {
+        unsafe { core::mem::transmute(val & 0x1f) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Gpio29ctrlFuncsel {
+    #[inline(always)]
+    fn from(val: u8) -> Gpio29ctrlFuncsel {
+        Gpio29ctrlFuncsel::from_bits(val)
+    }
+}
+impl From<Gpio29ctrlFuncsel> for u8 {
+    #[inline(always)]
+    fn from(val: Gpio29ctrlFuncsel) -> u8 {
+        Gpio29ctrlFuncsel::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Gpio2ctrlFuncsel {
+    JTAG_TDI = 0,
+    SPI0_SCLK = 0x01,
+    UART0_CTS = 0x02,
+    I2C1_SDA = 0x03,
+    PWM_A_1 = 0x04,
+    SIOB_PROC_2 = 0x05,
+    PIO0_2 = 0x06,
+    PIO1_2 = 0x07,
+    PIO2_2 = 0x08,
+    CORESIGHT_TRACEDATA_0 = 0x09,
+    USB_MUXING_VBUS_EN = 0x0a,
+    UART0_TX = 0x0b,
+    _RESERVED_c = 0x0c,
+    _RESERVED_d = 0x0d,
+    _RESERVED_e = 0x0e,
+    _RESERVED_f = 0x0f,
+    _RESERVED_10 = 0x10,
+    _RESERVED_11 = 0x11,
+    _RESERVED_12 = 0x12,
+    _RESERVED_13 = 0x13,
+    _RESERVED_14 = 0x14,
+    _RESERVED_15 = 0x15,
+    _RESERVED_16 = 0x16,
+    _RESERVED_17 = 0x17,
+    _RESERVED_18 = 0x18,
+    _RESERVED_19 = 0x19,
+    _RESERVED_1a = 0x1a,
+    _RESERVED_1b = 0x1b,
+    _RESERVED_1c = 0x1c,
+    _RESERVED_1d = 0x1d,
+    _RESERVED_1e = 0x1e,
+    NULL = 0x1f,
+}
+impl Gpio2ctrlFuncsel {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Gpio2ctrlFuncsel {
+        unsafe { core::mem::transmute(val & 0x1f) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Gpio2ctrlFuncsel {
+    #[inline(always)]
+    fn from(val: u8) -> Gpio2ctrlFuncsel {
+        Gpio2ctrlFuncsel::from_bits(val)
+    }
+}
+impl From<Gpio2ctrlFuncsel> for u8 {
+    #[inline(always)]
+    fn from(val: Gpio2ctrlFuncsel) -> u8 {
+        Gpio2ctrlFuncsel::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Gpio30ctrlFuncsel {
+    _RESERVED_0 = 0,
+    SPI1_SCLK = 0x01,
+    UART0_CTS = 0x02,
+    I2C1_SDA = 0x03,
+    PWM_A_7 = 0x04,
+    SIOB_PROC_30 = 0x05,
+    PIO0_30 = 0x06,
+    PIO1_30 = 0x07,
+    PIO2_30 = 0x08,
+    _RESERVED_9 = 0x09,
+    USB_MUXING_OVERCURR_DETECT = 0x0a,
+    UART0_TX = 0x0b,
+    _RESERVED_c = 0x0c,
+    _RESERVED_d = 0x0d,
+    _RESERVED_e = 0x0e,
+    _RESERVED_f = 0x0f,
+    _RESERVED_10 = 0x10,
+    _RESERVED_11 = 0x11,
+    _RESERVED_12 = 0x12,
+    _RESERVED_13 = 0x13,
+    _RESERVED_14 = 0x14,
+    _RESERVED_15 = 0x15,
+    _RESERVED_16 = 0x16,
+    _RESERVED_17 = 0x17,
+    _RESERVED_18 = 0x18,
+    _RESERVED_19 = 0x19,
+    _RESERVED_1a = 0x1a,
+    _RESERVED_1b = 0x1b,
+    _RESERVED_1c = 0x1c,
+    _RESERVED_1d = 0x1d,
+    _RESERVED_1e = 0x1e,
+    NULL = 0x1f,
+}
+impl Gpio30ctrlFuncsel {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Gpio30ctrlFuncsel {
+        unsafe { core::mem::transmute(val & 0x1f) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Gpio30ctrlFuncsel {
+    #[inline(always)]
+    fn from(val: u8) -> Gpio30ctrlFuncsel {
+        Gpio30ctrlFuncsel::from_bits(val)
+    }
+}
+impl From<Gpio30ctrlFuncsel> for u8 {
+    #[inline(always)]
+    fn from(val: Gpio30ctrlFuncsel) -> u8 {
+        Gpio30ctrlFuncsel::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Gpio31ctrlFuncsel {
+    _RESERVED_0 = 0,
+    SPI1_TX = 0x01,
+    UART0_RTS = 0x02,
+    I2C1_SCL = 0x03,
+    PWM_B_7 = 0x04,
+    SIOB_PROC_31 = 0x05,
+    PIO0_31 = 0x06,
+    PIO1_31 = 0x07,
+    PIO2_31 = 0x08,
+    _RESERVED_9 = 0x09,
+    USB_MUXING_VBUS_DETECT = 0x0a,
+    UART0_RX = 0x0b,
+    _RESERVED_c = 0x0c,
+    _RESERVED_d = 0x0d,
+    _RESERVED_e = 0x0e,
+    _RESERVED_f = 0x0f,
+    _RESERVED_10 = 0x10,
+    _RESERVED_11 = 0x11,
+    _RESERVED_12 = 0x12,
+    _RESERVED_13 = 0x13,
+    _RESERVED_14 = 0x14,
+    _RESERVED_15 = 0x15,
+    _RESERVED_16 = 0x16,
+    _RESERVED_17 = 0x17,
+    _RESERVED_18 = 0x18,
+    _RESERVED_19 = 0x19,
+    _RESERVED_1a = 0x1a,
+    _RESERVED_1b = 0x1b,
+    _RESERVED_1c = 0x1c,
+    _RESERVED_1d = 0x1d,
+    _RESERVED_1e = 0x1e,
+    NULL = 0x1f,
+}
+impl Gpio31ctrlFuncsel {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Gpio31ctrlFuncsel {
+        unsafe { core::mem::transmute(val & 0x1f) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Gpio31ctrlFuncsel {
+    #[inline(always)]
+    fn from(val: u8) -> Gpio31ctrlFuncsel {
+        Gpio31ctrlFuncsel::from_bits(val)
+    }
+}
+impl From<Gpio31ctrlFuncsel> for u8 {
+    #[inline(always)]
+    fn from(val: Gpio31ctrlFuncsel) -> u8 {
+        Gpio31ctrlFuncsel::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Gpio32ctrlFuncsel {
+    _RESERVED_0 = 0,
+    SPI0_RX = 0x01,
+    UART0_TX = 0x02,
+    I2C0_SDA = 0x03,
+    PWM_A_8 = 0x04,
+    SIOB_PROC_32 = 0x05,
+    PIO0_32 = 0x06,
+    PIO1_32 = 0x07,
+    PIO2_32 = 0x08,
+    _RESERVED_9 = 0x09,
+    USB_MUXING_VBUS_EN = 0x0a,
+    _RESERVED_b = 0x0b,
+    _RESERVED_c = 0x0c,
+    _RESERVED_d = 0x0d,
+    _RESERVED_e = 0x0e,
+    _RESERVED_f = 0x0f,
+    _RESERVED_10 = 0x10,
+    _RESERVED_11 = 0x11,
+    _RESERVED_12 = 0x12,
+    _RESERVED_13 = 0x13,
+    _RESERVED_14 = 0x14,
+    _RESERVED_15 = 0x15,
+    _RESERVED_16 = 0x16,
+    _RESERVED_17 = 0x17,
+    _RESERVED_18 = 0x18,
+    _RESERVED_19 = 0x19,
+    _RESERVED_1a = 0x1a,
+    _RESERVED_1b = 0x1b,
+    _RESERVED_1c = 0x1c,
+    _RESERVED_1d = 0x1d,
+    _RESERVED_1e = 0x1e,
+    NULL = 0x1f,
+}
+impl Gpio32ctrlFuncsel {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Gpio32ctrlFuncsel {
+        unsafe { core::mem::transmute(val & 0x1f) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Gpio32ctrlFuncsel {
+    #[inline(always)]
+    fn from(val: u8) -> Gpio32ctrlFuncsel {
+        Gpio32ctrlFuncsel::from_bits(val)
+    }
+}
+impl From<Gpio32ctrlFuncsel> for u8 {
+    #[inline(always)]
+    fn from(val: Gpio32ctrlFuncsel) -> u8 {
+        Gpio32ctrlFuncsel::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Gpio33ctrlFuncsel {
+    _RESERVED_0 = 0,
+    SPI0_SS_N = 0x01,
+    UART0_RX = 0x02,
+    I2C0_SCL = 0x03,
+    PWM_B_8 = 0x04,
+    SIOB_PROC_33 = 0x05,
+    PIO0_33 = 0x06,
+    PIO1_33 = 0x07,
+    PIO2_33 = 0x08,
+    _RESERVED_9 = 0x09,
+    USB_MUXING_OVERCURR_DETECT = 0x0a,
+    _RESERVED_b = 0x0b,
+    _RESERVED_c = 0x0c,
+    _RESERVED_d = 0x0d,
+    _RESERVED_e = 0x0e,
+    _RESERVED_f = 0x0f,
+    _RESERVED_10 = 0x10,
+    _RESERVED_11 = 0x11,
+    _RESERVED_12 = 0x12,
+    _RESERVED_13 = 0x13,
+    _RESERVED_14 = 0x14,
+    _RESERVED_15 = 0x15,
+    _RESERVED_16 = 0x16,
+    _RESERVED_17 = 0x17,
+    _RESERVED_18 = 0x18,
+    _RESERVED_19 = 0x19,
+    _RESERVED_1a = 0x1a,
+    _RESERVED_1b = 0x1b,
+    _RESERVED_1c = 0x1c,
+    _RESERVED_1d = 0x1d,
+    _RESERVED_1e = 0x1e,
+    NULL = 0x1f,
+}
+impl Gpio33ctrlFuncsel {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Gpio33ctrlFuncsel {
+        unsafe { core::mem::transmute(val & 0x1f) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Gpio33ctrlFuncsel {
+    #[inline(always)]
+    fn from(val: u8) -> Gpio33ctrlFuncsel {
+        Gpio33ctrlFuncsel::from_bits(val)
+    }
+}
+impl From<Gpio33ctrlFuncsel> for u8 {
+    #[inline(always)]
+    fn from(val: Gpio33ctrlFuncsel) -> u8 {
+        Gpio33ctrlFuncsel::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Gpio34ctrlFuncsel {
+    _RESERVED_0 = 0,
+    SPI0_SCLK = 0x01,
+    UART0_CTS = 0x02,
+    I2C1_SDA = 0x03,
+    PWM_A_9 = 0x04,
+    SIOB_PROC_34 = 0x05,
+    PIO0_34 = 0x06,
+    PIO1_34 = 0x07,
+    PIO2_34 = 0x08,
+    _RESERVED_9 = 0x09,
+    USB_MUXING_VBUS_DETECT = 0x0a,
+    UART0_TX = 0x0b,
+    _RESERVED_c = 0x0c,
+    _RESERVED_d = 0x0d,
+    _RESERVED_e = 0x0e,
+    _RESERVED_f = 0x0f,
+    _RESERVED_10 = 0x10,
+    _RESERVED_11 = 0x11,
+    _RESERVED_12 = 0x12,
+    _RESERVED_13 = 0x13,
+    _RESERVED_14 = 0x14,
+    _RESERVED_15 = 0x15,
+    _RESERVED_16 = 0x16,
+    _RESERVED_17 = 0x17,
+    _RESERVED_18 = 0x18,
+    _RESERVED_19 = 0x19,
+    _RESERVED_1a = 0x1a,
+    _RESERVED_1b = 0x1b,
+    _RESERVED_1c = 0x1c,
+    _RESERVED_1d = 0x1d,
+    _RESERVED_1e = 0x1e,
+    NULL = 0x1f,
+}
+impl Gpio34ctrlFuncsel {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Gpio34ctrlFuncsel {
+        unsafe { core::mem::transmute(val & 0x1f) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Gpio34ctrlFuncsel {
+    #[inline(always)]
+    fn from(val: u8) -> Gpio34ctrlFuncsel {
+        Gpio34ctrlFuncsel::from_bits(val)
+    }
+}
+impl From<Gpio34ctrlFuncsel> for u8 {
+    #[inline(always)]
+    fn from(val: Gpio34ctrlFuncsel) -> u8 {
+        Gpio34ctrlFuncsel::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Gpio35ctrlFuncsel {
+    _RESERVED_0 = 0,
+    SPI0_TX = 0x01,
+    UART0_RTS = 0x02,
+    I2C1_SCL = 0x03,
+    PWM_B_9 = 0x04,
+    SIOB_PROC_35 = 0x05,
+    PIO0_35 = 0x06,
+    PIO1_35 = 0x07,
+    PIO2_35 = 0x08,
+    _RESERVED_9 = 0x09,
+    USB_MUXING_VBUS_EN = 0x0a,
+    UART0_RX = 0x0b,
+    _RESERVED_c = 0x0c,
+    _RESERVED_d = 0x0d,
+    _RESERVED_e = 0x0e,
+    _RESERVED_f = 0x0f,
+    _RESERVED_10 = 0x10,
+    _RESERVED_11 = 0x11,
+    _RESERVED_12 = 0x12,
+    _RESERVED_13 = 0x13,
+    _RESERVED_14 = 0x14,
+    _RESERVED_15 = 0x15,
+    _RESERVED_16 = 0x16,
+    _RESERVED_17 = 0x17,
+    _RESERVED_18 = 0x18,
+    _RESERVED_19 = 0x19,
+    _RESERVED_1a = 0x1a,
+    _RESERVED_1b = 0x1b,
+    _RESERVED_1c = 0x1c,
+    _RESERVED_1d = 0x1d,
+    _RESERVED_1e = 0x1e,
+    NULL = 0x1f,
+}
+impl Gpio35ctrlFuncsel {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Gpio35ctrlFuncsel {
+        unsafe { core::mem::transmute(val & 0x1f) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Gpio35ctrlFuncsel {
+    #[inline(always)]
+    fn from(val: u8) -> Gpio35ctrlFuncsel {
+        Gpio35ctrlFuncsel::from_bits(val)
+    }
+}
+impl From<Gpio35ctrlFuncsel> for u8 {
+    #[inline(always)]
+    fn from(val: Gpio35ctrlFuncsel) -> u8 {
+        Gpio35ctrlFuncsel::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Gpio36ctrlFuncsel {
+    _RESERVED_0 = 0,
+    SPI0_RX = 0x01,
+    UART1_TX = 0x02,
+    I2C0_SDA = 0x03,
+    PWM_A_10 = 0x04,
+    SIOB_PROC_36 = 0x05,
+    PIO0_36 = 0x06,
+    PIO1_36 = 0x07,
+    PIO2_36 = 0x08,
+    _RESERVED_9 = 0x09,
+    USB_MUXING_OVERCURR_DETECT = 0x0a,
+    _RESERVED_b = 0x0b,
+    _RESERVED_c = 0x0c,
+    _RESERVED_d = 0x0d,
+    _RESERVED_e = 0x0e,
+    _RESERVED_f = 0x0f,
+    _RESERVED_10 = 0x10,
+    _RESERVED_11 = 0x11,
+    _RESERVED_12 = 0x12,
+    _RESERVED_13 = 0x13,
+    _RESERVED_14 = 0x14,
+    _RESERVED_15 = 0x15,
+    _RESERVED_16 = 0x16,
+    _RESERVED_17 = 0x17,
+    _RESERVED_18 = 0x18,
+    _RESERVED_19 = 0x19,
+    _RESERVED_1a = 0x1a,
+    _RESERVED_1b = 0x1b,
+    _RESERVED_1c = 0x1c,
+    _RESERVED_1d = 0x1d,
+    _RESERVED_1e = 0x1e,
+    NULL = 0x1f,
+}
+impl Gpio36ctrlFuncsel {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Gpio36ctrlFuncsel {
+        unsafe { core::mem::transmute(val & 0x1f) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Gpio36ctrlFuncsel {
+    #[inline(always)]
+    fn from(val: u8) -> Gpio36ctrlFuncsel {
+        Gpio36ctrlFuncsel::from_bits(val)
+    }
+}
+impl From<Gpio36ctrlFuncsel> for u8 {
+    #[inline(always)]
+    fn from(val: Gpio36ctrlFuncsel) -> u8 {
+        Gpio36ctrlFuncsel::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Gpio37ctrlFuncsel {
+    _RESERVED_0 = 0,
+    SPI0_SS_N = 0x01,
+    UART1_RX = 0x02,
+    I2C0_SCL = 0x03,
+    PWM_B_10 = 0x04,
+    SIOB_PROC_37 = 0x05,
+    PIO0_37 = 0x06,
+    PIO1_37 = 0x07,
+    PIO2_37 = 0x08,
+    _RESERVED_9 = 0x09,
+    USB_MUXING_VBUS_DETECT = 0x0a,
+    _RESERVED_b = 0x0b,
+    _RESERVED_c = 0x0c,
+    _RESERVED_d = 0x0d,
+    _RESERVED_e = 0x0e,
+    _RESERVED_f = 0x0f,
+    _RESERVED_10 = 0x10,
+    _RESERVED_11 = 0x11,
+    _RESERVED_12 = 0x12,
+    _RESERVED_13 = 0x13,
+    _RESERVED_14 = 0x14,
+    _RESERVED_15 = 0x15,
+    _RESERVED_16 = 0x16,
+    _RESERVED_17 = 0x17,
+    _RESERVED_18 = 0x18,
+    _RESERVED_19 = 0x19,
+    _RESERVED_1a = 0x1a,
+    _RESERVED_1b = 0x1b,
+    _RESERVED_1c = 0x1c,
+    _RESERVED_1d = 0x1d,
+    _RESERVED_1e = 0x1e,
+    NULL = 0x1f,
+}
+impl Gpio37ctrlFuncsel {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Gpio37ctrlFuncsel {
+        unsafe { core::mem::transmute(val & 0x1f) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Gpio37ctrlFuncsel {
+    #[inline(always)]
+    fn from(val: u8) -> Gpio37ctrlFuncsel {
+        Gpio37ctrlFuncsel::from_bits(val)
+    }
+}
+impl From<Gpio37ctrlFuncsel> for u8 {
+    #[inline(always)]
+    fn from(val: Gpio37ctrlFuncsel) -> u8 {
+        Gpio37ctrlFuncsel::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Gpio38ctrlFuncsel {
+    _RESERVED_0 = 0,
+    SPI0_SCLK = 0x01,
+    UART1_CTS = 0x02,
+    I2C1_SDA = 0x03,
+    PWM_A_11 = 0x04,
+    SIOB_PROC_38 = 0x05,
+    PIO0_38 = 0x06,
+    PIO1_38 = 0x07,
+    PIO2_38 = 0x08,
+    _RESERVED_9 = 0x09,
+    USB_MUXING_VBUS_EN = 0x0a,
+    UART1_TX = 0x0b,
+    _RESERVED_c = 0x0c,
+    _RESERVED_d = 0x0d,
+    _RESERVED_e = 0x0e,
+    _RESERVED_f = 0x0f,
+    _RESERVED_10 = 0x10,
+    _RESERVED_11 = 0x11,
+    _RESERVED_12 = 0x12,
+    _RESERVED_13 = 0x13,
+    _RESERVED_14 = 0x14,
+    _RESERVED_15 = 0x15,
+    _RESERVED_16 = 0x16,
+    _RESERVED_17 = 0x17,
+    _RESERVED_18 = 0x18,
+    _RESERVED_19 = 0x19,
+    _RESERVED_1a = 0x1a,
+    _RESERVED_1b = 0x1b,
+    _RESERVED_1c = 0x1c,
+    _RESERVED_1d = 0x1d,
+    _RESERVED_1e = 0x1e,
+    NULL = 0x1f,
+}
+impl Gpio38ctrlFuncsel {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Gpio38ctrlFuncsel {
+        unsafe { core::mem::transmute(val & 0x1f) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Gpio38ctrlFuncsel {
+    #[inline(always)]
+    fn from(val: u8) -> Gpio38ctrlFuncsel {
+        Gpio38ctrlFuncsel::from_bits(val)
+    }
+}
+impl From<Gpio38ctrlFuncsel> for u8 {
+    #[inline(always)]
+    fn from(val: Gpio38ctrlFuncsel) -> u8 {
+        Gpio38ctrlFuncsel::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Gpio39ctrlFuncsel {
+    _RESERVED_0 = 0,
+    SPI0_TX = 0x01,
+    UART1_RTS = 0x02,
+    I2C1_SCL = 0x03,
+    PWM_B_11 = 0x04,
+    SIOB_PROC_39 = 0x05,
+    PIO0_39 = 0x06,
+    PIO1_39 = 0x07,
+    PIO2_39 = 0x08,
+    _RESERVED_9 = 0x09,
+    USB_MUXING_OVERCURR_DETECT = 0x0a,
+    UART1_RX = 0x0b,
+    _RESERVED_c = 0x0c,
+    _RESERVED_d = 0x0d,
+    _RESERVED_e = 0x0e,
+    _RESERVED_f = 0x0f,
+    _RESERVED_10 = 0x10,
+    _RESERVED_11 = 0x11,
+    _RESERVED_12 = 0x12,
+    _RESERVED_13 = 0x13,
+    _RESERVED_14 = 0x14,
+    _RESERVED_15 = 0x15,
+    _RESERVED_16 = 0x16,
+    _RESERVED_17 = 0x17,
+    _RESERVED_18 = 0x18,
+    _RESERVED_19 = 0x19,
+    _RESERVED_1a = 0x1a,
+    _RESERVED_1b = 0x1b,
+    _RESERVED_1c = 0x1c,
+    _RESERVED_1d = 0x1d,
+    _RESERVED_1e = 0x1e,
+    NULL = 0x1f,
+}
+impl Gpio39ctrlFuncsel {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Gpio39ctrlFuncsel {
+        unsafe { core::mem::transmute(val & 0x1f) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Gpio39ctrlFuncsel {
+    #[inline(always)]
+    fn from(val: u8) -> Gpio39ctrlFuncsel {
+        Gpio39ctrlFuncsel::from_bits(val)
+    }
+}
+impl From<Gpio39ctrlFuncsel> for u8 {
+    #[inline(always)]
+    fn from(val: Gpio39ctrlFuncsel) -> u8 {
+        Gpio39ctrlFuncsel::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Gpio3ctrlFuncsel {
+    JTAG_TDO = 0,
+    SPI0_TX = 0x01,
+    UART0_RTS = 0x02,
+    I2C1_SCL = 0x03,
+    PWM_B_1 = 0x04,
+    SIOB_PROC_3 = 0x05,
+    PIO0_3 = 0x06,
+    PIO1_3 = 0x07,
+    PIO2_3 = 0x08,
+    CORESIGHT_TRACEDATA_1 = 0x09,
+    USB_MUXING_OVERCURR_DETECT = 0x0a,
+    UART0_RX = 0x0b,
+    _RESERVED_c = 0x0c,
+    _RESERVED_d = 0x0d,
+    _RESERVED_e = 0x0e,
+    _RESERVED_f = 0x0f,
+    _RESERVED_10 = 0x10,
+    _RESERVED_11 = 0x11,
+    _RESERVED_12 = 0x12,
+    _RESERVED_13 = 0x13,
+    _RESERVED_14 = 0x14,
+    _RESERVED_15 = 0x15,
+    _RESERVED_16 = 0x16,
+    _RESERVED_17 = 0x17,
+    _RESERVED_18 = 0x18,
+    _RESERVED_19 = 0x19,
+    _RESERVED_1a = 0x1a,
+    _RESERVED_1b = 0x1b,
+    _RESERVED_1c = 0x1c,
+    _RESERVED_1d = 0x1d,
+    _RESERVED_1e = 0x1e,
+    NULL = 0x1f,
+}
+impl Gpio3ctrlFuncsel {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Gpio3ctrlFuncsel {
+        unsafe { core::mem::transmute(val & 0x1f) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Gpio3ctrlFuncsel {
+    #[inline(always)]
+    fn from(val: u8) -> Gpio3ctrlFuncsel {
+        Gpio3ctrlFuncsel::from_bits(val)
+    }
+}
+impl From<Gpio3ctrlFuncsel> for u8 {
+    #[inline(always)]
+    fn from(val: Gpio3ctrlFuncsel) -> u8 {
+        Gpio3ctrlFuncsel::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Gpio40ctrlFuncsel {
+    _RESERVED_0 = 0,
+    SPI1_RX = 0x01,
+    UART1_TX = 0x02,
+    I2C0_SDA = 0x03,
+    PWM_A_8 = 0x04,
+    SIOB_PROC_40 = 0x05,
+    PIO0_40 = 0x06,
+    PIO1_40 = 0x07,
+    PIO2_40 = 0x08,
+    _RESERVED_9 = 0x09,
+    USB_MUXING_VBUS_DETECT = 0x0a,
+    _RESERVED_b = 0x0b,
+    _RESERVED_c = 0x0c,
+    _RESERVED_d = 0x0d,
+    _RESERVED_e = 0x0e,
+    _RESERVED_f = 0x0f,
+    _RESERVED_10 = 0x10,
+    _RESERVED_11 = 0x11,
+    _RESERVED_12 = 0x12,
+    _RESERVED_13 = 0x13,
+    _RESERVED_14 = 0x14,
+    _RESERVED_15 = 0x15,
+    _RESERVED_16 = 0x16,
+    _RESERVED_17 = 0x17,
+    _RESERVED_18 = 0x18,
+    _RESERVED_19 = 0x19,
+    _RESERVED_1a = 0x1a,
+    _RESERVED_1b = 0x1b,
+    _RESERVED_1c = 0x1c,
+    _RESERVED_1d = 0x1d,
+    _RESERVED_1e = 0x1e,
+    NULL = 0x1f,
+}
+impl Gpio40ctrlFuncsel {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Gpio40ctrlFuncsel {
+        unsafe { core::mem::transmute(val & 0x1f) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Gpio40ctrlFuncsel {
+    #[inline(always)]
+    fn from(val: u8) -> Gpio40ctrlFuncsel {
+        Gpio40ctrlFuncsel::from_bits(val)
+    }
+}
+impl From<Gpio40ctrlFuncsel> for u8 {
+    #[inline(always)]
+    fn from(val: Gpio40ctrlFuncsel) -> u8 {
+        Gpio40ctrlFuncsel::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Gpio41ctrlFuncsel {
+    _RESERVED_0 = 0,
+    SPI1_SS_N = 0x01,
+    UART1_RX = 0x02,
+    I2C0_SCL = 0x03,
+    PWM_B_8 = 0x04,
+    SIOB_PROC_41 = 0x05,
+    PIO0_41 = 0x06,
+    PIO1_41 = 0x07,
+    PIO2_41 = 0x08,
+    _RESERVED_9 = 0x09,
+    USB_MUXING_VBUS_EN = 0x0a,
+    _RESERVED_b = 0x0b,
+    _RESERVED_c = 0x0c,
+    _RESERVED_d = 0x0d,
+    _RESERVED_e = 0x0e,
+    _RESERVED_f = 0x0f,
+    _RESERVED_10 = 0x10,
+    _RESERVED_11 = 0x11,
+    _RESERVED_12 = 0x12,
+    _RESERVED_13 = 0x13,
+    _RESERVED_14 = 0x14,
+    _RESERVED_15 = 0x15,
+    _RESERVED_16 = 0x16,
+    _RESERVED_17 = 0x17,
+    _RESERVED_18 = 0x18,
+    _RESERVED_19 = 0x19,
+    _RESERVED_1a = 0x1a,
+    _RESERVED_1b = 0x1b,
+    _RESERVED_1c = 0x1c,
+    _RESERVED_1d = 0x1d,
+    _RESERVED_1e = 0x1e,
+    NULL = 0x1f,
+}
+impl Gpio41ctrlFuncsel {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Gpio41ctrlFuncsel {
+        unsafe { core::mem::transmute(val & 0x1f) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Gpio41ctrlFuncsel {
+    #[inline(always)]
+    fn from(val: u8) -> Gpio41ctrlFuncsel {
+        Gpio41ctrlFuncsel::from_bits(val)
+    }
+}
+impl From<Gpio41ctrlFuncsel> for u8 {
+    #[inline(always)]
+    fn from(val: Gpio41ctrlFuncsel) -> u8 {
+        Gpio41ctrlFuncsel::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Gpio42ctrlFuncsel {
+    _RESERVED_0 = 0,
+    SPI1_SCLK = 0x01,
+    UART1_CTS = 0x02,
+    I2C1_SDA = 0x03,
+    PWM_A_9 = 0x04,
+    SIOB_PROC_42 = 0x05,
+    PIO0_42 = 0x06,
+    PIO1_42 = 0x07,
+    PIO2_42 = 0x08,
+    _RESERVED_9 = 0x09,
+    USB_MUXING_OVERCURR_DETECT = 0x0a,
+    UART1_TX = 0x0b,
+    _RESERVED_c = 0x0c,
+    _RESERVED_d = 0x0d,
+    _RESERVED_e = 0x0e,
+    _RESERVED_f = 0x0f,
+    _RESERVED_10 = 0x10,
+    _RESERVED_11 = 0x11,
+    _RESERVED_12 = 0x12,
+    _RESERVED_13 = 0x13,
+    _RESERVED_14 = 0x14,
+    _RESERVED_15 = 0x15,
+    _RESERVED_16 = 0x16,
+    _RESERVED_17 = 0x17,
+    _RESERVED_18 = 0x18,
+    _RESERVED_19 = 0x19,
+    _RESERVED_1a = 0x1a,
+    _RESERVED_1b = 0x1b,
+    _RESERVED_1c = 0x1c,
+    _RESERVED_1d = 0x1d,
+    _RESERVED_1e = 0x1e,
+    NULL = 0x1f,
+}
+impl Gpio42ctrlFuncsel {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Gpio42ctrlFuncsel {
+        unsafe { core::mem::transmute(val & 0x1f) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Gpio42ctrlFuncsel {
+    #[inline(always)]
+    fn from(val: u8) -> Gpio42ctrlFuncsel {
+        Gpio42ctrlFuncsel::from_bits(val)
+    }
+}
+impl From<Gpio42ctrlFuncsel> for u8 {
+    #[inline(always)]
+    fn from(val: Gpio42ctrlFuncsel) -> u8 {
+        Gpio42ctrlFuncsel::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Gpio43ctrlFuncsel {
+    _RESERVED_0 = 0,
+    SPI1_TX = 0x01,
+    UART1_RTS = 0x02,
+    I2C1_SCL = 0x03,
+    PWM_B_9 = 0x04,
+    SIOB_PROC_43 = 0x05,
+    PIO0_43 = 0x06,
+    PIO1_43 = 0x07,
+    PIO2_43 = 0x08,
+    _RESERVED_9 = 0x09,
+    USB_MUXING_VBUS_DETECT = 0x0a,
+    UART1_RX = 0x0b,
+    _RESERVED_c = 0x0c,
+    _RESERVED_d = 0x0d,
+    _RESERVED_e = 0x0e,
+    _RESERVED_f = 0x0f,
+    _RESERVED_10 = 0x10,
+    _RESERVED_11 = 0x11,
+    _RESERVED_12 = 0x12,
+    _RESERVED_13 = 0x13,
+    _RESERVED_14 = 0x14,
+    _RESERVED_15 = 0x15,
+    _RESERVED_16 = 0x16,
+    _RESERVED_17 = 0x17,
+    _RESERVED_18 = 0x18,
+    _RESERVED_19 = 0x19,
+    _RESERVED_1a = 0x1a,
+    _RESERVED_1b = 0x1b,
+    _RESERVED_1c = 0x1c,
+    _RESERVED_1d = 0x1d,
+    _RESERVED_1e = 0x1e,
+    NULL = 0x1f,
+}
+impl Gpio43ctrlFuncsel {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Gpio43ctrlFuncsel {
+        unsafe { core::mem::transmute(val & 0x1f) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Gpio43ctrlFuncsel {
+    #[inline(always)]
+    fn from(val: u8) -> Gpio43ctrlFuncsel {
+        Gpio43ctrlFuncsel::from_bits(val)
+    }
+}
+impl From<Gpio43ctrlFuncsel> for u8 {
+    #[inline(always)]
+    fn from(val: Gpio43ctrlFuncsel) -> u8 {
+        Gpio43ctrlFuncsel::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Gpio44ctrlFuncsel {
+    _RESERVED_0 = 0,
+    SPI1_RX = 0x01,
+    UART0_TX = 0x02,
+    I2C0_SDA = 0x03,
+    PWM_A_10 = 0x04,
+    SIOB_PROC_44 = 0x05,
+    PIO0_44 = 0x06,
+    PIO1_44 = 0x07,
+    PIO2_44 = 0x08,
+    _RESERVED_9 = 0x09,
+    USB_MUXING_VBUS_EN = 0x0a,
+    _RESERVED_b = 0x0b,
+    _RESERVED_c = 0x0c,
+    _RESERVED_d = 0x0d,
+    _RESERVED_e = 0x0e,
+    _RESERVED_f = 0x0f,
+    _RESERVED_10 = 0x10,
+    _RESERVED_11 = 0x11,
+    _RESERVED_12 = 0x12,
+    _RESERVED_13 = 0x13,
+    _RESERVED_14 = 0x14,
+    _RESERVED_15 = 0x15,
+    _RESERVED_16 = 0x16,
+    _RESERVED_17 = 0x17,
+    _RESERVED_18 = 0x18,
+    _RESERVED_19 = 0x19,
+    _RESERVED_1a = 0x1a,
+    _RESERVED_1b = 0x1b,
+    _RESERVED_1c = 0x1c,
+    _RESERVED_1d = 0x1d,
+    _RESERVED_1e = 0x1e,
+    NULL = 0x1f,
+}
+impl Gpio44ctrlFuncsel {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Gpio44ctrlFuncsel {
+        unsafe { core::mem::transmute(val & 0x1f) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Gpio44ctrlFuncsel {
+    #[inline(always)]
+    fn from(val: u8) -> Gpio44ctrlFuncsel {
+        Gpio44ctrlFuncsel::from_bits(val)
+    }
+}
+impl From<Gpio44ctrlFuncsel> for u8 {
+    #[inline(always)]
+    fn from(val: Gpio44ctrlFuncsel) -> u8 {
+        Gpio44ctrlFuncsel::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Gpio45ctrlFuncsel {
+    _RESERVED_0 = 0,
+    SPI1_SS_N = 0x01,
+    UART0_RX = 0x02,
+    I2C0_SCL = 0x03,
+    PWM_B_10 = 0x04,
+    SIOB_PROC_45 = 0x05,
+    PIO0_45 = 0x06,
+    PIO1_45 = 0x07,
+    PIO2_45 = 0x08,
+    _RESERVED_9 = 0x09,
+    USB_MUXING_OVERCURR_DETECT = 0x0a,
+    _RESERVED_b = 0x0b,
+    _RESERVED_c = 0x0c,
+    _RESERVED_d = 0x0d,
+    _RESERVED_e = 0x0e,
+    _RESERVED_f = 0x0f,
+    _RESERVED_10 = 0x10,
+    _RESERVED_11 = 0x11,
+    _RESERVED_12 = 0x12,
+    _RESERVED_13 = 0x13,
+    _RESERVED_14 = 0x14,
+    _RESERVED_15 = 0x15,
+    _RESERVED_16 = 0x16,
+    _RESERVED_17 = 0x17,
+    _RESERVED_18 = 0x18,
+    _RESERVED_19 = 0x19,
+    _RESERVED_1a = 0x1a,
+    _RESERVED_1b = 0x1b,
+    _RESERVED_1c = 0x1c,
+    _RESERVED_1d = 0x1d,
+    _RESERVED_1e = 0x1e,
+    NULL = 0x1f,
+}
+impl Gpio45ctrlFuncsel {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Gpio45ctrlFuncsel {
+        unsafe { core::mem::transmute(val & 0x1f) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Gpio45ctrlFuncsel {
+    #[inline(always)]
+    fn from(val: u8) -> Gpio45ctrlFuncsel {
+        Gpio45ctrlFuncsel::from_bits(val)
+    }
+}
+impl From<Gpio45ctrlFuncsel> for u8 {
+    #[inline(always)]
+    fn from(val: Gpio45ctrlFuncsel) -> u8 {
+        Gpio45ctrlFuncsel::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Gpio46ctrlFuncsel {
+    _RESERVED_0 = 0,
+    SPI1_SCLK = 0x01,
+    UART0_CTS = 0x02,
+    I2C1_SDA = 0x03,
+    PWM_A_11 = 0x04,
+    SIOB_PROC_46 = 0x05,
+    PIO0_46 = 0x06,
+    PIO1_46 = 0x07,
+    PIO2_46 = 0x08,
+    _RESERVED_9 = 0x09,
+    USB_MUXING_VBUS_DETECT = 0x0a,
+    UART0_TX = 0x0b,
+    _RESERVED_c = 0x0c,
+    _RESERVED_d = 0x0d,
+    _RESERVED_e = 0x0e,
+    _RESERVED_f = 0x0f,
+    _RESERVED_10 = 0x10,
+    _RESERVED_11 = 0x11,
+    _RESERVED_12 = 0x12,
+    _RESERVED_13 = 0x13,
+    _RESERVED_14 = 0x14,
+    _RESERVED_15 = 0x15,
+    _RESERVED_16 = 0x16,
+    _RESERVED_17 = 0x17,
+    _RESERVED_18 = 0x18,
+    _RESERVED_19 = 0x19,
+    _RESERVED_1a = 0x1a,
+    _RESERVED_1b = 0x1b,
+    _RESERVED_1c = 0x1c,
+    _RESERVED_1d = 0x1d,
+    _RESERVED_1e = 0x1e,
+    NULL = 0x1f,
+}
+impl Gpio46ctrlFuncsel {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Gpio46ctrlFuncsel {
+        unsafe { core::mem::transmute(val & 0x1f) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Gpio46ctrlFuncsel {
+    #[inline(always)]
+    fn from(val: u8) -> Gpio46ctrlFuncsel {
+        Gpio46ctrlFuncsel::from_bits(val)
+    }
+}
+impl From<Gpio46ctrlFuncsel> for u8 {
+    #[inline(always)]
+    fn from(val: Gpio46ctrlFuncsel) -> u8 {
+        Gpio46ctrlFuncsel::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Gpio47ctrlFuncsel {
+    _RESERVED_0 = 0,
+    SPI1_TX = 0x01,
+    UART0_RTS = 0x02,
+    I2C1_SCL = 0x03,
+    PWM_B_11 = 0x04,
+    SIOB_PROC_47 = 0x05,
+    PIO0_47 = 0x06,
+    PIO1_47 = 0x07,
+    PIO2_47 = 0x08,
+    XIP_SS_N_1 = 0x09,
+    USB_MUXING_VBUS_EN = 0x0a,
+    UART0_RX = 0x0b,
+    _RESERVED_c = 0x0c,
+    _RESERVED_d = 0x0d,
+    _RESERVED_e = 0x0e,
+    _RESERVED_f = 0x0f,
+    _RESERVED_10 = 0x10,
+    _RESERVED_11 = 0x11,
+    _RESERVED_12 = 0x12,
+    _RESERVED_13 = 0x13,
+    _RESERVED_14 = 0x14,
+    _RESERVED_15 = 0x15,
+    _RESERVED_16 = 0x16,
+    _RESERVED_17 = 0x17,
+    _RESERVED_18 = 0x18,
+    _RESERVED_19 = 0x19,
+    _RESERVED_1a = 0x1a,
+    _RESERVED_1b = 0x1b,
+    _RESERVED_1c = 0x1c,
+    _RESERVED_1d = 0x1d,
+    _RESERVED_1e = 0x1e,
+    NULL = 0x1f,
+}
+impl Gpio47ctrlFuncsel {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Gpio47ctrlFuncsel {
+        unsafe { core::mem::transmute(val & 0x1f) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Gpio47ctrlFuncsel {
+    #[inline(always)]
+    fn from(val: u8) -> Gpio47ctrlFuncsel {
+        Gpio47ctrlFuncsel::from_bits(val)
+    }
+}
+impl From<Gpio47ctrlFuncsel> for u8 {
+    #[inline(always)]
+    fn from(val: Gpio47ctrlFuncsel) -> u8 {
+        Gpio47ctrlFuncsel::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Gpio4ctrlFuncsel {
+    _RESERVED_0 = 0,
+    SPI0_RX = 0x01,
+    UART1_TX = 0x02,
+    I2C0_SDA = 0x03,
+    PWM_A_2 = 0x04,
+    SIOB_PROC_4 = 0x05,
+    PIO0_4 = 0x06,
+    PIO1_4 = 0x07,
+    PIO2_4 = 0x08,
+    CORESIGHT_TRACEDATA_2 = 0x09,
+    USB_MUXING_VBUS_DETECT = 0x0a,
+    _RESERVED_b = 0x0b,
+    _RESERVED_c = 0x0c,
+    _RESERVED_d = 0x0d,
+    _RESERVED_e = 0x0e,
+    _RESERVED_f = 0x0f,
+    _RESERVED_10 = 0x10,
+    _RESERVED_11 = 0x11,
+    _RESERVED_12 = 0x12,
+    _RESERVED_13 = 0x13,
+    _RESERVED_14 = 0x14,
+    _RESERVED_15 = 0x15,
+    _RESERVED_16 = 0x16,
+    _RESERVED_17 = 0x17,
+    _RESERVED_18 = 0x18,
+    _RESERVED_19 = 0x19,
+    _RESERVED_1a = 0x1a,
+    _RESERVED_1b = 0x1b,
+    _RESERVED_1c = 0x1c,
+    _RESERVED_1d = 0x1d,
+    _RESERVED_1e = 0x1e,
+    NULL = 0x1f,
+}
+impl Gpio4ctrlFuncsel {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Gpio4ctrlFuncsel {
+        unsafe { core::mem::transmute(val & 0x1f) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Gpio4ctrlFuncsel {
+    #[inline(always)]
+    fn from(val: u8) -> Gpio4ctrlFuncsel {
+        Gpio4ctrlFuncsel::from_bits(val)
+    }
+}
+impl From<Gpio4ctrlFuncsel> for u8 {
+    #[inline(always)]
+    fn from(val: Gpio4ctrlFuncsel) -> u8 {
+        Gpio4ctrlFuncsel::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Gpio5ctrlFuncsel {
+    _RESERVED_0 = 0,
+    SPI0_SS_N = 0x01,
+    UART1_RX = 0x02,
+    I2C0_SCL = 0x03,
+    PWM_B_2 = 0x04,
+    SIOB_PROC_5 = 0x05,
+    PIO0_5 = 0x06,
+    PIO1_5 = 0x07,
+    PIO2_5 = 0x08,
+    CORESIGHT_TRACEDATA_3 = 0x09,
+    USB_MUXING_VBUS_EN = 0x0a,
+    _RESERVED_b = 0x0b,
+    _RESERVED_c = 0x0c,
+    _RESERVED_d = 0x0d,
+    _RESERVED_e = 0x0e,
+    _RESERVED_f = 0x0f,
+    _RESERVED_10 = 0x10,
+    _RESERVED_11 = 0x11,
+    _RESERVED_12 = 0x12,
+    _RESERVED_13 = 0x13,
+    _RESERVED_14 = 0x14,
+    _RESERVED_15 = 0x15,
+    _RESERVED_16 = 0x16,
+    _RESERVED_17 = 0x17,
+    _RESERVED_18 = 0x18,
+    _RESERVED_19 = 0x19,
+    _RESERVED_1a = 0x1a,
+    _RESERVED_1b = 0x1b,
+    _RESERVED_1c = 0x1c,
+    _RESERVED_1d = 0x1d,
+    _RESERVED_1e = 0x1e,
+    NULL = 0x1f,
+}
+impl Gpio5ctrlFuncsel {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Gpio5ctrlFuncsel {
+        unsafe { core::mem::transmute(val & 0x1f) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Gpio5ctrlFuncsel {
+    #[inline(always)]
+    fn from(val: u8) -> Gpio5ctrlFuncsel {
+        Gpio5ctrlFuncsel::from_bits(val)
+    }
+}
+impl From<Gpio5ctrlFuncsel> for u8 {
+    #[inline(always)]
+    fn from(val: Gpio5ctrlFuncsel) -> u8 {
+        Gpio5ctrlFuncsel::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Gpio6ctrlFuncsel {
+    _RESERVED_0 = 0,
+    SPI0_SCLK = 0x01,
+    UART1_CTS = 0x02,
+    I2C1_SDA = 0x03,
+    PWM_A_3 = 0x04,
+    SIOB_PROC_6 = 0x05,
+    PIO0_6 = 0x06,
+    PIO1_6 = 0x07,
+    PIO2_6 = 0x08,
+    _RESERVED_9 = 0x09,
+    USB_MUXING_OVERCURR_DETECT = 0x0a,
+    UART1_TX = 0x0b,
+    _RESERVED_c = 0x0c,
+    _RESERVED_d = 0x0d,
+    _RESERVED_e = 0x0e,
+    _RESERVED_f = 0x0f,
+    _RESERVED_10 = 0x10,
+    _RESERVED_11 = 0x11,
+    _RESERVED_12 = 0x12,
+    _RESERVED_13 = 0x13,
+    _RESERVED_14 = 0x14,
+    _RESERVED_15 = 0x15,
+    _RESERVED_16 = 0x16,
+    _RESERVED_17 = 0x17,
+    _RESERVED_18 = 0x18,
+    _RESERVED_19 = 0x19,
+    _RESERVED_1a = 0x1a,
+    _RESERVED_1b = 0x1b,
+    _RESERVED_1c = 0x1c,
+    _RESERVED_1d = 0x1d,
+    _RESERVED_1e = 0x1e,
+    NULL = 0x1f,
+}
+impl Gpio6ctrlFuncsel {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Gpio6ctrlFuncsel {
+        unsafe { core::mem::transmute(val & 0x1f) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Gpio6ctrlFuncsel {
+    #[inline(always)]
+    fn from(val: u8) -> Gpio6ctrlFuncsel {
+        Gpio6ctrlFuncsel::from_bits(val)
+    }
+}
+impl From<Gpio6ctrlFuncsel> for u8 {
+    #[inline(always)]
+    fn from(val: Gpio6ctrlFuncsel) -> u8 {
+        Gpio6ctrlFuncsel::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Gpio7ctrlFuncsel {
+    _RESERVED_0 = 0,
+    SPI0_TX = 0x01,
+    UART1_RTS = 0x02,
+    I2C1_SCL = 0x03,
+    PWM_B_3 = 0x04,
+    SIOB_PROC_7 = 0x05,
+    PIO0_7 = 0x06,
+    PIO1_7 = 0x07,
+    PIO2_7 = 0x08,
+    _RESERVED_9 = 0x09,
+    USB_MUXING_VBUS_DETECT = 0x0a,
+    UART1_RX = 0x0b,
+    _RESERVED_c = 0x0c,
+    _RESERVED_d = 0x0d,
+    _RESERVED_e = 0x0e,
+    _RESERVED_f = 0x0f,
+    _RESERVED_10 = 0x10,
+    _RESERVED_11 = 0x11,
+    _RESERVED_12 = 0x12,
+    _RESERVED_13 = 0x13,
+    _RESERVED_14 = 0x14,
+    _RESERVED_15 = 0x15,
+    _RESERVED_16 = 0x16,
+    _RESERVED_17 = 0x17,
+    _RESERVED_18 = 0x18,
+    _RESERVED_19 = 0x19,
+    _RESERVED_1a = 0x1a,
+    _RESERVED_1b = 0x1b,
+    _RESERVED_1c = 0x1c,
+    _RESERVED_1d = 0x1d,
+    _RESERVED_1e = 0x1e,
+    NULL = 0x1f,
+}
+impl Gpio7ctrlFuncsel {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Gpio7ctrlFuncsel {
+        unsafe { core::mem::transmute(val & 0x1f) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Gpio7ctrlFuncsel {
+    #[inline(always)]
+    fn from(val: u8) -> Gpio7ctrlFuncsel {
+        Gpio7ctrlFuncsel::from_bits(val)
+    }
+}
+impl From<Gpio7ctrlFuncsel> for u8 {
+    #[inline(always)]
+    fn from(val: Gpio7ctrlFuncsel) -> u8 {
+        Gpio7ctrlFuncsel::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Gpio8ctrlFuncsel {
+    _RESERVED_0 = 0,
+    SPI1_RX = 0x01,
+    UART1_TX = 0x02,
+    I2C0_SDA = 0x03,
+    PWM_A_4 = 0x04,
+    SIOB_PROC_8 = 0x05,
+    PIO0_8 = 0x06,
+    PIO1_8 = 0x07,
+    PIO2_8 = 0x08,
+    XIP_SS_N_1 = 0x09,
+    USB_MUXING_VBUS_EN = 0x0a,
+    _RESERVED_b = 0x0b,
+    _RESERVED_c = 0x0c,
+    _RESERVED_d = 0x0d,
+    _RESERVED_e = 0x0e,
+    _RESERVED_f = 0x0f,
+    _RESERVED_10 = 0x10,
+    _RESERVED_11 = 0x11,
+    _RESERVED_12 = 0x12,
+    _RESERVED_13 = 0x13,
+    _RESERVED_14 = 0x14,
+    _RESERVED_15 = 0x15,
+    _RESERVED_16 = 0x16,
+    _RESERVED_17 = 0x17,
+    _RESERVED_18 = 0x18,
+    _RESERVED_19 = 0x19,
+    _RESERVED_1a = 0x1a,
+    _RESERVED_1b = 0x1b,
+    _RESERVED_1c = 0x1c,
+    _RESERVED_1d = 0x1d,
+    _RESERVED_1e = 0x1e,
+    NULL = 0x1f,
+}
+impl Gpio8ctrlFuncsel {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Gpio8ctrlFuncsel {
+        unsafe { core::mem::transmute(val & 0x1f) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Gpio8ctrlFuncsel {
+    #[inline(always)]
+    fn from(val: u8) -> Gpio8ctrlFuncsel {
+        Gpio8ctrlFuncsel::from_bits(val)
+    }
+}
+impl From<Gpio8ctrlFuncsel> for u8 {
+    #[inline(always)]
+    fn from(val: Gpio8ctrlFuncsel) -> u8 {
+        Gpio8ctrlFuncsel::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Gpio9ctrlFuncsel {
+    _RESERVED_0 = 0,
+    SPI1_SS_N = 0x01,
+    UART1_RX = 0x02,
+    I2C0_SCL = 0x03,
+    PWM_B_4 = 0x04,
+    SIOB_PROC_9 = 0x05,
+    PIO0_9 = 0x06,
+    PIO1_9 = 0x07,
+    PIO2_9 = 0x08,
+    _RESERVED_9 = 0x09,
+    USB_MUXING_OVERCURR_DETECT = 0x0a,
+    _RESERVED_b = 0x0b,
+    _RESERVED_c = 0x0c,
+    _RESERVED_d = 0x0d,
+    _RESERVED_e = 0x0e,
+    _RESERVED_f = 0x0f,
+    _RESERVED_10 = 0x10,
+    _RESERVED_11 = 0x11,
+    _RESERVED_12 = 0x12,
+    _RESERVED_13 = 0x13,
+    _RESERVED_14 = 0x14,
+    _RESERVED_15 = 0x15,
+    _RESERVED_16 = 0x16,
+    _RESERVED_17 = 0x17,
+    _RESERVED_18 = 0x18,
+    _RESERVED_19 = 0x19,
+    _RESERVED_1a = 0x1a,
+    _RESERVED_1b = 0x1b,
+    _RESERVED_1c = 0x1c,
+    _RESERVED_1d = 0x1d,
+    _RESERVED_1e = 0x1e,
+    NULL = 0x1f,
+}
+impl Gpio9ctrlFuncsel {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Gpio9ctrlFuncsel {
+        unsafe { core::mem::transmute(val & 0x1f) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Gpio9ctrlFuncsel {
+    #[inline(always)]
+    fn from(val: u8) -> Gpio9ctrlFuncsel {
+        Gpio9ctrlFuncsel::from_bits(val)
+    }
+}
+impl From<Gpio9ctrlFuncsel> for u8 {
+    #[inline(always)]
+    fn from(val: Gpio9ctrlFuncsel) -> u8 {
+        Gpio9ctrlFuncsel::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Inover {
+    #[doc = "don't invert the peri input"]
+    NORMAL = 0,
+    #[doc = "invert the peri input"]
+    INVERT = 0x01,
+    #[doc = "drive peri input low"]
+    LOW = 0x02,
+    #[doc = "drive peri input high"]
+    HIGH = 0x03,
+}
+impl Inover {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Inover {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Inover {
+    #[inline(always)]
+    fn from(val: u8) -> Inover {
+        Inover::from_bits(val)
+    }
+}
+impl From<Inover> for u8 {
+    #[inline(always)]
+    fn from(val: Inover) -> u8 {
+        Inover::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Irqover {
+    #[doc = "don't invert the interrupt"]
+    NORMAL = 0,
+    #[doc = "invert the interrupt"]
+    INVERT = 0x01,
+    #[doc = "drive interrupt low"]
+    LOW = 0x02,
+    #[doc = "drive interrupt high"]
+    HIGH = 0x03,
+}
+impl Irqover {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Irqover {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Irqover {
+    #[inline(always)]
+    fn from(val: u8) -> Irqover {
+        Irqover::from_bits(val)
+    }
+}
+impl From<Irqover> for u8 {
+    #[inline(always)]
+    fn from(val: Irqover) -> u8 {
+        Irqover::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Oeover {
+    #[doc = "drive output enable from peripheral signal selected by funcsel"]
+    NORMAL = 0,
+    #[doc = "drive output enable from inverse of peripheral signal selected by funcsel"]
+    INVERT = 0x01,
+    #[doc = "disable output"]
+    DISABLE = 0x02,
+    #[doc = "enable output"]
+    ENABLE = 0x03,
+}
+impl Oeover {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Oeover {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Oeover {
+    #[inline(always)]
+    fn from(val: u8) -> Oeover {
+        Oeover::from_bits(val)
+    }
+}
+impl From<Oeover> for u8 {
+    #[inline(always)]
+    fn from(val: Oeover) -> u8 {
+        Oeover::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Outover {
+    #[doc = "drive output from peripheral signal selected by funcsel"]
+    NORMAL = 0,
+    #[doc = "drive output from inverse of peripheral signal selected by funcsel"]
+    INVERT = 0x01,
+    #[doc = "drive output low"]
+    LOW = 0x02,
+    #[doc = "drive output high"]
+    HIGH = 0x03,
+}
+impl Outover {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Outover {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Outover {
+    #[inline(always)]
+    fn from(val: u8) -> Outover {
+        Outover::from_bits(val)
+    }
+}
+impl From<Outover> for u8 {
+    #[inline(always)]
+    fn from(val: Outover) -> u8 {
+        Outover::to_bits(val)
+    }
+}
diff --git a/src/rp2350/mod.rs b/src/rp2350/mod.rs
new file mode 100644
index 00000000..5d0b2a14
--- /dev/null
+++ b/src/rp2350/mod.rs
@@ -0,0 +1,256 @@
+#![no_std]
+#![doc = "Peripheral access API (generated using chiptool v0.1.0 (d290630 2023-06-29))"]
+#[derive(Copy, Clone, Debug, PartialEq, Eq)]
+pub enum Interrupt {
+    #[doc = "0 - TIMER0_IRQ_0"]
+    TIMER0_IRQ_0 = 0,
+    #[doc = "1 - TIMER0_IRQ_1"]
+    TIMER0_IRQ_1 = 1,
+    #[doc = "2 - TIMER0_IRQ_2"]
+    TIMER0_IRQ_2 = 2,
+    #[doc = "3 - TIMER0_IRQ_3"]
+    TIMER0_IRQ_3 = 3,
+    #[doc = "4 - TIMER1_IRQ_0"]
+    TIMER1_IRQ_0 = 4,
+    #[doc = "5 - TIMER1_IRQ_1"]
+    TIMER1_IRQ_1 = 5,
+    #[doc = "6 - TIMER1_IRQ_2"]
+    TIMER1_IRQ_2 = 6,
+    #[doc = "7 - TIMER1_IRQ_3"]
+    TIMER1_IRQ_3 = 7,
+    #[doc = "8 - PWM_IRQ_WRAP_0"]
+    PWM_IRQ_WRAP_0 = 8,
+    #[doc = "9 - PWM_IRQ_WRAP_1"]
+    PWM_IRQ_WRAP_1 = 9,
+    #[doc = "10 - DMA_IRQ_0"]
+    DMA_IRQ_0 = 10,
+    #[doc = "11 - DMA_IRQ_1"]
+    DMA_IRQ_1 = 11,
+    #[doc = "12 - DMA_IRQ_2"]
+    DMA_IRQ_2 = 12,
+    #[doc = "13 - DMA_IRQ_3"]
+    DMA_IRQ_3 = 13,
+    #[doc = "14 - USBCTRL_IRQ"]
+    USBCTRL_IRQ = 14,
+    #[doc = "15 - PIO0_IRQ_0"]
+    PIO0_IRQ_0 = 15,
+    #[doc = "16 - PIO0_IRQ_1"]
+    PIO0_IRQ_1 = 16,
+    #[doc = "17 - PIO1_IRQ_0"]
+    PIO1_IRQ_0 = 17,
+    #[doc = "18 - PIO1_IRQ_1"]
+    PIO1_IRQ_1 = 18,
+    #[doc = "19 - PIO2_IRQ_0"]
+    PIO2_IRQ_0 = 19,
+    #[doc = "20 - PIO2_IRQ_1"]
+    PIO2_IRQ_1 = 20,
+    #[doc = "21 - IO_IRQ_BANK0"]
+    IO_IRQ_BANK0 = 21,
+    #[doc = "22 - IO_IRQ_BANK0_NS"]
+    IO_IRQ_BANK0_NS = 22,
+    #[doc = "23 - IO_IRQ_QSPI"]
+    IO_IRQ_QSPI = 23,
+    #[doc = "24 - IO_IRQ_QSPI_NS"]
+    IO_IRQ_QSPI_NS = 24,
+    #[doc = "25 - SIO_IRQ_FIFO"]
+    SIO_IRQ_FIFO = 25,
+    #[doc = "26 - SIO_IRQ_BELL"]
+    SIO_IRQ_BELL = 26,
+    #[doc = "27 - SIO_IRQ_FIFO_NS"]
+    SIO_IRQ_FIFO_NS = 27,
+    #[doc = "28 - SIO_IRQ_BELL_NS"]
+    SIO_IRQ_BELL_NS = 28,
+    #[doc = "29 - SIO_IRQ_MTIMECMP"]
+    SIO_IRQ_MTIMECMP = 29,
+    #[doc = "30 - CLOCKS_IRQ"]
+    CLOCKS_IRQ = 30,
+    #[doc = "31 - SPI0_IRQ"]
+    SPI0_IRQ = 31,
+    #[doc = "32 - SPI1_IRQ"]
+    SPI1_IRQ = 32,
+    #[doc = "33 - UART0_IRQ"]
+    UART0_IRQ = 33,
+    #[doc = "34 - UART1_IRQ"]
+    UART1_IRQ = 34,
+    #[doc = "35 - ADC_IRQ_FIFO"]
+    ADC_IRQ_FIFO = 35,
+    #[doc = "36 - I2C0_IRQ"]
+    I2C0_IRQ = 36,
+    #[doc = "37 - I2C1_IRQ"]
+    I2C1_IRQ = 37,
+    #[doc = "38 - OTP_IRQ"]
+    OTP_IRQ = 38,
+    #[doc = "39 - TRNG_IRQ"]
+    TRNG_IRQ = 39,
+    #[doc = "42 - PLL_SYS_IRQ"]
+    PLL_SYS_IRQ = 42,
+    #[doc = "43 - PLL_USB_IRQ"]
+    PLL_USB_IRQ = 43,
+    #[doc = "44 - POWMAN_IRQ_POW"]
+    POWMAN_IRQ_POW = 44,
+    #[doc = "45 - POWMAN_IRQ_TIMER"]
+    POWMAN_IRQ_TIMER = 45,
+    #[doc = "47 - SWI_IRQ_0"]
+    SWI_IRQ_0 = 47,
+    #[doc = "48 - SWI_IRQ_1"]
+    SWI_IRQ_1 = 48,
+    #[doc = "49 - SWI_IRQ_2"]
+    SWI_IRQ_2 = 49,
+    #[doc = "50 - SWI_IRQ_3"]
+    SWI_IRQ_3 = 50,
+    #[doc = "51 - SWI_IRQ_4"]
+    SWI_IRQ_4 = 51,
+    #[doc = "52 - SWI_IRQ_5"]
+    SWI_IRQ_5 = 52,
+}
+unsafe impl cortex_m::interrupt::InterruptNumber for Interrupt {
+    #[inline(always)]
+    fn number(self) -> u16 {
+        self as u16
+    }
+}
+#[cfg(feature = "rt")]
+mod _vectors;
+pub const SYSINFO: sysinfo::Sysinfo =
+    unsafe { sysinfo::Sysinfo::from_ptr(0x4000_0000 as usize as _) };
+#[doc = "Register block for various chip control signals"]
+pub const SYSCFG: syscfg::Syscfg = unsafe { syscfg::Syscfg::from_ptr(0x4000_8000 as usize as _) };
+pub const CLOCKS: clocks::Clocks = unsafe { clocks::Clocks::from_ptr(0x4001_0000 as usize as _) };
+pub const PSM: psm::Psm = unsafe { psm::Psm::from_ptr(0x4001_8000 as usize as _) };
+pub const RESETS: resets::Resets = unsafe { resets::Resets::from_ptr(0x4002_0000 as usize as _) };
+pub const IO_BANK0: io::Io = unsafe { io::Io::from_ptr(0x4002_8000 as usize as _) };
+pub const IO_QSPI: io::Io = unsafe { io::Io::from_ptr(0x4003_0000 as usize as _) };
+pub const PADS_BANK0: pads::Pads = unsafe { pads::Pads::from_ptr(0x4003_8000 as usize as _) };
+pub const PADS_QSPI: pads::Pads = unsafe { pads::Pads::from_ptr(0x4004_0000 as usize as _) };
+#[doc = "Controls the crystal oscillator"]
+pub const XOSC: xosc::Xosc = unsafe { xosc::Xosc::from_ptr(0x4004_8000 as usize as _) };
+pub const PLL_SYS: pll::Pll = unsafe { pll::Pll::from_ptr(0x4005_0000 as usize as _) };
+pub const PLL_USB: pll::Pll = unsafe { pll::Pll::from_ptr(0x4005_8000 as usize as _) };
+#[doc = "Hardware access control registers"]
+pub const ACCESSCTRL: accessctrl::Accessctrl =
+    unsafe { accessctrl::Accessctrl::from_ptr(0x4006_0000 as usize as _) };
+#[doc = "Register block for busfabric control signals and performance counters"]
+pub const BUSCTRL: busctrl::Busctrl =
+    unsafe { busctrl::Busctrl::from_ptr(0x4006_8000 as usize as _) };
+pub const UART0: uart::Uart = unsafe { uart::Uart::from_ptr(0x4007_0000 as usize as _) };
+pub const UART1: uart::Uart = unsafe { uart::Uart::from_ptr(0x4007_8000 as usize as _) };
+pub const SPI0: spi::Spi = unsafe { spi::Spi::from_ptr(0x4008_0000 as usize as _) };
+pub const SPI1: spi::Spi = unsafe { spi::Spi::from_ptr(0x4008_8000 as usize as _) };
+#[doc = "DW_apb_i2c address block List of configuration constants for the Synopsys I2C hardware (you may see references to these in I2C register header; these are *fixed* values, set at hardware design time): IC_ULTRA_FAST_MODE ................ 0x0 IC_UFM_TBUF_CNT_DEFAULT ........... 0x8 IC_UFM_SCL_LOW_COUNT .............. 0x0008 IC_UFM_SCL_HIGH_COUNT ............. 0x0006 IC_TX_TL .......................... 0x0 IC_TX_CMD_BLOCK ................... 0x1 IC_HAS_DMA ........................ 0x1 IC_HAS_ASYNC_FIFO ................. 0x0 IC_SMBUS_ARP ...................... 0x0 IC_FIRST_DATA_BYTE_STATUS ......... 0x1 IC_INTR_IO ........................ 0x1 IC_MASTER_MODE .................... 0x1 IC_DEFAULT_ACK_GENERAL_CALL ....... 0x1 IC_INTR_POL ....................... 0x1 IC_OPTIONAL_SAR ................... 0x0 IC_DEFAULT_TAR_SLAVE_ADDR ......... 0x055 IC_DEFAULT_SLAVE_ADDR ............. 0x055 IC_DEFAULT_HS_SPKLEN .............. 0x1 IC_FS_SCL_HIGH_COUNT .............. 0x0006 IC_HS_SCL_LOW_COUNT ............... 0x0008 IC_DEVICE_ID_VALUE ................ 0x0 IC_10BITADDR_MASTER ............... 0x0 IC_CLK_FREQ_OPTIMIZATION .......... 0x0 IC_DEFAULT_FS_SPKLEN .............. 0x7 IC_ADD_ENCODED_PARAMS ............. 0x0 IC_DEFAULT_SDA_HOLD ............... 0x000001 IC_DEFAULT_SDA_SETUP .............. 0x64 IC_AVOID_RX_FIFO_FLUSH_ON_TX_ABRT . 0x0 IC_CLOCK_PERIOD ................... 100 IC_EMPTYFIFO_HOLD_MASTER_EN ....... 1 IC_RESTART_EN ..................... 0x1 IC_TX_CMD_BLOCK_DEFAULT ........... 0x0 IC_BUS_CLEAR_FEATURE .............. 0x0 IC_CAP_LOADING .................... 100 IC_FS_SCL_LOW_COUNT ............... 0x000d APB_DATA_WIDTH .................... 32 IC_SDA_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff IC_SLV_DATA_NACK_ONLY ............. 0x1 IC_10BITADDR_SLAVE ................ 0x0 IC_CLK_TYPE ....................... 0x0 IC_SMBUS_UDID_MSB ................. 0x0 IC_SMBUS_SUSPEND_ALERT ............ 0x0 IC_HS_SCL_HIGH_COUNT .............. 0x0006 IC_SLV_RESTART_DET_EN ............. 0x1 IC_SMBUS .......................... 0x0 IC_OPTIONAL_SAR_DEFAULT ........... 0x0 IC_PERSISTANT_SLV_ADDR_DEFAULT .... 0x0 IC_USE_COUNTS ..................... 0x0 IC_RX_BUFFER_DEPTH ................ 16 IC_SCL_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff IC_RX_FULL_HLD_BUS_EN ............. 0x1 IC_SLAVE_DISABLE .................. 0x1 IC_RX_TL .......................... 0x0 IC_DEVICE_ID ...................... 0x0 IC_HC_COUNT_VALUES ................ 0x0 I2C_DYNAMIC_TAR_UPDATE ............ 0 IC_SMBUS_CLK_LOW_MEXT_DEFAULT ..... 0xffffffff IC_SMBUS_CLK_LOW_SEXT_DEFAULT ..... 0xffffffff IC_HS_MASTER_CODE ................. 0x1 IC_SMBUS_RST_IDLE_CNT_DEFAULT ..... 0xffff IC_SMBUS_UDID_LSB_DEFAULT ......... 0xffffffff IC_SS_SCL_HIGH_COUNT .............. 0x0028 IC_SS_SCL_LOW_COUNT ............... 0x002f IC_MAX_SPEED_MODE ................. 0x2 IC_STAT_FOR_CLK_STRETCH ........... 0x0 IC_STOP_DET_IF_MASTER_ACTIVE ...... 0x0 IC_DEFAULT_UFM_SPKLEN ............. 0x1 IC_TX_BUFFER_DEPTH ................ 16"]
+pub const I2C0: i2c::I2c = unsafe { i2c::I2c::from_ptr(0x4009_0000 as usize as _) };
+pub const I2C1: i2c::I2c = unsafe { i2c::I2c::from_ptr(0x4009_8000 as usize as _) };
+#[doc = "Control and data interface to SAR ADC"]
+pub const ADC: adc::Adc = unsafe { adc::Adc::from_ptr(0x400a_0000 as usize as _) };
+#[doc = "Simple PWM"]
+pub const PWM: pwm::Pwm = unsafe { pwm::Pwm::from_ptr(0x400a_8000 as usize as _) };
+#[doc = "Controls time and alarms time is a 64 bit value indicating the time since power-on timeh is the top 32 bits of time & timel is the bottom 32 bits to change time write to timelw before timehw to read time read from timelr before timehr An alarm is set by setting alarm_enable and writing to the corresponding alarm register When an alarm is pending, the corresponding alarm_running signal will be high An alarm can be cancelled before it has finished by clearing the alarm_enable When an alarm fires, the corresponding alarm_irq is set and alarm_running is cleared To clear the interrupt write a 1 to the corresponding alarm_irq The timer can be locked to prevent writing"]
+pub const TIMER0: timer::Timer = unsafe { timer::Timer::from_ptr(0x400b_0000 as usize as _) };
+pub const TIMER1: timer::Timer = unsafe { timer::Timer::from_ptr(0x400b_8000 as usize as _) };
+#[doc = "Control interface to HSTX. For FIFO write access and status, see the HSTX_FIFO register block."]
+pub const HSTX_CTRL: hstx_ctrl::HstxCtrl =
+    unsafe { hstx_ctrl::HstxCtrl::from_ptr(0x400c_0000 as usize as _) };
+#[doc = "QSPI flash execute-in-place block"]
+pub const XIP_CTRL: xip_ctrl::XipCtrl =
+    unsafe { xip_ctrl::XipCtrl::from_ptr(0x400c_8000 as usize as _) };
+#[doc = "QSPI Memory Interface. Provides a memory-mapped interface to up to two SPI/DSPI/QSPI flash or PSRAM devices. Also provides a serial interface for programming and configuration of the external device."]
+pub const QMI: qmi::Qmi = unsafe { qmi::Qmi::from_ptr(0x400d_0000 as usize as _) };
+pub const WATCHDOG: watchdog::Watchdog =
+    unsafe { watchdog::Watchdog::from_ptr(0x400d_8000 as usize as _) };
+#[doc = "Additional registers mapped adjacent to the bootram, for use by the bootrom."]
+pub const BOOTRAM: bootram::Bootram =
+    unsafe { bootram::Bootram::from_ptr(0x400e_0000 as usize as _) };
+pub const ROSC: rosc::Rosc = unsafe { rosc::Rosc::from_ptr(0x400e_8000 as usize as _) };
+#[doc = "ARM TrustZone RNG register block"]
+pub const TRNG: trng::Trng = unsafe { trng::Trng::from_ptr(0x400f_0000 as usize as _) };
+#[doc = "SHA-256 hash function implementation"]
+pub const SHA256: sha256::Sha256 = unsafe { sha256::Sha256::from_ptr(0x400f_8000 as usize as _) };
+#[doc = "Controls vreg, bor, lposc, chip resets & xosc startup, powman and provides scratch register for general use and for bootcode use"]
+pub const POWMAN: powman::Powman = unsafe { powman::Powman::from_ptr(0x4010_0000 as usize as _) };
+pub const TICKS: ticks::Ticks = unsafe { ticks::Ticks::from_ptr(0x4010_8000 as usize as _) };
+#[doc = "SNPS OTP control IF (SBPI and RPi wrapper control)"]
+pub const OTP: otp::Otp = unsafe { otp::Otp::from_ptr(0x4012_0000 as usize as _) };
+#[doc = "Predefined OTP data layout for RP2350"]
+pub const OTP_DATA: otp_data::OtpData =
+    unsafe { otp_data::OtpData::from_ptr(0x4013_0000 as usize as _) };
+#[doc = "Predefined OTP data layout for RP2350"]
+pub const OTP_DATA_RAW: otp_data_raw::OtpDataRaw =
+    unsafe { otp_data_raw::OtpDataRaw::from_ptr(0x4013_4000 as usize as _) };
+#[doc = "Glitch detector controls"]
+pub const GLITCH_DETECTOR: glitch_detector::GlitchDetector =
+    unsafe { glitch_detector::GlitchDetector::from_ptr(0x4015_8000 as usize as _) };
+#[doc = "For managing simulation testbenches"]
+pub const TBMAN: tbman::Tbman = unsafe { tbman::Tbman::from_ptr(0x4016_0000 as usize as _) };
+#[doc = "DMA with separate read and write masters"]
+pub const DMA: dma::Dma = unsafe { dma::Dma::from_ptr(0x5000_0000 as usize as _) };
+#[doc = "DPRAM layout for USB device."]
+pub const USB_DPRAM: usb_dpram::UsbDpram =
+    unsafe { usb_dpram::UsbDpram::from_ptr(0x5010_0000 as usize as _) };
+#[doc = "USB FS/LS controller device registers"]
+pub const USB: usb::Usb = unsafe { usb::Usb::from_ptr(0x5011_0000 as usize as _) };
+#[doc = "Programmable IO block"]
+pub const PIO0: pio::Pio = unsafe { pio::Pio::from_ptr(0x5020_0000 as usize as _) };
+pub const PIO1: pio::Pio = unsafe { pio::Pio::from_ptr(0x5030_0000 as usize as _) };
+pub const PIO2: pio::Pio = unsafe { pio::Pio::from_ptr(0x5040_0000 as usize as _) };
+#[doc = "Auxiliary DMA access to XIP FIFOs, via fast AHB bus access"]
+pub const XIP_AUX: xip_aux::XipAux =
+    unsafe { xip_aux::XipAux::from_ptr(0x5050_0000 as usize as _) };
+#[doc = "FIFO status and write access for HSTX"]
+pub const HSTX_FIFO: hstx_fifo::HstxFifo =
+    unsafe { hstx_fifo::HstxFifo::from_ptr(0x5060_0000 as usize as _) };
+#[doc = "Coresight block - RP specific registers"]
+pub const CORESIGHT_TRACE: coresight_trace::CoresightTrace =
+    unsafe { coresight_trace::CoresightTrace::from_ptr(0x5070_0000 as usize as _) };
+#[doc = "Single-cycle IO block Provides core-local and inter-core hardware for the two processors, with single-cycle access."]
+pub const SIO: sio::Sio = unsafe { sio::Sio::from_ptr(0xd000_0000 as usize as _) };
+pub const SIO_NS: sio::Sio = unsafe { sio::Sio::from_ptr(0xd002_0000 as usize as _) };
+#[doc = "Cortex-M33 EPPB vendor register block for RP2350"]
+pub const EPPB: eppb::Eppb = unsafe { eppb::Eppb::from_ptr(0xe008_0000 as usize as _) };
+#[doc = r" Number available in the NVIC for configuring priority"]
+#[cfg(feature = "rt")]
+pub const NVIC_PRIO_BITS: u8 = 4;
+#[cfg(feature = "rt")]
+pub use cortex_m_rt::interrupt;
+#[cfg(feature = "rt")]
+pub use Interrupt as interrupt;
+pub mod accessctrl;
+pub mod adc;
+pub mod bootram;
+pub mod busctrl;
+pub mod clocks;
+pub mod common;
+pub mod coresight_trace;
+pub mod dma;
+pub mod eppb;
+pub mod glitch_detector;
+pub mod hstx_ctrl;
+pub mod hstx_fifo;
+pub mod i2c;
+pub mod io;
+pub mod otp;
+pub mod otp_data;
+pub mod otp_data_raw;
+pub mod pads;
+pub mod pio;
+pub mod pll;
+pub mod powman;
+pub mod psm;
+pub mod pwm;
+pub mod qmi;
+pub mod resets;
+pub mod rosc;
+pub mod sha256;
+pub mod sio;
+pub mod spi;
+pub mod syscfg;
+pub mod sysinfo;
+pub mod tbman;
+pub mod ticks;
+pub mod timer;
+pub mod trng;
+pub mod uart;
+pub mod usb;
+pub mod usb_dpram;
+pub mod watchdog;
+pub mod xip_aux;
+pub mod xip_ctrl;
+pub mod xosc;
diff --git a/src/rp2350/otp.rs b/src/rp2350/otp.rs
new file mode 100644
index 00000000..d82ec108
--- /dev/null
+++ b/src/rp2350/otp.rs
@@ -0,0 +1,480 @@
+#[doc = "SNPS OTP control IF (SBPI and RPi wrapper control)"]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Otp {
+    ptr: *mut u8,
+}
+unsafe impl Send for Otp {}
+unsafe impl Sync for Otp {}
+impl Otp {
+    #[inline(always)]
+    pub const unsafe fn from_ptr(ptr: *mut ()) -> Self {
+        Self { ptr: ptr as _ }
+    }
+    #[inline(always)]
+    pub const fn as_ptr(&self) -> *mut () {
+        self.ptr as _
+    }
+    #[doc = "Software lock register for page 0. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."]
+    #[inline(always)]
+    pub const fn sw_lock0(self) -> crate::common::Reg<regs::SwLock0, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(0usize) as _) }
+    }
+    #[doc = "Software lock register for page 1. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."]
+    #[inline(always)]
+    pub const fn sw_lock1(self) -> crate::common::Reg<regs::SwLock1, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(4usize) as _) }
+    }
+    #[doc = "Software lock register for page 2. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."]
+    #[inline(always)]
+    pub const fn sw_lock2(self) -> crate::common::Reg<regs::SwLock2, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(8usize) as _) }
+    }
+    #[doc = "Software lock register for page 3. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."]
+    #[inline(always)]
+    pub const fn sw_lock3(self) -> crate::common::Reg<regs::SwLock3, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(12usize) as _) }
+    }
+    #[doc = "Software lock register for page 4. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."]
+    #[inline(always)]
+    pub const fn sw_lock4(self) -> crate::common::Reg<regs::SwLock4, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(16usize) as _) }
+    }
+    #[doc = "Software lock register for page 5. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."]
+    #[inline(always)]
+    pub const fn sw_lock5(self) -> crate::common::Reg<regs::SwLock5, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(20usize) as _) }
+    }
+    #[doc = "Software lock register for page 6. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."]
+    #[inline(always)]
+    pub const fn sw_lock6(self) -> crate::common::Reg<regs::SwLock6, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(24usize) as _) }
+    }
+    #[doc = "Software lock register for page 7. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."]
+    #[inline(always)]
+    pub const fn sw_lock7(self) -> crate::common::Reg<regs::SwLock7, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(28usize) as _) }
+    }
+    #[doc = "Software lock register for page 8. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."]
+    #[inline(always)]
+    pub const fn sw_lock8(self) -> crate::common::Reg<regs::SwLock8, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(32usize) as _) }
+    }
+    #[doc = "Software lock register for page 9. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."]
+    #[inline(always)]
+    pub const fn sw_lock9(self) -> crate::common::Reg<regs::SwLock9, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(36usize) as _) }
+    }
+    #[doc = "Software lock register for page 10. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."]
+    #[inline(always)]
+    pub const fn sw_lock10(self) -> crate::common::Reg<regs::SwLock10, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(40usize) as _) }
+    }
+    #[doc = "Software lock register for page 11. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."]
+    #[inline(always)]
+    pub const fn sw_lock11(self) -> crate::common::Reg<regs::SwLock11, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(44usize) as _) }
+    }
+    #[doc = "Software lock register for page 12. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."]
+    #[inline(always)]
+    pub const fn sw_lock12(self) -> crate::common::Reg<regs::SwLock12, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(48usize) as _) }
+    }
+    #[doc = "Software lock register for page 13. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."]
+    #[inline(always)]
+    pub const fn sw_lock13(self) -> crate::common::Reg<regs::SwLock13, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(52usize) as _) }
+    }
+    #[doc = "Software lock register for page 14. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."]
+    #[inline(always)]
+    pub const fn sw_lock14(self) -> crate::common::Reg<regs::SwLock14, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(56usize) as _) }
+    }
+    #[doc = "Software lock register for page 15. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."]
+    #[inline(always)]
+    pub const fn sw_lock15(self) -> crate::common::Reg<regs::SwLock15, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(60usize) as _) }
+    }
+    #[doc = "Software lock register for page 16. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."]
+    #[inline(always)]
+    pub const fn sw_lock16(self) -> crate::common::Reg<regs::SwLock16, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(64usize) as _) }
+    }
+    #[doc = "Software lock register for page 17. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."]
+    #[inline(always)]
+    pub const fn sw_lock17(self) -> crate::common::Reg<regs::SwLock17, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(68usize) as _) }
+    }
+    #[doc = "Software lock register for page 18. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."]
+    #[inline(always)]
+    pub const fn sw_lock18(self) -> crate::common::Reg<regs::SwLock18, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(72usize) as _) }
+    }
+    #[doc = "Software lock register for page 19. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."]
+    #[inline(always)]
+    pub const fn sw_lock19(self) -> crate::common::Reg<regs::SwLock19, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(76usize) as _) }
+    }
+    #[doc = "Software lock register for page 20. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."]
+    #[inline(always)]
+    pub const fn sw_lock20(self) -> crate::common::Reg<regs::SwLock20, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(80usize) as _) }
+    }
+    #[doc = "Software lock register for page 21. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."]
+    #[inline(always)]
+    pub const fn sw_lock21(self) -> crate::common::Reg<regs::SwLock21, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(84usize) as _) }
+    }
+    #[doc = "Software lock register for page 22. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."]
+    #[inline(always)]
+    pub const fn sw_lock22(self) -> crate::common::Reg<regs::SwLock22, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(88usize) as _) }
+    }
+    #[doc = "Software lock register for page 23. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."]
+    #[inline(always)]
+    pub const fn sw_lock23(self) -> crate::common::Reg<regs::SwLock23, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(92usize) as _) }
+    }
+    #[doc = "Software lock register for page 24. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."]
+    #[inline(always)]
+    pub const fn sw_lock24(self) -> crate::common::Reg<regs::SwLock24, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(96usize) as _) }
+    }
+    #[doc = "Software lock register for page 25. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."]
+    #[inline(always)]
+    pub const fn sw_lock25(self) -> crate::common::Reg<regs::SwLock25, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(100usize) as _) }
+    }
+    #[doc = "Software lock register for page 26. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."]
+    #[inline(always)]
+    pub const fn sw_lock26(self) -> crate::common::Reg<regs::SwLock26, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(104usize) as _) }
+    }
+    #[doc = "Software lock register for page 27. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."]
+    #[inline(always)]
+    pub const fn sw_lock27(self) -> crate::common::Reg<regs::SwLock27, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(108usize) as _) }
+    }
+    #[doc = "Software lock register for page 28. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."]
+    #[inline(always)]
+    pub const fn sw_lock28(self) -> crate::common::Reg<regs::SwLock28, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(112usize) as _) }
+    }
+    #[doc = "Software lock register for page 29. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."]
+    #[inline(always)]
+    pub const fn sw_lock29(self) -> crate::common::Reg<regs::SwLock29, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(116usize) as _) }
+    }
+    #[doc = "Software lock register for page 30. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."]
+    #[inline(always)]
+    pub const fn sw_lock30(self) -> crate::common::Reg<regs::SwLock30, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(120usize) as _) }
+    }
+    #[doc = "Software lock register for page 31. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."]
+    #[inline(always)]
+    pub const fn sw_lock31(self) -> crate::common::Reg<regs::SwLock31, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(124usize) as _) }
+    }
+    #[doc = "Software lock register for page 32. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."]
+    #[inline(always)]
+    pub const fn sw_lock32(self) -> crate::common::Reg<regs::SwLock32, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(128usize) as _) }
+    }
+    #[doc = "Software lock register for page 33. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."]
+    #[inline(always)]
+    pub const fn sw_lock33(self) -> crate::common::Reg<regs::SwLock33, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(132usize) as _) }
+    }
+    #[doc = "Software lock register for page 34. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."]
+    #[inline(always)]
+    pub const fn sw_lock34(self) -> crate::common::Reg<regs::SwLock34, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(136usize) as _) }
+    }
+    #[doc = "Software lock register for page 35. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."]
+    #[inline(always)]
+    pub const fn sw_lock35(self) -> crate::common::Reg<regs::SwLock35, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(140usize) as _) }
+    }
+    #[doc = "Software lock register for page 36. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."]
+    #[inline(always)]
+    pub const fn sw_lock36(self) -> crate::common::Reg<regs::SwLock36, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(144usize) as _) }
+    }
+    #[doc = "Software lock register for page 37. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."]
+    #[inline(always)]
+    pub const fn sw_lock37(self) -> crate::common::Reg<regs::SwLock37, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(148usize) as _) }
+    }
+    #[doc = "Software lock register for page 38. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."]
+    #[inline(always)]
+    pub const fn sw_lock38(self) -> crate::common::Reg<regs::SwLock38, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(152usize) as _) }
+    }
+    #[doc = "Software lock register for page 39. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."]
+    #[inline(always)]
+    pub const fn sw_lock39(self) -> crate::common::Reg<regs::SwLock39, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(156usize) as _) }
+    }
+    #[doc = "Software lock register for page 40. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."]
+    #[inline(always)]
+    pub const fn sw_lock40(self) -> crate::common::Reg<regs::SwLock40, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(160usize) as _) }
+    }
+    #[doc = "Software lock register for page 41. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."]
+    #[inline(always)]
+    pub const fn sw_lock41(self) -> crate::common::Reg<regs::SwLock41, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(164usize) as _) }
+    }
+    #[doc = "Software lock register for page 42. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."]
+    #[inline(always)]
+    pub const fn sw_lock42(self) -> crate::common::Reg<regs::SwLock42, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(168usize) as _) }
+    }
+    #[doc = "Software lock register for page 43. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."]
+    #[inline(always)]
+    pub const fn sw_lock43(self) -> crate::common::Reg<regs::SwLock43, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(172usize) as _) }
+    }
+    #[doc = "Software lock register for page 44. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."]
+    #[inline(always)]
+    pub const fn sw_lock44(self) -> crate::common::Reg<regs::SwLock44, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(176usize) as _) }
+    }
+    #[doc = "Software lock register for page 45. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."]
+    #[inline(always)]
+    pub const fn sw_lock45(self) -> crate::common::Reg<regs::SwLock45, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(180usize) as _) }
+    }
+    #[doc = "Software lock register for page 46. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."]
+    #[inline(always)]
+    pub const fn sw_lock46(self) -> crate::common::Reg<regs::SwLock46, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(184usize) as _) }
+    }
+    #[doc = "Software lock register for page 47. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."]
+    #[inline(always)]
+    pub const fn sw_lock47(self) -> crate::common::Reg<regs::SwLock47, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(188usize) as _) }
+    }
+    #[doc = "Software lock register for page 48. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."]
+    #[inline(always)]
+    pub const fn sw_lock48(self) -> crate::common::Reg<regs::SwLock48, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(192usize) as _) }
+    }
+    #[doc = "Software lock register for page 49. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."]
+    #[inline(always)]
+    pub const fn sw_lock49(self) -> crate::common::Reg<regs::SwLock49, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(196usize) as _) }
+    }
+    #[doc = "Software lock register for page 50. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."]
+    #[inline(always)]
+    pub const fn sw_lock50(self) -> crate::common::Reg<regs::SwLock50, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(200usize) as _) }
+    }
+    #[doc = "Software lock register for page 51. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."]
+    #[inline(always)]
+    pub const fn sw_lock51(self) -> crate::common::Reg<regs::SwLock51, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(204usize) as _) }
+    }
+    #[doc = "Software lock register for page 52. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."]
+    #[inline(always)]
+    pub const fn sw_lock52(self) -> crate::common::Reg<regs::SwLock52, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(208usize) as _) }
+    }
+    #[doc = "Software lock register for page 53. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."]
+    #[inline(always)]
+    pub const fn sw_lock53(self) -> crate::common::Reg<regs::SwLock53, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(212usize) as _) }
+    }
+    #[doc = "Software lock register for page 54. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."]
+    #[inline(always)]
+    pub const fn sw_lock54(self) -> crate::common::Reg<regs::SwLock54, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(216usize) as _) }
+    }
+    #[doc = "Software lock register for page 55. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."]
+    #[inline(always)]
+    pub const fn sw_lock55(self) -> crate::common::Reg<regs::SwLock55, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(220usize) as _) }
+    }
+    #[doc = "Software lock register for page 56. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."]
+    #[inline(always)]
+    pub const fn sw_lock56(self) -> crate::common::Reg<regs::SwLock56, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(224usize) as _) }
+    }
+    #[doc = "Software lock register for page 57. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."]
+    #[inline(always)]
+    pub const fn sw_lock57(self) -> crate::common::Reg<regs::SwLock57, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(228usize) as _) }
+    }
+    #[doc = "Software lock register for page 58. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."]
+    #[inline(always)]
+    pub const fn sw_lock58(self) -> crate::common::Reg<regs::SwLock58, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(232usize) as _) }
+    }
+    #[doc = "Software lock register for page 59. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."]
+    #[inline(always)]
+    pub const fn sw_lock59(self) -> crate::common::Reg<regs::SwLock59, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(236usize) as _) }
+    }
+    #[doc = "Software lock register for page 60. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."]
+    #[inline(always)]
+    pub const fn sw_lock60(self) -> crate::common::Reg<regs::SwLock60, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(240usize) as _) }
+    }
+    #[doc = "Software lock register for page 61. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."]
+    #[inline(always)]
+    pub const fn sw_lock61(self) -> crate::common::Reg<regs::SwLock61, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(244usize) as _) }
+    }
+    #[doc = "Software lock register for page 62. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."]
+    #[inline(always)]
+    pub const fn sw_lock62(self) -> crate::common::Reg<regs::SwLock62, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(248usize) as _) }
+    }
+    #[doc = "Software lock register for page 63. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."]
+    #[inline(always)]
+    pub const fn sw_lock63(self) -> crate::common::Reg<regs::SwLock63, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(252usize) as _) }
+    }
+    #[doc = "Dispatch instructions to the SBPI interface, used for programming the OTP fuses."]
+    #[inline(always)]
+    pub const fn sbpi_instr(self) -> crate::common::Reg<regs::SbpiInstr, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(256usize) as _) }
+    }
+    #[doc = "SBPI write payload bytes 3..0"]
+    #[inline(always)]
+    pub const fn sbpi_wdata_0(self) -> crate::common::Reg<u32, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(260usize) as _) }
+    }
+    #[doc = "SBPI write payload bytes 7..4"]
+    #[inline(always)]
+    pub const fn sbpi_wdata_1(self) -> crate::common::Reg<u32, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(264usize) as _) }
+    }
+    #[doc = "SBPI write payload bytes 11..8"]
+    #[inline(always)]
+    pub const fn sbpi_wdata_2(self) -> crate::common::Reg<u32, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(268usize) as _) }
+    }
+    #[doc = "SBPI write payload bytes 15..12"]
+    #[inline(always)]
+    pub const fn sbpi_wdata_3(self) -> crate::common::Reg<u32, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(272usize) as _) }
+    }
+    #[doc = "Read payload bytes 3..0. Once read, the data in the register will automatically clear to 0."]
+    #[inline(always)]
+    pub const fn sbpi_rdata_0(self) -> crate::common::Reg<u32, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(276usize) as _) }
+    }
+    #[doc = "Read payload bytes 7..4. Once read, the data in the register will automatically clear to 0."]
+    #[inline(always)]
+    pub const fn sbpi_rdata_1(self) -> crate::common::Reg<u32, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(280usize) as _) }
+    }
+    #[doc = "Read payload bytes 11..8. Once read, the data in the register will automatically clear to 0."]
+    #[inline(always)]
+    pub const fn sbpi_rdata_2(self) -> crate::common::Reg<u32, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(284usize) as _) }
+    }
+    #[doc = "Read payload bytes 15..12. Once read, the data in the register will automatically clear to 0."]
+    #[inline(always)]
+    pub const fn sbpi_rdata_3(self) -> crate::common::Reg<u32, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(288usize) as _) }
+    }
+    #[inline(always)]
+    pub const fn sbpi_status(self) -> crate::common::Reg<regs::SbpiStatus, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(292usize) as _) }
+    }
+    #[doc = "Controls for APB data read interface (USER interface)"]
+    #[inline(always)]
+    pub const fn usr(self) -> crate::common::Reg<regs::Usr, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(296usize) as _) }
+    }
+    #[doc = "Debug for OTP power-on state machine"]
+    #[inline(always)]
+    pub const fn dbg(self) -> crate::common::Reg<regs::Dbg, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(300usize) as _) }
+    }
+    #[doc = "During BIST, count address locations that have at least one leaky bit"]
+    #[inline(always)]
+    pub const fn bist(self) -> crate::common::Reg<regs::Bist, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(308usize) as _) }
+    }
+    #[doc = "Word 0 (bits 31..0) of the key. Write only, read returns 0x0"]
+    #[inline(always)]
+    pub const fn crt_key_w0(self) -> crate::common::Reg<u32, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(312usize) as _) }
+    }
+    #[doc = "Word 1 (bits 63..32) of the key. Write only, read returns 0x0"]
+    #[inline(always)]
+    pub const fn crt_key_w1(self) -> crate::common::Reg<u32, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(316usize) as _) }
+    }
+    #[doc = "Word 2 (bits 95..64) of the key. Write only, read returns 0x0"]
+    #[inline(always)]
+    pub const fn crt_key_w2(self) -> crate::common::Reg<u32, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(320usize) as _) }
+    }
+    #[doc = "Word 3 (bits 127..96) of the key. Write only, read returns 0x0"]
+    #[inline(always)]
+    pub const fn crt_key_w3(self) -> crate::common::Reg<u32, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(324usize) as _) }
+    }
+    #[doc = "Quickly check values of critical flags read during boot up"]
+    #[inline(always)]
+    pub const fn critical(self) -> crate::common::Reg<regs::Critical, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(328usize) as _) }
+    }
+    #[doc = "Which keys were valid (enrolled) at boot time"]
+    #[inline(always)]
+    pub const fn key_valid(self) -> crate::common::Reg<regs::KeyValid, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(332usize) as _) }
+    }
+    #[doc = "Enable a debug feature that has been disabled. Debug features are disabled if one of the relevant critical boot flags is set in OTP (DEBUG_DISABLE or SECURE_DEBUG_DISABLE), OR if a debug key is marked valid in OTP, and the matching key value has not been supplied over SWD. Specifically: - The DEBUG_DISABLE flag disables all debug features. This can be fully overridden by setting all bits of this register. - The SECURE_DEBUG_DISABLE flag disables secure processor debug. This can be fully overridden by setting the PROC0_SECURE and PROC1_SECURE bits of this register. - If a single debug key has been registered, and no matching key value has been supplied over SWD, then all debug features are disabled. This can be fully overridden by setting all bits of this register. - If both debug keys have been registered, and the Non-secure key's value (key 6) has been supplied over SWD, secure processor debug is disabled. This can be fully overridden by setting the PROC0_SECURE and PROC1_SECURE bits of this register. - If both debug keys have been registered, and the Secure key's value (key 5) has been supplied over SWD, then no debug features are disabled by the key mechanism. However, note that in this case debug features may still be disabled by the critical boot flags."]
+    #[inline(always)]
+    pub const fn debugen(self) -> crate::common::Reg<regs::Debugen, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(336usize) as _) }
+    }
+    #[doc = "Write 1s to lock corresponding bits in DEBUGEN. This register is reset by the processor cold reset."]
+    #[inline(always)]
+    pub const fn debugen_lock(self) -> crate::common::Reg<regs::DebugenLock, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(340usize) as _) }
+    }
+    #[doc = "Architecture select (Arm/RISC-V). The default and allowable values of this register are constrained by the critical boot flags. This register is reset by the earliest reset in the switched core power domain (before a processor cold reset). Cores sample their architecture select signal on a warm reset. The source of the warm reset could be the system power-up state machine, the watchdog timer, Arm SYSRESETREQ or from RISC-V hartresetreq. Note that when an Arm core is deselected, its cold reset domain is also held in reset, since in particular the SYSRESETREQ bit becomes inaccessible once the core is deselected. Note also the RISC-V cores do not have a cold reset domain, since their corresponding controls are located in the Debug Module."]
+    #[inline(always)]
+    pub const fn archsel(self) -> crate::common::Reg<regs::Archsel, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(344usize) as _) }
+    }
+    #[doc = "Get the current architecture select state of each core. Cores sample the current value of the ARCHSEL register when their warm reset is released, at which point the corresponding bit in this register will also update."]
+    #[inline(always)]
+    pub const fn archsel_status(
+        self,
+    ) -> crate::common::Reg<regs::ArchselStatus, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(348usize) as _) }
+    }
+    #[doc = "Tell the bootrom to ignore scratch register boot vectors (both power manager and watchdog) on the next power up. If an early boot stage has soft-locked some OTP pages in order to protect their contents from later stages, there is a risk that Secure code running at a later stage can unlock the pages by performing a watchdog reset that resets the OTP. This register can be used to ensure that the bootloader runs as normal on the next power up, preventing Secure code at a later stage from accessing OTP in its unlocked state. Should be used in conjunction with the power manager BOOTDIS register."]
+    #[inline(always)]
+    pub const fn bootdis(self) -> crate::common::Reg<regs::Bootdis, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(352usize) as _) }
+    }
+    #[doc = "Raw Interrupts"]
+    #[inline(always)]
+    pub const fn intr(self) -> crate::common::Reg<regs::Intr, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(356usize) as _) }
+    }
+    #[doc = "Interrupt Enable"]
+    #[inline(always)]
+    pub const fn inte(self) -> crate::common::Reg<regs::Inte, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(360usize) as _) }
+    }
+    #[doc = "Interrupt Force"]
+    #[inline(always)]
+    pub const fn intf(self) -> crate::common::Reg<regs::Intf, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(364usize) as _) }
+    }
+    #[doc = "Interrupt status after masking & forcing"]
+    #[inline(always)]
+    pub const fn ints(self) -> crate::common::Reg<regs::Ints, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(368usize) as _) }
+    }
+}
+pub mod regs;
+pub mod vals;
diff --git a/src/rp2350/otp/regs.rs b/src/rp2350/otp/regs.rs
new file mode 100644
index 00000000..321411cb
--- /dev/null
+++ b/src/rp2350/otp/regs.rs
@@ -0,0 +1,3077 @@
+#[doc = "Architecture select (Arm/RISC-V). The default and allowable values of this register are constrained by the critical boot flags. This register is reset by the earliest reset in the switched core power domain (before a processor cold reset). Cores sample their architecture select signal on a warm reset. The source of the warm reset could be the system power-up state machine, the watchdog timer, Arm SYSRESETREQ or from RISC-V hartresetreq. Note that when an Arm core is deselected, its cold reset domain is also held in reset, since in particular the SYSRESETREQ bit becomes inaccessible once the core is deselected. Note also the RISC-V cores do not have a cold reset domain, since their corresponding controls are located in the Debug Module."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Archsel(pub u32);
+impl Archsel {
+    #[doc = "Select architecture for core 0."]
+    #[inline(always)]
+    pub const fn core0(&self) -> super::vals::ArchselCore0 {
+        let val = (self.0 >> 0usize) & 0x01;
+        super::vals::ArchselCore0::from_bits(val as u8)
+    }
+    #[doc = "Select architecture for core 0."]
+    #[inline(always)]
+    pub fn set_core0(&mut self, val: super::vals::ArchselCore0) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val.to_bits() as u32) & 0x01) << 0usize);
+    }
+    #[doc = "Select architecture for core 1."]
+    #[inline(always)]
+    pub const fn core1(&self) -> super::vals::ArchselCore1 {
+        let val = (self.0 >> 1usize) & 0x01;
+        super::vals::ArchselCore1::from_bits(val as u8)
+    }
+    #[doc = "Select architecture for core 1."]
+    #[inline(always)]
+    pub fn set_core1(&mut self, val: super::vals::ArchselCore1) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val.to_bits() as u32) & 0x01) << 1usize);
+    }
+}
+impl Default for Archsel {
+    #[inline(always)]
+    fn default() -> Archsel {
+        Archsel(0)
+    }
+}
+#[doc = "Get the current architecture select state of each core. Cores sample the current value of the ARCHSEL register when their warm reset is released, at which point the corresponding bit in this register will also update."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct ArchselStatus(pub u32);
+impl ArchselStatus {
+    #[doc = "Current architecture for core 0. Updated on processor warm reset."]
+    #[inline(always)]
+    pub const fn core0(&self) -> super::vals::ArchselStatusCore0 {
+        let val = (self.0 >> 0usize) & 0x01;
+        super::vals::ArchselStatusCore0::from_bits(val as u8)
+    }
+    #[doc = "Current architecture for core 0. Updated on processor warm reset."]
+    #[inline(always)]
+    pub fn set_core0(&mut self, val: super::vals::ArchselStatusCore0) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val.to_bits() as u32) & 0x01) << 0usize);
+    }
+    #[doc = "Current architecture for core 0. Updated on processor warm reset."]
+    #[inline(always)]
+    pub const fn core1(&self) -> super::vals::ArchselStatusCore1 {
+        let val = (self.0 >> 1usize) & 0x01;
+        super::vals::ArchselStatusCore1::from_bits(val as u8)
+    }
+    #[doc = "Current architecture for core 0. Updated on processor warm reset."]
+    #[inline(always)]
+    pub fn set_core1(&mut self, val: super::vals::ArchselStatusCore1) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val.to_bits() as u32) & 0x01) << 1usize);
+    }
+}
+impl Default for ArchselStatus {
+    #[inline(always)]
+    fn default() -> ArchselStatus {
+        ArchselStatus(0)
+    }
+}
+#[doc = "During BIST, count address locations that have at least one leaky bit"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Bist(pub u32);
+impl Bist {
+    #[doc = "Number of locations that have at least one leaky bit. Note: This count is true only if the BIST was initiated without the fix option."]
+    #[inline(always)]
+    pub const fn cnt(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0x1fff;
+        val as u16
+    }
+    #[doc = "Number of locations that have at least one leaky bit. Note: This count is true only if the BIST was initiated without the fix option."]
+    #[inline(always)]
+    pub fn set_cnt(&mut self, val: u16) {
+        self.0 = (self.0 & !(0x1fff << 0usize)) | (((val as u32) & 0x1fff) << 0usize);
+    }
+    #[doc = "The cnt_fail flag will be set if the number of leaky locations exceeds this number"]
+    #[inline(always)]
+    pub const fn cnt_max(&self) -> u16 {
+        let val = (self.0 >> 16usize) & 0x0fff;
+        val as u16
+    }
+    #[doc = "The cnt_fail flag will be set if the number of leaky locations exceeds this number"]
+    #[inline(always)]
+    pub fn set_cnt_max(&mut self, val: u16) {
+        self.0 = (self.0 & !(0x0fff << 16usize)) | (((val as u32) & 0x0fff) << 16usize);
+    }
+    #[doc = "Enable the counter before the BIST function is initiated"]
+    #[inline(always)]
+    pub const fn cnt_ena(&self) -> bool {
+        let val = (self.0 >> 28usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Enable the counter before the BIST function is initiated"]
+    #[inline(always)]
+    pub fn set_cnt_ena(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 28usize)) | (((val as u32) & 0x01) << 28usize);
+    }
+    #[doc = "Clear counter before use"]
+    #[inline(always)]
+    pub const fn cnt_clr(&self) -> bool {
+        let val = (self.0 >> 29usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Clear counter before use"]
+    #[inline(always)]
+    pub fn set_cnt_clr(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 29usize)) | (((val as u32) & 0x01) << 29usize);
+    }
+    #[doc = "Flag if the count of address locations with at least one leaky bit exceeds cnt_max"]
+    #[inline(always)]
+    pub const fn cnt_fail(&self) -> bool {
+        let val = (self.0 >> 30usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Flag if the count of address locations with at least one leaky bit exceeds cnt_max"]
+    #[inline(always)]
+    pub fn set_cnt_fail(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 30usize)) | (((val as u32) & 0x01) << 30usize);
+    }
+}
+impl Default for Bist {
+    #[inline(always)]
+    fn default() -> Bist {
+        Bist(0)
+    }
+}
+#[doc = "Tell the bootrom to ignore scratch register boot vectors (both power manager and watchdog) on the next power up. If an early boot stage has soft-locked some OTP pages in order to protect their contents from later stages, there is a risk that Secure code running at a later stage can unlock the pages by performing a watchdog reset that resets the OTP. This register can be used to ensure that the bootloader runs as normal on the next power up, preventing Secure code at a later stage from accessing OTP in its unlocked state. Should be used in conjunction with the power manager BOOTDIS register."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Bootdis(pub u32);
+impl Bootdis {
+    #[doc = "When the core is powered down, the current value of BOOTDIS_NEXT is OR'd into BOOTDIS_NOW, and BOOTDIS_NEXT is cleared. The bootrom checks this flag before reading the boot scratch registers. If it is set, the bootrom clears it, and ignores the BOOT registers. This prevents Secure software from diverting the boot path before a bootloader has had the chance to soft lock OTP pages containing sensitive data."]
+    #[inline(always)]
+    pub const fn now(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "When the core is powered down, the current value of BOOTDIS_NEXT is OR'd into BOOTDIS_NOW, and BOOTDIS_NEXT is cleared. The bootrom checks this flag before reading the boot scratch registers. If it is set, the bootrom clears it, and ignores the BOOT registers. This prevents Secure software from diverting the boot path before a bootloader has had the chance to soft lock OTP pages containing sensitive data."]
+    #[inline(always)]
+    pub fn set_now(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[doc = "This flag always ORs writes into its current contents. It can be set but not cleared by software. The BOOTDIS_NEXT bit is OR'd into the BOOTDIS_NOW bit when the core is powered down. Simultaneously, the BOOTDIS_NEXT bit is cleared. Setting this bit means that the boot scratch registers will be ignored following the next core power down. This flag should be set by an early boot stage that has soft-locked OTP pages, to prevent later stages from unlocking it via watchdog reset."]
+    #[inline(always)]
+    pub const fn next(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[doc = "This flag always ORs writes into its current contents. It can be set but not cleared by software. The BOOTDIS_NEXT bit is OR'd into the BOOTDIS_NOW bit when the core is powered down. Simultaneously, the BOOTDIS_NEXT bit is cleared. Setting this bit means that the boot scratch registers will be ignored following the next core power down. This flag should be set by an early boot stage that has soft-locked OTP pages, to prevent later stages from unlocking it via watchdog reset."]
+    #[inline(always)]
+    pub fn set_next(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+}
+impl Default for Bootdis {
+    #[inline(always)]
+    fn default() -> Bootdis {
+        Bootdis(0)
+    }
+}
+#[doc = "Quickly check values of critical flags read during boot up"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Critical(pub u32);
+impl Critical {
+    #[inline(always)]
+    pub const fn secure_boot_enable(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_secure_boot_enable(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[inline(always)]
+    pub const fn secure_debug_disable(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_secure_debug_disable(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+    #[inline(always)]
+    pub const fn debug_disable(&self) -> bool {
+        let val = (self.0 >> 2usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_debug_disable(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+    }
+    #[inline(always)]
+    pub const fn default_archsel(&self) -> bool {
+        let val = (self.0 >> 3usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_default_archsel(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
+    }
+    #[inline(always)]
+    pub const fn glitch_detector_enable(&self) -> bool {
+        let val = (self.0 >> 4usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_glitch_detector_enable(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
+    }
+    #[inline(always)]
+    pub const fn glitch_detector_sens(&self) -> u8 {
+        let val = (self.0 >> 5usize) & 0x03;
+        val as u8
+    }
+    #[inline(always)]
+    pub fn set_glitch_detector_sens(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x03 << 5usize)) | (((val as u32) & 0x03) << 5usize);
+    }
+    #[inline(always)]
+    pub const fn arm_disable(&self) -> bool {
+        let val = (self.0 >> 16usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_arm_disable(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
+    }
+    #[inline(always)]
+    pub const fn riscv_disable(&self) -> bool {
+        let val = (self.0 >> 17usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_riscv_disable(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
+    }
+}
+impl Default for Critical {
+    #[inline(always)]
+    fn default() -> Critical {
+        Critical(0)
+    }
+}
+#[doc = "Debug for OTP power-on state machine"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Dbg(pub u32);
+impl Dbg {
+    #[doc = "PSM done status flag"]
+    #[inline(always)]
+    pub const fn psm_done(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "PSM done status flag"]
+    #[inline(always)]
+    pub fn set_psm_done(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[doc = "PSM boot done status flag"]
+    #[inline(always)]
+    pub const fn boot_done(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[doc = "PSM boot done status flag"]
+    #[inline(always)]
+    pub fn set_boot_done(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+    #[doc = "Ring oscillator was seen up and running"]
+    #[inline(always)]
+    pub const fn rosc_up_seen(&self) -> bool {
+        let val = (self.0 >> 2usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Ring oscillator was seen up and running"]
+    #[inline(always)]
+    pub fn set_rosc_up_seen(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+    }
+    #[doc = "Ring oscillator is up and running"]
+    #[inline(always)]
+    pub const fn rosc_up(&self) -> bool {
+        let val = (self.0 >> 3usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Ring oscillator is up and running"]
+    #[inline(always)]
+    pub fn set_rosc_up(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
+    }
+    #[doc = "Monitor the PSM FSM's state"]
+    #[inline(always)]
+    pub const fn psm_state(&self) -> u8 {
+        let val = (self.0 >> 4usize) & 0x0f;
+        val as u8
+    }
+    #[doc = "Monitor the PSM FSM's state"]
+    #[inline(always)]
+    pub fn set_psm_state(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x0f << 4usize)) | (((val as u32) & 0x0f) << 4usize);
+    }
+    #[doc = "The chip is in RMA mode"]
+    #[inline(always)]
+    pub const fn customer_rma_flag(&self) -> bool {
+        let val = (self.0 >> 12usize) & 0x01;
+        val != 0
+    }
+    #[doc = "The chip is in RMA mode"]
+    #[inline(always)]
+    pub fn set_customer_rma_flag(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
+    }
+}
+impl Default for Dbg {
+    #[inline(always)]
+    fn default() -> Dbg {
+        Dbg(0)
+    }
+}
+#[doc = "Enable a debug feature that has been disabled. Debug features are disabled if one of the relevant critical boot flags is set in OTP (DEBUG_DISABLE or SECURE_DEBUG_DISABLE), OR if a debug key is marked valid in OTP, and the matching key value has not been supplied over SWD. Specifically: - The DEBUG_DISABLE flag disables all debug features. This can be fully overridden by setting all bits of this register. - The SECURE_DEBUG_DISABLE flag disables secure processor debug. This can be fully overridden by setting the PROC0_SECURE and PROC1_SECURE bits of this register. - If a single debug key has been registered, and no matching key value has been supplied over SWD, then all debug features are disabled. This can be fully overridden by setting all bits of this register. - If both debug keys have been registered, and the Non-secure key's value (key 6) has been supplied over SWD, secure processor debug is disabled. This can be fully overridden by setting the PROC0_SECURE and PROC1_SECURE bits of this register. - If both debug keys have been registered, and the Secure key's value (key 5) has been supplied over SWD, then no debug features are disabled by the key mechanism. However, note that in this case debug features may still be disabled by the critical boot flags."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Debugen(pub u32);
+impl Debugen {
+    #[doc = "Enable core 0's Mem-AP if it is currently disabled. The Mem-AP is disabled by default if either of the debug disable critical flags is set, or if at least one debug key has been enrolled and the least secure of these enrolled key values has not been provided over SWD. Note also that core Mem-APs are unconditionally disabled when a core is switched to RISC-V mode (by setting the ARCHSEL bit and performing a warm reset of the core)."]
+    #[inline(always)]
+    pub const fn proc0(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Enable core 0's Mem-AP if it is currently disabled. The Mem-AP is disabled by default if either of the debug disable critical flags is set, or if at least one debug key has been enrolled and the least secure of these enrolled key values has not been provided over SWD. Note also that core Mem-APs are unconditionally disabled when a core is switched to RISC-V mode (by setting the ARCHSEL bit and performing a warm reset of the core)."]
+    #[inline(always)]
+    pub fn set_proc0(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[doc = "Permit core 0's Mem-AP to generate Secure accesses, assuming it is enabled at all. Also enable secure debug of core 0 (SPIDEN and SPNIDEN). Secure debug of core 0 is disabled by default if the secure debug disable critical flag is set, or if at least one debug key has been enrolled and the most secure of these enrolled key values not yet provided over SWD. Note also that core Mem-APs are unconditionally disabled when a core is switched to RISC-V mode (by setting the ARCHSEL bit and performing a warm reset of the core)."]
+    #[inline(always)]
+    pub const fn proc0_secure(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Permit core 0's Mem-AP to generate Secure accesses, assuming it is enabled at all. Also enable secure debug of core 0 (SPIDEN and SPNIDEN). Secure debug of core 0 is disabled by default if the secure debug disable critical flag is set, or if at least one debug key has been enrolled and the most secure of these enrolled key values not yet provided over SWD. Note also that core Mem-APs are unconditionally disabled when a core is switched to RISC-V mode (by setting the ARCHSEL bit and performing a warm reset of the core)."]
+    #[inline(always)]
+    pub fn set_proc0_secure(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+    #[doc = "Enable core 1's Mem-AP if it is currently disabled. The Mem-AP is disabled by default if either of the debug disable critical flags is set, or if at least one debug key has been enrolled and the least secure of these enrolled key values has not been provided over SWD."]
+    #[inline(always)]
+    pub const fn proc1(&self) -> bool {
+        let val = (self.0 >> 2usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Enable core 1's Mem-AP if it is currently disabled. The Mem-AP is disabled by default if either of the debug disable critical flags is set, or if at least one debug key has been enrolled and the least secure of these enrolled key values has not been provided over SWD."]
+    #[inline(always)]
+    pub fn set_proc1(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+    }
+    #[doc = "Permit core 1's Mem-AP to generate Secure accesses, assuming it is enabled at all. Also enable secure debug of core 1 (SPIDEN and SPNIDEN). Secure debug of core 1 is disabled by default if the secure debug disable critical flag is set, or if at least one debug key has been enrolled and the most secure of these enrolled key values not yet provided over SWD."]
+    #[inline(always)]
+    pub const fn proc1_secure(&self) -> bool {
+        let val = (self.0 >> 3usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Permit core 1's Mem-AP to generate Secure accesses, assuming it is enabled at all. Also enable secure debug of core 1 (SPIDEN and SPNIDEN). Secure debug of core 1 is disabled by default if the secure debug disable critical flag is set, or if at least one debug key has been enrolled and the most secure of these enrolled key values not yet provided over SWD."]
+    #[inline(always)]
+    pub fn set_proc1_secure(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
+    }
+    #[doc = "Enable other debug components. Specifically, the CTI, and the APB-AP used to access the RISC-V Debug Module. These components are disabled by default if either of the debug disable critical flags is set, or if at least one debug key has been enrolled and the least secure of these enrolled key values has not been provided over SWD."]
+    #[inline(always)]
+    pub const fn misc(&self) -> bool {
+        let val = (self.0 >> 8usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Enable other debug components. Specifically, the CTI, and the APB-AP used to access the RISC-V Debug Module. These components are disabled by default if either of the debug disable critical flags is set, or if at least one debug key has been enrolled and the least secure of these enrolled key values has not been provided over SWD."]
+    #[inline(always)]
+    pub fn set_misc(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
+    }
+}
+impl Default for Debugen {
+    #[inline(always)]
+    fn default() -> Debugen {
+        Debugen(0)
+    }
+}
+#[doc = "Write 1s to lock corresponding bits in DEBUGEN. This register is reset by the processor cold reset."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct DebugenLock(pub u32);
+impl DebugenLock {
+    #[doc = "Write 1 to lock the PROC0 bit of DEBUGEN. Can't be cleared once set."]
+    #[inline(always)]
+    pub const fn proc0(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Write 1 to lock the PROC0 bit of DEBUGEN. Can't be cleared once set."]
+    #[inline(always)]
+    pub fn set_proc0(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[doc = "Write 1 to lock the PROC0_SECURE bit of DEBUGEN. Can't be cleared once set."]
+    #[inline(always)]
+    pub const fn proc0_secure(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Write 1 to lock the PROC0_SECURE bit of DEBUGEN. Can't be cleared once set."]
+    #[inline(always)]
+    pub fn set_proc0_secure(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+    #[doc = "Write 1 to lock the PROC1 bit of DEBUGEN. Can't be cleared once set."]
+    #[inline(always)]
+    pub const fn proc1(&self) -> bool {
+        let val = (self.0 >> 2usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Write 1 to lock the PROC1 bit of DEBUGEN. Can't be cleared once set."]
+    #[inline(always)]
+    pub fn set_proc1(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+    }
+    #[doc = "Write 1 to lock the PROC1_SECURE bit of DEBUGEN. Can't be cleared once set."]
+    #[inline(always)]
+    pub const fn proc1_secure(&self) -> bool {
+        let val = (self.0 >> 3usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Write 1 to lock the PROC1_SECURE bit of DEBUGEN. Can't be cleared once set."]
+    #[inline(always)]
+    pub fn set_proc1_secure(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
+    }
+    #[doc = "Write 1 to lock the MISC bit of DEBUGEN. Can't be cleared once set."]
+    #[inline(always)]
+    pub const fn misc(&self) -> bool {
+        let val = (self.0 >> 8usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Write 1 to lock the MISC bit of DEBUGEN. Can't be cleared once set."]
+    #[inline(always)]
+    pub fn set_misc(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
+    }
+}
+impl Default for DebugenLock {
+    #[inline(always)]
+    fn default() -> DebugenLock {
+        DebugenLock(0)
+    }
+}
+#[doc = "Interrupt Enable"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Inte(pub u32);
+impl Inte {
+    #[inline(always)]
+    pub const fn sbpi_flag_n(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_sbpi_flag_n(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[inline(always)]
+    pub const fn sbpi_wr_fail(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_sbpi_wr_fail(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+    #[inline(always)]
+    pub const fn apb_dctrl_fail(&self) -> bool {
+        let val = (self.0 >> 2usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_apb_dctrl_fail(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+    }
+    #[inline(always)]
+    pub const fn apb_rd_sec_fail(&self) -> bool {
+        let val = (self.0 >> 3usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_apb_rd_sec_fail(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
+    }
+    #[inline(always)]
+    pub const fn apb_rd_nsec_fail(&self) -> bool {
+        let val = (self.0 >> 4usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_apb_rd_nsec_fail(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
+    }
+}
+impl Default for Inte {
+    #[inline(always)]
+    fn default() -> Inte {
+        Inte(0)
+    }
+}
+#[doc = "Interrupt Force"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Intf(pub u32);
+impl Intf {
+    #[inline(always)]
+    pub const fn sbpi_flag_n(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_sbpi_flag_n(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[inline(always)]
+    pub const fn sbpi_wr_fail(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_sbpi_wr_fail(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+    #[inline(always)]
+    pub const fn apb_dctrl_fail(&self) -> bool {
+        let val = (self.0 >> 2usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_apb_dctrl_fail(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+    }
+    #[inline(always)]
+    pub const fn apb_rd_sec_fail(&self) -> bool {
+        let val = (self.0 >> 3usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_apb_rd_sec_fail(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
+    }
+    #[inline(always)]
+    pub const fn apb_rd_nsec_fail(&self) -> bool {
+        let val = (self.0 >> 4usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_apb_rd_nsec_fail(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
+    }
+}
+impl Default for Intf {
+    #[inline(always)]
+    fn default() -> Intf {
+        Intf(0)
+    }
+}
+#[doc = "Raw Interrupts"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Intr(pub u32);
+impl Intr {
+    #[inline(always)]
+    pub const fn sbpi_flag_n(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_sbpi_flag_n(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[inline(always)]
+    pub const fn sbpi_wr_fail(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_sbpi_wr_fail(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+    #[inline(always)]
+    pub const fn apb_dctrl_fail(&self) -> bool {
+        let val = (self.0 >> 2usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_apb_dctrl_fail(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+    }
+    #[inline(always)]
+    pub const fn apb_rd_sec_fail(&self) -> bool {
+        let val = (self.0 >> 3usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_apb_rd_sec_fail(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
+    }
+    #[inline(always)]
+    pub const fn apb_rd_nsec_fail(&self) -> bool {
+        let val = (self.0 >> 4usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_apb_rd_nsec_fail(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
+    }
+}
+impl Default for Intr {
+    #[inline(always)]
+    fn default() -> Intr {
+        Intr(0)
+    }
+}
+#[doc = "Interrupt status after masking & forcing"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Ints(pub u32);
+impl Ints {
+    #[inline(always)]
+    pub const fn sbpi_flag_n(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_sbpi_flag_n(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[inline(always)]
+    pub const fn sbpi_wr_fail(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_sbpi_wr_fail(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+    #[inline(always)]
+    pub const fn apb_dctrl_fail(&self) -> bool {
+        let val = (self.0 >> 2usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_apb_dctrl_fail(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+    }
+    #[inline(always)]
+    pub const fn apb_rd_sec_fail(&self) -> bool {
+        let val = (self.0 >> 3usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_apb_rd_sec_fail(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
+    }
+    #[inline(always)]
+    pub const fn apb_rd_nsec_fail(&self) -> bool {
+        let val = (self.0 >> 4usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_apb_rd_nsec_fail(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
+    }
+}
+impl Default for Ints {
+    #[inline(always)]
+    fn default() -> Ints {
+        Ints(0)
+    }
+}
+#[doc = "Which keys were valid (enrolled) at boot time"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct KeyValid(pub u32);
+impl KeyValid {
+    #[inline(always)]
+    pub const fn key_valid(&self) -> u8 {
+        let val = (self.0 >> 0usize) & 0xff;
+        val as u8
+    }
+    #[inline(always)]
+    pub fn set_key_valid(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize);
+    }
+}
+impl Default for KeyValid {
+    #[inline(always)]
+    fn default() -> KeyValid {
+        KeyValid(0)
+    }
+}
+#[doc = "Dispatch instructions to the SBPI interface, used for programming the OTP fuses."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct SbpiInstr(pub u32);
+impl SbpiInstr {
+    #[doc = "wdata to be used only when payload_size_m1=0"]
+    #[inline(always)]
+    pub const fn short_wdata(&self) -> u8 {
+        let val = (self.0 >> 0usize) & 0xff;
+        val as u8
+    }
+    #[doc = "wdata to be used only when payload_size_m1=0"]
+    #[inline(always)]
+    pub fn set_short_wdata(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize);
+    }
+    #[inline(always)]
+    pub const fn cmd(&self) -> u8 {
+        let val = (self.0 >> 8usize) & 0xff;
+        val as u8
+    }
+    #[inline(always)]
+    pub fn set_cmd(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize);
+    }
+    #[doc = "Instruction target, it can be PMC (0x3a) or DAP (0x02)"]
+    #[inline(always)]
+    pub const fn target(&self) -> u8 {
+        let val = (self.0 >> 16usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Instruction target, it can be PMC (0x3a) or DAP (0x02)"]
+    #[inline(always)]
+    pub fn set_target(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize);
+    }
+    #[doc = "Instruction payload size in bytes minus 1"]
+    #[inline(always)]
+    pub const fn payload_size_m1(&self) -> u8 {
+        let val = (self.0 >> 24usize) & 0x0f;
+        val as u8
+    }
+    #[doc = "Instruction payload size in bytes minus 1"]
+    #[inline(always)]
+    pub fn set_payload_size_m1(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x0f << 24usize)) | (((val as u32) & 0x0f) << 24usize);
+    }
+    #[doc = "Instruction has payload (data to be written or to be read)"]
+    #[inline(always)]
+    pub const fn has_payload(&self) -> bool {
+        let val = (self.0 >> 28usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Instruction has payload (data to be written or to be read)"]
+    #[inline(always)]
+    pub fn set_has_payload(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 28usize)) | (((val as u32) & 0x01) << 28usize);
+    }
+    #[doc = "Payload type is write"]
+    #[inline(always)]
+    pub const fn is_wr(&self) -> bool {
+        let val = (self.0 >> 29usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Payload type is write"]
+    #[inline(always)]
+    pub fn set_is_wr(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 29usize)) | (((val as u32) & 0x01) << 29usize);
+    }
+    #[doc = "Execute instruction"]
+    #[inline(always)]
+    pub const fn exec(&self) -> bool {
+        let val = (self.0 >> 30usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Execute instruction"]
+    #[inline(always)]
+    pub fn set_exec(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 30usize)) | (((val as u32) & 0x01) << 30usize);
+    }
+}
+impl Default for SbpiInstr {
+    #[inline(always)]
+    fn default() -> SbpiInstr {
+        SbpiInstr(0)
+    }
+}
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct SbpiStatus(pub u32);
+impl SbpiStatus {
+    #[doc = "Read command has returned data"]
+    #[inline(always)]
+    pub const fn rdata_vld(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Read command has returned data"]
+    #[inline(always)]
+    pub fn set_rdata_vld(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[doc = "Last instruction done"]
+    #[inline(always)]
+    pub const fn instr_done(&self) -> bool {
+        let val = (self.0 >> 4usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Last instruction done"]
+    #[inline(always)]
+    pub fn set_instr_done(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
+    }
+    #[doc = "Last instruction missed (dropped), as the previous has not finished running"]
+    #[inline(always)]
+    pub const fn instr_miss(&self) -> bool {
+        let val = (self.0 >> 8usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Last instruction missed (dropped), as the previous has not finished running"]
+    #[inline(always)]
+    pub fn set_instr_miss(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
+    }
+    #[doc = "SBPI flag"]
+    #[inline(always)]
+    pub const fn flag(&self) -> bool {
+        let val = (self.0 >> 12usize) & 0x01;
+        val != 0
+    }
+    #[doc = "SBPI flag"]
+    #[inline(always)]
+    pub fn set_flag(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
+    }
+    #[doc = "SBPI MISO (master in - slave out): response from SBPI"]
+    #[inline(always)]
+    pub const fn miso(&self) -> u8 {
+        let val = (self.0 >> 16usize) & 0xff;
+        val as u8
+    }
+    #[doc = "SBPI MISO (master in - slave out): response from SBPI"]
+    #[inline(always)]
+    pub fn set_miso(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize);
+    }
+}
+impl Default for SbpiStatus {
+    #[inline(always)]
+    fn default() -> SbpiStatus {
+        SbpiStatus(0)
+    }
+}
+#[doc = "Software lock register for page 0. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct SwLock0(pub u32);
+impl SwLock0 {
+    #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."]
+    #[inline(always)]
+    pub const fn sec(&self) -> super::vals::SwLock0sec {
+        let val = (self.0 >> 0usize) & 0x03;
+        super::vals::SwLock0sec::from_bits(val as u8)
+    }
+    #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."]
+    #[inline(always)]
+    pub fn set_sec(&mut self, val: super::vals::SwLock0sec) {
+        self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize);
+    }
+    #[doc = "Non-secure lock status. Writes are OR'd with the current value."]
+    #[inline(always)]
+    pub const fn nsec(&self) -> super::vals::SwLock0nsec {
+        let val = (self.0 >> 2usize) & 0x03;
+        super::vals::SwLock0nsec::from_bits(val as u8)
+    }
+    #[doc = "Non-secure lock status. Writes are OR'd with the current value."]
+    #[inline(always)]
+    pub fn set_nsec(&mut self, val: super::vals::SwLock0nsec) {
+        self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize);
+    }
+}
+impl Default for SwLock0 {
+    #[inline(always)]
+    fn default() -> SwLock0 {
+        SwLock0(0)
+    }
+}
+#[doc = "Software lock register for page 1. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct SwLock1(pub u32);
+impl SwLock1 {
+    #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."]
+    #[inline(always)]
+    pub const fn sec(&self) -> super::vals::SwLock1sec {
+        let val = (self.0 >> 0usize) & 0x03;
+        super::vals::SwLock1sec::from_bits(val as u8)
+    }
+    #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."]
+    #[inline(always)]
+    pub fn set_sec(&mut self, val: super::vals::SwLock1sec) {
+        self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize);
+    }
+    #[doc = "Non-secure lock status. Writes are OR'd with the current value."]
+    #[inline(always)]
+    pub const fn nsec(&self) -> super::vals::SwLock1nsec {
+        let val = (self.0 >> 2usize) & 0x03;
+        super::vals::SwLock1nsec::from_bits(val as u8)
+    }
+    #[doc = "Non-secure lock status. Writes are OR'd with the current value."]
+    #[inline(always)]
+    pub fn set_nsec(&mut self, val: super::vals::SwLock1nsec) {
+        self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize);
+    }
+}
+impl Default for SwLock1 {
+    #[inline(always)]
+    fn default() -> SwLock1 {
+        SwLock1(0)
+    }
+}
+#[doc = "Software lock register for page 10. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct SwLock10(pub u32);
+impl SwLock10 {
+    #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."]
+    #[inline(always)]
+    pub const fn sec(&self) -> super::vals::SwLock10sec {
+        let val = (self.0 >> 0usize) & 0x03;
+        super::vals::SwLock10sec::from_bits(val as u8)
+    }
+    #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."]
+    #[inline(always)]
+    pub fn set_sec(&mut self, val: super::vals::SwLock10sec) {
+        self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize);
+    }
+    #[doc = "Non-secure lock status. Writes are OR'd with the current value."]
+    #[inline(always)]
+    pub const fn nsec(&self) -> super::vals::SwLock10nsec {
+        let val = (self.0 >> 2usize) & 0x03;
+        super::vals::SwLock10nsec::from_bits(val as u8)
+    }
+    #[doc = "Non-secure lock status. Writes are OR'd with the current value."]
+    #[inline(always)]
+    pub fn set_nsec(&mut self, val: super::vals::SwLock10nsec) {
+        self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize);
+    }
+}
+impl Default for SwLock10 {
+    #[inline(always)]
+    fn default() -> SwLock10 {
+        SwLock10(0)
+    }
+}
+#[doc = "Software lock register for page 11. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct SwLock11(pub u32);
+impl SwLock11 {
+    #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."]
+    #[inline(always)]
+    pub const fn sec(&self) -> super::vals::SwLock11sec {
+        let val = (self.0 >> 0usize) & 0x03;
+        super::vals::SwLock11sec::from_bits(val as u8)
+    }
+    #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."]
+    #[inline(always)]
+    pub fn set_sec(&mut self, val: super::vals::SwLock11sec) {
+        self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize);
+    }
+    #[doc = "Non-secure lock status. Writes are OR'd with the current value."]
+    #[inline(always)]
+    pub const fn nsec(&self) -> super::vals::SwLock11nsec {
+        let val = (self.0 >> 2usize) & 0x03;
+        super::vals::SwLock11nsec::from_bits(val as u8)
+    }
+    #[doc = "Non-secure lock status. Writes are OR'd with the current value."]
+    #[inline(always)]
+    pub fn set_nsec(&mut self, val: super::vals::SwLock11nsec) {
+        self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize);
+    }
+}
+impl Default for SwLock11 {
+    #[inline(always)]
+    fn default() -> SwLock11 {
+        SwLock11(0)
+    }
+}
+#[doc = "Software lock register for page 12. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct SwLock12(pub u32);
+impl SwLock12 {
+    #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."]
+    #[inline(always)]
+    pub const fn sec(&self) -> super::vals::SwLock12sec {
+        let val = (self.0 >> 0usize) & 0x03;
+        super::vals::SwLock12sec::from_bits(val as u8)
+    }
+    #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."]
+    #[inline(always)]
+    pub fn set_sec(&mut self, val: super::vals::SwLock12sec) {
+        self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize);
+    }
+    #[doc = "Non-secure lock status. Writes are OR'd with the current value."]
+    #[inline(always)]
+    pub const fn nsec(&self) -> super::vals::SwLock12nsec {
+        let val = (self.0 >> 2usize) & 0x03;
+        super::vals::SwLock12nsec::from_bits(val as u8)
+    }
+    #[doc = "Non-secure lock status. Writes are OR'd with the current value."]
+    #[inline(always)]
+    pub fn set_nsec(&mut self, val: super::vals::SwLock12nsec) {
+        self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize);
+    }
+}
+impl Default for SwLock12 {
+    #[inline(always)]
+    fn default() -> SwLock12 {
+        SwLock12(0)
+    }
+}
+#[doc = "Software lock register for page 13. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct SwLock13(pub u32);
+impl SwLock13 {
+    #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."]
+    #[inline(always)]
+    pub const fn sec(&self) -> super::vals::SwLock13sec {
+        let val = (self.0 >> 0usize) & 0x03;
+        super::vals::SwLock13sec::from_bits(val as u8)
+    }
+    #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."]
+    #[inline(always)]
+    pub fn set_sec(&mut self, val: super::vals::SwLock13sec) {
+        self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize);
+    }
+    #[doc = "Non-secure lock status. Writes are OR'd with the current value."]
+    #[inline(always)]
+    pub const fn nsec(&self) -> super::vals::SwLock13nsec {
+        let val = (self.0 >> 2usize) & 0x03;
+        super::vals::SwLock13nsec::from_bits(val as u8)
+    }
+    #[doc = "Non-secure lock status. Writes are OR'd with the current value."]
+    #[inline(always)]
+    pub fn set_nsec(&mut self, val: super::vals::SwLock13nsec) {
+        self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize);
+    }
+}
+impl Default for SwLock13 {
+    #[inline(always)]
+    fn default() -> SwLock13 {
+        SwLock13(0)
+    }
+}
+#[doc = "Software lock register for page 14. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct SwLock14(pub u32);
+impl SwLock14 {
+    #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."]
+    #[inline(always)]
+    pub const fn sec(&self) -> super::vals::SwLock14sec {
+        let val = (self.0 >> 0usize) & 0x03;
+        super::vals::SwLock14sec::from_bits(val as u8)
+    }
+    #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."]
+    #[inline(always)]
+    pub fn set_sec(&mut self, val: super::vals::SwLock14sec) {
+        self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize);
+    }
+    #[doc = "Non-secure lock status. Writes are OR'd with the current value."]
+    #[inline(always)]
+    pub const fn nsec(&self) -> super::vals::SwLock14nsec {
+        let val = (self.0 >> 2usize) & 0x03;
+        super::vals::SwLock14nsec::from_bits(val as u8)
+    }
+    #[doc = "Non-secure lock status. Writes are OR'd with the current value."]
+    #[inline(always)]
+    pub fn set_nsec(&mut self, val: super::vals::SwLock14nsec) {
+        self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize);
+    }
+}
+impl Default for SwLock14 {
+    #[inline(always)]
+    fn default() -> SwLock14 {
+        SwLock14(0)
+    }
+}
+#[doc = "Software lock register for page 15. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct SwLock15(pub u32);
+impl SwLock15 {
+    #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."]
+    #[inline(always)]
+    pub const fn sec(&self) -> super::vals::SwLock15sec {
+        let val = (self.0 >> 0usize) & 0x03;
+        super::vals::SwLock15sec::from_bits(val as u8)
+    }
+    #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."]
+    #[inline(always)]
+    pub fn set_sec(&mut self, val: super::vals::SwLock15sec) {
+        self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize);
+    }
+    #[doc = "Non-secure lock status. Writes are OR'd with the current value."]
+    #[inline(always)]
+    pub const fn nsec(&self) -> super::vals::SwLock15nsec {
+        let val = (self.0 >> 2usize) & 0x03;
+        super::vals::SwLock15nsec::from_bits(val as u8)
+    }
+    #[doc = "Non-secure lock status. Writes are OR'd with the current value."]
+    #[inline(always)]
+    pub fn set_nsec(&mut self, val: super::vals::SwLock15nsec) {
+        self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize);
+    }
+}
+impl Default for SwLock15 {
+    #[inline(always)]
+    fn default() -> SwLock15 {
+        SwLock15(0)
+    }
+}
+#[doc = "Software lock register for page 16. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct SwLock16(pub u32);
+impl SwLock16 {
+    #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."]
+    #[inline(always)]
+    pub const fn sec(&self) -> super::vals::SwLock16sec {
+        let val = (self.0 >> 0usize) & 0x03;
+        super::vals::SwLock16sec::from_bits(val as u8)
+    }
+    #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."]
+    #[inline(always)]
+    pub fn set_sec(&mut self, val: super::vals::SwLock16sec) {
+        self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize);
+    }
+    #[doc = "Non-secure lock status. Writes are OR'd with the current value."]
+    #[inline(always)]
+    pub const fn nsec(&self) -> super::vals::SwLock16nsec {
+        let val = (self.0 >> 2usize) & 0x03;
+        super::vals::SwLock16nsec::from_bits(val as u8)
+    }
+    #[doc = "Non-secure lock status. Writes are OR'd with the current value."]
+    #[inline(always)]
+    pub fn set_nsec(&mut self, val: super::vals::SwLock16nsec) {
+        self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize);
+    }
+}
+impl Default for SwLock16 {
+    #[inline(always)]
+    fn default() -> SwLock16 {
+        SwLock16(0)
+    }
+}
+#[doc = "Software lock register for page 17. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct SwLock17(pub u32);
+impl SwLock17 {
+    #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."]
+    #[inline(always)]
+    pub const fn sec(&self) -> super::vals::SwLock17sec {
+        let val = (self.0 >> 0usize) & 0x03;
+        super::vals::SwLock17sec::from_bits(val as u8)
+    }
+    #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."]
+    #[inline(always)]
+    pub fn set_sec(&mut self, val: super::vals::SwLock17sec) {
+        self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize);
+    }
+    #[doc = "Non-secure lock status. Writes are OR'd with the current value."]
+    #[inline(always)]
+    pub const fn nsec(&self) -> super::vals::SwLock17nsec {
+        let val = (self.0 >> 2usize) & 0x03;
+        super::vals::SwLock17nsec::from_bits(val as u8)
+    }
+    #[doc = "Non-secure lock status. Writes are OR'd with the current value."]
+    #[inline(always)]
+    pub fn set_nsec(&mut self, val: super::vals::SwLock17nsec) {
+        self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize);
+    }
+}
+impl Default for SwLock17 {
+    #[inline(always)]
+    fn default() -> SwLock17 {
+        SwLock17(0)
+    }
+}
+#[doc = "Software lock register for page 18. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct SwLock18(pub u32);
+impl SwLock18 {
+    #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."]
+    #[inline(always)]
+    pub const fn sec(&self) -> super::vals::SwLock18sec {
+        let val = (self.0 >> 0usize) & 0x03;
+        super::vals::SwLock18sec::from_bits(val as u8)
+    }
+    #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."]
+    #[inline(always)]
+    pub fn set_sec(&mut self, val: super::vals::SwLock18sec) {
+        self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize);
+    }
+    #[doc = "Non-secure lock status. Writes are OR'd with the current value."]
+    #[inline(always)]
+    pub const fn nsec(&self) -> super::vals::SwLock18nsec {
+        let val = (self.0 >> 2usize) & 0x03;
+        super::vals::SwLock18nsec::from_bits(val as u8)
+    }
+    #[doc = "Non-secure lock status. Writes are OR'd with the current value."]
+    #[inline(always)]
+    pub fn set_nsec(&mut self, val: super::vals::SwLock18nsec) {
+        self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize);
+    }
+}
+impl Default for SwLock18 {
+    #[inline(always)]
+    fn default() -> SwLock18 {
+        SwLock18(0)
+    }
+}
+#[doc = "Software lock register for page 19. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct SwLock19(pub u32);
+impl SwLock19 {
+    #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."]
+    #[inline(always)]
+    pub const fn sec(&self) -> super::vals::SwLock19sec {
+        let val = (self.0 >> 0usize) & 0x03;
+        super::vals::SwLock19sec::from_bits(val as u8)
+    }
+    #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."]
+    #[inline(always)]
+    pub fn set_sec(&mut self, val: super::vals::SwLock19sec) {
+        self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize);
+    }
+    #[doc = "Non-secure lock status. Writes are OR'd with the current value."]
+    #[inline(always)]
+    pub const fn nsec(&self) -> super::vals::SwLock19nsec {
+        let val = (self.0 >> 2usize) & 0x03;
+        super::vals::SwLock19nsec::from_bits(val as u8)
+    }
+    #[doc = "Non-secure lock status. Writes are OR'd with the current value."]
+    #[inline(always)]
+    pub fn set_nsec(&mut self, val: super::vals::SwLock19nsec) {
+        self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize);
+    }
+}
+impl Default for SwLock19 {
+    #[inline(always)]
+    fn default() -> SwLock19 {
+        SwLock19(0)
+    }
+}
+#[doc = "Software lock register for page 2. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct SwLock2(pub u32);
+impl SwLock2 {
+    #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."]
+    #[inline(always)]
+    pub const fn sec(&self) -> super::vals::SwLock2sec {
+        let val = (self.0 >> 0usize) & 0x03;
+        super::vals::SwLock2sec::from_bits(val as u8)
+    }
+    #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."]
+    #[inline(always)]
+    pub fn set_sec(&mut self, val: super::vals::SwLock2sec) {
+        self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize);
+    }
+    #[doc = "Non-secure lock status. Writes are OR'd with the current value."]
+    #[inline(always)]
+    pub const fn nsec(&self) -> super::vals::SwLock2nsec {
+        let val = (self.0 >> 2usize) & 0x03;
+        super::vals::SwLock2nsec::from_bits(val as u8)
+    }
+    #[doc = "Non-secure lock status. Writes are OR'd with the current value."]
+    #[inline(always)]
+    pub fn set_nsec(&mut self, val: super::vals::SwLock2nsec) {
+        self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize);
+    }
+}
+impl Default for SwLock2 {
+    #[inline(always)]
+    fn default() -> SwLock2 {
+        SwLock2(0)
+    }
+}
+#[doc = "Software lock register for page 20. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct SwLock20(pub u32);
+impl SwLock20 {
+    #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."]
+    #[inline(always)]
+    pub const fn sec(&self) -> super::vals::SwLock20sec {
+        let val = (self.0 >> 0usize) & 0x03;
+        super::vals::SwLock20sec::from_bits(val as u8)
+    }
+    #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."]
+    #[inline(always)]
+    pub fn set_sec(&mut self, val: super::vals::SwLock20sec) {
+        self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize);
+    }
+    #[doc = "Non-secure lock status. Writes are OR'd with the current value."]
+    #[inline(always)]
+    pub const fn nsec(&self) -> super::vals::SwLock20nsec {
+        let val = (self.0 >> 2usize) & 0x03;
+        super::vals::SwLock20nsec::from_bits(val as u8)
+    }
+    #[doc = "Non-secure lock status. Writes are OR'd with the current value."]
+    #[inline(always)]
+    pub fn set_nsec(&mut self, val: super::vals::SwLock20nsec) {
+        self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize);
+    }
+}
+impl Default for SwLock20 {
+    #[inline(always)]
+    fn default() -> SwLock20 {
+        SwLock20(0)
+    }
+}
+#[doc = "Software lock register for page 21. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct SwLock21(pub u32);
+impl SwLock21 {
+    #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."]
+    #[inline(always)]
+    pub const fn sec(&self) -> super::vals::SwLock21sec {
+        let val = (self.0 >> 0usize) & 0x03;
+        super::vals::SwLock21sec::from_bits(val as u8)
+    }
+    #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."]
+    #[inline(always)]
+    pub fn set_sec(&mut self, val: super::vals::SwLock21sec) {
+        self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize);
+    }
+    #[doc = "Non-secure lock status. Writes are OR'd with the current value."]
+    #[inline(always)]
+    pub const fn nsec(&self) -> super::vals::SwLock21nsec {
+        let val = (self.0 >> 2usize) & 0x03;
+        super::vals::SwLock21nsec::from_bits(val as u8)
+    }
+    #[doc = "Non-secure lock status. Writes are OR'd with the current value."]
+    #[inline(always)]
+    pub fn set_nsec(&mut self, val: super::vals::SwLock21nsec) {
+        self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize);
+    }
+}
+impl Default for SwLock21 {
+    #[inline(always)]
+    fn default() -> SwLock21 {
+        SwLock21(0)
+    }
+}
+#[doc = "Software lock register for page 22. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct SwLock22(pub u32);
+impl SwLock22 {
+    #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."]
+    #[inline(always)]
+    pub const fn sec(&self) -> super::vals::SwLock22sec {
+        let val = (self.0 >> 0usize) & 0x03;
+        super::vals::SwLock22sec::from_bits(val as u8)
+    }
+    #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."]
+    #[inline(always)]
+    pub fn set_sec(&mut self, val: super::vals::SwLock22sec) {
+        self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize);
+    }
+    #[doc = "Non-secure lock status. Writes are OR'd with the current value."]
+    #[inline(always)]
+    pub const fn nsec(&self) -> super::vals::SwLock22nsec {
+        let val = (self.0 >> 2usize) & 0x03;
+        super::vals::SwLock22nsec::from_bits(val as u8)
+    }
+    #[doc = "Non-secure lock status. Writes are OR'd with the current value."]
+    #[inline(always)]
+    pub fn set_nsec(&mut self, val: super::vals::SwLock22nsec) {
+        self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize);
+    }
+}
+impl Default for SwLock22 {
+    #[inline(always)]
+    fn default() -> SwLock22 {
+        SwLock22(0)
+    }
+}
+#[doc = "Software lock register for page 23. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct SwLock23(pub u32);
+impl SwLock23 {
+    #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."]
+    #[inline(always)]
+    pub const fn sec(&self) -> super::vals::SwLock23sec {
+        let val = (self.0 >> 0usize) & 0x03;
+        super::vals::SwLock23sec::from_bits(val as u8)
+    }
+    #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."]
+    #[inline(always)]
+    pub fn set_sec(&mut self, val: super::vals::SwLock23sec) {
+        self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize);
+    }
+    #[doc = "Non-secure lock status. Writes are OR'd with the current value."]
+    #[inline(always)]
+    pub const fn nsec(&self) -> super::vals::SwLock23nsec {
+        let val = (self.0 >> 2usize) & 0x03;
+        super::vals::SwLock23nsec::from_bits(val as u8)
+    }
+    #[doc = "Non-secure lock status. Writes are OR'd with the current value."]
+    #[inline(always)]
+    pub fn set_nsec(&mut self, val: super::vals::SwLock23nsec) {
+        self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize);
+    }
+}
+impl Default for SwLock23 {
+    #[inline(always)]
+    fn default() -> SwLock23 {
+        SwLock23(0)
+    }
+}
+#[doc = "Software lock register for page 24. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct SwLock24(pub u32);
+impl SwLock24 {
+    #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."]
+    #[inline(always)]
+    pub const fn sec(&self) -> super::vals::SwLock24sec {
+        let val = (self.0 >> 0usize) & 0x03;
+        super::vals::SwLock24sec::from_bits(val as u8)
+    }
+    #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."]
+    #[inline(always)]
+    pub fn set_sec(&mut self, val: super::vals::SwLock24sec) {
+        self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize);
+    }
+    #[doc = "Non-secure lock status. Writes are OR'd with the current value."]
+    #[inline(always)]
+    pub const fn nsec(&self) -> super::vals::SwLock24nsec {
+        let val = (self.0 >> 2usize) & 0x03;
+        super::vals::SwLock24nsec::from_bits(val as u8)
+    }
+    #[doc = "Non-secure lock status. Writes are OR'd with the current value."]
+    #[inline(always)]
+    pub fn set_nsec(&mut self, val: super::vals::SwLock24nsec) {
+        self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize);
+    }
+}
+impl Default for SwLock24 {
+    #[inline(always)]
+    fn default() -> SwLock24 {
+        SwLock24(0)
+    }
+}
+#[doc = "Software lock register for page 25. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct SwLock25(pub u32);
+impl SwLock25 {
+    #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."]
+    #[inline(always)]
+    pub const fn sec(&self) -> super::vals::SwLock25sec {
+        let val = (self.0 >> 0usize) & 0x03;
+        super::vals::SwLock25sec::from_bits(val as u8)
+    }
+    #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."]
+    #[inline(always)]
+    pub fn set_sec(&mut self, val: super::vals::SwLock25sec) {
+        self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize);
+    }
+    #[doc = "Non-secure lock status. Writes are OR'd with the current value."]
+    #[inline(always)]
+    pub const fn nsec(&self) -> super::vals::SwLock25nsec {
+        let val = (self.0 >> 2usize) & 0x03;
+        super::vals::SwLock25nsec::from_bits(val as u8)
+    }
+    #[doc = "Non-secure lock status. Writes are OR'd with the current value."]
+    #[inline(always)]
+    pub fn set_nsec(&mut self, val: super::vals::SwLock25nsec) {
+        self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize);
+    }
+}
+impl Default for SwLock25 {
+    #[inline(always)]
+    fn default() -> SwLock25 {
+        SwLock25(0)
+    }
+}
+#[doc = "Software lock register for page 26. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct SwLock26(pub u32);
+impl SwLock26 {
+    #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."]
+    #[inline(always)]
+    pub const fn sec(&self) -> super::vals::SwLock26sec {
+        let val = (self.0 >> 0usize) & 0x03;
+        super::vals::SwLock26sec::from_bits(val as u8)
+    }
+    #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."]
+    #[inline(always)]
+    pub fn set_sec(&mut self, val: super::vals::SwLock26sec) {
+        self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize);
+    }
+    #[doc = "Non-secure lock status. Writes are OR'd with the current value."]
+    #[inline(always)]
+    pub const fn nsec(&self) -> super::vals::SwLock26nsec {
+        let val = (self.0 >> 2usize) & 0x03;
+        super::vals::SwLock26nsec::from_bits(val as u8)
+    }
+    #[doc = "Non-secure lock status. Writes are OR'd with the current value."]
+    #[inline(always)]
+    pub fn set_nsec(&mut self, val: super::vals::SwLock26nsec) {
+        self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize);
+    }
+}
+impl Default for SwLock26 {
+    #[inline(always)]
+    fn default() -> SwLock26 {
+        SwLock26(0)
+    }
+}
+#[doc = "Software lock register for page 27. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct SwLock27(pub u32);
+impl SwLock27 {
+    #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."]
+    #[inline(always)]
+    pub const fn sec(&self) -> super::vals::SwLock27sec {
+        let val = (self.0 >> 0usize) & 0x03;
+        super::vals::SwLock27sec::from_bits(val as u8)
+    }
+    #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."]
+    #[inline(always)]
+    pub fn set_sec(&mut self, val: super::vals::SwLock27sec) {
+        self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize);
+    }
+    #[doc = "Non-secure lock status. Writes are OR'd with the current value."]
+    #[inline(always)]
+    pub const fn nsec(&self) -> super::vals::SwLock27nsec {
+        let val = (self.0 >> 2usize) & 0x03;
+        super::vals::SwLock27nsec::from_bits(val as u8)
+    }
+    #[doc = "Non-secure lock status. Writes are OR'd with the current value."]
+    #[inline(always)]
+    pub fn set_nsec(&mut self, val: super::vals::SwLock27nsec) {
+        self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize);
+    }
+}
+impl Default for SwLock27 {
+    #[inline(always)]
+    fn default() -> SwLock27 {
+        SwLock27(0)
+    }
+}
+#[doc = "Software lock register for page 28. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct SwLock28(pub u32);
+impl SwLock28 {
+    #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."]
+    #[inline(always)]
+    pub const fn sec(&self) -> super::vals::SwLock28sec {
+        let val = (self.0 >> 0usize) & 0x03;
+        super::vals::SwLock28sec::from_bits(val as u8)
+    }
+    #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."]
+    #[inline(always)]
+    pub fn set_sec(&mut self, val: super::vals::SwLock28sec) {
+        self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize);
+    }
+    #[doc = "Non-secure lock status. Writes are OR'd with the current value."]
+    #[inline(always)]
+    pub const fn nsec(&self) -> super::vals::SwLock28nsec {
+        let val = (self.0 >> 2usize) & 0x03;
+        super::vals::SwLock28nsec::from_bits(val as u8)
+    }
+    #[doc = "Non-secure lock status. Writes are OR'd with the current value."]
+    #[inline(always)]
+    pub fn set_nsec(&mut self, val: super::vals::SwLock28nsec) {
+        self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize);
+    }
+}
+impl Default for SwLock28 {
+    #[inline(always)]
+    fn default() -> SwLock28 {
+        SwLock28(0)
+    }
+}
+#[doc = "Software lock register for page 29. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct SwLock29(pub u32);
+impl SwLock29 {
+    #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."]
+    #[inline(always)]
+    pub const fn sec(&self) -> super::vals::SwLock29sec {
+        let val = (self.0 >> 0usize) & 0x03;
+        super::vals::SwLock29sec::from_bits(val as u8)
+    }
+    #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."]
+    #[inline(always)]
+    pub fn set_sec(&mut self, val: super::vals::SwLock29sec) {
+        self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize);
+    }
+    #[doc = "Non-secure lock status. Writes are OR'd with the current value."]
+    #[inline(always)]
+    pub const fn nsec(&self) -> super::vals::SwLock29nsec {
+        let val = (self.0 >> 2usize) & 0x03;
+        super::vals::SwLock29nsec::from_bits(val as u8)
+    }
+    #[doc = "Non-secure lock status. Writes are OR'd with the current value."]
+    #[inline(always)]
+    pub fn set_nsec(&mut self, val: super::vals::SwLock29nsec) {
+        self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize);
+    }
+}
+impl Default for SwLock29 {
+    #[inline(always)]
+    fn default() -> SwLock29 {
+        SwLock29(0)
+    }
+}
+#[doc = "Software lock register for page 3. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct SwLock3(pub u32);
+impl SwLock3 {
+    #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."]
+    #[inline(always)]
+    pub const fn sec(&self) -> super::vals::SwLock3sec {
+        let val = (self.0 >> 0usize) & 0x03;
+        super::vals::SwLock3sec::from_bits(val as u8)
+    }
+    #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."]
+    #[inline(always)]
+    pub fn set_sec(&mut self, val: super::vals::SwLock3sec) {
+        self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize);
+    }
+    #[doc = "Non-secure lock status. Writes are OR'd with the current value."]
+    #[inline(always)]
+    pub const fn nsec(&self) -> super::vals::SwLock3nsec {
+        let val = (self.0 >> 2usize) & 0x03;
+        super::vals::SwLock3nsec::from_bits(val as u8)
+    }
+    #[doc = "Non-secure lock status. Writes are OR'd with the current value."]
+    #[inline(always)]
+    pub fn set_nsec(&mut self, val: super::vals::SwLock3nsec) {
+        self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize);
+    }
+}
+impl Default for SwLock3 {
+    #[inline(always)]
+    fn default() -> SwLock3 {
+        SwLock3(0)
+    }
+}
+#[doc = "Software lock register for page 30. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct SwLock30(pub u32);
+impl SwLock30 {
+    #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."]
+    #[inline(always)]
+    pub const fn sec(&self) -> super::vals::SwLock30sec {
+        let val = (self.0 >> 0usize) & 0x03;
+        super::vals::SwLock30sec::from_bits(val as u8)
+    }
+    #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."]
+    #[inline(always)]
+    pub fn set_sec(&mut self, val: super::vals::SwLock30sec) {
+        self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize);
+    }
+    #[doc = "Non-secure lock status. Writes are OR'd with the current value."]
+    #[inline(always)]
+    pub const fn nsec(&self) -> super::vals::SwLock30nsec {
+        let val = (self.0 >> 2usize) & 0x03;
+        super::vals::SwLock30nsec::from_bits(val as u8)
+    }
+    #[doc = "Non-secure lock status. Writes are OR'd with the current value."]
+    #[inline(always)]
+    pub fn set_nsec(&mut self, val: super::vals::SwLock30nsec) {
+        self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize);
+    }
+}
+impl Default for SwLock30 {
+    #[inline(always)]
+    fn default() -> SwLock30 {
+        SwLock30(0)
+    }
+}
+#[doc = "Software lock register for page 31. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct SwLock31(pub u32);
+impl SwLock31 {
+    #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."]
+    #[inline(always)]
+    pub const fn sec(&self) -> super::vals::SwLock31sec {
+        let val = (self.0 >> 0usize) & 0x03;
+        super::vals::SwLock31sec::from_bits(val as u8)
+    }
+    #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."]
+    #[inline(always)]
+    pub fn set_sec(&mut self, val: super::vals::SwLock31sec) {
+        self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize);
+    }
+    #[doc = "Non-secure lock status. Writes are OR'd with the current value."]
+    #[inline(always)]
+    pub const fn nsec(&self) -> super::vals::SwLock31nsec {
+        let val = (self.0 >> 2usize) & 0x03;
+        super::vals::SwLock31nsec::from_bits(val as u8)
+    }
+    #[doc = "Non-secure lock status. Writes are OR'd with the current value."]
+    #[inline(always)]
+    pub fn set_nsec(&mut self, val: super::vals::SwLock31nsec) {
+        self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize);
+    }
+}
+impl Default for SwLock31 {
+    #[inline(always)]
+    fn default() -> SwLock31 {
+        SwLock31(0)
+    }
+}
+#[doc = "Software lock register for page 32. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct SwLock32(pub u32);
+impl SwLock32 {
+    #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."]
+    #[inline(always)]
+    pub const fn sec(&self) -> super::vals::SwLock32sec {
+        let val = (self.0 >> 0usize) & 0x03;
+        super::vals::SwLock32sec::from_bits(val as u8)
+    }
+    #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."]
+    #[inline(always)]
+    pub fn set_sec(&mut self, val: super::vals::SwLock32sec) {
+        self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize);
+    }
+    #[doc = "Non-secure lock status. Writes are OR'd with the current value."]
+    #[inline(always)]
+    pub const fn nsec(&self) -> super::vals::SwLock32nsec {
+        let val = (self.0 >> 2usize) & 0x03;
+        super::vals::SwLock32nsec::from_bits(val as u8)
+    }
+    #[doc = "Non-secure lock status. Writes are OR'd with the current value."]
+    #[inline(always)]
+    pub fn set_nsec(&mut self, val: super::vals::SwLock32nsec) {
+        self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize);
+    }
+}
+impl Default for SwLock32 {
+    #[inline(always)]
+    fn default() -> SwLock32 {
+        SwLock32(0)
+    }
+}
+#[doc = "Software lock register for page 33. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct SwLock33(pub u32);
+impl SwLock33 {
+    #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."]
+    #[inline(always)]
+    pub const fn sec(&self) -> super::vals::SwLock33sec {
+        let val = (self.0 >> 0usize) & 0x03;
+        super::vals::SwLock33sec::from_bits(val as u8)
+    }
+    #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."]
+    #[inline(always)]
+    pub fn set_sec(&mut self, val: super::vals::SwLock33sec) {
+        self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize);
+    }
+    #[doc = "Non-secure lock status. Writes are OR'd with the current value."]
+    #[inline(always)]
+    pub const fn nsec(&self) -> super::vals::SwLock33nsec {
+        let val = (self.0 >> 2usize) & 0x03;
+        super::vals::SwLock33nsec::from_bits(val as u8)
+    }
+    #[doc = "Non-secure lock status. Writes are OR'd with the current value."]
+    #[inline(always)]
+    pub fn set_nsec(&mut self, val: super::vals::SwLock33nsec) {
+        self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize);
+    }
+}
+impl Default for SwLock33 {
+    #[inline(always)]
+    fn default() -> SwLock33 {
+        SwLock33(0)
+    }
+}
+#[doc = "Software lock register for page 34. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct SwLock34(pub u32);
+impl SwLock34 {
+    #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."]
+    #[inline(always)]
+    pub const fn sec(&self) -> super::vals::SwLock34sec {
+        let val = (self.0 >> 0usize) & 0x03;
+        super::vals::SwLock34sec::from_bits(val as u8)
+    }
+    #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."]
+    #[inline(always)]
+    pub fn set_sec(&mut self, val: super::vals::SwLock34sec) {
+        self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize);
+    }
+    #[doc = "Non-secure lock status. Writes are OR'd with the current value."]
+    #[inline(always)]
+    pub const fn nsec(&self) -> super::vals::SwLock34nsec {
+        let val = (self.0 >> 2usize) & 0x03;
+        super::vals::SwLock34nsec::from_bits(val as u8)
+    }
+    #[doc = "Non-secure lock status. Writes are OR'd with the current value."]
+    #[inline(always)]
+    pub fn set_nsec(&mut self, val: super::vals::SwLock34nsec) {
+        self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize);
+    }
+}
+impl Default for SwLock34 {
+    #[inline(always)]
+    fn default() -> SwLock34 {
+        SwLock34(0)
+    }
+}
+#[doc = "Software lock register for page 35. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct SwLock35(pub u32);
+impl SwLock35 {
+    #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."]
+    #[inline(always)]
+    pub const fn sec(&self) -> super::vals::SwLock35sec {
+        let val = (self.0 >> 0usize) & 0x03;
+        super::vals::SwLock35sec::from_bits(val as u8)
+    }
+    #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."]
+    #[inline(always)]
+    pub fn set_sec(&mut self, val: super::vals::SwLock35sec) {
+        self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize);
+    }
+    #[doc = "Non-secure lock status. Writes are OR'd with the current value."]
+    #[inline(always)]
+    pub const fn nsec(&self) -> super::vals::SwLock35nsec {
+        let val = (self.0 >> 2usize) & 0x03;
+        super::vals::SwLock35nsec::from_bits(val as u8)
+    }
+    #[doc = "Non-secure lock status. Writes are OR'd with the current value."]
+    #[inline(always)]
+    pub fn set_nsec(&mut self, val: super::vals::SwLock35nsec) {
+        self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize);
+    }
+}
+impl Default for SwLock35 {
+    #[inline(always)]
+    fn default() -> SwLock35 {
+        SwLock35(0)
+    }
+}
+#[doc = "Software lock register for page 36. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct SwLock36(pub u32);
+impl SwLock36 {
+    #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."]
+    #[inline(always)]
+    pub const fn sec(&self) -> super::vals::SwLock36sec {
+        let val = (self.0 >> 0usize) & 0x03;
+        super::vals::SwLock36sec::from_bits(val as u8)
+    }
+    #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."]
+    #[inline(always)]
+    pub fn set_sec(&mut self, val: super::vals::SwLock36sec) {
+        self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize);
+    }
+    #[doc = "Non-secure lock status. Writes are OR'd with the current value."]
+    #[inline(always)]
+    pub const fn nsec(&self) -> super::vals::SwLock36nsec {
+        let val = (self.0 >> 2usize) & 0x03;
+        super::vals::SwLock36nsec::from_bits(val as u8)
+    }
+    #[doc = "Non-secure lock status. Writes are OR'd with the current value."]
+    #[inline(always)]
+    pub fn set_nsec(&mut self, val: super::vals::SwLock36nsec) {
+        self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize);
+    }
+}
+impl Default for SwLock36 {
+    #[inline(always)]
+    fn default() -> SwLock36 {
+        SwLock36(0)
+    }
+}
+#[doc = "Software lock register for page 37. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct SwLock37(pub u32);
+impl SwLock37 {
+    #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."]
+    #[inline(always)]
+    pub const fn sec(&self) -> super::vals::SwLock37sec {
+        let val = (self.0 >> 0usize) & 0x03;
+        super::vals::SwLock37sec::from_bits(val as u8)
+    }
+    #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."]
+    #[inline(always)]
+    pub fn set_sec(&mut self, val: super::vals::SwLock37sec) {
+        self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize);
+    }
+    #[doc = "Non-secure lock status. Writes are OR'd with the current value."]
+    #[inline(always)]
+    pub const fn nsec(&self) -> super::vals::SwLock37nsec {
+        let val = (self.0 >> 2usize) & 0x03;
+        super::vals::SwLock37nsec::from_bits(val as u8)
+    }
+    #[doc = "Non-secure lock status. Writes are OR'd with the current value."]
+    #[inline(always)]
+    pub fn set_nsec(&mut self, val: super::vals::SwLock37nsec) {
+        self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize);
+    }
+}
+impl Default for SwLock37 {
+    #[inline(always)]
+    fn default() -> SwLock37 {
+        SwLock37(0)
+    }
+}
+#[doc = "Software lock register for page 38. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct SwLock38(pub u32);
+impl SwLock38 {
+    #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."]
+    #[inline(always)]
+    pub const fn sec(&self) -> super::vals::SwLock38sec {
+        let val = (self.0 >> 0usize) & 0x03;
+        super::vals::SwLock38sec::from_bits(val as u8)
+    }
+    #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."]
+    #[inline(always)]
+    pub fn set_sec(&mut self, val: super::vals::SwLock38sec) {
+        self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize);
+    }
+    #[doc = "Non-secure lock status. Writes are OR'd with the current value."]
+    #[inline(always)]
+    pub const fn nsec(&self) -> super::vals::SwLock38nsec {
+        let val = (self.0 >> 2usize) & 0x03;
+        super::vals::SwLock38nsec::from_bits(val as u8)
+    }
+    #[doc = "Non-secure lock status. Writes are OR'd with the current value."]
+    #[inline(always)]
+    pub fn set_nsec(&mut self, val: super::vals::SwLock38nsec) {
+        self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize);
+    }
+}
+impl Default for SwLock38 {
+    #[inline(always)]
+    fn default() -> SwLock38 {
+        SwLock38(0)
+    }
+}
+#[doc = "Software lock register for page 39. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct SwLock39(pub u32);
+impl SwLock39 {
+    #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."]
+    #[inline(always)]
+    pub const fn sec(&self) -> super::vals::SwLock39sec {
+        let val = (self.0 >> 0usize) & 0x03;
+        super::vals::SwLock39sec::from_bits(val as u8)
+    }
+    #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."]
+    #[inline(always)]
+    pub fn set_sec(&mut self, val: super::vals::SwLock39sec) {
+        self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize);
+    }
+    #[doc = "Non-secure lock status. Writes are OR'd with the current value."]
+    #[inline(always)]
+    pub const fn nsec(&self) -> super::vals::SwLock39nsec {
+        let val = (self.0 >> 2usize) & 0x03;
+        super::vals::SwLock39nsec::from_bits(val as u8)
+    }
+    #[doc = "Non-secure lock status. Writes are OR'd with the current value."]
+    #[inline(always)]
+    pub fn set_nsec(&mut self, val: super::vals::SwLock39nsec) {
+        self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize);
+    }
+}
+impl Default for SwLock39 {
+    #[inline(always)]
+    fn default() -> SwLock39 {
+        SwLock39(0)
+    }
+}
+#[doc = "Software lock register for page 4. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct SwLock4(pub u32);
+impl SwLock4 {
+    #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."]
+    #[inline(always)]
+    pub const fn sec(&self) -> super::vals::SwLock4sec {
+        let val = (self.0 >> 0usize) & 0x03;
+        super::vals::SwLock4sec::from_bits(val as u8)
+    }
+    #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."]
+    #[inline(always)]
+    pub fn set_sec(&mut self, val: super::vals::SwLock4sec) {
+        self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize);
+    }
+    #[doc = "Non-secure lock status. Writes are OR'd with the current value."]
+    #[inline(always)]
+    pub const fn nsec(&self) -> super::vals::SwLock4nsec {
+        let val = (self.0 >> 2usize) & 0x03;
+        super::vals::SwLock4nsec::from_bits(val as u8)
+    }
+    #[doc = "Non-secure lock status. Writes are OR'd with the current value."]
+    #[inline(always)]
+    pub fn set_nsec(&mut self, val: super::vals::SwLock4nsec) {
+        self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize);
+    }
+}
+impl Default for SwLock4 {
+    #[inline(always)]
+    fn default() -> SwLock4 {
+        SwLock4(0)
+    }
+}
+#[doc = "Software lock register for page 40. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct SwLock40(pub u32);
+impl SwLock40 {
+    #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."]
+    #[inline(always)]
+    pub const fn sec(&self) -> super::vals::SwLock40sec {
+        let val = (self.0 >> 0usize) & 0x03;
+        super::vals::SwLock40sec::from_bits(val as u8)
+    }
+    #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."]
+    #[inline(always)]
+    pub fn set_sec(&mut self, val: super::vals::SwLock40sec) {
+        self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize);
+    }
+    #[doc = "Non-secure lock status. Writes are OR'd with the current value."]
+    #[inline(always)]
+    pub const fn nsec(&self) -> super::vals::SwLock40nsec {
+        let val = (self.0 >> 2usize) & 0x03;
+        super::vals::SwLock40nsec::from_bits(val as u8)
+    }
+    #[doc = "Non-secure lock status. Writes are OR'd with the current value."]
+    #[inline(always)]
+    pub fn set_nsec(&mut self, val: super::vals::SwLock40nsec) {
+        self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize);
+    }
+}
+impl Default for SwLock40 {
+    #[inline(always)]
+    fn default() -> SwLock40 {
+        SwLock40(0)
+    }
+}
+#[doc = "Software lock register for page 41. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct SwLock41(pub u32);
+impl SwLock41 {
+    #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."]
+    #[inline(always)]
+    pub const fn sec(&self) -> super::vals::SwLock41sec {
+        let val = (self.0 >> 0usize) & 0x03;
+        super::vals::SwLock41sec::from_bits(val as u8)
+    }
+    #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."]
+    #[inline(always)]
+    pub fn set_sec(&mut self, val: super::vals::SwLock41sec) {
+        self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize);
+    }
+    #[doc = "Non-secure lock status. Writes are OR'd with the current value."]
+    #[inline(always)]
+    pub const fn nsec(&self) -> super::vals::SwLock41nsec {
+        let val = (self.0 >> 2usize) & 0x03;
+        super::vals::SwLock41nsec::from_bits(val as u8)
+    }
+    #[doc = "Non-secure lock status. Writes are OR'd with the current value."]
+    #[inline(always)]
+    pub fn set_nsec(&mut self, val: super::vals::SwLock41nsec) {
+        self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize);
+    }
+}
+impl Default for SwLock41 {
+    #[inline(always)]
+    fn default() -> SwLock41 {
+        SwLock41(0)
+    }
+}
+#[doc = "Software lock register for page 42. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct SwLock42(pub u32);
+impl SwLock42 {
+    #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."]
+    #[inline(always)]
+    pub const fn sec(&self) -> super::vals::SwLock42sec {
+        let val = (self.0 >> 0usize) & 0x03;
+        super::vals::SwLock42sec::from_bits(val as u8)
+    }
+    #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."]
+    #[inline(always)]
+    pub fn set_sec(&mut self, val: super::vals::SwLock42sec) {
+        self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize);
+    }
+    #[doc = "Non-secure lock status. Writes are OR'd with the current value."]
+    #[inline(always)]
+    pub const fn nsec(&self) -> super::vals::SwLock42nsec {
+        let val = (self.0 >> 2usize) & 0x03;
+        super::vals::SwLock42nsec::from_bits(val as u8)
+    }
+    #[doc = "Non-secure lock status. Writes are OR'd with the current value."]
+    #[inline(always)]
+    pub fn set_nsec(&mut self, val: super::vals::SwLock42nsec) {
+        self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize);
+    }
+}
+impl Default for SwLock42 {
+    #[inline(always)]
+    fn default() -> SwLock42 {
+        SwLock42(0)
+    }
+}
+#[doc = "Software lock register for page 43. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct SwLock43(pub u32);
+impl SwLock43 {
+    #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."]
+    #[inline(always)]
+    pub const fn sec(&self) -> super::vals::SwLock43sec {
+        let val = (self.0 >> 0usize) & 0x03;
+        super::vals::SwLock43sec::from_bits(val as u8)
+    }
+    #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."]
+    #[inline(always)]
+    pub fn set_sec(&mut self, val: super::vals::SwLock43sec) {
+        self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize);
+    }
+    #[doc = "Non-secure lock status. Writes are OR'd with the current value."]
+    #[inline(always)]
+    pub const fn nsec(&self) -> super::vals::SwLock43nsec {
+        let val = (self.0 >> 2usize) & 0x03;
+        super::vals::SwLock43nsec::from_bits(val as u8)
+    }
+    #[doc = "Non-secure lock status. Writes are OR'd with the current value."]
+    #[inline(always)]
+    pub fn set_nsec(&mut self, val: super::vals::SwLock43nsec) {
+        self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize);
+    }
+}
+impl Default for SwLock43 {
+    #[inline(always)]
+    fn default() -> SwLock43 {
+        SwLock43(0)
+    }
+}
+#[doc = "Software lock register for page 44. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct SwLock44(pub u32);
+impl SwLock44 {
+    #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."]
+    #[inline(always)]
+    pub const fn sec(&self) -> super::vals::SwLock44sec {
+        let val = (self.0 >> 0usize) & 0x03;
+        super::vals::SwLock44sec::from_bits(val as u8)
+    }
+    #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."]
+    #[inline(always)]
+    pub fn set_sec(&mut self, val: super::vals::SwLock44sec) {
+        self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize);
+    }
+    #[doc = "Non-secure lock status. Writes are OR'd with the current value."]
+    #[inline(always)]
+    pub const fn nsec(&self) -> super::vals::SwLock44nsec {
+        let val = (self.0 >> 2usize) & 0x03;
+        super::vals::SwLock44nsec::from_bits(val as u8)
+    }
+    #[doc = "Non-secure lock status. Writes are OR'd with the current value."]
+    #[inline(always)]
+    pub fn set_nsec(&mut self, val: super::vals::SwLock44nsec) {
+        self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize);
+    }
+}
+impl Default for SwLock44 {
+    #[inline(always)]
+    fn default() -> SwLock44 {
+        SwLock44(0)
+    }
+}
+#[doc = "Software lock register for page 45. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct SwLock45(pub u32);
+impl SwLock45 {
+    #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."]
+    #[inline(always)]
+    pub const fn sec(&self) -> super::vals::SwLock45sec {
+        let val = (self.0 >> 0usize) & 0x03;
+        super::vals::SwLock45sec::from_bits(val as u8)
+    }
+    #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."]
+    #[inline(always)]
+    pub fn set_sec(&mut self, val: super::vals::SwLock45sec) {
+        self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize);
+    }
+    #[doc = "Non-secure lock status. Writes are OR'd with the current value."]
+    #[inline(always)]
+    pub const fn nsec(&self) -> super::vals::SwLock45nsec {
+        let val = (self.0 >> 2usize) & 0x03;
+        super::vals::SwLock45nsec::from_bits(val as u8)
+    }
+    #[doc = "Non-secure lock status. Writes are OR'd with the current value."]
+    #[inline(always)]
+    pub fn set_nsec(&mut self, val: super::vals::SwLock45nsec) {
+        self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize);
+    }
+}
+impl Default for SwLock45 {
+    #[inline(always)]
+    fn default() -> SwLock45 {
+        SwLock45(0)
+    }
+}
+#[doc = "Software lock register for page 46. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct SwLock46(pub u32);
+impl SwLock46 {
+    #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."]
+    #[inline(always)]
+    pub const fn sec(&self) -> super::vals::SwLock46sec {
+        let val = (self.0 >> 0usize) & 0x03;
+        super::vals::SwLock46sec::from_bits(val as u8)
+    }
+    #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."]
+    #[inline(always)]
+    pub fn set_sec(&mut self, val: super::vals::SwLock46sec) {
+        self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize);
+    }
+    #[doc = "Non-secure lock status. Writes are OR'd with the current value."]
+    #[inline(always)]
+    pub const fn nsec(&self) -> super::vals::SwLock46nsec {
+        let val = (self.0 >> 2usize) & 0x03;
+        super::vals::SwLock46nsec::from_bits(val as u8)
+    }
+    #[doc = "Non-secure lock status. Writes are OR'd with the current value."]
+    #[inline(always)]
+    pub fn set_nsec(&mut self, val: super::vals::SwLock46nsec) {
+        self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize);
+    }
+}
+impl Default for SwLock46 {
+    #[inline(always)]
+    fn default() -> SwLock46 {
+        SwLock46(0)
+    }
+}
+#[doc = "Software lock register for page 47. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct SwLock47(pub u32);
+impl SwLock47 {
+    #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."]
+    #[inline(always)]
+    pub const fn sec(&self) -> super::vals::SwLock47sec {
+        let val = (self.0 >> 0usize) & 0x03;
+        super::vals::SwLock47sec::from_bits(val as u8)
+    }
+    #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."]
+    #[inline(always)]
+    pub fn set_sec(&mut self, val: super::vals::SwLock47sec) {
+        self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize);
+    }
+    #[doc = "Non-secure lock status. Writes are OR'd with the current value."]
+    #[inline(always)]
+    pub const fn nsec(&self) -> super::vals::SwLock47nsec {
+        let val = (self.0 >> 2usize) & 0x03;
+        super::vals::SwLock47nsec::from_bits(val as u8)
+    }
+    #[doc = "Non-secure lock status. Writes are OR'd with the current value."]
+    #[inline(always)]
+    pub fn set_nsec(&mut self, val: super::vals::SwLock47nsec) {
+        self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize);
+    }
+}
+impl Default for SwLock47 {
+    #[inline(always)]
+    fn default() -> SwLock47 {
+        SwLock47(0)
+    }
+}
+#[doc = "Software lock register for page 48. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct SwLock48(pub u32);
+impl SwLock48 {
+    #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."]
+    #[inline(always)]
+    pub const fn sec(&self) -> super::vals::SwLock48sec {
+        let val = (self.0 >> 0usize) & 0x03;
+        super::vals::SwLock48sec::from_bits(val as u8)
+    }
+    #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."]
+    #[inline(always)]
+    pub fn set_sec(&mut self, val: super::vals::SwLock48sec) {
+        self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize);
+    }
+    #[doc = "Non-secure lock status. Writes are OR'd with the current value."]
+    #[inline(always)]
+    pub const fn nsec(&self) -> super::vals::SwLock48nsec {
+        let val = (self.0 >> 2usize) & 0x03;
+        super::vals::SwLock48nsec::from_bits(val as u8)
+    }
+    #[doc = "Non-secure lock status. Writes are OR'd with the current value."]
+    #[inline(always)]
+    pub fn set_nsec(&mut self, val: super::vals::SwLock48nsec) {
+        self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize);
+    }
+}
+impl Default for SwLock48 {
+    #[inline(always)]
+    fn default() -> SwLock48 {
+        SwLock48(0)
+    }
+}
+#[doc = "Software lock register for page 49. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct SwLock49(pub u32);
+impl SwLock49 {
+    #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."]
+    #[inline(always)]
+    pub const fn sec(&self) -> super::vals::SwLock49sec {
+        let val = (self.0 >> 0usize) & 0x03;
+        super::vals::SwLock49sec::from_bits(val as u8)
+    }
+    #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."]
+    #[inline(always)]
+    pub fn set_sec(&mut self, val: super::vals::SwLock49sec) {
+        self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize);
+    }
+    #[doc = "Non-secure lock status. Writes are OR'd with the current value."]
+    #[inline(always)]
+    pub const fn nsec(&self) -> super::vals::SwLock49nsec {
+        let val = (self.0 >> 2usize) & 0x03;
+        super::vals::SwLock49nsec::from_bits(val as u8)
+    }
+    #[doc = "Non-secure lock status. Writes are OR'd with the current value."]
+    #[inline(always)]
+    pub fn set_nsec(&mut self, val: super::vals::SwLock49nsec) {
+        self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize);
+    }
+}
+impl Default for SwLock49 {
+    #[inline(always)]
+    fn default() -> SwLock49 {
+        SwLock49(0)
+    }
+}
+#[doc = "Software lock register for page 5. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct SwLock5(pub u32);
+impl SwLock5 {
+    #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."]
+    #[inline(always)]
+    pub const fn sec(&self) -> super::vals::SwLock5sec {
+        let val = (self.0 >> 0usize) & 0x03;
+        super::vals::SwLock5sec::from_bits(val as u8)
+    }
+    #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."]
+    #[inline(always)]
+    pub fn set_sec(&mut self, val: super::vals::SwLock5sec) {
+        self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize);
+    }
+    #[doc = "Non-secure lock status. Writes are OR'd with the current value."]
+    #[inline(always)]
+    pub const fn nsec(&self) -> super::vals::SwLock5nsec {
+        let val = (self.0 >> 2usize) & 0x03;
+        super::vals::SwLock5nsec::from_bits(val as u8)
+    }
+    #[doc = "Non-secure lock status. Writes are OR'd with the current value."]
+    #[inline(always)]
+    pub fn set_nsec(&mut self, val: super::vals::SwLock5nsec) {
+        self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize);
+    }
+}
+impl Default for SwLock5 {
+    #[inline(always)]
+    fn default() -> SwLock5 {
+        SwLock5(0)
+    }
+}
+#[doc = "Software lock register for page 50. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct SwLock50(pub u32);
+impl SwLock50 {
+    #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."]
+    #[inline(always)]
+    pub const fn sec(&self) -> super::vals::SwLock50sec {
+        let val = (self.0 >> 0usize) & 0x03;
+        super::vals::SwLock50sec::from_bits(val as u8)
+    }
+    #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."]
+    #[inline(always)]
+    pub fn set_sec(&mut self, val: super::vals::SwLock50sec) {
+        self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize);
+    }
+    #[doc = "Non-secure lock status. Writes are OR'd with the current value."]
+    #[inline(always)]
+    pub const fn nsec(&self) -> super::vals::SwLock50nsec {
+        let val = (self.0 >> 2usize) & 0x03;
+        super::vals::SwLock50nsec::from_bits(val as u8)
+    }
+    #[doc = "Non-secure lock status. Writes are OR'd with the current value."]
+    #[inline(always)]
+    pub fn set_nsec(&mut self, val: super::vals::SwLock50nsec) {
+        self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize);
+    }
+}
+impl Default for SwLock50 {
+    #[inline(always)]
+    fn default() -> SwLock50 {
+        SwLock50(0)
+    }
+}
+#[doc = "Software lock register for page 51. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct SwLock51(pub u32);
+impl SwLock51 {
+    #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."]
+    #[inline(always)]
+    pub const fn sec(&self) -> super::vals::SwLock51sec {
+        let val = (self.0 >> 0usize) & 0x03;
+        super::vals::SwLock51sec::from_bits(val as u8)
+    }
+    #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."]
+    #[inline(always)]
+    pub fn set_sec(&mut self, val: super::vals::SwLock51sec) {
+        self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize);
+    }
+    #[doc = "Non-secure lock status. Writes are OR'd with the current value."]
+    #[inline(always)]
+    pub const fn nsec(&self) -> super::vals::SwLock51nsec {
+        let val = (self.0 >> 2usize) & 0x03;
+        super::vals::SwLock51nsec::from_bits(val as u8)
+    }
+    #[doc = "Non-secure lock status. Writes are OR'd with the current value."]
+    #[inline(always)]
+    pub fn set_nsec(&mut self, val: super::vals::SwLock51nsec) {
+        self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize);
+    }
+}
+impl Default for SwLock51 {
+    #[inline(always)]
+    fn default() -> SwLock51 {
+        SwLock51(0)
+    }
+}
+#[doc = "Software lock register for page 52. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct SwLock52(pub u32);
+impl SwLock52 {
+    #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."]
+    #[inline(always)]
+    pub const fn sec(&self) -> super::vals::SwLock52sec {
+        let val = (self.0 >> 0usize) & 0x03;
+        super::vals::SwLock52sec::from_bits(val as u8)
+    }
+    #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."]
+    #[inline(always)]
+    pub fn set_sec(&mut self, val: super::vals::SwLock52sec) {
+        self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize);
+    }
+    #[doc = "Non-secure lock status. Writes are OR'd with the current value."]
+    #[inline(always)]
+    pub const fn nsec(&self) -> super::vals::SwLock52nsec {
+        let val = (self.0 >> 2usize) & 0x03;
+        super::vals::SwLock52nsec::from_bits(val as u8)
+    }
+    #[doc = "Non-secure lock status. Writes are OR'd with the current value."]
+    #[inline(always)]
+    pub fn set_nsec(&mut self, val: super::vals::SwLock52nsec) {
+        self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize);
+    }
+}
+impl Default for SwLock52 {
+    #[inline(always)]
+    fn default() -> SwLock52 {
+        SwLock52(0)
+    }
+}
+#[doc = "Software lock register for page 53. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct SwLock53(pub u32);
+impl SwLock53 {
+    #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."]
+    #[inline(always)]
+    pub const fn sec(&self) -> super::vals::SwLock53sec {
+        let val = (self.0 >> 0usize) & 0x03;
+        super::vals::SwLock53sec::from_bits(val as u8)
+    }
+    #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."]
+    #[inline(always)]
+    pub fn set_sec(&mut self, val: super::vals::SwLock53sec) {
+        self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize);
+    }
+    #[doc = "Non-secure lock status. Writes are OR'd with the current value."]
+    #[inline(always)]
+    pub const fn nsec(&self) -> super::vals::SwLock53nsec {
+        let val = (self.0 >> 2usize) & 0x03;
+        super::vals::SwLock53nsec::from_bits(val as u8)
+    }
+    #[doc = "Non-secure lock status. Writes are OR'd with the current value."]
+    #[inline(always)]
+    pub fn set_nsec(&mut self, val: super::vals::SwLock53nsec) {
+        self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize);
+    }
+}
+impl Default for SwLock53 {
+    #[inline(always)]
+    fn default() -> SwLock53 {
+        SwLock53(0)
+    }
+}
+#[doc = "Software lock register for page 54. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct SwLock54(pub u32);
+impl SwLock54 {
+    #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."]
+    #[inline(always)]
+    pub const fn sec(&self) -> super::vals::SwLock54sec {
+        let val = (self.0 >> 0usize) & 0x03;
+        super::vals::SwLock54sec::from_bits(val as u8)
+    }
+    #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."]
+    #[inline(always)]
+    pub fn set_sec(&mut self, val: super::vals::SwLock54sec) {
+        self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize);
+    }
+    #[doc = "Non-secure lock status. Writes are OR'd with the current value."]
+    #[inline(always)]
+    pub const fn nsec(&self) -> super::vals::SwLock54nsec {
+        let val = (self.0 >> 2usize) & 0x03;
+        super::vals::SwLock54nsec::from_bits(val as u8)
+    }
+    #[doc = "Non-secure lock status. Writes are OR'd with the current value."]
+    #[inline(always)]
+    pub fn set_nsec(&mut self, val: super::vals::SwLock54nsec) {
+        self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize);
+    }
+}
+impl Default for SwLock54 {
+    #[inline(always)]
+    fn default() -> SwLock54 {
+        SwLock54(0)
+    }
+}
+#[doc = "Software lock register for page 55. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct SwLock55(pub u32);
+impl SwLock55 {
+    #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."]
+    #[inline(always)]
+    pub const fn sec(&self) -> super::vals::SwLock55sec {
+        let val = (self.0 >> 0usize) & 0x03;
+        super::vals::SwLock55sec::from_bits(val as u8)
+    }
+    #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."]
+    #[inline(always)]
+    pub fn set_sec(&mut self, val: super::vals::SwLock55sec) {
+        self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize);
+    }
+    #[doc = "Non-secure lock status. Writes are OR'd with the current value."]
+    #[inline(always)]
+    pub const fn nsec(&self) -> super::vals::SwLock55nsec {
+        let val = (self.0 >> 2usize) & 0x03;
+        super::vals::SwLock55nsec::from_bits(val as u8)
+    }
+    #[doc = "Non-secure lock status. Writes are OR'd with the current value."]
+    #[inline(always)]
+    pub fn set_nsec(&mut self, val: super::vals::SwLock55nsec) {
+        self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize);
+    }
+}
+impl Default for SwLock55 {
+    #[inline(always)]
+    fn default() -> SwLock55 {
+        SwLock55(0)
+    }
+}
+#[doc = "Software lock register for page 56. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct SwLock56(pub u32);
+impl SwLock56 {
+    #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."]
+    #[inline(always)]
+    pub const fn sec(&self) -> super::vals::SwLock56sec {
+        let val = (self.0 >> 0usize) & 0x03;
+        super::vals::SwLock56sec::from_bits(val as u8)
+    }
+    #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."]
+    #[inline(always)]
+    pub fn set_sec(&mut self, val: super::vals::SwLock56sec) {
+        self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize);
+    }
+    #[doc = "Non-secure lock status. Writes are OR'd with the current value."]
+    #[inline(always)]
+    pub const fn nsec(&self) -> super::vals::SwLock56nsec {
+        let val = (self.0 >> 2usize) & 0x03;
+        super::vals::SwLock56nsec::from_bits(val as u8)
+    }
+    #[doc = "Non-secure lock status. Writes are OR'd with the current value."]
+    #[inline(always)]
+    pub fn set_nsec(&mut self, val: super::vals::SwLock56nsec) {
+        self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize);
+    }
+}
+impl Default for SwLock56 {
+    #[inline(always)]
+    fn default() -> SwLock56 {
+        SwLock56(0)
+    }
+}
+#[doc = "Software lock register for page 57. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct SwLock57(pub u32);
+impl SwLock57 {
+    #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."]
+    #[inline(always)]
+    pub const fn sec(&self) -> super::vals::SwLock57sec {
+        let val = (self.0 >> 0usize) & 0x03;
+        super::vals::SwLock57sec::from_bits(val as u8)
+    }
+    #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."]
+    #[inline(always)]
+    pub fn set_sec(&mut self, val: super::vals::SwLock57sec) {
+        self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize);
+    }
+    #[doc = "Non-secure lock status. Writes are OR'd with the current value."]
+    #[inline(always)]
+    pub const fn nsec(&self) -> super::vals::SwLock57nsec {
+        let val = (self.0 >> 2usize) & 0x03;
+        super::vals::SwLock57nsec::from_bits(val as u8)
+    }
+    #[doc = "Non-secure lock status. Writes are OR'd with the current value."]
+    #[inline(always)]
+    pub fn set_nsec(&mut self, val: super::vals::SwLock57nsec) {
+        self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize);
+    }
+}
+impl Default for SwLock57 {
+    #[inline(always)]
+    fn default() -> SwLock57 {
+        SwLock57(0)
+    }
+}
+#[doc = "Software lock register for page 58. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct SwLock58(pub u32);
+impl SwLock58 {
+    #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."]
+    #[inline(always)]
+    pub const fn sec(&self) -> super::vals::SwLock58sec {
+        let val = (self.0 >> 0usize) & 0x03;
+        super::vals::SwLock58sec::from_bits(val as u8)
+    }
+    #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."]
+    #[inline(always)]
+    pub fn set_sec(&mut self, val: super::vals::SwLock58sec) {
+        self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize);
+    }
+    #[doc = "Non-secure lock status. Writes are OR'd with the current value."]
+    #[inline(always)]
+    pub const fn nsec(&self) -> super::vals::SwLock58nsec {
+        let val = (self.0 >> 2usize) & 0x03;
+        super::vals::SwLock58nsec::from_bits(val as u8)
+    }
+    #[doc = "Non-secure lock status. Writes are OR'd with the current value."]
+    #[inline(always)]
+    pub fn set_nsec(&mut self, val: super::vals::SwLock58nsec) {
+        self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize);
+    }
+}
+impl Default for SwLock58 {
+    #[inline(always)]
+    fn default() -> SwLock58 {
+        SwLock58(0)
+    }
+}
+#[doc = "Software lock register for page 59. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct SwLock59(pub u32);
+impl SwLock59 {
+    #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."]
+    #[inline(always)]
+    pub const fn sec(&self) -> super::vals::SwLock59sec {
+        let val = (self.0 >> 0usize) & 0x03;
+        super::vals::SwLock59sec::from_bits(val as u8)
+    }
+    #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."]
+    #[inline(always)]
+    pub fn set_sec(&mut self, val: super::vals::SwLock59sec) {
+        self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize);
+    }
+    #[doc = "Non-secure lock status. Writes are OR'd with the current value."]
+    #[inline(always)]
+    pub const fn nsec(&self) -> super::vals::SwLock59nsec {
+        let val = (self.0 >> 2usize) & 0x03;
+        super::vals::SwLock59nsec::from_bits(val as u8)
+    }
+    #[doc = "Non-secure lock status. Writes are OR'd with the current value."]
+    #[inline(always)]
+    pub fn set_nsec(&mut self, val: super::vals::SwLock59nsec) {
+        self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize);
+    }
+}
+impl Default for SwLock59 {
+    #[inline(always)]
+    fn default() -> SwLock59 {
+        SwLock59(0)
+    }
+}
+#[doc = "Software lock register for page 6. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct SwLock6(pub u32);
+impl SwLock6 {
+    #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."]
+    #[inline(always)]
+    pub const fn sec(&self) -> super::vals::SwLock6sec {
+        let val = (self.0 >> 0usize) & 0x03;
+        super::vals::SwLock6sec::from_bits(val as u8)
+    }
+    #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."]
+    #[inline(always)]
+    pub fn set_sec(&mut self, val: super::vals::SwLock6sec) {
+        self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize);
+    }
+    #[doc = "Non-secure lock status. Writes are OR'd with the current value."]
+    #[inline(always)]
+    pub const fn nsec(&self) -> super::vals::SwLock6nsec {
+        let val = (self.0 >> 2usize) & 0x03;
+        super::vals::SwLock6nsec::from_bits(val as u8)
+    }
+    #[doc = "Non-secure lock status. Writes are OR'd with the current value."]
+    #[inline(always)]
+    pub fn set_nsec(&mut self, val: super::vals::SwLock6nsec) {
+        self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize);
+    }
+}
+impl Default for SwLock6 {
+    #[inline(always)]
+    fn default() -> SwLock6 {
+        SwLock6(0)
+    }
+}
+#[doc = "Software lock register for page 60. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct SwLock60(pub u32);
+impl SwLock60 {
+    #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."]
+    #[inline(always)]
+    pub const fn sec(&self) -> super::vals::SwLock60sec {
+        let val = (self.0 >> 0usize) & 0x03;
+        super::vals::SwLock60sec::from_bits(val as u8)
+    }
+    #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."]
+    #[inline(always)]
+    pub fn set_sec(&mut self, val: super::vals::SwLock60sec) {
+        self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize);
+    }
+    #[doc = "Non-secure lock status. Writes are OR'd with the current value."]
+    #[inline(always)]
+    pub const fn nsec(&self) -> super::vals::SwLock60nsec {
+        let val = (self.0 >> 2usize) & 0x03;
+        super::vals::SwLock60nsec::from_bits(val as u8)
+    }
+    #[doc = "Non-secure lock status. Writes are OR'd with the current value."]
+    #[inline(always)]
+    pub fn set_nsec(&mut self, val: super::vals::SwLock60nsec) {
+        self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize);
+    }
+}
+impl Default for SwLock60 {
+    #[inline(always)]
+    fn default() -> SwLock60 {
+        SwLock60(0)
+    }
+}
+#[doc = "Software lock register for page 61. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct SwLock61(pub u32);
+impl SwLock61 {
+    #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."]
+    #[inline(always)]
+    pub const fn sec(&self) -> super::vals::SwLock61sec {
+        let val = (self.0 >> 0usize) & 0x03;
+        super::vals::SwLock61sec::from_bits(val as u8)
+    }
+    #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."]
+    #[inline(always)]
+    pub fn set_sec(&mut self, val: super::vals::SwLock61sec) {
+        self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize);
+    }
+    #[doc = "Non-secure lock status. Writes are OR'd with the current value."]
+    #[inline(always)]
+    pub const fn nsec(&self) -> super::vals::SwLock61nsec {
+        let val = (self.0 >> 2usize) & 0x03;
+        super::vals::SwLock61nsec::from_bits(val as u8)
+    }
+    #[doc = "Non-secure lock status. Writes are OR'd with the current value."]
+    #[inline(always)]
+    pub fn set_nsec(&mut self, val: super::vals::SwLock61nsec) {
+        self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize);
+    }
+}
+impl Default for SwLock61 {
+    #[inline(always)]
+    fn default() -> SwLock61 {
+        SwLock61(0)
+    }
+}
+#[doc = "Software lock register for page 62. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct SwLock62(pub u32);
+impl SwLock62 {
+    #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."]
+    #[inline(always)]
+    pub const fn sec(&self) -> super::vals::SwLock62sec {
+        let val = (self.0 >> 0usize) & 0x03;
+        super::vals::SwLock62sec::from_bits(val as u8)
+    }
+    #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."]
+    #[inline(always)]
+    pub fn set_sec(&mut self, val: super::vals::SwLock62sec) {
+        self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize);
+    }
+    #[doc = "Non-secure lock status. Writes are OR'd with the current value."]
+    #[inline(always)]
+    pub const fn nsec(&self) -> super::vals::SwLock62nsec {
+        let val = (self.0 >> 2usize) & 0x03;
+        super::vals::SwLock62nsec::from_bits(val as u8)
+    }
+    #[doc = "Non-secure lock status. Writes are OR'd with the current value."]
+    #[inline(always)]
+    pub fn set_nsec(&mut self, val: super::vals::SwLock62nsec) {
+        self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize);
+    }
+}
+impl Default for SwLock62 {
+    #[inline(always)]
+    fn default() -> SwLock62 {
+        SwLock62(0)
+    }
+}
+#[doc = "Software lock register for page 63. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct SwLock63(pub u32);
+impl SwLock63 {
+    #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."]
+    #[inline(always)]
+    pub const fn sec(&self) -> super::vals::SwLock63sec {
+        let val = (self.0 >> 0usize) & 0x03;
+        super::vals::SwLock63sec::from_bits(val as u8)
+    }
+    #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."]
+    #[inline(always)]
+    pub fn set_sec(&mut self, val: super::vals::SwLock63sec) {
+        self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize);
+    }
+    #[doc = "Non-secure lock status. Writes are OR'd with the current value."]
+    #[inline(always)]
+    pub const fn nsec(&self) -> super::vals::SwLock63nsec {
+        let val = (self.0 >> 2usize) & 0x03;
+        super::vals::SwLock63nsec::from_bits(val as u8)
+    }
+    #[doc = "Non-secure lock status. Writes are OR'd with the current value."]
+    #[inline(always)]
+    pub fn set_nsec(&mut self, val: super::vals::SwLock63nsec) {
+        self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize);
+    }
+}
+impl Default for SwLock63 {
+    #[inline(always)]
+    fn default() -> SwLock63 {
+        SwLock63(0)
+    }
+}
+#[doc = "Software lock register for page 7. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct SwLock7(pub u32);
+impl SwLock7 {
+    #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."]
+    #[inline(always)]
+    pub const fn sec(&self) -> super::vals::SwLock7sec {
+        let val = (self.0 >> 0usize) & 0x03;
+        super::vals::SwLock7sec::from_bits(val as u8)
+    }
+    #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."]
+    #[inline(always)]
+    pub fn set_sec(&mut self, val: super::vals::SwLock7sec) {
+        self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize);
+    }
+    #[doc = "Non-secure lock status. Writes are OR'd with the current value."]
+    #[inline(always)]
+    pub const fn nsec(&self) -> super::vals::SwLock7nsec {
+        let val = (self.0 >> 2usize) & 0x03;
+        super::vals::SwLock7nsec::from_bits(val as u8)
+    }
+    #[doc = "Non-secure lock status. Writes are OR'd with the current value."]
+    #[inline(always)]
+    pub fn set_nsec(&mut self, val: super::vals::SwLock7nsec) {
+        self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize);
+    }
+}
+impl Default for SwLock7 {
+    #[inline(always)]
+    fn default() -> SwLock7 {
+        SwLock7(0)
+    }
+}
+#[doc = "Software lock register for page 8. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct SwLock8(pub u32);
+impl SwLock8 {
+    #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."]
+    #[inline(always)]
+    pub const fn sec(&self) -> super::vals::SwLock8sec {
+        let val = (self.0 >> 0usize) & 0x03;
+        super::vals::SwLock8sec::from_bits(val as u8)
+    }
+    #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."]
+    #[inline(always)]
+    pub fn set_sec(&mut self, val: super::vals::SwLock8sec) {
+        self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize);
+    }
+    #[doc = "Non-secure lock status. Writes are OR'd with the current value."]
+    #[inline(always)]
+    pub const fn nsec(&self) -> super::vals::SwLock8nsec {
+        let val = (self.0 >> 2usize) & 0x03;
+        super::vals::SwLock8nsec::from_bits(val as u8)
+    }
+    #[doc = "Non-secure lock status. Writes are OR'd with the current value."]
+    #[inline(always)]
+    pub fn set_nsec(&mut self, val: super::vals::SwLock8nsec) {
+        self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize);
+    }
+}
+impl Default for SwLock8 {
+    #[inline(always)]
+    fn default() -> SwLock8 {
+        SwLock8(0)
+    }
+}
+#[doc = "Software lock register for page 9. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct SwLock9(pub u32);
+impl SwLock9 {
+    #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."]
+    #[inline(always)]
+    pub const fn sec(&self) -> super::vals::SwLock9sec {
+        let val = (self.0 >> 0usize) & 0x03;
+        super::vals::SwLock9sec::from_bits(val as u8)
+    }
+    #[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."]
+    #[inline(always)]
+    pub fn set_sec(&mut self, val: super::vals::SwLock9sec) {
+        self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize);
+    }
+    #[doc = "Non-secure lock status. Writes are OR'd with the current value."]
+    #[inline(always)]
+    pub const fn nsec(&self) -> super::vals::SwLock9nsec {
+        let val = (self.0 >> 2usize) & 0x03;
+        super::vals::SwLock9nsec::from_bits(val as u8)
+    }
+    #[doc = "Non-secure lock status. Writes are OR'd with the current value."]
+    #[inline(always)]
+    pub fn set_nsec(&mut self, val: super::vals::SwLock9nsec) {
+        self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize);
+    }
+}
+impl Default for SwLock9 {
+    #[inline(always)]
+    fn default() -> SwLock9 {
+        SwLock9(0)
+    }
+}
+#[doc = "Controls for APB data read interface (USER interface)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Usr(pub u32);
+impl Usr {
+    #[doc = "1 enables USER interface; 0 disables USER interface (enables SBPI). This bit must be cleared before performing any SBPI access, such as when programming the OTP. The APB data read interface (USER interface) will be inaccessible during this time, and will return a bus error if any read is attempted."]
+    #[inline(always)]
+    pub const fn dctrl(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "1 enables USER interface; 0 disables USER interface (enables SBPI). This bit must be cleared before performing any SBPI access, such as when programming the OTP. The APB data read interface (USER interface) will be inaccessible during this time, and will return a bus error if any read is attempted."]
+    #[inline(always)]
+    pub fn set_dctrl(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[doc = "Power-down; 1 disables current reference. Must be 0 to read data from the OTP."]
+    #[inline(always)]
+    pub const fn pd(&self) -> bool {
+        let val = (self.0 >> 4usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Power-down; 1 disables current reference. Must be 0 to read data from the OTP."]
+    #[inline(always)]
+    pub fn set_pd(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
+    }
+}
+impl Default for Usr {
+    #[inline(always)]
+    fn default() -> Usr {
+        Usr(0)
+    }
+}
diff --git a/src/rp2350/otp/vals.rs b/src/rp2350/otp/vals.rs
new file mode 100644
index 00000000..315ba766
--- /dev/null
+++ b/src/rp2350/otp/vals.rs
@@ -0,0 +1,3960 @@
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum ArchselCore0 {
+    #[doc = "Switch core 0 to Arm (Cortex-M33)"]
+    ARM = 0,
+    #[doc = "Switch core 0 to RISC-V (Hazard3)"]
+    RISCV = 0x01,
+}
+impl ArchselCore0 {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> ArchselCore0 {
+        unsafe { core::mem::transmute(val & 0x01) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for ArchselCore0 {
+    #[inline(always)]
+    fn from(val: u8) -> ArchselCore0 {
+        ArchselCore0::from_bits(val)
+    }
+}
+impl From<ArchselCore0> for u8 {
+    #[inline(always)]
+    fn from(val: ArchselCore0) -> u8 {
+        ArchselCore0::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum ArchselCore1 {
+    #[doc = "Switch core 1 to Arm (Cortex-M33)"]
+    ARM = 0,
+    #[doc = "Switch core 1 to RISC-V (Hazard3)"]
+    RISCV = 0x01,
+}
+impl ArchselCore1 {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> ArchselCore1 {
+        unsafe { core::mem::transmute(val & 0x01) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for ArchselCore1 {
+    #[inline(always)]
+    fn from(val: u8) -> ArchselCore1 {
+        ArchselCore1::from_bits(val)
+    }
+}
+impl From<ArchselCore1> for u8 {
+    #[inline(always)]
+    fn from(val: ArchselCore1) -> u8 {
+        ArchselCore1::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum ArchselStatusCore0 {
+    #[doc = "Core 0 is currently Arm (Cortex-M33)"]
+    ARM = 0,
+    #[doc = "Core 0 is currently RISC-V (Hazard3)"]
+    RISCV = 0x01,
+}
+impl ArchselStatusCore0 {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> ArchselStatusCore0 {
+        unsafe { core::mem::transmute(val & 0x01) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for ArchselStatusCore0 {
+    #[inline(always)]
+    fn from(val: u8) -> ArchselStatusCore0 {
+        ArchselStatusCore0::from_bits(val)
+    }
+}
+impl From<ArchselStatusCore0> for u8 {
+    #[inline(always)]
+    fn from(val: ArchselStatusCore0) -> u8 {
+        ArchselStatusCore0::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum ArchselStatusCore1 {
+    #[doc = "Core 1 is currently Arm (Cortex-M33)"]
+    ARM = 0,
+    #[doc = "Core 1 is currently RISC-V (Hazard3)"]
+    RISCV = 0x01,
+}
+impl ArchselStatusCore1 {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> ArchselStatusCore1 {
+        unsafe { core::mem::transmute(val & 0x01) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for ArchselStatusCore1 {
+    #[inline(always)]
+    fn from(val: u8) -> ArchselStatusCore1 {
+        ArchselStatusCore1::from_bits(val)
+    }
+}
+impl From<ArchselStatusCore1> for u8 {
+    #[inline(always)]
+    fn from(val: ArchselStatusCore1) -> u8 {
+        ArchselStatusCore1::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum SwLock0nsec {
+    READ_WRITE = 0,
+    READ_ONLY = 0x01,
+    _RESERVED_2 = 0x02,
+    INACCESSIBLE = 0x03,
+}
+impl SwLock0nsec {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> SwLock0nsec {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for SwLock0nsec {
+    #[inline(always)]
+    fn from(val: u8) -> SwLock0nsec {
+        SwLock0nsec::from_bits(val)
+    }
+}
+impl From<SwLock0nsec> for u8 {
+    #[inline(always)]
+    fn from(val: SwLock0nsec) -> u8 {
+        SwLock0nsec::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum SwLock0sec {
+    READ_WRITE = 0,
+    READ_ONLY = 0x01,
+    _RESERVED_2 = 0x02,
+    INACCESSIBLE = 0x03,
+}
+impl SwLock0sec {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> SwLock0sec {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for SwLock0sec {
+    #[inline(always)]
+    fn from(val: u8) -> SwLock0sec {
+        SwLock0sec::from_bits(val)
+    }
+}
+impl From<SwLock0sec> for u8 {
+    #[inline(always)]
+    fn from(val: SwLock0sec) -> u8 {
+        SwLock0sec::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum SwLock10nsec {
+    READ_WRITE = 0,
+    READ_ONLY = 0x01,
+    _RESERVED_2 = 0x02,
+    INACCESSIBLE = 0x03,
+}
+impl SwLock10nsec {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> SwLock10nsec {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for SwLock10nsec {
+    #[inline(always)]
+    fn from(val: u8) -> SwLock10nsec {
+        SwLock10nsec::from_bits(val)
+    }
+}
+impl From<SwLock10nsec> for u8 {
+    #[inline(always)]
+    fn from(val: SwLock10nsec) -> u8 {
+        SwLock10nsec::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum SwLock10sec {
+    READ_WRITE = 0,
+    READ_ONLY = 0x01,
+    _RESERVED_2 = 0x02,
+    INACCESSIBLE = 0x03,
+}
+impl SwLock10sec {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> SwLock10sec {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for SwLock10sec {
+    #[inline(always)]
+    fn from(val: u8) -> SwLock10sec {
+        SwLock10sec::from_bits(val)
+    }
+}
+impl From<SwLock10sec> for u8 {
+    #[inline(always)]
+    fn from(val: SwLock10sec) -> u8 {
+        SwLock10sec::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum SwLock11nsec {
+    READ_WRITE = 0,
+    READ_ONLY = 0x01,
+    _RESERVED_2 = 0x02,
+    INACCESSIBLE = 0x03,
+}
+impl SwLock11nsec {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> SwLock11nsec {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for SwLock11nsec {
+    #[inline(always)]
+    fn from(val: u8) -> SwLock11nsec {
+        SwLock11nsec::from_bits(val)
+    }
+}
+impl From<SwLock11nsec> for u8 {
+    #[inline(always)]
+    fn from(val: SwLock11nsec) -> u8 {
+        SwLock11nsec::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum SwLock11sec {
+    READ_WRITE = 0,
+    READ_ONLY = 0x01,
+    _RESERVED_2 = 0x02,
+    INACCESSIBLE = 0x03,
+}
+impl SwLock11sec {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> SwLock11sec {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for SwLock11sec {
+    #[inline(always)]
+    fn from(val: u8) -> SwLock11sec {
+        SwLock11sec::from_bits(val)
+    }
+}
+impl From<SwLock11sec> for u8 {
+    #[inline(always)]
+    fn from(val: SwLock11sec) -> u8 {
+        SwLock11sec::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum SwLock12nsec {
+    READ_WRITE = 0,
+    READ_ONLY = 0x01,
+    _RESERVED_2 = 0x02,
+    INACCESSIBLE = 0x03,
+}
+impl SwLock12nsec {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> SwLock12nsec {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for SwLock12nsec {
+    #[inline(always)]
+    fn from(val: u8) -> SwLock12nsec {
+        SwLock12nsec::from_bits(val)
+    }
+}
+impl From<SwLock12nsec> for u8 {
+    #[inline(always)]
+    fn from(val: SwLock12nsec) -> u8 {
+        SwLock12nsec::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum SwLock12sec {
+    READ_WRITE = 0,
+    READ_ONLY = 0x01,
+    _RESERVED_2 = 0x02,
+    INACCESSIBLE = 0x03,
+}
+impl SwLock12sec {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> SwLock12sec {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for SwLock12sec {
+    #[inline(always)]
+    fn from(val: u8) -> SwLock12sec {
+        SwLock12sec::from_bits(val)
+    }
+}
+impl From<SwLock12sec> for u8 {
+    #[inline(always)]
+    fn from(val: SwLock12sec) -> u8 {
+        SwLock12sec::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum SwLock13nsec {
+    READ_WRITE = 0,
+    READ_ONLY = 0x01,
+    _RESERVED_2 = 0x02,
+    INACCESSIBLE = 0x03,
+}
+impl SwLock13nsec {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> SwLock13nsec {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for SwLock13nsec {
+    #[inline(always)]
+    fn from(val: u8) -> SwLock13nsec {
+        SwLock13nsec::from_bits(val)
+    }
+}
+impl From<SwLock13nsec> for u8 {
+    #[inline(always)]
+    fn from(val: SwLock13nsec) -> u8 {
+        SwLock13nsec::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum SwLock13sec {
+    READ_WRITE = 0,
+    READ_ONLY = 0x01,
+    _RESERVED_2 = 0x02,
+    INACCESSIBLE = 0x03,
+}
+impl SwLock13sec {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> SwLock13sec {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for SwLock13sec {
+    #[inline(always)]
+    fn from(val: u8) -> SwLock13sec {
+        SwLock13sec::from_bits(val)
+    }
+}
+impl From<SwLock13sec> for u8 {
+    #[inline(always)]
+    fn from(val: SwLock13sec) -> u8 {
+        SwLock13sec::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum SwLock14nsec {
+    READ_WRITE = 0,
+    READ_ONLY = 0x01,
+    _RESERVED_2 = 0x02,
+    INACCESSIBLE = 0x03,
+}
+impl SwLock14nsec {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> SwLock14nsec {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for SwLock14nsec {
+    #[inline(always)]
+    fn from(val: u8) -> SwLock14nsec {
+        SwLock14nsec::from_bits(val)
+    }
+}
+impl From<SwLock14nsec> for u8 {
+    #[inline(always)]
+    fn from(val: SwLock14nsec) -> u8 {
+        SwLock14nsec::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum SwLock14sec {
+    READ_WRITE = 0,
+    READ_ONLY = 0x01,
+    _RESERVED_2 = 0x02,
+    INACCESSIBLE = 0x03,
+}
+impl SwLock14sec {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> SwLock14sec {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for SwLock14sec {
+    #[inline(always)]
+    fn from(val: u8) -> SwLock14sec {
+        SwLock14sec::from_bits(val)
+    }
+}
+impl From<SwLock14sec> for u8 {
+    #[inline(always)]
+    fn from(val: SwLock14sec) -> u8 {
+        SwLock14sec::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum SwLock15nsec {
+    READ_WRITE = 0,
+    READ_ONLY = 0x01,
+    _RESERVED_2 = 0x02,
+    INACCESSIBLE = 0x03,
+}
+impl SwLock15nsec {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> SwLock15nsec {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for SwLock15nsec {
+    #[inline(always)]
+    fn from(val: u8) -> SwLock15nsec {
+        SwLock15nsec::from_bits(val)
+    }
+}
+impl From<SwLock15nsec> for u8 {
+    #[inline(always)]
+    fn from(val: SwLock15nsec) -> u8 {
+        SwLock15nsec::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum SwLock15sec {
+    READ_WRITE = 0,
+    READ_ONLY = 0x01,
+    _RESERVED_2 = 0x02,
+    INACCESSIBLE = 0x03,
+}
+impl SwLock15sec {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> SwLock15sec {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for SwLock15sec {
+    #[inline(always)]
+    fn from(val: u8) -> SwLock15sec {
+        SwLock15sec::from_bits(val)
+    }
+}
+impl From<SwLock15sec> for u8 {
+    #[inline(always)]
+    fn from(val: SwLock15sec) -> u8 {
+        SwLock15sec::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum SwLock16nsec {
+    READ_WRITE = 0,
+    READ_ONLY = 0x01,
+    _RESERVED_2 = 0x02,
+    INACCESSIBLE = 0x03,
+}
+impl SwLock16nsec {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> SwLock16nsec {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for SwLock16nsec {
+    #[inline(always)]
+    fn from(val: u8) -> SwLock16nsec {
+        SwLock16nsec::from_bits(val)
+    }
+}
+impl From<SwLock16nsec> for u8 {
+    #[inline(always)]
+    fn from(val: SwLock16nsec) -> u8 {
+        SwLock16nsec::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum SwLock16sec {
+    READ_WRITE = 0,
+    READ_ONLY = 0x01,
+    _RESERVED_2 = 0x02,
+    INACCESSIBLE = 0x03,
+}
+impl SwLock16sec {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> SwLock16sec {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for SwLock16sec {
+    #[inline(always)]
+    fn from(val: u8) -> SwLock16sec {
+        SwLock16sec::from_bits(val)
+    }
+}
+impl From<SwLock16sec> for u8 {
+    #[inline(always)]
+    fn from(val: SwLock16sec) -> u8 {
+        SwLock16sec::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum SwLock17nsec {
+    READ_WRITE = 0,
+    READ_ONLY = 0x01,
+    _RESERVED_2 = 0x02,
+    INACCESSIBLE = 0x03,
+}
+impl SwLock17nsec {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> SwLock17nsec {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for SwLock17nsec {
+    #[inline(always)]
+    fn from(val: u8) -> SwLock17nsec {
+        SwLock17nsec::from_bits(val)
+    }
+}
+impl From<SwLock17nsec> for u8 {
+    #[inline(always)]
+    fn from(val: SwLock17nsec) -> u8 {
+        SwLock17nsec::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum SwLock17sec {
+    READ_WRITE = 0,
+    READ_ONLY = 0x01,
+    _RESERVED_2 = 0x02,
+    INACCESSIBLE = 0x03,
+}
+impl SwLock17sec {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> SwLock17sec {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for SwLock17sec {
+    #[inline(always)]
+    fn from(val: u8) -> SwLock17sec {
+        SwLock17sec::from_bits(val)
+    }
+}
+impl From<SwLock17sec> for u8 {
+    #[inline(always)]
+    fn from(val: SwLock17sec) -> u8 {
+        SwLock17sec::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum SwLock18nsec {
+    READ_WRITE = 0,
+    READ_ONLY = 0x01,
+    _RESERVED_2 = 0x02,
+    INACCESSIBLE = 0x03,
+}
+impl SwLock18nsec {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> SwLock18nsec {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for SwLock18nsec {
+    #[inline(always)]
+    fn from(val: u8) -> SwLock18nsec {
+        SwLock18nsec::from_bits(val)
+    }
+}
+impl From<SwLock18nsec> for u8 {
+    #[inline(always)]
+    fn from(val: SwLock18nsec) -> u8 {
+        SwLock18nsec::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum SwLock18sec {
+    READ_WRITE = 0,
+    READ_ONLY = 0x01,
+    _RESERVED_2 = 0x02,
+    INACCESSIBLE = 0x03,
+}
+impl SwLock18sec {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> SwLock18sec {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for SwLock18sec {
+    #[inline(always)]
+    fn from(val: u8) -> SwLock18sec {
+        SwLock18sec::from_bits(val)
+    }
+}
+impl From<SwLock18sec> for u8 {
+    #[inline(always)]
+    fn from(val: SwLock18sec) -> u8 {
+        SwLock18sec::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum SwLock19nsec {
+    READ_WRITE = 0,
+    READ_ONLY = 0x01,
+    _RESERVED_2 = 0x02,
+    INACCESSIBLE = 0x03,
+}
+impl SwLock19nsec {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> SwLock19nsec {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for SwLock19nsec {
+    #[inline(always)]
+    fn from(val: u8) -> SwLock19nsec {
+        SwLock19nsec::from_bits(val)
+    }
+}
+impl From<SwLock19nsec> for u8 {
+    #[inline(always)]
+    fn from(val: SwLock19nsec) -> u8 {
+        SwLock19nsec::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum SwLock19sec {
+    READ_WRITE = 0,
+    READ_ONLY = 0x01,
+    _RESERVED_2 = 0x02,
+    INACCESSIBLE = 0x03,
+}
+impl SwLock19sec {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> SwLock19sec {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for SwLock19sec {
+    #[inline(always)]
+    fn from(val: u8) -> SwLock19sec {
+        SwLock19sec::from_bits(val)
+    }
+}
+impl From<SwLock19sec> for u8 {
+    #[inline(always)]
+    fn from(val: SwLock19sec) -> u8 {
+        SwLock19sec::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum SwLock1nsec {
+    READ_WRITE = 0,
+    READ_ONLY = 0x01,
+    _RESERVED_2 = 0x02,
+    INACCESSIBLE = 0x03,
+}
+impl SwLock1nsec {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> SwLock1nsec {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for SwLock1nsec {
+    #[inline(always)]
+    fn from(val: u8) -> SwLock1nsec {
+        SwLock1nsec::from_bits(val)
+    }
+}
+impl From<SwLock1nsec> for u8 {
+    #[inline(always)]
+    fn from(val: SwLock1nsec) -> u8 {
+        SwLock1nsec::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum SwLock1sec {
+    READ_WRITE = 0,
+    READ_ONLY = 0x01,
+    _RESERVED_2 = 0x02,
+    INACCESSIBLE = 0x03,
+}
+impl SwLock1sec {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> SwLock1sec {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for SwLock1sec {
+    #[inline(always)]
+    fn from(val: u8) -> SwLock1sec {
+        SwLock1sec::from_bits(val)
+    }
+}
+impl From<SwLock1sec> for u8 {
+    #[inline(always)]
+    fn from(val: SwLock1sec) -> u8 {
+        SwLock1sec::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum SwLock20nsec {
+    READ_WRITE = 0,
+    READ_ONLY = 0x01,
+    _RESERVED_2 = 0x02,
+    INACCESSIBLE = 0x03,
+}
+impl SwLock20nsec {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> SwLock20nsec {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for SwLock20nsec {
+    #[inline(always)]
+    fn from(val: u8) -> SwLock20nsec {
+        SwLock20nsec::from_bits(val)
+    }
+}
+impl From<SwLock20nsec> for u8 {
+    #[inline(always)]
+    fn from(val: SwLock20nsec) -> u8 {
+        SwLock20nsec::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum SwLock20sec {
+    READ_WRITE = 0,
+    READ_ONLY = 0x01,
+    _RESERVED_2 = 0x02,
+    INACCESSIBLE = 0x03,
+}
+impl SwLock20sec {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> SwLock20sec {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for SwLock20sec {
+    #[inline(always)]
+    fn from(val: u8) -> SwLock20sec {
+        SwLock20sec::from_bits(val)
+    }
+}
+impl From<SwLock20sec> for u8 {
+    #[inline(always)]
+    fn from(val: SwLock20sec) -> u8 {
+        SwLock20sec::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum SwLock21nsec {
+    READ_WRITE = 0,
+    READ_ONLY = 0x01,
+    _RESERVED_2 = 0x02,
+    INACCESSIBLE = 0x03,
+}
+impl SwLock21nsec {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> SwLock21nsec {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for SwLock21nsec {
+    #[inline(always)]
+    fn from(val: u8) -> SwLock21nsec {
+        SwLock21nsec::from_bits(val)
+    }
+}
+impl From<SwLock21nsec> for u8 {
+    #[inline(always)]
+    fn from(val: SwLock21nsec) -> u8 {
+        SwLock21nsec::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum SwLock21sec {
+    READ_WRITE = 0,
+    READ_ONLY = 0x01,
+    _RESERVED_2 = 0x02,
+    INACCESSIBLE = 0x03,
+}
+impl SwLock21sec {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> SwLock21sec {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for SwLock21sec {
+    #[inline(always)]
+    fn from(val: u8) -> SwLock21sec {
+        SwLock21sec::from_bits(val)
+    }
+}
+impl From<SwLock21sec> for u8 {
+    #[inline(always)]
+    fn from(val: SwLock21sec) -> u8 {
+        SwLock21sec::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum SwLock22nsec {
+    READ_WRITE = 0,
+    READ_ONLY = 0x01,
+    _RESERVED_2 = 0x02,
+    INACCESSIBLE = 0x03,
+}
+impl SwLock22nsec {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> SwLock22nsec {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for SwLock22nsec {
+    #[inline(always)]
+    fn from(val: u8) -> SwLock22nsec {
+        SwLock22nsec::from_bits(val)
+    }
+}
+impl From<SwLock22nsec> for u8 {
+    #[inline(always)]
+    fn from(val: SwLock22nsec) -> u8 {
+        SwLock22nsec::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum SwLock22sec {
+    READ_WRITE = 0,
+    READ_ONLY = 0x01,
+    _RESERVED_2 = 0x02,
+    INACCESSIBLE = 0x03,
+}
+impl SwLock22sec {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> SwLock22sec {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for SwLock22sec {
+    #[inline(always)]
+    fn from(val: u8) -> SwLock22sec {
+        SwLock22sec::from_bits(val)
+    }
+}
+impl From<SwLock22sec> for u8 {
+    #[inline(always)]
+    fn from(val: SwLock22sec) -> u8 {
+        SwLock22sec::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum SwLock23nsec {
+    READ_WRITE = 0,
+    READ_ONLY = 0x01,
+    _RESERVED_2 = 0x02,
+    INACCESSIBLE = 0x03,
+}
+impl SwLock23nsec {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> SwLock23nsec {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for SwLock23nsec {
+    #[inline(always)]
+    fn from(val: u8) -> SwLock23nsec {
+        SwLock23nsec::from_bits(val)
+    }
+}
+impl From<SwLock23nsec> for u8 {
+    #[inline(always)]
+    fn from(val: SwLock23nsec) -> u8 {
+        SwLock23nsec::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum SwLock23sec {
+    READ_WRITE = 0,
+    READ_ONLY = 0x01,
+    _RESERVED_2 = 0x02,
+    INACCESSIBLE = 0x03,
+}
+impl SwLock23sec {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> SwLock23sec {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for SwLock23sec {
+    #[inline(always)]
+    fn from(val: u8) -> SwLock23sec {
+        SwLock23sec::from_bits(val)
+    }
+}
+impl From<SwLock23sec> for u8 {
+    #[inline(always)]
+    fn from(val: SwLock23sec) -> u8 {
+        SwLock23sec::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum SwLock24nsec {
+    READ_WRITE = 0,
+    READ_ONLY = 0x01,
+    _RESERVED_2 = 0x02,
+    INACCESSIBLE = 0x03,
+}
+impl SwLock24nsec {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> SwLock24nsec {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for SwLock24nsec {
+    #[inline(always)]
+    fn from(val: u8) -> SwLock24nsec {
+        SwLock24nsec::from_bits(val)
+    }
+}
+impl From<SwLock24nsec> for u8 {
+    #[inline(always)]
+    fn from(val: SwLock24nsec) -> u8 {
+        SwLock24nsec::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum SwLock24sec {
+    READ_WRITE = 0,
+    READ_ONLY = 0x01,
+    _RESERVED_2 = 0x02,
+    INACCESSIBLE = 0x03,
+}
+impl SwLock24sec {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> SwLock24sec {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for SwLock24sec {
+    #[inline(always)]
+    fn from(val: u8) -> SwLock24sec {
+        SwLock24sec::from_bits(val)
+    }
+}
+impl From<SwLock24sec> for u8 {
+    #[inline(always)]
+    fn from(val: SwLock24sec) -> u8 {
+        SwLock24sec::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum SwLock25nsec {
+    READ_WRITE = 0,
+    READ_ONLY = 0x01,
+    _RESERVED_2 = 0x02,
+    INACCESSIBLE = 0x03,
+}
+impl SwLock25nsec {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> SwLock25nsec {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for SwLock25nsec {
+    #[inline(always)]
+    fn from(val: u8) -> SwLock25nsec {
+        SwLock25nsec::from_bits(val)
+    }
+}
+impl From<SwLock25nsec> for u8 {
+    #[inline(always)]
+    fn from(val: SwLock25nsec) -> u8 {
+        SwLock25nsec::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum SwLock25sec {
+    READ_WRITE = 0,
+    READ_ONLY = 0x01,
+    _RESERVED_2 = 0x02,
+    INACCESSIBLE = 0x03,
+}
+impl SwLock25sec {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> SwLock25sec {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for SwLock25sec {
+    #[inline(always)]
+    fn from(val: u8) -> SwLock25sec {
+        SwLock25sec::from_bits(val)
+    }
+}
+impl From<SwLock25sec> for u8 {
+    #[inline(always)]
+    fn from(val: SwLock25sec) -> u8 {
+        SwLock25sec::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum SwLock26nsec {
+    READ_WRITE = 0,
+    READ_ONLY = 0x01,
+    _RESERVED_2 = 0x02,
+    INACCESSIBLE = 0x03,
+}
+impl SwLock26nsec {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> SwLock26nsec {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for SwLock26nsec {
+    #[inline(always)]
+    fn from(val: u8) -> SwLock26nsec {
+        SwLock26nsec::from_bits(val)
+    }
+}
+impl From<SwLock26nsec> for u8 {
+    #[inline(always)]
+    fn from(val: SwLock26nsec) -> u8 {
+        SwLock26nsec::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum SwLock26sec {
+    READ_WRITE = 0,
+    READ_ONLY = 0x01,
+    _RESERVED_2 = 0x02,
+    INACCESSIBLE = 0x03,
+}
+impl SwLock26sec {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> SwLock26sec {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for SwLock26sec {
+    #[inline(always)]
+    fn from(val: u8) -> SwLock26sec {
+        SwLock26sec::from_bits(val)
+    }
+}
+impl From<SwLock26sec> for u8 {
+    #[inline(always)]
+    fn from(val: SwLock26sec) -> u8 {
+        SwLock26sec::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum SwLock27nsec {
+    READ_WRITE = 0,
+    READ_ONLY = 0x01,
+    _RESERVED_2 = 0x02,
+    INACCESSIBLE = 0x03,
+}
+impl SwLock27nsec {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> SwLock27nsec {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for SwLock27nsec {
+    #[inline(always)]
+    fn from(val: u8) -> SwLock27nsec {
+        SwLock27nsec::from_bits(val)
+    }
+}
+impl From<SwLock27nsec> for u8 {
+    #[inline(always)]
+    fn from(val: SwLock27nsec) -> u8 {
+        SwLock27nsec::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum SwLock27sec {
+    READ_WRITE = 0,
+    READ_ONLY = 0x01,
+    _RESERVED_2 = 0x02,
+    INACCESSIBLE = 0x03,
+}
+impl SwLock27sec {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> SwLock27sec {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for SwLock27sec {
+    #[inline(always)]
+    fn from(val: u8) -> SwLock27sec {
+        SwLock27sec::from_bits(val)
+    }
+}
+impl From<SwLock27sec> for u8 {
+    #[inline(always)]
+    fn from(val: SwLock27sec) -> u8 {
+        SwLock27sec::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum SwLock28nsec {
+    READ_WRITE = 0,
+    READ_ONLY = 0x01,
+    _RESERVED_2 = 0x02,
+    INACCESSIBLE = 0x03,
+}
+impl SwLock28nsec {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> SwLock28nsec {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for SwLock28nsec {
+    #[inline(always)]
+    fn from(val: u8) -> SwLock28nsec {
+        SwLock28nsec::from_bits(val)
+    }
+}
+impl From<SwLock28nsec> for u8 {
+    #[inline(always)]
+    fn from(val: SwLock28nsec) -> u8 {
+        SwLock28nsec::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum SwLock28sec {
+    READ_WRITE = 0,
+    READ_ONLY = 0x01,
+    _RESERVED_2 = 0x02,
+    INACCESSIBLE = 0x03,
+}
+impl SwLock28sec {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> SwLock28sec {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for SwLock28sec {
+    #[inline(always)]
+    fn from(val: u8) -> SwLock28sec {
+        SwLock28sec::from_bits(val)
+    }
+}
+impl From<SwLock28sec> for u8 {
+    #[inline(always)]
+    fn from(val: SwLock28sec) -> u8 {
+        SwLock28sec::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum SwLock29nsec {
+    READ_WRITE = 0,
+    READ_ONLY = 0x01,
+    _RESERVED_2 = 0x02,
+    INACCESSIBLE = 0x03,
+}
+impl SwLock29nsec {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> SwLock29nsec {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for SwLock29nsec {
+    #[inline(always)]
+    fn from(val: u8) -> SwLock29nsec {
+        SwLock29nsec::from_bits(val)
+    }
+}
+impl From<SwLock29nsec> for u8 {
+    #[inline(always)]
+    fn from(val: SwLock29nsec) -> u8 {
+        SwLock29nsec::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum SwLock29sec {
+    READ_WRITE = 0,
+    READ_ONLY = 0x01,
+    _RESERVED_2 = 0x02,
+    INACCESSIBLE = 0x03,
+}
+impl SwLock29sec {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> SwLock29sec {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for SwLock29sec {
+    #[inline(always)]
+    fn from(val: u8) -> SwLock29sec {
+        SwLock29sec::from_bits(val)
+    }
+}
+impl From<SwLock29sec> for u8 {
+    #[inline(always)]
+    fn from(val: SwLock29sec) -> u8 {
+        SwLock29sec::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum SwLock2nsec {
+    READ_WRITE = 0,
+    READ_ONLY = 0x01,
+    _RESERVED_2 = 0x02,
+    INACCESSIBLE = 0x03,
+}
+impl SwLock2nsec {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> SwLock2nsec {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for SwLock2nsec {
+    #[inline(always)]
+    fn from(val: u8) -> SwLock2nsec {
+        SwLock2nsec::from_bits(val)
+    }
+}
+impl From<SwLock2nsec> for u8 {
+    #[inline(always)]
+    fn from(val: SwLock2nsec) -> u8 {
+        SwLock2nsec::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum SwLock2sec {
+    READ_WRITE = 0,
+    READ_ONLY = 0x01,
+    _RESERVED_2 = 0x02,
+    INACCESSIBLE = 0x03,
+}
+impl SwLock2sec {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> SwLock2sec {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for SwLock2sec {
+    #[inline(always)]
+    fn from(val: u8) -> SwLock2sec {
+        SwLock2sec::from_bits(val)
+    }
+}
+impl From<SwLock2sec> for u8 {
+    #[inline(always)]
+    fn from(val: SwLock2sec) -> u8 {
+        SwLock2sec::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum SwLock30nsec {
+    READ_WRITE = 0,
+    READ_ONLY = 0x01,
+    _RESERVED_2 = 0x02,
+    INACCESSIBLE = 0x03,
+}
+impl SwLock30nsec {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> SwLock30nsec {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for SwLock30nsec {
+    #[inline(always)]
+    fn from(val: u8) -> SwLock30nsec {
+        SwLock30nsec::from_bits(val)
+    }
+}
+impl From<SwLock30nsec> for u8 {
+    #[inline(always)]
+    fn from(val: SwLock30nsec) -> u8 {
+        SwLock30nsec::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum SwLock30sec {
+    READ_WRITE = 0,
+    READ_ONLY = 0x01,
+    _RESERVED_2 = 0x02,
+    INACCESSIBLE = 0x03,
+}
+impl SwLock30sec {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> SwLock30sec {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for SwLock30sec {
+    #[inline(always)]
+    fn from(val: u8) -> SwLock30sec {
+        SwLock30sec::from_bits(val)
+    }
+}
+impl From<SwLock30sec> for u8 {
+    #[inline(always)]
+    fn from(val: SwLock30sec) -> u8 {
+        SwLock30sec::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum SwLock31nsec {
+    READ_WRITE = 0,
+    READ_ONLY = 0x01,
+    _RESERVED_2 = 0x02,
+    INACCESSIBLE = 0x03,
+}
+impl SwLock31nsec {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> SwLock31nsec {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for SwLock31nsec {
+    #[inline(always)]
+    fn from(val: u8) -> SwLock31nsec {
+        SwLock31nsec::from_bits(val)
+    }
+}
+impl From<SwLock31nsec> for u8 {
+    #[inline(always)]
+    fn from(val: SwLock31nsec) -> u8 {
+        SwLock31nsec::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum SwLock31sec {
+    READ_WRITE = 0,
+    READ_ONLY = 0x01,
+    _RESERVED_2 = 0x02,
+    INACCESSIBLE = 0x03,
+}
+impl SwLock31sec {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> SwLock31sec {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for SwLock31sec {
+    #[inline(always)]
+    fn from(val: u8) -> SwLock31sec {
+        SwLock31sec::from_bits(val)
+    }
+}
+impl From<SwLock31sec> for u8 {
+    #[inline(always)]
+    fn from(val: SwLock31sec) -> u8 {
+        SwLock31sec::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum SwLock32nsec {
+    READ_WRITE = 0,
+    READ_ONLY = 0x01,
+    _RESERVED_2 = 0x02,
+    INACCESSIBLE = 0x03,
+}
+impl SwLock32nsec {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> SwLock32nsec {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for SwLock32nsec {
+    #[inline(always)]
+    fn from(val: u8) -> SwLock32nsec {
+        SwLock32nsec::from_bits(val)
+    }
+}
+impl From<SwLock32nsec> for u8 {
+    #[inline(always)]
+    fn from(val: SwLock32nsec) -> u8 {
+        SwLock32nsec::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum SwLock32sec {
+    READ_WRITE = 0,
+    READ_ONLY = 0x01,
+    _RESERVED_2 = 0x02,
+    INACCESSIBLE = 0x03,
+}
+impl SwLock32sec {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> SwLock32sec {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for SwLock32sec {
+    #[inline(always)]
+    fn from(val: u8) -> SwLock32sec {
+        SwLock32sec::from_bits(val)
+    }
+}
+impl From<SwLock32sec> for u8 {
+    #[inline(always)]
+    fn from(val: SwLock32sec) -> u8 {
+        SwLock32sec::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum SwLock33nsec {
+    READ_WRITE = 0,
+    READ_ONLY = 0x01,
+    _RESERVED_2 = 0x02,
+    INACCESSIBLE = 0x03,
+}
+impl SwLock33nsec {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> SwLock33nsec {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for SwLock33nsec {
+    #[inline(always)]
+    fn from(val: u8) -> SwLock33nsec {
+        SwLock33nsec::from_bits(val)
+    }
+}
+impl From<SwLock33nsec> for u8 {
+    #[inline(always)]
+    fn from(val: SwLock33nsec) -> u8 {
+        SwLock33nsec::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum SwLock33sec {
+    READ_WRITE = 0,
+    READ_ONLY = 0x01,
+    _RESERVED_2 = 0x02,
+    INACCESSIBLE = 0x03,
+}
+impl SwLock33sec {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> SwLock33sec {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for SwLock33sec {
+    #[inline(always)]
+    fn from(val: u8) -> SwLock33sec {
+        SwLock33sec::from_bits(val)
+    }
+}
+impl From<SwLock33sec> for u8 {
+    #[inline(always)]
+    fn from(val: SwLock33sec) -> u8 {
+        SwLock33sec::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum SwLock34nsec {
+    READ_WRITE = 0,
+    READ_ONLY = 0x01,
+    _RESERVED_2 = 0x02,
+    INACCESSIBLE = 0x03,
+}
+impl SwLock34nsec {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> SwLock34nsec {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for SwLock34nsec {
+    #[inline(always)]
+    fn from(val: u8) -> SwLock34nsec {
+        SwLock34nsec::from_bits(val)
+    }
+}
+impl From<SwLock34nsec> for u8 {
+    #[inline(always)]
+    fn from(val: SwLock34nsec) -> u8 {
+        SwLock34nsec::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum SwLock34sec {
+    READ_WRITE = 0,
+    READ_ONLY = 0x01,
+    _RESERVED_2 = 0x02,
+    INACCESSIBLE = 0x03,
+}
+impl SwLock34sec {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> SwLock34sec {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for SwLock34sec {
+    #[inline(always)]
+    fn from(val: u8) -> SwLock34sec {
+        SwLock34sec::from_bits(val)
+    }
+}
+impl From<SwLock34sec> for u8 {
+    #[inline(always)]
+    fn from(val: SwLock34sec) -> u8 {
+        SwLock34sec::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum SwLock35nsec {
+    READ_WRITE = 0,
+    READ_ONLY = 0x01,
+    _RESERVED_2 = 0x02,
+    INACCESSIBLE = 0x03,
+}
+impl SwLock35nsec {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> SwLock35nsec {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for SwLock35nsec {
+    #[inline(always)]
+    fn from(val: u8) -> SwLock35nsec {
+        SwLock35nsec::from_bits(val)
+    }
+}
+impl From<SwLock35nsec> for u8 {
+    #[inline(always)]
+    fn from(val: SwLock35nsec) -> u8 {
+        SwLock35nsec::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum SwLock35sec {
+    READ_WRITE = 0,
+    READ_ONLY = 0x01,
+    _RESERVED_2 = 0x02,
+    INACCESSIBLE = 0x03,
+}
+impl SwLock35sec {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> SwLock35sec {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for SwLock35sec {
+    #[inline(always)]
+    fn from(val: u8) -> SwLock35sec {
+        SwLock35sec::from_bits(val)
+    }
+}
+impl From<SwLock35sec> for u8 {
+    #[inline(always)]
+    fn from(val: SwLock35sec) -> u8 {
+        SwLock35sec::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum SwLock36nsec {
+    READ_WRITE = 0,
+    READ_ONLY = 0x01,
+    _RESERVED_2 = 0x02,
+    INACCESSIBLE = 0x03,
+}
+impl SwLock36nsec {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> SwLock36nsec {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for SwLock36nsec {
+    #[inline(always)]
+    fn from(val: u8) -> SwLock36nsec {
+        SwLock36nsec::from_bits(val)
+    }
+}
+impl From<SwLock36nsec> for u8 {
+    #[inline(always)]
+    fn from(val: SwLock36nsec) -> u8 {
+        SwLock36nsec::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum SwLock36sec {
+    READ_WRITE = 0,
+    READ_ONLY = 0x01,
+    _RESERVED_2 = 0x02,
+    INACCESSIBLE = 0x03,
+}
+impl SwLock36sec {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> SwLock36sec {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for SwLock36sec {
+    #[inline(always)]
+    fn from(val: u8) -> SwLock36sec {
+        SwLock36sec::from_bits(val)
+    }
+}
+impl From<SwLock36sec> for u8 {
+    #[inline(always)]
+    fn from(val: SwLock36sec) -> u8 {
+        SwLock36sec::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum SwLock37nsec {
+    READ_WRITE = 0,
+    READ_ONLY = 0x01,
+    _RESERVED_2 = 0x02,
+    INACCESSIBLE = 0x03,
+}
+impl SwLock37nsec {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> SwLock37nsec {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for SwLock37nsec {
+    #[inline(always)]
+    fn from(val: u8) -> SwLock37nsec {
+        SwLock37nsec::from_bits(val)
+    }
+}
+impl From<SwLock37nsec> for u8 {
+    #[inline(always)]
+    fn from(val: SwLock37nsec) -> u8 {
+        SwLock37nsec::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum SwLock37sec {
+    READ_WRITE = 0,
+    READ_ONLY = 0x01,
+    _RESERVED_2 = 0x02,
+    INACCESSIBLE = 0x03,
+}
+impl SwLock37sec {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> SwLock37sec {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for SwLock37sec {
+    #[inline(always)]
+    fn from(val: u8) -> SwLock37sec {
+        SwLock37sec::from_bits(val)
+    }
+}
+impl From<SwLock37sec> for u8 {
+    #[inline(always)]
+    fn from(val: SwLock37sec) -> u8 {
+        SwLock37sec::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum SwLock38nsec {
+    READ_WRITE = 0,
+    READ_ONLY = 0x01,
+    _RESERVED_2 = 0x02,
+    INACCESSIBLE = 0x03,
+}
+impl SwLock38nsec {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> SwLock38nsec {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for SwLock38nsec {
+    #[inline(always)]
+    fn from(val: u8) -> SwLock38nsec {
+        SwLock38nsec::from_bits(val)
+    }
+}
+impl From<SwLock38nsec> for u8 {
+    #[inline(always)]
+    fn from(val: SwLock38nsec) -> u8 {
+        SwLock38nsec::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum SwLock38sec {
+    READ_WRITE = 0,
+    READ_ONLY = 0x01,
+    _RESERVED_2 = 0x02,
+    INACCESSIBLE = 0x03,
+}
+impl SwLock38sec {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> SwLock38sec {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for SwLock38sec {
+    #[inline(always)]
+    fn from(val: u8) -> SwLock38sec {
+        SwLock38sec::from_bits(val)
+    }
+}
+impl From<SwLock38sec> for u8 {
+    #[inline(always)]
+    fn from(val: SwLock38sec) -> u8 {
+        SwLock38sec::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum SwLock39nsec {
+    READ_WRITE = 0,
+    READ_ONLY = 0x01,
+    _RESERVED_2 = 0x02,
+    INACCESSIBLE = 0x03,
+}
+impl SwLock39nsec {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> SwLock39nsec {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for SwLock39nsec {
+    #[inline(always)]
+    fn from(val: u8) -> SwLock39nsec {
+        SwLock39nsec::from_bits(val)
+    }
+}
+impl From<SwLock39nsec> for u8 {
+    #[inline(always)]
+    fn from(val: SwLock39nsec) -> u8 {
+        SwLock39nsec::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum SwLock39sec {
+    READ_WRITE = 0,
+    READ_ONLY = 0x01,
+    _RESERVED_2 = 0x02,
+    INACCESSIBLE = 0x03,
+}
+impl SwLock39sec {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> SwLock39sec {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for SwLock39sec {
+    #[inline(always)]
+    fn from(val: u8) -> SwLock39sec {
+        SwLock39sec::from_bits(val)
+    }
+}
+impl From<SwLock39sec> for u8 {
+    #[inline(always)]
+    fn from(val: SwLock39sec) -> u8 {
+        SwLock39sec::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum SwLock3nsec {
+    READ_WRITE = 0,
+    READ_ONLY = 0x01,
+    _RESERVED_2 = 0x02,
+    INACCESSIBLE = 0x03,
+}
+impl SwLock3nsec {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> SwLock3nsec {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for SwLock3nsec {
+    #[inline(always)]
+    fn from(val: u8) -> SwLock3nsec {
+        SwLock3nsec::from_bits(val)
+    }
+}
+impl From<SwLock3nsec> for u8 {
+    #[inline(always)]
+    fn from(val: SwLock3nsec) -> u8 {
+        SwLock3nsec::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum SwLock3sec {
+    READ_WRITE = 0,
+    READ_ONLY = 0x01,
+    _RESERVED_2 = 0x02,
+    INACCESSIBLE = 0x03,
+}
+impl SwLock3sec {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> SwLock3sec {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for SwLock3sec {
+    #[inline(always)]
+    fn from(val: u8) -> SwLock3sec {
+        SwLock3sec::from_bits(val)
+    }
+}
+impl From<SwLock3sec> for u8 {
+    #[inline(always)]
+    fn from(val: SwLock3sec) -> u8 {
+        SwLock3sec::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum SwLock40nsec {
+    READ_WRITE = 0,
+    READ_ONLY = 0x01,
+    _RESERVED_2 = 0x02,
+    INACCESSIBLE = 0x03,
+}
+impl SwLock40nsec {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> SwLock40nsec {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for SwLock40nsec {
+    #[inline(always)]
+    fn from(val: u8) -> SwLock40nsec {
+        SwLock40nsec::from_bits(val)
+    }
+}
+impl From<SwLock40nsec> for u8 {
+    #[inline(always)]
+    fn from(val: SwLock40nsec) -> u8 {
+        SwLock40nsec::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum SwLock40sec {
+    READ_WRITE = 0,
+    READ_ONLY = 0x01,
+    _RESERVED_2 = 0x02,
+    INACCESSIBLE = 0x03,
+}
+impl SwLock40sec {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> SwLock40sec {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for SwLock40sec {
+    #[inline(always)]
+    fn from(val: u8) -> SwLock40sec {
+        SwLock40sec::from_bits(val)
+    }
+}
+impl From<SwLock40sec> for u8 {
+    #[inline(always)]
+    fn from(val: SwLock40sec) -> u8 {
+        SwLock40sec::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum SwLock41nsec {
+    READ_WRITE = 0,
+    READ_ONLY = 0x01,
+    _RESERVED_2 = 0x02,
+    INACCESSIBLE = 0x03,
+}
+impl SwLock41nsec {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> SwLock41nsec {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for SwLock41nsec {
+    #[inline(always)]
+    fn from(val: u8) -> SwLock41nsec {
+        SwLock41nsec::from_bits(val)
+    }
+}
+impl From<SwLock41nsec> for u8 {
+    #[inline(always)]
+    fn from(val: SwLock41nsec) -> u8 {
+        SwLock41nsec::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum SwLock41sec {
+    READ_WRITE = 0,
+    READ_ONLY = 0x01,
+    _RESERVED_2 = 0x02,
+    INACCESSIBLE = 0x03,
+}
+impl SwLock41sec {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> SwLock41sec {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for SwLock41sec {
+    #[inline(always)]
+    fn from(val: u8) -> SwLock41sec {
+        SwLock41sec::from_bits(val)
+    }
+}
+impl From<SwLock41sec> for u8 {
+    #[inline(always)]
+    fn from(val: SwLock41sec) -> u8 {
+        SwLock41sec::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum SwLock42nsec {
+    READ_WRITE = 0,
+    READ_ONLY = 0x01,
+    _RESERVED_2 = 0x02,
+    INACCESSIBLE = 0x03,
+}
+impl SwLock42nsec {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> SwLock42nsec {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for SwLock42nsec {
+    #[inline(always)]
+    fn from(val: u8) -> SwLock42nsec {
+        SwLock42nsec::from_bits(val)
+    }
+}
+impl From<SwLock42nsec> for u8 {
+    #[inline(always)]
+    fn from(val: SwLock42nsec) -> u8 {
+        SwLock42nsec::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum SwLock42sec {
+    READ_WRITE = 0,
+    READ_ONLY = 0x01,
+    _RESERVED_2 = 0x02,
+    INACCESSIBLE = 0x03,
+}
+impl SwLock42sec {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> SwLock42sec {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for SwLock42sec {
+    #[inline(always)]
+    fn from(val: u8) -> SwLock42sec {
+        SwLock42sec::from_bits(val)
+    }
+}
+impl From<SwLock42sec> for u8 {
+    #[inline(always)]
+    fn from(val: SwLock42sec) -> u8 {
+        SwLock42sec::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum SwLock43nsec {
+    READ_WRITE = 0,
+    READ_ONLY = 0x01,
+    _RESERVED_2 = 0x02,
+    INACCESSIBLE = 0x03,
+}
+impl SwLock43nsec {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> SwLock43nsec {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for SwLock43nsec {
+    #[inline(always)]
+    fn from(val: u8) -> SwLock43nsec {
+        SwLock43nsec::from_bits(val)
+    }
+}
+impl From<SwLock43nsec> for u8 {
+    #[inline(always)]
+    fn from(val: SwLock43nsec) -> u8 {
+        SwLock43nsec::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum SwLock43sec {
+    READ_WRITE = 0,
+    READ_ONLY = 0x01,
+    _RESERVED_2 = 0x02,
+    INACCESSIBLE = 0x03,
+}
+impl SwLock43sec {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> SwLock43sec {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for SwLock43sec {
+    #[inline(always)]
+    fn from(val: u8) -> SwLock43sec {
+        SwLock43sec::from_bits(val)
+    }
+}
+impl From<SwLock43sec> for u8 {
+    #[inline(always)]
+    fn from(val: SwLock43sec) -> u8 {
+        SwLock43sec::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum SwLock44nsec {
+    READ_WRITE = 0,
+    READ_ONLY = 0x01,
+    _RESERVED_2 = 0x02,
+    INACCESSIBLE = 0x03,
+}
+impl SwLock44nsec {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> SwLock44nsec {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for SwLock44nsec {
+    #[inline(always)]
+    fn from(val: u8) -> SwLock44nsec {
+        SwLock44nsec::from_bits(val)
+    }
+}
+impl From<SwLock44nsec> for u8 {
+    #[inline(always)]
+    fn from(val: SwLock44nsec) -> u8 {
+        SwLock44nsec::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum SwLock44sec {
+    READ_WRITE = 0,
+    READ_ONLY = 0x01,
+    _RESERVED_2 = 0x02,
+    INACCESSIBLE = 0x03,
+}
+impl SwLock44sec {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> SwLock44sec {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for SwLock44sec {
+    #[inline(always)]
+    fn from(val: u8) -> SwLock44sec {
+        SwLock44sec::from_bits(val)
+    }
+}
+impl From<SwLock44sec> for u8 {
+    #[inline(always)]
+    fn from(val: SwLock44sec) -> u8 {
+        SwLock44sec::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum SwLock45nsec {
+    READ_WRITE = 0,
+    READ_ONLY = 0x01,
+    _RESERVED_2 = 0x02,
+    INACCESSIBLE = 0x03,
+}
+impl SwLock45nsec {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> SwLock45nsec {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for SwLock45nsec {
+    #[inline(always)]
+    fn from(val: u8) -> SwLock45nsec {
+        SwLock45nsec::from_bits(val)
+    }
+}
+impl From<SwLock45nsec> for u8 {
+    #[inline(always)]
+    fn from(val: SwLock45nsec) -> u8 {
+        SwLock45nsec::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum SwLock45sec {
+    READ_WRITE = 0,
+    READ_ONLY = 0x01,
+    _RESERVED_2 = 0x02,
+    INACCESSIBLE = 0x03,
+}
+impl SwLock45sec {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> SwLock45sec {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for SwLock45sec {
+    #[inline(always)]
+    fn from(val: u8) -> SwLock45sec {
+        SwLock45sec::from_bits(val)
+    }
+}
+impl From<SwLock45sec> for u8 {
+    #[inline(always)]
+    fn from(val: SwLock45sec) -> u8 {
+        SwLock45sec::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum SwLock46nsec {
+    READ_WRITE = 0,
+    READ_ONLY = 0x01,
+    _RESERVED_2 = 0x02,
+    INACCESSIBLE = 0x03,
+}
+impl SwLock46nsec {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> SwLock46nsec {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for SwLock46nsec {
+    #[inline(always)]
+    fn from(val: u8) -> SwLock46nsec {
+        SwLock46nsec::from_bits(val)
+    }
+}
+impl From<SwLock46nsec> for u8 {
+    #[inline(always)]
+    fn from(val: SwLock46nsec) -> u8 {
+        SwLock46nsec::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum SwLock46sec {
+    READ_WRITE = 0,
+    READ_ONLY = 0x01,
+    _RESERVED_2 = 0x02,
+    INACCESSIBLE = 0x03,
+}
+impl SwLock46sec {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> SwLock46sec {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for SwLock46sec {
+    #[inline(always)]
+    fn from(val: u8) -> SwLock46sec {
+        SwLock46sec::from_bits(val)
+    }
+}
+impl From<SwLock46sec> for u8 {
+    #[inline(always)]
+    fn from(val: SwLock46sec) -> u8 {
+        SwLock46sec::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum SwLock47nsec {
+    READ_WRITE = 0,
+    READ_ONLY = 0x01,
+    _RESERVED_2 = 0x02,
+    INACCESSIBLE = 0x03,
+}
+impl SwLock47nsec {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> SwLock47nsec {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for SwLock47nsec {
+    #[inline(always)]
+    fn from(val: u8) -> SwLock47nsec {
+        SwLock47nsec::from_bits(val)
+    }
+}
+impl From<SwLock47nsec> for u8 {
+    #[inline(always)]
+    fn from(val: SwLock47nsec) -> u8 {
+        SwLock47nsec::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum SwLock47sec {
+    READ_WRITE = 0,
+    READ_ONLY = 0x01,
+    _RESERVED_2 = 0x02,
+    INACCESSIBLE = 0x03,
+}
+impl SwLock47sec {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> SwLock47sec {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for SwLock47sec {
+    #[inline(always)]
+    fn from(val: u8) -> SwLock47sec {
+        SwLock47sec::from_bits(val)
+    }
+}
+impl From<SwLock47sec> for u8 {
+    #[inline(always)]
+    fn from(val: SwLock47sec) -> u8 {
+        SwLock47sec::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum SwLock48nsec {
+    READ_WRITE = 0,
+    READ_ONLY = 0x01,
+    _RESERVED_2 = 0x02,
+    INACCESSIBLE = 0x03,
+}
+impl SwLock48nsec {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> SwLock48nsec {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for SwLock48nsec {
+    #[inline(always)]
+    fn from(val: u8) -> SwLock48nsec {
+        SwLock48nsec::from_bits(val)
+    }
+}
+impl From<SwLock48nsec> for u8 {
+    #[inline(always)]
+    fn from(val: SwLock48nsec) -> u8 {
+        SwLock48nsec::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum SwLock48sec {
+    READ_WRITE = 0,
+    READ_ONLY = 0x01,
+    _RESERVED_2 = 0x02,
+    INACCESSIBLE = 0x03,
+}
+impl SwLock48sec {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> SwLock48sec {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for SwLock48sec {
+    #[inline(always)]
+    fn from(val: u8) -> SwLock48sec {
+        SwLock48sec::from_bits(val)
+    }
+}
+impl From<SwLock48sec> for u8 {
+    #[inline(always)]
+    fn from(val: SwLock48sec) -> u8 {
+        SwLock48sec::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum SwLock49nsec {
+    READ_WRITE = 0,
+    READ_ONLY = 0x01,
+    _RESERVED_2 = 0x02,
+    INACCESSIBLE = 0x03,
+}
+impl SwLock49nsec {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> SwLock49nsec {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for SwLock49nsec {
+    #[inline(always)]
+    fn from(val: u8) -> SwLock49nsec {
+        SwLock49nsec::from_bits(val)
+    }
+}
+impl From<SwLock49nsec> for u8 {
+    #[inline(always)]
+    fn from(val: SwLock49nsec) -> u8 {
+        SwLock49nsec::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum SwLock49sec {
+    READ_WRITE = 0,
+    READ_ONLY = 0x01,
+    _RESERVED_2 = 0x02,
+    INACCESSIBLE = 0x03,
+}
+impl SwLock49sec {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> SwLock49sec {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for SwLock49sec {
+    #[inline(always)]
+    fn from(val: u8) -> SwLock49sec {
+        SwLock49sec::from_bits(val)
+    }
+}
+impl From<SwLock49sec> for u8 {
+    #[inline(always)]
+    fn from(val: SwLock49sec) -> u8 {
+        SwLock49sec::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum SwLock4nsec {
+    READ_WRITE = 0,
+    READ_ONLY = 0x01,
+    _RESERVED_2 = 0x02,
+    INACCESSIBLE = 0x03,
+}
+impl SwLock4nsec {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> SwLock4nsec {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for SwLock4nsec {
+    #[inline(always)]
+    fn from(val: u8) -> SwLock4nsec {
+        SwLock4nsec::from_bits(val)
+    }
+}
+impl From<SwLock4nsec> for u8 {
+    #[inline(always)]
+    fn from(val: SwLock4nsec) -> u8 {
+        SwLock4nsec::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum SwLock4sec {
+    READ_WRITE = 0,
+    READ_ONLY = 0x01,
+    _RESERVED_2 = 0x02,
+    INACCESSIBLE = 0x03,
+}
+impl SwLock4sec {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> SwLock4sec {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for SwLock4sec {
+    #[inline(always)]
+    fn from(val: u8) -> SwLock4sec {
+        SwLock4sec::from_bits(val)
+    }
+}
+impl From<SwLock4sec> for u8 {
+    #[inline(always)]
+    fn from(val: SwLock4sec) -> u8 {
+        SwLock4sec::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum SwLock50nsec {
+    READ_WRITE = 0,
+    READ_ONLY = 0x01,
+    _RESERVED_2 = 0x02,
+    INACCESSIBLE = 0x03,
+}
+impl SwLock50nsec {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> SwLock50nsec {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for SwLock50nsec {
+    #[inline(always)]
+    fn from(val: u8) -> SwLock50nsec {
+        SwLock50nsec::from_bits(val)
+    }
+}
+impl From<SwLock50nsec> for u8 {
+    #[inline(always)]
+    fn from(val: SwLock50nsec) -> u8 {
+        SwLock50nsec::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum SwLock50sec {
+    READ_WRITE = 0,
+    READ_ONLY = 0x01,
+    _RESERVED_2 = 0x02,
+    INACCESSIBLE = 0x03,
+}
+impl SwLock50sec {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> SwLock50sec {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for SwLock50sec {
+    #[inline(always)]
+    fn from(val: u8) -> SwLock50sec {
+        SwLock50sec::from_bits(val)
+    }
+}
+impl From<SwLock50sec> for u8 {
+    #[inline(always)]
+    fn from(val: SwLock50sec) -> u8 {
+        SwLock50sec::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum SwLock51nsec {
+    READ_WRITE = 0,
+    READ_ONLY = 0x01,
+    _RESERVED_2 = 0x02,
+    INACCESSIBLE = 0x03,
+}
+impl SwLock51nsec {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> SwLock51nsec {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for SwLock51nsec {
+    #[inline(always)]
+    fn from(val: u8) -> SwLock51nsec {
+        SwLock51nsec::from_bits(val)
+    }
+}
+impl From<SwLock51nsec> for u8 {
+    #[inline(always)]
+    fn from(val: SwLock51nsec) -> u8 {
+        SwLock51nsec::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum SwLock51sec {
+    READ_WRITE = 0,
+    READ_ONLY = 0x01,
+    _RESERVED_2 = 0x02,
+    INACCESSIBLE = 0x03,
+}
+impl SwLock51sec {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> SwLock51sec {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for SwLock51sec {
+    #[inline(always)]
+    fn from(val: u8) -> SwLock51sec {
+        SwLock51sec::from_bits(val)
+    }
+}
+impl From<SwLock51sec> for u8 {
+    #[inline(always)]
+    fn from(val: SwLock51sec) -> u8 {
+        SwLock51sec::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum SwLock52nsec {
+    READ_WRITE = 0,
+    READ_ONLY = 0x01,
+    _RESERVED_2 = 0x02,
+    INACCESSIBLE = 0x03,
+}
+impl SwLock52nsec {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> SwLock52nsec {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for SwLock52nsec {
+    #[inline(always)]
+    fn from(val: u8) -> SwLock52nsec {
+        SwLock52nsec::from_bits(val)
+    }
+}
+impl From<SwLock52nsec> for u8 {
+    #[inline(always)]
+    fn from(val: SwLock52nsec) -> u8 {
+        SwLock52nsec::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum SwLock52sec {
+    READ_WRITE = 0,
+    READ_ONLY = 0x01,
+    _RESERVED_2 = 0x02,
+    INACCESSIBLE = 0x03,
+}
+impl SwLock52sec {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> SwLock52sec {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for SwLock52sec {
+    #[inline(always)]
+    fn from(val: u8) -> SwLock52sec {
+        SwLock52sec::from_bits(val)
+    }
+}
+impl From<SwLock52sec> for u8 {
+    #[inline(always)]
+    fn from(val: SwLock52sec) -> u8 {
+        SwLock52sec::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum SwLock53nsec {
+    READ_WRITE = 0,
+    READ_ONLY = 0x01,
+    _RESERVED_2 = 0x02,
+    INACCESSIBLE = 0x03,
+}
+impl SwLock53nsec {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> SwLock53nsec {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for SwLock53nsec {
+    #[inline(always)]
+    fn from(val: u8) -> SwLock53nsec {
+        SwLock53nsec::from_bits(val)
+    }
+}
+impl From<SwLock53nsec> for u8 {
+    #[inline(always)]
+    fn from(val: SwLock53nsec) -> u8 {
+        SwLock53nsec::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum SwLock53sec {
+    READ_WRITE = 0,
+    READ_ONLY = 0x01,
+    _RESERVED_2 = 0x02,
+    INACCESSIBLE = 0x03,
+}
+impl SwLock53sec {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> SwLock53sec {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for SwLock53sec {
+    #[inline(always)]
+    fn from(val: u8) -> SwLock53sec {
+        SwLock53sec::from_bits(val)
+    }
+}
+impl From<SwLock53sec> for u8 {
+    #[inline(always)]
+    fn from(val: SwLock53sec) -> u8 {
+        SwLock53sec::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum SwLock54nsec {
+    READ_WRITE = 0,
+    READ_ONLY = 0x01,
+    _RESERVED_2 = 0x02,
+    INACCESSIBLE = 0x03,
+}
+impl SwLock54nsec {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> SwLock54nsec {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for SwLock54nsec {
+    #[inline(always)]
+    fn from(val: u8) -> SwLock54nsec {
+        SwLock54nsec::from_bits(val)
+    }
+}
+impl From<SwLock54nsec> for u8 {
+    #[inline(always)]
+    fn from(val: SwLock54nsec) -> u8 {
+        SwLock54nsec::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum SwLock54sec {
+    READ_WRITE = 0,
+    READ_ONLY = 0x01,
+    _RESERVED_2 = 0x02,
+    INACCESSIBLE = 0x03,
+}
+impl SwLock54sec {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> SwLock54sec {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for SwLock54sec {
+    #[inline(always)]
+    fn from(val: u8) -> SwLock54sec {
+        SwLock54sec::from_bits(val)
+    }
+}
+impl From<SwLock54sec> for u8 {
+    #[inline(always)]
+    fn from(val: SwLock54sec) -> u8 {
+        SwLock54sec::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum SwLock55nsec {
+    READ_WRITE = 0,
+    READ_ONLY = 0x01,
+    _RESERVED_2 = 0x02,
+    INACCESSIBLE = 0x03,
+}
+impl SwLock55nsec {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> SwLock55nsec {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for SwLock55nsec {
+    #[inline(always)]
+    fn from(val: u8) -> SwLock55nsec {
+        SwLock55nsec::from_bits(val)
+    }
+}
+impl From<SwLock55nsec> for u8 {
+    #[inline(always)]
+    fn from(val: SwLock55nsec) -> u8 {
+        SwLock55nsec::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum SwLock55sec {
+    READ_WRITE = 0,
+    READ_ONLY = 0x01,
+    _RESERVED_2 = 0x02,
+    INACCESSIBLE = 0x03,
+}
+impl SwLock55sec {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> SwLock55sec {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for SwLock55sec {
+    #[inline(always)]
+    fn from(val: u8) -> SwLock55sec {
+        SwLock55sec::from_bits(val)
+    }
+}
+impl From<SwLock55sec> for u8 {
+    #[inline(always)]
+    fn from(val: SwLock55sec) -> u8 {
+        SwLock55sec::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum SwLock56nsec {
+    READ_WRITE = 0,
+    READ_ONLY = 0x01,
+    _RESERVED_2 = 0x02,
+    INACCESSIBLE = 0x03,
+}
+impl SwLock56nsec {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> SwLock56nsec {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for SwLock56nsec {
+    #[inline(always)]
+    fn from(val: u8) -> SwLock56nsec {
+        SwLock56nsec::from_bits(val)
+    }
+}
+impl From<SwLock56nsec> for u8 {
+    #[inline(always)]
+    fn from(val: SwLock56nsec) -> u8 {
+        SwLock56nsec::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum SwLock56sec {
+    READ_WRITE = 0,
+    READ_ONLY = 0x01,
+    _RESERVED_2 = 0x02,
+    INACCESSIBLE = 0x03,
+}
+impl SwLock56sec {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> SwLock56sec {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for SwLock56sec {
+    #[inline(always)]
+    fn from(val: u8) -> SwLock56sec {
+        SwLock56sec::from_bits(val)
+    }
+}
+impl From<SwLock56sec> for u8 {
+    #[inline(always)]
+    fn from(val: SwLock56sec) -> u8 {
+        SwLock56sec::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum SwLock57nsec {
+    READ_WRITE = 0,
+    READ_ONLY = 0x01,
+    _RESERVED_2 = 0x02,
+    INACCESSIBLE = 0x03,
+}
+impl SwLock57nsec {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> SwLock57nsec {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for SwLock57nsec {
+    #[inline(always)]
+    fn from(val: u8) -> SwLock57nsec {
+        SwLock57nsec::from_bits(val)
+    }
+}
+impl From<SwLock57nsec> for u8 {
+    #[inline(always)]
+    fn from(val: SwLock57nsec) -> u8 {
+        SwLock57nsec::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum SwLock57sec {
+    READ_WRITE = 0,
+    READ_ONLY = 0x01,
+    _RESERVED_2 = 0x02,
+    INACCESSIBLE = 0x03,
+}
+impl SwLock57sec {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> SwLock57sec {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for SwLock57sec {
+    #[inline(always)]
+    fn from(val: u8) -> SwLock57sec {
+        SwLock57sec::from_bits(val)
+    }
+}
+impl From<SwLock57sec> for u8 {
+    #[inline(always)]
+    fn from(val: SwLock57sec) -> u8 {
+        SwLock57sec::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum SwLock58nsec {
+    READ_WRITE = 0,
+    READ_ONLY = 0x01,
+    _RESERVED_2 = 0x02,
+    INACCESSIBLE = 0x03,
+}
+impl SwLock58nsec {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> SwLock58nsec {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for SwLock58nsec {
+    #[inline(always)]
+    fn from(val: u8) -> SwLock58nsec {
+        SwLock58nsec::from_bits(val)
+    }
+}
+impl From<SwLock58nsec> for u8 {
+    #[inline(always)]
+    fn from(val: SwLock58nsec) -> u8 {
+        SwLock58nsec::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum SwLock58sec {
+    READ_WRITE = 0,
+    READ_ONLY = 0x01,
+    _RESERVED_2 = 0x02,
+    INACCESSIBLE = 0x03,
+}
+impl SwLock58sec {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> SwLock58sec {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for SwLock58sec {
+    #[inline(always)]
+    fn from(val: u8) -> SwLock58sec {
+        SwLock58sec::from_bits(val)
+    }
+}
+impl From<SwLock58sec> for u8 {
+    #[inline(always)]
+    fn from(val: SwLock58sec) -> u8 {
+        SwLock58sec::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum SwLock59nsec {
+    READ_WRITE = 0,
+    READ_ONLY = 0x01,
+    _RESERVED_2 = 0x02,
+    INACCESSIBLE = 0x03,
+}
+impl SwLock59nsec {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> SwLock59nsec {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for SwLock59nsec {
+    #[inline(always)]
+    fn from(val: u8) -> SwLock59nsec {
+        SwLock59nsec::from_bits(val)
+    }
+}
+impl From<SwLock59nsec> for u8 {
+    #[inline(always)]
+    fn from(val: SwLock59nsec) -> u8 {
+        SwLock59nsec::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum SwLock59sec {
+    READ_WRITE = 0,
+    READ_ONLY = 0x01,
+    _RESERVED_2 = 0x02,
+    INACCESSIBLE = 0x03,
+}
+impl SwLock59sec {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> SwLock59sec {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for SwLock59sec {
+    #[inline(always)]
+    fn from(val: u8) -> SwLock59sec {
+        SwLock59sec::from_bits(val)
+    }
+}
+impl From<SwLock59sec> for u8 {
+    #[inline(always)]
+    fn from(val: SwLock59sec) -> u8 {
+        SwLock59sec::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum SwLock5nsec {
+    READ_WRITE = 0,
+    READ_ONLY = 0x01,
+    _RESERVED_2 = 0x02,
+    INACCESSIBLE = 0x03,
+}
+impl SwLock5nsec {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> SwLock5nsec {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for SwLock5nsec {
+    #[inline(always)]
+    fn from(val: u8) -> SwLock5nsec {
+        SwLock5nsec::from_bits(val)
+    }
+}
+impl From<SwLock5nsec> for u8 {
+    #[inline(always)]
+    fn from(val: SwLock5nsec) -> u8 {
+        SwLock5nsec::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum SwLock5sec {
+    READ_WRITE = 0,
+    READ_ONLY = 0x01,
+    _RESERVED_2 = 0x02,
+    INACCESSIBLE = 0x03,
+}
+impl SwLock5sec {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> SwLock5sec {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for SwLock5sec {
+    #[inline(always)]
+    fn from(val: u8) -> SwLock5sec {
+        SwLock5sec::from_bits(val)
+    }
+}
+impl From<SwLock5sec> for u8 {
+    #[inline(always)]
+    fn from(val: SwLock5sec) -> u8 {
+        SwLock5sec::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum SwLock60nsec {
+    READ_WRITE = 0,
+    READ_ONLY = 0x01,
+    _RESERVED_2 = 0x02,
+    INACCESSIBLE = 0x03,
+}
+impl SwLock60nsec {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> SwLock60nsec {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for SwLock60nsec {
+    #[inline(always)]
+    fn from(val: u8) -> SwLock60nsec {
+        SwLock60nsec::from_bits(val)
+    }
+}
+impl From<SwLock60nsec> for u8 {
+    #[inline(always)]
+    fn from(val: SwLock60nsec) -> u8 {
+        SwLock60nsec::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum SwLock60sec {
+    READ_WRITE = 0,
+    READ_ONLY = 0x01,
+    _RESERVED_2 = 0x02,
+    INACCESSIBLE = 0x03,
+}
+impl SwLock60sec {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> SwLock60sec {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for SwLock60sec {
+    #[inline(always)]
+    fn from(val: u8) -> SwLock60sec {
+        SwLock60sec::from_bits(val)
+    }
+}
+impl From<SwLock60sec> for u8 {
+    #[inline(always)]
+    fn from(val: SwLock60sec) -> u8 {
+        SwLock60sec::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum SwLock61nsec {
+    READ_WRITE = 0,
+    READ_ONLY = 0x01,
+    _RESERVED_2 = 0x02,
+    INACCESSIBLE = 0x03,
+}
+impl SwLock61nsec {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> SwLock61nsec {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for SwLock61nsec {
+    #[inline(always)]
+    fn from(val: u8) -> SwLock61nsec {
+        SwLock61nsec::from_bits(val)
+    }
+}
+impl From<SwLock61nsec> for u8 {
+    #[inline(always)]
+    fn from(val: SwLock61nsec) -> u8 {
+        SwLock61nsec::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum SwLock61sec {
+    READ_WRITE = 0,
+    READ_ONLY = 0x01,
+    _RESERVED_2 = 0x02,
+    INACCESSIBLE = 0x03,
+}
+impl SwLock61sec {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> SwLock61sec {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for SwLock61sec {
+    #[inline(always)]
+    fn from(val: u8) -> SwLock61sec {
+        SwLock61sec::from_bits(val)
+    }
+}
+impl From<SwLock61sec> for u8 {
+    #[inline(always)]
+    fn from(val: SwLock61sec) -> u8 {
+        SwLock61sec::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum SwLock62nsec {
+    READ_WRITE = 0,
+    READ_ONLY = 0x01,
+    _RESERVED_2 = 0x02,
+    INACCESSIBLE = 0x03,
+}
+impl SwLock62nsec {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> SwLock62nsec {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for SwLock62nsec {
+    #[inline(always)]
+    fn from(val: u8) -> SwLock62nsec {
+        SwLock62nsec::from_bits(val)
+    }
+}
+impl From<SwLock62nsec> for u8 {
+    #[inline(always)]
+    fn from(val: SwLock62nsec) -> u8 {
+        SwLock62nsec::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum SwLock62sec {
+    READ_WRITE = 0,
+    READ_ONLY = 0x01,
+    _RESERVED_2 = 0x02,
+    INACCESSIBLE = 0x03,
+}
+impl SwLock62sec {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> SwLock62sec {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for SwLock62sec {
+    #[inline(always)]
+    fn from(val: u8) -> SwLock62sec {
+        SwLock62sec::from_bits(val)
+    }
+}
+impl From<SwLock62sec> for u8 {
+    #[inline(always)]
+    fn from(val: SwLock62sec) -> u8 {
+        SwLock62sec::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum SwLock63nsec {
+    READ_WRITE = 0,
+    READ_ONLY = 0x01,
+    _RESERVED_2 = 0x02,
+    INACCESSIBLE = 0x03,
+}
+impl SwLock63nsec {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> SwLock63nsec {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for SwLock63nsec {
+    #[inline(always)]
+    fn from(val: u8) -> SwLock63nsec {
+        SwLock63nsec::from_bits(val)
+    }
+}
+impl From<SwLock63nsec> for u8 {
+    #[inline(always)]
+    fn from(val: SwLock63nsec) -> u8 {
+        SwLock63nsec::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum SwLock63sec {
+    READ_WRITE = 0,
+    READ_ONLY = 0x01,
+    _RESERVED_2 = 0x02,
+    INACCESSIBLE = 0x03,
+}
+impl SwLock63sec {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> SwLock63sec {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for SwLock63sec {
+    #[inline(always)]
+    fn from(val: u8) -> SwLock63sec {
+        SwLock63sec::from_bits(val)
+    }
+}
+impl From<SwLock63sec> for u8 {
+    #[inline(always)]
+    fn from(val: SwLock63sec) -> u8 {
+        SwLock63sec::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum SwLock6nsec {
+    READ_WRITE = 0,
+    READ_ONLY = 0x01,
+    _RESERVED_2 = 0x02,
+    INACCESSIBLE = 0x03,
+}
+impl SwLock6nsec {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> SwLock6nsec {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for SwLock6nsec {
+    #[inline(always)]
+    fn from(val: u8) -> SwLock6nsec {
+        SwLock6nsec::from_bits(val)
+    }
+}
+impl From<SwLock6nsec> for u8 {
+    #[inline(always)]
+    fn from(val: SwLock6nsec) -> u8 {
+        SwLock6nsec::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum SwLock6sec {
+    READ_WRITE = 0,
+    READ_ONLY = 0x01,
+    _RESERVED_2 = 0x02,
+    INACCESSIBLE = 0x03,
+}
+impl SwLock6sec {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> SwLock6sec {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for SwLock6sec {
+    #[inline(always)]
+    fn from(val: u8) -> SwLock6sec {
+        SwLock6sec::from_bits(val)
+    }
+}
+impl From<SwLock6sec> for u8 {
+    #[inline(always)]
+    fn from(val: SwLock6sec) -> u8 {
+        SwLock6sec::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum SwLock7nsec {
+    READ_WRITE = 0,
+    READ_ONLY = 0x01,
+    _RESERVED_2 = 0x02,
+    INACCESSIBLE = 0x03,
+}
+impl SwLock7nsec {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> SwLock7nsec {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for SwLock7nsec {
+    #[inline(always)]
+    fn from(val: u8) -> SwLock7nsec {
+        SwLock7nsec::from_bits(val)
+    }
+}
+impl From<SwLock7nsec> for u8 {
+    #[inline(always)]
+    fn from(val: SwLock7nsec) -> u8 {
+        SwLock7nsec::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum SwLock7sec {
+    READ_WRITE = 0,
+    READ_ONLY = 0x01,
+    _RESERVED_2 = 0x02,
+    INACCESSIBLE = 0x03,
+}
+impl SwLock7sec {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> SwLock7sec {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for SwLock7sec {
+    #[inline(always)]
+    fn from(val: u8) -> SwLock7sec {
+        SwLock7sec::from_bits(val)
+    }
+}
+impl From<SwLock7sec> for u8 {
+    #[inline(always)]
+    fn from(val: SwLock7sec) -> u8 {
+        SwLock7sec::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum SwLock8nsec {
+    READ_WRITE = 0,
+    READ_ONLY = 0x01,
+    _RESERVED_2 = 0x02,
+    INACCESSIBLE = 0x03,
+}
+impl SwLock8nsec {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> SwLock8nsec {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for SwLock8nsec {
+    #[inline(always)]
+    fn from(val: u8) -> SwLock8nsec {
+        SwLock8nsec::from_bits(val)
+    }
+}
+impl From<SwLock8nsec> for u8 {
+    #[inline(always)]
+    fn from(val: SwLock8nsec) -> u8 {
+        SwLock8nsec::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum SwLock8sec {
+    READ_WRITE = 0,
+    READ_ONLY = 0x01,
+    _RESERVED_2 = 0x02,
+    INACCESSIBLE = 0x03,
+}
+impl SwLock8sec {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> SwLock8sec {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for SwLock8sec {
+    #[inline(always)]
+    fn from(val: u8) -> SwLock8sec {
+        SwLock8sec::from_bits(val)
+    }
+}
+impl From<SwLock8sec> for u8 {
+    #[inline(always)]
+    fn from(val: SwLock8sec) -> u8 {
+        SwLock8sec::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum SwLock9nsec {
+    READ_WRITE = 0,
+    READ_ONLY = 0x01,
+    _RESERVED_2 = 0x02,
+    INACCESSIBLE = 0x03,
+}
+impl SwLock9nsec {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> SwLock9nsec {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for SwLock9nsec {
+    #[inline(always)]
+    fn from(val: u8) -> SwLock9nsec {
+        SwLock9nsec::from_bits(val)
+    }
+}
+impl From<SwLock9nsec> for u8 {
+    #[inline(always)]
+    fn from(val: SwLock9nsec) -> u8 {
+        SwLock9nsec::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum SwLock9sec {
+    READ_WRITE = 0,
+    READ_ONLY = 0x01,
+    _RESERVED_2 = 0x02,
+    INACCESSIBLE = 0x03,
+}
+impl SwLock9sec {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> SwLock9sec {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for SwLock9sec {
+    #[inline(always)]
+    fn from(val: u8) -> SwLock9sec {
+        SwLock9sec::from_bits(val)
+    }
+}
+impl From<SwLock9sec> for u8 {
+    #[inline(always)]
+    fn from(val: SwLock9sec) -> u8 {
+        SwLock9sec::to_bits(val)
+    }
+}
diff --git a/src/rp2350/otp_data.rs b/src/rp2350/otp_data.rs
new file mode 100644
index 00000000..33d55839
--- /dev/null
+++ b/src/rp2350/otp_data.rs
@@ -0,0 +1,724 @@
+#[doc = "Predefined OTP data layout for RP2350"]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct OtpData {
+    ptr: *mut u8,
+}
+unsafe impl Send for OtpData {}
+unsafe impl Sync for OtpData {}
+impl OtpData {
+    #[inline(always)]
+    pub const unsafe fn from_ptr(ptr: *mut ()) -> Self {
+        Self { ptr: ptr as _ }
+    }
+    #[inline(always)]
+    pub const fn as_ptr(&self) -> *mut () {
+        self.ptr as _
+    }
+    #[doc = "Bits 15:0 of public device ID. (ECC) The CHIPID0..3 rows contain a 64-bit random identifier for this chip, which can be read from the USB bootloader PICOBOOT interface or from the get_sys_info ROM API. The number of random bits makes the occurrence of twins exceedingly unlikely: for example, a fleet of a hundred million devices has a 99.97% probability of no twinned IDs. This is estimated to be lower than the occurrence of process errors in the assignment of sequential random IDs, and for practical purposes CHIPID may be treated as unique."]
+    #[inline(always)]
+    pub const fn chipid0(self) -> crate::common::Reg<regs::Chipid0, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(0usize) as _) }
+    }
+    #[doc = "Bits 31:16 of public device ID (ECC)"]
+    #[inline(always)]
+    pub const fn chipid1(self) -> crate::common::Reg<regs::Chipid1, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(2usize) as _) }
+    }
+    #[doc = "Bits 47:32 of public device ID (ECC)"]
+    #[inline(always)]
+    pub const fn chipid2(self) -> crate::common::Reg<regs::Chipid2, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(4usize) as _) }
+    }
+    #[doc = "Bits 63:48 of public device ID (ECC)"]
+    #[inline(always)]
+    pub const fn chipid3(self) -> crate::common::Reg<regs::Chipid3, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(6usize) as _) }
+    }
+    #[doc = "Bits 15:0 of private per-device random number (ECC) The RANDID0..7 rows form a 128-bit random number generated during device test. This ID is not exposed through the USB PICOBOOT GET_INFO command or the ROM `get_sys_info()` API. However note that the USB PICOBOOT OTP access point can read the entirety of page 0, so this value is not meaningfully private unless the USB PICOBOOT interface is disabled via the DISABLE_BOOTSEL_USB_PICOBOOT_IFC flag in BOOT_FLAGS0."]
+    #[inline(always)]
+    pub const fn randid0(self) -> crate::common::Reg<regs::Randid0, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(8usize) as _) }
+    }
+    #[doc = "Bits 31:16 of private per-device random number (ECC)"]
+    #[inline(always)]
+    pub const fn randid1(self) -> crate::common::Reg<regs::Randid1, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(10usize) as _) }
+    }
+    #[doc = "Bits 47:32 of private per-device random number (ECC)"]
+    #[inline(always)]
+    pub const fn randid2(self) -> crate::common::Reg<regs::Randid2, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(12usize) as _) }
+    }
+    #[doc = "Bits 63:48 of private per-device random number (ECC)"]
+    #[inline(always)]
+    pub const fn randid3(self) -> crate::common::Reg<regs::Randid3, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(14usize) as _) }
+    }
+    #[doc = "Bits 79:64 of private per-device random number (ECC)"]
+    #[inline(always)]
+    pub const fn randid4(self) -> crate::common::Reg<regs::Randid4, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(16usize) as _) }
+    }
+    #[doc = "Bits 95:80 of private per-device random number (ECC)"]
+    #[inline(always)]
+    pub const fn randid5(self) -> crate::common::Reg<regs::Randid5, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(18usize) as _) }
+    }
+    #[doc = "Bits 111:96 of private per-device random number (ECC)"]
+    #[inline(always)]
+    pub const fn randid6(self) -> crate::common::Reg<regs::Randid6, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(20usize) as _) }
+    }
+    #[doc = "Bits 127:112 of private per-device random number (ECC)"]
+    #[inline(always)]
+    pub const fn randid7(self) -> crate::common::Reg<regs::Randid7, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(22usize) as _) }
+    }
+    #[doc = "Ring oscillator frequency in kHz, measured during manufacturing (ECC) This is measured at 1.1 V, at room temperature, with the ROSC configuration registers in their reset state."]
+    #[inline(always)]
+    pub const fn rosc_calib(self) -> crate::common::Reg<regs::RoscCalib, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(32usize) as _) }
+    }
+    #[doc = "Low-power oscillator frequency in Hz, measured during manufacturing (ECC) This is measured at 1.1V, at room temperature, with the LPOSC trim register in its reset state."]
+    #[inline(always)]
+    pub const fn lposc_calib(self) -> crate::common::Reg<regs::LposcCalib, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(34usize) as _) }
+    }
+    #[doc = "The number of main user GPIOs (bank 0). Should read 48 in the QFN80 package, and 30 in the QFN60 package. (ECC)"]
+    #[inline(always)]
+    pub const fn num_gpios(self) -> crate::common::Reg<regs::NumGpios, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(48usize) as _) }
+    }
+    #[doc = "Lower 16 bits of CRC32 of OTP addresses 0x00 through 0x6b (polynomial 0x4c11db7, input reflected, output reflected, seed all-ones, final XOR all-ones) (ECC)"]
+    #[inline(always)]
+    pub const fn info_crc0(self) -> crate::common::Reg<regs::InfoCrc0, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(108usize) as _) }
+    }
+    #[doc = "Upper 16 bits of CRC32 of OTP addresses 0x00 through 0x6b (ECC)"]
+    #[inline(always)]
+    pub const fn info_crc1(self) -> crate::common::Reg<regs::InfoCrc1, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(110usize) as _) }
+    }
+    #[doc = "Stores information about external flash device(s). (ECC) Assumed to be valid if BOOT_FLAGS0_FLASH_DEVINFO_ENABLE is set."]
+    #[inline(always)]
+    pub const fn flash_devinfo(self) -> crate::common::Reg<regs::FlashDevinfo, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(168usize) as _) }
+    }
+    #[doc = "Gap between partition table slot 0 and slot 1 at the start of flash (the default size is 4096 bytes) (ECC) Enabled by the OVERRIDE_FLASH_PARTITION_SLOT_SIZE bit in BOOT_FLAGS, the size is 4096 * (value + 1)"]
+    #[inline(always)]
+    pub const fn flash_partition_slot_size(
+        self,
+    ) -> crate::common::Reg<regs::FlashPartitionSlotSize, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(170usize) as _) }
+    }
+    #[doc = "Pin configuration for LED status, used by USB bootloader. (ECC) Must be valid if BOOT_FLAGS0_ENABLE_BOOTSEL_LED is set."]
+    #[inline(always)]
+    pub const fn bootsel_led_cfg(
+        self,
+    ) -> crate::common::Reg<regs::BootselLedCfg, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(172usize) as _) }
+    }
+    #[doc = "Optional PLL configuration for BOOTSEL mode. (ECC) This should be configured to produce an exact 48 MHz based on the crystal oscillator frequency. User mode software may also use this value to calculate the expected crystal frequency based on an assumed 48 MHz PLL output. If no configuration is given, the crystal is assumed to be 12 MHz. The PLL frequency can be calculated as: PLL out = (XOSC frequency / (REFDIV+1)) x FBDIV / (POSTDIV1 x POSTDIV2) Conversely the crystal frequency can be calculated as: XOSC frequency = 48 MHz x (REFDIV+1) x (POSTDIV1 x POSTDIV2) / FBDIV (Note the +1 on REFDIV is because the value stored in this OTP location is the actual divisor value minus one.) Used if and only if ENABLE_BOOTSEL_NON_DEFAULT_PLL_XOSC_CFG is set in BOOT_FLAGS0. That bit should be set only after this row and BOOTSEL_XOSC_CFG are both correctly programmed."]
+    #[inline(always)]
+    pub const fn bootsel_pll_cfg(
+        self,
+    ) -> crate::common::Reg<regs::BootselPllCfg, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(174usize) as _) }
+    }
+    #[doc = "Non-default crystal oscillator configuration for the USB bootloader. (ECC) These values may also be used by user code configuring the crystal oscillator. Used if and only if ENABLE_BOOTSEL_NON_DEFAULT_PLL_XOSC_CFG is set in BOOT_FLAGS0. That bit should be set only after this row and BOOTSEL_PLL_CFG are both correctly programmed."]
+    #[inline(always)]
+    pub const fn bootsel_xosc_cfg(
+        self,
+    ) -> crate::common::Reg<regs::BootselXoscCfg, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(176usize) as _) }
+    }
+    #[doc = "Row index of the USB_WHITE_LABEL structure within OTP (ECC) The table has 16 rows, each of which are also ECC and marked valid by the corresponding valid bit in USB_BOOT_FLAGS (ECC). The entries are either _VALUEs where the 16 bit value is used as is, or _STRDEFs which acts as a pointers to a string value. The value stored in a _STRDEF is two separate bytes: The low seven bits of the first (LSB) byte indicates the number of characters in the string, and the top bit of the first (LSB) byte if set to indicate that each character in the string is two bytes (Unicode) versus one byte if unset. The second (MSB) byte represents the location of the string data, and is encoded as the number of rows from this USB_WHITE_LABEL_ADDR; i.e. the row of the start of the string is USB_WHITE_LABEL_ADDR value + msb_byte. In each case, the corresponding valid bit enables replacing the default value for the corresponding item provided by the boot rom. Note that Unicode _STRDEFs are only supported for USB_DEVICE_PRODUCT_STRDEF, USB_DEVICE_SERIAL_NUMBER_STRDEF and USB_DEVICE_MANUFACTURER_STRDEF. Unicode values will be ignored if specified for other fields, and non-unicode values for these three items will be converted to Unicode characters by setting the upper 8 bits to zero. Note that if the USB_WHITE_LABEL structure or the corresponding strings are not readable by BOOTSEL mode based on OTP permissions, or if alignment requirements are not met, then the corresponding default values are used. The index values indicate where each field is located (row USB_WHITE_LABEL_ADDR value + index):"]
+    #[inline(always)]
+    pub const fn usb_white_label_addr(
+        self,
+    ) -> crate::common::Reg<regs::UsbWhiteLabelAddr, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(184usize) as _) }
+    }
+    #[doc = "OTP start row for the OTP boot image. (ECC) If OTP boot is enabled, the bootrom will load from this location into SRAM and then directly enter the loaded image. Note that the image must be signed if SECURE_BOOT_ENABLE is set. The image itself is assumed to be ECC-protected. This must be an even number. Equivalently, the OTP boot image must start at a word-aligned location in the ECC read data address window."]
+    #[inline(always)]
+    pub const fn otpboot_src(self) -> crate::common::Reg<regs::OtpbootSrc, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(188usize) as _) }
+    }
+    #[doc = "Length in rows of the OTP boot image. (ECC) OTPBOOT_LEN must be even. The total image size must be a multiple of 4 bytes (32 bits)."]
+    #[inline(always)]
+    pub const fn otpboot_len(self) -> crate::common::Reg<regs::OtpbootLen, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(190usize) as _) }
+    }
+    #[doc = "Bits 15:0 of the OTP boot image load destination (and entry point). (ECC) This must be a location in main SRAM (main SRAM is addresses 0x20000000 through 0x20082000) and must be word-aligned."]
+    #[inline(always)]
+    pub const fn otpboot_dst0(self) -> crate::common::Reg<regs::OtpbootDst0, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(192usize) as _) }
+    }
+    #[doc = "Bits 31:16 of the OTP boot image load destination (and entry point). (ECC) This must be a location in main SRAM (main SRAM is addresses 0x20000000 through 0x20082000) and must be word-aligned."]
+    #[inline(always)]
+    pub const fn otpboot_dst1(self) -> crate::common::Reg<regs::OtpbootDst1, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(194usize) as _) }
+    }
+    #[doc = "Bits 15:0 of SHA-256 hash of boot key 0 (ECC)"]
+    #[inline(always)]
+    pub const fn bootkey0_0(self) -> crate::common::Reg<regs::Bootkey00, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(256usize) as _) }
+    }
+    #[doc = "Bits 31:16 of SHA-256 hash of boot key 0 (ECC)"]
+    #[inline(always)]
+    pub const fn bootkey0_1(self) -> crate::common::Reg<regs::Bootkey01, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(258usize) as _) }
+    }
+    #[doc = "Bits 47:32 of SHA-256 hash of boot key 0 (ECC)"]
+    #[inline(always)]
+    pub const fn bootkey0_2(self) -> crate::common::Reg<regs::Bootkey02, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(260usize) as _) }
+    }
+    #[doc = "Bits 63:48 of SHA-256 hash of boot key 0 (ECC)"]
+    #[inline(always)]
+    pub const fn bootkey0_3(self) -> crate::common::Reg<regs::Bootkey03, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(262usize) as _) }
+    }
+    #[doc = "Bits 79:64 of SHA-256 hash of boot key 0 (ECC)"]
+    #[inline(always)]
+    pub const fn bootkey0_4(self) -> crate::common::Reg<regs::Bootkey04, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(264usize) as _) }
+    }
+    #[doc = "Bits 95:80 of SHA-256 hash of boot key 0 (ECC)"]
+    #[inline(always)]
+    pub const fn bootkey0_5(self) -> crate::common::Reg<regs::Bootkey05, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(266usize) as _) }
+    }
+    #[doc = "Bits 111:96 of SHA-256 hash of boot key 0 (ECC)"]
+    #[inline(always)]
+    pub const fn bootkey0_6(self) -> crate::common::Reg<regs::Bootkey06, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(268usize) as _) }
+    }
+    #[doc = "Bits 127:112 of SHA-256 hash of boot key 0 (ECC)"]
+    #[inline(always)]
+    pub const fn bootkey0_7(self) -> crate::common::Reg<regs::Bootkey07, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(270usize) as _) }
+    }
+    #[doc = "Bits 143:128 of SHA-256 hash of boot key 0 (ECC)"]
+    #[inline(always)]
+    pub const fn bootkey0_8(self) -> crate::common::Reg<regs::Bootkey08, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(272usize) as _) }
+    }
+    #[doc = "Bits 159:144 of SHA-256 hash of boot key 0 (ECC)"]
+    #[inline(always)]
+    pub const fn bootkey0_9(self) -> crate::common::Reg<regs::Bootkey09, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(274usize) as _) }
+    }
+    #[doc = "Bits 175:160 of SHA-256 hash of boot key 0 (ECC)"]
+    #[inline(always)]
+    pub const fn bootkey0_10(self) -> crate::common::Reg<regs::Bootkey010, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(276usize) as _) }
+    }
+    #[doc = "Bits 191:176 of SHA-256 hash of boot key 0 (ECC)"]
+    #[inline(always)]
+    pub const fn bootkey0_11(self) -> crate::common::Reg<regs::Bootkey011, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(278usize) as _) }
+    }
+    #[doc = "Bits 207:192 of SHA-256 hash of boot key 0 (ECC)"]
+    #[inline(always)]
+    pub const fn bootkey0_12(self) -> crate::common::Reg<regs::Bootkey012, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(280usize) as _) }
+    }
+    #[doc = "Bits 223:208 of SHA-256 hash of boot key 0 (ECC)"]
+    #[inline(always)]
+    pub const fn bootkey0_13(self) -> crate::common::Reg<regs::Bootkey013, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(282usize) as _) }
+    }
+    #[doc = "Bits 239:224 of SHA-256 hash of boot key 0 (ECC)"]
+    #[inline(always)]
+    pub const fn bootkey0_14(self) -> crate::common::Reg<regs::Bootkey014, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(284usize) as _) }
+    }
+    #[doc = "Bits 255:240 of SHA-256 hash of boot key 0 (ECC)"]
+    #[inline(always)]
+    pub const fn bootkey0_15(self) -> crate::common::Reg<regs::Bootkey015, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(286usize) as _) }
+    }
+    #[doc = "Bits 15:0 of SHA-256 hash of boot key 1 (ECC)"]
+    #[inline(always)]
+    pub const fn bootkey1_0(self) -> crate::common::Reg<regs::Bootkey10, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(288usize) as _) }
+    }
+    #[doc = "Bits 31:16 of SHA-256 hash of boot key 1 (ECC)"]
+    #[inline(always)]
+    pub const fn bootkey1_1(self) -> crate::common::Reg<regs::Bootkey11, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(290usize) as _) }
+    }
+    #[doc = "Bits 47:32 of SHA-256 hash of boot key 1 (ECC)"]
+    #[inline(always)]
+    pub const fn bootkey1_2(self) -> crate::common::Reg<regs::Bootkey12, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(292usize) as _) }
+    }
+    #[doc = "Bits 63:48 of SHA-256 hash of boot key 1 (ECC)"]
+    #[inline(always)]
+    pub const fn bootkey1_3(self) -> crate::common::Reg<regs::Bootkey13, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(294usize) as _) }
+    }
+    #[doc = "Bits 79:64 of SHA-256 hash of boot key 1 (ECC)"]
+    #[inline(always)]
+    pub const fn bootkey1_4(self) -> crate::common::Reg<regs::Bootkey14, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(296usize) as _) }
+    }
+    #[doc = "Bits 95:80 of SHA-256 hash of boot key 1 (ECC)"]
+    #[inline(always)]
+    pub const fn bootkey1_5(self) -> crate::common::Reg<regs::Bootkey15, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(298usize) as _) }
+    }
+    #[doc = "Bits 111:96 of SHA-256 hash of boot key 1 (ECC)"]
+    #[inline(always)]
+    pub const fn bootkey1_6(self) -> crate::common::Reg<regs::Bootkey16, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(300usize) as _) }
+    }
+    #[doc = "Bits 127:112 of SHA-256 hash of boot key 1 (ECC)"]
+    #[inline(always)]
+    pub const fn bootkey1_7(self) -> crate::common::Reg<regs::Bootkey17, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(302usize) as _) }
+    }
+    #[doc = "Bits 143:128 of SHA-256 hash of boot key 1 (ECC)"]
+    #[inline(always)]
+    pub const fn bootkey1_8(self) -> crate::common::Reg<regs::Bootkey18, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(304usize) as _) }
+    }
+    #[doc = "Bits 159:144 of SHA-256 hash of boot key 1 (ECC)"]
+    #[inline(always)]
+    pub const fn bootkey1_9(self) -> crate::common::Reg<regs::Bootkey19, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(306usize) as _) }
+    }
+    #[doc = "Bits 175:160 of SHA-256 hash of boot key 1 (ECC)"]
+    #[inline(always)]
+    pub const fn bootkey1_10(self) -> crate::common::Reg<regs::Bootkey110, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(308usize) as _) }
+    }
+    #[doc = "Bits 191:176 of SHA-256 hash of boot key 1 (ECC)"]
+    #[inline(always)]
+    pub const fn bootkey1_11(self) -> crate::common::Reg<regs::Bootkey111, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(310usize) as _) }
+    }
+    #[doc = "Bits 207:192 of SHA-256 hash of boot key 1 (ECC)"]
+    #[inline(always)]
+    pub const fn bootkey1_12(self) -> crate::common::Reg<regs::Bootkey112, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(312usize) as _) }
+    }
+    #[doc = "Bits 223:208 of SHA-256 hash of boot key 1 (ECC)"]
+    #[inline(always)]
+    pub const fn bootkey1_13(self) -> crate::common::Reg<regs::Bootkey113, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(314usize) as _) }
+    }
+    #[doc = "Bits 239:224 of SHA-256 hash of boot key 1 (ECC)"]
+    #[inline(always)]
+    pub const fn bootkey1_14(self) -> crate::common::Reg<regs::Bootkey114, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(316usize) as _) }
+    }
+    #[doc = "Bits 255:240 of SHA-256 hash of boot key 1 (ECC)"]
+    #[inline(always)]
+    pub const fn bootkey1_15(self) -> crate::common::Reg<regs::Bootkey115, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(318usize) as _) }
+    }
+    #[doc = "Bits 15:0 of SHA-256 hash of boot key 2 (ECC)"]
+    #[inline(always)]
+    pub const fn bootkey2_0(self) -> crate::common::Reg<regs::Bootkey20, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(320usize) as _) }
+    }
+    #[doc = "Bits 31:16 of SHA-256 hash of boot key 2 (ECC)"]
+    #[inline(always)]
+    pub const fn bootkey2_1(self) -> crate::common::Reg<regs::Bootkey21, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(322usize) as _) }
+    }
+    #[doc = "Bits 47:32 of SHA-256 hash of boot key 2 (ECC)"]
+    #[inline(always)]
+    pub const fn bootkey2_2(self) -> crate::common::Reg<regs::Bootkey22, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(324usize) as _) }
+    }
+    #[doc = "Bits 63:48 of SHA-256 hash of boot key 2 (ECC)"]
+    #[inline(always)]
+    pub const fn bootkey2_3(self) -> crate::common::Reg<regs::Bootkey23, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(326usize) as _) }
+    }
+    #[doc = "Bits 79:64 of SHA-256 hash of boot key 2 (ECC)"]
+    #[inline(always)]
+    pub const fn bootkey2_4(self) -> crate::common::Reg<regs::Bootkey24, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(328usize) as _) }
+    }
+    #[doc = "Bits 95:80 of SHA-256 hash of boot key 2 (ECC)"]
+    #[inline(always)]
+    pub const fn bootkey2_5(self) -> crate::common::Reg<regs::Bootkey25, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(330usize) as _) }
+    }
+    #[doc = "Bits 111:96 of SHA-256 hash of boot key 2 (ECC)"]
+    #[inline(always)]
+    pub const fn bootkey2_6(self) -> crate::common::Reg<regs::Bootkey26, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(332usize) as _) }
+    }
+    #[doc = "Bits 127:112 of SHA-256 hash of boot key 2 (ECC)"]
+    #[inline(always)]
+    pub const fn bootkey2_7(self) -> crate::common::Reg<regs::Bootkey27, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(334usize) as _) }
+    }
+    #[doc = "Bits 143:128 of SHA-256 hash of boot key 2 (ECC)"]
+    #[inline(always)]
+    pub const fn bootkey2_8(self) -> crate::common::Reg<regs::Bootkey28, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(336usize) as _) }
+    }
+    #[doc = "Bits 159:144 of SHA-256 hash of boot key 2 (ECC)"]
+    #[inline(always)]
+    pub const fn bootkey2_9(self) -> crate::common::Reg<regs::Bootkey29, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(338usize) as _) }
+    }
+    #[doc = "Bits 175:160 of SHA-256 hash of boot key 2 (ECC)"]
+    #[inline(always)]
+    pub const fn bootkey2_10(self) -> crate::common::Reg<regs::Bootkey210, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(340usize) as _) }
+    }
+    #[doc = "Bits 191:176 of SHA-256 hash of boot key 2 (ECC)"]
+    #[inline(always)]
+    pub const fn bootkey2_11(self) -> crate::common::Reg<regs::Bootkey211, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(342usize) as _) }
+    }
+    #[doc = "Bits 207:192 of SHA-256 hash of boot key 2 (ECC)"]
+    #[inline(always)]
+    pub const fn bootkey2_12(self) -> crate::common::Reg<regs::Bootkey212, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(344usize) as _) }
+    }
+    #[doc = "Bits 223:208 of SHA-256 hash of boot key 2 (ECC)"]
+    #[inline(always)]
+    pub const fn bootkey2_13(self) -> crate::common::Reg<regs::Bootkey213, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(346usize) as _) }
+    }
+    #[doc = "Bits 239:224 of SHA-256 hash of boot key 2 (ECC)"]
+    #[inline(always)]
+    pub const fn bootkey2_14(self) -> crate::common::Reg<regs::Bootkey214, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(348usize) as _) }
+    }
+    #[doc = "Bits 255:240 of SHA-256 hash of boot key 2 (ECC)"]
+    #[inline(always)]
+    pub const fn bootkey2_15(self) -> crate::common::Reg<regs::Bootkey215, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(350usize) as _) }
+    }
+    #[doc = "Bits 15:0 of SHA-256 hash of boot key 3 (ECC)"]
+    #[inline(always)]
+    pub const fn bootkey3_0(self) -> crate::common::Reg<regs::Bootkey30, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(352usize) as _) }
+    }
+    #[doc = "Bits 31:16 of SHA-256 hash of boot key 3 (ECC)"]
+    #[inline(always)]
+    pub const fn bootkey3_1(self) -> crate::common::Reg<regs::Bootkey31, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(354usize) as _) }
+    }
+    #[doc = "Bits 47:32 of SHA-256 hash of boot key 3 (ECC)"]
+    #[inline(always)]
+    pub const fn bootkey3_2(self) -> crate::common::Reg<regs::Bootkey32, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(356usize) as _) }
+    }
+    #[doc = "Bits 63:48 of SHA-256 hash of boot key 3 (ECC)"]
+    #[inline(always)]
+    pub const fn bootkey3_3(self) -> crate::common::Reg<regs::Bootkey33, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(358usize) as _) }
+    }
+    #[doc = "Bits 79:64 of SHA-256 hash of boot key 3 (ECC)"]
+    #[inline(always)]
+    pub const fn bootkey3_4(self) -> crate::common::Reg<regs::Bootkey34, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(360usize) as _) }
+    }
+    #[doc = "Bits 95:80 of SHA-256 hash of boot key 3 (ECC)"]
+    #[inline(always)]
+    pub const fn bootkey3_5(self) -> crate::common::Reg<regs::Bootkey35, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(362usize) as _) }
+    }
+    #[doc = "Bits 111:96 of SHA-256 hash of boot key 3 (ECC)"]
+    #[inline(always)]
+    pub const fn bootkey3_6(self) -> crate::common::Reg<regs::Bootkey36, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(364usize) as _) }
+    }
+    #[doc = "Bits 127:112 of SHA-256 hash of boot key 3 (ECC)"]
+    #[inline(always)]
+    pub const fn bootkey3_7(self) -> crate::common::Reg<regs::Bootkey37, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(366usize) as _) }
+    }
+    #[doc = "Bits 143:128 of SHA-256 hash of boot key 3 (ECC)"]
+    #[inline(always)]
+    pub const fn bootkey3_8(self) -> crate::common::Reg<regs::Bootkey38, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(368usize) as _) }
+    }
+    #[doc = "Bits 159:144 of SHA-256 hash of boot key 3 (ECC)"]
+    #[inline(always)]
+    pub const fn bootkey3_9(self) -> crate::common::Reg<regs::Bootkey39, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(370usize) as _) }
+    }
+    #[doc = "Bits 175:160 of SHA-256 hash of boot key 3 (ECC)"]
+    #[inline(always)]
+    pub const fn bootkey3_10(self) -> crate::common::Reg<regs::Bootkey310, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(372usize) as _) }
+    }
+    #[doc = "Bits 191:176 of SHA-256 hash of boot key 3 (ECC)"]
+    #[inline(always)]
+    pub const fn bootkey3_11(self) -> crate::common::Reg<regs::Bootkey311, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(374usize) as _) }
+    }
+    #[doc = "Bits 207:192 of SHA-256 hash of boot key 3 (ECC)"]
+    #[inline(always)]
+    pub const fn bootkey3_12(self) -> crate::common::Reg<regs::Bootkey312, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(376usize) as _) }
+    }
+    #[doc = "Bits 223:208 of SHA-256 hash of boot key 3 (ECC)"]
+    #[inline(always)]
+    pub const fn bootkey3_13(self) -> crate::common::Reg<regs::Bootkey313, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(378usize) as _) }
+    }
+    #[doc = "Bits 239:224 of SHA-256 hash of boot key 3 (ECC)"]
+    #[inline(always)]
+    pub const fn bootkey3_14(self) -> crate::common::Reg<regs::Bootkey314, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(380usize) as _) }
+    }
+    #[doc = "Bits 255:240 of SHA-256 hash of boot key 3 (ECC)"]
+    #[inline(always)]
+    pub const fn bootkey3_15(self) -> crate::common::Reg<regs::Bootkey315, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(382usize) as _) }
+    }
+    #[doc = "Bits 15:0 of OTP access key 1 (ECC)"]
+    #[inline(always)]
+    pub const fn key1_0(self) -> crate::common::Reg<regs::Key10, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(7824usize) as _) }
+    }
+    #[doc = "Bits 31:16 of OTP access key 1 (ECC)"]
+    #[inline(always)]
+    pub const fn key1_1(self) -> crate::common::Reg<regs::Key11, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(7826usize) as _) }
+    }
+    #[doc = "Bits 47:32 of OTP access key 1 (ECC)"]
+    #[inline(always)]
+    pub const fn key1_2(self) -> crate::common::Reg<regs::Key12, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(7828usize) as _) }
+    }
+    #[doc = "Bits 63:48 of OTP access key 1 (ECC)"]
+    #[inline(always)]
+    pub const fn key1_3(self) -> crate::common::Reg<regs::Key13, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(7830usize) as _) }
+    }
+    #[doc = "Bits 79:64 of OTP access key 1 (ECC)"]
+    #[inline(always)]
+    pub const fn key1_4(self) -> crate::common::Reg<regs::Key14, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(7832usize) as _) }
+    }
+    #[doc = "Bits 95:80 of OTP access key 1 (ECC)"]
+    #[inline(always)]
+    pub const fn key1_5(self) -> crate::common::Reg<regs::Key15, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(7834usize) as _) }
+    }
+    #[doc = "Bits 111:96 of OTP access key 1 (ECC)"]
+    #[inline(always)]
+    pub const fn key1_6(self) -> crate::common::Reg<regs::Key16, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(7836usize) as _) }
+    }
+    #[doc = "Bits 127:112 of OTP access key 1 (ECC)"]
+    #[inline(always)]
+    pub const fn key1_7(self) -> crate::common::Reg<regs::Key17, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(7838usize) as _) }
+    }
+    #[doc = "Bits 15:0 of OTP access key 2 (ECC)"]
+    #[inline(always)]
+    pub const fn key2_0(self) -> crate::common::Reg<regs::Key20, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(7840usize) as _) }
+    }
+    #[doc = "Bits 31:16 of OTP access key 2 (ECC)"]
+    #[inline(always)]
+    pub const fn key2_1(self) -> crate::common::Reg<regs::Key21, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(7842usize) as _) }
+    }
+    #[doc = "Bits 47:32 of OTP access key 2 (ECC)"]
+    #[inline(always)]
+    pub const fn key2_2(self) -> crate::common::Reg<regs::Key22, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(7844usize) as _) }
+    }
+    #[doc = "Bits 63:48 of OTP access key 2 (ECC)"]
+    #[inline(always)]
+    pub const fn key2_3(self) -> crate::common::Reg<regs::Key23, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(7846usize) as _) }
+    }
+    #[doc = "Bits 79:64 of OTP access key 2 (ECC)"]
+    #[inline(always)]
+    pub const fn key2_4(self) -> crate::common::Reg<regs::Key24, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(7848usize) as _) }
+    }
+    #[doc = "Bits 95:80 of OTP access key 2 (ECC)"]
+    #[inline(always)]
+    pub const fn key2_5(self) -> crate::common::Reg<regs::Key25, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(7850usize) as _) }
+    }
+    #[doc = "Bits 111:96 of OTP access key 2 (ECC)"]
+    #[inline(always)]
+    pub const fn key2_6(self) -> crate::common::Reg<regs::Key26, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(7852usize) as _) }
+    }
+    #[doc = "Bits 127:112 of OTP access key 2 (ECC)"]
+    #[inline(always)]
+    pub const fn key2_7(self) -> crate::common::Reg<regs::Key27, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(7854usize) as _) }
+    }
+    #[doc = "Bits 15:0 of OTP access key 3 (ECC)"]
+    #[inline(always)]
+    pub const fn key3_0(self) -> crate::common::Reg<regs::Key30, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(7856usize) as _) }
+    }
+    #[doc = "Bits 31:16 of OTP access key 3 (ECC)"]
+    #[inline(always)]
+    pub const fn key3_1(self) -> crate::common::Reg<regs::Key31, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(7858usize) as _) }
+    }
+    #[doc = "Bits 47:32 of OTP access key 3 (ECC)"]
+    #[inline(always)]
+    pub const fn key3_2(self) -> crate::common::Reg<regs::Key32, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(7860usize) as _) }
+    }
+    #[doc = "Bits 63:48 of OTP access key 3 (ECC)"]
+    #[inline(always)]
+    pub const fn key3_3(self) -> crate::common::Reg<regs::Key33, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(7862usize) as _) }
+    }
+    #[doc = "Bits 79:64 of OTP access key 3 (ECC)"]
+    #[inline(always)]
+    pub const fn key3_4(self) -> crate::common::Reg<regs::Key34, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(7864usize) as _) }
+    }
+    #[doc = "Bits 95:80 of OTP access key 3 (ECC)"]
+    #[inline(always)]
+    pub const fn key3_5(self) -> crate::common::Reg<regs::Key35, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(7866usize) as _) }
+    }
+    #[doc = "Bits 111:96 of OTP access key 3 (ECC)"]
+    #[inline(always)]
+    pub const fn key3_6(self) -> crate::common::Reg<regs::Key36, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(7868usize) as _) }
+    }
+    #[doc = "Bits 127:112 of OTP access key 3 (ECC)"]
+    #[inline(always)]
+    pub const fn key3_7(self) -> crate::common::Reg<regs::Key37, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(7870usize) as _) }
+    }
+    #[doc = "Bits 15:0 of OTP access key 4 (ECC)"]
+    #[inline(always)]
+    pub const fn key4_0(self) -> crate::common::Reg<regs::Key40, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(7872usize) as _) }
+    }
+    #[doc = "Bits 31:16 of OTP access key 4 (ECC)"]
+    #[inline(always)]
+    pub const fn key4_1(self) -> crate::common::Reg<regs::Key41, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(7874usize) as _) }
+    }
+    #[doc = "Bits 47:32 of OTP access key 4 (ECC)"]
+    #[inline(always)]
+    pub const fn key4_2(self) -> crate::common::Reg<regs::Key42, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(7876usize) as _) }
+    }
+    #[doc = "Bits 63:48 of OTP access key 4 (ECC)"]
+    #[inline(always)]
+    pub const fn key4_3(self) -> crate::common::Reg<regs::Key43, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(7878usize) as _) }
+    }
+    #[doc = "Bits 79:64 of OTP access key 4 (ECC)"]
+    #[inline(always)]
+    pub const fn key4_4(self) -> crate::common::Reg<regs::Key44, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(7880usize) as _) }
+    }
+    #[doc = "Bits 95:80 of OTP access key 4 (ECC)"]
+    #[inline(always)]
+    pub const fn key4_5(self) -> crate::common::Reg<regs::Key45, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(7882usize) as _) }
+    }
+    #[doc = "Bits 111:96 of OTP access key 4 (ECC)"]
+    #[inline(always)]
+    pub const fn key4_6(self) -> crate::common::Reg<regs::Key46, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(7884usize) as _) }
+    }
+    #[doc = "Bits 127:112 of OTP access key 4 (ECC)"]
+    #[inline(always)]
+    pub const fn key4_7(self) -> crate::common::Reg<regs::Key47, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(7886usize) as _) }
+    }
+    #[doc = "Bits 15:0 of OTP access key 5 (ECC)"]
+    #[inline(always)]
+    pub const fn key5_0(self) -> crate::common::Reg<regs::Key50, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(7888usize) as _) }
+    }
+    #[doc = "Bits 31:16 of OTP access key 5 (ECC)"]
+    #[inline(always)]
+    pub const fn key5_1(self) -> crate::common::Reg<regs::Key51, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(7890usize) as _) }
+    }
+    #[doc = "Bits 47:32 of OTP access key 5 (ECC)"]
+    #[inline(always)]
+    pub const fn key5_2(self) -> crate::common::Reg<regs::Key52, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(7892usize) as _) }
+    }
+    #[doc = "Bits 63:48 of OTP access key 5 (ECC)"]
+    #[inline(always)]
+    pub const fn key5_3(self) -> crate::common::Reg<regs::Key53, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(7894usize) as _) }
+    }
+    #[doc = "Bits 79:64 of OTP access key 5 (ECC)"]
+    #[inline(always)]
+    pub const fn key5_4(self) -> crate::common::Reg<regs::Key54, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(7896usize) as _) }
+    }
+    #[doc = "Bits 95:80 of OTP access key 5 (ECC)"]
+    #[inline(always)]
+    pub const fn key5_5(self) -> crate::common::Reg<regs::Key55, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(7898usize) as _) }
+    }
+    #[doc = "Bits 111:96 of OTP access key 5 (ECC)"]
+    #[inline(always)]
+    pub const fn key5_6(self) -> crate::common::Reg<regs::Key56, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(7900usize) as _) }
+    }
+    #[doc = "Bits 127:112 of OTP access key 5 (ECC)"]
+    #[inline(always)]
+    pub const fn key5_7(self) -> crate::common::Reg<regs::Key57, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(7902usize) as _) }
+    }
+    #[doc = "Bits 15:0 of OTP access key 6 (ECC)"]
+    #[inline(always)]
+    pub const fn key6_0(self) -> crate::common::Reg<regs::Key60, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(7904usize) as _) }
+    }
+    #[doc = "Bits 31:16 of OTP access key 6 (ECC)"]
+    #[inline(always)]
+    pub const fn key6_1(self) -> crate::common::Reg<regs::Key61, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(7906usize) as _) }
+    }
+    #[doc = "Bits 47:32 of OTP access key 6 (ECC)"]
+    #[inline(always)]
+    pub const fn key6_2(self) -> crate::common::Reg<regs::Key62, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(7908usize) as _) }
+    }
+    #[doc = "Bits 63:48 of OTP access key 6 (ECC)"]
+    #[inline(always)]
+    pub const fn key6_3(self) -> crate::common::Reg<regs::Key63, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(7910usize) as _) }
+    }
+    #[doc = "Bits 79:64 of OTP access key 6 (ECC)"]
+    #[inline(always)]
+    pub const fn key6_4(self) -> crate::common::Reg<regs::Key64, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(7912usize) as _) }
+    }
+    #[doc = "Bits 95:80 of OTP access key 6 (ECC)"]
+    #[inline(always)]
+    pub const fn key6_5(self) -> crate::common::Reg<regs::Key65, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(7914usize) as _) }
+    }
+    #[doc = "Bits 111:96 of OTP access key 6 (ECC)"]
+    #[inline(always)]
+    pub const fn key6_6(self) -> crate::common::Reg<regs::Key66, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(7916usize) as _) }
+    }
+    #[doc = "Bits 127:112 of OTP access key 6 (ECC)"]
+    #[inline(always)]
+    pub const fn key6_7(self) -> crate::common::Reg<regs::Key67, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(7918usize) as _) }
+    }
+}
+pub mod regs;
+pub mod vals;
diff --git a/src/rp2350/otp_data/regs.rs b/src/rp2350/otp_data/regs.rs
new file mode 100644
index 00000000..6eedcc0a
--- /dev/null
+++ b/src/rp2350/otp_data/regs.rs
@@ -0,0 +1,3015 @@
+#[doc = "Bits 15:0 of SHA-256 hash of boot key 0 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Bootkey00(pub u32);
+impl Bootkey00 {
+    #[inline(always)]
+    pub const fn bootkey0_0(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0xffff;
+        val as u16
+    }
+    #[inline(always)]
+    pub fn set_bootkey0_0(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+    }
+}
+impl Default for Bootkey00 {
+    #[inline(always)]
+    fn default() -> Bootkey00 {
+        Bootkey00(0)
+    }
+}
+#[doc = "Bits 31:16 of SHA-256 hash of boot key 0 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Bootkey01(pub u32);
+impl Bootkey01 {
+    #[inline(always)]
+    pub const fn bootkey0_1(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0xffff;
+        val as u16
+    }
+    #[inline(always)]
+    pub fn set_bootkey0_1(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+    }
+}
+impl Default for Bootkey01 {
+    #[inline(always)]
+    fn default() -> Bootkey01 {
+        Bootkey01(0)
+    }
+}
+#[doc = "Bits 175:160 of SHA-256 hash of boot key 0 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Bootkey010(pub u32);
+impl Bootkey010 {
+    #[inline(always)]
+    pub const fn bootkey0_10(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0xffff;
+        val as u16
+    }
+    #[inline(always)]
+    pub fn set_bootkey0_10(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+    }
+}
+impl Default for Bootkey010 {
+    #[inline(always)]
+    fn default() -> Bootkey010 {
+        Bootkey010(0)
+    }
+}
+#[doc = "Bits 191:176 of SHA-256 hash of boot key 0 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Bootkey011(pub u32);
+impl Bootkey011 {
+    #[inline(always)]
+    pub const fn bootkey0_11(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0xffff;
+        val as u16
+    }
+    #[inline(always)]
+    pub fn set_bootkey0_11(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+    }
+}
+impl Default for Bootkey011 {
+    #[inline(always)]
+    fn default() -> Bootkey011 {
+        Bootkey011(0)
+    }
+}
+#[doc = "Bits 207:192 of SHA-256 hash of boot key 0 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Bootkey012(pub u32);
+impl Bootkey012 {
+    #[inline(always)]
+    pub const fn bootkey0_12(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0xffff;
+        val as u16
+    }
+    #[inline(always)]
+    pub fn set_bootkey0_12(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+    }
+}
+impl Default for Bootkey012 {
+    #[inline(always)]
+    fn default() -> Bootkey012 {
+        Bootkey012(0)
+    }
+}
+#[doc = "Bits 223:208 of SHA-256 hash of boot key 0 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Bootkey013(pub u32);
+impl Bootkey013 {
+    #[inline(always)]
+    pub const fn bootkey0_13(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0xffff;
+        val as u16
+    }
+    #[inline(always)]
+    pub fn set_bootkey0_13(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+    }
+}
+impl Default for Bootkey013 {
+    #[inline(always)]
+    fn default() -> Bootkey013 {
+        Bootkey013(0)
+    }
+}
+#[doc = "Bits 239:224 of SHA-256 hash of boot key 0 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Bootkey014(pub u32);
+impl Bootkey014 {
+    #[inline(always)]
+    pub const fn bootkey0_14(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0xffff;
+        val as u16
+    }
+    #[inline(always)]
+    pub fn set_bootkey0_14(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+    }
+}
+impl Default for Bootkey014 {
+    #[inline(always)]
+    fn default() -> Bootkey014 {
+        Bootkey014(0)
+    }
+}
+#[doc = "Bits 255:240 of SHA-256 hash of boot key 0 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Bootkey015(pub u32);
+impl Bootkey015 {
+    #[inline(always)]
+    pub const fn bootkey0_15(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0xffff;
+        val as u16
+    }
+    #[inline(always)]
+    pub fn set_bootkey0_15(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+    }
+}
+impl Default for Bootkey015 {
+    #[inline(always)]
+    fn default() -> Bootkey015 {
+        Bootkey015(0)
+    }
+}
+#[doc = "Bits 47:32 of SHA-256 hash of boot key 0 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Bootkey02(pub u32);
+impl Bootkey02 {
+    #[inline(always)]
+    pub const fn bootkey0_2(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0xffff;
+        val as u16
+    }
+    #[inline(always)]
+    pub fn set_bootkey0_2(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+    }
+}
+impl Default for Bootkey02 {
+    #[inline(always)]
+    fn default() -> Bootkey02 {
+        Bootkey02(0)
+    }
+}
+#[doc = "Bits 63:48 of SHA-256 hash of boot key 0 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Bootkey03(pub u32);
+impl Bootkey03 {
+    #[inline(always)]
+    pub const fn bootkey0_3(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0xffff;
+        val as u16
+    }
+    #[inline(always)]
+    pub fn set_bootkey0_3(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+    }
+}
+impl Default for Bootkey03 {
+    #[inline(always)]
+    fn default() -> Bootkey03 {
+        Bootkey03(0)
+    }
+}
+#[doc = "Bits 79:64 of SHA-256 hash of boot key 0 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Bootkey04(pub u32);
+impl Bootkey04 {
+    #[inline(always)]
+    pub const fn bootkey0_4(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0xffff;
+        val as u16
+    }
+    #[inline(always)]
+    pub fn set_bootkey0_4(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+    }
+}
+impl Default for Bootkey04 {
+    #[inline(always)]
+    fn default() -> Bootkey04 {
+        Bootkey04(0)
+    }
+}
+#[doc = "Bits 95:80 of SHA-256 hash of boot key 0 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Bootkey05(pub u32);
+impl Bootkey05 {
+    #[inline(always)]
+    pub const fn bootkey0_5(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0xffff;
+        val as u16
+    }
+    #[inline(always)]
+    pub fn set_bootkey0_5(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+    }
+}
+impl Default for Bootkey05 {
+    #[inline(always)]
+    fn default() -> Bootkey05 {
+        Bootkey05(0)
+    }
+}
+#[doc = "Bits 111:96 of SHA-256 hash of boot key 0 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Bootkey06(pub u32);
+impl Bootkey06 {
+    #[inline(always)]
+    pub const fn bootkey0_6(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0xffff;
+        val as u16
+    }
+    #[inline(always)]
+    pub fn set_bootkey0_6(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+    }
+}
+impl Default for Bootkey06 {
+    #[inline(always)]
+    fn default() -> Bootkey06 {
+        Bootkey06(0)
+    }
+}
+#[doc = "Bits 127:112 of SHA-256 hash of boot key 0 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Bootkey07(pub u32);
+impl Bootkey07 {
+    #[inline(always)]
+    pub const fn bootkey0_7(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0xffff;
+        val as u16
+    }
+    #[inline(always)]
+    pub fn set_bootkey0_7(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+    }
+}
+impl Default for Bootkey07 {
+    #[inline(always)]
+    fn default() -> Bootkey07 {
+        Bootkey07(0)
+    }
+}
+#[doc = "Bits 143:128 of SHA-256 hash of boot key 0 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Bootkey08(pub u32);
+impl Bootkey08 {
+    #[inline(always)]
+    pub const fn bootkey0_8(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0xffff;
+        val as u16
+    }
+    #[inline(always)]
+    pub fn set_bootkey0_8(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+    }
+}
+impl Default for Bootkey08 {
+    #[inline(always)]
+    fn default() -> Bootkey08 {
+        Bootkey08(0)
+    }
+}
+#[doc = "Bits 159:144 of SHA-256 hash of boot key 0 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Bootkey09(pub u32);
+impl Bootkey09 {
+    #[inline(always)]
+    pub const fn bootkey0_9(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0xffff;
+        val as u16
+    }
+    #[inline(always)]
+    pub fn set_bootkey0_9(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+    }
+}
+impl Default for Bootkey09 {
+    #[inline(always)]
+    fn default() -> Bootkey09 {
+        Bootkey09(0)
+    }
+}
+#[doc = "Bits 15:0 of SHA-256 hash of boot key 1 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Bootkey10(pub u32);
+impl Bootkey10 {
+    #[inline(always)]
+    pub const fn bootkey1_0(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0xffff;
+        val as u16
+    }
+    #[inline(always)]
+    pub fn set_bootkey1_0(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+    }
+}
+impl Default for Bootkey10 {
+    #[inline(always)]
+    fn default() -> Bootkey10 {
+        Bootkey10(0)
+    }
+}
+#[doc = "Bits 31:16 of SHA-256 hash of boot key 1 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Bootkey11(pub u32);
+impl Bootkey11 {
+    #[inline(always)]
+    pub const fn bootkey1_1(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0xffff;
+        val as u16
+    }
+    #[inline(always)]
+    pub fn set_bootkey1_1(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+    }
+}
+impl Default for Bootkey11 {
+    #[inline(always)]
+    fn default() -> Bootkey11 {
+        Bootkey11(0)
+    }
+}
+#[doc = "Bits 175:160 of SHA-256 hash of boot key 1 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Bootkey110(pub u32);
+impl Bootkey110 {
+    #[inline(always)]
+    pub const fn bootkey1_10(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0xffff;
+        val as u16
+    }
+    #[inline(always)]
+    pub fn set_bootkey1_10(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+    }
+}
+impl Default for Bootkey110 {
+    #[inline(always)]
+    fn default() -> Bootkey110 {
+        Bootkey110(0)
+    }
+}
+#[doc = "Bits 191:176 of SHA-256 hash of boot key 1 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Bootkey111(pub u32);
+impl Bootkey111 {
+    #[inline(always)]
+    pub const fn bootkey1_11(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0xffff;
+        val as u16
+    }
+    #[inline(always)]
+    pub fn set_bootkey1_11(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+    }
+}
+impl Default for Bootkey111 {
+    #[inline(always)]
+    fn default() -> Bootkey111 {
+        Bootkey111(0)
+    }
+}
+#[doc = "Bits 207:192 of SHA-256 hash of boot key 1 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Bootkey112(pub u32);
+impl Bootkey112 {
+    #[inline(always)]
+    pub const fn bootkey1_12(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0xffff;
+        val as u16
+    }
+    #[inline(always)]
+    pub fn set_bootkey1_12(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+    }
+}
+impl Default for Bootkey112 {
+    #[inline(always)]
+    fn default() -> Bootkey112 {
+        Bootkey112(0)
+    }
+}
+#[doc = "Bits 223:208 of SHA-256 hash of boot key 1 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Bootkey113(pub u32);
+impl Bootkey113 {
+    #[inline(always)]
+    pub const fn bootkey1_13(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0xffff;
+        val as u16
+    }
+    #[inline(always)]
+    pub fn set_bootkey1_13(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+    }
+}
+impl Default for Bootkey113 {
+    #[inline(always)]
+    fn default() -> Bootkey113 {
+        Bootkey113(0)
+    }
+}
+#[doc = "Bits 239:224 of SHA-256 hash of boot key 1 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Bootkey114(pub u32);
+impl Bootkey114 {
+    #[inline(always)]
+    pub const fn bootkey1_14(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0xffff;
+        val as u16
+    }
+    #[inline(always)]
+    pub fn set_bootkey1_14(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+    }
+}
+impl Default for Bootkey114 {
+    #[inline(always)]
+    fn default() -> Bootkey114 {
+        Bootkey114(0)
+    }
+}
+#[doc = "Bits 255:240 of SHA-256 hash of boot key 1 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Bootkey115(pub u32);
+impl Bootkey115 {
+    #[inline(always)]
+    pub const fn bootkey1_15(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0xffff;
+        val as u16
+    }
+    #[inline(always)]
+    pub fn set_bootkey1_15(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+    }
+}
+impl Default for Bootkey115 {
+    #[inline(always)]
+    fn default() -> Bootkey115 {
+        Bootkey115(0)
+    }
+}
+#[doc = "Bits 47:32 of SHA-256 hash of boot key 1 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Bootkey12(pub u32);
+impl Bootkey12 {
+    #[inline(always)]
+    pub const fn bootkey1_2(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0xffff;
+        val as u16
+    }
+    #[inline(always)]
+    pub fn set_bootkey1_2(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+    }
+}
+impl Default for Bootkey12 {
+    #[inline(always)]
+    fn default() -> Bootkey12 {
+        Bootkey12(0)
+    }
+}
+#[doc = "Bits 63:48 of SHA-256 hash of boot key 1 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Bootkey13(pub u32);
+impl Bootkey13 {
+    #[inline(always)]
+    pub const fn bootkey1_3(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0xffff;
+        val as u16
+    }
+    #[inline(always)]
+    pub fn set_bootkey1_3(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+    }
+}
+impl Default for Bootkey13 {
+    #[inline(always)]
+    fn default() -> Bootkey13 {
+        Bootkey13(0)
+    }
+}
+#[doc = "Bits 79:64 of SHA-256 hash of boot key 1 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Bootkey14(pub u32);
+impl Bootkey14 {
+    #[inline(always)]
+    pub const fn bootkey1_4(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0xffff;
+        val as u16
+    }
+    #[inline(always)]
+    pub fn set_bootkey1_4(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+    }
+}
+impl Default for Bootkey14 {
+    #[inline(always)]
+    fn default() -> Bootkey14 {
+        Bootkey14(0)
+    }
+}
+#[doc = "Bits 95:80 of SHA-256 hash of boot key 1 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Bootkey15(pub u32);
+impl Bootkey15 {
+    #[inline(always)]
+    pub const fn bootkey1_5(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0xffff;
+        val as u16
+    }
+    #[inline(always)]
+    pub fn set_bootkey1_5(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+    }
+}
+impl Default for Bootkey15 {
+    #[inline(always)]
+    fn default() -> Bootkey15 {
+        Bootkey15(0)
+    }
+}
+#[doc = "Bits 111:96 of SHA-256 hash of boot key 1 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Bootkey16(pub u32);
+impl Bootkey16 {
+    #[inline(always)]
+    pub const fn bootkey1_6(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0xffff;
+        val as u16
+    }
+    #[inline(always)]
+    pub fn set_bootkey1_6(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+    }
+}
+impl Default for Bootkey16 {
+    #[inline(always)]
+    fn default() -> Bootkey16 {
+        Bootkey16(0)
+    }
+}
+#[doc = "Bits 127:112 of SHA-256 hash of boot key 1 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Bootkey17(pub u32);
+impl Bootkey17 {
+    #[inline(always)]
+    pub const fn bootkey1_7(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0xffff;
+        val as u16
+    }
+    #[inline(always)]
+    pub fn set_bootkey1_7(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+    }
+}
+impl Default for Bootkey17 {
+    #[inline(always)]
+    fn default() -> Bootkey17 {
+        Bootkey17(0)
+    }
+}
+#[doc = "Bits 143:128 of SHA-256 hash of boot key 1 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Bootkey18(pub u32);
+impl Bootkey18 {
+    #[inline(always)]
+    pub const fn bootkey1_8(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0xffff;
+        val as u16
+    }
+    #[inline(always)]
+    pub fn set_bootkey1_8(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+    }
+}
+impl Default for Bootkey18 {
+    #[inline(always)]
+    fn default() -> Bootkey18 {
+        Bootkey18(0)
+    }
+}
+#[doc = "Bits 159:144 of SHA-256 hash of boot key 1 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Bootkey19(pub u32);
+impl Bootkey19 {
+    #[inline(always)]
+    pub const fn bootkey1_9(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0xffff;
+        val as u16
+    }
+    #[inline(always)]
+    pub fn set_bootkey1_9(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+    }
+}
+impl Default for Bootkey19 {
+    #[inline(always)]
+    fn default() -> Bootkey19 {
+        Bootkey19(0)
+    }
+}
+#[doc = "Bits 15:0 of SHA-256 hash of boot key 2 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Bootkey20(pub u32);
+impl Bootkey20 {
+    #[inline(always)]
+    pub const fn bootkey2_0(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0xffff;
+        val as u16
+    }
+    #[inline(always)]
+    pub fn set_bootkey2_0(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+    }
+}
+impl Default for Bootkey20 {
+    #[inline(always)]
+    fn default() -> Bootkey20 {
+        Bootkey20(0)
+    }
+}
+#[doc = "Bits 31:16 of SHA-256 hash of boot key 2 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Bootkey21(pub u32);
+impl Bootkey21 {
+    #[inline(always)]
+    pub const fn bootkey2_1(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0xffff;
+        val as u16
+    }
+    #[inline(always)]
+    pub fn set_bootkey2_1(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+    }
+}
+impl Default for Bootkey21 {
+    #[inline(always)]
+    fn default() -> Bootkey21 {
+        Bootkey21(0)
+    }
+}
+#[doc = "Bits 175:160 of SHA-256 hash of boot key 2 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Bootkey210(pub u32);
+impl Bootkey210 {
+    #[inline(always)]
+    pub const fn bootkey2_10(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0xffff;
+        val as u16
+    }
+    #[inline(always)]
+    pub fn set_bootkey2_10(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+    }
+}
+impl Default for Bootkey210 {
+    #[inline(always)]
+    fn default() -> Bootkey210 {
+        Bootkey210(0)
+    }
+}
+#[doc = "Bits 191:176 of SHA-256 hash of boot key 2 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Bootkey211(pub u32);
+impl Bootkey211 {
+    #[inline(always)]
+    pub const fn bootkey2_11(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0xffff;
+        val as u16
+    }
+    #[inline(always)]
+    pub fn set_bootkey2_11(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+    }
+}
+impl Default for Bootkey211 {
+    #[inline(always)]
+    fn default() -> Bootkey211 {
+        Bootkey211(0)
+    }
+}
+#[doc = "Bits 207:192 of SHA-256 hash of boot key 2 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Bootkey212(pub u32);
+impl Bootkey212 {
+    #[inline(always)]
+    pub const fn bootkey2_12(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0xffff;
+        val as u16
+    }
+    #[inline(always)]
+    pub fn set_bootkey2_12(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+    }
+}
+impl Default for Bootkey212 {
+    #[inline(always)]
+    fn default() -> Bootkey212 {
+        Bootkey212(0)
+    }
+}
+#[doc = "Bits 223:208 of SHA-256 hash of boot key 2 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Bootkey213(pub u32);
+impl Bootkey213 {
+    #[inline(always)]
+    pub const fn bootkey2_13(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0xffff;
+        val as u16
+    }
+    #[inline(always)]
+    pub fn set_bootkey2_13(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+    }
+}
+impl Default for Bootkey213 {
+    #[inline(always)]
+    fn default() -> Bootkey213 {
+        Bootkey213(0)
+    }
+}
+#[doc = "Bits 239:224 of SHA-256 hash of boot key 2 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Bootkey214(pub u32);
+impl Bootkey214 {
+    #[inline(always)]
+    pub const fn bootkey2_14(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0xffff;
+        val as u16
+    }
+    #[inline(always)]
+    pub fn set_bootkey2_14(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+    }
+}
+impl Default for Bootkey214 {
+    #[inline(always)]
+    fn default() -> Bootkey214 {
+        Bootkey214(0)
+    }
+}
+#[doc = "Bits 255:240 of SHA-256 hash of boot key 2 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Bootkey215(pub u32);
+impl Bootkey215 {
+    #[inline(always)]
+    pub const fn bootkey2_15(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0xffff;
+        val as u16
+    }
+    #[inline(always)]
+    pub fn set_bootkey2_15(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+    }
+}
+impl Default for Bootkey215 {
+    #[inline(always)]
+    fn default() -> Bootkey215 {
+        Bootkey215(0)
+    }
+}
+#[doc = "Bits 47:32 of SHA-256 hash of boot key 2 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Bootkey22(pub u32);
+impl Bootkey22 {
+    #[inline(always)]
+    pub const fn bootkey2_2(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0xffff;
+        val as u16
+    }
+    #[inline(always)]
+    pub fn set_bootkey2_2(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+    }
+}
+impl Default for Bootkey22 {
+    #[inline(always)]
+    fn default() -> Bootkey22 {
+        Bootkey22(0)
+    }
+}
+#[doc = "Bits 63:48 of SHA-256 hash of boot key 2 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Bootkey23(pub u32);
+impl Bootkey23 {
+    #[inline(always)]
+    pub const fn bootkey2_3(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0xffff;
+        val as u16
+    }
+    #[inline(always)]
+    pub fn set_bootkey2_3(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+    }
+}
+impl Default for Bootkey23 {
+    #[inline(always)]
+    fn default() -> Bootkey23 {
+        Bootkey23(0)
+    }
+}
+#[doc = "Bits 79:64 of SHA-256 hash of boot key 2 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Bootkey24(pub u32);
+impl Bootkey24 {
+    #[inline(always)]
+    pub const fn bootkey2_4(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0xffff;
+        val as u16
+    }
+    #[inline(always)]
+    pub fn set_bootkey2_4(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+    }
+}
+impl Default for Bootkey24 {
+    #[inline(always)]
+    fn default() -> Bootkey24 {
+        Bootkey24(0)
+    }
+}
+#[doc = "Bits 95:80 of SHA-256 hash of boot key 2 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Bootkey25(pub u32);
+impl Bootkey25 {
+    #[inline(always)]
+    pub const fn bootkey2_5(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0xffff;
+        val as u16
+    }
+    #[inline(always)]
+    pub fn set_bootkey2_5(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+    }
+}
+impl Default for Bootkey25 {
+    #[inline(always)]
+    fn default() -> Bootkey25 {
+        Bootkey25(0)
+    }
+}
+#[doc = "Bits 111:96 of SHA-256 hash of boot key 2 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Bootkey26(pub u32);
+impl Bootkey26 {
+    #[inline(always)]
+    pub const fn bootkey2_6(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0xffff;
+        val as u16
+    }
+    #[inline(always)]
+    pub fn set_bootkey2_6(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+    }
+}
+impl Default for Bootkey26 {
+    #[inline(always)]
+    fn default() -> Bootkey26 {
+        Bootkey26(0)
+    }
+}
+#[doc = "Bits 127:112 of SHA-256 hash of boot key 2 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Bootkey27(pub u32);
+impl Bootkey27 {
+    #[inline(always)]
+    pub const fn bootkey2_7(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0xffff;
+        val as u16
+    }
+    #[inline(always)]
+    pub fn set_bootkey2_7(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+    }
+}
+impl Default for Bootkey27 {
+    #[inline(always)]
+    fn default() -> Bootkey27 {
+        Bootkey27(0)
+    }
+}
+#[doc = "Bits 143:128 of SHA-256 hash of boot key 2 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Bootkey28(pub u32);
+impl Bootkey28 {
+    #[inline(always)]
+    pub const fn bootkey2_8(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0xffff;
+        val as u16
+    }
+    #[inline(always)]
+    pub fn set_bootkey2_8(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+    }
+}
+impl Default for Bootkey28 {
+    #[inline(always)]
+    fn default() -> Bootkey28 {
+        Bootkey28(0)
+    }
+}
+#[doc = "Bits 159:144 of SHA-256 hash of boot key 2 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Bootkey29(pub u32);
+impl Bootkey29 {
+    #[inline(always)]
+    pub const fn bootkey2_9(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0xffff;
+        val as u16
+    }
+    #[inline(always)]
+    pub fn set_bootkey2_9(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+    }
+}
+impl Default for Bootkey29 {
+    #[inline(always)]
+    fn default() -> Bootkey29 {
+        Bootkey29(0)
+    }
+}
+#[doc = "Bits 15:0 of SHA-256 hash of boot key 3 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Bootkey30(pub u32);
+impl Bootkey30 {
+    #[inline(always)]
+    pub const fn bootkey3_0(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0xffff;
+        val as u16
+    }
+    #[inline(always)]
+    pub fn set_bootkey3_0(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+    }
+}
+impl Default for Bootkey30 {
+    #[inline(always)]
+    fn default() -> Bootkey30 {
+        Bootkey30(0)
+    }
+}
+#[doc = "Bits 31:16 of SHA-256 hash of boot key 3 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Bootkey31(pub u32);
+impl Bootkey31 {
+    #[inline(always)]
+    pub const fn bootkey3_1(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0xffff;
+        val as u16
+    }
+    #[inline(always)]
+    pub fn set_bootkey3_1(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+    }
+}
+impl Default for Bootkey31 {
+    #[inline(always)]
+    fn default() -> Bootkey31 {
+        Bootkey31(0)
+    }
+}
+#[doc = "Bits 175:160 of SHA-256 hash of boot key 3 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Bootkey310(pub u32);
+impl Bootkey310 {
+    #[inline(always)]
+    pub const fn bootkey3_10(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0xffff;
+        val as u16
+    }
+    #[inline(always)]
+    pub fn set_bootkey3_10(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+    }
+}
+impl Default for Bootkey310 {
+    #[inline(always)]
+    fn default() -> Bootkey310 {
+        Bootkey310(0)
+    }
+}
+#[doc = "Bits 191:176 of SHA-256 hash of boot key 3 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Bootkey311(pub u32);
+impl Bootkey311 {
+    #[inline(always)]
+    pub const fn bootkey3_11(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0xffff;
+        val as u16
+    }
+    #[inline(always)]
+    pub fn set_bootkey3_11(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+    }
+}
+impl Default for Bootkey311 {
+    #[inline(always)]
+    fn default() -> Bootkey311 {
+        Bootkey311(0)
+    }
+}
+#[doc = "Bits 207:192 of SHA-256 hash of boot key 3 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Bootkey312(pub u32);
+impl Bootkey312 {
+    #[inline(always)]
+    pub const fn bootkey3_12(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0xffff;
+        val as u16
+    }
+    #[inline(always)]
+    pub fn set_bootkey3_12(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+    }
+}
+impl Default for Bootkey312 {
+    #[inline(always)]
+    fn default() -> Bootkey312 {
+        Bootkey312(0)
+    }
+}
+#[doc = "Bits 223:208 of SHA-256 hash of boot key 3 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Bootkey313(pub u32);
+impl Bootkey313 {
+    #[inline(always)]
+    pub const fn bootkey3_13(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0xffff;
+        val as u16
+    }
+    #[inline(always)]
+    pub fn set_bootkey3_13(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+    }
+}
+impl Default for Bootkey313 {
+    #[inline(always)]
+    fn default() -> Bootkey313 {
+        Bootkey313(0)
+    }
+}
+#[doc = "Bits 239:224 of SHA-256 hash of boot key 3 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Bootkey314(pub u32);
+impl Bootkey314 {
+    #[inline(always)]
+    pub const fn bootkey3_14(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0xffff;
+        val as u16
+    }
+    #[inline(always)]
+    pub fn set_bootkey3_14(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+    }
+}
+impl Default for Bootkey314 {
+    #[inline(always)]
+    fn default() -> Bootkey314 {
+        Bootkey314(0)
+    }
+}
+#[doc = "Bits 255:240 of SHA-256 hash of boot key 3 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Bootkey315(pub u32);
+impl Bootkey315 {
+    #[inline(always)]
+    pub const fn bootkey3_15(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0xffff;
+        val as u16
+    }
+    #[inline(always)]
+    pub fn set_bootkey3_15(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+    }
+}
+impl Default for Bootkey315 {
+    #[inline(always)]
+    fn default() -> Bootkey315 {
+        Bootkey315(0)
+    }
+}
+#[doc = "Bits 47:32 of SHA-256 hash of boot key 3 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Bootkey32(pub u32);
+impl Bootkey32 {
+    #[inline(always)]
+    pub const fn bootkey3_2(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0xffff;
+        val as u16
+    }
+    #[inline(always)]
+    pub fn set_bootkey3_2(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+    }
+}
+impl Default for Bootkey32 {
+    #[inline(always)]
+    fn default() -> Bootkey32 {
+        Bootkey32(0)
+    }
+}
+#[doc = "Bits 63:48 of SHA-256 hash of boot key 3 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Bootkey33(pub u32);
+impl Bootkey33 {
+    #[inline(always)]
+    pub const fn bootkey3_3(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0xffff;
+        val as u16
+    }
+    #[inline(always)]
+    pub fn set_bootkey3_3(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+    }
+}
+impl Default for Bootkey33 {
+    #[inline(always)]
+    fn default() -> Bootkey33 {
+        Bootkey33(0)
+    }
+}
+#[doc = "Bits 79:64 of SHA-256 hash of boot key 3 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Bootkey34(pub u32);
+impl Bootkey34 {
+    #[inline(always)]
+    pub const fn bootkey3_4(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0xffff;
+        val as u16
+    }
+    #[inline(always)]
+    pub fn set_bootkey3_4(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+    }
+}
+impl Default for Bootkey34 {
+    #[inline(always)]
+    fn default() -> Bootkey34 {
+        Bootkey34(0)
+    }
+}
+#[doc = "Bits 95:80 of SHA-256 hash of boot key 3 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Bootkey35(pub u32);
+impl Bootkey35 {
+    #[inline(always)]
+    pub const fn bootkey3_5(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0xffff;
+        val as u16
+    }
+    #[inline(always)]
+    pub fn set_bootkey3_5(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+    }
+}
+impl Default for Bootkey35 {
+    #[inline(always)]
+    fn default() -> Bootkey35 {
+        Bootkey35(0)
+    }
+}
+#[doc = "Bits 111:96 of SHA-256 hash of boot key 3 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Bootkey36(pub u32);
+impl Bootkey36 {
+    #[inline(always)]
+    pub const fn bootkey3_6(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0xffff;
+        val as u16
+    }
+    #[inline(always)]
+    pub fn set_bootkey3_6(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+    }
+}
+impl Default for Bootkey36 {
+    #[inline(always)]
+    fn default() -> Bootkey36 {
+        Bootkey36(0)
+    }
+}
+#[doc = "Bits 127:112 of SHA-256 hash of boot key 3 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Bootkey37(pub u32);
+impl Bootkey37 {
+    #[inline(always)]
+    pub const fn bootkey3_7(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0xffff;
+        val as u16
+    }
+    #[inline(always)]
+    pub fn set_bootkey3_7(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+    }
+}
+impl Default for Bootkey37 {
+    #[inline(always)]
+    fn default() -> Bootkey37 {
+        Bootkey37(0)
+    }
+}
+#[doc = "Bits 143:128 of SHA-256 hash of boot key 3 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Bootkey38(pub u32);
+impl Bootkey38 {
+    #[inline(always)]
+    pub const fn bootkey3_8(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0xffff;
+        val as u16
+    }
+    #[inline(always)]
+    pub fn set_bootkey3_8(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+    }
+}
+impl Default for Bootkey38 {
+    #[inline(always)]
+    fn default() -> Bootkey38 {
+        Bootkey38(0)
+    }
+}
+#[doc = "Bits 159:144 of SHA-256 hash of boot key 3 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Bootkey39(pub u32);
+impl Bootkey39 {
+    #[inline(always)]
+    pub const fn bootkey3_9(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0xffff;
+        val as u16
+    }
+    #[inline(always)]
+    pub fn set_bootkey3_9(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+    }
+}
+impl Default for Bootkey39 {
+    #[inline(always)]
+    fn default() -> Bootkey39 {
+        Bootkey39(0)
+    }
+}
+#[doc = "Pin configuration for LED status, used by USB bootloader. (ECC) Must be valid if BOOT_FLAGS0_ENABLE_BOOTSEL_LED is set."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct BootselLedCfg(pub u32);
+impl BootselLedCfg {
+    #[doc = "GPIO index to use for bootloader activity LED."]
+    #[inline(always)]
+    pub const fn pin(&self) -> u8 {
+        let val = (self.0 >> 0usize) & 0x3f;
+        val as u8
+    }
+    #[doc = "GPIO index to use for bootloader activity LED."]
+    #[inline(always)]
+    pub fn set_pin(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x3f << 0usize)) | (((val as u32) & 0x3f) << 0usize);
+    }
+    #[doc = "LED is active-low. (Default: active-high.)"]
+    #[inline(always)]
+    pub const fn activelow(&self) -> bool {
+        let val = (self.0 >> 8usize) & 0x01;
+        val != 0
+    }
+    #[doc = "LED is active-low. (Default: active-high.)"]
+    #[inline(always)]
+    pub fn set_activelow(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
+    }
+}
+impl Default for BootselLedCfg {
+    #[inline(always)]
+    fn default() -> BootselLedCfg {
+        BootselLedCfg(0)
+    }
+}
+#[doc = "Optional PLL configuration for BOOTSEL mode. (ECC) This should be configured to produce an exact 48 MHz based on the crystal oscillator frequency. User mode software may also use this value to calculate the expected crystal frequency based on an assumed 48 MHz PLL output. If no configuration is given, the crystal is assumed to be 12 MHz. The PLL frequency can be calculated as: PLL out = (XOSC frequency / (REFDIV+1)) x FBDIV / (POSTDIV1 x POSTDIV2) Conversely the crystal frequency can be calculated as: XOSC frequency = 48 MHz x (REFDIV+1) x (POSTDIV1 x POSTDIV2) / FBDIV (Note the +1 on REFDIV is because the value stored in this OTP location is the actual divisor value minus one.) Used if and only if ENABLE_BOOTSEL_NON_DEFAULT_PLL_XOSC_CFG is set in BOOT_FLAGS0. That bit should be set only after this row and BOOTSEL_XOSC_CFG are both correctly programmed."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct BootselPllCfg(pub u32);
+impl BootselPllCfg {
+    #[doc = "PLL feedback divisor, in the range 16..320 inclusive."]
+    #[inline(always)]
+    pub const fn fbdiv(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0x01ff;
+        val as u16
+    }
+    #[doc = "PLL feedback divisor, in the range 16..320 inclusive."]
+    #[inline(always)]
+    pub fn set_fbdiv(&mut self, val: u16) {
+        self.0 = (self.0 & !(0x01ff << 0usize)) | (((val as u32) & 0x01ff) << 0usize);
+    }
+    #[doc = "PLL post-divide 1 divisor, in the range 1..7 inclusive."]
+    #[inline(always)]
+    pub const fn postdiv1(&self) -> u8 {
+        let val = (self.0 >> 9usize) & 0x07;
+        val as u8
+    }
+    #[doc = "PLL post-divide 1 divisor, in the range 1..7 inclusive."]
+    #[inline(always)]
+    pub fn set_postdiv1(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x07 << 9usize)) | (((val as u32) & 0x07) << 9usize);
+    }
+    #[doc = "PLL post-divide 2 divisor, in the range 1..7 inclusive."]
+    #[inline(always)]
+    pub const fn postdiv2(&self) -> u8 {
+        let val = (self.0 >> 12usize) & 0x07;
+        val as u8
+    }
+    #[doc = "PLL post-divide 2 divisor, in the range 1..7 inclusive."]
+    #[inline(always)]
+    pub fn set_postdiv2(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x07 << 12usize)) | (((val as u32) & 0x07) << 12usize);
+    }
+    #[doc = "PLL reference divisor, minus one. Programming a value of 0 means a reference divisor of 1. Programming a value of 1 means a reference divisor of 2 (for exceptionally fast XIN inputs)"]
+    #[inline(always)]
+    pub const fn refdiv(&self) -> bool {
+        let val = (self.0 >> 15usize) & 0x01;
+        val != 0
+    }
+    #[doc = "PLL reference divisor, minus one. Programming a value of 0 means a reference divisor of 1. Programming a value of 1 means a reference divisor of 2 (for exceptionally fast XIN inputs)"]
+    #[inline(always)]
+    pub fn set_refdiv(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize);
+    }
+}
+impl Default for BootselPllCfg {
+    #[inline(always)]
+    fn default() -> BootselPllCfg {
+        BootselPllCfg(0)
+    }
+}
+#[doc = "Non-default crystal oscillator configuration for the USB bootloader. (ECC) These values may also be used by user code configuring the crystal oscillator. Used if and only if ENABLE_BOOTSEL_NON_DEFAULT_PLL_XOSC_CFG is set in BOOT_FLAGS0. That bit should be set only after this row and BOOTSEL_PLL_CFG are both correctly programmed."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct BootselXoscCfg(pub u32);
+impl BootselXoscCfg {
+    #[doc = "Value of the XOSC_STARTUP register"]
+    #[inline(always)]
+    pub const fn startup(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0x3fff;
+        val as u16
+    }
+    #[doc = "Value of the XOSC_STARTUP register"]
+    #[inline(always)]
+    pub fn set_startup(&mut self, val: u16) {
+        self.0 = (self.0 & !(0x3fff << 0usize)) | (((val as u32) & 0x3fff) << 0usize);
+    }
+    #[doc = "Value of the XOSC_CTRL_FREQ_RANGE register."]
+    #[inline(always)]
+    pub const fn range(&self) -> super::vals::Range {
+        let val = (self.0 >> 14usize) & 0x03;
+        super::vals::Range::from_bits(val as u8)
+    }
+    #[doc = "Value of the XOSC_CTRL_FREQ_RANGE register."]
+    #[inline(always)]
+    pub fn set_range(&mut self, val: super::vals::Range) {
+        self.0 = (self.0 & !(0x03 << 14usize)) | (((val.to_bits() as u32) & 0x03) << 14usize);
+    }
+}
+impl Default for BootselXoscCfg {
+    #[inline(always)]
+    fn default() -> BootselXoscCfg {
+        BootselXoscCfg(0)
+    }
+}
+#[doc = "Bits 15:0 of public device ID. (ECC) The CHIPID0..3 rows contain a 64-bit random identifier for this chip, which can be read from the USB bootloader PICOBOOT interface or from the get_sys_info ROM API. The number of random bits makes the occurrence of twins exceedingly unlikely: for example, a fleet of a hundred million devices has a 99.97% probability of no twinned IDs. This is estimated to be lower than the occurrence of process errors in the assignment of sequential random IDs, and for practical purposes CHIPID may be treated as unique."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Chipid0(pub u32);
+impl Chipid0 {
+    #[inline(always)]
+    pub const fn chipid0(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0xffff;
+        val as u16
+    }
+    #[inline(always)]
+    pub fn set_chipid0(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+    }
+}
+impl Default for Chipid0 {
+    #[inline(always)]
+    fn default() -> Chipid0 {
+        Chipid0(0)
+    }
+}
+#[doc = "Bits 31:16 of public device ID (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Chipid1(pub u32);
+impl Chipid1 {
+    #[inline(always)]
+    pub const fn chipid1(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0xffff;
+        val as u16
+    }
+    #[inline(always)]
+    pub fn set_chipid1(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+    }
+}
+impl Default for Chipid1 {
+    #[inline(always)]
+    fn default() -> Chipid1 {
+        Chipid1(0)
+    }
+}
+#[doc = "Bits 47:32 of public device ID (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Chipid2(pub u32);
+impl Chipid2 {
+    #[inline(always)]
+    pub const fn chipid2(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0xffff;
+        val as u16
+    }
+    #[inline(always)]
+    pub fn set_chipid2(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+    }
+}
+impl Default for Chipid2 {
+    #[inline(always)]
+    fn default() -> Chipid2 {
+        Chipid2(0)
+    }
+}
+#[doc = "Bits 63:48 of public device ID (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Chipid3(pub u32);
+impl Chipid3 {
+    #[inline(always)]
+    pub const fn chipid3(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0xffff;
+        val as u16
+    }
+    #[inline(always)]
+    pub fn set_chipid3(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+    }
+}
+impl Default for Chipid3 {
+    #[inline(always)]
+    fn default() -> Chipid3 {
+        Chipid3(0)
+    }
+}
+#[doc = "Stores information about external flash device(s). (ECC) Assumed to be valid if BOOT_FLAGS0_FLASH_DEVINFO_ENABLE is set."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct FlashDevinfo(pub u32);
+impl FlashDevinfo {
+    #[doc = "Indicate a GPIO number to be used for the secondary flash chip select (CS1), which selects the external QSPI device mapped at system addresses 0x11000000 through 0x11ffffff. There is no such configuration for CS0, as the primary chip select has a dedicated pin. On RP2350 the permissible GPIO numbers are 0, 8, 19 and 47. Ignored if CS1_size is zero. If CS1_SIZE is nonzero, the bootrom will automatically configure this GPIO as a second chip select upon entering the flash boot path, or entering any other path that may use the QSPI flash interface, such as BOOTSEL mode (nsboot)."]
+    #[inline(always)]
+    pub const fn cs1_gpio(&self) -> u8 {
+        let val = (self.0 >> 0usize) & 0x3f;
+        val as u8
+    }
+    #[doc = "Indicate a GPIO number to be used for the secondary flash chip select (CS1), which selects the external QSPI device mapped at system addresses 0x11000000 through 0x11ffffff. There is no such configuration for CS0, as the primary chip select has a dedicated pin. On RP2350 the permissible GPIO numbers are 0, 8, 19 and 47. Ignored if CS1_size is zero. If CS1_SIZE is nonzero, the bootrom will automatically configure this GPIO as a second chip select upon entering the flash boot path, or entering any other path that may use the QSPI flash interface, such as BOOTSEL mode (nsboot)."]
+    #[inline(always)]
+    pub fn set_cs1_gpio(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x3f << 0usize)) | (((val as u32) & 0x3f) << 0usize);
+    }
+    #[doc = "If true, all attached devices are assumed to support (or ignore, in the case of PSRAM) a block erase command with a command prefix of D8h, an erase size of 64 kiB, and a 24-bit address. Almost all 25-series flash devices support this command. If set, the bootrom will use the D8h erase command where it is able, to accelerate bulk erase operations. This makes flash programming faster. When BOOT_FLAGS0_FLASH_DEVINFO_ENABLE is not set, this field defaults to false."]
+    #[inline(always)]
+    pub const fn d8h_erase_supported(&self) -> bool {
+        let val = (self.0 >> 7usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If true, all attached devices are assumed to support (or ignore, in the case of PSRAM) a block erase command with a command prefix of D8h, an erase size of 64 kiB, and a 24-bit address. Almost all 25-series flash devices support this command. If set, the bootrom will use the D8h erase command where it is able, to accelerate bulk erase operations. This makes flash programming faster. When BOOT_FLAGS0_FLASH_DEVINFO_ENABLE is not set, this field defaults to false."]
+    #[inline(always)]
+    pub fn set_d8h_erase_supported(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
+    }
+    #[doc = "The size of the flash/PSRAM device on chip select 0 (addressable at 0x10000000 through 0x10ffffff). A value of zero is decoded as a size of zero (no device). Nonzero values are decoded as 4kiB << CS0_SIZE. For example, four megabytes is encoded with a CS0_SIZE value of 10, and 16 megabytes is encoded with a CS0_SIZE value of 12. When BOOT_FLAGS0_FLASH_DEVINFO_ENABLE is not set, a default of 12 (16 MiB) is used."]
+    #[inline(always)]
+    pub const fn cs0_size(&self) -> super::vals::Cs0size {
+        let val = (self.0 >> 8usize) & 0x0f;
+        super::vals::Cs0size::from_bits(val as u8)
+    }
+    #[doc = "The size of the flash/PSRAM device on chip select 0 (addressable at 0x10000000 through 0x10ffffff). A value of zero is decoded as a size of zero (no device). Nonzero values are decoded as 4kiB << CS0_SIZE. For example, four megabytes is encoded with a CS0_SIZE value of 10, and 16 megabytes is encoded with a CS0_SIZE value of 12. When BOOT_FLAGS0_FLASH_DEVINFO_ENABLE is not set, a default of 12 (16 MiB) is used."]
+    #[inline(always)]
+    pub fn set_cs0_size(&mut self, val: super::vals::Cs0size) {
+        self.0 = (self.0 & !(0x0f << 8usize)) | (((val.to_bits() as u32) & 0x0f) << 8usize);
+    }
+    #[doc = "The size of the flash/PSRAM device on chip select 1 (addressable at 0x11000000 through 0x11ffffff). A value of zero is decoded as a size of zero (no device). Nonzero values are decoded as 4kiB << CS1_SIZE. For example, four megabytes is encoded with a CS1_SIZE value of 10, and 16 megabytes is encoded with a CS1_SIZE value of 12. When BOOT_FLAGS0_FLASH_DEVINFO_ENABLE is not set, a default of zero is used."]
+    #[inline(always)]
+    pub const fn cs1_size(&self) -> super::vals::Cs1size {
+        let val = (self.0 >> 12usize) & 0x0f;
+        super::vals::Cs1size::from_bits(val as u8)
+    }
+    #[doc = "The size of the flash/PSRAM device on chip select 1 (addressable at 0x11000000 through 0x11ffffff). A value of zero is decoded as a size of zero (no device). Nonzero values are decoded as 4kiB << CS1_SIZE. For example, four megabytes is encoded with a CS1_SIZE value of 10, and 16 megabytes is encoded with a CS1_SIZE value of 12. When BOOT_FLAGS0_FLASH_DEVINFO_ENABLE is not set, a default of zero is used."]
+    #[inline(always)]
+    pub fn set_cs1_size(&mut self, val: super::vals::Cs1size) {
+        self.0 = (self.0 & !(0x0f << 12usize)) | (((val.to_bits() as u32) & 0x0f) << 12usize);
+    }
+}
+impl Default for FlashDevinfo {
+    #[inline(always)]
+    fn default() -> FlashDevinfo {
+        FlashDevinfo(0)
+    }
+}
+#[doc = "Gap between partition table slot 0 and slot 1 at the start of flash (the default size is 4096 bytes) (ECC) Enabled by the OVERRIDE_FLASH_PARTITION_SLOT_SIZE bit in BOOT_FLAGS, the size is 4096 * (value + 1)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct FlashPartitionSlotSize(pub u32);
+impl FlashPartitionSlotSize {
+    #[inline(always)]
+    pub const fn flash_partition_slot_size(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0xffff;
+        val as u16
+    }
+    #[inline(always)]
+    pub fn set_flash_partition_slot_size(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+    }
+}
+impl Default for FlashPartitionSlotSize {
+    #[inline(always)]
+    fn default() -> FlashPartitionSlotSize {
+        FlashPartitionSlotSize(0)
+    }
+}
+#[doc = "Lower 16 bits of CRC32 of OTP addresses 0x00 through 0x6b (polynomial 0x4c11db7, input reflected, output reflected, seed all-ones, final XOR all-ones) (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct InfoCrc0(pub u32);
+impl InfoCrc0 {
+    #[inline(always)]
+    pub const fn info_crc0(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0xffff;
+        val as u16
+    }
+    #[inline(always)]
+    pub fn set_info_crc0(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+    }
+}
+impl Default for InfoCrc0 {
+    #[inline(always)]
+    fn default() -> InfoCrc0 {
+        InfoCrc0(0)
+    }
+}
+#[doc = "Upper 16 bits of CRC32 of OTP addresses 0x00 through 0x6b (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct InfoCrc1(pub u32);
+impl InfoCrc1 {
+    #[inline(always)]
+    pub const fn info_crc1(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0xffff;
+        val as u16
+    }
+    #[inline(always)]
+    pub fn set_info_crc1(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+    }
+}
+impl Default for InfoCrc1 {
+    #[inline(always)]
+    fn default() -> InfoCrc1 {
+        InfoCrc1(0)
+    }
+}
+#[doc = "Bits 15:0 of OTP access key 1 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Key10(pub u32);
+impl Key10 {
+    #[inline(always)]
+    pub const fn key1_0(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0xffff;
+        val as u16
+    }
+    #[inline(always)]
+    pub fn set_key1_0(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+    }
+}
+impl Default for Key10 {
+    #[inline(always)]
+    fn default() -> Key10 {
+        Key10(0)
+    }
+}
+#[doc = "Bits 31:16 of OTP access key 1 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Key11(pub u32);
+impl Key11 {
+    #[inline(always)]
+    pub const fn key1_1(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0xffff;
+        val as u16
+    }
+    #[inline(always)]
+    pub fn set_key1_1(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+    }
+}
+impl Default for Key11 {
+    #[inline(always)]
+    fn default() -> Key11 {
+        Key11(0)
+    }
+}
+#[doc = "Bits 47:32 of OTP access key 1 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Key12(pub u32);
+impl Key12 {
+    #[inline(always)]
+    pub const fn key1_2(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0xffff;
+        val as u16
+    }
+    #[inline(always)]
+    pub fn set_key1_2(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+    }
+}
+impl Default for Key12 {
+    #[inline(always)]
+    fn default() -> Key12 {
+        Key12(0)
+    }
+}
+#[doc = "Bits 63:48 of OTP access key 1 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Key13(pub u32);
+impl Key13 {
+    #[inline(always)]
+    pub const fn key1_3(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0xffff;
+        val as u16
+    }
+    #[inline(always)]
+    pub fn set_key1_3(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+    }
+}
+impl Default for Key13 {
+    #[inline(always)]
+    fn default() -> Key13 {
+        Key13(0)
+    }
+}
+#[doc = "Bits 79:64 of OTP access key 1 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Key14(pub u32);
+impl Key14 {
+    #[inline(always)]
+    pub const fn key1_4(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0xffff;
+        val as u16
+    }
+    #[inline(always)]
+    pub fn set_key1_4(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+    }
+}
+impl Default for Key14 {
+    #[inline(always)]
+    fn default() -> Key14 {
+        Key14(0)
+    }
+}
+#[doc = "Bits 95:80 of OTP access key 1 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Key15(pub u32);
+impl Key15 {
+    #[inline(always)]
+    pub const fn key1_5(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0xffff;
+        val as u16
+    }
+    #[inline(always)]
+    pub fn set_key1_5(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+    }
+}
+impl Default for Key15 {
+    #[inline(always)]
+    fn default() -> Key15 {
+        Key15(0)
+    }
+}
+#[doc = "Bits 111:96 of OTP access key 1 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Key16(pub u32);
+impl Key16 {
+    #[inline(always)]
+    pub const fn key1_6(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0xffff;
+        val as u16
+    }
+    #[inline(always)]
+    pub fn set_key1_6(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+    }
+}
+impl Default for Key16 {
+    #[inline(always)]
+    fn default() -> Key16 {
+        Key16(0)
+    }
+}
+#[doc = "Bits 127:112 of OTP access key 1 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Key17(pub u32);
+impl Key17 {
+    #[inline(always)]
+    pub const fn key1_7(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0xffff;
+        val as u16
+    }
+    #[inline(always)]
+    pub fn set_key1_7(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+    }
+}
+impl Default for Key17 {
+    #[inline(always)]
+    fn default() -> Key17 {
+        Key17(0)
+    }
+}
+#[doc = "Bits 15:0 of OTP access key 2 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Key20(pub u32);
+impl Key20 {
+    #[inline(always)]
+    pub const fn key2_0(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0xffff;
+        val as u16
+    }
+    #[inline(always)]
+    pub fn set_key2_0(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+    }
+}
+impl Default for Key20 {
+    #[inline(always)]
+    fn default() -> Key20 {
+        Key20(0)
+    }
+}
+#[doc = "Bits 31:16 of OTP access key 2 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Key21(pub u32);
+impl Key21 {
+    #[inline(always)]
+    pub const fn key2_1(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0xffff;
+        val as u16
+    }
+    #[inline(always)]
+    pub fn set_key2_1(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+    }
+}
+impl Default for Key21 {
+    #[inline(always)]
+    fn default() -> Key21 {
+        Key21(0)
+    }
+}
+#[doc = "Bits 47:32 of OTP access key 2 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Key22(pub u32);
+impl Key22 {
+    #[inline(always)]
+    pub const fn key2_2(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0xffff;
+        val as u16
+    }
+    #[inline(always)]
+    pub fn set_key2_2(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+    }
+}
+impl Default for Key22 {
+    #[inline(always)]
+    fn default() -> Key22 {
+        Key22(0)
+    }
+}
+#[doc = "Bits 63:48 of OTP access key 2 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Key23(pub u32);
+impl Key23 {
+    #[inline(always)]
+    pub const fn key2_3(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0xffff;
+        val as u16
+    }
+    #[inline(always)]
+    pub fn set_key2_3(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+    }
+}
+impl Default for Key23 {
+    #[inline(always)]
+    fn default() -> Key23 {
+        Key23(0)
+    }
+}
+#[doc = "Bits 79:64 of OTP access key 2 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Key24(pub u32);
+impl Key24 {
+    #[inline(always)]
+    pub const fn key2_4(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0xffff;
+        val as u16
+    }
+    #[inline(always)]
+    pub fn set_key2_4(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+    }
+}
+impl Default for Key24 {
+    #[inline(always)]
+    fn default() -> Key24 {
+        Key24(0)
+    }
+}
+#[doc = "Bits 95:80 of OTP access key 2 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Key25(pub u32);
+impl Key25 {
+    #[inline(always)]
+    pub const fn key2_5(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0xffff;
+        val as u16
+    }
+    #[inline(always)]
+    pub fn set_key2_5(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+    }
+}
+impl Default for Key25 {
+    #[inline(always)]
+    fn default() -> Key25 {
+        Key25(0)
+    }
+}
+#[doc = "Bits 111:96 of OTP access key 2 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Key26(pub u32);
+impl Key26 {
+    #[inline(always)]
+    pub const fn key2_6(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0xffff;
+        val as u16
+    }
+    #[inline(always)]
+    pub fn set_key2_6(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+    }
+}
+impl Default for Key26 {
+    #[inline(always)]
+    fn default() -> Key26 {
+        Key26(0)
+    }
+}
+#[doc = "Bits 127:112 of OTP access key 2 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Key27(pub u32);
+impl Key27 {
+    #[inline(always)]
+    pub const fn key2_7(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0xffff;
+        val as u16
+    }
+    #[inline(always)]
+    pub fn set_key2_7(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+    }
+}
+impl Default for Key27 {
+    #[inline(always)]
+    fn default() -> Key27 {
+        Key27(0)
+    }
+}
+#[doc = "Bits 15:0 of OTP access key 3 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Key30(pub u32);
+impl Key30 {
+    #[inline(always)]
+    pub const fn key3_0(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0xffff;
+        val as u16
+    }
+    #[inline(always)]
+    pub fn set_key3_0(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+    }
+}
+impl Default for Key30 {
+    #[inline(always)]
+    fn default() -> Key30 {
+        Key30(0)
+    }
+}
+#[doc = "Bits 31:16 of OTP access key 3 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Key31(pub u32);
+impl Key31 {
+    #[inline(always)]
+    pub const fn key3_1(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0xffff;
+        val as u16
+    }
+    #[inline(always)]
+    pub fn set_key3_1(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+    }
+}
+impl Default for Key31 {
+    #[inline(always)]
+    fn default() -> Key31 {
+        Key31(0)
+    }
+}
+#[doc = "Bits 47:32 of OTP access key 3 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Key32(pub u32);
+impl Key32 {
+    #[inline(always)]
+    pub const fn key3_2(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0xffff;
+        val as u16
+    }
+    #[inline(always)]
+    pub fn set_key3_2(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+    }
+}
+impl Default for Key32 {
+    #[inline(always)]
+    fn default() -> Key32 {
+        Key32(0)
+    }
+}
+#[doc = "Bits 63:48 of OTP access key 3 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Key33(pub u32);
+impl Key33 {
+    #[inline(always)]
+    pub const fn key3_3(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0xffff;
+        val as u16
+    }
+    #[inline(always)]
+    pub fn set_key3_3(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+    }
+}
+impl Default for Key33 {
+    #[inline(always)]
+    fn default() -> Key33 {
+        Key33(0)
+    }
+}
+#[doc = "Bits 79:64 of OTP access key 3 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Key34(pub u32);
+impl Key34 {
+    #[inline(always)]
+    pub const fn key3_4(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0xffff;
+        val as u16
+    }
+    #[inline(always)]
+    pub fn set_key3_4(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+    }
+}
+impl Default for Key34 {
+    #[inline(always)]
+    fn default() -> Key34 {
+        Key34(0)
+    }
+}
+#[doc = "Bits 95:80 of OTP access key 3 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Key35(pub u32);
+impl Key35 {
+    #[inline(always)]
+    pub const fn key3_5(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0xffff;
+        val as u16
+    }
+    #[inline(always)]
+    pub fn set_key3_5(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+    }
+}
+impl Default for Key35 {
+    #[inline(always)]
+    fn default() -> Key35 {
+        Key35(0)
+    }
+}
+#[doc = "Bits 111:96 of OTP access key 3 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Key36(pub u32);
+impl Key36 {
+    #[inline(always)]
+    pub const fn key3_6(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0xffff;
+        val as u16
+    }
+    #[inline(always)]
+    pub fn set_key3_6(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+    }
+}
+impl Default for Key36 {
+    #[inline(always)]
+    fn default() -> Key36 {
+        Key36(0)
+    }
+}
+#[doc = "Bits 127:112 of OTP access key 3 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Key37(pub u32);
+impl Key37 {
+    #[inline(always)]
+    pub const fn key3_7(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0xffff;
+        val as u16
+    }
+    #[inline(always)]
+    pub fn set_key3_7(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+    }
+}
+impl Default for Key37 {
+    #[inline(always)]
+    fn default() -> Key37 {
+        Key37(0)
+    }
+}
+#[doc = "Bits 15:0 of OTP access key 4 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Key40(pub u32);
+impl Key40 {
+    #[inline(always)]
+    pub const fn key4_0(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0xffff;
+        val as u16
+    }
+    #[inline(always)]
+    pub fn set_key4_0(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+    }
+}
+impl Default for Key40 {
+    #[inline(always)]
+    fn default() -> Key40 {
+        Key40(0)
+    }
+}
+#[doc = "Bits 31:16 of OTP access key 4 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Key41(pub u32);
+impl Key41 {
+    #[inline(always)]
+    pub const fn key4_1(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0xffff;
+        val as u16
+    }
+    #[inline(always)]
+    pub fn set_key4_1(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+    }
+}
+impl Default for Key41 {
+    #[inline(always)]
+    fn default() -> Key41 {
+        Key41(0)
+    }
+}
+#[doc = "Bits 47:32 of OTP access key 4 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Key42(pub u32);
+impl Key42 {
+    #[inline(always)]
+    pub const fn key4_2(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0xffff;
+        val as u16
+    }
+    #[inline(always)]
+    pub fn set_key4_2(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+    }
+}
+impl Default for Key42 {
+    #[inline(always)]
+    fn default() -> Key42 {
+        Key42(0)
+    }
+}
+#[doc = "Bits 63:48 of OTP access key 4 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Key43(pub u32);
+impl Key43 {
+    #[inline(always)]
+    pub const fn key4_3(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0xffff;
+        val as u16
+    }
+    #[inline(always)]
+    pub fn set_key4_3(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+    }
+}
+impl Default for Key43 {
+    #[inline(always)]
+    fn default() -> Key43 {
+        Key43(0)
+    }
+}
+#[doc = "Bits 79:64 of OTP access key 4 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Key44(pub u32);
+impl Key44 {
+    #[inline(always)]
+    pub const fn key4_4(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0xffff;
+        val as u16
+    }
+    #[inline(always)]
+    pub fn set_key4_4(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+    }
+}
+impl Default for Key44 {
+    #[inline(always)]
+    fn default() -> Key44 {
+        Key44(0)
+    }
+}
+#[doc = "Bits 95:80 of OTP access key 4 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Key45(pub u32);
+impl Key45 {
+    #[inline(always)]
+    pub const fn key4_5(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0xffff;
+        val as u16
+    }
+    #[inline(always)]
+    pub fn set_key4_5(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+    }
+}
+impl Default for Key45 {
+    #[inline(always)]
+    fn default() -> Key45 {
+        Key45(0)
+    }
+}
+#[doc = "Bits 111:96 of OTP access key 4 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Key46(pub u32);
+impl Key46 {
+    #[inline(always)]
+    pub const fn key4_6(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0xffff;
+        val as u16
+    }
+    #[inline(always)]
+    pub fn set_key4_6(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+    }
+}
+impl Default for Key46 {
+    #[inline(always)]
+    fn default() -> Key46 {
+        Key46(0)
+    }
+}
+#[doc = "Bits 127:112 of OTP access key 4 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Key47(pub u32);
+impl Key47 {
+    #[inline(always)]
+    pub const fn key4_7(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0xffff;
+        val as u16
+    }
+    #[inline(always)]
+    pub fn set_key4_7(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+    }
+}
+impl Default for Key47 {
+    #[inline(always)]
+    fn default() -> Key47 {
+        Key47(0)
+    }
+}
+#[doc = "Bits 15:0 of OTP access key 5 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Key50(pub u32);
+impl Key50 {
+    #[inline(always)]
+    pub const fn key5_0(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0xffff;
+        val as u16
+    }
+    #[inline(always)]
+    pub fn set_key5_0(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+    }
+}
+impl Default for Key50 {
+    #[inline(always)]
+    fn default() -> Key50 {
+        Key50(0)
+    }
+}
+#[doc = "Bits 31:16 of OTP access key 5 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Key51(pub u32);
+impl Key51 {
+    #[inline(always)]
+    pub const fn key5_1(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0xffff;
+        val as u16
+    }
+    #[inline(always)]
+    pub fn set_key5_1(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+    }
+}
+impl Default for Key51 {
+    #[inline(always)]
+    fn default() -> Key51 {
+        Key51(0)
+    }
+}
+#[doc = "Bits 47:32 of OTP access key 5 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Key52(pub u32);
+impl Key52 {
+    #[inline(always)]
+    pub const fn key5_2(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0xffff;
+        val as u16
+    }
+    #[inline(always)]
+    pub fn set_key5_2(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+    }
+}
+impl Default for Key52 {
+    #[inline(always)]
+    fn default() -> Key52 {
+        Key52(0)
+    }
+}
+#[doc = "Bits 63:48 of OTP access key 5 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Key53(pub u32);
+impl Key53 {
+    #[inline(always)]
+    pub const fn key5_3(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0xffff;
+        val as u16
+    }
+    #[inline(always)]
+    pub fn set_key5_3(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+    }
+}
+impl Default for Key53 {
+    #[inline(always)]
+    fn default() -> Key53 {
+        Key53(0)
+    }
+}
+#[doc = "Bits 79:64 of OTP access key 5 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Key54(pub u32);
+impl Key54 {
+    #[inline(always)]
+    pub const fn key5_4(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0xffff;
+        val as u16
+    }
+    #[inline(always)]
+    pub fn set_key5_4(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+    }
+}
+impl Default for Key54 {
+    #[inline(always)]
+    fn default() -> Key54 {
+        Key54(0)
+    }
+}
+#[doc = "Bits 95:80 of OTP access key 5 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Key55(pub u32);
+impl Key55 {
+    #[inline(always)]
+    pub const fn key5_5(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0xffff;
+        val as u16
+    }
+    #[inline(always)]
+    pub fn set_key5_5(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+    }
+}
+impl Default for Key55 {
+    #[inline(always)]
+    fn default() -> Key55 {
+        Key55(0)
+    }
+}
+#[doc = "Bits 111:96 of OTP access key 5 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Key56(pub u32);
+impl Key56 {
+    #[inline(always)]
+    pub const fn key5_6(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0xffff;
+        val as u16
+    }
+    #[inline(always)]
+    pub fn set_key5_6(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+    }
+}
+impl Default for Key56 {
+    #[inline(always)]
+    fn default() -> Key56 {
+        Key56(0)
+    }
+}
+#[doc = "Bits 127:112 of OTP access key 5 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Key57(pub u32);
+impl Key57 {
+    #[inline(always)]
+    pub const fn key5_7(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0xffff;
+        val as u16
+    }
+    #[inline(always)]
+    pub fn set_key5_7(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+    }
+}
+impl Default for Key57 {
+    #[inline(always)]
+    fn default() -> Key57 {
+        Key57(0)
+    }
+}
+#[doc = "Bits 15:0 of OTP access key 6 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Key60(pub u32);
+impl Key60 {
+    #[inline(always)]
+    pub const fn key6_0(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0xffff;
+        val as u16
+    }
+    #[inline(always)]
+    pub fn set_key6_0(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+    }
+}
+impl Default for Key60 {
+    #[inline(always)]
+    fn default() -> Key60 {
+        Key60(0)
+    }
+}
+#[doc = "Bits 31:16 of OTP access key 6 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Key61(pub u32);
+impl Key61 {
+    #[inline(always)]
+    pub const fn key6_1(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0xffff;
+        val as u16
+    }
+    #[inline(always)]
+    pub fn set_key6_1(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+    }
+}
+impl Default for Key61 {
+    #[inline(always)]
+    fn default() -> Key61 {
+        Key61(0)
+    }
+}
+#[doc = "Bits 47:32 of OTP access key 6 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Key62(pub u32);
+impl Key62 {
+    #[inline(always)]
+    pub const fn key6_2(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0xffff;
+        val as u16
+    }
+    #[inline(always)]
+    pub fn set_key6_2(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+    }
+}
+impl Default for Key62 {
+    #[inline(always)]
+    fn default() -> Key62 {
+        Key62(0)
+    }
+}
+#[doc = "Bits 63:48 of OTP access key 6 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Key63(pub u32);
+impl Key63 {
+    #[inline(always)]
+    pub const fn key6_3(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0xffff;
+        val as u16
+    }
+    #[inline(always)]
+    pub fn set_key6_3(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+    }
+}
+impl Default for Key63 {
+    #[inline(always)]
+    fn default() -> Key63 {
+        Key63(0)
+    }
+}
+#[doc = "Bits 79:64 of OTP access key 6 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Key64(pub u32);
+impl Key64 {
+    #[inline(always)]
+    pub const fn key6_4(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0xffff;
+        val as u16
+    }
+    #[inline(always)]
+    pub fn set_key6_4(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+    }
+}
+impl Default for Key64 {
+    #[inline(always)]
+    fn default() -> Key64 {
+        Key64(0)
+    }
+}
+#[doc = "Bits 95:80 of OTP access key 6 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Key65(pub u32);
+impl Key65 {
+    #[inline(always)]
+    pub const fn key6_5(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0xffff;
+        val as u16
+    }
+    #[inline(always)]
+    pub fn set_key6_5(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+    }
+}
+impl Default for Key65 {
+    #[inline(always)]
+    fn default() -> Key65 {
+        Key65(0)
+    }
+}
+#[doc = "Bits 111:96 of OTP access key 6 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Key66(pub u32);
+impl Key66 {
+    #[inline(always)]
+    pub const fn key6_6(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0xffff;
+        val as u16
+    }
+    #[inline(always)]
+    pub fn set_key6_6(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+    }
+}
+impl Default for Key66 {
+    #[inline(always)]
+    fn default() -> Key66 {
+        Key66(0)
+    }
+}
+#[doc = "Bits 127:112 of OTP access key 6 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Key67(pub u32);
+impl Key67 {
+    #[inline(always)]
+    pub const fn key6_7(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0xffff;
+        val as u16
+    }
+    #[inline(always)]
+    pub fn set_key6_7(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+    }
+}
+impl Default for Key67 {
+    #[inline(always)]
+    fn default() -> Key67 {
+        Key67(0)
+    }
+}
+#[doc = "Low-power oscillator frequency in Hz, measured during manufacturing (ECC) This is measured at 1.1V, at room temperature, with the LPOSC trim register in its reset state."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct LposcCalib(pub u32);
+impl LposcCalib {
+    #[inline(always)]
+    pub const fn lposc_calib(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0xffff;
+        val as u16
+    }
+    #[inline(always)]
+    pub fn set_lposc_calib(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+    }
+}
+impl Default for LposcCalib {
+    #[inline(always)]
+    fn default() -> LposcCalib {
+        LposcCalib(0)
+    }
+}
+#[doc = "The number of main user GPIOs (bank 0). Should read 48 in the QFN80 package, and 30 in the QFN60 package. (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct NumGpios(pub u32);
+impl NumGpios {
+    #[inline(always)]
+    pub const fn num_gpios(&self) -> u8 {
+        let val = (self.0 >> 0usize) & 0xff;
+        val as u8
+    }
+    #[inline(always)]
+    pub fn set_num_gpios(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize);
+    }
+}
+impl Default for NumGpios {
+    #[inline(always)]
+    fn default() -> NumGpios {
+        NumGpios(0)
+    }
+}
+#[doc = "Bits 15:0 of the OTP boot image load destination (and entry point). (ECC) This must be a location in main SRAM (main SRAM is addresses 0x20000000 through 0x20082000) and must be word-aligned."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct OtpbootDst0(pub u32);
+impl OtpbootDst0 {
+    #[inline(always)]
+    pub const fn otpboot_dst0(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0xffff;
+        val as u16
+    }
+    #[inline(always)]
+    pub fn set_otpboot_dst0(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+    }
+}
+impl Default for OtpbootDst0 {
+    #[inline(always)]
+    fn default() -> OtpbootDst0 {
+        OtpbootDst0(0)
+    }
+}
+#[doc = "Bits 31:16 of the OTP boot image load destination (and entry point). (ECC) This must be a location in main SRAM (main SRAM is addresses 0x20000000 through 0x20082000) and must be word-aligned."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct OtpbootDst1(pub u32);
+impl OtpbootDst1 {
+    #[inline(always)]
+    pub const fn otpboot_dst1(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0xffff;
+        val as u16
+    }
+    #[inline(always)]
+    pub fn set_otpboot_dst1(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+    }
+}
+impl Default for OtpbootDst1 {
+    #[inline(always)]
+    fn default() -> OtpbootDst1 {
+        OtpbootDst1(0)
+    }
+}
+#[doc = "Length in rows of the OTP boot image. (ECC) OTPBOOT_LEN must be even. The total image size must be a multiple of 4 bytes (32 bits)."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct OtpbootLen(pub u32);
+impl OtpbootLen {
+    #[inline(always)]
+    pub const fn otpboot_len(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0xffff;
+        val as u16
+    }
+    #[inline(always)]
+    pub fn set_otpboot_len(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+    }
+}
+impl Default for OtpbootLen {
+    #[inline(always)]
+    fn default() -> OtpbootLen {
+        OtpbootLen(0)
+    }
+}
+#[doc = "OTP start row for the OTP boot image. (ECC) If OTP boot is enabled, the bootrom will load from this location into SRAM and then directly enter the loaded image. Note that the image must be signed if SECURE_BOOT_ENABLE is set. The image itself is assumed to be ECC-protected. This must be an even number. Equivalently, the OTP boot image must start at a word-aligned location in the ECC read data address window."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct OtpbootSrc(pub u32);
+impl OtpbootSrc {
+    #[inline(always)]
+    pub const fn otpboot_src(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0xffff;
+        val as u16
+    }
+    #[inline(always)]
+    pub fn set_otpboot_src(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+    }
+}
+impl Default for OtpbootSrc {
+    #[inline(always)]
+    fn default() -> OtpbootSrc {
+        OtpbootSrc(0)
+    }
+}
+#[doc = "Bits 15:0 of private per-device random number (ECC) The RANDID0..7 rows form a 128-bit random number generated during device test. This ID is not exposed through the USB PICOBOOT GET_INFO command or the ROM `get_sys_info()` API. However note that the USB PICOBOOT OTP access point can read the entirety of page 0, so this value is not meaningfully private unless the USB PICOBOOT interface is disabled via the DISABLE_BOOTSEL_USB_PICOBOOT_IFC flag in BOOT_FLAGS0."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Randid0(pub u32);
+impl Randid0 {
+    #[inline(always)]
+    pub const fn randid0(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0xffff;
+        val as u16
+    }
+    #[inline(always)]
+    pub fn set_randid0(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+    }
+}
+impl Default for Randid0 {
+    #[inline(always)]
+    fn default() -> Randid0 {
+        Randid0(0)
+    }
+}
+#[doc = "Bits 31:16 of private per-device random number (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Randid1(pub u32);
+impl Randid1 {
+    #[inline(always)]
+    pub const fn randid1(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0xffff;
+        val as u16
+    }
+    #[inline(always)]
+    pub fn set_randid1(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+    }
+}
+impl Default for Randid1 {
+    #[inline(always)]
+    fn default() -> Randid1 {
+        Randid1(0)
+    }
+}
+#[doc = "Bits 47:32 of private per-device random number (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Randid2(pub u32);
+impl Randid2 {
+    #[inline(always)]
+    pub const fn randid2(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0xffff;
+        val as u16
+    }
+    #[inline(always)]
+    pub fn set_randid2(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+    }
+}
+impl Default for Randid2 {
+    #[inline(always)]
+    fn default() -> Randid2 {
+        Randid2(0)
+    }
+}
+#[doc = "Bits 63:48 of private per-device random number (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Randid3(pub u32);
+impl Randid3 {
+    #[inline(always)]
+    pub const fn randid3(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0xffff;
+        val as u16
+    }
+    #[inline(always)]
+    pub fn set_randid3(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+    }
+}
+impl Default for Randid3 {
+    #[inline(always)]
+    fn default() -> Randid3 {
+        Randid3(0)
+    }
+}
+#[doc = "Bits 79:64 of private per-device random number (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Randid4(pub u32);
+impl Randid4 {
+    #[inline(always)]
+    pub const fn randid4(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0xffff;
+        val as u16
+    }
+    #[inline(always)]
+    pub fn set_randid4(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+    }
+}
+impl Default for Randid4 {
+    #[inline(always)]
+    fn default() -> Randid4 {
+        Randid4(0)
+    }
+}
+#[doc = "Bits 95:80 of private per-device random number (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Randid5(pub u32);
+impl Randid5 {
+    #[inline(always)]
+    pub const fn randid5(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0xffff;
+        val as u16
+    }
+    #[inline(always)]
+    pub fn set_randid5(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+    }
+}
+impl Default for Randid5 {
+    #[inline(always)]
+    fn default() -> Randid5 {
+        Randid5(0)
+    }
+}
+#[doc = "Bits 111:96 of private per-device random number (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Randid6(pub u32);
+impl Randid6 {
+    #[inline(always)]
+    pub const fn randid6(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0xffff;
+        val as u16
+    }
+    #[inline(always)]
+    pub fn set_randid6(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+    }
+}
+impl Default for Randid6 {
+    #[inline(always)]
+    fn default() -> Randid6 {
+        Randid6(0)
+    }
+}
+#[doc = "Bits 127:112 of private per-device random number (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Randid7(pub u32);
+impl Randid7 {
+    #[inline(always)]
+    pub const fn randid7(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0xffff;
+        val as u16
+    }
+    #[inline(always)]
+    pub fn set_randid7(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+    }
+}
+impl Default for Randid7 {
+    #[inline(always)]
+    fn default() -> Randid7 {
+        Randid7(0)
+    }
+}
+#[doc = "Ring oscillator frequency in kHz, measured during manufacturing (ECC) This is measured at 1.1 V, at room temperature, with the ROSC configuration registers in their reset state."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct RoscCalib(pub u32);
+impl RoscCalib {
+    #[inline(always)]
+    pub const fn rosc_calib(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0xffff;
+        val as u16
+    }
+    #[inline(always)]
+    pub fn set_rosc_calib(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+    }
+}
+impl Default for RoscCalib {
+    #[inline(always)]
+    fn default() -> RoscCalib {
+        RoscCalib(0)
+    }
+}
+#[doc = "Row index of the USB_WHITE_LABEL structure within OTP (ECC) The table has 16 rows, each of which are also ECC and marked valid by the corresponding valid bit in USB_BOOT_FLAGS (ECC). The entries are either _VALUEs where the 16 bit value is used as is, or _STRDEFs which acts as a pointers to a string value. The value stored in a _STRDEF is two separate bytes: The low seven bits of the first (LSB) byte indicates the number of characters in the string, and the top bit of the first (LSB) byte if set to indicate that each character in the string is two bytes (Unicode) versus one byte if unset. The second (MSB) byte represents the location of the string data, and is encoded as the number of rows from this USB_WHITE_LABEL_ADDR; i.e. the row of the start of the string is USB_WHITE_LABEL_ADDR value + msb_byte. In each case, the corresponding valid bit enables replacing the default value for the corresponding item provided by the boot rom. Note that Unicode _STRDEFs are only supported for USB_DEVICE_PRODUCT_STRDEF, USB_DEVICE_SERIAL_NUMBER_STRDEF and USB_DEVICE_MANUFACTURER_STRDEF. Unicode values will be ignored if specified for other fields, and non-unicode values for these three items will be converted to Unicode characters by setting the upper 8 bits to zero. Note that if the USB_WHITE_LABEL structure or the corresponding strings are not readable by BOOTSEL mode based on OTP permissions, or if alignment requirements are not met, then the corresponding default values are used. The index values indicate where each field is located (row USB_WHITE_LABEL_ADDR value + index):"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct UsbWhiteLabelAddr(pub u32);
+impl UsbWhiteLabelAddr {
+    #[inline(always)]
+    pub const fn usb_white_label_addr(&self) -> super::vals::UsbWhiteLabelAddr {
+        let val = (self.0 >> 0usize) & 0xffff;
+        super::vals::UsbWhiteLabelAddr::from_bits(val as u16)
+    }
+    #[inline(always)]
+    pub fn set_usb_white_label_addr(&mut self, val: super::vals::UsbWhiteLabelAddr) {
+        self.0 = (self.0 & !(0xffff << 0usize)) | (((val.to_bits() as u32) & 0xffff) << 0usize);
+    }
+}
+impl Default for UsbWhiteLabelAddr {
+    #[inline(always)]
+    fn default() -> UsbWhiteLabelAddr {
+        UsbWhiteLabelAddr(0)
+    }
+}
diff --git a/src/rp2350/otp_data/vals.rs b/src/rp2350/otp_data/vals.rs
new file mode 100644
index 00000000..68e29e02
--- /dev/null
+++ b/src/rp2350/otp_data/vals.rs
@@ -0,0 +1,155 @@
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Cs0size {
+    NONE = 0,
+    _8K = 0x01,
+    _16K = 0x02,
+    _32K = 0x03,
+    _64K = 0x04,
+    _128K = 0x05,
+    _256K = 0x06,
+    _512K = 0x07,
+    _1M = 0x08,
+    _2M = 0x09,
+    _4M = 0x0a,
+    _8M = 0x0b,
+    _16M = 0x0c,
+    _RESERVED_d = 0x0d,
+    _RESERVED_e = 0x0e,
+    _RESERVED_f = 0x0f,
+}
+impl Cs0size {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Cs0size {
+        unsafe { core::mem::transmute(val & 0x0f) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Cs0size {
+    #[inline(always)]
+    fn from(val: u8) -> Cs0size {
+        Cs0size::from_bits(val)
+    }
+}
+impl From<Cs0size> for u8 {
+    #[inline(always)]
+    fn from(val: Cs0size) -> u8 {
+        Cs0size::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Cs1size {
+    NONE = 0,
+    _8K = 0x01,
+    _16K = 0x02,
+    _32K = 0x03,
+    _64K = 0x04,
+    _128K = 0x05,
+    _256K = 0x06,
+    _512K = 0x07,
+    _1M = 0x08,
+    _2M = 0x09,
+    _4M = 0x0a,
+    _8M = 0x0b,
+    _16M = 0x0c,
+    _RESERVED_d = 0x0d,
+    _RESERVED_e = 0x0e,
+    _RESERVED_f = 0x0f,
+}
+impl Cs1size {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Cs1size {
+        unsafe { core::mem::transmute(val & 0x0f) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Cs1size {
+    #[inline(always)]
+    fn from(val: u8) -> Cs1size {
+        Cs1size::from_bits(val)
+    }
+}
+impl From<Cs1size> for u8 {
+    #[inline(always)]
+    fn from(val: Cs1size) -> u8 {
+        Cs1size::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Range {
+    _1_15MHZ = 0,
+    _10_30MHZ = 0x01,
+    _25_60MHZ = 0x02,
+    _40_100MHZ = 0x03,
+}
+impl Range {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Range {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Range {
+    #[inline(always)]
+    fn from(val: u8) -> Range {
+        Range::from_bits(val)
+    }
+}
+impl From<Range> for u8 {
+    #[inline(always)]
+    fn from(val: Range) -> u8 {
+        Range::to_bits(val)
+    }
+}
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub struct UsbWhiteLabelAddr(pub u16);
+impl UsbWhiteLabelAddr {
+    pub const INDEX_USB_DEVICE_VID_VALUE: Self = Self(0);
+    pub const INDEX_USB_DEVICE_PID_VALUE: Self = Self(0x01);
+    pub const INDEX_USB_DEVICE_BCD_DEVICE_VALUE: Self = Self(0x02);
+    pub const INDEX_USB_DEVICE_LANG_ID_VALUE: Self = Self(0x03);
+    pub const INDEX_USB_DEVICE_MANUFACTURER_STRDEF: Self = Self(0x04);
+    pub const INDEX_USB_DEVICE_PRODUCT_STRDEF: Self = Self(0x05);
+    pub const INDEX_USB_DEVICE_SERIAL_NUMBER_STRDEF: Self = Self(0x06);
+    pub const INDEX_USB_CONFIG_ATTRIBUTES_MAX_POWER_VALUES: Self = Self(0x07);
+    pub const INDEX_VOLUME_LABEL_STRDEF: Self = Self(0x08);
+    pub const INDEX_SCSI_INQUIRY_VENDOR_STRDEF: Self = Self(0x09);
+    pub const INDEX_SCSI_INQUIRY_PRODUCT_STRDEF: Self = Self(0x0a);
+    pub const INDEX_SCSI_INQUIRY_VERSION_STRDEF: Self = Self(0x0b);
+    pub const INDEX_INDEX_HTM_REDIRECT_URL_STRDEF: Self = Self(0x0c);
+    pub const INDEX_INDEX_HTM_REDIRECT_NAME_STRDEF: Self = Self(0x0d);
+    pub const INDEX_INFO_UF2_TXT_MODEL_STRDEF: Self = Self(0x0e);
+    pub const INDEX_INFO_UF2_TXT_BOARD_ID_STRDEF: Self = Self(0x0f);
+}
+impl UsbWhiteLabelAddr {
+    pub const fn from_bits(val: u16) -> UsbWhiteLabelAddr {
+        Self(val & 0xffff)
+    }
+    pub const fn to_bits(self) -> u16 {
+        self.0
+    }
+}
+impl From<u16> for UsbWhiteLabelAddr {
+    #[inline(always)]
+    fn from(val: u16) -> UsbWhiteLabelAddr {
+        UsbWhiteLabelAddr::from_bits(val)
+    }
+}
+impl From<UsbWhiteLabelAddr> for u16 {
+    #[inline(always)]
+    fn from(val: UsbWhiteLabelAddr) -> u16 {
+        UsbWhiteLabelAddr::to_bits(val)
+    }
+}
diff --git a/src/rp2350/otp_data_raw.rs b/src/rp2350/otp_data_raw.rs
new file mode 100644
index 00000000..6173c50a
--- /dev/null
+++ b/src/rp2350/otp_data_raw.rs
@@ -0,0 +1,1565 @@
+#[doc = "Predefined OTP data layout for RP2350"]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct OtpDataRaw {
+    ptr: *mut u8,
+}
+unsafe impl Send for OtpDataRaw {}
+unsafe impl Sync for OtpDataRaw {}
+impl OtpDataRaw {
+    #[inline(always)]
+    pub const unsafe fn from_ptr(ptr: *mut ()) -> Self {
+        Self { ptr: ptr as _ }
+    }
+    #[inline(always)]
+    pub const fn as_ptr(&self) -> *mut () {
+        self.ptr as _
+    }
+    #[doc = "Bits 15:0 of public device ID. (ECC) The CHIPID0..3 rows contain a 64-bit random identifier for this chip, which can be read from the USB bootloader PICOBOOT interface or from the get_sys_info ROM API. The number of random bits makes the occurrence of twins exceedingly unlikely: for example, a fleet of a hundred million devices has a 99.97% probability of no twinned IDs. This is estimated to be lower than the occurrence of process errors in the assignment of sequential random IDs, and for practical purposes CHIPID may be treated as unique."]
+    #[inline(always)]
+    pub const fn chipid0(self) -> crate::common::Reg<regs::Chipid0, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(0usize) as _) }
+    }
+    #[doc = "Bits 31:16 of public device ID (ECC)"]
+    #[inline(always)]
+    pub const fn chipid1(self) -> crate::common::Reg<regs::Chipid1, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(4usize) as _) }
+    }
+    #[doc = "Bits 47:32 of public device ID (ECC)"]
+    #[inline(always)]
+    pub const fn chipid2(self) -> crate::common::Reg<regs::Chipid2, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(8usize) as _) }
+    }
+    #[doc = "Bits 63:48 of public device ID (ECC)"]
+    #[inline(always)]
+    pub const fn chipid3(self) -> crate::common::Reg<regs::Chipid3, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(12usize) as _) }
+    }
+    #[doc = "Bits 15:0 of private per-device random number (ECC) The RANDID0..7 rows form a 128-bit random number generated during device test. This ID is not exposed through the USB PICOBOOT GET_INFO command or the ROM `get_sys_info()` API. However note that the USB PICOBOOT OTP access point can read the entirety of page 0, so this value is not meaningfully private unless the USB PICOBOOT interface is disabled via the DISABLE_BOOTSEL_USB_PICOBOOT_IFC flag in BOOT_FLAGS0."]
+    #[inline(always)]
+    pub const fn randid0(self) -> crate::common::Reg<regs::Randid0, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(16usize) as _) }
+    }
+    #[doc = "Bits 31:16 of private per-device random number (ECC)"]
+    #[inline(always)]
+    pub const fn randid1(self) -> crate::common::Reg<regs::Randid1, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(20usize) as _) }
+    }
+    #[doc = "Bits 47:32 of private per-device random number (ECC)"]
+    #[inline(always)]
+    pub const fn randid2(self) -> crate::common::Reg<regs::Randid2, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(24usize) as _) }
+    }
+    #[doc = "Bits 63:48 of private per-device random number (ECC)"]
+    #[inline(always)]
+    pub const fn randid3(self) -> crate::common::Reg<regs::Randid3, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(28usize) as _) }
+    }
+    #[doc = "Bits 79:64 of private per-device random number (ECC)"]
+    #[inline(always)]
+    pub const fn randid4(self) -> crate::common::Reg<regs::Randid4, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(32usize) as _) }
+    }
+    #[doc = "Bits 95:80 of private per-device random number (ECC)"]
+    #[inline(always)]
+    pub const fn randid5(self) -> crate::common::Reg<regs::Randid5, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(36usize) as _) }
+    }
+    #[doc = "Bits 111:96 of private per-device random number (ECC)"]
+    #[inline(always)]
+    pub const fn randid6(self) -> crate::common::Reg<regs::Randid6, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(40usize) as _) }
+    }
+    #[doc = "Bits 127:112 of private per-device random number (ECC)"]
+    #[inline(always)]
+    pub const fn randid7(self) -> crate::common::Reg<regs::Randid7, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(44usize) as _) }
+    }
+    #[doc = "Ring oscillator frequency in kHz, measured during manufacturing (ECC) This is measured at 1.1 V, at room temperature, with the ROSC configuration registers in their reset state."]
+    #[inline(always)]
+    pub const fn rosc_calib(self) -> crate::common::Reg<regs::RoscCalib, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(64usize) as _) }
+    }
+    #[doc = "Low-power oscillator frequency in Hz, measured during manufacturing (ECC) This is measured at 1.1V, at room temperature, with the LPOSC trim register in its reset state."]
+    #[inline(always)]
+    pub const fn lposc_calib(self) -> crate::common::Reg<regs::LposcCalib, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(68usize) as _) }
+    }
+    #[doc = "The number of main user GPIOs (bank 0). Should read 48 in the QFN80 package, and 30 in the QFN60 package. (ECC)"]
+    #[inline(always)]
+    pub const fn num_gpios(self) -> crate::common::Reg<regs::NumGpios, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(96usize) as _) }
+    }
+    #[doc = "Lower 16 bits of CRC32 of OTP addresses 0x00 through 0x6b (polynomial 0x4c11db7, input reflected, output reflected, seed all-ones, final XOR all-ones) (ECC)"]
+    #[inline(always)]
+    pub const fn info_crc0(self) -> crate::common::Reg<regs::InfoCrc0, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(216usize) as _) }
+    }
+    #[doc = "Upper 16 bits of CRC32 of OTP addresses 0x00 through 0x6b (ECC)"]
+    #[inline(always)]
+    pub const fn info_crc1(self) -> crate::common::Reg<regs::InfoCrc1, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(220usize) as _) }
+    }
+    #[doc = "Page 0 critical boot flags (RBIT-8)"]
+    #[inline(always)]
+    pub const fn crit0(self) -> crate::common::Reg<regs::Crit0, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(224usize) as _) }
+    }
+    #[doc = "Redundant copy of CRIT0"]
+    #[inline(always)]
+    pub const fn crit0_r1(self) -> crate::common::Reg<regs::Crit0r1, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(228usize) as _) }
+    }
+    #[doc = "Redundant copy of CRIT0"]
+    #[inline(always)]
+    pub const fn crit0_r2(self) -> crate::common::Reg<regs::Crit0r2, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(232usize) as _) }
+    }
+    #[doc = "Redundant copy of CRIT0"]
+    #[inline(always)]
+    pub const fn crit0_r3(self) -> crate::common::Reg<regs::Crit0r3, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(236usize) as _) }
+    }
+    #[doc = "Redundant copy of CRIT0"]
+    #[inline(always)]
+    pub const fn crit0_r4(self) -> crate::common::Reg<regs::Crit0r4, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(240usize) as _) }
+    }
+    #[doc = "Redundant copy of CRIT0"]
+    #[inline(always)]
+    pub const fn crit0_r5(self) -> crate::common::Reg<regs::Crit0r5, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(244usize) as _) }
+    }
+    #[doc = "Redundant copy of CRIT0"]
+    #[inline(always)]
+    pub const fn crit0_r6(self) -> crate::common::Reg<regs::Crit0r6, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(248usize) as _) }
+    }
+    #[doc = "Redundant copy of CRIT0"]
+    #[inline(always)]
+    pub const fn crit0_r7(self) -> crate::common::Reg<regs::Crit0r7, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(252usize) as _) }
+    }
+    #[doc = "Page 1 critical boot flags (RBIT-8)"]
+    #[inline(always)]
+    pub const fn crit1(self) -> crate::common::Reg<regs::Crit1, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(256usize) as _) }
+    }
+    #[doc = "Redundant copy of CRIT1"]
+    #[inline(always)]
+    pub const fn crit1_r1(self) -> crate::common::Reg<regs::Crit1r1, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(260usize) as _) }
+    }
+    #[doc = "Redundant copy of CRIT1"]
+    #[inline(always)]
+    pub const fn crit1_r2(self) -> crate::common::Reg<regs::Crit1r2, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(264usize) as _) }
+    }
+    #[doc = "Redundant copy of CRIT1"]
+    #[inline(always)]
+    pub const fn crit1_r3(self) -> crate::common::Reg<regs::Crit1r3, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(268usize) as _) }
+    }
+    #[doc = "Redundant copy of CRIT1"]
+    #[inline(always)]
+    pub const fn crit1_r4(self) -> crate::common::Reg<regs::Crit1r4, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(272usize) as _) }
+    }
+    #[doc = "Redundant copy of CRIT1"]
+    #[inline(always)]
+    pub const fn crit1_r5(self) -> crate::common::Reg<regs::Crit1r5, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(276usize) as _) }
+    }
+    #[doc = "Redundant copy of CRIT1"]
+    #[inline(always)]
+    pub const fn crit1_r6(self) -> crate::common::Reg<regs::Crit1r6, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(280usize) as _) }
+    }
+    #[doc = "Redundant copy of CRIT1"]
+    #[inline(always)]
+    pub const fn crit1_r7(self) -> crate::common::Reg<regs::Crit1r7, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(284usize) as _) }
+    }
+    #[doc = "Disable/Enable boot paths/features in the RP2350 mask ROM. Disables always supersede enables. Enables are provided where there are other configurations in OTP that must be valid. (RBIT-3)"]
+    #[inline(always)]
+    pub const fn boot_flags0(self) -> crate::common::Reg<regs::BootFlags0, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(288usize) as _) }
+    }
+    #[doc = "Redundant copy of BOOT_FLAGS0"]
+    #[inline(always)]
+    pub const fn boot_flags0_r1(self) -> crate::common::Reg<regs::BootFlags0r1, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(292usize) as _) }
+    }
+    #[doc = "Redundant copy of BOOT_FLAGS0"]
+    #[inline(always)]
+    pub const fn boot_flags0_r2(self) -> crate::common::Reg<regs::BootFlags0r2, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(296usize) as _) }
+    }
+    #[doc = "Disable/Enable boot paths/features in the RP2350 mask ROM. Disables always supersede enables. Enables are provided where there are other configurations in OTP that must be valid. (RBIT-3)"]
+    #[inline(always)]
+    pub const fn boot_flags1(self) -> crate::common::Reg<regs::BootFlags1, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(300usize) as _) }
+    }
+    #[doc = "Redundant copy of BOOT_FLAGS1"]
+    #[inline(always)]
+    pub const fn boot_flags1_r1(self) -> crate::common::Reg<regs::BootFlags1r1, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(304usize) as _) }
+    }
+    #[doc = "Redundant copy of BOOT_FLAGS1"]
+    #[inline(always)]
+    pub const fn boot_flags1_r2(self) -> crate::common::Reg<regs::BootFlags1r2, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(308usize) as _) }
+    }
+    #[doc = "Default boot version thermometer counter, bits 23:0 (RBIT-3)"]
+    #[inline(always)]
+    pub const fn default_boot_version0(
+        self,
+    ) -> crate::common::Reg<regs::DefaultBootVersion0, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(312usize) as _) }
+    }
+    #[doc = "Redundant copy of DEFAULT_BOOT_VERSION0"]
+    #[inline(always)]
+    pub const fn default_boot_version0_r1(
+        self,
+    ) -> crate::common::Reg<regs::DefaultBootVersion0r1, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(316usize) as _) }
+    }
+    #[doc = "Redundant copy of DEFAULT_BOOT_VERSION0"]
+    #[inline(always)]
+    pub const fn default_boot_version0_r2(
+        self,
+    ) -> crate::common::Reg<regs::DefaultBootVersion0r2, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(320usize) as _) }
+    }
+    #[doc = "Default boot version thermometer counter, bits 47:24 (RBIT-3)"]
+    #[inline(always)]
+    pub const fn default_boot_version1(
+        self,
+    ) -> crate::common::Reg<regs::DefaultBootVersion1, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(324usize) as _) }
+    }
+    #[doc = "Redundant copy of DEFAULT_BOOT_VERSION1"]
+    #[inline(always)]
+    pub const fn default_boot_version1_r1(
+        self,
+    ) -> crate::common::Reg<regs::DefaultBootVersion1r1, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(328usize) as _) }
+    }
+    #[doc = "Redundant copy of DEFAULT_BOOT_VERSION1"]
+    #[inline(always)]
+    pub const fn default_boot_version1_r2(
+        self,
+    ) -> crate::common::Reg<regs::DefaultBootVersion1r2, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(332usize) as _) }
+    }
+    #[doc = "Stores information about external flash device(s). (ECC) Assumed to be valid if BOOT_FLAGS0_FLASH_DEVINFO_ENABLE is set."]
+    #[inline(always)]
+    pub const fn flash_devinfo(self) -> crate::common::Reg<regs::FlashDevinfo, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(336usize) as _) }
+    }
+    #[doc = "Gap between partition table slot 0 and slot 1 at the start of flash (the default size is 4096 bytes) (ECC) Enabled by the OVERRIDE_FLASH_PARTITION_SLOT_SIZE bit in BOOT_FLAGS, the size is 4096 * (value + 1)"]
+    #[inline(always)]
+    pub const fn flash_partition_slot_size(
+        self,
+    ) -> crate::common::Reg<regs::FlashPartitionSlotSize, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(340usize) as _) }
+    }
+    #[doc = "Pin configuration for LED status, used by USB bootloader. (ECC) Must be valid if BOOT_FLAGS0_ENABLE_BOOTSEL_LED is set."]
+    #[inline(always)]
+    pub const fn bootsel_led_cfg(
+        self,
+    ) -> crate::common::Reg<regs::BootselLedCfg, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(344usize) as _) }
+    }
+    #[doc = "Optional PLL configuration for BOOTSEL mode. (ECC) This should be configured to produce an exact 48 MHz based on the crystal oscillator frequency. User mode software may also use this value to calculate the expected crystal frequency based on an assumed 48 MHz PLL output. If no configuration is given, the crystal is assumed to be 12 MHz. The PLL frequency can be calculated as: PLL out = (XOSC frequency / (REFDIV+1)) x FBDIV / (POSTDIV1 x POSTDIV2) Conversely the crystal frequency can be calculated as: XOSC frequency = 48 MHz x (REFDIV+1) x (POSTDIV1 x POSTDIV2) / FBDIV (Note the +1 on REFDIV is because the value stored in this OTP location is the actual divisor value minus one.) Used if and only if ENABLE_BOOTSEL_NON_DEFAULT_PLL_XOSC_CFG is set in BOOT_FLAGS0. That bit should be set only after this row and BOOTSEL_XOSC_CFG are both correctly programmed."]
+    #[inline(always)]
+    pub const fn bootsel_pll_cfg(
+        self,
+    ) -> crate::common::Reg<regs::BootselPllCfg, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(348usize) as _) }
+    }
+    #[doc = "Non-default crystal oscillator configuration for the USB bootloader. (ECC) These values may also be used by user code configuring the crystal oscillator. Used if and only if ENABLE_BOOTSEL_NON_DEFAULT_PLL_XOSC_CFG is set in BOOT_FLAGS0. That bit should be set only after this row and BOOTSEL_PLL_CFG are both correctly programmed."]
+    #[inline(always)]
+    pub const fn bootsel_xosc_cfg(
+        self,
+    ) -> crate::common::Reg<regs::BootselXoscCfg, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(352usize) as _) }
+    }
+    #[doc = "USB boot specific feature flags (RBIT-3)"]
+    #[inline(always)]
+    pub const fn usb_boot_flags(self) -> crate::common::Reg<regs::UsbBootFlags, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(356usize) as _) }
+    }
+    #[doc = "Redundant copy of USB_BOOT_FLAGS"]
+    #[inline(always)]
+    pub const fn usb_boot_flags_r1(
+        self,
+    ) -> crate::common::Reg<regs::UsbBootFlagsR1, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(360usize) as _) }
+    }
+    #[doc = "Redundant copy of USB_BOOT_FLAGS"]
+    #[inline(always)]
+    pub const fn usb_boot_flags_r2(
+        self,
+    ) -> crate::common::Reg<regs::UsbBootFlagsR2, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(364usize) as _) }
+    }
+    #[doc = "Row index of the USB_WHITE_LABEL structure within OTP (ECC) The table has 16 rows, each of which are also ECC and marked valid by the corresponding valid bit in USB_BOOT_FLAGS (ECC). The entries are either _VALUEs where the 16 bit value is used as is, or _STRDEFs which acts as a pointers to a string value. The value stored in a _STRDEF is two separate bytes: The low seven bits of the first (LSB) byte indicates the number of characters in the string, and the top bit of the first (LSB) byte if set to indicate that each character in the string is two bytes (Unicode) versus one byte if unset. The second (MSB) byte represents the location of the string data, and is encoded as the number of rows from this USB_WHITE_LABEL_ADDR; i.e. the row of the start of the string is USB_WHITE_LABEL_ADDR value + msb_byte. In each case, the corresponding valid bit enables replacing the default value for the corresponding item provided by the boot rom. Note that Unicode _STRDEFs are only supported for USB_DEVICE_PRODUCT_STRDEF, USB_DEVICE_SERIAL_NUMBER_STRDEF and USB_DEVICE_MANUFACTURER_STRDEF. Unicode values will be ignored if specified for other fields, and non-unicode values for these three items will be converted to Unicode characters by setting the upper 8 bits to zero. Note that if the USB_WHITE_LABEL structure or the corresponding strings are not readable by BOOTSEL mode based on OTP permissions, or if alignment requirements are not met, then the corresponding default values are used. The index values indicate where each field is located (row USB_WHITE_LABEL_ADDR value + index):"]
+    #[inline(always)]
+    pub const fn usb_white_label_addr(
+        self,
+    ) -> crate::common::Reg<regs::UsbWhiteLabelAddr, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(368usize) as _) }
+    }
+    #[doc = "OTP start row for the OTP boot image. (ECC) If OTP boot is enabled, the bootrom will load from this location into SRAM and then directly enter the loaded image. Note that the image must be signed if SECURE_BOOT_ENABLE is set. The image itself is assumed to be ECC-protected. This must be an even number. Equivalently, the OTP boot image must start at a word-aligned location in the ECC read data address window."]
+    #[inline(always)]
+    pub const fn otpboot_src(self) -> crate::common::Reg<regs::OtpbootSrc, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(376usize) as _) }
+    }
+    #[doc = "Length in rows of the OTP boot image. (ECC) OTPBOOT_LEN must be even. The total image size must be a multiple of 4 bytes (32 bits)."]
+    #[inline(always)]
+    pub const fn otpboot_len(self) -> crate::common::Reg<regs::OtpbootLen, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(380usize) as _) }
+    }
+    #[doc = "Bits 15:0 of the OTP boot image load destination (and entry point). (ECC) This must be a location in main SRAM (main SRAM is addresses 0x20000000 through 0x20082000) and must be word-aligned."]
+    #[inline(always)]
+    pub const fn otpboot_dst0(self) -> crate::common::Reg<regs::OtpbootDst0, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(384usize) as _) }
+    }
+    #[doc = "Bits 31:16 of the OTP boot image load destination (and entry point). (ECC) This must be a location in main SRAM (main SRAM is addresses 0x20000000 through 0x20082000) and must be word-aligned."]
+    #[inline(always)]
+    pub const fn otpboot_dst1(self) -> crate::common::Reg<regs::OtpbootDst1, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(388usize) as _) }
+    }
+    #[doc = "Bits 15:0 of SHA-256 hash of boot key 0 (ECC)"]
+    #[inline(always)]
+    pub const fn bootkey0_0(self) -> crate::common::Reg<regs::Bootkey00, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(512usize) as _) }
+    }
+    #[doc = "Bits 31:16 of SHA-256 hash of boot key 0 (ECC)"]
+    #[inline(always)]
+    pub const fn bootkey0_1(self) -> crate::common::Reg<regs::Bootkey01, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(516usize) as _) }
+    }
+    #[doc = "Bits 47:32 of SHA-256 hash of boot key 0 (ECC)"]
+    #[inline(always)]
+    pub const fn bootkey0_2(self) -> crate::common::Reg<regs::Bootkey02, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(520usize) as _) }
+    }
+    #[doc = "Bits 63:48 of SHA-256 hash of boot key 0 (ECC)"]
+    #[inline(always)]
+    pub const fn bootkey0_3(self) -> crate::common::Reg<regs::Bootkey03, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(524usize) as _) }
+    }
+    #[doc = "Bits 79:64 of SHA-256 hash of boot key 0 (ECC)"]
+    #[inline(always)]
+    pub const fn bootkey0_4(self) -> crate::common::Reg<regs::Bootkey04, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(528usize) as _) }
+    }
+    #[doc = "Bits 95:80 of SHA-256 hash of boot key 0 (ECC)"]
+    #[inline(always)]
+    pub const fn bootkey0_5(self) -> crate::common::Reg<regs::Bootkey05, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(532usize) as _) }
+    }
+    #[doc = "Bits 111:96 of SHA-256 hash of boot key 0 (ECC)"]
+    #[inline(always)]
+    pub const fn bootkey0_6(self) -> crate::common::Reg<regs::Bootkey06, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(536usize) as _) }
+    }
+    #[doc = "Bits 127:112 of SHA-256 hash of boot key 0 (ECC)"]
+    #[inline(always)]
+    pub const fn bootkey0_7(self) -> crate::common::Reg<regs::Bootkey07, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(540usize) as _) }
+    }
+    #[doc = "Bits 143:128 of SHA-256 hash of boot key 0 (ECC)"]
+    #[inline(always)]
+    pub const fn bootkey0_8(self) -> crate::common::Reg<regs::Bootkey08, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(544usize) as _) }
+    }
+    #[doc = "Bits 159:144 of SHA-256 hash of boot key 0 (ECC)"]
+    #[inline(always)]
+    pub const fn bootkey0_9(self) -> crate::common::Reg<regs::Bootkey09, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(548usize) as _) }
+    }
+    #[doc = "Bits 175:160 of SHA-256 hash of boot key 0 (ECC)"]
+    #[inline(always)]
+    pub const fn bootkey0_10(self) -> crate::common::Reg<regs::Bootkey010, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(552usize) as _) }
+    }
+    #[doc = "Bits 191:176 of SHA-256 hash of boot key 0 (ECC)"]
+    #[inline(always)]
+    pub const fn bootkey0_11(self) -> crate::common::Reg<regs::Bootkey011, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(556usize) as _) }
+    }
+    #[doc = "Bits 207:192 of SHA-256 hash of boot key 0 (ECC)"]
+    #[inline(always)]
+    pub const fn bootkey0_12(self) -> crate::common::Reg<regs::Bootkey012, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(560usize) as _) }
+    }
+    #[doc = "Bits 223:208 of SHA-256 hash of boot key 0 (ECC)"]
+    #[inline(always)]
+    pub const fn bootkey0_13(self) -> crate::common::Reg<regs::Bootkey013, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(564usize) as _) }
+    }
+    #[doc = "Bits 239:224 of SHA-256 hash of boot key 0 (ECC)"]
+    #[inline(always)]
+    pub const fn bootkey0_14(self) -> crate::common::Reg<regs::Bootkey014, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(568usize) as _) }
+    }
+    #[doc = "Bits 255:240 of SHA-256 hash of boot key 0 (ECC)"]
+    #[inline(always)]
+    pub const fn bootkey0_15(self) -> crate::common::Reg<regs::Bootkey015, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(572usize) as _) }
+    }
+    #[doc = "Bits 15:0 of SHA-256 hash of boot key 1 (ECC)"]
+    #[inline(always)]
+    pub const fn bootkey1_0(self) -> crate::common::Reg<regs::Bootkey10, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(576usize) as _) }
+    }
+    #[doc = "Bits 31:16 of SHA-256 hash of boot key 1 (ECC)"]
+    #[inline(always)]
+    pub const fn bootkey1_1(self) -> crate::common::Reg<regs::Bootkey11, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(580usize) as _) }
+    }
+    #[doc = "Bits 47:32 of SHA-256 hash of boot key 1 (ECC)"]
+    #[inline(always)]
+    pub const fn bootkey1_2(self) -> crate::common::Reg<regs::Bootkey12, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(584usize) as _) }
+    }
+    #[doc = "Bits 63:48 of SHA-256 hash of boot key 1 (ECC)"]
+    #[inline(always)]
+    pub const fn bootkey1_3(self) -> crate::common::Reg<regs::Bootkey13, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(588usize) as _) }
+    }
+    #[doc = "Bits 79:64 of SHA-256 hash of boot key 1 (ECC)"]
+    #[inline(always)]
+    pub const fn bootkey1_4(self) -> crate::common::Reg<regs::Bootkey14, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(592usize) as _) }
+    }
+    #[doc = "Bits 95:80 of SHA-256 hash of boot key 1 (ECC)"]
+    #[inline(always)]
+    pub const fn bootkey1_5(self) -> crate::common::Reg<regs::Bootkey15, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(596usize) as _) }
+    }
+    #[doc = "Bits 111:96 of SHA-256 hash of boot key 1 (ECC)"]
+    #[inline(always)]
+    pub const fn bootkey1_6(self) -> crate::common::Reg<regs::Bootkey16, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(600usize) as _) }
+    }
+    #[doc = "Bits 127:112 of SHA-256 hash of boot key 1 (ECC)"]
+    #[inline(always)]
+    pub const fn bootkey1_7(self) -> crate::common::Reg<regs::Bootkey17, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(604usize) as _) }
+    }
+    #[doc = "Bits 143:128 of SHA-256 hash of boot key 1 (ECC)"]
+    #[inline(always)]
+    pub const fn bootkey1_8(self) -> crate::common::Reg<regs::Bootkey18, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(608usize) as _) }
+    }
+    #[doc = "Bits 159:144 of SHA-256 hash of boot key 1 (ECC)"]
+    #[inline(always)]
+    pub const fn bootkey1_9(self) -> crate::common::Reg<regs::Bootkey19, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(612usize) as _) }
+    }
+    #[doc = "Bits 175:160 of SHA-256 hash of boot key 1 (ECC)"]
+    #[inline(always)]
+    pub const fn bootkey1_10(self) -> crate::common::Reg<regs::Bootkey110, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(616usize) as _) }
+    }
+    #[doc = "Bits 191:176 of SHA-256 hash of boot key 1 (ECC)"]
+    #[inline(always)]
+    pub const fn bootkey1_11(self) -> crate::common::Reg<regs::Bootkey111, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(620usize) as _) }
+    }
+    #[doc = "Bits 207:192 of SHA-256 hash of boot key 1 (ECC)"]
+    #[inline(always)]
+    pub const fn bootkey1_12(self) -> crate::common::Reg<regs::Bootkey112, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(624usize) as _) }
+    }
+    #[doc = "Bits 223:208 of SHA-256 hash of boot key 1 (ECC)"]
+    #[inline(always)]
+    pub const fn bootkey1_13(self) -> crate::common::Reg<regs::Bootkey113, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(628usize) as _) }
+    }
+    #[doc = "Bits 239:224 of SHA-256 hash of boot key 1 (ECC)"]
+    #[inline(always)]
+    pub const fn bootkey1_14(self) -> crate::common::Reg<regs::Bootkey114, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(632usize) as _) }
+    }
+    #[doc = "Bits 255:240 of SHA-256 hash of boot key 1 (ECC)"]
+    #[inline(always)]
+    pub const fn bootkey1_15(self) -> crate::common::Reg<regs::Bootkey115, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(636usize) as _) }
+    }
+    #[doc = "Bits 15:0 of SHA-256 hash of boot key 2 (ECC)"]
+    #[inline(always)]
+    pub const fn bootkey2_0(self) -> crate::common::Reg<regs::Bootkey20, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(640usize) as _) }
+    }
+    #[doc = "Bits 31:16 of SHA-256 hash of boot key 2 (ECC)"]
+    #[inline(always)]
+    pub const fn bootkey2_1(self) -> crate::common::Reg<regs::Bootkey21, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(644usize) as _) }
+    }
+    #[doc = "Bits 47:32 of SHA-256 hash of boot key 2 (ECC)"]
+    #[inline(always)]
+    pub const fn bootkey2_2(self) -> crate::common::Reg<regs::Bootkey22, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(648usize) as _) }
+    }
+    #[doc = "Bits 63:48 of SHA-256 hash of boot key 2 (ECC)"]
+    #[inline(always)]
+    pub const fn bootkey2_3(self) -> crate::common::Reg<regs::Bootkey23, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(652usize) as _) }
+    }
+    #[doc = "Bits 79:64 of SHA-256 hash of boot key 2 (ECC)"]
+    #[inline(always)]
+    pub const fn bootkey2_4(self) -> crate::common::Reg<regs::Bootkey24, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(656usize) as _) }
+    }
+    #[doc = "Bits 95:80 of SHA-256 hash of boot key 2 (ECC)"]
+    #[inline(always)]
+    pub const fn bootkey2_5(self) -> crate::common::Reg<regs::Bootkey25, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(660usize) as _) }
+    }
+    #[doc = "Bits 111:96 of SHA-256 hash of boot key 2 (ECC)"]
+    #[inline(always)]
+    pub const fn bootkey2_6(self) -> crate::common::Reg<regs::Bootkey26, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(664usize) as _) }
+    }
+    #[doc = "Bits 127:112 of SHA-256 hash of boot key 2 (ECC)"]
+    #[inline(always)]
+    pub const fn bootkey2_7(self) -> crate::common::Reg<regs::Bootkey27, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(668usize) as _) }
+    }
+    #[doc = "Bits 143:128 of SHA-256 hash of boot key 2 (ECC)"]
+    #[inline(always)]
+    pub const fn bootkey2_8(self) -> crate::common::Reg<regs::Bootkey28, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(672usize) as _) }
+    }
+    #[doc = "Bits 159:144 of SHA-256 hash of boot key 2 (ECC)"]
+    #[inline(always)]
+    pub const fn bootkey2_9(self) -> crate::common::Reg<regs::Bootkey29, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(676usize) as _) }
+    }
+    #[doc = "Bits 175:160 of SHA-256 hash of boot key 2 (ECC)"]
+    #[inline(always)]
+    pub const fn bootkey2_10(self) -> crate::common::Reg<regs::Bootkey210, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(680usize) as _) }
+    }
+    #[doc = "Bits 191:176 of SHA-256 hash of boot key 2 (ECC)"]
+    #[inline(always)]
+    pub const fn bootkey2_11(self) -> crate::common::Reg<regs::Bootkey211, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(684usize) as _) }
+    }
+    #[doc = "Bits 207:192 of SHA-256 hash of boot key 2 (ECC)"]
+    #[inline(always)]
+    pub const fn bootkey2_12(self) -> crate::common::Reg<regs::Bootkey212, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(688usize) as _) }
+    }
+    #[doc = "Bits 223:208 of SHA-256 hash of boot key 2 (ECC)"]
+    #[inline(always)]
+    pub const fn bootkey2_13(self) -> crate::common::Reg<regs::Bootkey213, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(692usize) as _) }
+    }
+    #[doc = "Bits 239:224 of SHA-256 hash of boot key 2 (ECC)"]
+    #[inline(always)]
+    pub const fn bootkey2_14(self) -> crate::common::Reg<regs::Bootkey214, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(696usize) as _) }
+    }
+    #[doc = "Bits 255:240 of SHA-256 hash of boot key 2 (ECC)"]
+    #[inline(always)]
+    pub const fn bootkey2_15(self) -> crate::common::Reg<regs::Bootkey215, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(700usize) as _) }
+    }
+    #[doc = "Bits 15:0 of SHA-256 hash of boot key 3 (ECC)"]
+    #[inline(always)]
+    pub const fn bootkey3_0(self) -> crate::common::Reg<regs::Bootkey30, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(704usize) as _) }
+    }
+    #[doc = "Bits 31:16 of SHA-256 hash of boot key 3 (ECC)"]
+    #[inline(always)]
+    pub const fn bootkey3_1(self) -> crate::common::Reg<regs::Bootkey31, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(708usize) as _) }
+    }
+    #[doc = "Bits 47:32 of SHA-256 hash of boot key 3 (ECC)"]
+    #[inline(always)]
+    pub const fn bootkey3_2(self) -> crate::common::Reg<regs::Bootkey32, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(712usize) as _) }
+    }
+    #[doc = "Bits 63:48 of SHA-256 hash of boot key 3 (ECC)"]
+    #[inline(always)]
+    pub const fn bootkey3_3(self) -> crate::common::Reg<regs::Bootkey33, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(716usize) as _) }
+    }
+    #[doc = "Bits 79:64 of SHA-256 hash of boot key 3 (ECC)"]
+    #[inline(always)]
+    pub const fn bootkey3_4(self) -> crate::common::Reg<regs::Bootkey34, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(720usize) as _) }
+    }
+    #[doc = "Bits 95:80 of SHA-256 hash of boot key 3 (ECC)"]
+    #[inline(always)]
+    pub const fn bootkey3_5(self) -> crate::common::Reg<regs::Bootkey35, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(724usize) as _) }
+    }
+    #[doc = "Bits 111:96 of SHA-256 hash of boot key 3 (ECC)"]
+    #[inline(always)]
+    pub const fn bootkey3_6(self) -> crate::common::Reg<regs::Bootkey36, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(728usize) as _) }
+    }
+    #[doc = "Bits 127:112 of SHA-256 hash of boot key 3 (ECC)"]
+    #[inline(always)]
+    pub const fn bootkey3_7(self) -> crate::common::Reg<regs::Bootkey37, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(732usize) as _) }
+    }
+    #[doc = "Bits 143:128 of SHA-256 hash of boot key 3 (ECC)"]
+    #[inline(always)]
+    pub const fn bootkey3_8(self) -> crate::common::Reg<regs::Bootkey38, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(736usize) as _) }
+    }
+    #[doc = "Bits 159:144 of SHA-256 hash of boot key 3 (ECC)"]
+    #[inline(always)]
+    pub const fn bootkey3_9(self) -> crate::common::Reg<regs::Bootkey39, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(740usize) as _) }
+    }
+    #[doc = "Bits 175:160 of SHA-256 hash of boot key 3 (ECC)"]
+    #[inline(always)]
+    pub const fn bootkey3_10(self) -> crate::common::Reg<regs::Bootkey310, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(744usize) as _) }
+    }
+    #[doc = "Bits 191:176 of SHA-256 hash of boot key 3 (ECC)"]
+    #[inline(always)]
+    pub const fn bootkey3_11(self) -> crate::common::Reg<regs::Bootkey311, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(748usize) as _) }
+    }
+    #[doc = "Bits 207:192 of SHA-256 hash of boot key 3 (ECC)"]
+    #[inline(always)]
+    pub const fn bootkey3_12(self) -> crate::common::Reg<regs::Bootkey312, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(752usize) as _) }
+    }
+    #[doc = "Bits 223:208 of SHA-256 hash of boot key 3 (ECC)"]
+    #[inline(always)]
+    pub const fn bootkey3_13(self) -> crate::common::Reg<regs::Bootkey313, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(756usize) as _) }
+    }
+    #[doc = "Bits 239:224 of SHA-256 hash of boot key 3 (ECC)"]
+    #[inline(always)]
+    pub const fn bootkey3_14(self) -> crate::common::Reg<regs::Bootkey314, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(760usize) as _) }
+    }
+    #[doc = "Bits 255:240 of SHA-256 hash of boot key 3 (ECC)"]
+    #[inline(always)]
+    pub const fn bootkey3_15(self) -> crate::common::Reg<regs::Bootkey315, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(764usize) as _) }
+    }
+    #[doc = "Bits 15:0 of OTP access key 1 (ECC)"]
+    #[inline(always)]
+    pub const fn key1_0(self) -> crate::common::Reg<regs::Key10, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(15648usize) as _) }
+    }
+    #[doc = "Bits 31:16 of OTP access key 1 (ECC)"]
+    #[inline(always)]
+    pub const fn key1_1(self) -> crate::common::Reg<regs::Key11, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(15652usize) as _) }
+    }
+    #[doc = "Bits 47:32 of OTP access key 1 (ECC)"]
+    #[inline(always)]
+    pub const fn key1_2(self) -> crate::common::Reg<regs::Key12, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(15656usize) as _) }
+    }
+    #[doc = "Bits 63:48 of OTP access key 1 (ECC)"]
+    #[inline(always)]
+    pub const fn key1_3(self) -> crate::common::Reg<regs::Key13, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(15660usize) as _) }
+    }
+    #[doc = "Bits 79:64 of OTP access key 1 (ECC)"]
+    #[inline(always)]
+    pub const fn key1_4(self) -> crate::common::Reg<regs::Key14, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(15664usize) as _) }
+    }
+    #[doc = "Bits 95:80 of OTP access key 1 (ECC)"]
+    #[inline(always)]
+    pub const fn key1_5(self) -> crate::common::Reg<regs::Key15, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(15668usize) as _) }
+    }
+    #[doc = "Bits 111:96 of OTP access key 1 (ECC)"]
+    #[inline(always)]
+    pub const fn key1_6(self) -> crate::common::Reg<regs::Key16, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(15672usize) as _) }
+    }
+    #[doc = "Bits 127:112 of OTP access key 1 (ECC)"]
+    #[inline(always)]
+    pub const fn key1_7(self) -> crate::common::Reg<regs::Key17, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(15676usize) as _) }
+    }
+    #[doc = "Bits 15:0 of OTP access key 2 (ECC)"]
+    #[inline(always)]
+    pub const fn key2_0(self) -> crate::common::Reg<regs::Key20, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(15680usize) as _) }
+    }
+    #[doc = "Bits 31:16 of OTP access key 2 (ECC)"]
+    #[inline(always)]
+    pub const fn key2_1(self) -> crate::common::Reg<regs::Key21, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(15684usize) as _) }
+    }
+    #[doc = "Bits 47:32 of OTP access key 2 (ECC)"]
+    #[inline(always)]
+    pub const fn key2_2(self) -> crate::common::Reg<regs::Key22, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(15688usize) as _) }
+    }
+    #[doc = "Bits 63:48 of OTP access key 2 (ECC)"]
+    #[inline(always)]
+    pub const fn key2_3(self) -> crate::common::Reg<regs::Key23, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(15692usize) as _) }
+    }
+    #[doc = "Bits 79:64 of OTP access key 2 (ECC)"]
+    #[inline(always)]
+    pub const fn key2_4(self) -> crate::common::Reg<regs::Key24, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(15696usize) as _) }
+    }
+    #[doc = "Bits 95:80 of OTP access key 2 (ECC)"]
+    #[inline(always)]
+    pub const fn key2_5(self) -> crate::common::Reg<regs::Key25, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(15700usize) as _) }
+    }
+    #[doc = "Bits 111:96 of OTP access key 2 (ECC)"]
+    #[inline(always)]
+    pub const fn key2_6(self) -> crate::common::Reg<regs::Key26, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(15704usize) as _) }
+    }
+    #[doc = "Bits 127:112 of OTP access key 2 (ECC)"]
+    #[inline(always)]
+    pub const fn key2_7(self) -> crate::common::Reg<regs::Key27, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(15708usize) as _) }
+    }
+    #[doc = "Bits 15:0 of OTP access key 3 (ECC)"]
+    #[inline(always)]
+    pub const fn key3_0(self) -> crate::common::Reg<regs::Key30, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(15712usize) as _) }
+    }
+    #[doc = "Bits 31:16 of OTP access key 3 (ECC)"]
+    #[inline(always)]
+    pub const fn key3_1(self) -> crate::common::Reg<regs::Key31, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(15716usize) as _) }
+    }
+    #[doc = "Bits 47:32 of OTP access key 3 (ECC)"]
+    #[inline(always)]
+    pub const fn key3_2(self) -> crate::common::Reg<regs::Key32, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(15720usize) as _) }
+    }
+    #[doc = "Bits 63:48 of OTP access key 3 (ECC)"]
+    #[inline(always)]
+    pub const fn key3_3(self) -> crate::common::Reg<regs::Key33, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(15724usize) as _) }
+    }
+    #[doc = "Bits 79:64 of OTP access key 3 (ECC)"]
+    #[inline(always)]
+    pub const fn key3_4(self) -> crate::common::Reg<regs::Key34, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(15728usize) as _) }
+    }
+    #[doc = "Bits 95:80 of OTP access key 3 (ECC)"]
+    #[inline(always)]
+    pub const fn key3_5(self) -> crate::common::Reg<regs::Key35, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(15732usize) as _) }
+    }
+    #[doc = "Bits 111:96 of OTP access key 3 (ECC)"]
+    #[inline(always)]
+    pub const fn key3_6(self) -> crate::common::Reg<regs::Key36, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(15736usize) as _) }
+    }
+    #[doc = "Bits 127:112 of OTP access key 3 (ECC)"]
+    #[inline(always)]
+    pub const fn key3_7(self) -> crate::common::Reg<regs::Key37, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(15740usize) as _) }
+    }
+    #[doc = "Bits 15:0 of OTP access key 4 (ECC)"]
+    #[inline(always)]
+    pub const fn key4_0(self) -> crate::common::Reg<regs::Key40, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(15744usize) as _) }
+    }
+    #[doc = "Bits 31:16 of OTP access key 4 (ECC)"]
+    #[inline(always)]
+    pub const fn key4_1(self) -> crate::common::Reg<regs::Key41, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(15748usize) as _) }
+    }
+    #[doc = "Bits 47:32 of OTP access key 4 (ECC)"]
+    #[inline(always)]
+    pub const fn key4_2(self) -> crate::common::Reg<regs::Key42, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(15752usize) as _) }
+    }
+    #[doc = "Bits 63:48 of OTP access key 4 (ECC)"]
+    #[inline(always)]
+    pub const fn key4_3(self) -> crate::common::Reg<regs::Key43, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(15756usize) as _) }
+    }
+    #[doc = "Bits 79:64 of OTP access key 4 (ECC)"]
+    #[inline(always)]
+    pub const fn key4_4(self) -> crate::common::Reg<regs::Key44, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(15760usize) as _) }
+    }
+    #[doc = "Bits 95:80 of OTP access key 4 (ECC)"]
+    #[inline(always)]
+    pub const fn key4_5(self) -> crate::common::Reg<regs::Key45, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(15764usize) as _) }
+    }
+    #[doc = "Bits 111:96 of OTP access key 4 (ECC)"]
+    #[inline(always)]
+    pub const fn key4_6(self) -> crate::common::Reg<regs::Key46, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(15768usize) as _) }
+    }
+    #[doc = "Bits 127:112 of OTP access key 4 (ECC)"]
+    #[inline(always)]
+    pub const fn key4_7(self) -> crate::common::Reg<regs::Key47, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(15772usize) as _) }
+    }
+    #[doc = "Bits 15:0 of OTP access key 5 (ECC)"]
+    #[inline(always)]
+    pub const fn key5_0(self) -> crate::common::Reg<regs::Key50, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(15776usize) as _) }
+    }
+    #[doc = "Bits 31:16 of OTP access key 5 (ECC)"]
+    #[inline(always)]
+    pub const fn key5_1(self) -> crate::common::Reg<regs::Key51, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(15780usize) as _) }
+    }
+    #[doc = "Bits 47:32 of OTP access key 5 (ECC)"]
+    #[inline(always)]
+    pub const fn key5_2(self) -> crate::common::Reg<regs::Key52, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(15784usize) as _) }
+    }
+    #[doc = "Bits 63:48 of OTP access key 5 (ECC)"]
+    #[inline(always)]
+    pub const fn key5_3(self) -> crate::common::Reg<regs::Key53, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(15788usize) as _) }
+    }
+    #[doc = "Bits 79:64 of OTP access key 5 (ECC)"]
+    #[inline(always)]
+    pub const fn key5_4(self) -> crate::common::Reg<regs::Key54, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(15792usize) as _) }
+    }
+    #[doc = "Bits 95:80 of OTP access key 5 (ECC)"]
+    #[inline(always)]
+    pub const fn key5_5(self) -> crate::common::Reg<regs::Key55, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(15796usize) as _) }
+    }
+    #[doc = "Bits 111:96 of OTP access key 5 (ECC)"]
+    #[inline(always)]
+    pub const fn key5_6(self) -> crate::common::Reg<regs::Key56, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(15800usize) as _) }
+    }
+    #[doc = "Bits 127:112 of OTP access key 5 (ECC)"]
+    #[inline(always)]
+    pub const fn key5_7(self) -> crate::common::Reg<regs::Key57, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(15804usize) as _) }
+    }
+    #[doc = "Bits 15:0 of OTP access key 6 (ECC)"]
+    #[inline(always)]
+    pub const fn key6_0(self) -> crate::common::Reg<regs::Key60, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(15808usize) as _) }
+    }
+    #[doc = "Bits 31:16 of OTP access key 6 (ECC)"]
+    #[inline(always)]
+    pub const fn key6_1(self) -> crate::common::Reg<regs::Key61, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(15812usize) as _) }
+    }
+    #[doc = "Bits 47:32 of OTP access key 6 (ECC)"]
+    #[inline(always)]
+    pub const fn key6_2(self) -> crate::common::Reg<regs::Key62, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(15816usize) as _) }
+    }
+    #[doc = "Bits 63:48 of OTP access key 6 (ECC)"]
+    #[inline(always)]
+    pub const fn key6_3(self) -> crate::common::Reg<regs::Key63, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(15820usize) as _) }
+    }
+    #[doc = "Bits 79:64 of OTP access key 6 (ECC)"]
+    #[inline(always)]
+    pub const fn key6_4(self) -> crate::common::Reg<regs::Key64, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(15824usize) as _) }
+    }
+    #[doc = "Bits 95:80 of OTP access key 6 (ECC)"]
+    #[inline(always)]
+    pub const fn key6_5(self) -> crate::common::Reg<regs::Key65, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(15828usize) as _) }
+    }
+    #[doc = "Bits 111:96 of OTP access key 6 (ECC)"]
+    #[inline(always)]
+    pub const fn key6_6(self) -> crate::common::Reg<regs::Key66, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(15832usize) as _) }
+    }
+    #[doc = "Bits 127:112 of OTP access key 6 (ECC)"]
+    #[inline(always)]
+    pub const fn key6_7(self) -> crate::common::Reg<regs::Key67, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(15836usize) as _) }
+    }
+    #[doc = "Valid flag for key 1. Once the valid flag is set, the key can no longer be read or written, and becomes a valid fixed key for protecting OTP pages."]
+    #[inline(always)]
+    pub const fn key1_valid(self) -> crate::common::Reg<regs::Key1valid, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(15844usize) as _) }
+    }
+    #[doc = "Valid flag for key 2. Once the valid flag is set, the key can no longer be read or written, and becomes a valid fixed key for protecting OTP pages."]
+    #[inline(always)]
+    pub const fn key2_valid(self) -> crate::common::Reg<regs::Key2valid, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(15848usize) as _) }
+    }
+    #[doc = "Valid flag for key 3. Once the valid flag is set, the key can no longer be read or written, and becomes a valid fixed key for protecting OTP pages."]
+    #[inline(always)]
+    pub const fn key3_valid(self) -> crate::common::Reg<regs::Key3valid, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(15852usize) as _) }
+    }
+    #[doc = "Valid flag for key 4. Once the valid flag is set, the key can no longer be read or written, and becomes a valid fixed key for protecting OTP pages."]
+    #[inline(always)]
+    pub const fn key4_valid(self) -> crate::common::Reg<regs::Key4valid, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(15856usize) as _) }
+    }
+    #[doc = "Valid flag for key 5. Once the valid flag is set, the key can no longer be read or written, and becomes a valid fixed key for protecting OTP pages."]
+    #[inline(always)]
+    pub const fn key5_valid(self) -> crate::common::Reg<regs::Key5valid, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(15860usize) as _) }
+    }
+    #[doc = "Valid flag for key 6. Once the valid flag is set, the key can no longer be read or written, and becomes a valid fixed key for protecting OTP pages."]
+    #[inline(always)]
+    pub const fn key6_valid(self) -> crate::common::Reg<regs::Key6valid, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(15864usize) as _) }
+    }
+    #[doc = "Lock configuration LSBs for page 0 (rows 0x0 through 0x3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+    #[inline(always)]
+    pub const fn page0_lock0(self) -> crate::common::Reg<regs::Page0lock0, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(15872usize) as _) }
+    }
+    #[doc = "Lock configuration MSBs for page 0 (rows 0x0 through 0x3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+    #[inline(always)]
+    pub const fn page0_lock1(self) -> crate::common::Reg<regs::Page0lock1, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(15876usize) as _) }
+    }
+    #[doc = "Lock configuration LSBs for page 1 (rows 0x40 through 0x7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+    #[inline(always)]
+    pub const fn page1_lock0(self) -> crate::common::Reg<regs::Page1lock0, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(15880usize) as _) }
+    }
+    #[doc = "Lock configuration MSBs for page 1 (rows 0x40 through 0x7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+    #[inline(always)]
+    pub const fn page1_lock1(self) -> crate::common::Reg<regs::Page1lock1, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(15884usize) as _) }
+    }
+    #[doc = "Lock configuration LSBs for page 2 (rows 0x80 through 0xbf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+    #[inline(always)]
+    pub const fn page2_lock0(self) -> crate::common::Reg<regs::Page2lock0, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(15888usize) as _) }
+    }
+    #[doc = "Lock configuration MSBs for page 2 (rows 0x80 through 0xbf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+    #[inline(always)]
+    pub const fn page2_lock1(self) -> crate::common::Reg<regs::Page2lock1, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(15892usize) as _) }
+    }
+    #[doc = "Lock configuration LSBs for page 3 (rows 0xc0 through 0xff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+    #[inline(always)]
+    pub const fn page3_lock0(self) -> crate::common::Reg<regs::Page3lock0, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(15896usize) as _) }
+    }
+    #[doc = "Lock configuration MSBs for page 3 (rows 0xc0 through 0xff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+    #[inline(always)]
+    pub const fn page3_lock1(self) -> crate::common::Reg<regs::Page3lock1, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(15900usize) as _) }
+    }
+    #[doc = "Lock configuration LSBs for page 4 (rows 0x100 through 0x13f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+    #[inline(always)]
+    pub const fn page4_lock0(self) -> crate::common::Reg<regs::Page4lock0, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(15904usize) as _) }
+    }
+    #[doc = "Lock configuration MSBs for page 4 (rows 0x100 through 0x13f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+    #[inline(always)]
+    pub const fn page4_lock1(self) -> crate::common::Reg<regs::Page4lock1, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(15908usize) as _) }
+    }
+    #[doc = "Lock configuration LSBs for page 5 (rows 0x140 through 0x17f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+    #[inline(always)]
+    pub const fn page5_lock0(self) -> crate::common::Reg<regs::Page5lock0, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(15912usize) as _) }
+    }
+    #[doc = "Lock configuration MSBs for page 5 (rows 0x140 through 0x17f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+    #[inline(always)]
+    pub const fn page5_lock1(self) -> crate::common::Reg<regs::Page5lock1, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(15916usize) as _) }
+    }
+    #[doc = "Lock configuration LSBs for page 6 (rows 0x180 through 0x1bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+    #[inline(always)]
+    pub const fn page6_lock0(self) -> crate::common::Reg<regs::Page6lock0, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(15920usize) as _) }
+    }
+    #[doc = "Lock configuration MSBs for page 6 (rows 0x180 through 0x1bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+    #[inline(always)]
+    pub const fn page6_lock1(self) -> crate::common::Reg<regs::Page6lock1, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(15924usize) as _) }
+    }
+    #[doc = "Lock configuration LSBs for page 7 (rows 0x1c0 through 0x1ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+    #[inline(always)]
+    pub const fn page7_lock0(self) -> crate::common::Reg<regs::Page7lock0, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(15928usize) as _) }
+    }
+    #[doc = "Lock configuration MSBs for page 7 (rows 0x1c0 through 0x1ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+    #[inline(always)]
+    pub const fn page7_lock1(self) -> crate::common::Reg<regs::Page7lock1, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(15932usize) as _) }
+    }
+    #[doc = "Lock configuration LSBs for page 8 (rows 0x200 through 0x23f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+    #[inline(always)]
+    pub const fn page8_lock0(self) -> crate::common::Reg<regs::Page8lock0, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(15936usize) as _) }
+    }
+    #[doc = "Lock configuration MSBs for page 8 (rows 0x200 through 0x23f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+    #[inline(always)]
+    pub const fn page8_lock1(self) -> crate::common::Reg<regs::Page8lock1, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(15940usize) as _) }
+    }
+    #[doc = "Lock configuration LSBs for page 9 (rows 0x240 through 0x27f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+    #[inline(always)]
+    pub const fn page9_lock0(self) -> crate::common::Reg<regs::Page9lock0, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(15944usize) as _) }
+    }
+    #[doc = "Lock configuration MSBs for page 9 (rows 0x240 through 0x27f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+    #[inline(always)]
+    pub const fn page9_lock1(self) -> crate::common::Reg<regs::Page9lock1, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(15948usize) as _) }
+    }
+    #[doc = "Lock configuration LSBs for page 10 (rows 0x280 through 0x2bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+    #[inline(always)]
+    pub const fn page10_lock0(self) -> crate::common::Reg<regs::Page10lock0, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(15952usize) as _) }
+    }
+    #[doc = "Lock configuration MSBs for page 10 (rows 0x280 through 0x2bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+    #[inline(always)]
+    pub const fn page10_lock1(self) -> crate::common::Reg<regs::Page10lock1, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(15956usize) as _) }
+    }
+    #[doc = "Lock configuration LSBs for page 11 (rows 0x2c0 through 0x2ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+    #[inline(always)]
+    pub const fn page11_lock0(self) -> crate::common::Reg<regs::Page11lock0, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(15960usize) as _) }
+    }
+    #[doc = "Lock configuration MSBs for page 11 (rows 0x2c0 through 0x2ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+    #[inline(always)]
+    pub const fn page11_lock1(self) -> crate::common::Reg<regs::Page11lock1, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(15964usize) as _) }
+    }
+    #[doc = "Lock configuration LSBs for page 12 (rows 0x300 through 0x33f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+    #[inline(always)]
+    pub const fn page12_lock0(self) -> crate::common::Reg<regs::Page12lock0, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(15968usize) as _) }
+    }
+    #[doc = "Lock configuration MSBs for page 12 (rows 0x300 through 0x33f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+    #[inline(always)]
+    pub const fn page12_lock1(self) -> crate::common::Reg<regs::Page12lock1, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(15972usize) as _) }
+    }
+    #[doc = "Lock configuration LSBs for page 13 (rows 0x340 through 0x37f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+    #[inline(always)]
+    pub const fn page13_lock0(self) -> crate::common::Reg<regs::Page13lock0, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(15976usize) as _) }
+    }
+    #[doc = "Lock configuration MSBs for page 13 (rows 0x340 through 0x37f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+    #[inline(always)]
+    pub const fn page13_lock1(self) -> crate::common::Reg<regs::Page13lock1, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(15980usize) as _) }
+    }
+    #[doc = "Lock configuration LSBs for page 14 (rows 0x380 through 0x3bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+    #[inline(always)]
+    pub const fn page14_lock0(self) -> crate::common::Reg<regs::Page14lock0, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(15984usize) as _) }
+    }
+    #[doc = "Lock configuration MSBs for page 14 (rows 0x380 through 0x3bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+    #[inline(always)]
+    pub const fn page14_lock1(self) -> crate::common::Reg<regs::Page14lock1, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(15988usize) as _) }
+    }
+    #[doc = "Lock configuration LSBs for page 15 (rows 0x3c0 through 0x3ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+    #[inline(always)]
+    pub const fn page15_lock0(self) -> crate::common::Reg<regs::Page15lock0, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(15992usize) as _) }
+    }
+    #[doc = "Lock configuration MSBs for page 15 (rows 0x3c0 through 0x3ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+    #[inline(always)]
+    pub const fn page15_lock1(self) -> crate::common::Reg<regs::Page15lock1, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(15996usize) as _) }
+    }
+    #[doc = "Lock configuration LSBs for page 16 (rows 0x400 through 0x43f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+    #[inline(always)]
+    pub const fn page16_lock0(self) -> crate::common::Reg<regs::Page16lock0, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(16000usize) as _) }
+    }
+    #[doc = "Lock configuration MSBs for page 16 (rows 0x400 through 0x43f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+    #[inline(always)]
+    pub const fn page16_lock1(self) -> crate::common::Reg<regs::Page16lock1, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(16004usize) as _) }
+    }
+    #[doc = "Lock configuration LSBs for page 17 (rows 0x440 through 0x47f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+    #[inline(always)]
+    pub const fn page17_lock0(self) -> crate::common::Reg<regs::Page17lock0, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(16008usize) as _) }
+    }
+    #[doc = "Lock configuration MSBs for page 17 (rows 0x440 through 0x47f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+    #[inline(always)]
+    pub const fn page17_lock1(self) -> crate::common::Reg<regs::Page17lock1, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(16012usize) as _) }
+    }
+    #[doc = "Lock configuration LSBs for page 18 (rows 0x480 through 0x4bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+    #[inline(always)]
+    pub const fn page18_lock0(self) -> crate::common::Reg<regs::Page18lock0, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(16016usize) as _) }
+    }
+    #[doc = "Lock configuration MSBs for page 18 (rows 0x480 through 0x4bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+    #[inline(always)]
+    pub const fn page18_lock1(self) -> crate::common::Reg<regs::Page18lock1, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(16020usize) as _) }
+    }
+    #[doc = "Lock configuration LSBs for page 19 (rows 0x4c0 through 0x4ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+    #[inline(always)]
+    pub const fn page19_lock0(self) -> crate::common::Reg<regs::Page19lock0, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(16024usize) as _) }
+    }
+    #[doc = "Lock configuration MSBs for page 19 (rows 0x4c0 through 0x4ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+    #[inline(always)]
+    pub const fn page19_lock1(self) -> crate::common::Reg<regs::Page19lock1, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(16028usize) as _) }
+    }
+    #[doc = "Lock configuration LSBs for page 20 (rows 0x500 through 0x53f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+    #[inline(always)]
+    pub const fn page20_lock0(self) -> crate::common::Reg<regs::Page20lock0, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(16032usize) as _) }
+    }
+    #[doc = "Lock configuration MSBs for page 20 (rows 0x500 through 0x53f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+    #[inline(always)]
+    pub const fn page20_lock1(self) -> crate::common::Reg<regs::Page20lock1, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(16036usize) as _) }
+    }
+    #[doc = "Lock configuration LSBs for page 21 (rows 0x540 through 0x57f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+    #[inline(always)]
+    pub const fn page21_lock0(self) -> crate::common::Reg<regs::Page21lock0, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(16040usize) as _) }
+    }
+    #[doc = "Lock configuration MSBs for page 21 (rows 0x540 through 0x57f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+    #[inline(always)]
+    pub const fn page21_lock1(self) -> crate::common::Reg<regs::Page21lock1, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(16044usize) as _) }
+    }
+    #[doc = "Lock configuration LSBs for page 22 (rows 0x580 through 0x5bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+    #[inline(always)]
+    pub const fn page22_lock0(self) -> crate::common::Reg<regs::Page22lock0, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(16048usize) as _) }
+    }
+    #[doc = "Lock configuration MSBs for page 22 (rows 0x580 through 0x5bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+    #[inline(always)]
+    pub const fn page22_lock1(self) -> crate::common::Reg<regs::Page22lock1, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(16052usize) as _) }
+    }
+    #[doc = "Lock configuration LSBs for page 23 (rows 0x5c0 through 0x5ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+    #[inline(always)]
+    pub const fn page23_lock0(self) -> crate::common::Reg<regs::Page23lock0, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(16056usize) as _) }
+    }
+    #[doc = "Lock configuration MSBs for page 23 (rows 0x5c0 through 0x5ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+    #[inline(always)]
+    pub const fn page23_lock1(self) -> crate::common::Reg<regs::Page23lock1, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(16060usize) as _) }
+    }
+    #[doc = "Lock configuration LSBs for page 24 (rows 0x600 through 0x63f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+    #[inline(always)]
+    pub const fn page24_lock0(self) -> crate::common::Reg<regs::Page24lock0, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(16064usize) as _) }
+    }
+    #[doc = "Lock configuration MSBs for page 24 (rows 0x600 through 0x63f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+    #[inline(always)]
+    pub const fn page24_lock1(self) -> crate::common::Reg<regs::Page24lock1, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(16068usize) as _) }
+    }
+    #[doc = "Lock configuration LSBs for page 25 (rows 0x640 through 0x67f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+    #[inline(always)]
+    pub const fn page25_lock0(self) -> crate::common::Reg<regs::Page25lock0, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(16072usize) as _) }
+    }
+    #[doc = "Lock configuration MSBs for page 25 (rows 0x640 through 0x67f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+    #[inline(always)]
+    pub const fn page25_lock1(self) -> crate::common::Reg<regs::Page25lock1, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(16076usize) as _) }
+    }
+    #[doc = "Lock configuration LSBs for page 26 (rows 0x680 through 0x6bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+    #[inline(always)]
+    pub const fn page26_lock0(self) -> crate::common::Reg<regs::Page26lock0, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(16080usize) as _) }
+    }
+    #[doc = "Lock configuration MSBs for page 26 (rows 0x680 through 0x6bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+    #[inline(always)]
+    pub const fn page26_lock1(self) -> crate::common::Reg<regs::Page26lock1, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(16084usize) as _) }
+    }
+    #[doc = "Lock configuration LSBs for page 27 (rows 0x6c0 through 0x6ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+    #[inline(always)]
+    pub const fn page27_lock0(self) -> crate::common::Reg<regs::Page27lock0, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(16088usize) as _) }
+    }
+    #[doc = "Lock configuration MSBs for page 27 (rows 0x6c0 through 0x6ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+    #[inline(always)]
+    pub const fn page27_lock1(self) -> crate::common::Reg<regs::Page27lock1, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(16092usize) as _) }
+    }
+    #[doc = "Lock configuration LSBs for page 28 (rows 0x700 through 0x73f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+    #[inline(always)]
+    pub const fn page28_lock0(self) -> crate::common::Reg<regs::Page28lock0, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(16096usize) as _) }
+    }
+    #[doc = "Lock configuration MSBs for page 28 (rows 0x700 through 0x73f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+    #[inline(always)]
+    pub const fn page28_lock1(self) -> crate::common::Reg<regs::Page28lock1, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(16100usize) as _) }
+    }
+    #[doc = "Lock configuration LSBs for page 29 (rows 0x740 through 0x77f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+    #[inline(always)]
+    pub const fn page29_lock0(self) -> crate::common::Reg<regs::Page29lock0, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(16104usize) as _) }
+    }
+    #[doc = "Lock configuration MSBs for page 29 (rows 0x740 through 0x77f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+    #[inline(always)]
+    pub const fn page29_lock1(self) -> crate::common::Reg<regs::Page29lock1, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(16108usize) as _) }
+    }
+    #[doc = "Lock configuration LSBs for page 30 (rows 0x780 through 0x7bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+    #[inline(always)]
+    pub const fn page30_lock0(self) -> crate::common::Reg<regs::Page30lock0, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(16112usize) as _) }
+    }
+    #[doc = "Lock configuration MSBs for page 30 (rows 0x780 through 0x7bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+    #[inline(always)]
+    pub const fn page30_lock1(self) -> crate::common::Reg<regs::Page30lock1, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(16116usize) as _) }
+    }
+    #[doc = "Lock configuration LSBs for page 31 (rows 0x7c0 through 0x7ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+    #[inline(always)]
+    pub const fn page31_lock0(self) -> crate::common::Reg<regs::Page31lock0, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(16120usize) as _) }
+    }
+    #[doc = "Lock configuration MSBs for page 31 (rows 0x7c0 through 0x7ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+    #[inline(always)]
+    pub const fn page31_lock1(self) -> crate::common::Reg<regs::Page31lock1, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(16124usize) as _) }
+    }
+    #[doc = "Lock configuration LSBs for page 32 (rows 0x800 through 0x83f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+    #[inline(always)]
+    pub const fn page32_lock0(self) -> crate::common::Reg<regs::Page32lock0, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(16128usize) as _) }
+    }
+    #[doc = "Lock configuration MSBs for page 32 (rows 0x800 through 0x83f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+    #[inline(always)]
+    pub const fn page32_lock1(self) -> crate::common::Reg<regs::Page32lock1, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(16132usize) as _) }
+    }
+    #[doc = "Lock configuration LSBs for page 33 (rows 0x840 through 0x87f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+    #[inline(always)]
+    pub const fn page33_lock0(self) -> crate::common::Reg<regs::Page33lock0, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(16136usize) as _) }
+    }
+    #[doc = "Lock configuration MSBs for page 33 (rows 0x840 through 0x87f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+    #[inline(always)]
+    pub const fn page33_lock1(self) -> crate::common::Reg<regs::Page33lock1, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(16140usize) as _) }
+    }
+    #[doc = "Lock configuration LSBs for page 34 (rows 0x880 through 0x8bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+    #[inline(always)]
+    pub const fn page34_lock0(self) -> crate::common::Reg<regs::Page34lock0, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(16144usize) as _) }
+    }
+    #[doc = "Lock configuration MSBs for page 34 (rows 0x880 through 0x8bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+    #[inline(always)]
+    pub const fn page34_lock1(self) -> crate::common::Reg<regs::Page34lock1, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(16148usize) as _) }
+    }
+    #[doc = "Lock configuration LSBs for page 35 (rows 0x8c0 through 0x8ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+    #[inline(always)]
+    pub const fn page35_lock0(self) -> crate::common::Reg<regs::Page35lock0, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(16152usize) as _) }
+    }
+    #[doc = "Lock configuration MSBs for page 35 (rows 0x8c0 through 0x8ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+    #[inline(always)]
+    pub const fn page35_lock1(self) -> crate::common::Reg<regs::Page35lock1, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(16156usize) as _) }
+    }
+    #[doc = "Lock configuration LSBs for page 36 (rows 0x900 through 0x93f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+    #[inline(always)]
+    pub const fn page36_lock0(self) -> crate::common::Reg<regs::Page36lock0, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(16160usize) as _) }
+    }
+    #[doc = "Lock configuration MSBs for page 36 (rows 0x900 through 0x93f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+    #[inline(always)]
+    pub const fn page36_lock1(self) -> crate::common::Reg<regs::Page36lock1, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(16164usize) as _) }
+    }
+    #[doc = "Lock configuration LSBs for page 37 (rows 0x940 through 0x97f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+    #[inline(always)]
+    pub const fn page37_lock0(self) -> crate::common::Reg<regs::Page37lock0, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(16168usize) as _) }
+    }
+    #[doc = "Lock configuration MSBs for page 37 (rows 0x940 through 0x97f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+    #[inline(always)]
+    pub const fn page37_lock1(self) -> crate::common::Reg<regs::Page37lock1, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(16172usize) as _) }
+    }
+    #[doc = "Lock configuration LSBs for page 38 (rows 0x980 through 0x9bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+    #[inline(always)]
+    pub const fn page38_lock0(self) -> crate::common::Reg<regs::Page38lock0, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(16176usize) as _) }
+    }
+    #[doc = "Lock configuration MSBs for page 38 (rows 0x980 through 0x9bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+    #[inline(always)]
+    pub const fn page38_lock1(self) -> crate::common::Reg<regs::Page38lock1, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(16180usize) as _) }
+    }
+    #[doc = "Lock configuration LSBs for page 39 (rows 0x9c0 through 0x9ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+    #[inline(always)]
+    pub const fn page39_lock0(self) -> crate::common::Reg<regs::Page39lock0, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(16184usize) as _) }
+    }
+    #[doc = "Lock configuration MSBs for page 39 (rows 0x9c0 through 0x9ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+    #[inline(always)]
+    pub const fn page39_lock1(self) -> crate::common::Reg<regs::Page39lock1, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(16188usize) as _) }
+    }
+    #[doc = "Lock configuration LSBs for page 40 (rows 0xa00 through 0xa3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+    #[inline(always)]
+    pub const fn page40_lock0(self) -> crate::common::Reg<regs::Page40lock0, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(16192usize) as _) }
+    }
+    #[doc = "Lock configuration MSBs for page 40 (rows 0xa00 through 0xa3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+    #[inline(always)]
+    pub const fn page40_lock1(self) -> crate::common::Reg<regs::Page40lock1, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(16196usize) as _) }
+    }
+    #[doc = "Lock configuration LSBs for page 41 (rows 0xa40 through 0xa7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+    #[inline(always)]
+    pub const fn page41_lock0(self) -> crate::common::Reg<regs::Page41lock0, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(16200usize) as _) }
+    }
+    #[doc = "Lock configuration MSBs for page 41 (rows 0xa40 through 0xa7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+    #[inline(always)]
+    pub const fn page41_lock1(self) -> crate::common::Reg<regs::Page41lock1, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(16204usize) as _) }
+    }
+    #[doc = "Lock configuration LSBs for page 42 (rows 0xa80 through 0xabf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+    #[inline(always)]
+    pub const fn page42_lock0(self) -> crate::common::Reg<regs::Page42lock0, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(16208usize) as _) }
+    }
+    #[doc = "Lock configuration MSBs for page 42 (rows 0xa80 through 0xabf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+    #[inline(always)]
+    pub const fn page42_lock1(self) -> crate::common::Reg<regs::Page42lock1, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(16212usize) as _) }
+    }
+    #[doc = "Lock configuration LSBs for page 43 (rows 0xac0 through 0xaff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+    #[inline(always)]
+    pub const fn page43_lock0(self) -> crate::common::Reg<regs::Page43lock0, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(16216usize) as _) }
+    }
+    #[doc = "Lock configuration MSBs for page 43 (rows 0xac0 through 0xaff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+    #[inline(always)]
+    pub const fn page43_lock1(self) -> crate::common::Reg<regs::Page43lock1, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(16220usize) as _) }
+    }
+    #[doc = "Lock configuration LSBs for page 44 (rows 0xb00 through 0xb3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+    #[inline(always)]
+    pub const fn page44_lock0(self) -> crate::common::Reg<regs::Page44lock0, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(16224usize) as _) }
+    }
+    #[doc = "Lock configuration MSBs for page 44 (rows 0xb00 through 0xb3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+    #[inline(always)]
+    pub const fn page44_lock1(self) -> crate::common::Reg<regs::Page44lock1, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(16228usize) as _) }
+    }
+    #[doc = "Lock configuration LSBs for page 45 (rows 0xb40 through 0xb7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+    #[inline(always)]
+    pub const fn page45_lock0(self) -> crate::common::Reg<regs::Page45lock0, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(16232usize) as _) }
+    }
+    #[doc = "Lock configuration MSBs for page 45 (rows 0xb40 through 0xb7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+    #[inline(always)]
+    pub const fn page45_lock1(self) -> crate::common::Reg<regs::Page45lock1, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(16236usize) as _) }
+    }
+    #[doc = "Lock configuration LSBs for page 46 (rows 0xb80 through 0xbbf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+    #[inline(always)]
+    pub const fn page46_lock0(self) -> crate::common::Reg<regs::Page46lock0, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(16240usize) as _) }
+    }
+    #[doc = "Lock configuration MSBs for page 46 (rows 0xb80 through 0xbbf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+    #[inline(always)]
+    pub const fn page46_lock1(self) -> crate::common::Reg<regs::Page46lock1, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(16244usize) as _) }
+    }
+    #[doc = "Lock configuration LSBs for page 47 (rows 0xbc0 through 0xbff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+    #[inline(always)]
+    pub const fn page47_lock0(self) -> crate::common::Reg<regs::Page47lock0, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(16248usize) as _) }
+    }
+    #[doc = "Lock configuration MSBs for page 47 (rows 0xbc0 through 0xbff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+    #[inline(always)]
+    pub const fn page47_lock1(self) -> crate::common::Reg<regs::Page47lock1, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(16252usize) as _) }
+    }
+    #[doc = "Lock configuration LSBs for page 48 (rows 0xc00 through 0xc3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+    #[inline(always)]
+    pub const fn page48_lock0(self) -> crate::common::Reg<regs::Page48lock0, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(16256usize) as _) }
+    }
+    #[doc = "Lock configuration MSBs for page 48 (rows 0xc00 through 0xc3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+    #[inline(always)]
+    pub const fn page48_lock1(self) -> crate::common::Reg<regs::Page48lock1, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(16260usize) as _) }
+    }
+    #[doc = "Lock configuration LSBs for page 49 (rows 0xc40 through 0xc7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+    #[inline(always)]
+    pub const fn page49_lock0(self) -> crate::common::Reg<regs::Page49lock0, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(16264usize) as _) }
+    }
+    #[doc = "Lock configuration MSBs for page 49 (rows 0xc40 through 0xc7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+    #[inline(always)]
+    pub const fn page49_lock1(self) -> crate::common::Reg<regs::Page49lock1, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(16268usize) as _) }
+    }
+    #[doc = "Lock configuration LSBs for page 50 (rows 0xc80 through 0xcbf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+    #[inline(always)]
+    pub const fn page50_lock0(self) -> crate::common::Reg<regs::Page50lock0, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(16272usize) as _) }
+    }
+    #[doc = "Lock configuration MSBs for page 50 (rows 0xc80 through 0xcbf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+    #[inline(always)]
+    pub const fn page50_lock1(self) -> crate::common::Reg<regs::Page50lock1, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(16276usize) as _) }
+    }
+    #[doc = "Lock configuration LSBs for page 51 (rows 0xcc0 through 0xcff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+    #[inline(always)]
+    pub const fn page51_lock0(self) -> crate::common::Reg<regs::Page51lock0, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(16280usize) as _) }
+    }
+    #[doc = "Lock configuration MSBs for page 51 (rows 0xcc0 through 0xcff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+    #[inline(always)]
+    pub const fn page51_lock1(self) -> crate::common::Reg<regs::Page51lock1, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(16284usize) as _) }
+    }
+    #[doc = "Lock configuration LSBs for page 52 (rows 0xd00 through 0xd3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+    #[inline(always)]
+    pub const fn page52_lock0(self) -> crate::common::Reg<regs::Page52lock0, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(16288usize) as _) }
+    }
+    #[doc = "Lock configuration MSBs for page 52 (rows 0xd00 through 0xd3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+    #[inline(always)]
+    pub const fn page52_lock1(self) -> crate::common::Reg<regs::Page52lock1, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(16292usize) as _) }
+    }
+    #[doc = "Lock configuration LSBs for page 53 (rows 0xd40 through 0xd7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+    #[inline(always)]
+    pub const fn page53_lock0(self) -> crate::common::Reg<regs::Page53lock0, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(16296usize) as _) }
+    }
+    #[doc = "Lock configuration MSBs for page 53 (rows 0xd40 through 0xd7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+    #[inline(always)]
+    pub const fn page53_lock1(self) -> crate::common::Reg<regs::Page53lock1, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(16300usize) as _) }
+    }
+    #[doc = "Lock configuration LSBs for page 54 (rows 0xd80 through 0xdbf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+    #[inline(always)]
+    pub const fn page54_lock0(self) -> crate::common::Reg<regs::Page54lock0, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(16304usize) as _) }
+    }
+    #[doc = "Lock configuration MSBs for page 54 (rows 0xd80 through 0xdbf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+    #[inline(always)]
+    pub const fn page54_lock1(self) -> crate::common::Reg<regs::Page54lock1, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(16308usize) as _) }
+    }
+    #[doc = "Lock configuration LSBs for page 55 (rows 0xdc0 through 0xdff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+    #[inline(always)]
+    pub const fn page55_lock0(self) -> crate::common::Reg<regs::Page55lock0, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(16312usize) as _) }
+    }
+    #[doc = "Lock configuration MSBs for page 55 (rows 0xdc0 through 0xdff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+    #[inline(always)]
+    pub const fn page55_lock1(self) -> crate::common::Reg<regs::Page55lock1, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(16316usize) as _) }
+    }
+    #[doc = "Lock configuration LSBs for page 56 (rows 0xe00 through 0xe3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+    #[inline(always)]
+    pub const fn page56_lock0(self) -> crate::common::Reg<regs::Page56lock0, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(16320usize) as _) }
+    }
+    #[doc = "Lock configuration MSBs for page 56 (rows 0xe00 through 0xe3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+    #[inline(always)]
+    pub const fn page56_lock1(self) -> crate::common::Reg<regs::Page56lock1, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(16324usize) as _) }
+    }
+    #[doc = "Lock configuration LSBs for page 57 (rows 0xe40 through 0xe7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+    #[inline(always)]
+    pub const fn page57_lock0(self) -> crate::common::Reg<regs::Page57lock0, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(16328usize) as _) }
+    }
+    #[doc = "Lock configuration MSBs for page 57 (rows 0xe40 through 0xe7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+    #[inline(always)]
+    pub const fn page57_lock1(self) -> crate::common::Reg<regs::Page57lock1, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(16332usize) as _) }
+    }
+    #[doc = "Lock configuration LSBs for page 58 (rows 0xe80 through 0xebf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+    #[inline(always)]
+    pub const fn page58_lock0(self) -> crate::common::Reg<regs::Page58lock0, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(16336usize) as _) }
+    }
+    #[doc = "Lock configuration MSBs for page 58 (rows 0xe80 through 0xebf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+    #[inline(always)]
+    pub const fn page58_lock1(self) -> crate::common::Reg<regs::Page58lock1, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(16340usize) as _) }
+    }
+    #[doc = "Lock configuration LSBs for page 59 (rows 0xec0 through 0xeff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+    #[inline(always)]
+    pub const fn page59_lock0(self) -> crate::common::Reg<regs::Page59lock0, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(16344usize) as _) }
+    }
+    #[doc = "Lock configuration MSBs for page 59 (rows 0xec0 through 0xeff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+    #[inline(always)]
+    pub const fn page59_lock1(self) -> crate::common::Reg<regs::Page59lock1, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(16348usize) as _) }
+    }
+    #[doc = "Lock configuration LSBs for page 60 (rows 0xf00 through 0xf3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+    #[inline(always)]
+    pub const fn page60_lock0(self) -> crate::common::Reg<regs::Page60lock0, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(16352usize) as _) }
+    }
+    #[doc = "Lock configuration MSBs for page 60 (rows 0xf00 through 0xf3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+    #[inline(always)]
+    pub const fn page60_lock1(self) -> crate::common::Reg<regs::Page60lock1, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(16356usize) as _) }
+    }
+    #[doc = "Lock configuration LSBs for page 61 (rows 0xf40 through 0xf7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+    #[inline(always)]
+    pub const fn page61_lock0(self) -> crate::common::Reg<regs::Page61lock0, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(16360usize) as _) }
+    }
+    #[doc = "Lock configuration MSBs for page 61 (rows 0xf40 through 0xf7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+    #[inline(always)]
+    pub const fn page61_lock1(self) -> crate::common::Reg<regs::Page61lock1, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(16364usize) as _) }
+    }
+    #[doc = "Lock configuration LSBs for page 62 (rows 0xf80 through 0xfbf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+    #[inline(always)]
+    pub const fn page62_lock0(self) -> crate::common::Reg<regs::Page62lock0, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(16368usize) as _) }
+    }
+    #[doc = "Lock configuration MSBs for page 62 (rows 0xf80 through 0xfbf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+    #[inline(always)]
+    pub const fn page62_lock1(self) -> crate::common::Reg<regs::Page62lock1, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(16372usize) as _) }
+    }
+    #[doc = "Lock configuration LSBs for page 63 (rows 0xfc0 through 0xfff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+    #[inline(always)]
+    pub const fn page63_lock0(self) -> crate::common::Reg<regs::Page63lock0, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(16376usize) as _) }
+    }
+    #[doc = "Lock configuration MSBs for page 63 (rows 0xfc0 through 0xfff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+    #[inline(always)]
+    pub const fn page63_lock1(self) -> crate::common::Reg<regs::Page63lock1, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(16380usize) as _) }
+    }
+}
+pub mod regs;
+pub mod vals;
diff --git a/src/rp2350/otp_data_raw/regs.rs b/src/rp2350/otp_data_raw/regs.rs
new file mode 100644
index 00000000..43a2f9fe
--- /dev/null
+++ b/src/rp2350/otp_data_raw/regs.rs
@@ -0,0 +1,13023 @@
+#[doc = "Disable/Enable boot paths/features in the RP2350 mask ROM. Disables always supersede enables. Enables are provided where there are other configurations in OTP that must be valid. (RBIT-3)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct BootFlags0(pub u32);
+impl BootFlags0 {
+    #[inline(always)]
+    pub const fn disable_bootsel_exec2(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_disable_bootsel_exec2(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[doc = "Enable bootloader activity LED. If set, bootsel_led_cfg is assumed to be valid"]
+    #[inline(always)]
+    pub const fn enable_bootsel_led(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Enable bootloader activity LED. If set, bootsel_led_cfg is assumed to be valid"]
+    #[inline(always)]
+    pub fn set_enable_bootsel_led(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+    #[doc = "Enable loading of the non-default XOSC and PLL configuration before entering BOOTSEL mode. Ensure that BOOTSEL_XOSC_CFG and BOOTSEL_PLL_CFG are correctly programmed before setting this bit. If this bit is set, user software may use the contents of BOOTSEL_PLL_CFG to calculated the expected XOSC frequency based on the fixed USB boot frequency of 48 MHz."]
+    #[inline(always)]
+    pub const fn enable_bootsel_non_default_pll_xosc_cfg(&self) -> bool {
+        let val = (self.0 >> 2usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Enable loading of the non-default XOSC and PLL configuration before entering BOOTSEL mode. Ensure that BOOTSEL_XOSC_CFG and BOOTSEL_PLL_CFG are correctly programmed before setting this bit. If this bit is set, user software may use the contents of BOOTSEL_PLL_CFG to calculated the expected XOSC frequency based on the fixed USB boot frequency of 48 MHz."]
+    #[inline(always)]
+    pub fn set_enable_bootsel_non_default_pll_xosc_cfg(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+    }
+    #[doc = "If 1, configure the QSPI pads for 1.8 V operation when accessing flash for the first time from the bootrom, using the VOLTAGE_SELECT register for the QSPI pads bank. This slightly improves the input timing of the pads at low voltages, but does not affect their output characteristics. If 0, leave VOLTAGE_SELECT in its reset state (suitable for operation at and above 2.5 V)"]
+    #[inline(always)]
+    pub const fn flash_io_voltage_1v8(&self) -> bool {
+        let val = (self.0 >> 3usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, configure the QSPI pads for 1.8 V operation when accessing flash for the first time from the bootrom, using the VOLTAGE_SELECT register for the QSPI pads bank. This slightly improves the input timing of the pads at low voltages, but does not affect their output characteristics. If 0, leave VOLTAGE_SELECT in its reset state (suitable for operation at and above 2.5 V)"]
+    #[inline(always)]
+    pub fn set_flash_io_voltage_1v8(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
+    }
+    #[doc = "Enable quartering of ROSC divisor during signature check, to reduce secure boot time"]
+    #[inline(always)]
+    pub const fn fast_sigcheck_rosc_div(&self) -> bool {
+        let val = (self.0 >> 4usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Enable quartering of ROSC divisor during signature check, to reduce secure boot time"]
+    #[inline(always)]
+    pub fn set_fast_sigcheck_rosc_div(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
+    }
+    #[doc = "Mark FLASH_DEVINFO as containing valid, ECC'd data which describes external flash devices."]
+    #[inline(always)]
+    pub const fn flash_devinfo_enable(&self) -> bool {
+        let val = (self.0 >> 5usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Mark FLASH_DEVINFO as containing valid, ECC'd data which describes external flash devices."]
+    #[inline(always)]
+    pub fn set_flash_devinfo_enable(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
+    }
+    #[doc = "Override the limit for default flash metadata scanning. The value is specified in FLASH_PARTITION_SLOT_SIZE. Make sure FLASH_PARTITION_SLOT_SIZE is valid before setting this bit"]
+    #[inline(always)]
+    pub const fn override_flash_partition_slot_size(&self) -> bool {
+        let val = (self.0 >> 6usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Override the limit for default flash metadata scanning. The value is specified in FLASH_PARTITION_SLOT_SIZE. Make sure FLASH_PARTITION_SLOT_SIZE is valid before setting this bit"]
+    #[inline(always)]
+    pub fn set_override_flash_partition_slot_size(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
+    }
+    #[doc = "Restrict flash boot path to use of a single binary at the start of flash"]
+    #[inline(always)]
+    pub const fn single_flash_binary(&self) -> bool {
+        let val = (self.0 >> 7usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Restrict flash boot path to use of a single binary at the start of flash"]
+    #[inline(always)]
+    pub fn set_single_flash_binary(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
+    }
+    #[doc = "Disable auto-switch of CPU architecture on boot when the (only) binary to be booted is for the other Arm/RISC-V architecture and both architectures are enabled"]
+    #[inline(always)]
+    pub const fn disable_auto_switch_arch(&self) -> bool {
+        let val = (self.0 >> 8usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Disable auto-switch of CPU architecture on boot when the (only) binary to be booted is for the other Arm/RISC-V architecture and both architectures are enabled"]
+    #[inline(always)]
+    pub fn set_disable_auto_switch_arch(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
+    }
+    #[doc = "Require a partition table to be signed"]
+    #[inline(always)]
+    pub const fn secure_partition_table(&self) -> bool {
+        let val = (self.0 >> 9usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Require a partition table to be signed"]
+    #[inline(always)]
+    pub fn set_secure_partition_table(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
+    }
+    #[doc = "Require a partition table to be hashed (if not signed)"]
+    #[inline(always)]
+    pub const fn hashed_partition_table(&self) -> bool {
+        let val = (self.0 >> 10usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Require a partition table to be hashed (if not signed)"]
+    #[inline(always)]
+    pub fn set_hashed_partition_table(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize);
+    }
+    #[doc = "Require binaries to have a rollback version. Set automatically the first time a binary with a rollback version is booted."]
+    #[inline(always)]
+    pub const fn rollback_required(&self) -> bool {
+        let val = (self.0 >> 11usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Require binaries to have a rollback version. Set automatically the first time a binary with a rollback version is booted."]
+    #[inline(always)]
+    pub fn set_rollback_required(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
+    }
+    #[inline(always)]
+    pub const fn disable_flash_boot(&self) -> bool {
+        let val = (self.0 >> 12usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_disable_flash_boot(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
+    }
+    #[doc = "Takes precedence over ENABLE_OTP_BOOT."]
+    #[inline(always)]
+    pub const fn disable_otp_boot(&self) -> bool {
+        let val = (self.0 >> 13usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Takes precedence over ENABLE_OTP_BOOT."]
+    #[inline(always)]
+    pub fn set_disable_otp_boot(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize);
+    }
+    #[doc = "Enable OTP boot. A number of OTP rows specified by OTPBOOT_LEN will be loaded, starting from OTPBOOT_SRC, into the SRAM location specified by OTPBOOT_DST1 and OTPBOOT_DST0. The loaded program image is stored with ECC, 16 bits per row, and must contain a valid IMAGE_DEF. Do not set this bit without first programming an image into OTP and configuring OTPBOOT_LEN, OTPBOOT_SRC, OTPBOOT_DST0 and OTPBOOT_DST1. Note that OTPBOOT_LEN and OTPBOOT_SRC must be even numbers of OTP rows. Equivalently, the image must be a multiple of 32 bits in size, and must start at a 32-bit-aligned address in the ECC read data address window."]
+    #[inline(always)]
+    pub const fn enable_otp_boot(&self) -> bool {
+        let val = (self.0 >> 14usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Enable OTP boot. A number of OTP rows specified by OTPBOOT_LEN will be loaded, starting from OTPBOOT_SRC, into the SRAM location specified by OTPBOOT_DST1 and OTPBOOT_DST0. The loaded program image is stored with ECC, 16 bits per row, and must contain a valid IMAGE_DEF. Do not set this bit without first programming an image into OTP and configuring OTPBOOT_LEN, OTPBOOT_SRC, OTPBOOT_DST0 and OTPBOOT_DST1. Note that OTPBOOT_LEN and OTPBOOT_SRC must be even numbers of OTP rows. Equivalently, the image must be a multiple of 32 bits in size, and must start at a 32-bit-aligned address in the ECC read data address window."]
+    #[inline(always)]
+    pub fn set_enable_otp_boot(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize);
+    }
+    #[inline(always)]
+    pub const fn disable_power_scratch(&self) -> bool {
+        let val = (self.0 >> 15usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_disable_power_scratch(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize);
+    }
+    #[inline(always)]
+    pub const fn disable_watchdog_scratch(&self) -> bool {
+        let val = (self.0 >> 16usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_disable_watchdog_scratch(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
+    }
+    #[inline(always)]
+    pub const fn disable_bootsel_usb_msd_ifc(&self) -> bool {
+        let val = (self.0 >> 17usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_disable_bootsel_usb_msd_ifc(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
+    }
+    #[inline(always)]
+    pub const fn disable_bootsel_usb_picoboot_ifc(&self) -> bool {
+        let val = (self.0 >> 18usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_disable_bootsel_usb_picoboot_ifc(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize);
+    }
+    #[inline(always)]
+    pub const fn disable_bootsel_uart_boot(&self) -> bool {
+        let val = (self.0 >> 19usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_disable_bootsel_uart_boot(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize);
+    }
+    #[doc = "Disable all access to XIP after entering an SRAM binary. Note that this will cause bootrom APIs that access XIP to fail, including APIs that interact with the partition table."]
+    #[inline(always)]
+    pub const fn disable_xip_access_on_sram_entry(&self) -> bool {
+        let val = (self.0 >> 20usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Disable all access to XIP after entering an SRAM binary. Note that this will cause bootrom APIs that access XIP to fail, including APIs that interact with the partition table."]
+    #[inline(always)]
+    pub fn set_disable_xip_access_on_sram_entry(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize);
+    }
+    #[inline(always)]
+    pub const fn disable_sram_window_boot(&self) -> bool {
+        let val = (self.0 >> 21usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_disable_sram_window_boot(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 21usize)) | (((val as u32) & 0x01) << 21usize);
+    }
+}
+impl Default for BootFlags0 {
+    #[inline(always)]
+    fn default() -> BootFlags0 {
+        BootFlags0(0)
+    }
+}
+#[doc = "Redundant copy of BOOT_FLAGS0"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct BootFlags0r1(pub u32);
+impl BootFlags0r1 {
+    #[inline(always)]
+    pub const fn boot_flags0_r1(&self) -> u32 {
+        let val = (self.0 >> 0usize) & 0x00ff_ffff;
+        val as u32
+    }
+    #[inline(always)]
+    pub fn set_boot_flags0_r1(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize);
+    }
+}
+impl Default for BootFlags0r1 {
+    #[inline(always)]
+    fn default() -> BootFlags0r1 {
+        BootFlags0r1(0)
+    }
+}
+#[doc = "Redundant copy of BOOT_FLAGS0"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct BootFlags0r2(pub u32);
+impl BootFlags0r2 {
+    #[inline(always)]
+    pub const fn boot_flags0_r2(&self) -> u32 {
+        let val = (self.0 >> 0usize) & 0x00ff_ffff;
+        val as u32
+    }
+    #[inline(always)]
+    pub fn set_boot_flags0_r2(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize);
+    }
+}
+impl Default for BootFlags0r2 {
+    #[inline(always)]
+    fn default() -> BootFlags0r2 {
+        BootFlags0r2(0)
+    }
+}
+#[doc = "Disable/Enable boot paths/features in the RP2350 mask ROM. Disables always supersede enables. Enables are provided where there are other configurations in OTP that must be valid. (RBIT-3)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct BootFlags1(pub u32);
+impl BootFlags1 {
+    #[doc = "Mark each of the possible boot keys as valid. The bootrom will check signatures against all valid boot keys, and ignore invalid boot keys. Each bit in this field corresponds to one of the four 256-bit boot key hashes that may be stored in page 2 of the OTP. A KEY_VALID bit is ignored if the corresponding KEY_INVALID bit is set. Boot keys are considered valid only when KEY_VALID is set and KEY_INVALID is clear. Do not mark a boot key as KEY_VALID if it does not contain a valid SHA-256 hash of your secp256k1 public key. Verify keys after programming, before setting the KEY_VALID bits -- a boot key with uncorrectable ECC faults will render your device unbootable if secure boot is enabled. Do not enable secure boot without first installing a valid key. This will render your device unbootable."]
+    #[inline(always)]
+    pub const fn key_valid(&self) -> u8 {
+        let val = (self.0 >> 0usize) & 0x0f;
+        val as u8
+    }
+    #[doc = "Mark each of the possible boot keys as valid. The bootrom will check signatures against all valid boot keys, and ignore invalid boot keys. Each bit in this field corresponds to one of the four 256-bit boot key hashes that may be stored in page 2 of the OTP. A KEY_VALID bit is ignored if the corresponding KEY_INVALID bit is set. Boot keys are considered valid only when KEY_VALID is set and KEY_INVALID is clear. Do not mark a boot key as KEY_VALID if it does not contain a valid SHA-256 hash of your secp256k1 public key. Verify keys after programming, before setting the KEY_VALID bits -- a boot key with uncorrectable ECC faults will render your device unbootable if secure boot is enabled. Do not enable secure boot without first installing a valid key. This will render your device unbootable."]
+    #[inline(always)]
+    pub fn set_key_valid(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize);
+    }
+    #[doc = "Mark a boot key as invalid, or prevent it from ever becoming valid. The bootrom will ignore any boot key marked as invalid during secure boot signature checks. Each bit in this field corresponds to one of the four 256-bit boot key hashes that may be stored in page 2 of the OTP. When provisioning boot keys, it's recommended to mark any boot key slots you don't intend to use as KEY_INVALID, so that spurious keys can not be installed at a later time."]
+    #[inline(always)]
+    pub const fn key_invalid(&self) -> u8 {
+        let val = (self.0 >> 8usize) & 0x0f;
+        val as u8
+    }
+    #[doc = "Mark a boot key as invalid, or prevent it from ever becoming valid. The bootrom will ignore any boot key marked as invalid during secure boot signature checks. Each bit in this field corresponds to one of the four 256-bit boot key hashes that may be stored in page 2 of the OTP. When provisioning boot keys, it's recommended to mark any boot key slots you don't intend to use as KEY_INVALID, so that spurious keys can not be installed at a later time."]
+    #[inline(always)]
+    pub fn set_key_invalid(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x0f << 8usize)) | (((val as u32) & 0x0f) << 8usize);
+    }
+    #[doc = "Adjust how long to wait for a second reset when double tap BOOTSEL mode is enabled via DOUBLE_TAP. The minimum is 50 milliseconds, and each unit of this field adds an additional 50 milliseconds. For example, settings this field to its maximum value of 7 will cause the chip to wait for 400 milliseconds at boot to check for a second reset which requests entry to BOOTSEL mode. 200 milliseconds (DOUBLE_TAP_DELAY=3) is a good intermediate value."]
+    #[inline(always)]
+    pub const fn double_tap_delay(&self) -> u8 {
+        let val = (self.0 >> 16usize) & 0x07;
+        val as u8
+    }
+    #[doc = "Adjust how long to wait for a second reset when double tap BOOTSEL mode is enabled via DOUBLE_TAP. The minimum is 50 milliseconds, and each unit of this field adds an additional 50 milliseconds. For example, settings this field to its maximum value of 7 will cause the chip to wait for 400 milliseconds at boot to check for a second reset which requests entry to BOOTSEL mode. 200 milliseconds (DOUBLE_TAP_DELAY=3) is a good intermediate value."]
+    #[inline(always)]
+    pub fn set_double_tap_delay(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x07 << 16usize)) | (((val as u32) & 0x07) << 16usize);
+    }
+    #[doc = "Enable entering BOOTSEL mode via double-tap of the RUN/RSTn pin. Adds a significant delay to boot time, as configured by DOUBLE_TAP_DELAY. This functions by waiting at startup (i.e. following a reset) to see if a second reset is applied soon afterward. The second reset is detected by the bootrom with help of the POWMAN_CHIP_RESET_DOUBLE_TAP flag, which is not reset by the external reset pin, and the bootrom enters BOOTSEL mode (NSBOOT) to await further instruction over USB or UART."]
+    #[inline(always)]
+    pub const fn double_tap(&self) -> bool {
+        let val = (self.0 >> 19usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Enable entering BOOTSEL mode via double-tap of the RUN/RSTn pin. Adds a significant delay to boot time, as configured by DOUBLE_TAP_DELAY. This functions by waiting at startup (i.e. following a reset) to see if a second reset is applied soon afterward. The second reset is detected by the bootrom with help of the POWMAN_CHIP_RESET_DOUBLE_TAP flag, which is not reset by the external reset pin, and the bootrom enters BOOTSEL mode (NSBOOT) to await further instruction over USB or UART."]
+    #[inline(always)]
+    pub fn set_double_tap(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize);
+    }
+}
+impl Default for BootFlags1 {
+    #[inline(always)]
+    fn default() -> BootFlags1 {
+        BootFlags1(0)
+    }
+}
+#[doc = "Redundant copy of BOOT_FLAGS1"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct BootFlags1r1(pub u32);
+impl BootFlags1r1 {
+    #[inline(always)]
+    pub const fn boot_flags1_r1(&self) -> u32 {
+        let val = (self.0 >> 0usize) & 0x00ff_ffff;
+        val as u32
+    }
+    #[inline(always)]
+    pub fn set_boot_flags1_r1(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize);
+    }
+}
+impl Default for BootFlags1r1 {
+    #[inline(always)]
+    fn default() -> BootFlags1r1 {
+        BootFlags1r1(0)
+    }
+}
+#[doc = "Redundant copy of BOOT_FLAGS1"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct BootFlags1r2(pub u32);
+impl BootFlags1r2 {
+    #[inline(always)]
+    pub const fn boot_flags1_r2(&self) -> u32 {
+        let val = (self.0 >> 0usize) & 0x00ff_ffff;
+        val as u32
+    }
+    #[inline(always)]
+    pub fn set_boot_flags1_r2(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize);
+    }
+}
+impl Default for BootFlags1r2 {
+    #[inline(always)]
+    fn default() -> BootFlags1r2 {
+        BootFlags1r2(0)
+    }
+}
+#[doc = "Bits 15:0 of SHA-256 hash of boot key 0 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Bootkey00(pub u32);
+impl Bootkey00 {
+    #[inline(always)]
+    pub const fn bootkey0_0(&self) -> u32 {
+        let val = (self.0 >> 0usize) & 0x00ff_ffff;
+        val as u32
+    }
+    #[inline(always)]
+    pub fn set_bootkey0_0(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize);
+    }
+}
+impl Default for Bootkey00 {
+    #[inline(always)]
+    fn default() -> Bootkey00 {
+        Bootkey00(0)
+    }
+}
+#[doc = "Bits 31:16 of SHA-256 hash of boot key 0 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Bootkey01(pub u32);
+impl Bootkey01 {
+    #[inline(always)]
+    pub const fn bootkey0_1(&self) -> u32 {
+        let val = (self.0 >> 0usize) & 0x00ff_ffff;
+        val as u32
+    }
+    #[inline(always)]
+    pub fn set_bootkey0_1(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize);
+    }
+}
+impl Default for Bootkey01 {
+    #[inline(always)]
+    fn default() -> Bootkey01 {
+        Bootkey01(0)
+    }
+}
+#[doc = "Bits 175:160 of SHA-256 hash of boot key 0 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Bootkey010(pub u32);
+impl Bootkey010 {
+    #[inline(always)]
+    pub const fn bootkey0_10(&self) -> u32 {
+        let val = (self.0 >> 0usize) & 0x00ff_ffff;
+        val as u32
+    }
+    #[inline(always)]
+    pub fn set_bootkey0_10(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize);
+    }
+}
+impl Default for Bootkey010 {
+    #[inline(always)]
+    fn default() -> Bootkey010 {
+        Bootkey010(0)
+    }
+}
+#[doc = "Bits 191:176 of SHA-256 hash of boot key 0 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Bootkey011(pub u32);
+impl Bootkey011 {
+    #[inline(always)]
+    pub const fn bootkey0_11(&self) -> u32 {
+        let val = (self.0 >> 0usize) & 0x00ff_ffff;
+        val as u32
+    }
+    #[inline(always)]
+    pub fn set_bootkey0_11(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize);
+    }
+}
+impl Default for Bootkey011 {
+    #[inline(always)]
+    fn default() -> Bootkey011 {
+        Bootkey011(0)
+    }
+}
+#[doc = "Bits 207:192 of SHA-256 hash of boot key 0 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Bootkey012(pub u32);
+impl Bootkey012 {
+    #[inline(always)]
+    pub const fn bootkey0_12(&self) -> u32 {
+        let val = (self.0 >> 0usize) & 0x00ff_ffff;
+        val as u32
+    }
+    #[inline(always)]
+    pub fn set_bootkey0_12(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize);
+    }
+}
+impl Default for Bootkey012 {
+    #[inline(always)]
+    fn default() -> Bootkey012 {
+        Bootkey012(0)
+    }
+}
+#[doc = "Bits 223:208 of SHA-256 hash of boot key 0 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Bootkey013(pub u32);
+impl Bootkey013 {
+    #[inline(always)]
+    pub const fn bootkey0_13(&self) -> u32 {
+        let val = (self.0 >> 0usize) & 0x00ff_ffff;
+        val as u32
+    }
+    #[inline(always)]
+    pub fn set_bootkey0_13(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize);
+    }
+}
+impl Default for Bootkey013 {
+    #[inline(always)]
+    fn default() -> Bootkey013 {
+        Bootkey013(0)
+    }
+}
+#[doc = "Bits 239:224 of SHA-256 hash of boot key 0 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Bootkey014(pub u32);
+impl Bootkey014 {
+    #[inline(always)]
+    pub const fn bootkey0_14(&self) -> u32 {
+        let val = (self.0 >> 0usize) & 0x00ff_ffff;
+        val as u32
+    }
+    #[inline(always)]
+    pub fn set_bootkey0_14(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize);
+    }
+}
+impl Default for Bootkey014 {
+    #[inline(always)]
+    fn default() -> Bootkey014 {
+        Bootkey014(0)
+    }
+}
+#[doc = "Bits 255:240 of SHA-256 hash of boot key 0 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Bootkey015(pub u32);
+impl Bootkey015 {
+    #[inline(always)]
+    pub const fn bootkey0_15(&self) -> u32 {
+        let val = (self.0 >> 0usize) & 0x00ff_ffff;
+        val as u32
+    }
+    #[inline(always)]
+    pub fn set_bootkey0_15(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize);
+    }
+}
+impl Default for Bootkey015 {
+    #[inline(always)]
+    fn default() -> Bootkey015 {
+        Bootkey015(0)
+    }
+}
+#[doc = "Bits 47:32 of SHA-256 hash of boot key 0 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Bootkey02(pub u32);
+impl Bootkey02 {
+    #[inline(always)]
+    pub const fn bootkey0_2(&self) -> u32 {
+        let val = (self.0 >> 0usize) & 0x00ff_ffff;
+        val as u32
+    }
+    #[inline(always)]
+    pub fn set_bootkey0_2(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize);
+    }
+}
+impl Default for Bootkey02 {
+    #[inline(always)]
+    fn default() -> Bootkey02 {
+        Bootkey02(0)
+    }
+}
+#[doc = "Bits 63:48 of SHA-256 hash of boot key 0 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Bootkey03(pub u32);
+impl Bootkey03 {
+    #[inline(always)]
+    pub const fn bootkey0_3(&self) -> u32 {
+        let val = (self.0 >> 0usize) & 0x00ff_ffff;
+        val as u32
+    }
+    #[inline(always)]
+    pub fn set_bootkey0_3(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize);
+    }
+}
+impl Default for Bootkey03 {
+    #[inline(always)]
+    fn default() -> Bootkey03 {
+        Bootkey03(0)
+    }
+}
+#[doc = "Bits 79:64 of SHA-256 hash of boot key 0 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Bootkey04(pub u32);
+impl Bootkey04 {
+    #[inline(always)]
+    pub const fn bootkey0_4(&self) -> u32 {
+        let val = (self.0 >> 0usize) & 0x00ff_ffff;
+        val as u32
+    }
+    #[inline(always)]
+    pub fn set_bootkey0_4(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize);
+    }
+}
+impl Default for Bootkey04 {
+    #[inline(always)]
+    fn default() -> Bootkey04 {
+        Bootkey04(0)
+    }
+}
+#[doc = "Bits 95:80 of SHA-256 hash of boot key 0 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Bootkey05(pub u32);
+impl Bootkey05 {
+    #[inline(always)]
+    pub const fn bootkey0_5(&self) -> u32 {
+        let val = (self.0 >> 0usize) & 0x00ff_ffff;
+        val as u32
+    }
+    #[inline(always)]
+    pub fn set_bootkey0_5(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize);
+    }
+}
+impl Default for Bootkey05 {
+    #[inline(always)]
+    fn default() -> Bootkey05 {
+        Bootkey05(0)
+    }
+}
+#[doc = "Bits 111:96 of SHA-256 hash of boot key 0 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Bootkey06(pub u32);
+impl Bootkey06 {
+    #[inline(always)]
+    pub const fn bootkey0_6(&self) -> u32 {
+        let val = (self.0 >> 0usize) & 0x00ff_ffff;
+        val as u32
+    }
+    #[inline(always)]
+    pub fn set_bootkey0_6(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize);
+    }
+}
+impl Default for Bootkey06 {
+    #[inline(always)]
+    fn default() -> Bootkey06 {
+        Bootkey06(0)
+    }
+}
+#[doc = "Bits 127:112 of SHA-256 hash of boot key 0 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Bootkey07(pub u32);
+impl Bootkey07 {
+    #[inline(always)]
+    pub const fn bootkey0_7(&self) -> u32 {
+        let val = (self.0 >> 0usize) & 0x00ff_ffff;
+        val as u32
+    }
+    #[inline(always)]
+    pub fn set_bootkey0_7(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize);
+    }
+}
+impl Default for Bootkey07 {
+    #[inline(always)]
+    fn default() -> Bootkey07 {
+        Bootkey07(0)
+    }
+}
+#[doc = "Bits 143:128 of SHA-256 hash of boot key 0 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Bootkey08(pub u32);
+impl Bootkey08 {
+    #[inline(always)]
+    pub const fn bootkey0_8(&self) -> u32 {
+        let val = (self.0 >> 0usize) & 0x00ff_ffff;
+        val as u32
+    }
+    #[inline(always)]
+    pub fn set_bootkey0_8(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize);
+    }
+}
+impl Default for Bootkey08 {
+    #[inline(always)]
+    fn default() -> Bootkey08 {
+        Bootkey08(0)
+    }
+}
+#[doc = "Bits 159:144 of SHA-256 hash of boot key 0 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Bootkey09(pub u32);
+impl Bootkey09 {
+    #[inline(always)]
+    pub const fn bootkey0_9(&self) -> u32 {
+        let val = (self.0 >> 0usize) & 0x00ff_ffff;
+        val as u32
+    }
+    #[inline(always)]
+    pub fn set_bootkey0_9(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize);
+    }
+}
+impl Default for Bootkey09 {
+    #[inline(always)]
+    fn default() -> Bootkey09 {
+        Bootkey09(0)
+    }
+}
+#[doc = "Bits 15:0 of SHA-256 hash of boot key 1 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Bootkey10(pub u32);
+impl Bootkey10 {
+    #[inline(always)]
+    pub const fn bootkey1_0(&self) -> u32 {
+        let val = (self.0 >> 0usize) & 0x00ff_ffff;
+        val as u32
+    }
+    #[inline(always)]
+    pub fn set_bootkey1_0(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize);
+    }
+}
+impl Default for Bootkey10 {
+    #[inline(always)]
+    fn default() -> Bootkey10 {
+        Bootkey10(0)
+    }
+}
+#[doc = "Bits 31:16 of SHA-256 hash of boot key 1 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Bootkey11(pub u32);
+impl Bootkey11 {
+    #[inline(always)]
+    pub const fn bootkey1_1(&self) -> u32 {
+        let val = (self.0 >> 0usize) & 0x00ff_ffff;
+        val as u32
+    }
+    #[inline(always)]
+    pub fn set_bootkey1_1(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize);
+    }
+}
+impl Default for Bootkey11 {
+    #[inline(always)]
+    fn default() -> Bootkey11 {
+        Bootkey11(0)
+    }
+}
+#[doc = "Bits 175:160 of SHA-256 hash of boot key 1 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Bootkey110(pub u32);
+impl Bootkey110 {
+    #[inline(always)]
+    pub const fn bootkey1_10(&self) -> u32 {
+        let val = (self.0 >> 0usize) & 0x00ff_ffff;
+        val as u32
+    }
+    #[inline(always)]
+    pub fn set_bootkey1_10(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize);
+    }
+}
+impl Default for Bootkey110 {
+    #[inline(always)]
+    fn default() -> Bootkey110 {
+        Bootkey110(0)
+    }
+}
+#[doc = "Bits 191:176 of SHA-256 hash of boot key 1 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Bootkey111(pub u32);
+impl Bootkey111 {
+    #[inline(always)]
+    pub const fn bootkey1_11(&self) -> u32 {
+        let val = (self.0 >> 0usize) & 0x00ff_ffff;
+        val as u32
+    }
+    #[inline(always)]
+    pub fn set_bootkey1_11(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize);
+    }
+}
+impl Default for Bootkey111 {
+    #[inline(always)]
+    fn default() -> Bootkey111 {
+        Bootkey111(0)
+    }
+}
+#[doc = "Bits 207:192 of SHA-256 hash of boot key 1 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Bootkey112(pub u32);
+impl Bootkey112 {
+    #[inline(always)]
+    pub const fn bootkey1_12(&self) -> u32 {
+        let val = (self.0 >> 0usize) & 0x00ff_ffff;
+        val as u32
+    }
+    #[inline(always)]
+    pub fn set_bootkey1_12(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize);
+    }
+}
+impl Default for Bootkey112 {
+    #[inline(always)]
+    fn default() -> Bootkey112 {
+        Bootkey112(0)
+    }
+}
+#[doc = "Bits 223:208 of SHA-256 hash of boot key 1 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Bootkey113(pub u32);
+impl Bootkey113 {
+    #[inline(always)]
+    pub const fn bootkey1_13(&self) -> u32 {
+        let val = (self.0 >> 0usize) & 0x00ff_ffff;
+        val as u32
+    }
+    #[inline(always)]
+    pub fn set_bootkey1_13(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize);
+    }
+}
+impl Default for Bootkey113 {
+    #[inline(always)]
+    fn default() -> Bootkey113 {
+        Bootkey113(0)
+    }
+}
+#[doc = "Bits 239:224 of SHA-256 hash of boot key 1 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Bootkey114(pub u32);
+impl Bootkey114 {
+    #[inline(always)]
+    pub const fn bootkey1_14(&self) -> u32 {
+        let val = (self.0 >> 0usize) & 0x00ff_ffff;
+        val as u32
+    }
+    #[inline(always)]
+    pub fn set_bootkey1_14(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize);
+    }
+}
+impl Default for Bootkey114 {
+    #[inline(always)]
+    fn default() -> Bootkey114 {
+        Bootkey114(0)
+    }
+}
+#[doc = "Bits 255:240 of SHA-256 hash of boot key 1 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Bootkey115(pub u32);
+impl Bootkey115 {
+    #[inline(always)]
+    pub const fn bootkey1_15(&self) -> u32 {
+        let val = (self.0 >> 0usize) & 0x00ff_ffff;
+        val as u32
+    }
+    #[inline(always)]
+    pub fn set_bootkey1_15(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize);
+    }
+}
+impl Default for Bootkey115 {
+    #[inline(always)]
+    fn default() -> Bootkey115 {
+        Bootkey115(0)
+    }
+}
+#[doc = "Bits 47:32 of SHA-256 hash of boot key 1 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Bootkey12(pub u32);
+impl Bootkey12 {
+    #[inline(always)]
+    pub const fn bootkey1_2(&self) -> u32 {
+        let val = (self.0 >> 0usize) & 0x00ff_ffff;
+        val as u32
+    }
+    #[inline(always)]
+    pub fn set_bootkey1_2(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize);
+    }
+}
+impl Default for Bootkey12 {
+    #[inline(always)]
+    fn default() -> Bootkey12 {
+        Bootkey12(0)
+    }
+}
+#[doc = "Bits 63:48 of SHA-256 hash of boot key 1 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Bootkey13(pub u32);
+impl Bootkey13 {
+    #[inline(always)]
+    pub const fn bootkey1_3(&self) -> u32 {
+        let val = (self.0 >> 0usize) & 0x00ff_ffff;
+        val as u32
+    }
+    #[inline(always)]
+    pub fn set_bootkey1_3(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize);
+    }
+}
+impl Default for Bootkey13 {
+    #[inline(always)]
+    fn default() -> Bootkey13 {
+        Bootkey13(0)
+    }
+}
+#[doc = "Bits 79:64 of SHA-256 hash of boot key 1 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Bootkey14(pub u32);
+impl Bootkey14 {
+    #[inline(always)]
+    pub const fn bootkey1_4(&self) -> u32 {
+        let val = (self.0 >> 0usize) & 0x00ff_ffff;
+        val as u32
+    }
+    #[inline(always)]
+    pub fn set_bootkey1_4(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize);
+    }
+}
+impl Default for Bootkey14 {
+    #[inline(always)]
+    fn default() -> Bootkey14 {
+        Bootkey14(0)
+    }
+}
+#[doc = "Bits 95:80 of SHA-256 hash of boot key 1 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Bootkey15(pub u32);
+impl Bootkey15 {
+    #[inline(always)]
+    pub const fn bootkey1_5(&self) -> u32 {
+        let val = (self.0 >> 0usize) & 0x00ff_ffff;
+        val as u32
+    }
+    #[inline(always)]
+    pub fn set_bootkey1_5(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize);
+    }
+}
+impl Default for Bootkey15 {
+    #[inline(always)]
+    fn default() -> Bootkey15 {
+        Bootkey15(0)
+    }
+}
+#[doc = "Bits 111:96 of SHA-256 hash of boot key 1 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Bootkey16(pub u32);
+impl Bootkey16 {
+    #[inline(always)]
+    pub const fn bootkey1_6(&self) -> u32 {
+        let val = (self.0 >> 0usize) & 0x00ff_ffff;
+        val as u32
+    }
+    #[inline(always)]
+    pub fn set_bootkey1_6(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize);
+    }
+}
+impl Default for Bootkey16 {
+    #[inline(always)]
+    fn default() -> Bootkey16 {
+        Bootkey16(0)
+    }
+}
+#[doc = "Bits 127:112 of SHA-256 hash of boot key 1 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Bootkey17(pub u32);
+impl Bootkey17 {
+    #[inline(always)]
+    pub const fn bootkey1_7(&self) -> u32 {
+        let val = (self.0 >> 0usize) & 0x00ff_ffff;
+        val as u32
+    }
+    #[inline(always)]
+    pub fn set_bootkey1_7(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize);
+    }
+}
+impl Default for Bootkey17 {
+    #[inline(always)]
+    fn default() -> Bootkey17 {
+        Bootkey17(0)
+    }
+}
+#[doc = "Bits 143:128 of SHA-256 hash of boot key 1 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Bootkey18(pub u32);
+impl Bootkey18 {
+    #[inline(always)]
+    pub const fn bootkey1_8(&self) -> u32 {
+        let val = (self.0 >> 0usize) & 0x00ff_ffff;
+        val as u32
+    }
+    #[inline(always)]
+    pub fn set_bootkey1_8(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize);
+    }
+}
+impl Default for Bootkey18 {
+    #[inline(always)]
+    fn default() -> Bootkey18 {
+        Bootkey18(0)
+    }
+}
+#[doc = "Bits 159:144 of SHA-256 hash of boot key 1 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Bootkey19(pub u32);
+impl Bootkey19 {
+    #[inline(always)]
+    pub const fn bootkey1_9(&self) -> u32 {
+        let val = (self.0 >> 0usize) & 0x00ff_ffff;
+        val as u32
+    }
+    #[inline(always)]
+    pub fn set_bootkey1_9(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize);
+    }
+}
+impl Default for Bootkey19 {
+    #[inline(always)]
+    fn default() -> Bootkey19 {
+        Bootkey19(0)
+    }
+}
+#[doc = "Bits 15:0 of SHA-256 hash of boot key 2 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Bootkey20(pub u32);
+impl Bootkey20 {
+    #[inline(always)]
+    pub const fn bootkey2_0(&self) -> u32 {
+        let val = (self.0 >> 0usize) & 0x00ff_ffff;
+        val as u32
+    }
+    #[inline(always)]
+    pub fn set_bootkey2_0(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize);
+    }
+}
+impl Default for Bootkey20 {
+    #[inline(always)]
+    fn default() -> Bootkey20 {
+        Bootkey20(0)
+    }
+}
+#[doc = "Bits 31:16 of SHA-256 hash of boot key 2 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Bootkey21(pub u32);
+impl Bootkey21 {
+    #[inline(always)]
+    pub const fn bootkey2_1(&self) -> u32 {
+        let val = (self.0 >> 0usize) & 0x00ff_ffff;
+        val as u32
+    }
+    #[inline(always)]
+    pub fn set_bootkey2_1(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize);
+    }
+}
+impl Default for Bootkey21 {
+    #[inline(always)]
+    fn default() -> Bootkey21 {
+        Bootkey21(0)
+    }
+}
+#[doc = "Bits 175:160 of SHA-256 hash of boot key 2 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Bootkey210(pub u32);
+impl Bootkey210 {
+    #[inline(always)]
+    pub const fn bootkey2_10(&self) -> u32 {
+        let val = (self.0 >> 0usize) & 0x00ff_ffff;
+        val as u32
+    }
+    #[inline(always)]
+    pub fn set_bootkey2_10(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize);
+    }
+}
+impl Default for Bootkey210 {
+    #[inline(always)]
+    fn default() -> Bootkey210 {
+        Bootkey210(0)
+    }
+}
+#[doc = "Bits 191:176 of SHA-256 hash of boot key 2 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Bootkey211(pub u32);
+impl Bootkey211 {
+    #[inline(always)]
+    pub const fn bootkey2_11(&self) -> u32 {
+        let val = (self.0 >> 0usize) & 0x00ff_ffff;
+        val as u32
+    }
+    #[inline(always)]
+    pub fn set_bootkey2_11(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize);
+    }
+}
+impl Default for Bootkey211 {
+    #[inline(always)]
+    fn default() -> Bootkey211 {
+        Bootkey211(0)
+    }
+}
+#[doc = "Bits 207:192 of SHA-256 hash of boot key 2 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Bootkey212(pub u32);
+impl Bootkey212 {
+    #[inline(always)]
+    pub const fn bootkey2_12(&self) -> u32 {
+        let val = (self.0 >> 0usize) & 0x00ff_ffff;
+        val as u32
+    }
+    #[inline(always)]
+    pub fn set_bootkey2_12(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize);
+    }
+}
+impl Default for Bootkey212 {
+    #[inline(always)]
+    fn default() -> Bootkey212 {
+        Bootkey212(0)
+    }
+}
+#[doc = "Bits 223:208 of SHA-256 hash of boot key 2 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Bootkey213(pub u32);
+impl Bootkey213 {
+    #[inline(always)]
+    pub const fn bootkey2_13(&self) -> u32 {
+        let val = (self.0 >> 0usize) & 0x00ff_ffff;
+        val as u32
+    }
+    #[inline(always)]
+    pub fn set_bootkey2_13(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize);
+    }
+}
+impl Default for Bootkey213 {
+    #[inline(always)]
+    fn default() -> Bootkey213 {
+        Bootkey213(0)
+    }
+}
+#[doc = "Bits 239:224 of SHA-256 hash of boot key 2 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Bootkey214(pub u32);
+impl Bootkey214 {
+    #[inline(always)]
+    pub const fn bootkey2_14(&self) -> u32 {
+        let val = (self.0 >> 0usize) & 0x00ff_ffff;
+        val as u32
+    }
+    #[inline(always)]
+    pub fn set_bootkey2_14(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize);
+    }
+}
+impl Default for Bootkey214 {
+    #[inline(always)]
+    fn default() -> Bootkey214 {
+        Bootkey214(0)
+    }
+}
+#[doc = "Bits 255:240 of SHA-256 hash of boot key 2 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Bootkey215(pub u32);
+impl Bootkey215 {
+    #[inline(always)]
+    pub const fn bootkey2_15(&self) -> u32 {
+        let val = (self.0 >> 0usize) & 0x00ff_ffff;
+        val as u32
+    }
+    #[inline(always)]
+    pub fn set_bootkey2_15(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize);
+    }
+}
+impl Default for Bootkey215 {
+    #[inline(always)]
+    fn default() -> Bootkey215 {
+        Bootkey215(0)
+    }
+}
+#[doc = "Bits 47:32 of SHA-256 hash of boot key 2 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Bootkey22(pub u32);
+impl Bootkey22 {
+    #[inline(always)]
+    pub const fn bootkey2_2(&self) -> u32 {
+        let val = (self.0 >> 0usize) & 0x00ff_ffff;
+        val as u32
+    }
+    #[inline(always)]
+    pub fn set_bootkey2_2(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize);
+    }
+}
+impl Default for Bootkey22 {
+    #[inline(always)]
+    fn default() -> Bootkey22 {
+        Bootkey22(0)
+    }
+}
+#[doc = "Bits 63:48 of SHA-256 hash of boot key 2 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Bootkey23(pub u32);
+impl Bootkey23 {
+    #[inline(always)]
+    pub const fn bootkey2_3(&self) -> u32 {
+        let val = (self.0 >> 0usize) & 0x00ff_ffff;
+        val as u32
+    }
+    #[inline(always)]
+    pub fn set_bootkey2_3(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize);
+    }
+}
+impl Default for Bootkey23 {
+    #[inline(always)]
+    fn default() -> Bootkey23 {
+        Bootkey23(0)
+    }
+}
+#[doc = "Bits 79:64 of SHA-256 hash of boot key 2 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Bootkey24(pub u32);
+impl Bootkey24 {
+    #[inline(always)]
+    pub const fn bootkey2_4(&self) -> u32 {
+        let val = (self.0 >> 0usize) & 0x00ff_ffff;
+        val as u32
+    }
+    #[inline(always)]
+    pub fn set_bootkey2_4(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize);
+    }
+}
+impl Default for Bootkey24 {
+    #[inline(always)]
+    fn default() -> Bootkey24 {
+        Bootkey24(0)
+    }
+}
+#[doc = "Bits 95:80 of SHA-256 hash of boot key 2 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Bootkey25(pub u32);
+impl Bootkey25 {
+    #[inline(always)]
+    pub const fn bootkey2_5(&self) -> u32 {
+        let val = (self.0 >> 0usize) & 0x00ff_ffff;
+        val as u32
+    }
+    #[inline(always)]
+    pub fn set_bootkey2_5(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize);
+    }
+}
+impl Default for Bootkey25 {
+    #[inline(always)]
+    fn default() -> Bootkey25 {
+        Bootkey25(0)
+    }
+}
+#[doc = "Bits 111:96 of SHA-256 hash of boot key 2 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Bootkey26(pub u32);
+impl Bootkey26 {
+    #[inline(always)]
+    pub const fn bootkey2_6(&self) -> u32 {
+        let val = (self.0 >> 0usize) & 0x00ff_ffff;
+        val as u32
+    }
+    #[inline(always)]
+    pub fn set_bootkey2_6(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize);
+    }
+}
+impl Default for Bootkey26 {
+    #[inline(always)]
+    fn default() -> Bootkey26 {
+        Bootkey26(0)
+    }
+}
+#[doc = "Bits 127:112 of SHA-256 hash of boot key 2 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Bootkey27(pub u32);
+impl Bootkey27 {
+    #[inline(always)]
+    pub const fn bootkey2_7(&self) -> u32 {
+        let val = (self.0 >> 0usize) & 0x00ff_ffff;
+        val as u32
+    }
+    #[inline(always)]
+    pub fn set_bootkey2_7(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize);
+    }
+}
+impl Default for Bootkey27 {
+    #[inline(always)]
+    fn default() -> Bootkey27 {
+        Bootkey27(0)
+    }
+}
+#[doc = "Bits 143:128 of SHA-256 hash of boot key 2 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Bootkey28(pub u32);
+impl Bootkey28 {
+    #[inline(always)]
+    pub const fn bootkey2_8(&self) -> u32 {
+        let val = (self.0 >> 0usize) & 0x00ff_ffff;
+        val as u32
+    }
+    #[inline(always)]
+    pub fn set_bootkey2_8(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize);
+    }
+}
+impl Default for Bootkey28 {
+    #[inline(always)]
+    fn default() -> Bootkey28 {
+        Bootkey28(0)
+    }
+}
+#[doc = "Bits 159:144 of SHA-256 hash of boot key 2 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Bootkey29(pub u32);
+impl Bootkey29 {
+    #[inline(always)]
+    pub const fn bootkey2_9(&self) -> u32 {
+        let val = (self.0 >> 0usize) & 0x00ff_ffff;
+        val as u32
+    }
+    #[inline(always)]
+    pub fn set_bootkey2_9(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize);
+    }
+}
+impl Default for Bootkey29 {
+    #[inline(always)]
+    fn default() -> Bootkey29 {
+        Bootkey29(0)
+    }
+}
+#[doc = "Bits 15:0 of SHA-256 hash of boot key 3 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Bootkey30(pub u32);
+impl Bootkey30 {
+    #[inline(always)]
+    pub const fn bootkey3_0(&self) -> u32 {
+        let val = (self.0 >> 0usize) & 0x00ff_ffff;
+        val as u32
+    }
+    #[inline(always)]
+    pub fn set_bootkey3_0(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize);
+    }
+}
+impl Default for Bootkey30 {
+    #[inline(always)]
+    fn default() -> Bootkey30 {
+        Bootkey30(0)
+    }
+}
+#[doc = "Bits 31:16 of SHA-256 hash of boot key 3 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Bootkey31(pub u32);
+impl Bootkey31 {
+    #[inline(always)]
+    pub const fn bootkey3_1(&self) -> u32 {
+        let val = (self.0 >> 0usize) & 0x00ff_ffff;
+        val as u32
+    }
+    #[inline(always)]
+    pub fn set_bootkey3_1(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize);
+    }
+}
+impl Default for Bootkey31 {
+    #[inline(always)]
+    fn default() -> Bootkey31 {
+        Bootkey31(0)
+    }
+}
+#[doc = "Bits 175:160 of SHA-256 hash of boot key 3 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Bootkey310(pub u32);
+impl Bootkey310 {
+    #[inline(always)]
+    pub const fn bootkey3_10(&self) -> u32 {
+        let val = (self.0 >> 0usize) & 0x00ff_ffff;
+        val as u32
+    }
+    #[inline(always)]
+    pub fn set_bootkey3_10(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize);
+    }
+}
+impl Default for Bootkey310 {
+    #[inline(always)]
+    fn default() -> Bootkey310 {
+        Bootkey310(0)
+    }
+}
+#[doc = "Bits 191:176 of SHA-256 hash of boot key 3 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Bootkey311(pub u32);
+impl Bootkey311 {
+    #[inline(always)]
+    pub const fn bootkey3_11(&self) -> u32 {
+        let val = (self.0 >> 0usize) & 0x00ff_ffff;
+        val as u32
+    }
+    #[inline(always)]
+    pub fn set_bootkey3_11(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize);
+    }
+}
+impl Default for Bootkey311 {
+    #[inline(always)]
+    fn default() -> Bootkey311 {
+        Bootkey311(0)
+    }
+}
+#[doc = "Bits 207:192 of SHA-256 hash of boot key 3 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Bootkey312(pub u32);
+impl Bootkey312 {
+    #[inline(always)]
+    pub const fn bootkey3_12(&self) -> u32 {
+        let val = (self.0 >> 0usize) & 0x00ff_ffff;
+        val as u32
+    }
+    #[inline(always)]
+    pub fn set_bootkey3_12(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize);
+    }
+}
+impl Default for Bootkey312 {
+    #[inline(always)]
+    fn default() -> Bootkey312 {
+        Bootkey312(0)
+    }
+}
+#[doc = "Bits 223:208 of SHA-256 hash of boot key 3 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Bootkey313(pub u32);
+impl Bootkey313 {
+    #[inline(always)]
+    pub const fn bootkey3_13(&self) -> u32 {
+        let val = (self.0 >> 0usize) & 0x00ff_ffff;
+        val as u32
+    }
+    #[inline(always)]
+    pub fn set_bootkey3_13(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize);
+    }
+}
+impl Default for Bootkey313 {
+    #[inline(always)]
+    fn default() -> Bootkey313 {
+        Bootkey313(0)
+    }
+}
+#[doc = "Bits 239:224 of SHA-256 hash of boot key 3 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Bootkey314(pub u32);
+impl Bootkey314 {
+    #[inline(always)]
+    pub const fn bootkey3_14(&self) -> u32 {
+        let val = (self.0 >> 0usize) & 0x00ff_ffff;
+        val as u32
+    }
+    #[inline(always)]
+    pub fn set_bootkey3_14(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize);
+    }
+}
+impl Default for Bootkey314 {
+    #[inline(always)]
+    fn default() -> Bootkey314 {
+        Bootkey314(0)
+    }
+}
+#[doc = "Bits 255:240 of SHA-256 hash of boot key 3 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Bootkey315(pub u32);
+impl Bootkey315 {
+    #[inline(always)]
+    pub const fn bootkey3_15(&self) -> u32 {
+        let val = (self.0 >> 0usize) & 0x00ff_ffff;
+        val as u32
+    }
+    #[inline(always)]
+    pub fn set_bootkey3_15(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize);
+    }
+}
+impl Default for Bootkey315 {
+    #[inline(always)]
+    fn default() -> Bootkey315 {
+        Bootkey315(0)
+    }
+}
+#[doc = "Bits 47:32 of SHA-256 hash of boot key 3 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Bootkey32(pub u32);
+impl Bootkey32 {
+    #[inline(always)]
+    pub const fn bootkey3_2(&self) -> u32 {
+        let val = (self.0 >> 0usize) & 0x00ff_ffff;
+        val as u32
+    }
+    #[inline(always)]
+    pub fn set_bootkey3_2(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize);
+    }
+}
+impl Default for Bootkey32 {
+    #[inline(always)]
+    fn default() -> Bootkey32 {
+        Bootkey32(0)
+    }
+}
+#[doc = "Bits 63:48 of SHA-256 hash of boot key 3 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Bootkey33(pub u32);
+impl Bootkey33 {
+    #[inline(always)]
+    pub const fn bootkey3_3(&self) -> u32 {
+        let val = (self.0 >> 0usize) & 0x00ff_ffff;
+        val as u32
+    }
+    #[inline(always)]
+    pub fn set_bootkey3_3(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize);
+    }
+}
+impl Default for Bootkey33 {
+    #[inline(always)]
+    fn default() -> Bootkey33 {
+        Bootkey33(0)
+    }
+}
+#[doc = "Bits 79:64 of SHA-256 hash of boot key 3 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Bootkey34(pub u32);
+impl Bootkey34 {
+    #[inline(always)]
+    pub const fn bootkey3_4(&self) -> u32 {
+        let val = (self.0 >> 0usize) & 0x00ff_ffff;
+        val as u32
+    }
+    #[inline(always)]
+    pub fn set_bootkey3_4(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize);
+    }
+}
+impl Default for Bootkey34 {
+    #[inline(always)]
+    fn default() -> Bootkey34 {
+        Bootkey34(0)
+    }
+}
+#[doc = "Bits 95:80 of SHA-256 hash of boot key 3 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Bootkey35(pub u32);
+impl Bootkey35 {
+    #[inline(always)]
+    pub const fn bootkey3_5(&self) -> u32 {
+        let val = (self.0 >> 0usize) & 0x00ff_ffff;
+        val as u32
+    }
+    #[inline(always)]
+    pub fn set_bootkey3_5(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize);
+    }
+}
+impl Default for Bootkey35 {
+    #[inline(always)]
+    fn default() -> Bootkey35 {
+        Bootkey35(0)
+    }
+}
+#[doc = "Bits 111:96 of SHA-256 hash of boot key 3 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Bootkey36(pub u32);
+impl Bootkey36 {
+    #[inline(always)]
+    pub const fn bootkey3_6(&self) -> u32 {
+        let val = (self.0 >> 0usize) & 0x00ff_ffff;
+        val as u32
+    }
+    #[inline(always)]
+    pub fn set_bootkey3_6(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize);
+    }
+}
+impl Default for Bootkey36 {
+    #[inline(always)]
+    fn default() -> Bootkey36 {
+        Bootkey36(0)
+    }
+}
+#[doc = "Bits 127:112 of SHA-256 hash of boot key 3 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Bootkey37(pub u32);
+impl Bootkey37 {
+    #[inline(always)]
+    pub const fn bootkey3_7(&self) -> u32 {
+        let val = (self.0 >> 0usize) & 0x00ff_ffff;
+        val as u32
+    }
+    #[inline(always)]
+    pub fn set_bootkey3_7(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize);
+    }
+}
+impl Default for Bootkey37 {
+    #[inline(always)]
+    fn default() -> Bootkey37 {
+        Bootkey37(0)
+    }
+}
+#[doc = "Bits 143:128 of SHA-256 hash of boot key 3 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Bootkey38(pub u32);
+impl Bootkey38 {
+    #[inline(always)]
+    pub const fn bootkey3_8(&self) -> u32 {
+        let val = (self.0 >> 0usize) & 0x00ff_ffff;
+        val as u32
+    }
+    #[inline(always)]
+    pub fn set_bootkey3_8(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize);
+    }
+}
+impl Default for Bootkey38 {
+    #[inline(always)]
+    fn default() -> Bootkey38 {
+        Bootkey38(0)
+    }
+}
+#[doc = "Bits 159:144 of SHA-256 hash of boot key 3 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Bootkey39(pub u32);
+impl Bootkey39 {
+    #[inline(always)]
+    pub const fn bootkey3_9(&self) -> u32 {
+        let val = (self.0 >> 0usize) & 0x00ff_ffff;
+        val as u32
+    }
+    #[inline(always)]
+    pub fn set_bootkey3_9(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize);
+    }
+}
+impl Default for Bootkey39 {
+    #[inline(always)]
+    fn default() -> Bootkey39 {
+        Bootkey39(0)
+    }
+}
+#[doc = "Pin configuration for LED status, used by USB bootloader. (ECC) Must be valid if BOOT_FLAGS0_ENABLE_BOOTSEL_LED is set."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct BootselLedCfg(pub u32);
+impl BootselLedCfg {
+    #[doc = "GPIO index to use for bootloader activity LED."]
+    #[inline(always)]
+    pub const fn pin(&self) -> u8 {
+        let val = (self.0 >> 0usize) & 0x3f;
+        val as u8
+    }
+    #[doc = "GPIO index to use for bootloader activity LED."]
+    #[inline(always)]
+    pub fn set_pin(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x3f << 0usize)) | (((val as u32) & 0x3f) << 0usize);
+    }
+    #[doc = "LED is active-low. (Default: active-high.)"]
+    #[inline(always)]
+    pub const fn activelow(&self) -> u16 {
+        let val = (self.0 >> 8usize) & 0xffff;
+        val as u16
+    }
+    #[doc = "LED is active-low. (Default: active-high.)"]
+    #[inline(always)]
+    pub fn set_activelow(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 8usize)) | (((val as u32) & 0xffff) << 8usize);
+    }
+}
+impl Default for BootselLedCfg {
+    #[inline(always)]
+    fn default() -> BootselLedCfg {
+        BootselLedCfg(0)
+    }
+}
+#[doc = "Optional PLL configuration for BOOTSEL mode. (ECC) This should be configured to produce an exact 48 MHz based on the crystal oscillator frequency. User mode software may also use this value to calculate the expected crystal frequency based on an assumed 48 MHz PLL output. If no configuration is given, the crystal is assumed to be 12 MHz. The PLL frequency can be calculated as: PLL out = (XOSC frequency / (REFDIV+1)) x FBDIV / (POSTDIV1 x POSTDIV2) Conversely the crystal frequency can be calculated as: XOSC frequency = 48 MHz x (REFDIV+1) x (POSTDIV1 x POSTDIV2) / FBDIV (Note the +1 on REFDIV is because the value stored in this OTP location is the actual divisor value minus one.) Used if and only if ENABLE_BOOTSEL_NON_DEFAULT_PLL_XOSC_CFG is set in BOOT_FLAGS0. That bit should be set only after this row and BOOTSEL_XOSC_CFG are both correctly programmed."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct BootselPllCfg(pub u32);
+impl BootselPllCfg {
+    #[doc = "PLL feedback divisor, in the range 16..320 inclusive."]
+    #[inline(always)]
+    pub const fn fbdiv(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0x01ff;
+        val as u16
+    }
+    #[doc = "PLL feedback divisor, in the range 16..320 inclusive."]
+    #[inline(always)]
+    pub fn set_fbdiv(&mut self, val: u16) {
+        self.0 = (self.0 & !(0x01ff << 0usize)) | (((val as u32) & 0x01ff) << 0usize);
+    }
+    #[doc = "PLL post-divide 1 divisor, in the range 1..7 inclusive."]
+    #[inline(always)]
+    pub const fn postdiv1(&self) -> u8 {
+        let val = (self.0 >> 9usize) & 0x07;
+        val as u8
+    }
+    #[doc = "PLL post-divide 1 divisor, in the range 1..7 inclusive."]
+    #[inline(always)]
+    pub fn set_postdiv1(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x07 << 9usize)) | (((val as u32) & 0x07) << 9usize);
+    }
+    #[doc = "PLL post-divide 2 divisor, in the range 1..7 inclusive."]
+    #[inline(always)]
+    pub const fn postdiv2(&self) -> u8 {
+        let val = (self.0 >> 12usize) & 0x07;
+        val as u8
+    }
+    #[doc = "PLL post-divide 2 divisor, in the range 1..7 inclusive."]
+    #[inline(always)]
+    pub fn set_postdiv2(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x07 << 12usize)) | (((val as u32) & 0x07) << 12usize);
+    }
+    #[doc = "PLL reference divisor, minus one. Programming a value of 0 means a reference divisor of 1. Programming a value of 1 means a reference divisor of 2 (for exceptionally fast XIN inputs)"]
+    #[inline(always)]
+    pub const fn refdiv(&self) -> u16 {
+        let val = (self.0 >> 15usize) & 0x01ff;
+        val as u16
+    }
+    #[doc = "PLL reference divisor, minus one. Programming a value of 0 means a reference divisor of 1. Programming a value of 1 means a reference divisor of 2 (for exceptionally fast XIN inputs)"]
+    #[inline(always)]
+    pub fn set_refdiv(&mut self, val: u16) {
+        self.0 = (self.0 & !(0x01ff << 15usize)) | (((val as u32) & 0x01ff) << 15usize);
+    }
+}
+impl Default for BootselPllCfg {
+    #[inline(always)]
+    fn default() -> BootselPllCfg {
+        BootselPllCfg(0)
+    }
+}
+#[doc = "Non-default crystal oscillator configuration for the USB bootloader. (ECC) These values may also be used by user code configuring the crystal oscillator. Used if and only if ENABLE_BOOTSEL_NON_DEFAULT_PLL_XOSC_CFG is set in BOOT_FLAGS0. That bit should be set only after this row and BOOTSEL_PLL_CFG are both correctly programmed."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct BootselXoscCfg(pub u32);
+impl BootselXoscCfg {
+    #[doc = "Value of the XOSC_STARTUP register"]
+    #[inline(always)]
+    pub const fn startup(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0x3fff;
+        val as u16
+    }
+    #[doc = "Value of the XOSC_STARTUP register"]
+    #[inline(always)]
+    pub fn set_startup(&mut self, val: u16) {
+        self.0 = (self.0 & !(0x3fff << 0usize)) | (((val as u32) & 0x3fff) << 0usize);
+    }
+    #[doc = "Value of the XOSC_CTRL_FREQ_RANGE register."]
+    #[inline(always)]
+    pub const fn range(&self) -> super::vals::Range {
+        let val = (self.0 >> 14usize) & 0x03ff;
+        super::vals::Range::from_bits(val as u16)
+    }
+    #[doc = "Value of the XOSC_CTRL_FREQ_RANGE register."]
+    #[inline(always)]
+    pub fn set_range(&mut self, val: super::vals::Range) {
+        self.0 = (self.0 & !(0x03ff << 14usize)) | (((val.to_bits() as u32) & 0x03ff) << 14usize);
+    }
+}
+impl Default for BootselXoscCfg {
+    #[inline(always)]
+    fn default() -> BootselXoscCfg {
+        BootselXoscCfg(0)
+    }
+}
+#[doc = "Bits 15:0 of public device ID. (ECC) The CHIPID0..3 rows contain a 64-bit random identifier for this chip, which can be read from the USB bootloader PICOBOOT interface or from the get_sys_info ROM API. The number of random bits makes the occurrence of twins exceedingly unlikely: for example, a fleet of a hundred million devices has a 99.97% probability of no twinned IDs. This is estimated to be lower than the occurrence of process errors in the assignment of sequential random IDs, and for practical purposes CHIPID may be treated as unique."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Chipid0(pub u32);
+impl Chipid0 {
+    #[inline(always)]
+    pub const fn chipid0(&self) -> u32 {
+        let val = (self.0 >> 0usize) & 0x00ff_ffff;
+        val as u32
+    }
+    #[inline(always)]
+    pub fn set_chipid0(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize);
+    }
+}
+impl Default for Chipid0 {
+    #[inline(always)]
+    fn default() -> Chipid0 {
+        Chipid0(0)
+    }
+}
+#[doc = "Bits 31:16 of public device ID (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Chipid1(pub u32);
+impl Chipid1 {
+    #[inline(always)]
+    pub const fn chipid1(&self) -> u32 {
+        let val = (self.0 >> 0usize) & 0x00ff_ffff;
+        val as u32
+    }
+    #[inline(always)]
+    pub fn set_chipid1(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize);
+    }
+}
+impl Default for Chipid1 {
+    #[inline(always)]
+    fn default() -> Chipid1 {
+        Chipid1(0)
+    }
+}
+#[doc = "Bits 47:32 of public device ID (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Chipid2(pub u32);
+impl Chipid2 {
+    #[inline(always)]
+    pub const fn chipid2(&self) -> u32 {
+        let val = (self.0 >> 0usize) & 0x00ff_ffff;
+        val as u32
+    }
+    #[inline(always)]
+    pub fn set_chipid2(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize);
+    }
+}
+impl Default for Chipid2 {
+    #[inline(always)]
+    fn default() -> Chipid2 {
+        Chipid2(0)
+    }
+}
+#[doc = "Bits 63:48 of public device ID (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Chipid3(pub u32);
+impl Chipid3 {
+    #[inline(always)]
+    pub const fn chipid3(&self) -> u32 {
+        let val = (self.0 >> 0usize) & 0x00ff_ffff;
+        val as u32
+    }
+    #[inline(always)]
+    pub fn set_chipid3(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize);
+    }
+}
+impl Default for Chipid3 {
+    #[inline(always)]
+    fn default() -> Chipid3 {
+        Chipid3(0)
+    }
+}
+#[doc = "Page 0 critical boot flags (RBIT-8)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Crit0(pub u32);
+impl Crit0 {
+    #[doc = "Permanently disable ARM processors (Cortex-M33)"]
+    #[inline(always)]
+    pub const fn arm_disable(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Permanently disable ARM processors (Cortex-M33)"]
+    #[inline(always)]
+    pub fn set_arm_disable(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[doc = "Permanently disable RISC-V processors (Hazard3)"]
+    #[inline(always)]
+    pub const fn riscv_disable(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Permanently disable RISC-V processors (Hazard3)"]
+    #[inline(always)]
+    pub fn set_riscv_disable(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+}
+impl Default for Crit0 {
+    #[inline(always)]
+    fn default() -> Crit0 {
+        Crit0(0)
+    }
+}
+#[doc = "Redundant copy of CRIT0"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Crit0r1(pub u32);
+impl Crit0r1 {
+    #[inline(always)]
+    pub const fn crit0_r1(&self) -> u32 {
+        let val = (self.0 >> 0usize) & 0x00ff_ffff;
+        val as u32
+    }
+    #[inline(always)]
+    pub fn set_crit0_r1(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize);
+    }
+}
+impl Default for Crit0r1 {
+    #[inline(always)]
+    fn default() -> Crit0r1 {
+        Crit0r1(0)
+    }
+}
+#[doc = "Redundant copy of CRIT0"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Crit0r2(pub u32);
+impl Crit0r2 {
+    #[inline(always)]
+    pub const fn crit0_r2(&self) -> u32 {
+        let val = (self.0 >> 0usize) & 0x00ff_ffff;
+        val as u32
+    }
+    #[inline(always)]
+    pub fn set_crit0_r2(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize);
+    }
+}
+impl Default for Crit0r2 {
+    #[inline(always)]
+    fn default() -> Crit0r2 {
+        Crit0r2(0)
+    }
+}
+#[doc = "Redundant copy of CRIT0"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Crit0r3(pub u32);
+impl Crit0r3 {
+    #[inline(always)]
+    pub const fn crit0_r3(&self) -> u32 {
+        let val = (self.0 >> 0usize) & 0x00ff_ffff;
+        val as u32
+    }
+    #[inline(always)]
+    pub fn set_crit0_r3(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize);
+    }
+}
+impl Default for Crit0r3 {
+    #[inline(always)]
+    fn default() -> Crit0r3 {
+        Crit0r3(0)
+    }
+}
+#[doc = "Redundant copy of CRIT0"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Crit0r4(pub u32);
+impl Crit0r4 {
+    #[inline(always)]
+    pub const fn crit0_r4(&self) -> u32 {
+        let val = (self.0 >> 0usize) & 0x00ff_ffff;
+        val as u32
+    }
+    #[inline(always)]
+    pub fn set_crit0_r4(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize);
+    }
+}
+impl Default for Crit0r4 {
+    #[inline(always)]
+    fn default() -> Crit0r4 {
+        Crit0r4(0)
+    }
+}
+#[doc = "Redundant copy of CRIT0"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Crit0r5(pub u32);
+impl Crit0r5 {
+    #[inline(always)]
+    pub const fn crit0_r5(&self) -> u32 {
+        let val = (self.0 >> 0usize) & 0x00ff_ffff;
+        val as u32
+    }
+    #[inline(always)]
+    pub fn set_crit0_r5(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize);
+    }
+}
+impl Default for Crit0r5 {
+    #[inline(always)]
+    fn default() -> Crit0r5 {
+        Crit0r5(0)
+    }
+}
+#[doc = "Redundant copy of CRIT0"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Crit0r6(pub u32);
+impl Crit0r6 {
+    #[inline(always)]
+    pub const fn crit0_r6(&self) -> u32 {
+        let val = (self.0 >> 0usize) & 0x00ff_ffff;
+        val as u32
+    }
+    #[inline(always)]
+    pub fn set_crit0_r6(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize);
+    }
+}
+impl Default for Crit0r6 {
+    #[inline(always)]
+    fn default() -> Crit0r6 {
+        Crit0r6(0)
+    }
+}
+#[doc = "Redundant copy of CRIT0"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Crit0r7(pub u32);
+impl Crit0r7 {
+    #[inline(always)]
+    pub const fn crit0_r7(&self) -> u32 {
+        let val = (self.0 >> 0usize) & 0x00ff_ffff;
+        val as u32
+    }
+    #[inline(always)]
+    pub fn set_crit0_r7(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize);
+    }
+}
+impl Default for Crit0r7 {
+    #[inline(always)]
+    fn default() -> Crit0r7 {
+        Crit0r7(0)
+    }
+}
+#[doc = "Page 1 critical boot flags (RBIT-8)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Crit1(pub u32);
+impl Crit1 {
+    #[doc = "Enable boot signature enforcement, and permanently disable the RISC-V cores."]
+    #[inline(always)]
+    pub const fn secure_boot_enable(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Enable boot signature enforcement, and permanently disable the RISC-V cores."]
+    #[inline(always)]
+    pub fn set_secure_boot_enable(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[doc = "Disable Secure debug access"]
+    #[inline(always)]
+    pub const fn secure_debug_disable(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Disable Secure debug access"]
+    #[inline(always)]
+    pub fn set_secure_debug_disable(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+    #[doc = "Disable all debug access"]
+    #[inline(always)]
+    pub const fn debug_disable(&self) -> bool {
+        let val = (self.0 >> 2usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Disable all debug access"]
+    #[inline(always)]
+    pub fn set_debug_disable(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+    }
+    #[doc = "Set the default boot architecture, 0=ARM 1=RISC-V. Ignored if ARM_DISABLE, RISCV_DISABLE or SECURE_BOOT_ENABLE is set."]
+    #[inline(always)]
+    pub const fn boot_arch(&self) -> bool {
+        let val = (self.0 >> 3usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Set the default boot architecture, 0=ARM 1=RISC-V. Ignored if ARM_DISABLE, RISCV_DISABLE or SECURE_BOOT_ENABLE is set."]
+    #[inline(always)]
+    pub fn set_boot_arch(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
+    }
+    #[doc = "Arm the glitch detectors to reset the system if an abnormal clock/power event is observed."]
+    #[inline(always)]
+    pub const fn glitch_detector_enable(&self) -> bool {
+        let val = (self.0 >> 4usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Arm the glitch detectors to reset the system if an abnormal clock/power event is observed."]
+    #[inline(always)]
+    pub fn set_glitch_detector_enable(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
+    }
+    #[doc = "Increase the sensitivity of the glitch detectors from their default."]
+    #[inline(always)]
+    pub const fn glitch_detector_sens(&self) -> u8 {
+        let val = (self.0 >> 5usize) & 0x03;
+        val as u8
+    }
+    #[doc = "Increase the sensitivity of the glitch detectors from their default."]
+    #[inline(always)]
+    pub fn set_glitch_detector_sens(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x03 << 5usize)) | (((val as u32) & 0x03) << 5usize);
+    }
+}
+impl Default for Crit1 {
+    #[inline(always)]
+    fn default() -> Crit1 {
+        Crit1(0)
+    }
+}
+#[doc = "Redundant copy of CRIT1"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Crit1r1(pub u32);
+impl Crit1r1 {
+    #[inline(always)]
+    pub const fn crit1_r1(&self) -> u32 {
+        let val = (self.0 >> 0usize) & 0x00ff_ffff;
+        val as u32
+    }
+    #[inline(always)]
+    pub fn set_crit1_r1(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize);
+    }
+}
+impl Default for Crit1r1 {
+    #[inline(always)]
+    fn default() -> Crit1r1 {
+        Crit1r1(0)
+    }
+}
+#[doc = "Redundant copy of CRIT1"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Crit1r2(pub u32);
+impl Crit1r2 {
+    #[inline(always)]
+    pub const fn crit1_r2(&self) -> u32 {
+        let val = (self.0 >> 0usize) & 0x00ff_ffff;
+        val as u32
+    }
+    #[inline(always)]
+    pub fn set_crit1_r2(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize);
+    }
+}
+impl Default for Crit1r2 {
+    #[inline(always)]
+    fn default() -> Crit1r2 {
+        Crit1r2(0)
+    }
+}
+#[doc = "Redundant copy of CRIT1"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Crit1r3(pub u32);
+impl Crit1r3 {
+    #[inline(always)]
+    pub const fn crit1_r3(&self) -> u32 {
+        let val = (self.0 >> 0usize) & 0x00ff_ffff;
+        val as u32
+    }
+    #[inline(always)]
+    pub fn set_crit1_r3(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize);
+    }
+}
+impl Default for Crit1r3 {
+    #[inline(always)]
+    fn default() -> Crit1r3 {
+        Crit1r3(0)
+    }
+}
+#[doc = "Redundant copy of CRIT1"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Crit1r4(pub u32);
+impl Crit1r4 {
+    #[inline(always)]
+    pub const fn crit1_r4(&self) -> u32 {
+        let val = (self.0 >> 0usize) & 0x00ff_ffff;
+        val as u32
+    }
+    #[inline(always)]
+    pub fn set_crit1_r4(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize);
+    }
+}
+impl Default for Crit1r4 {
+    #[inline(always)]
+    fn default() -> Crit1r4 {
+        Crit1r4(0)
+    }
+}
+#[doc = "Redundant copy of CRIT1"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Crit1r5(pub u32);
+impl Crit1r5 {
+    #[inline(always)]
+    pub const fn crit1_r5(&self) -> u32 {
+        let val = (self.0 >> 0usize) & 0x00ff_ffff;
+        val as u32
+    }
+    #[inline(always)]
+    pub fn set_crit1_r5(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize);
+    }
+}
+impl Default for Crit1r5 {
+    #[inline(always)]
+    fn default() -> Crit1r5 {
+        Crit1r5(0)
+    }
+}
+#[doc = "Redundant copy of CRIT1"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Crit1r6(pub u32);
+impl Crit1r6 {
+    #[inline(always)]
+    pub const fn crit1_r6(&self) -> u32 {
+        let val = (self.0 >> 0usize) & 0x00ff_ffff;
+        val as u32
+    }
+    #[inline(always)]
+    pub fn set_crit1_r6(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize);
+    }
+}
+impl Default for Crit1r6 {
+    #[inline(always)]
+    fn default() -> Crit1r6 {
+        Crit1r6(0)
+    }
+}
+#[doc = "Redundant copy of CRIT1"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Crit1r7(pub u32);
+impl Crit1r7 {
+    #[inline(always)]
+    pub const fn crit1_r7(&self) -> u32 {
+        let val = (self.0 >> 0usize) & 0x00ff_ffff;
+        val as u32
+    }
+    #[inline(always)]
+    pub fn set_crit1_r7(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize);
+    }
+}
+impl Default for Crit1r7 {
+    #[inline(always)]
+    fn default() -> Crit1r7 {
+        Crit1r7(0)
+    }
+}
+#[doc = "Default boot version thermometer counter, bits 23:0 (RBIT-3)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct DefaultBootVersion0(pub u32);
+impl DefaultBootVersion0 {
+    #[inline(always)]
+    pub const fn default_boot_version0(&self) -> u32 {
+        let val = (self.0 >> 0usize) & 0x00ff_ffff;
+        val as u32
+    }
+    #[inline(always)]
+    pub fn set_default_boot_version0(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize);
+    }
+}
+impl Default for DefaultBootVersion0 {
+    #[inline(always)]
+    fn default() -> DefaultBootVersion0 {
+        DefaultBootVersion0(0)
+    }
+}
+#[doc = "Redundant copy of DEFAULT_BOOT_VERSION0"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct DefaultBootVersion0r1(pub u32);
+impl DefaultBootVersion0r1 {
+    #[inline(always)]
+    pub const fn default_boot_version0_r1(&self) -> u32 {
+        let val = (self.0 >> 0usize) & 0x00ff_ffff;
+        val as u32
+    }
+    #[inline(always)]
+    pub fn set_default_boot_version0_r1(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize);
+    }
+}
+impl Default for DefaultBootVersion0r1 {
+    #[inline(always)]
+    fn default() -> DefaultBootVersion0r1 {
+        DefaultBootVersion0r1(0)
+    }
+}
+#[doc = "Redundant copy of DEFAULT_BOOT_VERSION0"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct DefaultBootVersion0r2(pub u32);
+impl DefaultBootVersion0r2 {
+    #[inline(always)]
+    pub const fn default_boot_version0_r2(&self) -> u32 {
+        let val = (self.0 >> 0usize) & 0x00ff_ffff;
+        val as u32
+    }
+    #[inline(always)]
+    pub fn set_default_boot_version0_r2(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize);
+    }
+}
+impl Default for DefaultBootVersion0r2 {
+    #[inline(always)]
+    fn default() -> DefaultBootVersion0r2 {
+        DefaultBootVersion0r2(0)
+    }
+}
+#[doc = "Default boot version thermometer counter, bits 47:24 (RBIT-3)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct DefaultBootVersion1(pub u32);
+impl DefaultBootVersion1 {
+    #[inline(always)]
+    pub const fn default_boot_version1(&self) -> u32 {
+        let val = (self.0 >> 0usize) & 0x00ff_ffff;
+        val as u32
+    }
+    #[inline(always)]
+    pub fn set_default_boot_version1(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize);
+    }
+}
+impl Default for DefaultBootVersion1 {
+    #[inline(always)]
+    fn default() -> DefaultBootVersion1 {
+        DefaultBootVersion1(0)
+    }
+}
+#[doc = "Redundant copy of DEFAULT_BOOT_VERSION1"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct DefaultBootVersion1r1(pub u32);
+impl DefaultBootVersion1r1 {
+    #[inline(always)]
+    pub const fn default_boot_version1_r1(&self) -> u32 {
+        let val = (self.0 >> 0usize) & 0x00ff_ffff;
+        val as u32
+    }
+    #[inline(always)]
+    pub fn set_default_boot_version1_r1(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize);
+    }
+}
+impl Default for DefaultBootVersion1r1 {
+    #[inline(always)]
+    fn default() -> DefaultBootVersion1r1 {
+        DefaultBootVersion1r1(0)
+    }
+}
+#[doc = "Redundant copy of DEFAULT_BOOT_VERSION1"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct DefaultBootVersion1r2(pub u32);
+impl DefaultBootVersion1r2 {
+    #[inline(always)]
+    pub const fn default_boot_version1_r2(&self) -> u32 {
+        let val = (self.0 >> 0usize) & 0x00ff_ffff;
+        val as u32
+    }
+    #[inline(always)]
+    pub fn set_default_boot_version1_r2(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize);
+    }
+}
+impl Default for DefaultBootVersion1r2 {
+    #[inline(always)]
+    fn default() -> DefaultBootVersion1r2 {
+        DefaultBootVersion1r2(0)
+    }
+}
+#[doc = "Stores information about external flash device(s). (ECC) Assumed to be valid if BOOT_FLAGS0_FLASH_DEVINFO_ENABLE is set."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct FlashDevinfo(pub u32);
+impl FlashDevinfo {
+    #[doc = "Indicate a GPIO number to be used for the secondary flash chip select (CS1), which selects the external QSPI device mapped at system addresses 0x11000000 through 0x11ffffff. There is no such configuration for CS0, as the primary chip select has a dedicated pin. On RP2350 the permissible GPIO numbers are 0, 8, 19 and 47. Ignored if CS1_size is zero. If CS1_SIZE is nonzero, the bootrom will automatically configure this GPIO as a second chip select upon entering the flash boot path, or entering any other path that may use the QSPI flash interface, such as BOOTSEL mode (nsboot)."]
+    #[inline(always)]
+    pub const fn cs1_gpio(&self) -> u8 {
+        let val = (self.0 >> 0usize) & 0x3f;
+        val as u8
+    }
+    #[doc = "Indicate a GPIO number to be used for the secondary flash chip select (CS1), which selects the external QSPI device mapped at system addresses 0x11000000 through 0x11ffffff. There is no such configuration for CS0, as the primary chip select has a dedicated pin. On RP2350 the permissible GPIO numbers are 0, 8, 19 and 47. Ignored if CS1_size is zero. If CS1_SIZE is nonzero, the bootrom will automatically configure this GPIO as a second chip select upon entering the flash boot path, or entering any other path that may use the QSPI flash interface, such as BOOTSEL mode (nsboot)."]
+    #[inline(always)]
+    pub fn set_cs1_gpio(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x3f << 0usize)) | (((val as u32) & 0x3f) << 0usize);
+    }
+    #[doc = "If true, all attached devices are assumed to support (or ignore, in the case of PSRAM) a block erase command with a command prefix of D8h, an erase size of 64 kiB, and a 24-bit address. Almost all 25-series flash devices support this command. If set, the bootrom will use the D8h erase command where it is able, to accelerate bulk erase operations. This makes flash programming faster. When BOOT_FLAGS0_FLASH_DEVINFO_ENABLE is not set, this field defaults to false."]
+    #[inline(always)]
+    pub const fn d8h_erase_supported(&self) -> bool {
+        let val = (self.0 >> 7usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If true, all attached devices are assumed to support (or ignore, in the case of PSRAM) a block erase command with a command prefix of D8h, an erase size of 64 kiB, and a 24-bit address. Almost all 25-series flash devices support this command. If set, the bootrom will use the D8h erase command where it is able, to accelerate bulk erase operations. This makes flash programming faster. When BOOT_FLAGS0_FLASH_DEVINFO_ENABLE is not set, this field defaults to false."]
+    #[inline(always)]
+    pub fn set_d8h_erase_supported(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
+    }
+    #[doc = "The size of the flash/PSRAM device on chip select 0 (addressable at 0x10000000 through 0x10ffffff). A value of zero is decoded as a size of zero (no device). Nonzero values are decoded as 4kiB << CS0_SIZE. For example, four megabytes is encoded with a CS0_SIZE value of 10, and 16 megabytes is encoded with a CS0_SIZE value of 12. When BOOT_FLAGS0_FLASH_DEVINFO_ENABLE is not set, a default of 12 (16 MiB) is used."]
+    #[inline(always)]
+    pub const fn cs0_size(&self) -> super::vals::Cs0size {
+        let val = (self.0 >> 8usize) & 0x0f;
+        super::vals::Cs0size::from_bits(val as u8)
+    }
+    #[doc = "The size of the flash/PSRAM device on chip select 0 (addressable at 0x10000000 through 0x10ffffff). A value of zero is decoded as a size of zero (no device). Nonzero values are decoded as 4kiB << CS0_SIZE. For example, four megabytes is encoded with a CS0_SIZE value of 10, and 16 megabytes is encoded with a CS0_SIZE value of 12. When BOOT_FLAGS0_FLASH_DEVINFO_ENABLE is not set, a default of 12 (16 MiB) is used."]
+    #[inline(always)]
+    pub fn set_cs0_size(&mut self, val: super::vals::Cs0size) {
+        self.0 = (self.0 & !(0x0f << 8usize)) | (((val.to_bits() as u32) & 0x0f) << 8usize);
+    }
+    #[doc = "The size of the flash/PSRAM device on chip select 1 (addressable at 0x11000000 through 0x11ffffff). A value of zero is decoded as a size of zero (no device). Nonzero values are decoded as 4kiB << CS1_SIZE. For example, four megabytes is encoded with a CS1_SIZE value of 10, and 16 megabytes is encoded with a CS1_SIZE value of 12. When BOOT_FLAGS0_FLASH_DEVINFO_ENABLE is not set, a default of zero is used."]
+    #[inline(always)]
+    pub const fn cs1_size(&self) -> super::vals::Cs1size {
+        let val = (self.0 >> 12usize) & 0x0fff;
+        super::vals::Cs1size::from_bits(val as u16)
+    }
+    #[doc = "The size of the flash/PSRAM device on chip select 1 (addressable at 0x11000000 through 0x11ffffff). A value of zero is decoded as a size of zero (no device). Nonzero values are decoded as 4kiB << CS1_SIZE. For example, four megabytes is encoded with a CS1_SIZE value of 10, and 16 megabytes is encoded with a CS1_SIZE value of 12. When BOOT_FLAGS0_FLASH_DEVINFO_ENABLE is not set, a default of zero is used."]
+    #[inline(always)]
+    pub fn set_cs1_size(&mut self, val: super::vals::Cs1size) {
+        self.0 = (self.0 & !(0x0fff << 12usize)) | (((val.to_bits() as u32) & 0x0fff) << 12usize);
+    }
+}
+impl Default for FlashDevinfo {
+    #[inline(always)]
+    fn default() -> FlashDevinfo {
+        FlashDevinfo(0)
+    }
+}
+#[doc = "Gap between partition table slot 0 and slot 1 at the start of flash (the default size is 4096 bytes) (ECC) Enabled by the OVERRIDE_FLASH_PARTITION_SLOT_SIZE bit in BOOT_FLAGS, the size is 4096 * (value + 1)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct FlashPartitionSlotSize(pub u32);
+impl FlashPartitionSlotSize {
+    #[inline(always)]
+    pub const fn flash_partition_slot_size(&self) -> u32 {
+        let val = (self.0 >> 0usize) & 0x00ff_ffff;
+        val as u32
+    }
+    #[inline(always)]
+    pub fn set_flash_partition_slot_size(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize);
+    }
+}
+impl Default for FlashPartitionSlotSize {
+    #[inline(always)]
+    fn default() -> FlashPartitionSlotSize {
+        FlashPartitionSlotSize(0)
+    }
+}
+#[doc = "Lower 16 bits of CRC32 of OTP addresses 0x00 through 0x6b (polynomial 0x4c11db7, input reflected, output reflected, seed all-ones, final XOR all-ones) (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct InfoCrc0(pub u32);
+impl InfoCrc0 {
+    #[inline(always)]
+    pub const fn info_crc0(&self) -> u32 {
+        let val = (self.0 >> 0usize) & 0x00ff_ffff;
+        val as u32
+    }
+    #[inline(always)]
+    pub fn set_info_crc0(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize);
+    }
+}
+impl Default for InfoCrc0 {
+    #[inline(always)]
+    fn default() -> InfoCrc0 {
+        InfoCrc0(0)
+    }
+}
+#[doc = "Upper 16 bits of CRC32 of OTP addresses 0x00 through 0x6b (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct InfoCrc1(pub u32);
+impl InfoCrc1 {
+    #[inline(always)]
+    pub const fn info_crc1(&self) -> u32 {
+        let val = (self.0 >> 0usize) & 0x00ff_ffff;
+        val as u32
+    }
+    #[inline(always)]
+    pub fn set_info_crc1(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize);
+    }
+}
+impl Default for InfoCrc1 {
+    #[inline(always)]
+    fn default() -> InfoCrc1 {
+        InfoCrc1(0)
+    }
+}
+#[doc = "Bits 15:0 of OTP access key 1 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Key10(pub u32);
+impl Key10 {
+    #[inline(always)]
+    pub const fn key1_0(&self) -> u32 {
+        let val = (self.0 >> 0usize) & 0x00ff_ffff;
+        val as u32
+    }
+    #[inline(always)]
+    pub fn set_key1_0(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize);
+    }
+}
+impl Default for Key10 {
+    #[inline(always)]
+    fn default() -> Key10 {
+        Key10(0)
+    }
+}
+#[doc = "Bits 31:16 of OTP access key 1 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Key11(pub u32);
+impl Key11 {
+    #[inline(always)]
+    pub const fn key1_1(&self) -> u32 {
+        let val = (self.0 >> 0usize) & 0x00ff_ffff;
+        val as u32
+    }
+    #[inline(always)]
+    pub fn set_key1_1(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize);
+    }
+}
+impl Default for Key11 {
+    #[inline(always)]
+    fn default() -> Key11 {
+        Key11(0)
+    }
+}
+#[doc = "Bits 47:32 of OTP access key 1 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Key12(pub u32);
+impl Key12 {
+    #[inline(always)]
+    pub const fn key1_2(&self) -> u32 {
+        let val = (self.0 >> 0usize) & 0x00ff_ffff;
+        val as u32
+    }
+    #[inline(always)]
+    pub fn set_key1_2(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize);
+    }
+}
+impl Default for Key12 {
+    #[inline(always)]
+    fn default() -> Key12 {
+        Key12(0)
+    }
+}
+#[doc = "Bits 63:48 of OTP access key 1 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Key13(pub u32);
+impl Key13 {
+    #[inline(always)]
+    pub const fn key1_3(&self) -> u32 {
+        let val = (self.0 >> 0usize) & 0x00ff_ffff;
+        val as u32
+    }
+    #[inline(always)]
+    pub fn set_key1_3(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize);
+    }
+}
+impl Default for Key13 {
+    #[inline(always)]
+    fn default() -> Key13 {
+        Key13(0)
+    }
+}
+#[doc = "Bits 79:64 of OTP access key 1 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Key14(pub u32);
+impl Key14 {
+    #[inline(always)]
+    pub const fn key1_4(&self) -> u32 {
+        let val = (self.0 >> 0usize) & 0x00ff_ffff;
+        val as u32
+    }
+    #[inline(always)]
+    pub fn set_key1_4(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize);
+    }
+}
+impl Default for Key14 {
+    #[inline(always)]
+    fn default() -> Key14 {
+        Key14(0)
+    }
+}
+#[doc = "Bits 95:80 of OTP access key 1 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Key15(pub u32);
+impl Key15 {
+    #[inline(always)]
+    pub const fn key1_5(&self) -> u32 {
+        let val = (self.0 >> 0usize) & 0x00ff_ffff;
+        val as u32
+    }
+    #[inline(always)]
+    pub fn set_key1_5(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize);
+    }
+}
+impl Default for Key15 {
+    #[inline(always)]
+    fn default() -> Key15 {
+        Key15(0)
+    }
+}
+#[doc = "Bits 111:96 of OTP access key 1 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Key16(pub u32);
+impl Key16 {
+    #[inline(always)]
+    pub const fn key1_6(&self) -> u32 {
+        let val = (self.0 >> 0usize) & 0x00ff_ffff;
+        val as u32
+    }
+    #[inline(always)]
+    pub fn set_key1_6(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize);
+    }
+}
+impl Default for Key16 {
+    #[inline(always)]
+    fn default() -> Key16 {
+        Key16(0)
+    }
+}
+#[doc = "Bits 127:112 of OTP access key 1 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Key17(pub u32);
+impl Key17 {
+    #[inline(always)]
+    pub const fn key1_7(&self) -> u32 {
+        let val = (self.0 >> 0usize) & 0x00ff_ffff;
+        val as u32
+    }
+    #[inline(always)]
+    pub fn set_key1_7(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize);
+    }
+}
+impl Default for Key17 {
+    #[inline(always)]
+    fn default() -> Key17 {
+        Key17(0)
+    }
+}
+#[doc = "Valid flag for key 1. Once the valid flag is set, the key can no longer be read or written, and becomes a valid fixed key for protecting OTP pages."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Key1valid(pub u32);
+impl Key1valid {
+    #[inline(always)]
+    pub const fn valid(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_valid(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[doc = "Redundant copy of VALID, with 3-way majority vote"]
+    #[inline(always)]
+    pub const fn valid_r1(&self) -> bool {
+        let val = (self.0 >> 8usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Redundant copy of VALID, with 3-way majority vote"]
+    #[inline(always)]
+    pub fn set_valid_r1(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
+    }
+    #[doc = "Redundant copy of VALID, with 3-way majority vote"]
+    #[inline(always)]
+    pub const fn valid_r2(&self) -> bool {
+        let val = (self.0 >> 16usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Redundant copy of VALID, with 3-way majority vote"]
+    #[inline(always)]
+    pub fn set_valid_r2(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
+    }
+}
+impl Default for Key1valid {
+    #[inline(always)]
+    fn default() -> Key1valid {
+        Key1valid(0)
+    }
+}
+#[doc = "Bits 15:0 of OTP access key 2 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Key20(pub u32);
+impl Key20 {
+    #[inline(always)]
+    pub const fn key2_0(&self) -> u32 {
+        let val = (self.0 >> 0usize) & 0x00ff_ffff;
+        val as u32
+    }
+    #[inline(always)]
+    pub fn set_key2_0(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize);
+    }
+}
+impl Default for Key20 {
+    #[inline(always)]
+    fn default() -> Key20 {
+        Key20(0)
+    }
+}
+#[doc = "Bits 31:16 of OTP access key 2 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Key21(pub u32);
+impl Key21 {
+    #[inline(always)]
+    pub const fn key2_1(&self) -> u32 {
+        let val = (self.0 >> 0usize) & 0x00ff_ffff;
+        val as u32
+    }
+    #[inline(always)]
+    pub fn set_key2_1(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize);
+    }
+}
+impl Default for Key21 {
+    #[inline(always)]
+    fn default() -> Key21 {
+        Key21(0)
+    }
+}
+#[doc = "Bits 47:32 of OTP access key 2 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Key22(pub u32);
+impl Key22 {
+    #[inline(always)]
+    pub const fn key2_2(&self) -> u32 {
+        let val = (self.0 >> 0usize) & 0x00ff_ffff;
+        val as u32
+    }
+    #[inline(always)]
+    pub fn set_key2_2(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize);
+    }
+}
+impl Default for Key22 {
+    #[inline(always)]
+    fn default() -> Key22 {
+        Key22(0)
+    }
+}
+#[doc = "Bits 63:48 of OTP access key 2 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Key23(pub u32);
+impl Key23 {
+    #[inline(always)]
+    pub const fn key2_3(&self) -> u32 {
+        let val = (self.0 >> 0usize) & 0x00ff_ffff;
+        val as u32
+    }
+    #[inline(always)]
+    pub fn set_key2_3(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize);
+    }
+}
+impl Default for Key23 {
+    #[inline(always)]
+    fn default() -> Key23 {
+        Key23(0)
+    }
+}
+#[doc = "Bits 79:64 of OTP access key 2 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Key24(pub u32);
+impl Key24 {
+    #[inline(always)]
+    pub const fn key2_4(&self) -> u32 {
+        let val = (self.0 >> 0usize) & 0x00ff_ffff;
+        val as u32
+    }
+    #[inline(always)]
+    pub fn set_key2_4(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize);
+    }
+}
+impl Default for Key24 {
+    #[inline(always)]
+    fn default() -> Key24 {
+        Key24(0)
+    }
+}
+#[doc = "Bits 95:80 of OTP access key 2 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Key25(pub u32);
+impl Key25 {
+    #[inline(always)]
+    pub const fn key2_5(&self) -> u32 {
+        let val = (self.0 >> 0usize) & 0x00ff_ffff;
+        val as u32
+    }
+    #[inline(always)]
+    pub fn set_key2_5(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize);
+    }
+}
+impl Default for Key25 {
+    #[inline(always)]
+    fn default() -> Key25 {
+        Key25(0)
+    }
+}
+#[doc = "Bits 111:96 of OTP access key 2 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Key26(pub u32);
+impl Key26 {
+    #[inline(always)]
+    pub const fn key2_6(&self) -> u32 {
+        let val = (self.0 >> 0usize) & 0x00ff_ffff;
+        val as u32
+    }
+    #[inline(always)]
+    pub fn set_key2_6(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize);
+    }
+}
+impl Default for Key26 {
+    #[inline(always)]
+    fn default() -> Key26 {
+        Key26(0)
+    }
+}
+#[doc = "Bits 127:112 of OTP access key 2 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Key27(pub u32);
+impl Key27 {
+    #[inline(always)]
+    pub const fn key2_7(&self) -> u32 {
+        let val = (self.0 >> 0usize) & 0x00ff_ffff;
+        val as u32
+    }
+    #[inline(always)]
+    pub fn set_key2_7(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize);
+    }
+}
+impl Default for Key27 {
+    #[inline(always)]
+    fn default() -> Key27 {
+        Key27(0)
+    }
+}
+#[doc = "Valid flag for key 2. Once the valid flag is set, the key can no longer be read or written, and becomes a valid fixed key for protecting OTP pages."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Key2valid(pub u32);
+impl Key2valid {
+    #[inline(always)]
+    pub const fn valid(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_valid(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[doc = "Redundant copy of VALID, with 3-way majority vote"]
+    #[inline(always)]
+    pub const fn valid_r1(&self) -> bool {
+        let val = (self.0 >> 8usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Redundant copy of VALID, with 3-way majority vote"]
+    #[inline(always)]
+    pub fn set_valid_r1(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
+    }
+    #[doc = "Redundant copy of VALID, with 3-way majority vote"]
+    #[inline(always)]
+    pub const fn valid_r2(&self) -> bool {
+        let val = (self.0 >> 16usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Redundant copy of VALID, with 3-way majority vote"]
+    #[inline(always)]
+    pub fn set_valid_r2(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
+    }
+}
+impl Default for Key2valid {
+    #[inline(always)]
+    fn default() -> Key2valid {
+        Key2valid(0)
+    }
+}
+#[doc = "Bits 15:0 of OTP access key 3 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Key30(pub u32);
+impl Key30 {
+    #[inline(always)]
+    pub const fn key3_0(&self) -> u32 {
+        let val = (self.0 >> 0usize) & 0x00ff_ffff;
+        val as u32
+    }
+    #[inline(always)]
+    pub fn set_key3_0(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize);
+    }
+}
+impl Default for Key30 {
+    #[inline(always)]
+    fn default() -> Key30 {
+        Key30(0)
+    }
+}
+#[doc = "Bits 31:16 of OTP access key 3 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Key31(pub u32);
+impl Key31 {
+    #[inline(always)]
+    pub const fn key3_1(&self) -> u32 {
+        let val = (self.0 >> 0usize) & 0x00ff_ffff;
+        val as u32
+    }
+    #[inline(always)]
+    pub fn set_key3_1(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize);
+    }
+}
+impl Default for Key31 {
+    #[inline(always)]
+    fn default() -> Key31 {
+        Key31(0)
+    }
+}
+#[doc = "Bits 47:32 of OTP access key 3 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Key32(pub u32);
+impl Key32 {
+    #[inline(always)]
+    pub const fn key3_2(&self) -> u32 {
+        let val = (self.0 >> 0usize) & 0x00ff_ffff;
+        val as u32
+    }
+    #[inline(always)]
+    pub fn set_key3_2(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize);
+    }
+}
+impl Default for Key32 {
+    #[inline(always)]
+    fn default() -> Key32 {
+        Key32(0)
+    }
+}
+#[doc = "Bits 63:48 of OTP access key 3 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Key33(pub u32);
+impl Key33 {
+    #[inline(always)]
+    pub const fn key3_3(&self) -> u32 {
+        let val = (self.0 >> 0usize) & 0x00ff_ffff;
+        val as u32
+    }
+    #[inline(always)]
+    pub fn set_key3_3(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize);
+    }
+}
+impl Default for Key33 {
+    #[inline(always)]
+    fn default() -> Key33 {
+        Key33(0)
+    }
+}
+#[doc = "Bits 79:64 of OTP access key 3 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Key34(pub u32);
+impl Key34 {
+    #[inline(always)]
+    pub const fn key3_4(&self) -> u32 {
+        let val = (self.0 >> 0usize) & 0x00ff_ffff;
+        val as u32
+    }
+    #[inline(always)]
+    pub fn set_key3_4(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize);
+    }
+}
+impl Default for Key34 {
+    #[inline(always)]
+    fn default() -> Key34 {
+        Key34(0)
+    }
+}
+#[doc = "Bits 95:80 of OTP access key 3 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Key35(pub u32);
+impl Key35 {
+    #[inline(always)]
+    pub const fn key3_5(&self) -> u32 {
+        let val = (self.0 >> 0usize) & 0x00ff_ffff;
+        val as u32
+    }
+    #[inline(always)]
+    pub fn set_key3_5(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize);
+    }
+}
+impl Default for Key35 {
+    #[inline(always)]
+    fn default() -> Key35 {
+        Key35(0)
+    }
+}
+#[doc = "Bits 111:96 of OTP access key 3 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Key36(pub u32);
+impl Key36 {
+    #[inline(always)]
+    pub const fn key3_6(&self) -> u32 {
+        let val = (self.0 >> 0usize) & 0x00ff_ffff;
+        val as u32
+    }
+    #[inline(always)]
+    pub fn set_key3_6(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize);
+    }
+}
+impl Default for Key36 {
+    #[inline(always)]
+    fn default() -> Key36 {
+        Key36(0)
+    }
+}
+#[doc = "Bits 127:112 of OTP access key 3 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Key37(pub u32);
+impl Key37 {
+    #[inline(always)]
+    pub const fn key3_7(&self) -> u32 {
+        let val = (self.0 >> 0usize) & 0x00ff_ffff;
+        val as u32
+    }
+    #[inline(always)]
+    pub fn set_key3_7(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize);
+    }
+}
+impl Default for Key37 {
+    #[inline(always)]
+    fn default() -> Key37 {
+        Key37(0)
+    }
+}
+#[doc = "Valid flag for key 3. Once the valid flag is set, the key can no longer be read or written, and becomes a valid fixed key for protecting OTP pages."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Key3valid(pub u32);
+impl Key3valid {
+    #[inline(always)]
+    pub const fn valid(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_valid(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[doc = "Redundant copy of VALID, with 3-way majority vote"]
+    #[inline(always)]
+    pub const fn valid_r1(&self) -> bool {
+        let val = (self.0 >> 8usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Redundant copy of VALID, with 3-way majority vote"]
+    #[inline(always)]
+    pub fn set_valid_r1(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
+    }
+    #[doc = "Redundant copy of VALID, with 3-way majority vote"]
+    #[inline(always)]
+    pub const fn valid_r2(&self) -> bool {
+        let val = (self.0 >> 16usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Redundant copy of VALID, with 3-way majority vote"]
+    #[inline(always)]
+    pub fn set_valid_r2(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
+    }
+}
+impl Default for Key3valid {
+    #[inline(always)]
+    fn default() -> Key3valid {
+        Key3valid(0)
+    }
+}
+#[doc = "Bits 15:0 of OTP access key 4 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Key40(pub u32);
+impl Key40 {
+    #[inline(always)]
+    pub const fn key4_0(&self) -> u32 {
+        let val = (self.0 >> 0usize) & 0x00ff_ffff;
+        val as u32
+    }
+    #[inline(always)]
+    pub fn set_key4_0(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize);
+    }
+}
+impl Default for Key40 {
+    #[inline(always)]
+    fn default() -> Key40 {
+        Key40(0)
+    }
+}
+#[doc = "Bits 31:16 of OTP access key 4 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Key41(pub u32);
+impl Key41 {
+    #[inline(always)]
+    pub const fn key4_1(&self) -> u32 {
+        let val = (self.0 >> 0usize) & 0x00ff_ffff;
+        val as u32
+    }
+    #[inline(always)]
+    pub fn set_key4_1(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize);
+    }
+}
+impl Default for Key41 {
+    #[inline(always)]
+    fn default() -> Key41 {
+        Key41(0)
+    }
+}
+#[doc = "Bits 47:32 of OTP access key 4 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Key42(pub u32);
+impl Key42 {
+    #[inline(always)]
+    pub const fn key4_2(&self) -> u32 {
+        let val = (self.0 >> 0usize) & 0x00ff_ffff;
+        val as u32
+    }
+    #[inline(always)]
+    pub fn set_key4_2(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize);
+    }
+}
+impl Default for Key42 {
+    #[inline(always)]
+    fn default() -> Key42 {
+        Key42(0)
+    }
+}
+#[doc = "Bits 63:48 of OTP access key 4 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Key43(pub u32);
+impl Key43 {
+    #[inline(always)]
+    pub const fn key4_3(&self) -> u32 {
+        let val = (self.0 >> 0usize) & 0x00ff_ffff;
+        val as u32
+    }
+    #[inline(always)]
+    pub fn set_key4_3(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize);
+    }
+}
+impl Default for Key43 {
+    #[inline(always)]
+    fn default() -> Key43 {
+        Key43(0)
+    }
+}
+#[doc = "Bits 79:64 of OTP access key 4 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Key44(pub u32);
+impl Key44 {
+    #[inline(always)]
+    pub const fn key4_4(&self) -> u32 {
+        let val = (self.0 >> 0usize) & 0x00ff_ffff;
+        val as u32
+    }
+    #[inline(always)]
+    pub fn set_key4_4(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize);
+    }
+}
+impl Default for Key44 {
+    #[inline(always)]
+    fn default() -> Key44 {
+        Key44(0)
+    }
+}
+#[doc = "Bits 95:80 of OTP access key 4 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Key45(pub u32);
+impl Key45 {
+    #[inline(always)]
+    pub const fn key4_5(&self) -> u32 {
+        let val = (self.0 >> 0usize) & 0x00ff_ffff;
+        val as u32
+    }
+    #[inline(always)]
+    pub fn set_key4_5(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize);
+    }
+}
+impl Default for Key45 {
+    #[inline(always)]
+    fn default() -> Key45 {
+        Key45(0)
+    }
+}
+#[doc = "Bits 111:96 of OTP access key 4 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Key46(pub u32);
+impl Key46 {
+    #[inline(always)]
+    pub const fn key4_6(&self) -> u32 {
+        let val = (self.0 >> 0usize) & 0x00ff_ffff;
+        val as u32
+    }
+    #[inline(always)]
+    pub fn set_key4_6(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize);
+    }
+}
+impl Default for Key46 {
+    #[inline(always)]
+    fn default() -> Key46 {
+        Key46(0)
+    }
+}
+#[doc = "Bits 127:112 of OTP access key 4 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Key47(pub u32);
+impl Key47 {
+    #[inline(always)]
+    pub const fn key4_7(&self) -> u32 {
+        let val = (self.0 >> 0usize) & 0x00ff_ffff;
+        val as u32
+    }
+    #[inline(always)]
+    pub fn set_key4_7(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize);
+    }
+}
+impl Default for Key47 {
+    #[inline(always)]
+    fn default() -> Key47 {
+        Key47(0)
+    }
+}
+#[doc = "Valid flag for key 4. Once the valid flag is set, the key can no longer be read or written, and becomes a valid fixed key for protecting OTP pages."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Key4valid(pub u32);
+impl Key4valid {
+    #[inline(always)]
+    pub const fn valid(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_valid(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[doc = "Redundant copy of VALID, with 3-way majority vote"]
+    #[inline(always)]
+    pub const fn valid_r1(&self) -> bool {
+        let val = (self.0 >> 8usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Redundant copy of VALID, with 3-way majority vote"]
+    #[inline(always)]
+    pub fn set_valid_r1(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
+    }
+    #[doc = "Redundant copy of VALID, with 3-way majority vote"]
+    #[inline(always)]
+    pub const fn valid_r2(&self) -> bool {
+        let val = (self.0 >> 16usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Redundant copy of VALID, with 3-way majority vote"]
+    #[inline(always)]
+    pub fn set_valid_r2(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
+    }
+}
+impl Default for Key4valid {
+    #[inline(always)]
+    fn default() -> Key4valid {
+        Key4valid(0)
+    }
+}
+#[doc = "Bits 15:0 of OTP access key 5 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Key50(pub u32);
+impl Key50 {
+    #[inline(always)]
+    pub const fn key5_0(&self) -> u32 {
+        let val = (self.0 >> 0usize) & 0x00ff_ffff;
+        val as u32
+    }
+    #[inline(always)]
+    pub fn set_key5_0(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize);
+    }
+}
+impl Default for Key50 {
+    #[inline(always)]
+    fn default() -> Key50 {
+        Key50(0)
+    }
+}
+#[doc = "Bits 31:16 of OTP access key 5 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Key51(pub u32);
+impl Key51 {
+    #[inline(always)]
+    pub const fn key5_1(&self) -> u32 {
+        let val = (self.0 >> 0usize) & 0x00ff_ffff;
+        val as u32
+    }
+    #[inline(always)]
+    pub fn set_key5_1(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize);
+    }
+}
+impl Default for Key51 {
+    #[inline(always)]
+    fn default() -> Key51 {
+        Key51(0)
+    }
+}
+#[doc = "Bits 47:32 of OTP access key 5 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Key52(pub u32);
+impl Key52 {
+    #[inline(always)]
+    pub const fn key5_2(&self) -> u32 {
+        let val = (self.0 >> 0usize) & 0x00ff_ffff;
+        val as u32
+    }
+    #[inline(always)]
+    pub fn set_key5_2(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize);
+    }
+}
+impl Default for Key52 {
+    #[inline(always)]
+    fn default() -> Key52 {
+        Key52(0)
+    }
+}
+#[doc = "Bits 63:48 of OTP access key 5 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Key53(pub u32);
+impl Key53 {
+    #[inline(always)]
+    pub const fn key5_3(&self) -> u32 {
+        let val = (self.0 >> 0usize) & 0x00ff_ffff;
+        val as u32
+    }
+    #[inline(always)]
+    pub fn set_key5_3(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize);
+    }
+}
+impl Default for Key53 {
+    #[inline(always)]
+    fn default() -> Key53 {
+        Key53(0)
+    }
+}
+#[doc = "Bits 79:64 of OTP access key 5 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Key54(pub u32);
+impl Key54 {
+    #[inline(always)]
+    pub const fn key5_4(&self) -> u32 {
+        let val = (self.0 >> 0usize) & 0x00ff_ffff;
+        val as u32
+    }
+    #[inline(always)]
+    pub fn set_key5_4(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize);
+    }
+}
+impl Default for Key54 {
+    #[inline(always)]
+    fn default() -> Key54 {
+        Key54(0)
+    }
+}
+#[doc = "Bits 95:80 of OTP access key 5 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Key55(pub u32);
+impl Key55 {
+    #[inline(always)]
+    pub const fn key5_5(&self) -> u32 {
+        let val = (self.0 >> 0usize) & 0x00ff_ffff;
+        val as u32
+    }
+    #[inline(always)]
+    pub fn set_key5_5(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize);
+    }
+}
+impl Default for Key55 {
+    #[inline(always)]
+    fn default() -> Key55 {
+        Key55(0)
+    }
+}
+#[doc = "Bits 111:96 of OTP access key 5 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Key56(pub u32);
+impl Key56 {
+    #[inline(always)]
+    pub const fn key5_6(&self) -> u32 {
+        let val = (self.0 >> 0usize) & 0x00ff_ffff;
+        val as u32
+    }
+    #[inline(always)]
+    pub fn set_key5_6(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize);
+    }
+}
+impl Default for Key56 {
+    #[inline(always)]
+    fn default() -> Key56 {
+        Key56(0)
+    }
+}
+#[doc = "Bits 127:112 of OTP access key 5 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Key57(pub u32);
+impl Key57 {
+    #[inline(always)]
+    pub const fn key5_7(&self) -> u32 {
+        let val = (self.0 >> 0usize) & 0x00ff_ffff;
+        val as u32
+    }
+    #[inline(always)]
+    pub fn set_key5_7(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize);
+    }
+}
+impl Default for Key57 {
+    #[inline(always)]
+    fn default() -> Key57 {
+        Key57(0)
+    }
+}
+#[doc = "Valid flag for key 5. Once the valid flag is set, the key can no longer be read or written, and becomes a valid fixed key for protecting OTP pages."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Key5valid(pub u32);
+impl Key5valid {
+    #[inline(always)]
+    pub const fn valid(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_valid(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[doc = "Redundant copy of VALID, with 3-way majority vote"]
+    #[inline(always)]
+    pub const fn valid_r1(&self) -> bool {
+        let val = (self.0 >> 8usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Redundant copy of VALID, with 3-way majority vote"]
+    #[inline(always)]
+    pub fn set_valid_r1(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
+    }
+    #[doc = "Redundant copy of VALID, with 3-way majority vote"]
+    #[inline(always)]
+    pub const fn valid_r2(&self) -> bool {
+        let val = (self.0 >> 16usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Redundant copy of VALID, with 3-way majority vote"]
+    #[inline(always)]
+    pub fn set_valid_r2(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
+    }
+}
+impl Default for Key5valid {
+    #[inline(always)]
+    fn default() -> Key5valid {
+        Key5valid(0)
+    }
+}
+#[doc = "Bits 15:0 of OTP access key 6 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Key60(pub u32);
+impl Key60 {
+    #[inline(always)]
+    pub const fn key6_0(&self) -> u32 {
+        let val = (self.0 >> 0usize) & 0x00ff_ffff;
+        val as u32
+    }
+    #[inline(always)]
+    pub fn set_key6_0(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize);
+    }
+}
+impl Default for Key60 {
+    #[inline(always)]
+    fn default() -> Key60 {
+        Key60(0)
+    }
+}
+#[doc = "Bits 31:16 of OTP access key 6 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Key61(pub u32);
+impl Key61 {
+    #[inline(always)]
+    pub const fn key6_1(&self) -> u32 {
+        let val = (self.0 >> 0usize) & 0x00ff_ffff;
+        val as u32
+    }
+    #[inline(always)]
+    pub fn set_key6_1(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize);
+    }
+}
+impl Default for Key61 {
+    #[inline(always)]
+    fn default() -> Key61 {
+        Key61(0)
+    }
+}
+#[doc = "Bits 47:32 of OTP access key 6 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Key62(pub u32);
+impl Key62 {
+    #[inline(always)]
+    pub const fn key6_2(&self) -> u32 {
+        let val = (self.0 >> 0usize) & 0x00ff_ffff;
+        val as u32
+    }
+    #[inline(always)]
+    pub fn set_key6_2(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize);
+    }
+}
+impl Default for Key62 {
+    #[inline(always)]
+    fn default() -> Key62 {
+        Key62(0)
+    }
+}
+#[doc = "Bits 63:48 of OTP access key 6 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Key63(pub u32);
+impl Key63 {
+    #[inline(always)]
+    pub const fn key6_3(&self) -> u32 {
+        let val = (self.0 >> 0usize) & 0x00ff_ffff;
+        val as u32
+    }
+    #[inline(always)]
+    pub fn set_key6_3(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize);
+    }
+}
+impl Default for Key63 {
+    #[inline(always)]
+    fn default() -> Key63 {
+        Key63(0)
+    }
+}
+#[doc = "Bits 79:64 of OTP access key 6 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Key64(pub u32);
+impl Key64 {
+    #[inline(always)]
+    pub const fn key6_4(&self) -> u32 {
+        let val = (self.0 >> 0usize) & 0x00ff_ffff;
+        val as u32
+    }
+    #[inline(always)]
+    pub fn set_key6_4(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize);
+    }
+}
+impl Default for Key64 {
+    #[inline(always)]
+    fn default() -> Key64 {
+        Key64(0)
+    }
+}
+#[doc = "Bits 95:80 of OTP access key 6 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Key65(pub u32);
+impl Key65 {
+    #[inline(always)]
+    pub const fn key6_5(&self) -> u32 {
+        let val = (self.0 >> 0usize) & 0x00ff_ffff;
+        val as u32
+    }
+    #[inline(always)]
+    pub fn set_key6_5(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize);
+    }
+}
+impl Default for Key65 {
+    #[inline(always)]
+    fn default() -> Key65 {
+        Key65(0)
+    }
+}
+#[doc = "Bits 111:96 of OTP access key 6 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Key66(pub u32);
+impl Key66 {
+    #[inline(always)]
+    pub const fn key6_6(&self) -> u32 {
+        let val = (self.0 >> 0usize) & 0x00ff_ffff;
+        val as u32
+    }
+    #[inline(always)]
+    pub fn set_key6_6(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize);
+    }
+}
+impl Default for Key66 {
+    #[inline(always)]
+    fn default() -> Key66 {
+        Key66(0)
+    }
+}
+#[doc = "Bits 127:112 of OTP access key 6 (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Key67(pub u32);
+impl Key67 {
+    #[inline(always)]
+    pub const fn key6_7(&self) -> u32 {
+        let val = (self.0 >> 0usize) & 0x00ff_ffff;
+        val as u32
+    }
+    #[inline(always)]
+    pub fn set_key6_7(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize);
+    }
+}
+impl Default for Key67 {
+    #[inline(always)]
+    fn default() -> Key67 {
+        Key67(0)
+    }
+}
+#[doc = "Valid flag for key 6. Once the valid flag is set, the key can no longer be read or written, and becomes a valid fixed key for protecting OTP pages."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Key6valid(pub u32);
+impl Key6valid {
+    #[inline(always)]
+    pub const fn valid(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_valid(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[doc = "Redundant copy of VALID, with 3-way majority vote"]
+    #[inline(always)]
+    pub const fn valid_r1(&self) -> bool {
+        let val = (self.0 >> 8usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Redundant copy of VALID, with 3-way majority vote"]
+    #[inline(always)]
+    pub fn set_valid_r1(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
+    }
+    #[doc = "Redundant copy of VALID, with 3-way majority vote"]
+    #[inline(always)]
+    pub const fn valid_r2(&self) -> bool {
+        let val = (self.0 >> 16usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Redundant copy of VALID, with 3-way majority vote"]
+    #[inline(always)]
+    pub fn set_valid_r2(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
+    }
+}
+impl Default for Key6valid {
+    #[inline(always)]
+    fn default() -> Key6valid {
+        Key6valid(0)
+    }
+}
+#[doc = "Low-power oscillator frequency in Hz, measured during manufacturing (ECC) This is measured at 1.1V, at room temperature, with the LPOSC trim register in its reset state."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct LposcCalib(pub u32);
+impl LposcCalib {
+    #[inline(always)]
+    pub const fn lposc_calib(&self) -> u32 {
+        let val = (self.0 >> 0usize) & 0x00ff_ffff;
+        val as u32
+    }
+    #[inline(always)]
+    pub fn set_lposc_calib(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize);
+    }
+}
+impl Default for LposcCalib {
+    #[inline(always)]
+    fn default() -> LposcCalib {
+        LposcCalib(0)
+    }
+}
+#[doc = "The number of main user GPIOs (bank 0). Should read 48 in the QFN80 package, and 30 in the QFN60 package. (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct NumGpios(pub u32);
+impl NumGpios {
+    #[inline(always)]
+    pub const fn num_gpios(&self) -> u32 {
+        let val = (self.0 >> 0usize) & 0x00ff_ffff;
+        val as u32
+    }
+    #[inline(always)]
+    pub fn set_num_gpios(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize);
+    }
+}
+impl Default for NumGpios {
+    #[inline(always)]
+    fn default() -> NumGpios {
+        NumGpios(0)
+    }
+}
+#[doc = "Bits 15:0 of the OTP boot image load destination (and entry point). (ECC) This must be a location in main SRAM (main SRAM is addresses 0x20000000 through 0x20082000) and must be word-aligned."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct OtpbootDst0(pub u32);
+impl OtpbootDst0 {
+    #[inline(always)]
+    pub const fn otpboot_dst0(&self) -> u32 {
+        let val = (self.0 >> 0usize) & 0x00ff_ffff;
+        val as u32
+    }
+    #[inline(always)]
+    pub fn set_otpboot_dst0(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize);
+    }
+}
+impl Default for OtpbootDst0 {
+    #[inline(always)]
+    fn default() -> OtpbootDst0 {
+        OtpbootDst0(0)
+    }
+}
+#[doc = "Bits 31:16 of the OTP boot image load destination (and entry point). (ECC) This must be a location in main SRAM (main SRAM is addresses 0x20000000 through 0x20082000) and must be word-aligned."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct OtpbootDst1(pub u32);
+impl OtpbootDst1 {
+    #[inline(always)]
+    pub const fn otpboot_dst1(&self) -> u32 {
+        let val = (self.0 >> 0usize) & 0x00ff_ffff;
+        val as u32
+    }
+    #[inline(always)]
+    pub fn set_otpboot_dst1(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize);
+    }
+}
+impl Default for OtpbootDst1 {
+    #[inline(always)]
+    fn default() -> OtpbootDst1 {
+        OtpbootDst1(0)
+    }
+}
+#[doc = "Length in rows of the OTP boot image. (ECC) OTPBOOT_LEN must be even. The total image size must be a multiple of 4 bytes (32 bits)."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct OtpbootLen(pub u32);
+impl OtpbootLen {
+    #[inline(always)]
+    pub const fn otpboot_len(&self) -> u32 {
+        let val = (self.0 >> 0usize) & 0x00ff_ffff;
+        val as u32
+    }
+    #[inline(always)]
+    pub fn set_otpboot_len(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize);
+    }
+}
+impl Default for OtpbootLen {
+    #[inline(always)]
+    fn default() -> OtpbootLen {
+        OtpbootLen(0)
+    }
+}
+#[doc = "OTP start row for the OTP boot image. (ECC) If OTP boot is enabled, the bootrom will load from this location into SRAM and then directly enter the loaded image. Note that the image must be signed if SECURE_BOOT_ENABLE is set. The image itself is assumed to be ECC-protected. This must be an even number. Equivalently, the OTP boot image must start at a word-aligned location in the ECC read data address window."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct OtpbootSrc(pub u32);
+impl OtpbootSrc {
+    #[inline(always)]
+    pub const fn otpboot_src(&self) -> u32 {
+        let val = (self.0 >> 0usize) & 0x00ff_ffff;
+        val as u32
+    }
+    #[inline(always)]
+    pub fn set_otpboot_src(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize);
+    }
+}
+impl Default for OtpbootSrc {
+    #[inline(always)]
+    fn default() -> OtpbootSrc {
+        OtpbootSrc(0)
+    }
+}
+#[doc = "Lock configuration LSBs for page 0 (rows 0x0 through 0x3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Page0lock0(pub u32);
+impl Page0lock0 {
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub const fn key_w(&self) -> u8 {
+        let val = (self.0 >> 0usize) & 0x07;
+        val as u8
+    }
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub fn set_key_w(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x07 << 0usize)) | (((val as u32) & 0x07) << 0usize);
+    }
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub const fn key_r(&self) -> u8 {
+        let val = (self.0 >> 3usize) & 0x07;
+        val as u8
+    }
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub fn set_key_r(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x07 << 3usize)) | (((val as u32) & 0x07) << 3usize);
+    }
+    #[doc = "State when at least one key is registered for this page and no matching key has been entered."]
+    #[inline(always)]
+    pub const fn no_key_state(&self) -> super::vals::Page0lock0noKeyState {
+        let val = (self.0 >> 6usize) & 0x01;
+        super::vals::Page0lock0noKeyState::from_bits(val as u8)
+    }
+    #[doc = "State when at least one key is registered for this page and no matching key has been entered."]
+    #[inline(always)]
+    pub fn set_no_key_state(&mut self, val: super::vals::Page0lock0noKeyState) {
+        self.0 = (self.0 & !(0x01 << 6usize)) | (((val.to_bits() as u32) & 0x01) << 6usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r1(&self) -> u8 {
+        let val = (self.0 >> 8usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r1(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r2(&self) -> u8 {
+        let val = (self.0 >> 16usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r2(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize);
+    }
+}
+impl Default for Page0lock0 {
+    #[inline(always)]
+    fn default() -> Page0lock0 {
+        Page0lock0(0)
+    }
+}
+#[doc = "Lock configuration MSBs for page 0 (rows 0x0 through 0x3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Page0lock1(pub u32);
+impl Page0lock1 {
+    #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."]
+    #[inline(always)]
+    pub const fn lock_s(&self) -> super::vals::Page0lock1lockS {
+        let val = (self.0 >> 0usize) & 0x03;
+        super::vals::Page0lock1lockS::from_bits(val as u8)
+    }
+    #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."]
+    #[inline(always)]
+    pub fn set_lock_s(&mut self, val: super::vals::Page0lock1lockS) {
+        self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize);
+    }
+    #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."]
+    #[inline(always)]
+    pub const fn lock_ns(&self) -> super::vals::Page0lock1lockNs {
+        let val = (self.0 >> 2usize) & 0x03;
+        super::vals::Page0lock1lockNs::from_bits(val as u8)
+    }
+    #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."]
+    #[inline(always)]
+    pub fn set_lock_ns(&mut self, val: super::vals::Page0lock1lockNs) {
+        self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize);
+    }
+    #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."]
+    #[inline(always)]
+    pub const fn lock_bl(&self) -> super::vals::Page0lock1lockBl {
+        let val = (self.0 >> 4usize) & 0x03;
+        super::vals::Page0lock1lockBl::from_bits(val as u8)
+    }
+    #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."]
+    #[inline(always)]
+    pub fn set_lock_bl(&mut self, val: super::vals::Page0lock1lockBl) {
+        self.0 = (self.0 & !(0x03 << 4usize)) | (((val.to_bits() as u32) & 0x03) << 4usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r1(&self) -> u8 {
+        let val = (self.0 >> 8usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r1(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r2(&self) -> u8 {
+        let val = (self.0 >> 16usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r2(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize);
+    }
+}
+impl Default for Page0lock1 {
+    #[inline(always)]
+    fn default() -> Page0lock1 {
+        Page0lock1(0)
+    }
+}
+#[doc = "Lock configuration LSBs for page 10 (rows 0x280 through 0x2bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Page10lock0(pub u32);
+impl Page10lock0 {
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub const fn key_w(&self) -> u8 {
+        let val = (self.0 >> 0usize) & 0x07;
+        val as u8
+    }
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub fn set_key_w(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x07 << 0usize)) | (((val as u32) & 0x07) << 0usize);
+    }
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub const fn key_r(&self) -> u8 {
+        let val = (self.0 >> 3usize) & 0x07;
+        val as u8
+    }
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub fn set_key_r(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x07 << 3usize)) | (((val as u32) & 0x07) << 3usize);
+    }
+    #[doc = "State when at least one key is registered for this page and no matching key has been entered."]
+    #[inline(always)]
+    pub const fn no_key_state(&self) -> super::vals::Page10lock0noKeyState {
+        let val = (self.0 >> 6usize) & 0x01;
+        super::vals::Page10lock0noKeyState::from_bits(val as u8)
+    }
+    #[doc = "State when at least one key is registered for this page and no matching key has been entered."]
+    #[inline(always)]
+    pub fn set_no_key_state(&mut self, val: super::vals::Page10lock0noKeyState) {
+        self.0 = (self.0 & !(0x01 << 6usize)) | (((val.to_bits() as u32) & 0x01) << 6usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r1(&self) -> u8 {
+        let val = (self.0 >> 8usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r1(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r2(&self) -> u8 {
+        let val = (self.0 >> 16usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r2(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize);
+    }
+}
+impl Default for Page10lock0 {
+    #[inline(always)]
+    fn default() -> Page10lock0 {
+        Page10lock0(0)
+    }
+}
+#[doc = "Lock configuration MSBs for page 10 (rows 0x280 through 0x2bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Page10lock1(pub u32);
+impl Page10lock1 {
+    #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."]
+    #[inline(always)]
+    pub const fn lock_s(&self) -> super::vals::Page10lock1lockS {
+        let val = (self.0 >> 0usize) & 0x03;
+        super::vals::Page10lock1lockS::from_bits(val as u8)
+    }
+    #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."]
+    #[inline(always)]
+    pub fn set_lock_s(&mut self, val: super::vals::Page10lock1lockS) {
+        self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize);
+    }
+    #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."]
+    #[inline(always)]
+    pub const fn lock_ns(&self) -> super::vals::Page10lock1lockNs {
+        let val = (self.0 >> 2usize) & 0x03;
+        super::vals::Page10lock1lockNs::from_bits(val as u8)
+    }
+    #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."]
+    #[inline(always)]
+    pub fn set_lock_ns(&mut self, val: super::vals::Page10lock1lockNs) {
+        self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize);
+    }
+    #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."]
+    #[inline(always)]
+    pub const fn lock_bl(&self) -> super::vals::Page10lock1lockBl {
+        let val = (self.0 >> 4usize) & 0x03;
+        super::vals::Page10lock1lockBl::from_bits(val as u8)
+    }
+    #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."]
+    #[inline(always)]
+    pub fn set_lock_bl(&mut self, val: super::vals::Page10lock1lockBl) {
+        self.0 = (self.0 & !(0x03 << 4usize)) | (((val.to_bits() as u32) & 0x03) << 4usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r1(&self) -> u8 {
+        let val = (self.0 >> 8usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r1(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r2(&self) -> u8 {
+        let val = (self.0 >> 16usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r2(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize);
+    }
+}
+impl Default for Page10lock1 {
+    #[inline(always)]
+    fn default() -> Page10lock1 {
+        Page10lock1(0)
+    }
+}
+#[doc = "Lock configuration LSBs for page 11 (rows 0x2c0 through 0x2ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Page11lock0(pub u32);
+impl Page11lock0 {
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub const fn key_w(&self) -> u8 {
+        let val = (self.0 >> 0usize) & 0x07;
+        val as u8
+    }
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub fn set_key_w(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x07 << 0usize)) | (((val as u32) & 0x07) << 0usize);
+    }
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub const fn key_r(&self) -> u8 {
+        let val = (self.0 >> 3usize) & 0x07;
+        val as u8
+    }
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub fn set_key_r(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x07 << 3usize)) | (((val as u32) & 0x07) << 3usize);
+    }
+    #[doc = "State when at least one key is registered for this page and no matching key has been entered."]
+    #[inline(always)]
+    pub const fn no_key_state(&self) -> super::vals::Page11lock0noKeyState {
+        let val = (self.0 >> 6usize) & 0x01;
+        super::vals::Page11lock0noKeyState::from_bits(val as u8)
+    }
+    #[doc = "State when at least one key is registered for this page and no matching key has been entered."]
+    #[inline(always)]
+    pub fn set_no_key_state(&mut self, val: super::vals::Page11lock0noKeyState) {
+        self.0 = (self.0 & !(0x01 << 6usize)) | (((val.to_bits() as u32) & 0x01) << 6usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r1(&self) -> u8 {
+        let val = (self.0 >> 8usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r1(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r2(&self) -> u8 {
+        let val = (self.0 >> 16usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r2(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize);
+    }
+}
+impl Default for Page11lock0 {
+    #[inline(always)]
+    fn default() -> Page11lock0 {
+        Page11lock0(0)
+    }
+}
+#[doc = "Lock configuration MSBs for page 11 (rows 0x2c0 through 0x2ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Page11lock1(pub u32);
+impl Page11lock1 {
+    #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."]
+    #[inline(always)]
+    pub const fn lock_s(&self) -> super::vals::Page11lock1lockS {
+        let val = (self.0 >> 0usize) & 0x03;
+        super::vals::Page11lock1lockS::from_bits(val as u8)
+    }
+    #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."]
+    #[inline(always)]
+    pub fn set_lock_s(&mut self, val: super::vals::Page11lock1lockS) {
+        self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize);
+    }
+    #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."]
+    #[inline(always)]
+    pub const fn lock_ns(&self) -> super::vals::Page11lock1lockNs {
+        let val = (self.0 >> 2usize) & 0x03;
+        super::vals::Page11lock1lockNs::from_bits(val as u8)
+    }
+    #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."]
+    #[inline(always)]
+    pub fn set_lock_ns(&mut self, val: super::vals::Page11lock1lockNs) {
+        self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize);
+    }
+    #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."]
+    #[inline(always)]
+    pub const fn lock_bl(&self) -> super::vals::Page11lock1lockBl {
+        let val = (self.0 >> 4usize) & 0x03;
+        super::vals::Page11lock1lockBl::from_bits(val as u8)
+    }
+    #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."]
+    #[inline(always)]
+    pub fn set_lock_bl(&mut self, val: super::vals::Page11lock1lockBl) {
+        self.0 = (self.0 & !(0x03 << 4usize)) | (((val.to_bits() as u32) & 0x03) << 4usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r1(&self) -> u8 {
+        let val = (self.0 >> 8usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r1(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r2(&self) -> u8 {
+        let val = (self.0 >> 16usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r2(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize);
+    }
+}
+impl Default for Page11lock1 {
+    #[inline(always)]
+    fn default() -> Page11lock1 {
+        Page11lock1(0)
+    }
+}
+#[doc = "Lock configuration LSBs for page 12 (rows 0x300 through 0x33f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Page12lock0(pub u32);
+impl Page12lock0 {
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub const fn key_w(&self) -> u8 {
+        let val = (self.0 >> 0usize) & 0x07;
+        val as u8
+    }
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub fn set_key_w(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x07 << 0usize)) | (((val as u32) & 0x07) << 0usize);
+    }
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub const fn key_r(&self) -> u8 {
+        let val = (self.0 >> 3usize) & 0x07;
+        val as u8
+    }
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub fn set_key_r(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x07 << 3usize)) | (((val as u32) & 0x07) << 3usize);
+    }
+    #[doc = "State when at least one key is registered for this page and no matching key has been entered."]
+    #[inline(always)]
+    pub const fn no_key_state(&self) -> super::vals::Page12lock0noKeyState {
+        let val = (self.0 >> 6usize) & 0x01;
+        super::vals::Page12lock0noKeyState::from_bits(val as u8)
+    }
+    #[doc = "State when at least one key is registered for this page and no matching key has been entered."]
+    #[inline(always)]
+    pub fn set_no_key_state(&mut self, val: super::vals::Page12lock0noKeyState) {
+        self.0 = (self.0 & !(0x01 << 6usize)) | (((val.to_bits() as u32) & 0x01) << 6usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r1(&self) -> u8 {
+        let val = (self.0 >> 8usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r1(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r2(&self) -> u8 {
+        let val = (self.0 >> 16usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r2(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize);
+    }
+}
+impl Default for Page12lock0 {
+    #[inline(always)]
+    fn default() -> Page12lock0 {
+        Page12lock0(0)
+    }
+}
+#[doc = "Lock configuration MSBs for page 12 (rows 0x300 through 0x33f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Page12lock1(pub u32);
+impl Page12lock1 {
+    #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."]
+    #[inline(always)]
+    pub const fn lock_s(&self) -> super::vals::Page12lock1lockS {
+        let val = (self.0 >> 0usize) & 0x03;
+        super::vals::Page12lock1lockS::from_bits(val as u8)
+    }
+    #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."]
+    #[inline(always)]
+    pub fn set_lock_s(&mut self, val: super::vals::Page12lock1lockS) {
+        self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize);
+    }
+    #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."]
+    #[inline(always)]
+    pub const fn lock_ns(&self) -> super::vals::Page12lock1lockNs {
+        let val = (self.0 >> 2usize) & 0x03;
+        super::vals::Page12lock1lockNs::from_bits(val as u8)
+    }
+    #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."]
+    #[inline(always)]
+    pub fn set_lock_ns(&mut self, val: super::vals::Page12lock1lockNs) {
+        self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize);
+    }
+    #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."]
+    #[inline(always)]
+    pub const fn lock_bl(&self) -> super::vals::Page12lock1lockBl {
+        let val = (self.0 >> 4usize) & 0x03;
+        super::vals::Page12lock1lockBl::from_bits(val as u8)
+    }
+    #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."]
+    #[inline(always)]
+    pub fn set_lock_bl(&mut self, val: super::vals::Page12lock1lockBl) {
+        self.0 = (self.0 & !(0x03 << 4usize)) | (((val.to_bits() as u32) & 0x03) << 4usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r1(&self) -> u8 {
+        let val = (self.0 >> 8usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r1(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r2(&self) -> u8 {
+        let val = (self.0 >> 16usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r2(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize);
+    }
+}
+impl Default for Page12lock1 {
+    #[inline(always)]
+    fn default() -> Page12lock1 {
+        Page12lock1(0)
+    }
+}
+#[doc = "Lock configuration LSBs for page 13 (rows 0x340 through 0x37f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Page13lock0(pub u32);
+impl Page13lock0 {
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub const fn key_w(&self) -> u8 {
+        let val = (self.0 >> 0usize) & 0x07;
+        val as u8
+    }
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub fn set_key_w(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x07 << 0usize)) | (((val as u32) & 0x07) << 0usize);
+    }
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub const fn key_r(&self) -> u8 {
+        let val = (self.0 >> 3usize) & 0x07;
+        val as u8
+    }
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub fn set_key_r(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x07 << 3usize)) | (((val as u32) & 0x07) << 3usize);
+    }
+    #[doc = "State when at least one key is registered for this page and no matching key has been entered."]
+    #[inline(always)]
+    pub const fn no_key_state(&self) -> super::vals::Page13lock0noKeyState {
+        let val = (self.0 >> 6usize) & 0x01;
+        super::vals::Page13lock0noKeyState::from_bits(val as u8)
+    }
+    #[doc = "State when at least one key is registered for this page and no matching key has been entered."]
+    #[inline(always)]
+    pub fn set_no_key_state(&mut self, val: super::vals::Page13lock0noKeyState) {
+        self.0 = (self.0 & !(0x01 << 6usize)) | (((val.to_bits() as u32) & 0x01) << 6usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r1(&self) -> u8 {
+        let val = (self.0 >> 8usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r1(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r2(&self) -> u8 {
+        let val = (self.0 >> 16usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r2(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize);
+    }
+}
+impl Default for Page13lock0 {
+    #[inline(always)]
+    fn default() -> Page13lock0 {
+        Page13lock0(0)
+    }
+}
+#[doc = "Lock configuration MSBs for page 13 (rows 0x340 through 0x37f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Page13lock1(pub u32);
+impl Page13lock1 {
+    #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."]
+    #[inline(always)]
+    pub const fn lock_s(&self) -> super::vals::Page13lock1lockS {
+        let val = (self.0 >> 0usize) & 0x03;
+        super::vals::Page13lock1lockS::from_bits(val as u8)
+    }
+    #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."]
+    #[inline(always)]
+    pub fn set_lock_s(&mut self, val: super::vals::Page13lock1lockS) {
+        self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize);
+    }
+    #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."]
+    #[inline(always)]
+    pub const fn lock_ns(&self) -> super::vals::Page13lock1lockNs {
+        let val = (self.0 >> 2usize) & 0x03;
+        super::vals::Page13lock1lockNs::from_bits(val as u8)
+    }
+    #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."]
+    #[inline(always)]
+    pub fn set_lock_ns(&mut self, val: super::vals::Page13lock1lockNs) {
+        self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize);
+    }
+    #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."]
+    #[inline(always)]
+    pub const fn lock_bl(&self) -> super::vals::Page13lock1lockBl {
+        let val = (self.0 >> 4usize) & 0x03;
+        super::vals::Page13lock1lockBl::from_bits(val as u8)
+    }
+    #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."]
+    #[inline(always)]
+    pub fn set_lock_bl(&mut self, val: super::vals::Page13lock1lockBl) {
+        self.0 = (self.0 & !(0x03 << 4usize)) | (((val.to_bits() as u32) & 0x03) << 4usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r1(&self) -> u8 {
+        let val = (self.0 >> 8usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r1(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r2(&self) -> u8 {
+        let val = (self.0 >> 16usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r2(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize);
+    }
+}
+impl Default for Page13lock1 {
+    #[inline(always)]
+    fn default() -> Page13lock1 {
+        Page13lock1(0)
+    }
+}
+#[doc = "Lock configuration LSBs for page 14 (rows 0x380 through 0x3bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Page14lock0(pub u32);
+impl Page14lock0 {
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub const fn key_w(&self) -> u8 {
+        let val = (self.0 >> 0usize) & 0x07;
+        val as u8
+    }
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub fn set_key_w(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x07 << 0usize)) | (((val as u32) & 0x07) << 0usize);
+    }
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub const fn key_r(&self) -> u8 {
+        let val = (self.0 >> 3usize) & 0x07;
+        val as u8
+    }
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub fn set_key_r(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x07 << 3usize)) | (((val as u32) & 0x07) << 3usize);
+    }
+    #[doc = "State when at least one key is registered for this page and no matching key has been entered."]
+    #[inline(always)]
+    pub const fn no_key_state(&self) -> super::vals::Page14lock0noKeyState {
+        let val = (self.0 >> 6usize) & 0x01;
+        super::vals::Page14lock0noKeyState::from_bits(val as u8)
+    }
+    #[doc = "State when at least one key is registered for this page and no matching key has been entered."]
+    #[inline(always)]
+    pub fn set_no_key_state(&mut self, val: super::vals::Page14lock0noKeyState) {
+        self.0 = (self.0 & !(0x01 << 6usize)) | (((val.to_bits() as u32) & 0x01) << 6usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r1(&self) -> u8 {
+        let val = (self.0 >> 8usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r1(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r2(&self) -> u8 {
+        let val = (self.0 >> 16usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r2(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize);
+    }
+}
+impl Default for Page14lock0 {
+    #[inline(always)]
+    fn default() -> Page14lock0 {
+        Page14lock0(0)
+    }
+}
+#[doc = "Lock configuration MSBs for page 14 (rows 0x380 through 0x3bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Page14lock1(pub u32);
+impl Page14lock1 {
+    #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."]
+    #[inline(always)]
+    pub const fn lock_s(&self) -> super::vals::Page14lock1lockS {
+        let val = (self.0 >> 0usize) & 0x03;
+        super::vals::Page14lock1lockS::from_bits(val as u8)
+    }
+    #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."]
+    #[inline(always)]
+    pub fn set_lock_s(&mut self, val: super::vals::Page14lock1lockS) {
+        self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize);
+    }
+    #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."]
+    #[inline(always)]
+    pub const fn lock_ns(&self) -> super::vals::Page14lock1lockNs {
+        let val = (self.0 >> 2usize) & 0x03;
+        super::vals::Page14lock1lockNs::from_bits(val as u8)
+    }
+    #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."]
+    #[inline(always)]
+    pub fn set_lock_ns(&mut self, val: super::vals::Page14lock1lockNs) {
+        self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize);
+    }
+    #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."]
+    #[inline(always)]
+    pub const fn lock_bl(&self) -> super::vals::Page14lock1lockBl {
+        let val = (self.0 >> 4usize) & 0x03;
+        super::vals::Page14lock1lockBl::from_bits(val as u8)
+    }
+    #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."]
+    #[inline(always)]
+    pub fn set_lock_bl(&mut self, val: super::vals::Page14lock1lockBl) {
+        self.0 = (self.0 & !(0x03 << 4usize)) | (((val.to_bits() as u32) & 0x03) << 4usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r1(&self) -> u8 {
+        let val = (self.0 >> 8usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r1(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r2(&self) -> u8 {
+        let val = (self.0 >> 16usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r2(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize);
+    }
+}
+impl Default for Page14lock1 {
+    #[inline(always)]
+    fn default() -> Page14lock1 {
+        Page14lock1(0)
+    }
+}
+#[doc = "Lock configuration LSBs for page 15 (rows 0x3c0 through 0x3ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Page15lock0(pub u32);
+impl Page15lock0 {
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub const fn key_w(&self) -> u8 {
+        let val = (self.0 >> 0usize) & 0x07;
+        val as u8
+    }
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub fn set_key_w(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x07 << 0usize)) | (((val as u32) & 0x07) << 0usize);
+    }
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub const fn key_r(&self) -> u8 {
+        let val = (self.0 >> 3usize) & 0x07;
+        val as u8
+    }
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub fn set_key_r(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x07 << 3usize)) | (((val as u32) & 0x07) << 3usize);
+    }
+    #[doc = "State when at least one key is registered for this page and no matching key has been entered."]
+    #[inline(always)]
+    pub const fn no_key_state(&self) -> super::vals::Page15lock0noKeyState {
+        let val = (self.0 >> 6usize) & 0x01;
+        super::vals::Page15lock0noKeyState::from_bits(val as u8)
+    }
+    #[doc = "State when at least one key is registered for this page and no matching key has been entered."]
+    #[inline(always)]
+    pub fn set_no_key_state(&mut self, val: super::vals::Page15lock0noKeyState) {
+        self.0 = (self.0 & !(0x01 << 6usize)) | (((val.to_bits() as u32) & 0x01) << 6usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r1(&self) -> u8 {
+        let val = (self.0 >> 8usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r1(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r2(&self) -> u8 {
+        let val = (self.0 >> 16usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r2(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize);
+    }
+}
+impl Default for Page15lock0 {
+    #[inline(always)]
+    fn default() -> Page15lock0 {
+        Page15lock0(0)
+    }
+}
+#[doc = "Lock configuration MSBs for page 15 (rows 0x3c0 through 0x3ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Page15lock1(pub u32);
+impl Page15lock1 {
+    #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."]
+    #[inline(always)]
+    pub const fn lock_s(&self) -> super::vals::Page15lock1lockS {
+        let val = (self.0 >> 0usize) & 0x03;
+        super::vals::Page15lock1lockS::from_bits(val as u8)
+    }
+    #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."]
+    #[inline(always)]
+    pub fn set_lock_s(&mut self, val: super::vals::Page15lock1lockS) {
+        self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize);
+    }
+    #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."]
+    #[inline(always)]
+    pub const fn lock_ns(&self) -> super::vals::Page15lock1lockNs {
+        let val = (self.0 >> 2usize) & 0x03;
+        super::vals::Page15lock1lockNs::from_bits(val as u8)
+    }
+    #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."]
+    #[inline(always)]
+    pub fn set_lock_ns(&mut self, val: super::vals::Page15lock1lockNs) {
+        self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize);
+    }
+    #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."]
+    #[inline(always)]
+    pub const fn lock_bl(&self) -> super::vals::Page15lock1lockBl {
+        let val = (self.0 >> 4usize) & 0x03;
+        super::vals::Page15lock1lockBl::from_bits(val as u8)
+    }
+    #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."]
+    #[inline(always)]
+    pub fn set_lock_bl(&mut self, val: super::vals::Page15lock1lockBl) {
+        self.0 = (self.0 & !(0x03 << 4usize)) | (((val.to_bits() as u32) & 0x03) << 4usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r1(&self) -> u8 {
+        let val = (self.0 >> 8usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r1(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r2(&self) -> u8 {
+        let val = (self.0 >> 16usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r2(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize);
+    }
+}
+impl Default for Page15lock1 {
+    #[inline(always)]
+    fn default() -> Page15lock1 {
+        Page15lock1(0)
+    }
+}
+#[doc = "Lock configuration LSBs for page 16 (rows 0x400 through 0x43f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Page16lock0(pub u32);
+impl Page16lock0 {
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub const fn key_w(&self) -> u8 {
+        let val = (self.0 >> 0usize) & 0x07;
+        val as u8
+    }
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub fn set_key_w(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x07 << 0usize)) | (((val as u32) & 0x07) << 0usize);
+    }
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub const fn key_r(&self) -> u8 {
+        let val = (self.0 >> 3usize) & 0x07;
+        val as u8
+    }
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub fn set_key_r(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x07 << 3usize)) | (((val as u32) & 0x07) << 3usize);
+    }
+    #[doc = "State when at least one key is registered for this page and no matching key has been entered."]
+    #[inline(always)]
+    pub const fn no_key_state(&self) -> super::vals::Page16lock0noKeyState {
+        let val = (self.0 >> 6usize) & 0x01;
+        super::vals::Page16lock0noKeyState::from_bits(val as u8)
+    }
+    #[doc = "State when at least one key is registered for this page and no matching key has been entered."]
+    #[inline(always)]
+    pub fn set_no_key_state(&mut self, val: super::vals::Page16lock0noKeyState) {
+        self.0 = (self.0 & !(0x01 << 6usize)) | (((val.to_bits() as u32) & 0x01) << 6usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r1(&self) -> u8 {
+        let val = (self.0 >> 8usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r1(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r2(&self) -> u8 {
+        let val = (self.0 >> 16usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r2(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize);
+    }
+}
+impl Default for Page16lock0 {
+    #[inline(always)]
+    fn default() -> Page16lock0 {
+        Page16lock0(0)
+    }
+}
+#[doc = "Lock configuration MSBs for page 16 (rows 0x400 through 0x43f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Page16lock1(pub u32);
+impl Page16lock1 {
+    #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."]
+    #[inline(always)]
+    pub const fn lock_s(&self) -> super::vals::Page16lock1lockS {
+        let val = (self.0 >> 0usize) & 0x03;
+        super::vals::Page16lock1lockS::from_bits(val as u8)
+    }
+    #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."]
+    #[inline(always)]
+    pub fn set_lock_s(&mut self, val: super::vals::Page16lock1lockS) {
+        self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize);
+    }
+    #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."]
+    #[inline(always)]
+    pub const fn lock_ns(&self) -> super::vals::Page16lock1lockNs {
+        let val = (self.0 >> 2usize) & 0x03;
+        super::vals::Page16lock1lockNs::from_bits(val as u8)
+    }
+    #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."]
+    #[inline(always)]
+    pub fn set_lock_ns(&mut self, val: super::vals::Page16lock1lockNs) {
+        self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize);
+    }
+    #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."]
+    #[inline(always)]
+    pub const fn lock_bl(&self) -> super::vals::Page16lock1lockBl {
+        let val = (self.0 >> 4usize) & 0x03;
+        super::vals::Page16lock1lockBl::from_bits(val as u8)
+    }
+    #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."]
+    #[inline(always)]
+    pub fn set_lock_bl(&mut self, val: super::vals::Page16lock1lockBl) {
+        self.0 = (self.0 & !(0x03 << 4usize)) | (((val.to_bits() as u32) & 0x03) << 4usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r1(&self) -> u8 {
+        let val = (self.0 >> 8usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r1(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r2(&self) -> u8 {
+        let val = (self.0 >> 16usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r2(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize);
+    }
+}
+impl Default for Page16lock1 {
+    #[inline(always)]
+    fn default() -> Page16lock1 {
+        Page16lock1(0)
+    }
+}
+#[doc = "Lock configuration LSBs for page 17 (rows 0x440 through 0x47f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Page17lock0(pub u32);
+impl Page17lock0 {
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub const fn key_w(&self) -> u8 {
+        let val = (self.0 >> 0usize) & 0x07;
+        val as u8
+    }
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub fn set_key_w(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x07 << 0usize)) | (((val as u32) & 0x07) << 0usize);
+    }
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub const fn key_r(&self) -> u8 {
+        let val = (self.0 >> 3usize) & 0x07;
+        val as u8
+    }
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub fn set_key_r(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x07 << 3usize)) | (((val as u32) & 0x07) << 3usize);
+    }
+    #[doc = "State when at least one key is registered for this page and no matching key has been entered."]
+    #[inline(always)]
+    pub const fn no_key_state(&self) -> super::vals::Page17lock0noKeyState {
+        let val = (self.0 >> 6usize) & 0x01;
+        super::vals::Page17lock0noKeyState::from_bits(val as u8)
+    }
+    #[doc = "State when at least one key is registered for this page and no matching key has been entered."]
+    #[inline(always)]
+    pub fn set_no_key_state(&mut self, val: super::vals::Page17lock0noKeyState) {
+        self.0 = (self.0 & !(0x01 << 6usize)) | (((val.to_bits() as u32) & 0x01) << 6usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r1(&self) -> u8 {
+        let val = (self.0 >> 8usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r1(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r2(&self) -> u8 {
+        let val = (self.0 >> 16usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r2(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize);
+    }
+}
+impl Default for Page17lock0 {
+    #[inline(always)]
+    fn default() -> Page17lock0 {
+        Page17lock0(0)
+    }
+}
+#[doc = "Lock configuration MSBs for page 17 (rows 0x440 through 0x47f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Page17lock1(pub u32);
+impl Page17lock1 {
+    #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."]
+    #[inline(always)]
+    pub const fn lock_s(&self) -> super::vals::Page17lock1lockS {
+        let val = (self.0 >> 0usize) & 0x03;
+        super::vals::Page17lock1lockS::from_bits(val as u8)
+    }
+    #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."]
+    #[inline(always)]
+    pub fn set_lock_s(&mut self, val: super::vals::Page17lock1lockS) {
+        self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize);
+    }
+    #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."]
+    #[inline(always)]
+    pub const fn lock_ns(&self) -> super::vals::Page17lock1lockNs {
+        let val = (self.0 >> 2usize) & 0x03;
+        super::vals::Page17lock1lockNs::from_bits(val as u8)
+    }
+    #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."]
+    #[inline(always)]
+    pub fn set_lock_ns(&mut self, val: super::vals::Page17lock1lockNs) {
+        self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize);
+    }
+    #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."]
+    #[inline(always)]
+    pub const fn lock_bl(&self) -> super::vals::Page17lock1lockBl {
+        let val = (self.0 >> 4usize) & 0x03;
+        super::vals::Page17lock1lockBl::from_bits(val as u8)
+    }
+    #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."]
+    #[inline(always)]
+    pub fn set_lock_bl(&mut self, val: super::vals::Page17lock1lockBl) {
+        self.0 = (self.0 & !(0x03 << 4usize)) | (((val.to_bits() as u32) & 0x03) << 4usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r1(&self) -> u8 {
+        let val = (self.0 >> 8usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r1(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r2(&self) -> u8 {
+        let val = (self.0 >> 16usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r2(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize);
+    }
+}
+impl Default for Page17lock1 {
+    #[inline(always)]
+    fn default() -> Page17lock1 {
+        Page17lock1(0)
+    }
+}
+#[doc = "Lock configuration LSBs for page 18 (rows 0x480 through 0x4bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Page18lock0(pub u32);
+impl Page18lock0 {
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub const fn key_w(&self) -> u8 {
+        let val = (self.0 >> 0usize) & 0x07;
+        val as u8
+    }
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub fn set_key_w(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x07 << 0usize)) | (((val as u32) & 0x07) << 0usize);
+    }
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub const fn key_r(&self) -> u8 {
+        let val = (self.0 >> 3usize) & 0x07;
+        val as u8
+    }
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub fn set_key_r(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x07 << 3usize)) | (((val as u32) & 0x07) << 3usize);
+    }
+    #[doc = "State when at least one key is registered for this page and no matching key has been entered."]
+    #[inline(always)]
+    pub const fn no_key_state(&self) -> super::vals::Page18lock0noKeyState {
+        let val = (self.0 >> 6usize) & 0x01;
+        super::vals::Page18lock0noKeyState::from_bits(val as u8)
+    }
+    #[doc = "State when at least one key is registered for this page and no matching key has been entered."]
+    #[inline(always)]
+    pub fn set_no_key_state(&mut self, val: super::vals::Page18lock0noKeyState) {
+        self.0 = (self.0 & !(0x01 << 6usize)) | (((val.to_bits() as u32) & 0x01) << 6usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r1(&self) -> u8 {
+        let val = (self.0 >> 8usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r1(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r2(&self) -> u8 {
+        let val = (self.0 >> 16usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r2(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize);
+    }
+}
+impl Default for Page18lock0 {
+    #[inline(always)]
+    fn default() -> Page18lock0 {
+        Page18lock0(0)
+    }
+}
+#[doc = "Lock configuration MSBs for page 18 (rows 0x480 through 0x4bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Page18lock1(pub u32);
+impl Page18lock1 {
+    #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."]
+    #[inline(always)]
+    pub const fn lock_s(&self) -> super::vals::Page18lock1lockS {
+        let val = (self.0 >> 0usize) & 0x03;
+        super::vals::Page18lock1lockS::from_bits(val as u8)
+    }
+    #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."]
+    #[inline(always)]
+    pub fn set_lock_s(&mut self, val: super::vals::Page18lock1lockS) {
+        self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize);
+    }
+    #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."]
+    #[inline(always)]
+    pub const fn lock_ns(&self) -> super::vals::Page18lock1lockNs {
+        let val = (self.0 >> 2usize) & 0x03;
+        super::vals::Page18lock1lockNs::from_bits(val as u8)
+    }
+    #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."]
+    #[inline(always)]
+    pub fn set_lock_ns(&mut self, val: super::vals::Page18lock1lockNs) {
+        self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize);
+    }
+    #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."]
+    #[inline(always)]
+    pub const fn lock_bl(&self) -> super::vals::Page18lock1lockBl {
+        let val = (self.0 >> 4usize) & 0x03;
+        super::vals::Page18lock1lockBl::from_bits(val as u8)
+    }
+    #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."]
+    #[inline(always)]
+    pub fn set_lock_bl(&mut self, val: super::vals::Page18lock1lockBl) {
+        self.0 = (self.0 & !(0x03 << 4usize)) | (((val.to_bits() as u32) & 0x03) << 4usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r1(&self) -> u8 {
+        let val = (self.0 >> 8usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r1(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r2(&self) -> u8 {
+        let val = (self.0 >> 16usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r2(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize);
+    }
+}
+impl Default for Page18lock1 {
+    #[inline(always)]
+    fn default() -> Page18lock1 {
+        Page18lock1(0)
+    }
+}
+#[doc = "Lock configuration LSBs for page 19 (rows 0x4c0 through 0x4ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Page19lock0(pub u32);
+impl Page19lock0 {
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub const fn key_w(&self) -> u8 {
+        let val = (self.0 >> 0usize) & 0x07;
+        val as u8
+    }
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub fn set_key_w(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x07 << 0usize)) | (((val as u32) & 0x07) << 0usize);
+    }
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub const fn key_r(&self) -> u8 {
+        let val = (self.0 >> 3usize) & 0x07;
+        val as u8
+    }
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub fn set_key_r(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x07 << 3usize)) | (((val as u32) & 0x07) << 3usize);
+    }
+    #[doc = "State when at least one key is registered for this page and no matching key has been entered."]
+    #[inline(always)]
+    pub const fn no_key_state(&self) -> super::vals::Page19lock0noKeyState {
+        let val = (self.0 >> 6usize) & 0x01;
+        super::vals::Page19lock0noKeyState::from_bits(val as u8)
+    }
+    #[doc = "State when at least one key is registered for this page and no matching key has been entered."]
+    #[inline(always)]
+    pub fn set_no_key_state(&mut self, val: super::vals::Page19lock0noKeyState) {
+        self.0 = (self.0 & !(0x01 << 6usize)) | (((val.to_bits() as u32) & 0x01) << 6usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r1(&self) -> u8 {
+        let val = (self.0 >> 8usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r1(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r2(&self) -> u8 {
+        let val = (self.0 >> 16usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r2(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize);
+    }
+}
+impl Default for Page19lock0 {
+    #[inline(always)]
+    fn default() -> Page19lock0 {
+        Page19lock0(0)
+    }
+}
+#[doc = "Lock configuration MSBs for page 19 (rows 0x4c0 through 0x4ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Page19lock1(pub u32);
+impl Page19lock1 {
+    #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."]
+    #[inline(always)]
+    pub const fn lock_s(&self) -> super::vals::Page19lock1lockS {
+        let val = (self.0 >> 0usize) & 0x03;
+        super::vals::Page19lock1lockS::from_bits(val as u8)
+    }
+    #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."]
+    #[inline(always)]
+    pub fn set_lock_s(&mut self, val: super::vals::Page19lock1lockS) {
+        self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize);
+    }
+    #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."]
+    #[inline(always)]
+    pub const fn lock_ns(&self) -> super::vals::Page19lock1lockNs {
+        let val = (self.0 >> 2usize) & 0x03;
+        super::vals::Page19lock1lockNs::from_bits(val as u8)
+    }
+    #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."]
+    #[inline(always)]
+    pub fn set_lock_ns(&mut self, val: super::vals::Page19lock1lockNs) {
+        self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize);
+    }
+    #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."]
+    #[inline(always)]
+    pub const fn lock_bl(&self) -> super::vals::Page19lock1lockBl {
+        let val = (self.0 >> 4usize) & 0x03;
+        super::vals::Page19lock1lockBl::from_bits(val as u8)
+    }
+    #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."]
+    #[inline(always)]
+    pub fn set_lock_bl(&mut self, val: super::vals::Page19lock1lockBl) {
+        self.0 = (self.0 & !(0x03 << 4usize)) | (((val.to_bits() as u32) & 0x03) << 4usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r1(&self) -> u8 {
+        let val = (self.0 >> 8usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r1(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r2(&self) -> u8 {
+        let val = (self.0 >> 16usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r2(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize);
+    }
+}
+impl Default for Page19lock1 {
+    #[inline(always)]
+    fn default() -> Page19lock1 {
+        Page19lock1(0)
+    }
+}
+#[doc = "Lock configuration LSBs for page 1 (rows 0x40 through 0x7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Page1lock0(pub u32);
+impl Page1lock0 {
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub const fn key_w(&self) -> u8 {
+        let val = (self.0 >> 0usize) & 0x07;
+        val as u8
+    }
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub fn set_key_w(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x07 << 0usize)) | (((val as u32) & 0x07) << 0usize);
+    }
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub const fn key_r(&self) -> u8 {
+        let val = (self.0 >> 3usize) & 0x07;
+        val as u8
+    }
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub fn set_key_r(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x07 << 3usize)) | (((val as u32) & 0x07) << 3usize);
+    }
+    #[doc = "State when at least one key is registered for this page and no matching key has been entered."]
+    #[inline(always)]
+    pub const fn no_key_state(&self) -> super::vals::Page1lock0noKeyState {
+        let val = (self.0 >> 6usize) & 0x01;
+        super::vals::Page1lock0noKeyState::from_bits(val as u8)
+    }
+    #[doc = "State when at least one key is registered for this page and no matching key has been entered."]
+    #[inline(always)]
+    pub fn set_no_key_state(&mut self, val: super::vals::Page1lock0noKeyState) {
+        self.0 = (self.0 & !(0x01 << 6usize)) | (((val.to_bits() as u32) & 0x01) << 6usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r1(&self) -> u8 {
+        let val = (self.0 >> 8usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r1(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r2(&self) -> u8 {
+        let val = (self.0 >> 16usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r2(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize);
+    }
+}
+impl Default for Page1lock0 {
+    #[inline(always)]
+    fn default() -> Page1lock0 {
+        Page1lock0(0)
+    }
+}
+#[doc = "Lock configuration MSBs for page 1 (rows 0x40 through 0x7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Page1lock1(pub u32);
+impl Page1lock1 {
+    #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."]
+    #[inline(always)]
+    pub const fn lock_s(&self) -> super::vals::Page1lock1lockS {
+        let val = (self.0 >> 0usize) & 0x03;
+        super::vals::Page1lock1lockS::from_bits(val as u8)
+    }
+    #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."]
+    #[inline(always)]
+    pub fn set_lock_s(&mut self, val: super::vals::Page1lock1lockS) {
+        self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize);
+    }
+    #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."]
+    #[inline(always)]
+    pub const fn lock_ns(&self) -> super::vals::Page1lock1lockNs {
+        let val = (self.0 >> 2usize) & 0x03;
+        super::vals::Page1lock1lockNs::from_bits(val as u8)
+    }
+    #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."]
+    #[inline(always)]
+    pub fn set_lock_ns(&mut self, val: super::vals::Page1lock1lockNs) {
+        self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize);
+    }
+    #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."]
+    #[inline(always)]
+    pub const fn lock_bl(&self) -> super::vals::Page1lock1lockBl {
+        let val = (self.0 >> 4usize) & 0x03;
+        super::vals::Page1lock1lockBl::from_bits(val as u8)
+    }
+    #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."]
+    #[inline(always)]
+    pub fn set_lock_bl(&mut self, val: super::vals::Page1lock1lockBl) {
+        self.0 = (self.0 & !(0x03 << 4usize)) | (((val.to_bits() as u32) & 0x03) << 4usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r1(&self) -> u8 {
+        let val = (self.0 >> 8usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r1(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r2(&self) -> u8 {
+        let val = (self.0 >> 16usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r2(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize);
+    }
+}
+impl Default for Page1lock1 {
+    #[inline(always)]
+    fn default() -> Page1lock1 {
+        Page1lock1(0)
+    }
+}
+#[doc = "Lock configuration LSBs for page 20 (rows 0x500 through 0x53f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Page20lock0(pub u32);
+impl Page20lock0 {
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub const fn key_w(&self) -> u8 {
+        let val = (self.0 >> 0usize) & 0x07;
+        val as u8
+    }
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub fn set_key_w(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x07 << 0usize)) | (((val as u32) & 0x07) << 0usize);
+    }
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub const fn key_r(&self) -> u8 {
+        let val = (self.0 >> 3usize) & 0x07;
+        val as u8
+    }
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub fn set_key_r(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x07 << 3usize)) | (((val as u32) & 0x07) << 3usize);
+    }
+    #[doc = "State when at least one key is registered for this page and no matching key has been entered."]
+    #[inline(always)]
+    pub const fn no_key_state(&self) -> super::vals::Page20lock0noKeyState {
+        let val = (self.0 >> 6usize) & 0x01;
+        super::vals::Page20lock0noKeyState::from_bits(val as u8)
+    }
+    #[doc = "State when at least one key is registered for this page and no matching key has been entered."]
+    #[inline(always)]
+    pub fn set_no_key_state(&mut self, val: super::vals::Page20lock0noKeyState) {
+        self.0 = (self.0 & !(0x01 << 6usize)) | (((val.to_bits() as u32) & 0x01) << 6usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r1(&self) -> u8 {
+        let val = (self.0 >> 8usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r1(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r2(&self) -> u8 {
+        let val = (self.0 >> 16usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r2(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize);
+    }
+}
+impl Default for Page20lock0 {
+    #[inline(always)]
+    fn default() -> Page20lock0 {
+        Page20lock0(0)
+    }
+}
+#[doc = "Lock configuration MSBs for page 20 (rows 0x500 through 0x53f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Page20lock1(pub u32);
+impl Page20lock1 {
+    #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."]
+    #[inline(always)]
+    pub const fn lock_s(&self) -> super::vals::Page20lock1lockS {
+        let val = (self.0 >> 0usize) & 0x03;
+        super::vals::Page20lock1lockS::from_bits(val as u8)
+    }
+    #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."]
+    #[inline(always)]
+    pub fn set_lock_s(&mut self, val: super::vals::Page20lock1lockS) {
+        self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize);
+    }
+    #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."]
+    #[inline(always)]
+    pub const fn lock_ns(&self) -> super::vals::Page20lock1lockNs {
+        let val = (self.0 >> 2usize) & 0x03;
+        super::vals::Page20lock1lockNs::from_bits(val as u8)
+    }
+    #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."]
+    #[inline(always)]
+    pub fn set_lock_ns(&mut self, val: super::vals::Page20lock1lockNs) {
+        self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize);
+    }
+    #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."]
+    #[inline(always)]
+    pub const fn lock_bl(&self) -> super::vals::Page20lock1lockBl {
+        let val = (self.0 >> 4usize) & 0x03;
+        super::vals::Page20lock1lockBl::from_bits(val as u8)
+    }
+    #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."]
+    #[inline(always)]
+    pub fn set_lock_bl(&mut self, val: super::vals::Page20lock1lockBl) {
+        self.0 = (self.0 & !(0x03 << 4usize)) | (((val.to_bits() as u32) & 0x03) << 4usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r1(&self) -> u8 {
+        let val = (self.0 >> 8usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r1(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r2(&self) -> u8 {
+        let val = (self.0 >> 16usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r2(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize);
+    }
+}
+impl Default for Page20lock1 {
+    #[inline(always)]
+    fn default() -> Page20lock1 {
+        Page20lock1(0)
+    }
+}
+#[doc = "Lock configuration LSBs for page 21 (rows 0x540 through 0x57f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Page21lock0(pub u32);
+impl Page21lock0 {
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub const fn key_w(&self) -> u8 {
+        let val = (self.0 >> 0usize) & 0x07;
+        val as u8
+    }
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub fn set_key_w(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x07 << 0usize)) | (((val as u32) & 0x07) << 0usize);
+    }
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub const fn key_r(&self) -> u8 {
+        let val = (self.0 >> 3usize) & 0x07;
+        val as u8
+    }
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub fn set_key_r(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x07 << 3usize)) | (((val as u32) & 0x07) << 3usize);
+    }
+    #[doc = "State when at least one key is registered for this page and no matching key has been entered."]
+    #[inline(always)]
+    pub const fn no_key_state(&self) -> super::vals::Page21lock0noKeyState {
+        let val = (self.0 >> 6usize) & 0x01;
+        super::vals::Page21lock0noKeyState::from_bits(val as u8)
+    }
+    #[doc = "State when at least one key is registered for this page and no matching key has been entered."]
+    #[inline(always)]
+    pub fn set_no_key_state(&mut self, val: super::vals::Page21lock0noKeyState) {
+        self.0 = (self.0 & !(0x01 << 6usize)) | (((val.to_bits() as u32) & 0x01) << 6usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r1(&self) -> u8 {
+        let val = (self.0 >> 8usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r1(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r2(&self) -> u8 {
+        let val = (self.0 >> 16usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r2(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize);
+    }
+}
+impl Default for Page21lock0 {
+    #[inline(always)]
+    fn default() -> Page21lock0 {
+        Page21lock0(0)
+    }
+}
+#[doc = "Lock configuration MSBs for page 21 (rows 0x540 through 0x57f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Page21lock1(pub u32);
+impl Page21lock1 {
+    #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."]
+    #[inline(always)]
+    pub const fn lock_s(&self) -> super::vals::Page21lock1lockS {
+        let val = (self.0 >> 0usize) & 0x03;
+        super::vals::Page21lock1lockS::from_bits(val as u8)
+    }
+    #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."]
+    #[inline(always)]
+    pub fn set_lock_s(&mut self, val: super::vals::Page21lock1lockS) {
+        self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize);
+    }
+    #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."]
+    #[inline(always)]
+    pub const fn lock_ns(&self) -> super::vals::Page21lock1lockNs {
+        let val = (self.0 >> 2usize) & 0x03;
+        super::vals::Page21lock1lockNs::from_bits(val as u8)
+    }
+    #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."]
+    #[inline(always)]
+    pub fn set_lock_ns(&mut self, val: super::vals::Page21lock1lockNs) {
+        self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize);
+    }
+    #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."]
+    #[inline(always)]
+    pub const fn lock_bl(&self) -> super::vals::Page21lock1lockBl {
+        let val = (self.0 >> 4usize) & 0x03;
+        super::vals::Page21lock1lockBl::from_bits(val as u8)
+    }
+    #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."]
+    #[inline(always)]
+    pub fn set_lock_bl(&mut self, val: super::vals::Page21lock1lockBl) {
+        self.0 = (self.0 & !(0x03 << 4usize)) | (((val.to_bits() as u32) & 0x03) << 4usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r1(&self) -> u8 {
+        let val = (self.0 >> 8usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r1(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r2(&self) -> u8 {
+        let val = (self.0 >> 16usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r2(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize);
+    }
+}
+impl Default for Page21lock1 {
+    #[inline(always)]
+    fn default() -> Page21lock1 {
+        Page21lock1(0)
+    }
+}
+#[doc = "Lock configuration LSBs for page 22 (rows 0x580 through 0x5bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Page22lock0(pub u32);
+impl Page22lock0 {
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub const fn key_w(&self) -> u8 {
+        let val = (self.0 >> 0usize) & 0x07;
+        val as u8
+    }
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub fn set_key_w(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x07 << 0usize)) | (((val as u32) & 0x07) << 0usize);
+    }
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub const fn key_r(&self) -> u8 {
+        let val = (self.0 >> 3usize) & 0x07;
+        val as u8
+    }
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub fn set_key_r(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x07 << 3usize)) | (((val as u32) & 0x07) << 3usize);
+    }
+    #[doc = "State when at least one key is registered for this page and no matching key has been entered."]
+    #[inline(always)]
+    pub const fn no_key_state(&self) -> super::vals::Page22lock0noKeyState {
+        let val = (self.0 >> 6usize) & 0x01;
+        super::vals::Page22lock0noKeyState::from_bits(val as u8)
+    }
+    #[doc = "State when at least one key is registered for this page and no matching key has been entered."]
+    #[inline(always)]
+    pub fn set_no_key_state(&mut self, val: super::vals::Page22lock0noKeyState) {
+        self.0 = (self.0 & !(0x01 << 6usize)) | (((val.to_bits() as u32) & 0x01) << 6usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r1(&self) -> u8 {
+        let val = (self.0 >> 8usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r1(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r2(&self) -> u8 {
+        let val = (self.0 >> 16usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r2(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize);
+    }
+}
+impl Default for Page22lock0 {
+    #[inline(always)]
+    fn default() -> Page22lock0 {
+        Page22lock0(0)
+    }
+}
+#[doc = "Lock configuration MSBs for page 22 (rows 0x580 through 0x5bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Page22lock1(pub u32);
+impl Page22lock1 {
+    #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."]
+    #[inline(always)]
+    pub const fn lock_s(&self) -> super::vals::Page22lock1lockS {
+        let val = (self.0 >> 0usize) & 0x03;
+        super::vals::Page22lock1lockS::from_bits(val as u8)
+    }
+    #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."]
+    #[inline(always)]
+    pub fn set_lock_s(&mut self, val: super::vals::Page22lock1lockS) {
+        self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize);
+    }
+    #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."]
+    #[inline(always)]
+    pub const fn lock_ns(&self) -> super::vals::Page22lock1lockNs {
+        let val = (self.0 >> 2usize) & 0x03;
+        super::vals::Page22lock1lockNs::from_bits(val as u8)
+    }
+    #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."]
+    #[inline(always)]
+    pub fn set_lock_ns(&mut self, val: super::vals::Page22lock1lockNs) {
+        self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize);
+    }
+    #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."]
+    #[inline(always)]
+    pub const fn lock_bl(&self) -> super::vals::Page22lock1lockBl {
+        let val = (self.0 >> 4usize) & 0x03;
+        super::vals::Page22lock1lockBl::from_bits(val as u8)
+    }
+    #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."]
+    #[inline(always)]
+    pub fn set_lock_bl(&mut self, val: super::vals::Page22lock1lockBl) {
+        self.0 = (self.0 & !(0x03 << 4usize)) | (((val.to_bits() as u32) & 0x03) << 4usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r1(&self) -> u8 {
+        let val = (self.0 >> 8usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r1(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r2(&self) -> u8 {
+        let val = (self.0 >> 16usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r2(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize);
+    }
+}
+impl Default for Page22lock1 {
+    #[inline(always)]
+    fn default() -> Page22lock1 {
+        Page22lock1(0)
+    }
+}
+#[doc = "Lock configuration LSBs for page 23 (rows 0x5c0 through 0x5ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Page23lock0(pub u32);
+impl Page23lock0 {
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub const fn key_w(&self) -> u8 {
+        let val = (self.0 >> 0usize) & 0x07;
+        val as u8
+    }
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub fn set_key_w(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x07 << 0usize)) | (((val as u32) & 0x07) << 0usize);
+    }
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub const fn key_r(&self) -> u8 {
+        let val = (self.0 >> 3usize) & 0x07;
+        val as u8
+    }
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub fn set_key_r(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x07 << 3usize)) | (((val as u32) & 0x07) << 3usize);
+    }
+    #[doc = "State when at least one key is registered for this page and no matching key has been entered."]
+    #[inline(always)]
+    pub const fn no_key_state(&self) -> super::vals::Page23lock0noKeyState {
+        let val = (self.0 >> 6usize) & 0x01;
+        super::vals::Page23lock0noKeyState::from_bits(val as u8)
+    }
+    #[doc = "State when at least one key is registered for this page and no matching key has been entered."]
+    #[inline(always)]
+    pub fn set_no_key_state(&mut self, val: super::vals::Page23lock0noKeyState) {
+        self.0 = (self.0 & !(0x01 << 6usize)) | (((val.to_bits() as u32) & 0x01) << 6usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r1(&self) -> u8 {
+        let val = (self.0 >> 8usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r1(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r2(&self) -> u8 {
+        let val = (self.0 >> 16usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r2(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize);
+    }
+}
+impl Default for Page23lock0 {
+    #[inline(always)]
+    fn default() -> Page23lock0 {
+        Page23lock0(0)
+    }
+}
+#[doc = "Lock configuration MSBs for page 23 (rows 0x5c0 through 0x5ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Page23lock1(pub u32);
+impl Page23lock1 {
+    #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."]
+    #[inline(always)]
+    pub const fn lock_s(&self) -> super::vals::Page23lock1lockS {
+        let val = (self.0 >> 0usize) & 0x03;
+        super::vals::Page23lock1lockS::from_bits(val as u8)
+    }
+    #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."]
+    #[inline(always)]
+    pub fn set_lock_s(&mut self, val: super::vals::Page23lock1lockS) {
+        self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize);
+    }
+    #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."]
+    #[inline(always)]
+    pub const fn lock_ns(&self) -> super::vals::Page23lock1lockNs {
+        let val = (self.0 >> 2usize) & 0x03;
+        super::vals::Page23lock1lockNs::from_bits(val as u8)
+    }
+    #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."]
+    #[inline(always)]
+    pub fn set_lock_ns(&mut self, val: super::vals::Page23lock1lockNs) {
+        self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize);
+    }
+    #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."]
+    #[inline(always)]
+    pub const fn lock_bl(&self) -> super::vals::Page23lock1lockBl {
+        let val = (self.0 >> 4usize) & 0x03;
+        super::vals::Page23lock1lockBl::from_bits(val as u8)
+    }
+    #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."]
+    #[inline(always)]
+    pub fn set_lock_bl(&mut self, val: super::vals::Page23lock1lockBl) {
+        self.0 = (self.0 & !(0x03 << 4usize)) | (((val.to_bits() as u32) & 0x03) << 4usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r1(&self) -> u8 {
+        let val = (self.0 >> 8usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r1(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r2(&self) -> u8 {
+        let val = (self.0 >> 16usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r2(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize);
+    }
+}
+impl Default for Page23lock1 {
+    #[inline(always)]
+    fn default() -> Page23lock1 {
+        Page23lock1(0)
+    }
+}
+#[doc = "Lock configuration LSBs for page 24 (rows 0x600 through 0x63f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Page24lock0(pub u32);
+impl Page24lock0 {
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub const fn key_w(&self) -> u8 {
+        let val = (self.0 >> 0usize) & 0x07;
+        val as u8
+    }
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub fn set_key_w(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x07 << 0usize)) | (((val as u32) & 0x07) << 0usize);
+    }
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub const fn key_r(&self) -> u8 {
+        let val = (self.0 >> 3usize) & 0x07;
+        val as u8
+    }
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub fn set_key_r(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x07 << 3usize)) | (((val as u32) & 0x07) << 3usize);
+    }
+    #[doc = "State when at least one key is registered for this page and no matching key has been entered."]
+    #[inline(always)]
+    pub const fn no_key_state(&self) -> super::vals::Page24lock0noKeyState {
+        let val = (self.0 >> 6usize) & 0x01;
+        super::vals::Page24lock0noKeyState::from_bits(val as u8)
+    }
+    #[doc = "State when at least one key is registered for this page and no matching key has been entered."]
+    #[inline(always)]
+    pub fn set_no_key_state(&mut self, val: super::vals::Page24lock0noKeyState) {
+        self.0 = (self.0 & !(0x01 << 6usize)) | (((val.to_bits() as u32) & 0x01) << 6usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r1(&self) -> u8 {
+        let val = (self.0 >> 8usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r1(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r2(&self) -> u8 {
+        let val = (self.0 >> 16usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r2(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize);
+    }
+}
+impl Default for Page24lock0 {
+    #[inline(always)]
+    fn default() -> Page24lock0 {
+        Page24lock0(0)
+    }
+}
+#[doc = "Lock configuration MSBs for page 24 (rows 0x600 through 0x63f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Page24lock1(pub u32);
+impl Page24lock1 {
+    #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."]
+    #[inline(always)]
+    pub const fn lock_s(&self) -> super::vals::Page24lock1lockS {
+        let val = (self.0 >> 0usize) & 0x03;
+        super::vals::Page24lock1lockS::from_bits(val as u8)
+    }
+    #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."]
+    #[inline(always)]
+    pub fn set_lock_s(&mut self, val: super::vals::Page24lock1lockS) {
+        self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize);
+    }
+    #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."]
+    #[inline(always)]
+    pub const fn lock_ns(&self) -> super::vals::Page24lock1lockNs {
+        let val = (self.0 >> 2usize) & 0x03;
+        super::vals::Page24lock1lockNs::from_bits(val as u8)
+    }
+    #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."]
+    #[inline(always)]
+    pub fn set_lock_ns(&mut self, val: super::vals::Page24lock1lockNs) {
+        self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize);
+    }
+    #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."]
+    #[inline(always)]
+    pub const fn lock_bl(&self) -> super::vals::Page24lock1lockBl {
+        let val = (self.0 >> 4usize) & 0x03;
+        super::vals::Page24lock1lockBl::from_bits(val as u8)
+    }
+    #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."]
+    #[inline(always)]
+    pub fn set_lock_bl(&mut self, val: super::vals::Page24lock1lockBl) {
+        self.0 = (self.0 & !(0x03 << 4usize)) | (((val.to_bits() as u32) & 0x03) << 4usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r1(&self) -> u8 {
+        let val = (self.0 >> 8usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r1(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r2(&self) -> u8 {
+        let val = (self.0 >> 16usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r2(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize);
+    }
+}
+impl Default for Page24lock1 {
+    #[inline(always)]
+    fn default() -> Page24lock1 {
+        Page24lock1(0)
+    }
+}
+#[doc = "Lock configuration LSBs for page 25 (rows 0x640 through 0x67f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Page25lock0(pub u32);
+impl Page25lock0 {
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub const fn key_w(&self) -> u8 {
+        let val = (self.0 >> 0usize) & 0x07;
+        val as u8
+    }
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub fn set_key_w(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x07 << 0usize)) | (((val as u32) & 0x07) << 0usize);
+    }
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub const fn key_r(&self) -> u8 {
+        let val = (self.0 >> 3usize) & 0x07;
+        val as u8
+    }
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub fn set_key_r(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x07 << 3usize)) | (((val as u32) & 0x07) << 3usize);
+    }
+    #[doc = "State when at least one key is registered for this page and no matching key has been entered."]
+    #[inline(always)]
+    pub const fn no_key_state(&self) -> super::vals::Page25lock0noKeyState {
+        let val = (self.0 >> 6usize) & 0x01;
+        super::vals::Page25lock0noKeyState::from_bits(val as u8)
+    }
+    #[doc = "State when at least one key is registered for this page and no matching key has been entered."]
+    #[inline(always)]
+    pub fn set_no_key_state(&mut self, val: super::vals::Page25lock0noKeyState) {
+        self.0 = (self.0 & !(0x01 << 6usize)) | (((val.to_bits() as u32) & 0x01) << 6usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r1(&self) -> u8 {
+        let val = (self.0 >> 8usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r1(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r2(&self) -> u8 {
+        let val = (self.0 >> 16usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r2(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize);
+    }
+}
+impl Default for Page25lock0 {
+    #[inline(always)]
+    fn default() -> Page25lock0 {
+        Page25lock0(0)
+    }
+}
+#[doc = "Lock configuration MSBs for page 25 (rows 0x640 through 0x67f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Page25lock1(pub u32);
+impl Page25lock1 {
+    #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."]
+    #[inline(always)]
+    pub const fn lock_s(&self) -> super::vals::Page25lock1lockS {
+        let val = (self.0 >> 0usize) & 0x03;
+        super::vals::Page25lock1lockS::from_bits(val as u8)
+    }
+    #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."]
+    #[inline(always)]
+    pub fn set_lock_s(&mut self, val: super::vals::Page25lock1lockS) {
+        self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize);
+    }
+    #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."]
+    #[inline(always)]
+    pub const fn lock_ns(&self) -> super::vals::Page25lock1lockNs {
+        let val = (self.0 >> 2usize) & 0x03;
+        super::vals::Page25lock1lockNs::from_bits(val as u8)
+    }
+    #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."]
+    #[inline(always)]
+    pub fn set_lock_ns(&mut self, val: super::vals::Page25lock1lockNs) {
+        self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize);
+    }
+    #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."]
+    #[inline(always)]
+    pub const fn lock_bl(&self) -> super::vals::Page25lock1lockBl {
+        let val = (self.0 >> 4usize) & 0x03;
+        super::vals::Page25lock1lockBl::from_bits(val as u8)
+    }
+    #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."]
+    #[inline(always)]
+    pub fn set_lock_bl(&mut self, val: super::vals::Page25lock1lockBl) {
+        self.0 = (self.0 & !(0x03 << 4usize)) | (((val.to_bits() as u32) & 0x03) << 4usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r1(&self) -> u8 {
+        let val = (self.0 >> 8usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r1(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r2(&self) -> u8 {
+        let val = (self.0 >> 16usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r2(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize);
+    }
+}
+impl Default for Page25lock1 {
+    #[inline(always)]
+    fn default() -> Page25lock1 {
+        Page25lock1(0)
+    }
+}
+#[doc = "Lock configuration LSBs for page 26 (rows 0x680 through 0x6bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Page26lock0(pub u32);
+impl Page26lock0 {
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub const fn key_w(&self) -> u8 {
+        let val = (self.0 >> 0usize) & 0x07;
+        val as u8
+    }
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub fn set_key_w(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x07 << 0usize)) | (((val as u32) & 0x07) << 0usize);
+    }
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub const fn key_r(&self) -> u8 {
+        let val = (self.0 >> 3usize) & 0x07;
+        val as u8
+    }
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub fn set_key_r(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x07 << 3usize)) | (((val as u32) & 0x07) << 3usize);
+    }
+    #[doc = "State when at least one key is registered for this page and no matching key has been entered."]
+    #[inline(always)]
+    pub const fn no_key_state(&self) -> super::vals::Page26lock0noKeyState {
+        let val = (self.0 >> 6usize) & 0x01;
+        super::vals::Page26lock0noKeyState::from_bits(val as u8)
+    }
+    #[doc = "State when at least one key is registered for this page and no matching key has been entered."]
+    #[inline(always)]
+    pub fn set_no_key_state(&mut self, val: super::vals::Page26lock0noKeyState) {
+        self.0 = (self.0 & !(0x01 << 6usize)) | (((val.to_bits() as u32) & 0x01) << 6usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r1(&self) -> u8 {
+        let val = (self.0 >> 8usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r1(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r2(&self) -> u8 {
+        let val = (self.0 >> 16usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r2(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize);
+    }
+}
+impl Default for Page26lock0 {
+    #[inline(always)]
+    fn default() -> Page26lock0 {
+        Page26lock0(0)
+    }
+}
+#[doc = "Lock configuration MSBs for page 26 (rows 0x680 through 0x6bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Page26lock1(pub u32);
+impl Page26lock1 {
+    #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."]
+    #[inline(always)]
+    pub const fn lock_s(&self) -> super::vals::Page26lock1lockS {
+        let val = (self.0 >> 0usize) & 0x03;
+        super::vals::Page26lock1lockS::from_bits(val as u8)
+    }
+    #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."]
+    #[inline(always)]
+    pub fn set_lock_s(&mut self, val: super::vals::Page26lock1lockS) {
+        self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize);
+    }
+    #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."]
+    #[inline(always)]
+    pub const fn lock_ns(&self) -> super::vals::Page26lock1lockNs {
+        let val = (self.0 >> 2usize) & 0x03;
+        super::vals::Page26lock1lockNs::from_bits(val as u8)
+    }
+    #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."]
+    #[inline(always)]
+    pub fn set_lock_ns(&mut self, val: super::vals::Page26lock1lockNs) {
+        self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize);
+    }
+    #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."]
+    #[inline(always)]
+    pub const fn lock_bl(&self) -> super::vals::Page26lock1lockBl {
+        let val = (self.0 >> 4usize) & 0x03;
+        super::vals::Page26lock1lockBl::from_bits(val as u8)
+    }
+    #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."]
+    #[inline(always)]
+    pub fn set_lock_bl(&mut self, val: super::vals::Page26lock1lockBl) {
+        self.0 = (self.0 & !(0x03 << 4usize)) | (((val.to_bits() as u32) & 0x03) << 4usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r1(&self) -> u8 {
+        let val = (self.0 >> 8usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r1(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r2(&self) -> u8 {
+        let val = (self.0 >> 16usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r2(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize);
+    }
+}
+impl Default for Page26lock1 {
+    #[inline(always)]
+    fn default() -> Page26lock1 {
+        Page26lock1(0)
+    }
+}
+#[doc = "Lock configuration LSBs for page 27 (rows 0x6c0 through 0x6ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Page27lock0(pub u32);
+impl Page27lock0 {
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub const fn key_w(&self) -> u8 {
+        let val = (self.0 >> 0usize) & 0x07;
+        val as u8
+    }
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub fn set_key_w(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x07 << 0usize)) | (((val as u32) & 0x07) << 0usize);
+    }
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub const fn key_r(&self) -> u8 {
+        let val = (self.0 >> 3usize) & 0x07;
+        val as u8
+    }
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub fn set_key_r(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x07 << 3usize)) | (((val as u32) & 0x07) << 3usize);
+    }
+    #[doc = "State when at least one key is registered for this page and no matching key has been entered."]
+    #[inline(always)]
+    pub const fn no_key_state(&self) -> super::vals::Page27lock0noKeyState {
+        let val = (self.0 >> 6usize) & 0x01;
+        super::vals::Page27lock0noKeyState::from_bits(val as u8)
+    }
+    #[doc = "State when at least one key is registered for this page and no matching key has been entered."]
+    #[inline(always)]
+    pub fn set_no_key_state(&mut self, val: super::vals::Page27lock0noKeyState) {
+        self.0 = (self.0 & !(0x01 << 6usize)) | (((val.to_bits() as u32) & 0x01) << 6usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r1(&self) -> u8 {
+        let val = (self.0 >> 8usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r1(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r2(&self) -> u8 {
+        let val = (self.0 >> 16usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r2(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize);
+    }
+}
+impl Default for Page27lock0 {
+    #[inline(always)]
+    fn default() -> Page27lock0 {
+        Page27lock0(0)
+    }
+}
+#[doc = "Lock configuration MSBs for page 27 (rows 0x6c0 through 0x6ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Page27lock1(pub u32);
+impl Page27lock1 {
+    #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."]
+    #[inline(always)]
+    pub const fn lock_s(&self) -> super::vals::Page27lock1lockS {
+        let val = (self.0 >> 0usize) & 0x03;
+        super::vals::Page27lock1lockS::from_bits(val as u8)
+    }
+    #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."]
+    #[inline(always)]
+    pub fn set_lock_s(&mut self, val: super::vals::Page27lock1lockS) {
+        self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize);
+    }
+    #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."]
+    #[inline(always)]
+    pub const fn lock_ns(&self) -> super::vals::Page27lock1lockNs {
+        let val = (self.0 >> 2usize) & 0x03;
+        super::vals::Page27lock1lockNs::from_bits(val as u8)
+    }
+    #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."]
+    #[inline(always)]
+    pub fn set_lock_ns(&mut self, val: super::vals::Page27lock1lockNs) {
+        self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize);
+    }
+    #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."]
+    #[inline(always)]
+    pub const fn lock_bl(&self) -> super::vals::Page27lock1lockBl {
+        let val = (self.0 >> 4usize) & 0x03;
+        super::vals::Page27lock1lockBl::from_bits(val as u8)
+    }
+    #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."]
+    #[inline(always)]
+    pub fn set_lock_bl(&mut self, val: super::vals::Page27lock1lockBl) {
+        self.0 = (self.0 & !(0x03 << 4usize)) | (((val.to_bits() as u32) & 0x03) << 4usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r1(&self) -> u8 {
+        let val = (self.0 >> 8usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r1(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r2(&self) -> u8 {
+        let val = (self.0 >> 16usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r2(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize);
+    }
+}
+impl Default for Page27lock1 {
+    #[inline(always)]
+    fn default() -> Page27lock1 {
+        Page27lock1(0)
+    }
+}
+#[doc = "Lock configuration LSBs for page 28 (rows 0x700 through 0x73f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Page28lock0(pub u32);
+impl Page28lock0 {
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub const fn key_w(&self) -> u8 {
+        let val = (self.0 >> 0usize) & 0x07;
+        val as u8
+    }
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub fn set_key_w(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x07 << 0usize)) | (((val as u32) & 0x07) << 0usize);
+    }
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub const fn key_r(&self) -> u8 {
+        let val = (self.0 >> 3usize) & 0x07;
+        val as u8
+    }
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub fn set_key_r(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x07 << 3usize)) | (((val as u32) & 0x07) << 3usize);
+    }
+    #[doc = "State when at least one key is registered for this page and no matching key has been entered."]
+    #[inline(always)]
+    pub const fn no_key_state(&self) -> super::vals::Page28lock0noKeyState {
+        let val = (self.0 >> 6usize) & 0x01;
+        super::vals::Page28lock0noKeyState::from_bits(val as u8)
+    }
+    #[doc = "State when at least one key is registered for this page and no matching key has been entered."]
+    #[inline(always)]
+    pub fn set_no_key_state(&mut self, val: super::vals::Page28lock0noKeyState) {
+        self.0 = (self.0 & !(0x01 << 6usize)) | (((val.to_bits() as u32) & 0x01) << 6usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r1(&self) -> u8 {
+        let val = (self.0 >> 8usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r1(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r2(&self) -> u8 {
+        let val = (self.0 >> 16usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r2(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize);
+    }
+}
+impl Default for Page28lock0 {
+    #[inline(always)]
+    fn default() -> Page28lock0 {
+        Page28lock0(0)
+    }
+}
+#[doc = "Lock configuration MSBs for page 28 (rows 0x700 through 0x73f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Page28lock1(pub u32);
+impl Page28lock1 {
+    #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."]
+    #[inline(always)]
+    pub const fn lock_s(&self) -> super::vals::Page28lock1lockS {
+        let val = (self.0 >> 0usize) & 0x03;
+        super::vals::Page28lock1lockS::from_bits(val as u8)
+    }
+    #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."]
+    #[inline(always)]
+    pub fn set_lock_s(&mut self, val: super::vals::Page28lock1lockS) {
+        self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize);
+    }
+    #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."]
+    #[inline(always)]
+    pub const fn lock_ns(&self) -> super::vals::Page28lock1lockNs {
+        let val = (self.0 >> 2usize) & 0x03;
+        super::vals::Page28lock1lockNs::from_bits(val as u8)
+    }
+    #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."]
+    #[inline(always)]
+    pub fn set_lock_ns(&mut self, val: super::vals::Page28lock1lockNs) {
+        self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize);
+    }
+    #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."]
+    #[inline(always)]
+    pub const fn lock_bl(&self) -> super::vals::Page28lock1lockBl {
+        let val = (self.0 >> 4usize) & 0x03;
+        super::vals::Page28lock1lockBl::from_bits(val as u8)
+    }
+    #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."]
+    #[inline(always)]
+    pub fn set_lock_bl(&mut self, val: super::vals::Page28lock1lockBl) {
+        self.0 = (self.0 & !(0x03 << 4usize)) | (((val.to_bits() as u32) & 0x03) << 4usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r1(&self) -> u8 {
+        let val = (self.0 >> 8usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r1(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r2(&self) -> u8 {
+        let val = (self.0 >> 16usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r2(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize);
+    }
+}
+impl Default for Page28lock1 {
+    #[inline(always)]
+    fn default() -> Page28lock1 {
+        Page28lock1(0)
+    }
+}
+#[doc = "Lock configuration LSBs for page 29 (rows 0x740 through 0x77f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Page29lock0(pub u32);
+impl Page29lock0 {
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub const fn key_w(&self) -> u8 {
+        let val = (self.0 >> 0usize) & 0x07;
+        val as u8
+    }
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub fn set_key_w(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x07 << 0usize)) | (((val as u32) & 0x07) << 0usize);
+    }
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub const fn key_r(&self) -> u8 {
+        let val = (self.0 >> 3usize) & 0x07;
+        val as u8
+    }
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub fn set_key_r(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x07 << 3usize)) | (((val as u32) & 0x07) << 3usize);
+    }
+    #[doc = "State when at least one key is registered for this page and no matching key has been entered."]
+    #[inline(always)]
+    pub const fn no_key_state(&self) -> super::vals::Page29lock0noKeyState {
+        let val = (self.0 >> 6usize) & 0x01;
+        super::vals::Page29lock0noKeyState::from_bits(val as u8)
+    }
+    #[doc = "State when at least one key is registered for this page and no matching key has been entered."]
+    #[inline(always)]
+    pub fn set_no_key_state(&mut self, val: super::vals::Page29lock0noKeyState) {
+        self.0 = (self.0 & !(0x01 << 6usize)) | (((val.to_bits() as u32) & 0x01) << 6usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r1(&self) -> u8 {
+        let val = (self.0 >> 8usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r1(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r2(&self) -> u8 {
+        let val = (self.0 >> 16usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r2(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize);
+    }
+}
+impl Default for Page29lock0 {
+    #[inline(always)]
+    fn default() -> Page29lock0 {
+        Page29lock0(0)
+    }
+}
+#[doc = "Lock configuration MSBs for page 29 (rows 0x740 through 0x77f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Page29lock1(pub u32);
+impl Page29lock1 {
+    #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."]
+    #[inline(always)]
+    pub const fn lock_s(&self) -> super::vals::Page29lock1lockS {
+        let val = (self.0 >> 0usize) & 0x03;
+        super::vals::Page29lock1lockS::from_bits(val as u8)
+    }
+    #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."]
+    #[inline(always)]
+    pub fn set_lock_s(&mut self, val: super::vals::Page29lock1lockS) {
+        self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize);
+    }
+    #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."]
+    #[inline(always)]
+    pub const fn lock_ns(&self) -> super::vals::Page29lock1lockNs {
+        let val = (self.0 >> 2usize) & 0x03;
+        super::vals::Page29lock1lockNs::from_bits(val as u8)
+    }
+    #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."]
+    #[inline(always)]
+    pub fn set_lock_ns(&mut self, val: super::vals::Page29lock1lockNs) {
+        self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize);
+    }
+    #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."]
+    #[inline(always)]
+    pub const fn lock_bl(&self) -> super::vals::Page29lock1lockBl {
+        let val = (self.0 >> 4usize) & 0x03;
+        super::vals::Page29lock1lockBl::from_bits(val as u8)
+    }
+    #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."]
+    #[inline(always)]
+    pub fn set_lock_bl(&mut self, val: super::vals::Page29lock1lockBl) {
+        self.0 = (self.0 & !(0x03 << 4usize)) | (((val.to_bits() as u32) & 0x03) << 4usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r1(&self) -> u8 {
+        let val = (self.0 >> 8usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r1(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r2(&self) -> u8 {
+        let val = (self.0 >> 16usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r2(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize);
+    }
+}
+impl Default for Page29lock1 {
+    #[inline(always)]
+    fn default() -> Page29lock1 {
+        Page29lock1(0)
+    }
+}
+#[doc = "Lock configuration LSBs for page 2 (rows 0x80 through 0xbf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Page2lock0(pub u32);
+impl Page2lock0 {
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub const fn key_w(&self) -> u8 {
+        let val = (self.0 >> 0usize) & 0x07;
+        val as u8
+    }
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub fn set_key_w(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x07 << 0usize)) | (((val as u32) & 0x07) << 0usize);
+    }
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub const fn key_r(&self) -> u8 {
+        let val = (self.0 >> 3usize) & 0x07;
+        val as u8
+    }
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub fn set_key_r(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x07 << 3usize)) | (((val as u32) & 0x07) << 3usize);
+    }
+    #[doc = "State when at least one key is registered for this page and no matching key has been entered."]
+    #[inline(always)]
+    pub const fn no_key_state(&self) -> super::vals::Page2lock0noKeyState {
+        let val = (self.0 >> 6usize) & 0x01;
+        super::vals::Page2lock0noKeyState::from_bits(val as u8)
+    }
+    #[doc = "State when at least one key is registered for this page and no matching key has been entered."]
+    #[inline(always)]
+    pub fn set_no_key_state(&mut self, val: super::vals::Page2lock0noKeyState) {
+        self.0 = (self.0 & !(0x01 << 6usize)) | (((val.to_bits() as u32) & 0x01) << 6usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r1(&self) -> u8 {
+        let val = (self.0 >> 8usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r1(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r2(&self) -> u8 {
+        let val = (self.0 >> 16usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r2(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize);
+    }
+}
+impl Default for Page2lock0 {
+    #[inline(always)]
+    fn default() -> Page2lock0 {
+        Page2lock0(0)
+    }
+}
+#[doc = "Lock configuration MSBs for page 2 (rows 0x80 through 0xbf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Page2lock1(pub u32);
+impl Page2lock1 {
+    #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."]
+    #[inline(always)]
+    pub const fn lock_s(&self) -> super::vals::Page2lock1lockS {
+        let val = (self.0 >> 0usize) & 0x03;
+        super::vals::Page2lock1lockS::from_bits(val as u8)
+    }
+    #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."]
+    #[inline(always)]
+    pub fn set_lock_s(&mut self, val: super::vals::Page2lock1lockS) {
+        self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize);
+    }
+    #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."]
+    #[inline(always)]
+    pub const fn lock_ns(&self) -> super::vals::Page2lock1lockNs {
+        let val = (self.0 >> 2usize) & 0x03;
+        super::vals::Page2lock1lockNs::from_bits(val as u8)
+    }
+    #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."]
+    #[inline(always)]
+    pub fn set_lock_ns(&mut self, val: super::vals::Page2lock1lockNs) {
+        self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize);
+    }
+    #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."]
+    #[inline(always)]
+    pub const fn lock_bl(&self) -> super::vals::Page2lock1lockBl {
+        let val = (self.0 >> 4usize) & 0x03;
+        super::vals::Page2lock1lockBl::from_bits(val as u8)
+    }
+    #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."]
+    #[inline(always)]
+    pub fn set_lock_bl(&mut self, val: super::vals::Page2lock1lockBl) {
+        self.0 = (self.0 & !(0x03 << 4usize)) | (((val.to_bits() as u32) & 0x03) << 4usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r1(&self) -> u8 {
+        let val = (self.0 >> 8usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r1(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r2(&self) -> u8 {
+        let val = (self.0 >> 16usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r2(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize);
+    }
+}
+impl Default for Page2lock1 {
+    #[inline(always)]
+    fn default() -> Page2lock1 {
+        Page2lock1(0)
+    }
+}
+#[doc = "Lock configuration LSBs for page 30 (rows 0x780 through 0x7bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Page30lock0(pub u32);
+impl Page30lock0 {
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub const fn key_w(&self) -> u8 {
+        let val = (self.0 >> 0usize) & 0x07;
+        val as u8
+    }
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub fn set_key_w(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x07 << 0usize)) | (((val as u32) & 0x07) << 0usize);
+    }
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub const fn key_r(&self) -> u8 {
+        let val = (self.0 >> 3usize) & 0x07;
+        val as u8
+    }
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub fn set_key_r(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x07 << 3usize)) | (((val as u32) & 0x07) << 3usize);
+    }
+    #[doc = "State when at least one key is registered for this page and no matching key has been entered."]
+    #[inline(always)]
+    pub const fn no_key_state(&self) -> super::vals::Page30lock0noKeyState {
+        let val = (self.0 >> 6usize) & 0x01;
+        super::vals::Page30lock0noKeyState::from_bits(val as u8)
+    }
+    #[doc = "State when at least one key is registered for this page and no matching key has been entered."]
+    #[inline(always)]
+    pub fn set_no_key_state(&mut self, val: super::vals::Page30lock0noKeyState) {
+        self.0 = (self.0 & !(0x01 << 6usize)) | (((val.to_bits() as u32) & 0x01) << 6usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r1(&self) -> u8 {
+        let val = (self.0 >> 8usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r1(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r2(&self) -> u8 {
+        let val = (self.0 >> 16usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r2(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize);
+    }
+}
+impl Default for Page30lock0 {
+    #[inline(always)]
+    fn default() -> Page30lock0 {
+        Page30lock0(0)
+    }
+}
+#[doc = "Lock configuration MSBs for page 30 (rows 0x780 through 0x7bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Page30lock1(pub u32);
+impl Page30lock1 {
+    #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."]
+    #[inline(always)]
+    pub const fn lock_s(&self) -> super::vals::Page30lock1lockS {
+        let val = (self.0 >> 0usize) & 0x03;
+        super::vals::Page30lock1lockS::from_bits(val as u8)
+    }
+    #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."]
+    #[inline(always)]
+    pub fn set_lock_s(&mut self, val: super::vals::Page30lock1lockS) {
+        self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize);
+    }
+    #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."]
+    #[inline(always)]
+    pub const fn lock_ns(&self) -> super::vals::Page30lock1lockNs {
+        let val = (self.0 >> 2usize) & 0x03;
+        super::vals::Page30lock1lockNs::from_bits(val as u8)
+    }
+    #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."]
+    #[inline(always)]
+    pub fn set_lock_ns(&mut self, val: super::vals::Page30lock1lockNs) {
+        self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize);
+    }
+    #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."]
+    #[inline(always)]
+    pub const fn lock_bl(&self) -> super::vals::Page30lock1lockBl {
+        let val = (self.0 >> 4usize) & 0x03;
+        super::vals::Page30lock1lockBl::from_bits(val as u8)
+    }
+    #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."]
+    #[inline(always)]
+    pub fn set_lock_bl(&mut self, val: super::vals::Page30lock1lockBl) {
+        self.0 = (self.0 & !(0x03 << 4usize)) | (((val.to_bits() as u32) & 0x03) << 4usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r1(&self) -> u8 {
+        let val = (self.0 >> 8usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r1(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r2(&self) -> u8 {
+        let val = (self.0 >> 16usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r2(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize);
+    }
+}
+impl Default for Page30lock1 {
+    #[inline(always)]
+    fn default() -> Page30lock1 {
+        Page30lock1(0)
+    }
+}
+#[doc = "Lock configuration LSBs for page 31 (rows 0x7c0 through 0x7ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Page31lock0(pub u32);
+impl Page31lock0 {
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub const fn key_w(&self) -> u8 {
+        let val = (self.0 >> 0usize) & 0x07;
+        val as u8
+    }
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub fn set_key_w(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x07 << 0usize)) | (((val as u32) & 0x07) << 0usize);
+    }
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub const fn key_r(&self) -> u8 {
+        let val = (self.0 >> 3usize) & 0x07;
+        val as u8
+    }
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub fn set_key_r(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x07 << 3usize)) | (((val as u32) & 0x07) << 3usize);
+    }
+    #[doc = "State when at least one key is registered for this page and no matching key has been entered."]
+    #[inline(always)]
+    pub const fn no_key_state(&self) -> super::vals::Page31lock0noKeyState {
+        let val = (self.0 >> 6usize) & 0x01;
+        super::vals::Page31lock0noKeyState::from_bits(val as u8)
+    }
+    #[doc = "State when at least one key is registered for this page and no matching key has been entered."]
+    #[inline(always)]
+    pub fn set_no_key_state(&mut self, val: super::vals::Page31lock0noKeyState) {
+        self.0 = (self.0 & !(0x01 << 6usize)) | (((val.to_bits() as u32) & 0x01) << 6usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r1(&self) -> u8 {
+        let val = (self.0 >> 8usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r1(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r2(&self) -> u8 {
+        let val = (self.0 >> 16usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r2(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize);
+    }
+}
+impl Default for Page31lock0 {
+    #[inline(always)]
+    fn default() -> Page31lock0 {
+        Page31lock0(0)
+    }
+}
+#[doc = "Lock configuration MSBs for page 31 (rows 0x7c0 through 0x7ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Page31lock1(pub u32);
+impl Page31lock1 {
+    #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."]
+    #[inline(always)]
+    pub const fn lock_s(&self) -> super::vals::Page31lock1lockS {
+        let val = (self.0 >> 0usize) & 0x03;
+        super::vals::Page31lock1lockS::from_bits(val as u8)
+    }
+    #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."]
+    #[inline(always)]
+    pub fn set_lock_s(&mut self, val: super::vals::Page31lock1lockS) {
+        self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize);
+    }
+    #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."]
+    #[inline(always)]
+    pub const fn lock_ns(&self) -> super::vals::Page31lock1lockNs {
+        let val = (self.0 >> 2usize) & 0x03;
+        super::vals::Page31lock1lockNs::from_bits(val as u8)
+    }
+    #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."]
+    #[inline(always)]
+    pub fn set_lock_ns(&mut self, val: super::vals::Page31lock1lockNs) {
+        self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize);
+    }
+    #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."]
+    #[inline(always)]
+    pub const fn lock_bl(&self) -> super::vals::Page31lock1lockBl {
+        let val = (self.0 >> 4usize) & 0x03;
+        super::vals::Page31lock1lockBl::from_bits(val as u8)
+    }
+    #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."]
+    #[inline(always)]
+    pub fn set_lock_bl(&mut self, val: super::vals::Page31lock1lockBl) {
+        self.0 = (self.0 & !(0x03 << 4usize)) | (((val.to_bits() as u32) & 0x03) << 4usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r1(&self) -> u8 {
+        let val = (self.0 >> 8usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r1(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r2(&self) -> u8 {
+        let val = (self.0 >> 16usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r2(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize);
+    }
+}
+impl Default for Page31lock1 {
+    #[inline(always)]
+    fn default() -> Page31lock1 {
+        Page31lock1(0)
+    }
+}
+#[doc = "Lock configuration LSBs for page 32 (rows 0x800 through 0x83f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Page32lock0(pub u32);
+impl Page32lock0 {
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub const fn key_w(&self) -> u8 {
+        let val = (self.0 >> 0usize) & 0x07;
+        val as u8
+    }
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub fn set_key_w(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x07 << 0usize)) | (((val as u32) & 0x07) << 0usize);
+    }
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub const fn key_r(&self) -> u8 {
+        let val = (self.0 >> 3usize) & 0x07;
+        val as u8
+    }
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub fn set_key_r(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x07 << 3usize)) | (((val as u32) & 0x07) << 3usize);
+    }
+    #[doc = "State when at least one key is registered for this page and no matching key has been entered."]
+    #[inline(always)]
+    pub const fn no_key_state(&self) -> super::vals::Page32lock0noKeyState {
+        let val = (self.0 >> 6usize) & 0x01;
+        super::vals::Page32lock0noKeyState::from_bits(val as u8)
+    }
+    #[doc = "State when at least one key is registered for this page and no matching key has been entered."]
+    #[inline(always)]
+    pub fn set_no_key_state(&mut self, val: super::vals::Page32lock0noKeyState) {
+        self.0 = (self.0 & !(0x01 << 6usize)) | (((val.to_bits() as u32) & 0x01) << 6usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r1(&self) -> u8 {
+        let val = (self.0 >> 8usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r1(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r2(&self) -> u8 {
+        let val = (self.0 >> 16usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r2(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize);
+    }
+}
+impl Default for Page32lock0 {
+    #[inline(always)]
+    fn default() -> Page32lock0 {
+        Page32lock0(0)
+    }
+}
+#[doc = "Lock configuration MSBs for page 32 (rows 0x800 through 0x83f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Page32lock1(pub u32);
+impl Page32lock1 {
+    #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."]
+    #[inline(always)]
+    pub const fn lock_s(&self) -> super::vals::Page32lock1lockS {
+        let val = (self.0 >> 0usize) & 0x03;
+        super::vals::Page32lock1lockS::from_bits(val as u8)
+    }
+    #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."]
+    #[inline(always)]
+    pub fn set_lock_s(&mut self, val: super::vals::Page32lock1lockS) {
+        self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize);
+    }
+    #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."]
+    #[inline(always)]
+    pub const fn lock_ns(&self) -> super::vals::Page32lock1lockNs {
+        let val = (self.0 >> 2usize) & 0x03;
+        super::vals::Page32lock1lockNs::from_bits(val as u8)
+    }
+    #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."]
+    #[inline(always)]
+    pub fn set_lock_ns(&mut self, val: super::vals::Page32lock1lockNs) {
+        self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize);
+    }
+    #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."]
+    #[inline(always)]
+    pub const fn lock_bl(&self) -> super::vals::Page32lock1lockBl {
+        let val = (self.0 >> 4usize) & 0x03;
+        super::vals::Page32lock1lockBl::from_bits(val as u8)
+    }
+    #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."]
+    #[inline(always)]
+    pub fn set_lock_bl(&mut self, val: super::vals::Page32lock1lockBl) {
+        self.0 = (self.0 & !(0x03 << 4usize)) | (((val.to_bits() as u32) & 0x03) << 4usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r1(&self) -> u8 {
+        let val = (self.0 >> 8usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r1(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r2(&self) -> u8 {
+        let val = (self.0 >> 16usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r2(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize);
+    }
+}
+impl Default for Page32lock1 {
+    #[inline(always)]
+    fn default() -> Page32lock1 {
+        Page32lock1(0)
+    }
+}
+#[doc = "Lock configuration LSBs for page 33 (rows 0x840 through 0x87f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Page33lock0(pub u32);
+impl Page33lock0 {
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub const fn key_w(&self) -> u8 {
+        let val = (self.0 >> 0usize) & 0x07;
+        val as u8
+    }
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub fn set_key_w(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x07 << 0usize)) | (((val as u32) & 0x07) << 0usize);
+    }
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub const fn key_r(&self) -> u8 {
+        let val = (self.0 >> 3usize) & 0x07;
+        val as u8
+    }
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub fn set_key_r(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x07 << 3usize)) | (((val as u32) & 0x07) << 3usize);
+    }
+    #[doc = "State when at least one key is registered for this page and no matching key has been entered."]
+    #[inline(always)]
+    pub const fn no_key_state(&self) -> super::vals::Page33lock0noKeyState {
+        let val = (self.0 >> 6usize) & 0x01;
+        super::vals::Page33lock0noKeyState::from_bits(val as u8)
+    }
+    #[doc = "State when at least one key is registered for this page and no matching key has been entered."]
+    #[inline(always)]
+    pub fn set_no_key_state(&mut self, val: super::vals::Page33lock0noKeyState) {
+        self.0 = (self.0 & !(0x01 << 6usize)) | (((val.to_bits() as u32) & 0x01) << 6usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r1(&self) -> u8 {
+        let val = (self.0 >> 8usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r1(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r2(&self) -> u8 {
+        let val = (self.0 >> 16usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r2(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize);
+    }
+}
+impl Default for Page33lock0 {
+    #[inline(always)]
+    fn default() -> Page33lock0 {
+        Page33lock0(0)
+    }
+}
+#[doc = "Lock configuration MSBs for page 33 (rows 0x840 through 0x87f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Page33lock1(pub u32);
+impl Page33lock1 {
+    #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."]
+    #[inline(always)]
+    pub const fn lock_s(&self) -> super::vals::Page33lock1lockS {
+        let val = (self.0 >> 0usize) & 0x03;
+        super::vals::Page33lock1lockS::from_bits(val as u8)
+    }
+    #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."]
+    #[inline(always)]
+    pub fn set_lock_s(&mut self, val: super::vals::Page33lock1lockS) {
+        self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize);
+    }
+    #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."]
+    #[inline(always)]
+    pub const fn lock_ns(&self) -> super::vals::Page33lock1lockNs {
+        let val = (self.0 >> 2usize) & 0x03;
+        super::vals::Page33lock1lockNs::from_bits(val as u8)
+    }
+    #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."]
+    #[inline(always)]
+    pub fn set_lock_ns(&mut self, val: super::vals::Page33lock1lockNs) {
+        self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize);
+    }
+    #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."]
+    #[inline(always)]
+    pub const fn lock_bl(&self) -> super::vals::Page33lock1lockBl {
+        let val = (self.0 >> 4usize) & 0x03;
+        super::vals::Page33lock1lockBl::from_bits(val as u8)
+    }
+    #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."]
+    #[inline(always)]
+    pub fn set_lock_bl(&mut self, val: super::vals::Page33lock1lockBl) {
+        self.0 = (self.0 & !(0x03 << 4usize)) | (((val.to_bits() as u32) & 0x03) << 4usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r1(&self) -> u8 {
+        let val = (self.0 >> 8usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r1(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r2(&self) -> u8 {
+        let val = (self.0 >> 16usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r2(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize);
+    }
+}
+impl Default for Page33lock1 {
+    #[inline(always)]
+    fn default() -> Page33lock1 {
+        Page33lock1(0)
+    }
+}
+#[doc = "Lock configuration LSBs for page 34 (rows 0x880 through 0x8bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Page34lock0(pub u32);
+impl Page34lock0 {
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub const fn key_w(&self) -> u8 {
+        let val = (self.0 >> 0usize) & 0x07;
+        val as u8
+    }
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub fn set_key_w(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x07 << 0usize)) | (((val as u32) & 0x07) << 0usize);
+    }
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub const fn key_r(&self) -> u8 {
+        let val = (self.0 >> 3usize) & 0x07;
+        val as u8
+    }
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub fn set_key_r(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x07 << 3usize)) | (((val as u32) & 0x07) << 3usize);
+    }
+    #[doc = "State when at least one key is registered for this page and no matching key has been entered."]
+    #[inline(always)]
+    pub const fn no_key_state(&self) -> super::vals::Page34lock0noKeyState {
+        let val = (self.0 >> 6usize) & 0x01;
+        super::vals::Page34lock0noKeyState::from_bits(val as u8)
+    }
+    #[doc = "State when at least one key is registered for this page and no matching key has been entered."]
+    #[inline(always)]
+    pub fn set_no_key_state(&mut self, val: super::vals::Page34lock0noKeyState) {
+        self.0 = (self.0 & !(0x01 << 6usize)) | (((val.to_bits() as u32) & 0x01) << 6usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r1(&self) -> u8 {
+        let val = (self.0 >> 8usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r1(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r2(&self) -> u8 {
+        let val = (self.0 >> 16usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r2(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize);
+    }
+}
+impl Default for Page34lock0 {
+    #[inline(always)]
+    fn default() -> Page34lock0 {
+        Page34lock0(0)
+    }
+}
+#[doc = "Lock configuration MSBs for page 34 (rows 0x880 through 0x8bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Page34lock1(pub u32);
+impl Page34lock1 {
+    #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."]
+    #[inline(always)]
+    pub const fn lock_s(&self) -> super::vals::Page34lock1lockS {
+        let val = (self.0 >> 0usize) & 0x03;
+        super::vals::Page34lock1lockS::from_bits(val as u8)
+    }
+    #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."]
+    #[inline(always)]
+    pub fn set_lock_s(&mut self, val: super::vals::Page34lock1lockS) {
+        self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize);
+    }
+    #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."]
+    #[inline(always)]
+    pub const fn lock_ns(&self) -> super::vals::Page34lock1lockNs {
+        let val = (self.0 >> 2usize) & 0x03;
+        super::vals::Page34lock1lockNs::from_bits(val as u8)
+    }
+    #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."]
+    #[inline(always)]
+    pub fn set_lock_ns(&mut self, val: super::vals::Page34lock1lockNs) {
+        self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize);
+    }
+    #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."]
+    #[inline(always)]
+    pub const fn lock_bl(&self) -> super::vals::Page34lock1lockBl {
+        let val = (self.0 >> 4usize) & 0x03;
+        super::vals::Page34lock1lockBl::from_bits(val as u8)
+    }
+    #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."]
+    #[inline(always)]
+    pub fn set_lock_bl(&mut self, val: super::vals::Page34lock1lockBl) {
+        self.0 = (self.0 & !(0x03 << 4usize)) | (((val.to_bits() as u32) & 0x03) << 4usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r1(&self) -> u8 {
+        let val = (self.0 >> 8usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r1(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r2(&self) -> u8 {
+        let val = (self.0 >> 16usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r2(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize);
+    }
+}
+impl Default for Page34lock1 {
+    #[inline(always)]
+    fn default() -> Page34lock1 {
+        Page34lock1(0)
+    }
+}
+#[doc = "Lock configuration LSBs for page 35 (rows 0x8c0 through 0x8ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Page35lock0(pub u32);
+impl Page35lock0 {
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub const fn key_w(&self) -> u8 {
+        let val = (self.0 >> 0usize) & 0x07;
+        val as u8
+    }
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub fn set_key_w(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x07 << 0usize)) | (((val as u32) & 0x07) << 0usize);
+    }
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub const fn key_r(&self) -> u8 {
+        let val = (self.0 >> 3usize) & 0x07;
+        val as u8
+    }
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub fn set_key_r(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x07 << 3usize)) | (((val as u32) & 0x07) << 3usize);
+    }
+    #[doc = "State when at least one key is registered for this page and no matching key has been entered."]
+    #[inline(always)]
+    pub const fn no_key_state(&self) -> super::vals::Page35lock0noKeyState {
+        let val = (self.0 >> 6usize) & 0x01;
+        super::vals::Page35lock0noKeyState::from_bits(val as u8)
+    }
+    #[doc = "State when at least one key is registered for this page and no matching key has been entered."]
+    #[inline(always)]
+    pub fn set_no_key_state(&mut self, val: super::vals::Page35lock0noKeyState) {
+        self.0 = (self.0 & !(0x01 << 6usize)) | (((val.to_bits() as u32) & 0x01) << 6usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r1(&self) -> u8 {
+        let val = (self.0 >> 8usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r1(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r2(&self) -> u8 {
+        let val = (self.0 >> 16usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r2(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize);
+    }
+}
+impl Default for Page35lock0 {
+    #[inline(always)]
+    fn default() -> Page35lock0 {
+        Page35lock0(0)
+    }
+}
+#[doc = "Lock configuration MSBs for page 35 (rows 0x8c0 through 0x8ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Page35lock1(pub u32);
+impl Page35lock1 {
+    #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."]
+    #[inline(always)]
+    pub const fn lock_s(&self) -> super::vals::Page35lock1lockS {
+        let val = (self.0 >> 0usize) & 0x03;
+        super::vals::Page35lock1lockS::from_bits(val as u8)
+    }
+    #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."]
+    #[inline(always)]
+    pub fn set_lock_s(&mut self, val: super::vals::Page35lock1lockS) {
+        self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize);
+    }
+    #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."]
+    #[inline(always)]
+    pub const fn lock_ns(&self) -> super::vals::Page35lock1lockNs {
+        let val = (self.0 >> 2usize) & 0x03;
+        super::vals::Page35lock1lockNs::from_bits(val as u8)
+    }
+    #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."]
+    #[inline(always)]
+    pub fn set_lock_ns(&mut self, val: super::vals::Page35lock1lockNs) {
+        self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize);
+    }
+    #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."]
+    #[inline(always)]
+    pub const fn lock_bl(&self) -> super::vals::Page35lock1lockBl {
+        let val = (self.0 >> 4usize) & 0x03;
+        super::vals::Page35lock1lockBl::from_bits(val as u8)
+    }
+    #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."]
+    #[inline(always)]
+    pub fn set_lock_bl(&mut self, val: super::vals::Page35lock1lockBl) {
+        self.0 = (self.0 & !(0x03 << 4usize)) | (((val.to_bits() as u32) & 0x03) << 4usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r1(&self) -> u8 {
+        let val = (self.0 >> 8usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r1(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r2(&self) -> u8 {
+        let val = (self.0 >> 16usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r2(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize);
+    }
+}
+impl Default for Page35lock1 {
+    #[inline(always)]
+    fn default() -> Page35lock1 {
+        Page35lock1(0)
+    }
+}
+#[doc = "Lock configuration LSBs for page 36 (rows 0x900 through 0x93f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Page36lock0(pub u32);
+impl Page36lock0 {
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub const fn key_w(&self) -> u8 {
+        let val = (self.0 >> 0usize) & 0x07;
+        val as u8
+    }
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub fn set_key_w(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x07 << 0usize)) | (((val as u32) & 0x07) << 0usize);
+    }
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub const fn key_r(&self) -> u8 {
+        let val = (self.0 >> 3usize) & 0x07;
+        val as u8
+    }
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub fn set_key_r(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x07 << 3usize)) | (((val as u32) & 0x07) << 3usize);
+    }
+    #[doc = "State when at least one key is registered for this page and no matching key has been entered."]
+    #[inline(always)]
+    pub const fn no_key_state(&self) -> super::vals::Page36lock0noKeyState {
+        let val = (self.0 >> 6usize) & 0x01;
+        super::vals::Page36lock0noKeyState::from_bits(val as u8)
+    }
+    #[doc = "State when at least one key is registered for this page and no matching key has been entered."]
+    #[inline(always)]
+    pub fn set_no_key_state(&mut self, val: super::vals::Page36lock0noKeyState) {
+        self.0 = (self.0 & !(0x01 << 6usize)) | (((val.to_bits() as u32) & 0x01) << 6usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r1(&self) -> u8 {
+        let val = (self.0 >> 8usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r1(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r2(&self) -> u8 {
+        let val = (self.0 >> 16usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r2(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize);
+    }
+}
+impl Default for Page36lock0 {
+    #[inline(always)]
+    fn default() -> Page36lock0 {
+        Page36lock0(0)
+    }
+}
+#[doc = "Lock configuration MSBs for page 36 (rows 0x900 through 0x93f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Page36lock1(pub u32);
+impl Page36lock1 {
+    #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."]
+    #[inline(always)]
+    pub const fn lock_s(&self) -> super::vals::Page36lock1lockS {
+        let val = (self.0 >> 0usize) & 0x03;
+        super::vals::Page36lock1lockS::from_bits(val as u8)
+    }
+    #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."]
+    #[inline(always)]
+    pub fn set_lock_s(&mut self, val: super::vals::Page36lock1lockS) {
+        self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize);
+    }
+    #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."]
+    #[inline(always)]
+    pub const fn lock_ns(&self) -> super::vals::Page36lock1lockNs {
+        let val = (self.0 >> 2usize) & 0x03;
+        super::vals::Page36lock1lockNs::from_bits(val as u8)
+    }
+    #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."]
+    #[inline(always)]
+    pub fn set_lock_ns(&mut self, val: super::vals::Page36lock1lockNs) {
+        self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize);
+    }
+    #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."]
+    #[inline(always)]
+    pub const fn lock_bl(&self) -> super::vals::Page36lock1lockBl {
+        let val = (self.0 >> 4usize) & 0x03;
+        super::vals::Page36lock1lockBl::from_bits(val as u8)
+    }
+    #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."]
+    #[inline(always)]
+    pub fn set_lock_bl(&mut self, val: super::vals::Page36lock1lockBl) {
+        self.0 = (self.0 & !(0x03 << 4usize)) | (((val.to_bits() as u32) & 0x03) << 4usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r1(&self) -> u8 {
+        let val = (self.0 >> 8usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r1(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r2(&self) -> u8 {
+        let val = (self.0 >> 16usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r2(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize);
+    }
+}
+impl Default for Page36lock1 {
+    #[inline(always)]
+    fn default() -> Page36lock1 {
+        Page36lock1(0)
+    }
+}
+#[doc = "Lock configuration LSBs for page 37 (rows 0x940 through 0x97f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Page37lock0(pub u32);
+impl Page37lock0 {
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub const fn key_w(&self) -> u8 {
+        let val = (self.0 >> 0usize) & 0x07;
+        val as u8
+    }
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub fn set_key_w(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x07 << 0usize)) | (((val as u32) & 0x07) << 0usize);
+    }
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub const fn key_r(&self) -> u8 {
+        let val = (self.0 >> 3usize) & 0x07;
+        val as u8
+    }
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub fn set_key_r(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x07 << 3usize)) | (((val as u32) & 0x07) << 3usize);
+    }
+    #[doc = "State when at least one key is registered for this page and no matching key has been entered."]
+    #[inline(always)]
+    pub const fn no_key_state(&self) -> super::vals::Page37lock0noKeyState {
+        let val = (self.0 >> 6usize) & 0x01;
+        super::vals::Page37lock0noKeyState::from_bits(val as u8)
+    }
+    #[doc = "State when at least one key is registered for this page and no matching key has been entered."]
+    #[inline(always)]
+    pub fn set_no_key_state(&mut self, val: super::vals::Page37lock0noKeyState) {
+        self.0 = (self.0 & !(0x01 << 6usize)) | (((val.to_bits() as u32) & 0x01) << 6usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r1(&self) -> u8 {
+        let val = (self.0 >> 8usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r1(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r2(&self) -> u8 {
+        let val = (self.0 >> 16usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r2(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize);
+    }
+}
+impl Default for Page37lock0 {
+    #[inline(always)]
+    fn default() -> Page37lock0 {
+        Page37lock0(0)
+    }
+}
+#[doc = "Lock configuration MSBs for page 37 (rows 0x940 through 0x97f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Page37lock1(pub u32);
+impl Page37lock1 {
+    #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."]
+    #[inline(always)]
+    pub const fn lock_s(&self) -> super::vals::Page37lock1lockS {
+        let val = (self.0 >> 0usize) & 0x03;
+        super::vals::Page37lock1lockS::from_bits(val as u8)
+    }
+    #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."]
+    #[inline(always)]
+    pub fn set_lock_s(&mut self, val: super::vals::Page37lock1lockS) {
+        self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize);
+    }
+    #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."]
+    #[inline(always)]
+    pub const fn lock_ns(&self) -> super::vals::Page37lock1lockNs {
+        let val = (self.0 >> 2usize) & 0x03;
+        super::vals::Page37lock1lockNs::from_bits(val as u8)
+    }
+    #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."]
+    #[inline(always)]
+    pub fn set_lock_ns(&mut self, val: super::vals::Page37lock1lockNs) {
+        self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize);
+    }
+    #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."]
+    #[inline(always)]
+    pub const fn lock_bl(&self) -> super::vals::Page37lock1lockBl {
+        let val = (self.0 >> 4usize) & 0x03;
+        super::vals::Page37lock1lockBl::from_bits(val as u8)
+    }
+    #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."]
+    #[inline(always)]
+    pub fn set_lock_bl(&mut self, val: super::vals::Page37lock1lockBl) {
+        self.0 = (self.0 & !(0x03 << 4usize)) | (((val.to_bits() as u32) & 0x03) << 4usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r1(&self) -> u8 {
+        let val = (self.0 >> 8usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r1(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r2(&self) -> u8 {
+        let val = (self.0 >> 16usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r2(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize);
+    }
+}
+impl Default for Page37lock1 {
+    #[inline(always)]
+    fn default() -> Page37lock1 {
+        Page37lock1(0)
+    }
+}
+#[doc = "Lock configuration LSBs for page 38 (rows 0x980 through 0x9bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Page38lock0(pub u32);
+impl Page38lock0 {
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub const fn key_w(&self) -> u8 {
+        let val = (self.0 >> 0usize) & 0x07;
+        val as u8
+    }
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub fn set_key_w(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x07 << 0usize)) | (((val as u32) & 0x07) << 0usize);
+    }
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub const fn key_r(&self) -> u8 {
+        let val = (self.0 >> 3usize) & 0x07;
+        val as u8
+    }
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub fn set_key_r(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x07 << 3usize)) | (((val as u32) & 0x07) << 3usize);
+    }
+    #[doc = "State when at least one key is registered for this page and no matching key has been entered."]
+    #[inline(always)]
+    pub const fn no_key_state(&self) -> super::vals::Page38lock0noKeyState {
+        let val = (self.0 >> 6usize) & 0x01;
+        super::vals::Page38lock0noKeyState::from_bits(val as u8)
+    }
+    #[doc = "State when at least one key is registered for this page and no matching key has been entered."]
+    #[inline(always)]
+    pub fn set_no_key_state(&mut self, val: super::vals::Page38lock0noKeyState) {
+        self.0 = (self.0 & !(0x01 << 6usize)) | (((val.to_bits() as u32) & 0x01) << 6usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r1(&self) -> u8 {
+        let val = (self.0 >> 8usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r1(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r2(&self) -> u8 {
+        let val = (self.0 >> 16usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r2(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize);
+    }
+}
+impl Default for Page38lock0 {
+    #[inline(always)]
+    fn default() -> Page38lock0 {
+        Page38lock0(0)
+    }
+}
+#[doc = "Lock configuration MSBs for page 38 (rows 0x980 through 0x9bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Page38lock1(pub u32);
+impl Page38lock1 {
+    #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."]
+    #[inline(always)]
+    pub const fn lock_s(&self) -> super::vals::Page38lock1lockS {
+        let val = (self.0 >> 0usize) & 0x03;
+        super::vals::Page38lock1lockS::from_bits(val as u8)
+    }
+    #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."]
+    #[inline(always)]
+    pub fn set_lock_s(&mut self, val: super::vals::Page38lock1lockS) {
+        self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize);
+    }
+    #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."]
+    #[inline(always)]
+    pub const fn lock_ns(&self) -> super::vals::Page38lock1lockNs {
+        let val = (self.0 >> 2usize) & 0x03;
+        super::vals::Page38lock1lockNs::from_bits(val as u8)
+    }
+    #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."]
+    #[inline(always)]
+    pub fn set_lock_ns(&mut self, val: super::vals::Page38lock1lockNs) {
+        self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize);
+    }
+    #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."]
+    #[inline(always)]
+    pub const fn lock_bl(&self) -> super::vals::Page38lock1lockBl {
+        let val = (self.0 >> 4usize) & 0x03;
+        super::vals::Page38lock1lockBl::from_bits(val as u8)
+    }
+    #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."]
+    #[inline(always)]
+    pub fn set_lock_bl(&mut self, val: super::vals::Page38lock1lockBl) {
+        self.0 = (self.0 & !(0x03 << 4usize)) | (((val.to_bits() as u32) & 0x03) << 4usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r1(&self) -> u8 {
+        let val = (self.0 >> 8usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r1(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r2(&self) -> u8 {
+        let val = (self.0 >> 16usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r2(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize);
+    }
+}
+impl Default for Page38lock1 {
+    #[inline(always)]
+    fn default() -> Page38lock1 {
+        Page38lock1(0)
+    }
+}
+#[doc = "Lock configuration LSBs for page 39 (rows 0x9c0 through 0x9ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Page39lock0(pub u32);
+impl Page39lock0 {
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub const fn key_w(&self) -> u8 {
+        let val = (self.0 >> 0usize) & 0x07;
+        val as u8
+    }
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub fn set_key_w(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x07 << 0usize)) | (((val as u32) & 0x07) << 0usize);
+    }
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub const fn key_r(&self) -> u8 {
+        let val = (self.0 >> 3usize) & 0x07;
+        val as u8
+    }
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub fn set_key_r(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x07 << 3usize)) | (((val as u32) & 0x07) << 3usize);
+    }
+    #[doc = "State when at least one key is registered for this page and no matching key has been entered."]
+    #[inline(always)]
+    pub const fn no_key_state(&self) -> super::vals::Page39lock0noKeyState {
+        let val = (self.0 >> 6usize) & 0x01;
+        super::vals::Page39lock0noKeyState::from_bits(val as u8)
+    }
+    #[doc = "State when at least one key is registered for this page and no matching key has been entered."]
+    #[inline(always)]
+    pub fn set_no_key_state(&mut self, val: super::vals::Page39lock0noKeyState) {
+        self.0 = (self.0 & !(0x01 << 6usize)) | (((val.to_bits() as u32) & 0x01) << 6usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r1(&self) -> u8 {
+        let val = (self.0 >> 8usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r1(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r2(&self) -> u8 {
+        let val = (self.0 >> 16usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r2(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize);
+    }
+}
+impl Default for Page39lock0 {
+    #[inline(always)]
+    fn default() -> Page39lock0 {
+        Page39lock0(0)
+    }
+}
+#[doc = "Lock configuration MSBs for page 39 (rows 0x9c0 through 0x9ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Page39lock1(pub u32);
+impl Page39lock1 {
+    #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."]
+    #[inline(always)]
+    pub const fn lock_s(&self) -> super::vals::Page39lock1lockS {
+        let val = (self.0 >> 0usize) & 0x03;
+        super::vals::Page39lock1lockS::from_bits(val as u8)
+    }
+    #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."]
+    #[inline(always)]
+    pub fn set_lock_s(&mut self, val: super::vals::Page39lock1lockS) {
+        self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize);
+    }
+    #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."]
+    #[inline(always)]
+    pub const fn lock_ns(&self) -> super::vals::Page39lock1lockNs {
+        let val = (self.0 >> 2usize) & 0x03;
+        super::vals::Page39lock1lockNs::from_bits(val as u8)
+    }
+    #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."]
+    #[inline(always)]
+    pub fn set_lock_ns(&mut self, val: super::vals::Page39lock1lockNs) {
+        self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize);
+    }
+    #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."]
+    #[inline(always)]
+    pub const fn lock_bl(&self) -> super::vals::Page39lock1lockBl {
+        let val = (self.0 >> 4usize) & 0x03;
+        super::vals::Page39lock1lockBl::from_bits(val as u8)
+    }
+    #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."]
+    #[inline(always)]
+    pub fn set_lock_bl(&mut self, val: super::vals::Page39lock1lockBl) {
+        self.0 = (self.0 & !(0x03 << 4usize)) | (((val.to_bits() as u32) & 0x03) << 4usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r1(&self) -> u8 {
+        let val = (self.0 >> 8usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r1(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r2(&self) -> u8 {
+        let val = (self.0 >> 16usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r2(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize);
+    }
+}
+impl Default for Page39lock1 {
+    #[inline(always)]
+    fn default() -> Page39lock1 {
+        Page39lock1(0)
+    }
+}
+#[doc = "Lock configuration LSBs for page 3 (rows 0xc0 through 0xff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Page3lock0(pub u32);
+impl Page3lock0 {
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub const fn key_w(&self) -> u8 {
+        let val = (self.0 >> 0usize) & 0x07;
+        val as u8
+    }
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub fn set_key_w(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x07 << 0usize)) | (((val as u32) & 0x07) << 0usize);
+    }
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub const fn key_r(&self) -> u8 {
+        let val = (self.0 >> 3usize) & 0x07;
+        val as u8
+    }
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub fn set_key_r(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x07 << 3usize)) | (((val as u32) & 0x07) << 3usize);
+    }
+    #[doc = "State when at least one key is registered for this page and no matching key has been entered."]
+    #[inline(always)]
+    pub const fn no_key_state(&self) -> super::vals::Page3lock0noKeyState {
+        let val = (self.0 >> 6usize) & 0x01;
+        super::vals::Page3lock0noKeyState::from_bits(val as u8)
+    }
+    #[doc = "State when at least one key is registered for this page and no matching key has been entered."]
+    #[inline(always)]
+    pub fn set_no_key_state(&mut self, val: super::vals::Page3lock0noKeyState) {
+        self.0 = (self.0 & !(0x01 << 6usize)) | (((val.to_bits() as u32) & 0x01) << 6usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r1(&self) -> u8 {
+        let val = (self.0 >> 8usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r1(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r2(&self) -> u8 {
+        let val = (self.0 >> 16usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r2(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize);
+    }
+}
+impl Default for Page3lock0 {
+    #[inline(always)]
+    fn default() -> Page3lock0 {
+        Page3lock0(0)
+    }
+}
+#[doc = "Lock configuration MSBs for page 3 (rows 0xc0 through 0xff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Page3lock1(pub u32);
+impl Page3lock1 {
+    #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."]
+    #[inline(always)]
+    pub const fn lock_s(&self) -> super::vals::Page3lock1lockS {
+        let val = (self.0 >> 0usize) & 0x03;
+        super::vals::Page3lock1lockS::from_bits(val as u8)
+    }
+    #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."]
+    #[inline(always)]
+    pub fn set_lock_s(&mut self, val: super::vals::Page3lock1lockS) {
+        self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize);
+    }
+    #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."]
+    #[inline(always)]
+    pub const fn lock_ns(&self) -> super::vals::Page3lock1lockNs {
+        let val = (self.0 >> 2usize) & 0x03;
+        super::vals::Page3lock1lockNs::from_bits(val as u8)
+    }
+    #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."]
+    #[inline(always)]
+    pub fn set_lock_ns(&mut self, val: super::vals::Page3lock1lockNs) {
+        self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize);
+    }
+    #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."]
+    #[inline(always)]
+    pub const fn lock_bl(&self) -> super::vals::Page3lock1lockBl {
+        let val = (self.0 >> 4usize) & 0x03;
+        super::vals::Page3lock1lockBl::from_bits(val as u8)
+    }
+    #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."]
+    #[inline(always)]
+    pub fn set_lock_bl(&mut self, val: super::vals::Page3lock1lockBl) {
+        self.0 = (self.0 & !(0x03 << 4usize)) | (((val.to_bits() as u32) & 0x03) << 4usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r1(&self) -> u8 {
+        let val = (self.0 >> 8usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r1(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r2(&self) -> u8 {
+        let val = (self.0 >> 16usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r2(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize);
+    }
+}
+impl Default for Page3lock1 {
+    #[inline(always)]
+    fn default() -> Page3lock1 {
+        Page3lock1(0)
+    }
+}
+#[doc = "Lock configuration LSBs for page 40 (rows 0xa00 through 0xa3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Page40lock0(pub u32);
+impl Page40lock0 {
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub const fn key_w(&self) -> u8 {
+        let val = (self.0 >> 0usize) & 0x07;
+        val as u8
+    }
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub fn set_key_w(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x07 << 0usize)) | (((val as u32) & 0x07) << 0usize);
+    }
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub const fn key_r(&self) -> u8 {
+        let val = (self.0 >> 3usize) & 0x07;
+        val as u8
+    }
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub fn set_key_r(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x07 << 3usize)) | (((val as u32) & 0x07) << 3usize);
+    }
+    #[doc = "State when at least one key is registered for this page and no matching key has been entered."]
+    #[inline(always)]
+    pub const fn no_key_state(&self) -> super::vals::Page40lock0noKeyState {
+        let val = (self.0 >> 6usize) & 0x01;
+        super::vals::Page40lock0noKeyState::from_bits(val as u8)
+    }
+    #[doc = "State when at least one key is registered for this page and no matching key has been entered."]
+    #[inline(always)]
+    pub fn set_no_key_state(&mut self, val: super::vals::Page40lock0noKeyState) {
+        self.0 = (self.0 & !(0x01 << 6usize)) | (((val.to_bits() as u32) & 0x01) << 6usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r1(&self) -> u8 {
+        let val = (self.0 >> 8usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r1(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r2(&self) -> u8 {
+        let val = (self.0 >> 16usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r2(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize);
+    }
+}
+impl Default for Page40lock0 {
+    #[inline(always)]
+    fn default() -> Page40lock0 {
+        Page40lock0(0)
+    }
+}
+#[doc = "Lock configuration MSBs for page 40 (rows 0xa00 through 0xa3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Page40lock1(pub u32);
+impl Page40lock1 {
+    #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."]
+    #[inline(always)]
+    pub const fn lock_s(&self) -> super::vals::Page40lock1lockS {
+        let val = (self.0 >> 0usize) & 0x03;
+        super::vals::Page40lock1lockS::from_bits(val as u8)
+    }
+    #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."]
+    #[inline(always)]
+    pub fn set_lock_s(&mut self, val: super::vals::Page40lock1lockS) {
+        self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize);
+    }
+    #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."]
+    #[inline(always)]
+    pub const fn lock_ns(&self) -> super::vals::Page40lock1lockNs {
+        let val = (self.0 >> 2usize) & 0x03;
+        super::vals::Page40lock1lockNs::from_bits(val as u8)
+    }
+    #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."]
+    #[inline(always)]
+    pub fn set_lock_ns(&mut self, val: super::vals::Page40lock1lockNs) {
+        self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize);
+    }
+    #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."]
+    #[inline(always)]
+    pub const fn lock_bl(&self) -> super::vals::Page40lock1lockBl {
+        let val = (self.0 >> 4usize) & 0x03;
+        super::vals::Page40lock1lockBl::from_bits(val as u8)
+    }
+    #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."]
+    #[inline(always)]
+    pub fn set_lock_bl(&mut self, val: super::vals::Page40lock1lockBl) {
+        self.0 = (self.0 & !(0x03 << 4usize)) | (((val.to_bits() as u32) & 0x03) << 4usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r1(&self) -> u8 {
+        let val = (self.0 >> 8usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r1(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r2(&self) -> u8 {
+        let val = (self.0 >> 16usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r2(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize);
+    }
+}
+impl Default for Page40lock1 {
+    #[inline(always)]
+    fn default() -> Page40lock1 {
+        Page40lock1(0)
+    }
+}
+#[doc = "Lock configuration LSBs for page 41 (rows 0xa40 through 0xa7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Page41lock0(pub u32);
+impl Page41lock0 {
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub const fn key_w(&self) -> u8 {
+        let val = (self.0 >> 0usize) & 0x07;
+        val as u8
+    }
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub fn set_key_w(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x07 << 0usize)) | (((val as u32) & 0x07) << 0usize);
+    }
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub const fn key_r(&self) -> u8 {
+        let val = (self.0 >> 3usize) & 0x07;
+        val as u8
+    }
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub fn set_key_r(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x07 << 3usize)) | (((val as u32) & 0x07) << 3usize);
+    }
+    #[doc = "State when at least one key is registered for this page and no matching key has been entered."]
+    #[inline(always)]
+    pub const fn no_key_state(&self) -> super::vals::Page41lock0noKeyState {
+        let val = (self.0 >> 6usize) & 0x01;
+        super::vals::Page41lock0noKeyState::from_bits(val as u8)
+    }
+    #[doc = "State when at least one key is registered for this page and no matching key has been entered."]
+    #[inline(always)]
+    pub fn set_no_key_state(&mut self, val: super::vals::Page41lock0noKeyState) {
+        self.0 = (self.0 & !(0x01 << 6usize)) | (((val.to_bits() as u32) & 0x01) << 6usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r1(&self) -> u8 {
+        let val = (self.0 >> 8usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r1(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r2(&self) -> u8 {
+        let val = (self.0 >> 16usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r2(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize);
+    }
+}
+impl Default for Page41lock0 {
+    #[inline(always)]
+    fn default() -> Page41lock0 {
+        Page41lock0(0)
+    }
+}
+#[doc = "Lock configuration MSBs for page 41 (rows 0xa40 through 0xa7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Page41lock1(pub u32);
+impl Page41lock1 {
+    #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."]
+    #[inline(always)]
+    pub const fn lock_s(&self) -> super::vals::Page41lock1lockS {
+        let val = (self.0 >> 0usize) & 0x03;
+        super::vals::Page41lock1lockS::from_bits(val as u8)
+    }
+    #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."]
+    #[inline(always)]
+    pub fn set_lock_s(&mut self, val: super::vals::Page41lock1lockS) {
+        self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize);
+    }
+    #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."]
+    #[inline(always)]
+    pub const fn lock_ns(&self) -> super::vals::Page41lock1lockNs {
+        let val = (self.0 >> 2usize) & 0x03;
+        super::vals::Page41lock1lockNs::from_bits(val as u8)
+    }
+    #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."]
+    #[inline(always)]
+    pub fn set_lock_ns(&mut self, val: super::vals::Page41lock1lockNs) {
+        self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize);
+    }
+    #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."]
+    #[inline(always)]
+    pub const fn lock_bl(&self) -> super::vals::Page41lock1lockBl {
+        let val = (self.0 >> 4usize) & 0x03;
+        super::vals::Page41lock1lockBl::from_bits(val as u8)
+    }
+    #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."]
+    #[inline(always)]
+    pub fn set_lock_bl(&mut self, val: super::vals::Page41lock1lockBl) {
+        self.0 = (self.0 & !(0x03 << 4usize)) | (((val.to_bits() as u32) & 0x03) << 4usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r1(&self) -> u8 {
+        let val = (self.0 >> 8usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r1(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r2(&self) -> u8 {
+        let val = (self.0 >> 16usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r2(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize);
+    }
+}
+impl Default for Page41lock1 {
+    #[inline(always)]
+    fn default() -> Page41lock1 {
+        Page41lock1(0)
+    }
+}
+#[doc = "Lock configuration LSBs for page 42 (rows 0xa80 through 0xabf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Page42lock0(pub u32);
+impl Page42lock0 {
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub const fn key_w(&self) -> u8 {
+        let val = (self.0 >> 0usize) & 0x07;
+        val as u8
+    }
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub fn set_key_w(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x07 << 0usize)) | (((val as u32) & 0x07) << 0usize);
+    }
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub const fn key_r(&self) -> u8 {
+        let val = (self.0 >> 3usize) & 0x07;
+        val as u8
+    }
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub fn set_key_r(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x07 << 3usize)) | (((val as u32) & 0x07) << 3usize);
+    }
+    #[doc = "State when at least one key is registered for this page and no matching key has been entered."]
+    #[inline(always)]
+    pub const fn no_key_state(&self) -> super::vals::Page42lock0noKeyState {
+        let val = (self.0 >> 6usize) & 0x01;
+        super::vals::Page42lock0noKeyState::from_bits(val as u8)
+    }
+    #[doc = "State when at least one key is registered for this page and no matching key has been entered."]
+    #[inline(always)]
+    pub fn set_no_key_state(&mut self, val: super::vals::Page42lock0noKeyState) {
+        self.0 = (self.0 & !(0x01 << 6usize)) | (((val.to_bits() as u32) & 0x01) << 6usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r1(&self) -> u8 {
+        let val = (self.0 >> 8usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r1(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r2(&self) -> u8 {
+        let val = (self.0 >> 16usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r2(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize);
+    }
+}
+impl Default for Page42lock0 {
+    #[inline(always)]
+    fn default() -> Page42lock0 {
+        Page42lock0(0)
+    }
+}
+#[doc = "Lock configuration MSBs for page 42 (rows 0xa80 through 0xabf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Page42lock1(pub u32);
+impl Page42lock1 {
+    #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."]
+    #[inline(always)]
+    pub const fn lock_s(&self) -> super::vals::Page42lock1lockS {
+        let val = (self.0 >> 0usize) & 0x03;
+        super::vals::Page42lock1lockS::from_bits(val as u8)
+    }
+    #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."]
+    #[inline(always)]
+    pub fn set_lock_s(&mut self, val: super::vals::Page42lock1lockS) {
+        self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize);
+    }
+    #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."]
+    #[inline(always)]
+    pub const fn lock_ns(&self) -> super::vals::Page42lock1lockNs {
+        let val = (self.0 >> 2usize) & 0x03;
+        super::vals::Page42lock1lockNs::from_bits(val as u8)
+    }
+    #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."]
+    #[inline(always)]
+    pub fn set_lock_ns(&mut self, val: super::vals::Page42lock1lockNs) {
+        self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize);
+    }
+    #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."]
+    #[inline(always)]
+    pub const fn lock_bl(&self) -> super::vals::Page42lock1lockBl {
+        let val = (self.0 >> 4usize) & 0x03;
+        super::vals::Page42lock1lockBl::from_bits(val as u8)
+    }
+    #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."]
+    #[inline(always)]
+    pub fn set_lock_bl(&mut self, val: super::vals::Page42lock1lockBl) {
+        self.0 = (self.0 & !(0x03 << 4usize)) | (((val.to_bits() as u32) & 0x03) << 4usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r1(&self) -> u8 {
+        let val = (self.0 >> 8usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r1(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r2(&self) -> u8 {
+        let val = (self.0 >> 16usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r2(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize);
+    }
+}
+impl Default for Page42lock1 {
+    #[inline(always)]
+    fn default() -> Page42lock1 {
+        Page42lock1(0)
+    }
+}
+#[doc = "Lock configuration LSBs for page 43 (rows 0xac0 through 0xaff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Page43lock0(pub u32);
+impl Page43lock0 {
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub const fn key_w(&self) -> u8 {
+        let val = (self.0 >> 0usize) & 0x07;
+        val as u8
+    }
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub fn set_key_w(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x07 << 0usize)) | (((val as u32) & 0x07) << 0usize);
+    }
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub const fn key_r(&self) -> u8 {
+        let val = (self.0 >> 3usize) & 0x07;
+        val as u8
+    }
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub fn set_key_r(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x07 << 3usize)) | (((val as u32) & 0x07) << 3usize);
+    }
+    #[doc = "State when at least one key is registered for this page and no matching key has been entered."]
+    #[inline(always)]
+    pub const fn no_key_state(&self) -> super::vals::Page43lock0noKeyState {
+        let val = (self.0 >> 6usize) & 0x01;
+        super::vals::Page43lock0noKeyState::from_bits(val as u8)
+    }
+    #[doc = "State when at least one key is registered for this page and no matching key has been entered."]
+    #[inline(always)]
+    pub fn set_no_key_state(&mut self, val: super::vals::Page43lock0noKeyState) {
+        self.0 = (self.0 & !(0x01 << 6usize)) | (((val.to_bits() as u32) & 0x01) << 6usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r1(&self) -> u8 {
+        let val = (self.0 >> 8usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r1(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r2(&self) -> u8 {
+        let val = (self.0 >> 16usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r2(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize);
+    }
+}
+impl Default for Page43lock0 {
+    #[inline(always)]
+    fn default() -> Page43lock0 {
+        Page43lock0(0)
+    }
+}
+#[doc = "Lock configuration MSBs for page 43 (rows 0xac0 through 0xaff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Page43lock1(pub u32);
+impl Page43lock1 {
+    #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."]
+    #[inline(always)]
+    pub const fn lock_s(&self) -> super::vals::Page43lock1lockS {
+        let val = (self.0 >> 0usize) & 0x03;
+        super::vals::Page43lock1lockS::from_bits(val as u8)
+    }
+    #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."]
+    #[inline(always)]
+    pub fn set_lock_s(&mut self, val: super::vals::Page43lock1lockS) {
+        self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize);
+    }
+    #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."]
+    #[inline(always)]
+    pub const fn lock_ns(&self) -> super::vals::Page43lock1lockNs {
+        let val = (self.0 >> 2usize) & 0x03;
+        super::vals::Page43lock1lockNs::from_bits(val as u8)
+    }
+    #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."]
+    #[inline(always)]
+    pub fn set_lock_ns(&mut self, val: super::vals::Page43lock1lockNs) {
+        self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize);
+    }
+    #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."]
+    #[inline(always)]
+    pub const fn lock_bl(&self) -> super::vals::Page43lock1lockBl {
+        let val = (self.0 >> 4usize) & 0x03;
+        super::vals::Page43lock1lockBl::from_bits(val as u8)
+    }
+    #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."]
+    #[inline(always)]
+    pub fn set_lock_bl(&mut self, val: super::vals::Page43lock1lockBl) {
+        self.0 = (self.0 & !(0x03 << 4usize)) | (((val.to_bits() as u32) & 0x03) << 4usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r1(&self) -> u8 {
+        let val = (self.0 >> 8usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r1(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r2(&self) -> u8 {
+        let val = (self.0 >> 16usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r2(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize);
+    }
+}
+impl Default for Page43lock1 {
+    #[inline(always)]
+    fn default() -> Page43lock1 {
+        Page43lock1(0)
+    }
+}
+#[doc = "Lock configuration LSBs for page 44 (rows 0xb00 through 0xb3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Page44lock0(pub u32);
+impl Page44lock0 {
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub const fn key_w(&self) -> u8 {
+        let val = (self.0 >> 0usize) & 0x07;
+        val as u8
+    }
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub fn set_key_w(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x07 << 0usize)) | (((val as u32) & 0x07) << 0usize);
+    }
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub const fn key_r(&self) -> u8 {
+        let val = (self.0 >> 3usize) & 0x07;
+        val as u8
+    }
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub fn set_key_r(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x07 << 3usize)) | (((val as u32) & 0x07) << 3usize);
+    }
+    #[doc = "State when at least one key is registered for this page and no matching key has been entered."]
+    #[inline(always)]
+    pub const fn no_key_state(&self) -> super::vals::Page44lock0noKeyState {
+        let val = (self.0 >> 6usize) & 0x01;
+        super::vals::Page44lock0noKeyState::from_bits(val as u8)
+    }
+    #[doc = "State when at least one key is registered for this page and no matching key has been entered."]
+    #[inline(always)]
+    pub fn set_no_key_state(&mut self, val: super::vals::Page44lock0noKeyState) {
+        self.0 = (self.0 & !(0x01 << 6usize)) | (((val.to_bits() as u32) & 0x01) << 6usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r1(&self) -> u8 {
+        let val = (self.0 >> 8usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r1(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r2(&self) -> u8 {
+        let val = (self.0 >> 16usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r2(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize);
+    }
+}
+impl Default for Page44lock0 {
+    #[inline(always)]
+    fn default() -> Page44lock0 {
+        Page44lock0(0)
+    }
+}
+#[doc = "Lock configuration MSBs for page 44 (rows 0xb00 through 0xb3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Page44lock1(pub u32);
+impl Page44lock1 {
+    #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."]
+    #[inline(always)]
+    pub const fn lock_s(&self) -> super::vals::Page44lock1lockS {
+        let val = (self.0 >> 0usize) & 0x03;
+        super::vals::Page44lock1lockS::from_bits(val as u8)
+    }
+    #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."]
+    #[inline(always)]
+    pub fn set_lock_s(&mut self, val: super::vals::Page44lock1lockS) {
+        self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize);
+    }
+    #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."]
+    #[inline(always)]
+    pub const fn lock_ns(&self) -> super::vals::Page44lock1lockNs {
+        let val = (self.0 >> 2usize) & 0x03;
+        super::vals::Page44lock1lockNs::from_bits(val as u8)
+    }
+    #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."]
+    #[inline(always)]
+    pub fn set_lock_ns(&mut self, val: super::vals::Page44lock1lockNs) {
+        self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize);
+    }
+    #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."]
+    #[inline(always)]
+    pub const fn lock_bl(&self) -> super::vals::Page44lock1lockBl {
+        let val = (self.0 >> 4usize) & 0x03;
+        super::vals::Page44lock1lockBl::from_bits(val as u8)
+    }
+    #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."]
+    #[inline(always)]
+    pub fn set_lock_bl(&mut self, val: super::vals::Page44lock1lockBl) {
+        self.0 = (self.0 & !(0x03 << 4usize)) | (((val.to_bits() as u32) & 0x03) << 4usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r1(&self) -> u8 {
+        let val = (self.0 >> 8usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r1(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r2(&self) -> u8 {
+        let val = (self.0 >> 16usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r2(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize);
+    }
+}
+impl Default for Page44lock1 {
+    #[inline(always)]
+    fn default() -> Page44lock1 {
+        Page44lock1(0)
+    }
+}
+#[doc = "Lock configuration LSBs for page 45 (rows 0xb40 through 0xb7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Page45lock0(pub u32);
+impl Page45lock0 {
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub const fn key_w(&self) -> u8 {
+        let val = (self.0 >> 0usize) & 0x07;
+        val as u8
+    }
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub fn set_key_w(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x07 << 0usize)) | (((val as u32) & 0x07) << 0usize);
+    }
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub const fn key_r(&self) -> u8 {
+        let val = (self.0 >> 3usize) & 0x07;
+        val as u8
+    }
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub fn set_key_r(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x07 << 3usize)) | (((val as u32) & 0x07) << 3usize);
+    }
+    #[doc = "State when at least one key is registered for this page and no matching key has been entered."]
+    #[inline(always)]
+    pub const fn no_key_state(&self) -> super::vals::Page45lock0noKeyState {
+        let val = (self.0 >> 6usize) & 0x01;
+        super::vals::Page45lock0noKeyState::from_bits(val as u8)
+    }
+    #[doc = "State when at least one key is registered for this page and no matching key has been entered."]
+    #[inline(always)]
+    pub fn set_no_key_state(&mut self, val: super::vals::Page45lock0noKeyState) {
+        self.0 = (self.0 & !(0x01 << 6usize)) | (((val.to_bits() as u32) & 0x01) << 6usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r1(&self) -> u8 {
+        let val = (self.0 >> 8usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r1(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r2(&self) -> u8 {
+        let val = (self.0 >> 16usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r2(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize);
+    }
+}
+impl Default for Page45lock0 {
+    #[inline(always)]
+    fn default() -> Page45lock0 {
+        Page45lock0(0)
+    }
+}
+#[doc = "Lock configuration MSBs for page 45 (rows 0xb40 through 0xb7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Page45lock1(pub u32);
+impl Page45lock1 {
+    #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."]
+    #[inline(always)]
+    pub const fn lock_s(&self) -> super::vals::Page45lock1lockS {
+        let val = (self.0 >> 0usize) & 0x03;
+        super::vals::Page45lock1lockS::from_bits(val as u8)
+    }
+    #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."]
+    #[inline(always)]
+    pub fn set_lock_s(&mut self, val: super::vals::Page45lock1lockS) {
+        self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize);
+    }
+    #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."]
+    #[inline(always)]
+    pub const fn lock_ns(&self) -> super::vals::Page45lock1lockNs {
+        let val = (self.0 >> 2usize) & 0x03;
+        super::vals::Page45lock1lockNs::from_bits(val as u8)
+    }
+    #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."]
+    #[inline(always)]
+    pub fn set_lock_ns(&mut self, val: super::vals::Page45lock1lockNs) {
+        self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize);
+    }
+    #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."]
+    #[inline(always)]
+    pub const fn lock_bl(&self) -> super::vals::Page45lock1lockBl {
+        let val = (self.0 >> 4usize) & 0x03;
+        super::vals::Page45lock1lockBl::from_bits(val as u8)
+    }
+    #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."]
+    #[inline(always)]
+    pub fn set_lock_bl(&mut self, val: super::vals::Page45lock1lockBl) {
+        self.0 = (self.0 & !(0x03 << 4usize)) | (((val.to_bits() as u32) & 0x03) << 4usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r1(&self) -> u8 {
+        let val = (self.0 >> 8usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r1(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r2(&self) -> u8 {
+        let val = (self.0 >> 16usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r2(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize);
+    }
+}
+impl Default for Page45lock1 {
+    #[inline(always)]
+    fn default() -> Page45lock1 {
+        Page45lock1(0)
+    }
+}
+#[doc = "Lock configuration LSBs for page 46 (rows 0xb80 through 0xbbf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Page46lock0(pub u32);
+impl Page46lock0 {
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub const fn key_w(&self) -> u8 {
+        let val = (self.0 >> 0usize) & 0x07;
+        val as u8
+    }
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub fn set_key_w(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x07 << 0usize)) | (((val as u32) & 0x07) << 0usize);
+    }
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub const fn key_r(&self) -> u8 {
+        let val = (self.0 >> 3usize) & 0x07;
+        val as u8
+    }
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub fn set_key_r(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x07 << 3usize)) | (((val as u32) & 0x07) << 3usize);
+    }
+    #[doc = "State when at least one key is registered for this page and no matching key has been entered."]
+    #[inline(always)]
+    pub const fn no_key_state(&self) -> super::vals::Page46lock0noKeyState {
+        let val = (self.0 >> 6usize) & 0x01;
+        super::vals::Page46lock0noKeyState::from_bits(val as u8)
+    }
+    #[doc = "State when at least one key is registered for this page and no matching key has been entered."]
+    #[inline(always)]
+    pub fn set_no_key_state(&mut self, val: super::vals::Page46lock0noKeyState) {
+        self.0 = (self.0 & !(0x01 << 6usize)) | (((val.to_bits() as u32) & 0x01) << 6usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r1(&self) -> u8 {
+        let val = (self.0 >> 8usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r1(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r2(&self) -> u8 {
+        let val = (self.0 >> 16usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r2(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize);
+    }
+}
+impl Default for Page46lock0 {
+    #[inline(always)]
+    fn default() -> Page46lock0 {
+        Page46lock0(0)
+    }
+}
+#[doc = "Lock configuration MSBs for page 46 (rows 0xb80 through 0xbbf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Page46lock1(pub u32);
+impl Page46lock1 {
+    #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."]
+    #[inline(always)]
+    pub const fn lock_s(&self) -> super::vals::Page46lock1lockS {
+        let val = (self.0 >> 0usize) & 0x03;
+        super::vals::Page46lock1lockS::from_bits(val as u8)
+    }
+    #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."]
+    #[inline(always)]
+    pub fn set_lock_s(&mut self, val: super::vals::Page46lock1lockS) {
+        self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize);
+    }
+    #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."]
+    #[inline(always)]
+    pub const fn lock_ns(&self) -> super::vals::Page46lock1lockNs {
+        let val = (self.0 >> 2usize) & 0x03;
+        super::vals::Page46lock1lockNs::from_bits(val as u8)
+    }
+    #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."]
+    #[inline(always)]
+    pub fn set_lock_ns(&mut self, val: super::vals::Page46lock1lockNs) {
+        self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize);
+    }
+    #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."]
+    #[inline(always)]
+    pub const fn lock_bl(&self) -> super::vals::Page46lock1lockBl {
+        let val = (self.0 >> 4usize) & 0x03;
+        super::vals::Page46lock1lockBl::from_bits(val as u8)
+    }
+    #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."]
+    #[inline(always)]
+    pub fn set_lock_bl(&mut self, val: super::vals::Page46lock1lockBl) {
+        self.0 = (self.0 & !(0x03 << 4usize)) | (((val.to_bits() as u32) & 0x03) << 4usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r1(&self) -> u8 {
+        let val = (self.0 >> 8usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r1(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r2(&self) -> u8 {
+        let val = (self.0 >> 16usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r2(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize);
+    }
+}
+impl Default for Page46lock1 {
+    #[inline(always)]
+    fn default() -> Page46lock1 {
+        Page46lock1(0)
+    }
+}
+#[doc = "Lock configuration LSBs for page 47 (rows 0xbc0 through 0xbff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Page47lock0(pub u32);
+impl Page47lock0 {
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub const fn key_w(&self) -> u8 {
+        let val = (self.0 >> 0usize) & 0x07;
+        val as u8
+    }
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub fn set_key_w(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x07 << 0usize)) | (((val as u32) & 0x07) << 0usize);
+    }
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub const fn key_r(&self) -> u8 {
+        let val = (self.0 >> 3usize) & 0x07;
+        val as u8
+    }
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub fn set_key_r(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x07 << 3usize)) | (((val as u32) & 0x07) << 3usize);
+    }
+    #[doc = "State when at least one key is registered for this page and no matching key has been entered."]
+    #[inline(always)]
+    pub const fn no_key_state(&self) -> super::vals::Page47lock0noKeyState {
+        let val = (self.0 >> 6usize) & 0x01;
+        super::vals::Page47lock0noKeyState::from_bits(val as u8)
+    }
+    #[doc = "State when at least one key is registered for this page and no matching key has been entered."]
+    #[inline(always)]
+    pub fn set_no_key_state(&mut self, val: super::vals::Page47lock0noKeyState) {
+        self.0 = (self.0 & !(0x01 << 6usize)) | (((val.to_bits() as u32) & 0x01) << 6usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r1(&self) -> u8 {
+        let val = (self.0 >> 8usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r1(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r2(&self) -> u8 {
+        let val = (self.0 >> 16usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r2(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize);
+    }
+}
+impl Default for Page47lock0 {
+    #[inline(always)]
+    fn default() -> Page47lock0 {
+        Page47lock0(0)
+    }
+}
+#[doc = "Lock configuration MSBs for page 47 (rows 0xbc0 through 0xbff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Page47lock1(pub u32);
+impl Page47lock1 {
+    #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."]
+    #[inline(always)]
+    pub const fn lock_s(&self) -> super::vals::Page47lock1lockS {
+        let val = (self.0 >> 0usize) & 0x03;
+        super::vals::Page47lock1lockS::from_bits(val as u8)
+    }
+    #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."]
+    #[inline(always)]
+    pub fn set_lock_s(&mut self, val: super::vals::Page47lock1lockS) {
+        self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize);
+    }
+    #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."]
+    #[inline(always)]
+    pub const fn lock_ns(&self) -> super::vals::Page47lock1lockNs {
+        let val = (self.0 >> 2usize) & 0x03;
+        super::vals::Page47lock1lockNs::from_bits(val as u8)
+    }
+    #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."]
+    #[inline(always)]
+    pub fn set_lock_ns(&mut self, val: super::vals::Page47lock1lockNs) {
+        self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize);
+    }
+    #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."]
+    #[inline(always)]
+    pub const fn lock_bl(&self) -> super::vals::Page47lock1lockBl {
+        let val = (self.0 >> 4usize) & 0x03;
+        super::vals::Page47lock1lockBl::from_bits(val as u8)
+    }
+    #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."]
+    #[inline(always)]
+    pub fn set_lock_bl(&mut self, val: super::vals::Page47lock1lockBl) {
+        self.0 = (self.0 & !(0x03 << 4usize)) | (((val.to_bits() as u32) & 0x03) << 4usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r1(&self) -> u8 {
+        let val = (self.0 >> 8usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r1(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r2(&self) -> u8 {
+        let val = (self.0 >> 16usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r2(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize);
+    }
+}
+impl Default for Page47lock1 {
+    #[inline(always)]
+    fn default() -> Page47lock1 {
+        Page47lock1(0)
+    }
+}
+#[doc = "Lock configuration LSBs for page 48 (rows 0xc00 through 0xc3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Page48lock0(pub u32);
+impl Page48lock0 {
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub const fn key_w(&self) -> u8 {
+        let val = (self.0 >> 0usize) & 0x07;
+        val as u8
+    }
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub fn set_key_w(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x07 << 0usize)) | (((val as u32) & 0x07) << 0usize);
+    }
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub const fn key_r(&self) -> u8 {
+        let val = (self.0 >> 3usize) & 0x07;
+        val as u8
+    }
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub fn set_key_r(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x07 << 3usize)) | (((val as u32) & 0x07) << 3usize);
+    }
+    #[doc = "State when at least one key is registered for this page and no matching key has been entered."]
+    #[inline(always)]
+    pub const fn no_key_state(&self) -> super::vals::Page48lock0noKeyState {
+        let val = (self.0 >> 6usize) & 0x01;
+        super::vals::Page48lock0noKeyState::from_bits(val as u8)
+    }
+    #[doc = "State when at least one key is registered for this page and no matching key has been entered."]
+    #[inline(always)]
+    pub fn set_no_key_state(&mut self, val: super::vals::Page48lock0noKeyState) {
+        self.0 = (self.0 & !(0x01 << 6usize)) | (((val.to_bits() as u32) & 0x01) << 6usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r1(&self) -> u8 {
+        let val = (self.0 >> 8usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r1(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r2(&self) -> u8 {
+        let val = (self.0 >> 16usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r2(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize);
+    }
+}
+impl Default for Page48lock0 {
+    #[inline(always)]
+    fn default() -> Page48lock0 {
+        Page48lock0(0)
+    }
+}
+#[doc = "Lock configuration MSBs for page 48 (rows 0xc00 through 0xc3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Page48lock1(pub u32);
+impl Page48lock1 {
+    #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."]
+    #[inline(always)]
+    pub const fn lock_s(&self) -> super::vals::Page48lock1lockS {
+        let val = (self.0 >> 0usize) & 0x03;
+        super::vals::Page48lock1lockS::from_bits(val as u8)
+    }
+    #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."]
+    #[inline(always)]
+    pub fn set_lock_s(&mut self, val: super::vals::Page48lock1lockS) {
+        self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize);
+    }
+    #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."]
+    #[inline(always)]
+    pub const fn lock_ns(&self) -> super::vals::Page48lock1lockNs {
+        let val = (self.0 >> 2usize) & 0x03;
+        super::vals::Page48lock1lockNs::from_bits(val as u8)
+    }
+    #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."]
+    #[inline(always)]
+    pub fn set_lock_ns(&mut self, val: super::vals::Page48lock1lockNs) {
+        self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize);
+    }
+    #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."]
+    #[inline(always)]
+    pub const fn lock_bl(&self) -> super::vals::Page48lock1lockBl {
+        let val = (self.0 >> 4usize) & 0x03;
+        super::vals::Page48lock1lockBl::from_bits(val as u8)
+    }
+    #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."]
+    #[inline(always)]
+    pub fn set_lock_bl(&mut self, val: super::vals::Page48lock1lockBl) {
+        self.0 = (self.0 & !(0x03 << 4usize)) | (((val.to_bits() as u32) & 0x03) << 4usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r1(&self) -> u8 {
+        let val = (self.0 >> 8usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r1(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r2(&self) -> u8 {
+        let val = (self.0 >> 16usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r2(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize);
+    }
+}
+impl Default for Page48lock1 {
+    #[inline(always)]
+    fn default() -> Page48lock1 {
+        Page48lock1(0)
+    }
+}
+#[doc = "Lock configuration LSBs for page 49 (rows 0xc40 through 0xc7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Page49lock0(pub u32);
+impl Page49lock0 {
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub const fn key_w(&self) -> u8 {
+        let val = (self.0 >> 0usize) & 0x07;
+        val as u8
+    }
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub fn set_key_w(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x07 << 0usize)) | (((val as u32) & 0x07) << 0usize);
+    }
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub const fn key_r(&self) -> u8 {
+        let val = (self.0 >> 3usize) & 0x07;
+        val as u8
+    }
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub fn set_key_r(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x07 << 3usize)) | (((val as u32) & 0x07) << 3usize);
+    }
+    #[doc = "State when at least one key is registered for this page and no matching key has been entered."]
+    #[inline(always)]
+    pub const fn no_key_state(&self) -> super::vals::Page49lock0noKeyState {
+        let val = (self.0 >> 6usize) & 0x01;
+        super::vals::Page49lock0noKeyState::from_bits(val as u8)
+    }
+    #[doc = "State when at least one key is registered for this page and no matching key has been entered."]
+    #[inline(always)]
+    pub fn set_no_key_state(&mut self, val: super::vals::Page49lock0noKeyState) {
+        self.0 = (self.0 & !(0x01 << 6usize)) | (((val.to_bits() as u32) & 0x01) << 6usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r1(&self) -> u8 {
+        let val = (self.0 >> 8usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r1(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r2(&self) -> u8 {
+        let val = (self.0 >> 16usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r2(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize);
+    }
+}
+impl Default for Page49lock0 {
+    #[inline(always)]
+    fn default() -> Page49lock0 {
+        Page49lock0(0)
+    }
+}
+#[doc = "Lock configuration MSBs for page 49 (rows 0xc40 through 0xc7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Page49lock1(pub u32);
+impl Page49lock1 {
+    #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."]
+    #[inline(always)]
+    pub const fn lock_s(&self) -> super::vals::Page49lock1lockS {
+        let val = (self.0 >> 0usize) & 0x03;
+        super::vals::Page49lock1lockS::from_bits(val as u8)
+    }
+    #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."]
+    #[inline(always)]
+    pub fn set_lock_s(&mut self, val: super::vals::Page49lock1lockS) {
+        self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize);
+    }
+    #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."]
+    #[inline(always)]
+    pub const fn lock_ns(&self) -> super::vals::Page49lock1lockNs {
+        let val = (self.0 >> 2usize) & 0x03;
+        super::vals::Page49lock1lockNs::from_bits(val as u8)
+    }
+    #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."]
+    #[inline(always)]
+    pub fn set_lock_ns(&mut self, val: super::vals::Page49lock1lockNs) {
+        self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize);
+    }
+    #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."]
+    #[inline(always)]
+    pub const fn lock_bl(&self) -> super::vals::Page49lock1lockBl {
+        let val = (self.0 >> 4usize) & 0x03;
+        super::vals::Page49lock1lockBl::from_bits(val as u8)
+    }
+    #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."]
+    #[inline(always)]
+    pub fn set_lock_bl(&mut self, val: super::vals::Page49lock1lockBl) {
+        self.0 = (self.0 & !(0x03 << 4usize)) | (((val.to_bits() as u32) & 0x03) << 4usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r1(&self) -> u8 {
+        let val = (self.0 >> 8usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r1(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r2(&self) -> u8 {
+        let val = (self.0 >> 16usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r2(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize);
+    }
+}
+impl Default for Page49lock1 {
+    #[inline(always)]
+    fn default() -> Page49lock1 {
+        Page49lock1(0)
+    }
+}
+#[doc = "Lock configuration LSBs for page 4 (rows 0x100 through 0x13f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Page4lock0(pub u32);
+impl Page4lock0 {
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub const fn key_w(&self) -> u8 {
+        let val = (self.0 >> 0usize) & 0x07;
+        val as u8
+    }
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub fn set_key_w(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x07 << 0usize)) | (((val as u32) & 0x07) << 0usize);
+    }
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub const fn key_r(&self) -> u8 {
+        let val = (self.0 >> 3usize) & 0x07;
+        val as u8
+    }
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub fn set_key_r(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x07 << 3usize)) | (((val as u32) & 0x07) << 3usize);
+    }
+    #[doc = "State when at least one key is registered for this page and no matching key has been entered."]
+    #[inline(always)]
+    pub const fn no_key_state(&self) -> super::vals::Page4lock0noKeyState {
+        let val = (self.0 >> 6usize) & 0x01;
+        super::vals::Page4lock0noKeyState::from_bits(val as u8)
+    }
+    #[doc = "State when at least one key is registered for this page and no matching key has been entered."]
+    #[inline(always)]
+    pub fn set_no_key_state(&mut self, val: super::vals::Page4lock0noKeyState) {
+        self.0 = (self.0 & !(0x01 << 6usize)) | (((val.to_bits() as u32) & 0x01) << 6usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r1(&self) -> u8 {
+        let val = (self.0 >> 8usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r1(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r2(&self) -> u8 {
+        let val = (self.0 >> 16usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r2(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize);
+    }
+}
+impl Default for Page4lock0 {
+    #[inline(always)]
+    fn default() -> Page4lock0 {
+        Page4lock0(0)
+    }
+}
+#[doc = "Lock configuration MSBs for page 4 (rows 0x100 through 0x13f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Page4lock1(pub u32);
+impl Page4lock1 {
+    #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."]
+    #[inline(always)]
+    pub const fn lock_s(&self) -> super::vals::Page4lock1lockS {
+        let val = (self.0 >> 0usize) & 0x03;
+        super::vals::Page4lock1lockS::from_bits(val as u8)
+    }
+    #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."]
+    #[inline(always)]
+    pub fn set_lock_s(&mut self, val: super::vals::Page4lock1lockS) {
+        self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize);
+    }
+    #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."]
+    #[inline(always)]
+    pub const fn lock_ns(&self) -> super::vals::Page4lock1lockNs {
+        let val = (self.0 >> 2usize) & 0x03;
+        super::vals::Page4lock1lockNs::from_bits(val as u8)
+    }
+    #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."]
+    #[inline(always)]
+    pub fn set_lock_ns(&mut self, val: super::vals::Page4lock1lockNs) {
+        self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize);
+    }
+    #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."]
+    #[inline(always)]
+    pub const fn lock_bl(&self) -> super::vals::Page4lock1lockBl {
+        let val = (self.0 >> 4usize) & 0x03;
+        super::vals::Page4lock1lockBl::from_bits(val as u8)
+    }
+    #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."]
+    #[inline(always)]
+    pub fn set_lock_bl(&mut self, val: super::vals::Page4lock1lockBl) {
+        self.0 = (self.0 & !(0x03 << 4usize)) | (((val.to_bits() as u32) & 0x03) << 4usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r1(&self) -> u8 {
+        let val = (self.0 >> 8usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r1(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r2(&self) -> u8 {
+        let val = (self.0 >> 16usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r2(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize);
+    }
+}
+impl Default for Page4lock1 {
+    #[inline(always)]
+    fn default() -> Page4lock1 {
+        Page4lock1(0)
+    }
+}
+#[doc = "Lock configuration LSBs for page 50 (rows 0xc80 through 0xcbf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Page50lock0(pub u32);
+impl Page50lock0 {
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub const fn key_w(&self) -> u8 {
+        let val = (self.0 >> 0usize) & 0x07;
+        val as u8
+    }
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub fn set_key_w(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x07 << 0usize)) | (((val as u32) & 0x07) << 0usize);
+    }
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub const fn key_r(&self) -> u8 {
+        let val = (self.0 >> 3usize) & 0x07;
+        val as u8
+    }
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub fn set_key_r(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x07 << 3usize)) | (((val as u32) & 0x07) << 3usize);
+    }
+    #[doc = "State when at least one key is registered for this page and no matching key has been entered."]
+    #[inline(always)]
+    pub const fn no_key_state(&self) -> super::vals::Page50lock0noKeyState {
+        let val = (self.0 >> 6usize) & 0x01;
+        super::vals::Page50lock0noKeyState::from_bits(val as u8)
+    }
+    #[doc = "State when at least one key is registered for this page and no matching key has been entered."]
+    #[inline(always)]
+    pub fn set_no_key_state(&mut self, val: super::vals::Page50lock0noKeyState) {
+        self.0 = (self.0 & !(0x01 << 6usize)) | (((val.to_bits() as u32) & 0x01) << 6usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r1(&self) -> u8 {
+        let val = (self.0 >> 8usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r1(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r2(&self) -> u8 {
+        let val = (self.0 >> 16usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r2(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize);
+    }
+}
+impl Default for Page50lock0 {
+    #[inline(always)]
+    fn default() -> Page50lock0 {
+        Page50lock0(0)
+    }
+}
+#[doc = "Lock configuration MSBs for page 50 (rows 0xc80 through 0xcbf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Page50lock1(pub u32);
+impl Page50lock1 {
+    #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."]
+    #[inline(always)]
+    pub const fn lock_s(&self) -> super::vals::Page50lock1lockS {
+        let val = (self.0 >> 0usize) & 0x03;
+        super::vals::Page50lock1lockS::from_bits(val as u8)
+    }
+    #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."]
+    #[inline(always)]
+    pub fn set_lock_s(&mut self, val: super::vals::Page50lock1lockS) {
+        self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize);
+    }
+    #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."]
+    #[inline(always)]
+    pub const fn lock_ns(&self) -> super::vals::Page50lock1lockNs {
+        let val = (self.0 >> 2usize) & 0x03;
+        super::vals::Page50lock1lockNs::from_bits(val as u8)
+    }
+    #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."]
+    #[inline(always)]
+    pub fn set_lock_ns(&mut self, val: super::vals::Page50lock1lockNs) {
+        self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize);
+    }
+    #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."]
+    #[inline(always)]
+    pub const fn lock_bl(&self) -> super::vals::Page50lock1lockBl {
+        let val = (self.0 >> 4usize) & 0x03;
+        super::vals::Page50lock1lockBl::from_bits(val as u8)
+    }
+    #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."]
+    #[inline(always)]
+    pub fn set_lock_bl(&mut self, val: super::vals::Page50lock1lockBl) {
+        self.0 = (self.0 & !(0x03 << 4usize)) | (((val.to_bits() as u32) & 0x03) << 4usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r1(&self) -> u8 {
+        let val = (self.0 >> 8usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r1(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r2(&self) -> u8 {
+        let val = (self.0 >> 16usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r2(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize);
+    }
+}
+impl Default for Page50lock1 {
+    #[inline(always)]
+    fn default() -> Page50lock1 {
+        Page50lock1(0)
+    }
+}
+#[doc = "Lock configuration LSBs for page 51 (rows 0xcc0 through 0xcff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Page51lock0(pub u32);
+impl Page51lock0 {
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub const fn key_w(&self) -> u8 {
+        let val = (self.0 >> 0usize) & 0x07;
+        val as u8
+    }
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub fn set_key_w(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x07 << 0usize)) | (((val as u32) & 0x07) << 0usize);
+    }
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub const fn key_r(&self) -> u8 {
+        let val = (self.0 >> 3usize) & 0x07;
+        val as u8
+    }
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub fn set_key_r(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x07 << 3usize)) | (((val as u32) & 0x07) << 3usize);
+    }
+    #[doc = "State when at least one key is registered for this page and no matching key has been entered."]
+    #[inline(always)]
+    pub const fn no_key_state(&self) -> super::vals::Page51lock0noKeyState {
+        let val = (self.0 >> 6usize) & 0x01;
+        super::vals::Page51lock0noKeyState::from_bits(val as u8)
+    }
+    #[doc = "State when at least one key is registered for this page and no matching key has been entered."]
+    #[inline(always)]
+    pub fn set_no_key_state(&mut self, val: super::vals::Page51lock0noKeyState) {
+        self.0 = (self.0 & !(0x01 << 6usize)) | (((val.to_bits() as u32) & 0x01) << 6usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r1(&self) -> u8 {
+        let val = (self.0 >> 8usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r1(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r2(&self) -> u8 {
+        let val = (self.0 >> 16usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r2(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize);
+    }
+}
+impl Default for Page51lock0 {
+    #[inline(always)]
+    fn default() -> Page51lock0 {
+        Page51lock0(0)
+    }
+}
+#[doc = "Lock configuration MSBs for page 51 (rows 0xcc0 through 0xcff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Page51lock1(pub u32);
+impl Page51lock1 {
+    #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."]
+    #[inline(always)]
+    pub const fn lock_s(&self) -> super::vals::Page51lock1lockS {
+        let val = (self.0 >> 0usize) & 0x03;
+        super::vals::Page51lock1lockS::from_bits(val as u8)
+    }
+    #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."]
+    #[inline(always)]
+    pub fn set_lock_s(&mut self, val: super::vals::Page51lock1lockS) {
+        self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize);
+    }
+    #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."]
+    #[inline(always)]
+    pub const fn lock_ns(&self) -> super::vals::Page51lock1lockNs {
+        let val = (self.0 >> 2usize) & 0x03;
+        super::vals::Page51lock1lockNs::from_bits(val as u8)
+    }
+    #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."]
+    #[inline(always)]
+    pub fn set_lock_ns(&mut self, val: super::vals::Page51lock1lockNs) {
+        self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize);
+    }
+    #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."]
+    #[inline(always)]
+    pub const fn lock_bl(&self) -> super::vals::Page51lock1lockBl {
+        let val = (self.0 >> 4usize) & 0x03;
+        super::vals::Page51lock1lockBl::from_bits(val as u8)
+    }
+    #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."]
+    #[inline(always)]
+    pub fn set_lock_bl(&mut self, val: super::vals::Page51lock1lockBl) {
+        self.0 = (self.0 & !(0x03 << 4usize)) | (((val.to_bits() as u32) & 0x03) << 4usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r1(&self) -> u8 {
+        let val = (self.0 >> 8usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r1(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r2(&self) -> u8 {
+        let val = (self.0 >> 16usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r2(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize);
+    }
+}
+impl Default for Page51lock1 {
+    #[inline(always)]
+    fn default() -> Page51lock1 {
+        Page51lock1(0)
+    }
+}
+#[doc = "Lock configuration LSBs for page 52 (rows 0xd00 through 0xd3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Page52lock0(pub u32);
+impl Page52lock0 {
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub const fn key_w(&self) -> u8 {
+        let val = (self.0 >> 0usize) & 0x07;
+        val as u8
+    }
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub fn set_key_w(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x07 << 0usize)) | (((val as u32) & 0x07) << 0usize);
+    }
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub const fn key_r(&self) -> u8 {
+        let val = (self.0 >> 3usize) & 0x07;
+        val as u8
+    }
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub fn set_key_r(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x07 << 3usize)) | (((val as u32) & 0x07) << 3usize);
+    }
+    #[doc = "State when at least one key is registered for this page and no matching key has been entered."]
+    #[inline(always)]
+    pub const fn no_key_state(&self) -> super::vals::Page52lock0noKeyState {
+        let val = (self.0 >> 6usize) & 0x01;
+        super::vals::Page52lock0noKeyState::from_bits(val as u8)
+    }
+    #[doc = "State when at least one key is registered for this page and no matching key has been entered."]
+    #[inline(always)]
+    pub fn set_no_key_state(&mut self, val: super::vals::Page52lock0noKeyState) {
+        self.0 = (self.0 & !(0x01 << 6usize)) | (((val.to_bits() as u32) & 0x01) << 6usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r1(&self) -> u8 {
+        let val = (self.0 >> 8usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r1(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r2(&self) -> u8 {
+        let val = (self.0 >> 16usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r2(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize);
+    }
+}
+impl Default for Page52lock0 {
+    #[inline(always)]
+    fn default() -> Page52lock0 {
+        Page52lock0(0)
+    }
+}
+#[doc = "Lock configuration MSBs for page 52 (rows 0xd00 through 0xd3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Page52lock1(pub u32);
+impl Page52lock1 {
+    #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."]
+    #[inline(always)]
+    pub const fn lock_s(&self) -> super::vals::Page52lock1lockS {
+        let val = (self.0 >> 0usize) & 0x03;
+        super::vals::Page52lock1lockS::from_bits(val as u8)
+    }
+    #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."]
+    #[inline(always)]
+    pub fn set_lock_s(&mut self, val: super::vals::Page52lock1lockS) {
+        self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize);
+    }
+    #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."]
+    #[inline(always)]
+    pub const fn lock_ns(&self) -> super::vals::Page52lock1lockNs {
+        let val = (self.0 >> 2usize) & 0x03;
+        super::vals::Page52lock1lockNs::from_bits(val as u8)
+    }
+    #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."]
+    #[inline(always)]
+    pub fn set_lock_ns(&mut self, val: super::vals::Page52lock1lockNs) {
+        self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize);
+    }
+    #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."]
+    #[inline(always)]
+    pub const fn lock_bl(&self) -> super::vals::Page52lock1lockBl {
+        let val = (self.0 >> 4usize) & 0x03;
+        super::vals::Page52lock1lockBl::from_bits(val as u8)
+    }
+    #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."]
+    #[inline(always)]
+    pub fn set_lock_bl(&mut self, val: super::vals::Page52lock1lockBl) {
+        self.0 = (self.0 & !(0x03 << 4usize)) | (((val.to_bits() as u32) & 0x03) << 4usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r1(&self) -> u8 {
+        let val = (self.0 >> 8usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r1(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r2(&self) -> u8 {
+        let val = (self.0 >> 16usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r2(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize);
+    }
+}
+impl Default for Page52lock1 {
+    #[inline(always)]
+    fn default() -> Page52lock1 {
+        Page52lock1(0)
+    }
+}
+#[doc = "Lock configuration LSBs for page 53 (rows 0xd40 through 0xd7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Page53lock0(pub u32);
+impl Page53lock0 {
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub const fn key_w(&self) -> u8 {
+        let val = (self.0 >> 0usize) & 0x07;
+        val as u8
+    }
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub fn set_key_w(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x07 << 0usize)) | (((val as u32) & 0x07) << 0usize);
+    }
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub const fn key_r(&self) -> u8 {
+        let val = (self.0 >> 3usize) & 0x07;
+        val as u8
+    }
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub fn set_key_r(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x07 << 3usize)) | (((val as u32) & 0x07) << 3usize);
+    }
+    #[doc = "State when at least one key is registered for this page and no matching key has been entered."]
+    #[inline(always)]
+    pub const fn no_key_state(&self) -> super::vals::Page53lock0noKeyState {
+        let val = (self.0 >> 6usize) & 0x01;
+        super::vals::Page53lock0noKeyState::from_bits(val as u8)
+    }
+    #[doc = "State when at least one key is registered for this page and no matching key has been entered."]
+    #[inline(always)]
+    pub fn set_no_key_state(&mut self, val: super::vals::Page53lock0noKeyState) {
+        self.0 = (self.0 & !(0x01 << 6usize)) | (((val.to_bits() as u32) & 0x01) << 6usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r1(&self) -> u8 {
+        let val = (self.0 >> 8usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r1(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r2(&self) -> u8 {
+        let val = (self.0 >> 16usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r2(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize);
+    }
+}
+impl Default for Page53lock0 {
+    #[inline(always)]
+    fn default() -> Page53lock0 {
+        Page53lock0(0)
+    }
+}
+#[doc = "Lock configuration MSBs for page 53 (rows 0xd40 through 0xd7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Page53lock1(pub u32);
+impl Page53lock1 {
+    #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."]
+    #[inline(always)]
+    pub const fn lock_s(&self) -> super::vals::Page53lock1lockS {
+        let val = (self.0 >> 0usize) & 0x03;
+        super::vals::Page53lock1lockS::from_bits(val as u8)
+    }
+    #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."]
+    #[inline(always)]
+    pub fn set_lock_s(&mut self, val: super::vals::Page53lock1lockS) {
+        self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize);
+    }
+    #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."]
+    #[inline(always)]
+    pub const fn lock_ns(&self) -> super::vals::Page53lock1lockNs {
+        let val = (self.0 >> 2usize) & 0x03;
+        super::vals::Page53lock1lockNs::from_bits(val as u8)
+    }
+    #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."]
+    #[inline(always)]
+    pub fn set_lock_ns(&mut self, val: super::vals::Page53lock1lockNs) {
+        self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize);
+    }
+    #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."]
+    #[inline(always)]
+    pub const fn lock_bl(&self) -> super::vals::Page53lock1lockBl {
+        let val = (self.0 >> 4usize) & 0x03;
+        super::vals::Page53lock1lockBl::from_bits(val as u8)
+    }
+    #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."]
+    #[inline(always)]
+    pub fn set_lock_bl(&mut self, val: super::vals::Page53lock1lockBl) {
+        self.0 = (self.0 & !(0x03 << 4usize)) | (((val.to_bits() as u32) & 0x03) << 4usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r1(&self) -> u8 {
+        let val = (self.0 >> 8usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r1(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r2(&self) -> u8 {
+        let val = (self.0 >> 16usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r2(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize);
+    }
+}
+impl Default for Page53lock1 {
+    #[inline(always)]
+    fn default() -> Page53lock1 {
+        Page53lock1(0)
+    }
+}
+#[doc = "Lock configuration LSBs for page 54 (rows 0xd80 through 0xdbf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Page54lock0(pub u32);
+impl Page54lock0 {
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub const fn key_w(&self) -> u8 {
+        let val = (self.0 >> 0usize) & 0x07;
+        val as u8
+    }
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub fn set_key_w(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x07 << 0usize)) | (((val as u32) & 0x07) << 0usize);
+    }
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub const fn key_r(&self) -> u8 {
+        let val = (self.0 >> 3usize) & 0x07;
+        val as u8
+    }
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub fn set_key_r(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x07 << 3usize)) | (((val as u32) & 0x07) << 3usize);
+    }
+    #[doc = "State when at least one key is registered for this page and no matching key has been entered."]
+    #[inline(always)]
+    pub const fn no_key_state(&self) -> super::vals::Page54lock0noKeyState {
+        let val = (self.0 >> 6usize) & 0x01;
+        super::vals::Page54lock0noKeyState::from_bits(val as u8)
+    }
+    #[doc = "State when at least one key is registered for this page and no matching key has been entered."]
+    #[inline(always)]
+    pub fn set_no_key_state(&mut self, val: super::vals::Page54lock0noKeyState) {
+        self.0 = (self.0 & !(0x01 << 6usize)) | (((val.to_bits() as u32) & 0x01) << 6usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r1(&self) -> u8 {
+        let val = (self.0 >> 8usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r1(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r2(&self) -> u8 {
+        let val = (self.0 >> 16usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r2(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize);
+    }
+}
+impl Default for Page54lock0 {
+    #[inline(always)]
+    fn default() -> Page54lock0 {
+        Page54lock0(0)
+    }
+}
+#[doc = "Lock configuration MSBs for page 54 (rows 0xd80 through 0xdbf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Page54lock1(pub u32);
+impl Page54lock1 {
+    #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."]
+    #[inline(always)]
+    pub const fn lock_s(&self) -> super::vals::Page54lock1lockS {
+        let val = (self.0 >> 0usize) & 0x03;
+        super::vals::Page54lock1lockS::from_bits(val as u8)
+    }
+    #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."]
+    #[inline(always)]
+    pub fn set_lock_s(&mut self, val: super::vals::Page54lock1lockS) {
+        self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize);
+    }
+    #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."]
+    #[inline(always)]
+    pub const fn lock_ns(&self) -> super::vals::Page54lock1lockNs {
+        let val = (self.0 >> 2usize) & 0x03;
+        super::vals::Page54lock1lockNs::from_bits(val as u8)
+    }
+    #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."]
+    #[inline(always)]
+    pub fn set_lock_ns(&mut self, val: super::vals::Page54lock1lockNs) {
+        self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize);
+    }
+    #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."]
+    #[inline(always)]
+    pub const fn lock_bl(&self) -> super::vals::Page54lock1lockBl {
+        let val = (self.0 >> 4usize) & 0x03;
+        super::vals::Page54lock1lockBl::from_bits(val as u8)
+    }
+    #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."]
+    #[inline(always)]
+    pub fn set_lock_bl(&mut self, val: super::vals::Page54lock1lockBl) {
+        self.0 = (self.0 & !(0x03 << 4usize)) | (((val.to_bits() as u32) & 0x03) << 4usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r1(&self) -> u8 {
+        let val = (self.0 >> 8usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r1(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r2(&self) -> u8 {
+        let val = (self.0 >> 16usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r2(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize);
+    }
+}
+impl Default for Page54lock1 {
+    #[inline(always)]
+    fn default() -> Page54lock1 {
+        Page54lock1(0)
+    }
+}
+#[doc = "Lock configuration LSBs for page 55 (rows 0xdc0 through 0xdff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Page55lock0(pub u32);
+impl Page55lock0 {
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub const fn key_w(&self) -> u8 {
+        let val = (self.0 >> 0usize) & 0x07;
+        val as u8
+    }
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub fn set_key_w(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x07 << 0usize)) | (((val as u32) & 0x07) << 0usize);
+    }
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub const fn key_r(&self) -> u8 {
+        let val = (self.0 >> 3usize) & 0x07;
+        val as u8
+    }
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub fn set_key_r(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x07 << 3usize)) | (((val as u32) & 0x07) << 3usize);
+    }
+    #[doc = "State when at least one key is registered for this page and no matching key has been entered."]
+    #[inline(always)]
+    pub const fn no_key_state(&self) -> super::vals::Page55lock0noKeyState {
+        let val = (self.0 >> 6usize) & 0x01;
+        super::vals::Page55lock0noKeyState::from_bits(val as u8)
+    }
+    #[doc = "State when at least one key is registered for this page and no matching key has been entered."]
+    #[inline(always)]
+    pub fn set_no_key_state(&mut self, val: super::vals::Page55lock0noKeyState) {
+        self.0 = (self.0 & !(0x01 << 6usize)) | (((val.to_bits() as u32) & 0x01) << 6usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r1(&self) -> u8 {
+        let val = (self.0 >> 8usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r1(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r2(&self) -> u8 {
+        let val = (self.0 >> 16usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r2(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize);
+    }
+}
+impl Default for Page55lock0 {
+    #[inline(always)]
+    fn default() -> Page55lock0 {
+        Page55lock0(0)
+    }
+}
+#[doc = "Lock configuration MSBs for page 55 (rows 0xdc0 through 0xdff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Page55lock1(pub u32);
+impl Page55lock1 {
+    #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."]
+    #[inline(always)]
+    pub const fn lock_s(&self) -> super::vals::Page55lock1lockS {
+        let val = (self.0 >> 0usize) & 0x03;
+        super::vals::Page55lock1lockS::from_bits(val as u8)
+    }
+    #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."]
+    #[inline(always)]
+    pub fn set_lock_s(&mut self, val: super::vals::Page55lock1lockS) {
+        self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize);
+    }
+    #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."]
+    #[inline(always)]
+    pub const fn lock_ns(&self) -> super::vals::Page55lock1lockNs {
+        let val = (self.0 >> 2usize) & 0x03;
+        super::vals::Page55lock1lockNs::from_bits(val as u8)
+    }
+    #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."]
+    #[inline(always)]
+    pub fn set_lock_ns(&mut self, val: super::vals::Page55lock1lockNs) {
+        self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize);
+    }
+    #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."]
+    #[inline(always)]
+    pub const fn lock_bl(&self) -> super::vals::Page55lock1lockBl {
+        let val = (self.0 >> 4usize) & 0x03;
+        super::vals::Page55lock1lockBl::from_bits(val as u8)
+    }
+    #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."]
+    #[inline(always)]
+    pub fn set_lock_bl(&mut self, val: super::vals::Page55lock1lockBl) {
+        self.0 = (self.0 & !(0x03 << 4usize)) | (((val.to_bits() as u32) & 0x03) << 4usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r1(&self) -> u8 {
+        let val = (self.0 >> 8usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r1(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r2(&self) -> u8 {
+        let val = (self.0 >> 16usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r2(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize);
+    }
+}
+impl Default for Page55lock1 {
+    #[inline(always)]
+    fn default() -> Page55lock1 {
+        Page55lock1(0)
+    }
+}
+#[doc = "Lock configuration LSBs for page 56 (rows 0xe00 through 0xe3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Page56lock0(pub u32);
+impl Page56lock0 {
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub const fn key_w(&self) -> u8 {
+        let val = (self.0 >> 0usize) & 0x07;
+        val as u8
+    }
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub fn set_key_w(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x07 << 0usize)) | (((val as u32) & 0x07) << 0usize);
+    }
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub const fn key_r(&self) -> u8 {
+        let val = (self.0 >> 3usize) & 0x07;
+        val as u8
+    }
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub fn set_key_r(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x07 << 3usize)) | (((val as u32) & 0x07) << 3usize);
+    }
+    #[doc = "State when at least one key is registered for this page and no matching key has been entered."]
+    #[inline(always)]
+    pub const fn no_key_state(&self) -> super::vals::Page56lock0noKeyState {
+        let val = (self.0 >> 6usize) & 0x01;
+        super::vals::Page56lock0noKeyState::from_bits(val as u8)
+    }
+    #[doc = "State when at least one key is registered for this page and no matching key has been entered."]
+    #[inline(always)]
+    pub fn set_no_key_state(&mut self, val: super::vals::Page56lock0noKeyState) {
+        self.0 = (self.0 & !(0x01 << 6usize)) | (((val.to_bits() as u32) & 0x01) << 6usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r1(&self) -> u8 {
+        let val = (self.0 >> 8usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r1(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r2(&self) -> u8 {
+        let val = (self.0 >> 16usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r2(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize);
+    }
+}
+impl Default for Page56lock0 {
+    #[inline(always)]
+    fn default() -> Page56lock0 {
+        Page56lock0(0)
+    }
+}
+#[doc = "Lock configuration MSBs for page 56 (rows 0xe00 through 0xe3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Page56lock1(pub u32);
+impl Page56lock1 {
+    #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."]
+    #[inline(always)]
+    pub const fn lock_s(&self) -> super::vals::Page56lock1lockS {
+        let val = (self.0 >> 0usize) & 0x03;
+        super::vals::Page56lock1lockS::from_bits(val as u8)
+    }
+    #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."]
+    #[inline(always)]
+    pub fn set_lock_s(&mut self, val: super::vals::Page56lock1lockS) {
+        self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize);
+    }
+    #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."]
+    #[inline(always)]
+    pub const fn lock_ns(&self) -> super::vals::Page56lock1lockNs {
+        let val = (self.0 >> 2usize) & 0x03;
+        super::vals::Page56lock1lockNs::from_bits(val as u8)
+    }
+    #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."]
+    #[inline(always)]
+    pub fn set_lock_ns(&mut self, val: super::vals::Page56lock1lockNs) {
+        self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize);
+    }
+    #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."]
+    #[inline(always)]
+    pub const fn lock_bl(&self) -> super::vals::Page56lock1lockBl {
+        let val = (self.0 >> 4usize) & 0x03;
+        super::vals::Page56lock1lockBl::from_bits(val as u8)
+    }
+    #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."]
+    #[inline(always)]
+    pub fn set_lock_bl(&mut self, val: super::vals::Page56lock1lockBl) {
+        self.0 = (self.0 & !(0x03 << 4usize)) | (((val.to_bits() as u32) & 0x03) << 4usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r1(&self) -> u8 {
+        let val = (self.0 >> 8usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r1(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r2(&self) -> u8 {
+        let val = (self.0 >> 16usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r2(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize);
+    }
+}
+impl Default for Page56lock1 {
+    #[inline(always)]
+    fn default() -> Page56lock1 {
+        Page56lock1(0)
+    }
+}
+#[doc = "Lock configuration LSBs for page 57 (rows 0xe40 through 0xe7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Page57lock0(pub u32);
+impl Page57lock0 {
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub const fn key_w(&self) -> u8 {
+        let val = (self.0 >> 0usize) & 0x07;
+        val as u8
+    }
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub fn set_key_w(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x07 << 0usize)) | (((val as u32) & 0x07) << 0usize);
+    }
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub const fn key_r(&self) -> u8 {
+        let val = (self.0 >> 3usize) & 0x07;
+        val as u8
+    }
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub fn set_key_r(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x07 << 3usize)) | (((val as u32) & 0x07) << 3usize);
+    }
+    #[doc = "State when at least one key is registered for this page and no matching key has been entered."]
+    #[inline(always)]
+    pub const fn no_key_state(&self) -> super::vals::Page57lock0noKeyState {
+        let val = (self.0 >> 6usize) & 0x01;
+        super::vals::Page57lock0noKeyState::from_bits(val as u8)
+    }
+    #[doc = "State when at least one key is registered for this page and no matching key has been entered."]
+    #[inline(always)]
+    pub fn set_no_key_state(&mut self, val: super::vals::Page57lock0noKeyState) {
+        self.0 = (self.0 & !(0x01 << 6usize)) | (((val.to_bits() as u32) & 0x01) << 6usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r1(&self) -> u8 {
+        let val = (self.0 >> 8usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r1(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r2(&self) -> u8 {
+        let val = (self.0 >> 16usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r2(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize);
+    }
+}
+impl Default for Page57lock0 {
+    #[inline(always)]
+    fn default() -> Page57lock0 {
+        Page57lock0(0)
+    }
+}
+#[doc = "Lock configuration MSBs for page 57 (rows 0xe40 through 0xe7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Page57lock1(pub u32);
+impl Page57lock1 {
+    #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."]
+    #[inline(always)]
+    pub const fn lock_s(&self) -> super::vals::Page57lock1lockS {
+        let val = (self.0 >> 0usize) & 0x03;
+        super::vals::Page57lock1lockS::from_bits(val as u8)
+    }
+    #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."]
+    #[inline(always)]
+    pub fn set_lock_s(&mut self, val: super::vals::Page57lock1lockS) {
+        self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize);
+    }
+    #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."]
+    #[inline(always)]
+    pub const fn lock_ns(&self) -> super::vals::Page57lock1lockNs {
+        let val = (self.0 >> 2usize) & 0x03;
+        super::vals::Page57lock1lockNs::from_bits(val as u8)
+    }
+    #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."]
+    #[inline(always)]
+    pub fn set_lock_ns(&mut self, val: super::vals::Page57lock1lockNs) {
+        self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize);
+    }
+    #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."]
+    #[inline(always)]
+    pub const fn lock_bl(&self) -> super::vals::Page57lock1lockBl {
+        let val = (self.0 >> 4usize) & 0x03;
+        super::vals::Page57lock1lockBl::from_bits(val as u8)
+    }
+    #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."]
+    #[inline(always)]
+    pub fn set_lock_bl(&mut self, val: super::vals::Page57lock1lockBl) {
+        self.0 = (self.0 & !(0x03 << 4usize)) | (((val.to_bits() as u32) & 0x03) << 4usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r1(&self) -> u8 {
+        let val = (self.0 >> 8usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r1(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r2(&self) -> u8 {
+        let val = (self.0 >> 16usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r2(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize);
+    }
+}
+impl Default for Page57lock1 {
+    #[inline(always)]
+    fn default() -> Page57lock1 {
+        Page57lock1(0)
+    }
+}
+#[doc = "Lock configuration LSBs for page 58 (rows 0xe80 through 0xebf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Page58lock0(pub u32);
+impl Page58lock0 {
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub const fn key_w(&self) -> u8 {
+        let val = (self.0 >> 0usize) & 0x07;
+        val as u8
+    }
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub fn set_key_w(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x07 << 0usize)) | (((val as u32) & 0x07) << 0usize);
+    }
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub const fn key_r(&self) -> u8 {
+        let val = (self.0 >> 3usize) & 0x07;
+        val as u8
+    }
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub fn set_key_r(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x07 << 3usize)) | (((val as u32) & 0x07) << 3usize);
+    }
+    #[doc = "State when at least one key is registered for this page and no matching key has been entered."]
+    #[inline(always)]
+    pub const fn no_key_state(&self) -> super::vals::Page58lock0noKeyState {
+        let val = (self.0 >> 6usize) & 0x01;
+        super::vals::Page58lock0noKeyState::from_bits(val as u8)
+    }
+    #[doc = "State when at least one key is registered for this page and no matching key has been entered."]
+    #[inline(always)]
+    pub fn set_no_key_state(&mut self, val: super::vals::Page58lock0noKeyState) {
+        self.0 = (self.0 & !(0x01 << 6usize)) | (((val.to_bits() as u32) & 0x01) << 6usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r1(&self) -> u8 {
+        let val = (self.0 >> 8usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r1(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r2(&self) -> u8 {
+        let val = (self.0 >> 16usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r2(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize);
+    }
+}
+impl Default for Page58lock0 {
+    #[inline(always)]
+    fn default() -> Page58lock0 {
+        Page58lock0(0)
+    }
+}
+#[doc = "Lock configuration MSBs for page 58 (rows 0xe80 through 0xebf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Page58lock1(pub u32);
+impl Page58lock1 {
+    #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."]
+    #[inline(always)]
+    pub const fn lock_s(&self) -> super::vals::Page58lock1lockS {
+        let val = (self.0 >> 0usize) & 0x03;
+        super::vals::Page58lock1lockS::from_bits(val as u8)
+    }
+    #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."]
+    #[inline(always)]
+    pub fn set_lock_s(&mut self, val: super::vals::Page58lock1lockS) {
+        self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize);
+    }
+    #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."]
+    #[inline(always)]
+    pub const fn lock_ns(&self) -> super::vals::Page58lock1lockNs {
+        let val = (self.0 >> 2usize) & 0x03;
+        super::vals::Page58lock1lockNs::from_bits(val as u8)
+    }
+    #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."]
+    #[inline(always)]
+    pub fn set_lock_ns(&mut self, val: super::vals::Page58lock1lockNs) {
+        self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize);
+    }
+    #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."]
+    #[inline(always)]
+    pub const fn lock_bl(&self) -> super::vals::Page58lock1lockBl {
+        let val = (self.0 >> 4usize) & 0x03;
+        super::vals::Page58lock1lockBl::from_bits(val as u8)
+    }
+    #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."]
+    #[inline(always)]
+    pub fn set_lock_bl(&mut self, val: super::vals::Page58lock1lockBl) {
+        self.0 = (self.0 & !(0x03 << 4usize)) | (((val.to_bits() as u32) & 0x03) << 4usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r1(&self) -> u8 {
+        let val = (self.0 >> 8usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r1(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r2(&self) -> u8 {
+        let val = (self.0 >> 16usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r2(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize);
+    }
+}
+impl Default for Page58lock1 {
+    #[inline(always)]
+    fn default() -> Page58lock1 {
+        Page58lock1(0)
+    }
+}
+#[doc = "Lock configuration LSBs for page 59 (rows 0xec0 through 0xeff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Page59lock0(pub u32);
+impl Page59lock0 {
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub const fn key_w(&self) -> u8 {
+        let val = (self.0 >> 0usize) & 0x07;
+        val as u8
+    }
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub fn set_key_w(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x07 << 0usize)) | (((val as u32) & 0x07) << 0usize);
+    }
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub const fn key_r(&self) -> u8 {
+        let val = (self.0 >> 3usize) & 0x07;
+        val as u8
+    }
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub fn set_key_r(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x07 << 3usize)) | (((val as u32) & 0x07) << 3usize);
+    }
+    #[doc = "State when at least one key is registered for this page and no matching key has been entered."]
+    #[inline(always)]
+    pub const fn no_key_state(&self) -> super::vals::Page59lock0noKeyState {
+        let val = (self.0 >> 6usize) & 0x01;
+        super::vals::Page59lock0noKeyState::from_bits(val as u8)
+    }
+    #[doc = "State when at least one key is registered for this page and no matching key has been entered."]
+    #[inline(always)]
+    pub fn set_no_key_state(&mut self, val: super::vals::Page59lock0noKeyState) {
+        self.0 = (self.0 & !(0x01 << 6usize)) | (((val.to_bits() as u32) & 0x01) << 6usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r1(&self) -> u8 {
+        let val = (self.0 >> 8usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r1(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r2(&self) -> u8 {
+        let val = (self.0 >> 16usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r2(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize);
+    }
+}
+impl Default for Page59lock0 {
+    #[inline(always)]
+    fn default() -> Page59lock0 {
+        Page59lock0(0)
+    }
+}
+#[doc = "Lock configuration MSBs for page 59 (rows 0xec0 through 0xeff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Page59lock1(pub u32);
+impl Page59lock1 {
+    #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."]
+    #[inline(always)]
+    pub const fn lock_s(&self) -> super::vals::Page59lock1lockS {
+        let val = (self.0 >> 0usize) & 0x03;
+        super::vals::Page59lock1lockS::from_bits(val as u8)
+    }
+    #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."]
+    #[inline(always)]
+    pub fn set_lock_s(&mut self, val: super::vals::Page59lock1lockS) {
+        self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize);
+    }
+    #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."]
+    #[inline(always)]
+    pub const fn lock_ns(&self) -> super::vals::Page59lock1lockNs {
+        let val = (self.0 >> 2usize) & 0x03;
+        super::vals::Page59lock1lockNs::from_bits(val as u8)
+    }
+    #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."]
+    #[inline(always)]
+    pub fn set_lock_ns(&mut self, val: super::vals::Page59lock1lockNs) {
+        self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize);
+    }
+    #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."]
+    #[inline(always)]
+    pub const fn lock_bl(&self) -> super::vals::Page59lock1lockBl {
+        let val = (self.0 >> 4usize) & 0x03;
+        super::vals::Page59lock1lockBl::from_bits(val as u8)
+    }
+    #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."]
+    #[inline(always)]
+    pub fn set_lock_bl(&mut self, val: super::vals::Page59lock1lockBl) {
+        self.0 = (self.0 & !(0x03 << 4usize)) | (((val.to_bits() as u32) & 0x03) << 4usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r1(&self) -> u8 {
+        let val = (self.0 >> 8usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r1(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r2(&self) -> u8 {
+        let val = (self.0 >> 16usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r2(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize);
+    }
+}
+impl Default for Page59lock1 {
+    #[inline(always)]
+    fn default() -> Page59lock1 {
+        Page59lock1(0)
+    }
+}
+#[doc = "Lock configuration LSBs for page 5 (rows 0x140 through 0x17f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Page5lock0(pub u32);
+impl Page5lock0 {
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub const fn key_w(&self) -> u8 {
+        let val = (self.0 >> 0usize) & 0x07;
+        val as u8
+    }
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub fn set_key_w(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x07 << 0usize)) | (((val as u32) & 0x07) << 0usize);
+    }
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub const fn key_r(&self) -> u8 {
+        let val = (self.0 >> 3usize) & 0x07;
+        val as u8
+    }
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub fn set_key_r(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x07 << 3usize)) | (((val as u32) & 0x07) << 3usize);
+    }
+    #[doc = "State when at least one key is registered for this page and no matching key has been entered."]
+    #[inline(always)]
+    pub const fn no_key_state(&self) -> super::vals::Page5lock0noKeyState {
+        let val = (self.0 >> 6usize) & 0x01;
+        super::vals::Page5lock0noKeyState::from_bits(val as u8)
+    }
+    #[doc = "State when at least one key is registered for this page and no matching key has been entered."]
+    #[inline(always)]
+    pub fn set_no_key_state(&mut self, val: super::vals::Page5lock0noKeyState) {
+        self.0 = (self.0 & !(0x01 << 6usize)) | (((val.to_bits() as u32) & 0x01) << 6usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r1(&self) -> u8 {
+        let val = (self.0 >> 8usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r1(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r2(&self) -> u8 {
+        let val = (self.0 >> 16usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r2(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize);
+    }
+}
+impl Default for Page5lock0 {
+    #[inline(always)]
+    fn default() -> Page5lock0 {
+        Page5lock0(0)
+    }
+}
+#[doc = "Lock configuration MSBs for page 5 (rows 0x140 through 0x17f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Page5lock1(pub u32);
+impl Page5lock1 {
+    #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."]
+    #[inline(always)]
+    pub const fn lock_s(&self) -> super::vals::Page5lock1lockS {
+        let val = (self.0 >> 0usize) & 0x03;
+        super::vals::Page5lock1lockS::from_bits(val as u8)
+    }
+    #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."]
+    #[inline(always)]
+    pub fn set_lock_s(&mut self, val: super::vals::Page5lock1lockS) {
+        self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize);
+    }
+    #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."]
+    #[inline(always)]
+    pub const fn lock_ns(&self) -> super::vals::Page5lock1lockNs {
+        let val = (self.0 >> 2usize) & 0x03;
+        super::vals::Page5lock1lockNs::from_bits(val as u8)
+    }
+    #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."]
+    #[inline(always)]
+    pub fn set_lock_ns(&mut self, val: super::vals::Page5lock1lockNs) {
+        self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize);
+    }
+    #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."]
+    #[inline(always)]
+    pub const fn lock_bl(&self) -> super::vals::Page5lock1lockBl {
+        let val = (self.0 >> 4usize) & 0x03;
+        super::vals::Page5lock1lockBl::from_bits(val as u8)
+    }
+    #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."]
+    #[inline(always)]
+    pub fn set_lock_bl(&mut self, val: super::vals::Page5lock1lockBl) {
+        self.0 = (self.0 & !(0x03 << 4usize)) | (((val.to_bits() as u32) & 0x03) << 4usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r1(&self) -> u8 {
+        let val = (self.0 >> 8usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r1(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r2(&self) -> u8 {
+        let val = (self.0 >> 16usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r2(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize);
+    }
+}
+impl Default for Page5lock1 {
+    #[inline(always)]
+    fn default() -> Page5lock1 {
+        Page5lock1(0)
+    }
+}
+#[doc = "Lock configuration LSBs for page 60 (rows 0xf00 through 0xf3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Page60lock0(pub u32);
+impl Page60lock0 {
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub const fn key_w(&self) -> u8 {
+        let val = (self.0 >> 0usize) & 0x07;
+        val as u8
+    }
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub fn set_key_w(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x07 << 0usize)) | (((val as u32) & 0x07) << 0usize);
+    }
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub const fn key_r(&self) -> u8 {
+        let val = (self.0 >> 3usize) & 0x07;
+        val as u8
+    }
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub fn set_key_r(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x07 << 3usize)) | (((val as u32) & 0x07) << 3usize);
+    }
+    #[doc = "State when at least one key is registered for this page and no matching key has been entered."]
+    #[inline(always)]
+    pub const fn no_key_state(&self) -> super::vals::Page60lock0noKeyState {
+        let val = (self.0 >> 6usize) & 0x01;
+        super::vals::Page60lock0noKeyState::from_bits(val as u8)
+    }
+    #[doc = "State when at least one key is registered for this page and no matching key has been entered."]
+    #[inline(always)]
+    pub fn set_no_key_state(&mut self, val: super::vals::Page60lock0noKeyState) {
+        self.0 = (self.0 & !(0x01 << 6usize)) | (((val.to_bits() as u32) & 0x01) << 6usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r1(&self) -> u8 {
+        let val = (self.0 >> 8usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r1(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r2(&self) -> u8 {
+        let val = (self.0 >> 16usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r2(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize);
+    }
+}
+impl Default for Page60lock0 {
+    #[inline(always)]
+    fn default() -> Page60lock0 {
+        Page60lock0(0)
+    }
+}
+#[doc = "Lock configuration MSBs for page 60 (rows 0xf00 through 0xf3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Page60lock1(pub u32);
+impl Page60lock1 {
+    #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."]
+    #[inline(always)]
+    pub const fn lock_s(&self) -> super::vals::Page60lock1lockS {
+        let val = (self.0 >> 0usize) & 0x03;
+        super::vals::Page60lock1lockS::from_bits(val as u8)
+    }
+    #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."]
+    #[inline(always)]
+    pub fn set_lock_s(&mut self, val: super::vals::Page60lock1lockS) {
+        self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize);
+    }
+    #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."]
+    #[inline(always)]
+    pub const fn lock_ns(&self) -> super::vals::Page60lock1lockNs {
+        let val = (self.0 >> 2usize) & 0x03;
+        super::vals::Page60lock1lockNs::from_bits(val as u8)
+    }
+    #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."]
+    #[inline(always)]
+    pub fn set_lock_ns(&mut self, val: super::vals::Page60lock1lockNs) {
+        self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize);
+    }
+    #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."]
+    #[inline(always)]
+    pub const fn lock_bl(&self) -> super::vals::Page60lock1lockBl {
+        let val = (self.0 >> 4usize) & 0x03;
+        super::vals::Page60lock1lockBl::from_bits(val as u8)
+    }
+    #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."]
+    #[inline(always)]
+    pub fn set_lock_bl(&mut self, val: super::vals::Page60lock1lockBl) {
+        self.0 = (self.0 & !(0x03 << 4usize)) | (((val.to_bits() as u32) & 0x03) << 4usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r1(&self) -> u8 {
+        let val = (self.0 >> 8usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r1(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r2(&self) -> u8 {
+        let val = (self.0 >> 16usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r2(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize);
+    }
+}
+impl Default for Page60lock1 {
+    #[inline(always)]
+    fn default() -> Page60lock1 {
+        Page60lock1(0)
+    }
+}
+#[doc = "Lock configuration LSBs for page 61 (rows 0xf40 through 0xf7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Page61lock0(pub u32);
+impl Page61lock0 {
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub const fn key_w(&self) -> u8 {
+        let val = (self.0 >> 0usize) & 0x07;
+        val as u8
+    }
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub fn set_key_w(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x07 << 0usize)) | (((val as u32) & 0x07) << 0usize);
+    }
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub const fn key_r(&self) -> u8 {
+        let val = (self.0 >> 3usize) & 0x07;
+        val as u8
+    }
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub fn set_key_r(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x07 << 3usize)) | (((val as u32) & 0x07) << 3usize);
+    }
+    #[doc = "State when at least one key is registered for this page and no matching key has been entered."]
+    #[inline(always)]
+    pub const fn no_key_state(&self) -> super::vals::Page61lock0noKeyState {
+        let val = (self.0 >> 6usize) & 0x01;
+        super::vals::Page61lock0noKeyState::from_bits(val as u8)
+    }
+    #[doc = "State when at least one key is registered for this page and no matching key has been entered."]
+    #[inline(always)]
+    pub fn set_no_key_state(&mut self, val: super::vals::Page61lock0noKeyState) {
+        self.0 = (self.0 & !(0x01 << 6usize)) | (((val.to_bits() as u32) & 0x01) << 6usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r1(&self) -> u8 {
+        let val = (self.0 >> 8usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r1(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r2(&self) -> u8 {
+        let val = (self.0 >> 16usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r2(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize);
+    }
+}
+impl Default for Page61lock0 {
+    #[inline(always)]
+    fn default() -> Page61lock0 {
+        Page61lock0(0)
+    }
+}
+#[doc = "Lock configuration MSBs for page 61 (rows 0xf40 through 0xf7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Page61lock1(pub u32);
+impl Page61lock1 {
+    #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."]
+    #[inline(always)]
+    pub const fn lock_s(&self) -> super::vals::Page61lock1lockS {
+        let val = (self.0 >> 0usize) & 0x03;
+        super::vals::Page61lock1lockS::from_bits(val as u8)
+    }
+    #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."]
+    #[inline(always)]
+    pub fn set_lock_s(&mut self, val: super::vals::Page61lock1lockS) {
+        self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize);
+    }
+    #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."]
+    #[inline(always)]
+    pub const fn lock_ns(&self) -> super::vals::Page61lock1lockNs {
+        let val = (self.0 >> 2usize) & 0x03;
+        super::vals::Page61lock1lockNs::from_bits(val as u8)
+    }
+    #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."]
+    #[inline(always)]
+    pub fn set_lock_ns(&mut self, val: super::vals::Page61lock1lockNs) {
+        self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize);
+    }
+    #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."]
+    #[inline(always)]
+    pub const fn lock_bl(&self) -> super::vals::Page61lock1lockBl {
+        let val = (self.0 >> 4usize) & 0x03;
+        super::vals::Page61lock1lockBl::from_bits(val as u8)
+    }
+    #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."]
+    #[inline(always)]
+    pub fn set_lock_bl(&mut self, val: super::vals::Page61lock1lockBl) {
+        self.0 = (self.0 & !(0x03 << 4usize)) | (((val.to_bits() as u32) & 0x03) << 4usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r1(&self) -> u8 {
+        let val = (self.0 >> 8usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r1(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r2(&self) -> u8 {
+        let val = (self.0 >> 16usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r2(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize);
+    }
+}
+impl Default for Page61lock1 {
+    #[inline(always)]
+    fn default() -> Page61lock1 {
+        Page61lock1(0)
+    }
+}
+#[doc = "Lock configuration LSBs for page 62 (rows 0xf80 through 0xfbf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Page62lock0(pub u32);
+impl Page62lock0 {
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub const fn key_w(&self) -> u8 {
+        let val = (self.0 >> 0usize) & 0x07;
+        val as u8
+    }
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub fn set_key_w(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x07 << 0usize)) | (((val as u32) & 0x07) << 0usize);
+    }
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub const fn key_r(&self) -> u8 {
+        let val = (self.0 >> 3usize) & 0x07;
+        val as u8
+    }
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub fn set_key_r(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x07 << 3usize)) | (((val as u32) & 0x07) << 3usize);
+    }
+    #[doc = "State when at least one key is registered for this page and no matching key has been entered."]
+    #[inline(always)]
+    pub const fn no_key_state(&self) -> super::vals::Page62lock0noKeyState {
+        let val = (self.0 >> 6usize) & 0x01;
+        super::vals::Page62lock0noKeyState::from_bits(val as u8)
+    }
+    #[doc = "State when at least one key is registered for this page and no matching key has been entered."]
+    #[inline(always)]
+    pub fn set_no_key_state(&mut self, val: super::vals::Page62lock0noKeyState) {
+        self.0 = (self.0 & !(0x01 << 6usize)) | (((val.to_bits() as u32) & 0x01) << 6usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r1(&self) -> u8 {
+        let val = (self.0 >> 8usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r1(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r2(&self) -> u8 {
+        let val = (self.0 >> 16usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r2(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize);
+    }
+}
+impl Default for Page62lock0 {
+    #[inline(always)]
+    fn default() -> Page62lock0 {
+        Page62lock0(0)
+    }
+}
+#[doc = "Lock configuration MSBs for page 62 (rows 0xf80 through 0xfbf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Page62lock1(pub u32);
+impl Page62lock1 {
+    #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."]
+    #[inline(always)]
+    pub const fn lock_s(&self) -> super::vals::Page62lock1lockS {
+        let val = (self.0 >> 0usize) & 0x03;
+        super::vals::Page62lock1lockS::from_bits(val as u8)
+    }
+    #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."]
+    #[inline(always)]
+    pub fn set_lock_s(&mut self, val: super::vals::Page62lock1lockS) {
+        self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize);
+    }
+    #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."]
+    #[inline(always)]
+    pub const fn lock_ns(&self) -> super::vals::Page62lock1lockNs {
+        let val = (self.0 >> 2usize) & 0x03;
+        super::vals::Page62lock1lockNs::from_bits(val as u8)
+    }
+    #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."]
+    #[inline(always)]
+    pub fn set_lock_ns(&mut self, val: super::vals::Page62lock1lockNs) {
+        self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize);
+    }
+    #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."]
+    #[inline(always)]
+    pub const fn lock_bl(&self) -> super::vals::Page62lock1lockBl {
+        let val = (self.0 >> 4usize) & 0x03;
+        super::vals::Page62lock1lockBl::from_bits(val as u8)
+    }
+    #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."]
+    #[inline(always)]
+    pub fn set_lock_bl(&mut self, val: super::vals::Page62lock1lockBl) {
+        self.0 = (self.0 & !(0x03 << 4usize)) | (((val.to_bits() as u32) & 0x03) << 4usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r1(&self) -> u8 {
+        let val = (self.0 >> 8usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r1(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r2(&self) -> u8 {
+        let val = (self.0 >> 16usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r2(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize);
+    }
+}
+impl Default for Page62lock1 {
+    #[inline(always)]
+    fn default() -> Page62lock1 {
+        Page62lock1(0)
+    }
+}
+#[doc = "Lock configuration LSBs for page 63 (rows 0xfc0 through 0xfff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Page63lock0(pub u32);
+impl Page63lock0 {
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub const fn key_w(&self) -> u8 {
+        let val = (self.0 >> 0usize) & 0x07;
+        val as u8
+    }
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub fn set_key_w(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x07 << 0usize)) | (((val as u32) & 0x07) << 0usize);
+    }
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub const fn key_r(&self) -> u8 {
+        let val = (self.0 >> 3usize) & 0x07;
+        val as u8
+    }
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub fn set_key_r(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x07 << 3usize)) | (((val as u32) & 0x07) << 3usize);
+    }
+    #[doc = "State when at least one key is registered for this page and no matching key has been entered."]
+    #[inline(always)]
+    pub const fn no_key_state(&self) -> super::vals::Page63lock0noKeyState {
+        let val = (self.0 >> 6usize) & 0x01;
+        super::vals::Page63lock0noKeyState::from_bits(val as u8)
+    }
+    #[doc = "State when at least one key is registered for this page and no matching key has been entered."]
+    #[inline(always)]
+    pub fn set_no_key_state(&mut self, val: super::vals::Page63lock0noKeyState) {
+        self.0 = (self.0 & !(0x01 << 6usize)) | (((val.to_bits() as u32) & 0x01) << 6usize);
+    }
+    #[doc = "Decommission for RMA of a suspected faulty device. This re-enables the factory test JTAG interface, and makes pages 3 through 61 of the OTP permanently inaccessible."]
+    #[inline(always)]
+    pub const fn rma(&self) -> bool {
+        let val = (self.0 >> 7usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Decommission for RMA of a suspected faulty device. This re-enables the factory test JTAG interface, and makes pages 3 through 61 of the OTP permanently inaccessible."]
+    #[inline(always)]
+    pub fn set_rma(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r1(&self) -> u8 {
+        let val = (self.0 >> 8usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r1(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r2(&self) -> u8 {
+        let val = (self.0 >> 16usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r2(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize);
+    }
+}
+impl Default for Page63lock0 {
+    #[inline(always)]
+    fn default() -> Page63lock0 {
+        Page63lock0(0)
+    }
+}
+#[doc = "Lock configuration MSBs for page 63 (rows 0xfc0 through 0xfff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Page63lock1(pub u32);
+impl Page63lock1 {
+    #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."]
+    #[inline(always)]
+    pub const fn lock_s(&self) -> super::vals::Page63lock1lockS {
+        let val = (self.0 >> 0usize) & 0x03;
+        super::vals::Page63lock1lockS::from_bits(val as u8)
+    }
+    #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."]
+    #[inline(always)]
+    pub fn set_lock_s(&mut self, val: super::vals::Page63lock1lockS) {
+        self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize);
+    }
+    #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."]
+    #[inline(always)]
+    pub const fn lock_ns(&self) -> super::vals::Page63lock1lockNs {
+        let val = (self.0 >> 2usize) & 0x03;
+        super::vals::Page63lock1lockNs::from_bits(val as u8)
+    }
+    #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."]
+    #[inline(always)]
+    pub fn set_lock_ns(&mut self, val: super::vals::Page63lock1lockNs) {
+        self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize);
+    }
+    #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."]
+    #[inline(always)]
+    pub const fn lock_bl(&self) -> super::vals::Page63lock1lockBl {
+        let val = (self.0 >> 4usize) & 0x03;
+        super::vals::Page63lock1lockBl::from_bits(val as u8)
+    }
+    #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."]
+    #[inline(always)]
+    pub fn set_lock_bl(&mut self, val: super::vals::Page63lock1lockBl) {
+        self.0 = (self.0 & !(0x03 << 4usize)) | (((val.to_bits() as u32) & 0x03) << 4usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r1(&self) -> u8 {
+        let val = (self.0 >> 8usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r1(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r2(&self) -> u8 {
+        let val = (self.0 >> 16usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r2(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize);
+    }
+}
+impl Default for Page63lock1 {
+    #[inline(always)]
+    fn default() -> Page63lock1 {
+        Page63lock1(0)
+    }
+}
+#[doc = "Lock configuration LSBs for page 6 (rows 0x180 through 0x1bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Page6lock0(pub u32);
+impl Page6lock0 {
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub const fn key_w(&self) -> u8 {
+        let val = (self.0 >> 0usize) & 0x07;
+        val as u8
+    }
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub fn set_key_w(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x07 << 0usize)) | (((val as u32) & 0x07) << 0usize);
+    }
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub const fn key_r(&self) -> u8 {
+        let val = (self.0 >> 3usize) & 0x07;
+        val as u8
+    }
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub fn set_key_r(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x07 << 3usize)) | (((val as u32) & 0x07) << 3usize);
+    }
+    #[doc = "State when at least one key is registered for this page and no matching key has been entered."]
+    #[inline(always)]
+    pub const fn no_key_state(&self) -> super::vals::Page6lock0noKeyState {
+        let val = (self.0 >> 6usize) & 0x01;
+        super::vals::Page6lock0noKeyState::from_bits(val as u8)
+    }
+    #[doc = "State when at least one key is registered for this page and no matching key has been entered."]
+    #[inline(always)]
+    pub fn set_no_key_state(&mut self, val: super::vals::Page6lock0noKeyState) {
+        self.0 = (self.0 & !(0x01 << 6usize)) | (((val.to_bits() as u32) & 0x01) << 6usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r1(&self) -> u8 {
+        let val = (self.0 >> 8usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r1(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r2(&self) -> u8 {
+        let val = (self.0 >> 16usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r2(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize);
+    }
+}
+impl Default for Page6lock0 {
+    #[inline(always)]
+    fn default() -> Page6lock0 {
+        Page6lock0(0)
+    }
+}
+#[doc = "Lock configuration MSBs for page 6 (rows 0x180 through 0x1bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Page6lock1(pub u32);
+impl Page6lock1 {
+    #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."]
+    #[inline(always)]
+    pub const fn lock_s(&self) -> super::vals::Page6lock1lockS {
+        let val = (self.0 >> 0usize) & 0x03;
+        super::vals::Page6lock1lockS::from_bits(val as u8)
+    }
+    #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."]
+    #[inline(always)]
+    pub fn set_lock_s(&mut self, val: super::vals::Page6lock1lockS) {
+        self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize);
+    }
+    #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."]
+    #[inline(always)]
+    pub const fn lock_ns(&self) -> super::vals::Page6lock1lockNs {
+        let val = (self.0 >> 2usize) & 0x03;
+        super::vals::Page6lock1lockNs::from_bits(val as u8)
+    }
+    #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."]
+    #[inline(always)]
+    pub fn set_lock_ns(&mut self, val: super::vals::Page6lock1lockNs) {
+        self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize);
+    }
+    #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."]
+    #[inline(always)]
+    pub const fn lock_bl(&self) -> super::vals::Page6lock1lockBl {
+        let val = (self.0 >> 4usize) & 0x03;
+        super::vals::Page6lock1lockBl::from_bits(val as u8)
+    }
+    #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."]
+    #[inline(always)]
+    pub fn set_lock_bl(&mut self, val: super::vals::Page6lock1lockBl) {
+        self.0 = (self.0 & !(0x03 << 4usize)) | (((val.to_bits() as u32) & 0x03) << 4usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r1(&self) -> u8 {
+        let val = (self.0 >> 8usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r1(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r2(&self) -> u8 {
+        let val = (self.0 >> 16usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r2(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize);
+    }
+}
+impl Default for Page6lock1 {
+    #[inline(always)]
+    fn default() -> Page6lock1 {
+        Page6lock1(0)
+    }
+}
+#[doc = "Lock configuration LSBs for page 7 (rows 0x1c0 through 0x1ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Page7lock0(pub u32);
+impl Page7lock0 {
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub const fn key_w(&self) -> u8 {
+        let val = (self.0 >> 0usize) & 0x07;
+        val as u8
+    }
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub fn set_key_w(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x07 << 0usize)) | (((val as u32) & 0x07) << 0usize);
+    }
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub const fn key_r(&self) -> u8 {
+        let val = (self.0 >> 3usize) & 0x07;
+        val as u8
+    }
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub fn set_key_r(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x07 << 3usize)) | (((val as u32) & 0x07) << 3usize);
+    }
+    #[doc = "State when at least one key is registered for this page and no matching key has been entered."]
+    #[inline(always)]
+    pub const fn no_key_state(&self) -> super::vals::Page7lock0noKeyState {
+        let val = (self.0 >> 6usize) & 0x01;
+        super::vals::Page7lock0noKeyState::from_bits(val as u8)
+    }
+    #[doc = "State when at least one key is registered for this page and no matching key has been entered."]
+    #[inline(always)]
+    pub fn set_no_key_state(&mut self, val: super::vals::Page7lock0noKeyState) {
+        self.0 = (self.0 & !(0x01 << 6usize)) | (((val.to_bits() as u32) & 0x01) << 6usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r1(&self) -> u8 {
+        let val = (self.0 >> 8usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r1(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r2(&self) -> u8 {
+        let val = (self.0 >> 16usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r2(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize);
+    }
+}
+impl Default for Page7lock0 {
+    #[inline(always)]
+    fn default() -> Page7lock0 {
+        Page7lock0(0)
+    }
+}
+#[doc = "Lock configuration MSBs for page 7 (rows 0x1c0 through 0x1ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Page7lock1(pub u32);
+impl Page7lock1 {
+    #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."]
+    #[inline(always)]
+    pub const fn lock_s(&self) -> super::vals::Page7lock1lockS {
+        let val = (self.0 >> 0usize) & 0x03;
+        super::vals::Page7lock1lockS::from_bits(val as u8)
+    }
+    #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."]
+    #[inline(always)]
+    pub fn set_lock_s(&mut self, val: super::vals::Page7lock1lockS) {
+        self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize);
+    }
+    #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."]
+    #[inline(always)]
+    pub const fn lock_ns(&self) -> super::vals::Page7lock1lockNs {
+        let val = (self.0 >> 2usize) & 0x03;
+        super::vals::Page7lock1lockNs::from_bits(val as u8)
+    }
+    #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."]
+    #[inline(always)]
+    pub fn set_lock_ns(&mut self, val: super::vals::Page7lock1lockNs) {
+        self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize);
+    }
+    #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."]
+    #[inline(always)]
+    pub const fn lock_bl(&self) -> super::vals::Page7lock1lockBl {
+        let val = (self.0 >> 4usize) & 0x03;
+        super::vals::Page7lock1lockBl::from_bits(val as u8)
+    }
+    #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."]
+    #[inline(always)]
+    pub fn set_lock_bl(&mut self, val: super::vals::Page7lock1lockBl) {
+        self.0 = (self.0 & !(0x03 << 4usize)) | (((val.to_bits() as u32) & 0x03) << 4usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r1(&self) -> u8 {
+        let val = (self.0 >> 8usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r1(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r2(&self) -> u8 {
+        let val = (self.0 >> 16usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r2(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize);
+    }
+}
+impl Default for Page7lock1 {
+    #[inline(always)]
+    fn default() -> Page7lock1 {
+        Page7lock1(0)
+    }
+}
+#[doc = "Lock configuration LSBs for page 8 (rows 0x200 through 0x23f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Page8lock0(pub u32);
+impl Page8lock0 {
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub const fn key_w(&self) -> u8 {
+        let val = (self.0 >> 0usize) & 0x07;
+        val as u8
+    }
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub fn set_key_w(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x07 << 0usize)) | (((val as u32) & 0x07) << 0usize);
+    }
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub const fn key_r(&self) -> u8 {
+        let val = (self.0 >> 3usize) & 0x07;
+        val as u8
+    }
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub fn set_key_r(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x07 << 3usize)) | (((val as u32) & 0x07) << 3usize);
+    }
+    #[doc = "State when at least one key is registered for this page and no matching key has been entered."]
+    #[inline(always)]
+    pub const fn no_key_state(&self) -> super::vals::Page8lock0noKeyState {
+        let val = (self.0 >> 6usize) & 0x01;
+        super::vals::Page8lock0noKeyState::from_bits(val as u8)
+    }
+    #[doc = "State when at least one key is registered for this page and no matching key has been entered."]
+    #[inline(always)]
+    pub fn set_no_key_state(&mut self, val: super::vals::Page8lock0noKeyState) {
+        self.0 = (self.0 & !(0x01 << 6usize)) | (((val.to_bits() as u32) & 0x01) << 6usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r1(&self) -> u8 {
+        let val = (self.0 >> 8usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r1(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r2(&self) -> u8 {
+        let val = (self.0 >> 16usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r2(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize);
+    }
+}
+impl Default for Page8lock0 {
+    #[inline(always)]
+    fn default() -> Page8lock0 {
+        Page8lock0(0)
+    }
+}
+#[doc = "Lock configuration MSBs for page 8 (rows 0x200 through 0x23f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Page8lock1(pub u32);
+impl Page8lock1 {
+    #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."]
+    #[inline(always)]
+    pub const fn lock_s(&self) -> super::vals::Page8lock1lockS {
+        let val = (self.0 >> 0usize) & 0x03;
+        super::vals::Page8lock1lockS::from_bits(val as u8)
+    }
+    #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."]
+    #[inline(always)]
+    pub fn set_lock_s(&mut self, val: super::vals::Page8lock1lockS) {
+        self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize);
+    }
+    #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."]
+    #[inline(always)]
+    pub const fn lock_ns(&self) -> super::vals::Page8lock1lockNs {
+        let val = (self.0 >> 2usize) & 0x03;
+        super::vals::Page8lock1lockNs::from_bits(val as u8)
+    }
+    #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."]
+    #[inline(always)]
+    pub fn set_lock_ns(&mut self, val: super::vals::Page8lock1lockNs) {
+        self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize);
+    }
+    #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."]
+    #[inline(always)]
+    pub const fn lock_bl(&self) -> super::vals::Page8lock1lockBl {
+        let val = (self.0 >> 4usize) & 0x03;
+        super::vals::Page8lock1lockBl::from_bits(val as u8)
+    }
+    #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."]
+    #[inline(always)]
+    pub fn set_lock_bl(&mut self, val: super::vals::Page8lock1lockBl) {
+        self.0 = (self.0 & !(0x03 << 4usize)) | (((val.to_bits() as u32) & 0x03) << 4usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r1(&self) -> u8 {
+        let val = (self.0 >> 8usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r1(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r2(&self) -> u8 {
+        let val = (self.0 >> 16usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r2(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize);
+    }
+}
+impl Default for Page8lock1 {
+    #[inline(always)]
+    fn default() -> Page8lock1 {
+        Page8lock1(0)
+    }
+}
+#[doc = "Lock configuration LSBs for page 9 (rows 0x240 through 0x27f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Page9lock0(pub u32);
+impl Page9lock0 {
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub const fn key_w(&self) -> u8 {
+        let val = (self.0 >> 0usize) & 0x07;
+        val as u8
+    }
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub fn set_key_w(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x07 << 0usize)) | (((val as u32) & 0x07) << 0usize);
+    }
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub const fn key_r(&self) -> u8 {
+        let val = (self.0 >> 3usize) & 0x07;
+        val as u8
+    }
+    #[doc = "Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."]
+    #[inline(always)]
+    pub fn set_key_r(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x07 << 3usize)) | (((val as u32) & 0x07) << 3usize);
+    }
+    #[doc = "State when at least one key is registered for this page and no matching key has been entered."]
+    #[inline(always)]
+    pub const fn no_key_state(&self) -> super::vals::Page9lock0noKeyState {
+        let val = (self.0 >> 6usize) & 0x01;
+        super::vals::Page9lock0noKeyState::from_bits(val as u8)
+    }
+    #[doc = "State when at least one key is registered for this page and no matching key has been entered."]
+    #[inline(always)]
+    pub fn set_no_key_state(&mut self, val: super::vals::Page9lock0noKeyState) {
+        self.0 = (self.0 & !(0x01 << 6usize)) | (((val.to_bits() as u32) & 0x01) << 6usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r1(&self) -> u8 {
+        let val = (self.0 >> 8usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r1(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r2(&self) -> u8 {
+        let val = (self.0 >> 16usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r2(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize);
+    }
+}
+impl Default for Page9lock0 {
+    #[inline(always)]
+    fn default() -> Page9lock0 {
+        Page9lock0(0)
+    }
+}
+#[doc = "Lock configuration MSBs for page 9 (rows 0x240 through 0x27f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Page9lock1(pub u32);
+impl Page9lock1 {
+    #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."]
+    #[inline(always)]
+    pub const fn lock_s(&self) -> super::vals::Page9lock1lockS {
+        let val = (self.0 >> 0usize) & 0x03;
+        super::vals::Page9lock1lockS::from_bits(val as u8)
+    }
+    #[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."]
+    #[inline(always)]
+    pub fn set_lock_s(&mut self, val: super::vals::Page9lock1lockS) {
+        self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize);
+    }
+    #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."]
+    #[inline(always)]
+    pub const fn lock_ns(&self) -> super::vals::Page9lock1lockNs {
+        let val = (self.0 >> 2usize) & 0x03;
+        super::vals::Page9lock1lockNs::from_bits(val as u8)
+    }
+    #[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."]
+    #[inline(always)]
+    pub fn set_lock_ns(&mut self, val: super::vals::Page9lock1lockNs) {
+        self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize);
+    }
+    #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."]
+    #[inline(always)]
+    pub const fn lock_bl(&self) -> super::vals::Page9lock1lockBl {
+        let val = (self.0 >> 4usize) & 0x03;
+        super::vals::Page9lock1lockBl::from_bits(val as u8)
+    }
+    #[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."]
+    #[inline(always)]
+    pub fn set_lock_bl(&mut self, val: super::vals::Page9lock1lockBl) {
+        self.0 = (self.0 & !(0x03 << 4usize)) | (((val.to_bits() as u32) & 0x03) << 4usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r1(&self) -> u8 {
+        let val = (self.0 >> 8usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r1(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize);
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub const fn r2(&self) -> u8 {
+        let val = (self.0 >> 16usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Redundant copy of bits 7:0"]
+    #[inline(always)]
+    pub fn set_r2(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize);
+    }
+}
+impl Default for Page9lock1 {
+    #[inline(always)]
+    fn default() -> Page9lock1 {
+        Page9lock1(0)
+    }
+}
+#[doc = "Bits 15:0 of private per-device random number (ECC) The RANDID0..7 rows form a 128-bit random number generated during device test. This ID is not exposed through the USB PICOBOOT GET_INFO command or the ROM `get_sys_info()` API. However note that the USB PICOBOOT OTP access point can read the entirety of page 0, so this value is not meaningfully private unless the USB PICOBOOT interface is disabled via the DISABLE_BOOTSEL_USB_PICOBOOT_IFC flag in BOOT_FLAGS0."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Randid0(pub u32);
+impl Randid0 {
+    #[inline(always)]
+    pub const fn randid0(&self) -> u32 {
+        let val = (self.0 >> 0usize) & 0x00ff_ffff;
+        val as u32
+    }
+    #[inline(always)]
+    pub fn set_randid0(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize);
+    }
+}
+impl Default for Randid0 {
+    #[inline(always)]
+    fn default() -> Randid0 {
+        Randid0(0)
+    }
+}
+#[doc = "Bits 31:16 of private per-device random number (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Randid1(pub u32);
+impl Randid1 {
+    #[inline(always)]
+    pub const fn randid1(&self) -> u32 {
+        let val = (self.0 >> 0usize) & 0x00ff_ffff;
+        val as u32
+    }
+    #[inline(always)]
+    pub fn set_randid1(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize);
+    }
+}
+impl Default for Randid1 {
+    #[inline(always)]
+    fn default() -> Randid1 {
+        Randid1(0)
+    }
+}
+#[doc = "Bits 47:32 of private per-device random number (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Randid2(pub u32);
+impl Randid2 {
+    #[inline(always)]
+    pub const fn randid2(&self) -> u32 {
+        let val = (self.0 >> 0usize) & 0x00ff_ffff;
+        val as u32
+    }
+    #[inline(always)]
+    pub fn set_randid2(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize);
+    }
+}
+impl Default for Randid2 {
+    #[inline(always)]
+    fn default() -> Randid2 {
+        Randid2(0)
+    }
+}
+#[doc = "Bits 63:48 of private per-device random number (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Randid3(pub u32);
+impl Randid3 {
+    #[inline(always)]
+    pub const fn randid3(&self) -> u32 {
+        let val = (self.0 >> 0usize) & 0x00ff_ffff;
+        val as u32
+    }
+    #[inline(always)]
+    pub fn set_randid3(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize);
+    }
+}
+impl Default for Randid3 {
+    #[inline(always)]
+    fn default() -> Randid3 {
+        Randid3(0)
+    }
+}
+#[doc = "Bits 79:64 of private per-device random number (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Randid4(pub u32);
+impl Randid4 {
+    #[inline(always)]
+    pub const fn randid4(&self) -> u32 {
+        let val = (self.0 >> 0usize) & 0x00ff_ffff;
+        val as u32
+    }
+    #[inline(always)]
+    pub fn set_randid4(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize);
+    }
+}
+impl Default for Randid4 {
+    #[inline(always)]
+    fn default() -> Randid4 {
+        Randid4(0)
+    }
+}
+#[doc = "Bits 95:80 of private per-device random number (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Randid5(pub u32);
+impl Randid5 {
+    #[inline(always)]
+    pub const fn randid5(&self) -> u32 {
+        let val = (self.0 >> 0usize) & 0x00ff_ffff;
+        val as u32
+    }
+    #[inline(always)]
+    pub fn set_randid5(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize);
+    }
+}
+impl Default for Randid5 {
+    #[inline(always)]
+    fn default() -> Randid5 {
+        Randid5(0)
+    }
+}
+#[doc = "Bits 111:96 of private per-device random number (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Randid6(pub u32);
+impl Randid6 {
+    #[inline(always)]
+    pub const fn randid6(&self) -> u32 {
+        let val = (self.0 >> 0usize) & 0x00ff_ffff;
+        val as u32
+    }
+    #[inline(always)]
+    pub fn set_randid6(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize);
+    }
+}
+impl Default for Randid6 {
+    #[inline(always)]
+    fn default() -> Randid6 {
+        Randid6(0)
+    }
+}
+#[doc = "Bits 127:112 of private per-device random number (ECC)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Randid7(pub u32);
+impl Randid7 {
+    #[inline(always)]
+    pub const fn randid7(&self) -> u32 {
+        let val = (self.0 >> 0usize) & 0x00ff_ffff;
+        val as u32
+    }
+    #[inline(always)]
+    pub fn set_randid7(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize);
+    }
+}
+impl Default for Randid7 {
+    #[inline(always)]
+    fn default() -> Randid7 {
+        Randid7(0)
+    }
+}
+#[doc = "Ring oscillator frequency in kHz, measured during manufacturing (ECC) This is measured at 1.1 V, at room temperature, with the ROSC configuration registers in their reset state."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct RoscCalib(pub u32);
+impl RoscCalib {
+    #[inline(always)]
+    pub const fn rosc_calib(&self) -> u32 {
+        let val = (self.0 >> 0usize) & 0x00ff_ffff;
+        val as u32
+    }
+    #[inline(always)]
+    pub fn set_rosc_calib(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize);
+    }
+}
+impl Default for RoscCalib {
+    #[inline(always)]
+    fn default() -> RoscCalib {
+        RoscCalib(0)
+    }
+}
+#[doc = "USB boot specific feature flags (RBIT-3)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct UsbBootFlags(pub u32);
+impl UsbBootFlags {
+    #[doc = "valid flag for USB_DEVICE_VID_VALUE entry of the USB_WHITE_LABEL struct (index 0)"]
+    #[inline(always)]
+    pub const fn wl_usb_device_vid_value_valid(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "valid flag for USB_DEVICE_VID_VALUE entry of the USB_WHITE_LABEL struct (index 0)"]
+    #[inline(always)]
+    pub fn set_wl_usb_device_vid_value_valid(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[doc = "valid flag for USB_DEVICE_PID_VALUE entry of the USB_WHITE_LABEL struct (index 1)"]
+    #[inline(always)]
+    pub const fn wl_usb_device_pid_value_valid(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[doc = "valid flag for USB_DEVICE_PID_VALUE entry of the USB_WHITE_LABEL struct (index 1)"]
+    #[inline(always)]
+    pub fn set_wl_usb_device_pid_value_valid(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+    #[doc = "valid flag for USB_DEVICE_BCD_DEVICEVALUE entry of the USB_WHITE_LABEL struct (index 2)"]
+    #[inline(always)]
+    pub const fn wl_usb_device_serial_number_value_valid(&self) -> bool {
+        let val = (self.0 >> 2usize) & 0x01;
+        val != 0
+    }
+    #[doc = "valid flag for USB_DEVICE_BCD_DEVICEVALUE entry of the USB_WHITE_LABEL struct (index 2)"]
+    #[inline(always)]
+    pub fn set_wl_usb_device_serial_number_value_valid(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+    }
+    #[doc = "valid flag for USB_DEVICE_LANG_ID_VALUE entry of the USB_WHITE_LABEL struct (index 3)"]
+    #[inline(always)]
+    pub const fn wl_usb_device_lang_id_value_valid(&self) -> bool {
+        let val = (self.0 >> 3usize) & 0x01;
+        val != 0
+    }
+    #[doc = "valid flag for USB_DEVICE_LANG_ID_VALUE entry of the USB_WHITE_LABEL struct (index 3)"]
+    #[inline(always)]
+    pub fn set_wl_usb_device_lang_id_value_valid(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
+    }
+    #[doc = "valid flag for USB_DEVICE_MANUFACTURER_STRDEF entry of the USB_WHITE_LABEL struct (index 4)"]
+    #[inline(always)]
+    pub const fn wl_usb_device_manufacturer_strdef_valid(&self) -> bool {
+        let val = (self.0 >> 4usize) & 0x01;
+        val != 0
+    }
+    #[doc = "valid flag for USB_DEVICE_MANUFACTURER_STRDEF entry of the USB_WHITE_LABEL struct (index 4)"]
+    #[inline(always)]
+    pub fn set_wl_usb_device_manufacturer_strdef_valid(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
+    }
+    #[doc = "valid flag for USB_DEVICE_PRODUCT_STRDEF entry of the USB_WHITE_LABEL struct (index 5)"]
+    #[inline(always)]
+    pub const fn wl_usb_device_product_strdef_valid(&self) -> bool {
+        let val = (self.0 >> 5usize) & 0x01;
+        val != 0
+    }
+    #[doc = "valid flag for USB_DEVICE_PRODUCT_STRDEF entry of the USB_WHITE_LABEL struct (index 5)"]
+    #[inline(always)]
+    pub fn set_wl_usb_device_product_strdef_valid(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
+    }
+    #[doc = "valid flag for USB_DEVICE_SERIAL_NUMBER_STRDEF entry of the USB_WHITE_LABEL struct (index 6)"]
+    #[inline(always)]
+    pub const fn wl_usb_device_serial_number_strdef_valid(&self) -> bool {
+        let val = (self.0 >> 6usize) & 0x01;
+        val != 0
+    }
+    #[doc = "valid flag for USB_DEVICE_SERIAL_NUMBER_STRDEF entry of the USB_WHITE_LABEL struct (index 6)"]
+    #[inline(always)]
+    pub fn set_wl_usb_device_serial_number_strdef_valid(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
+    }
+    #[doc = "valid flag for USB_CONFIG_ATTRIBUTES_MAX_POWER_VALUES entry of the USB_WHITE_LABEL struct (index 7)"]
+    #[inline(always)]
+    pub const fn wl_usb_config_attributes_max_power_values_valid(&self) -> bool {
+        let val = (self.0 >> 7usize) & 0x01;
+        val != 0
+    }
+    #[doc = "valid flag for USB_CONFIG_ATTRIBUTES_MAX_POWER_VALUES entry of the USB_WHITE_LABEL struct (index 7)"]
+    #[inline(always)]
+    pub fn set_wl_usb_config_attributes_max_power_values_valid(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
+    }
+    #[doc = "valid flag for VOLUME_LABEL_STRDEF entry of the USB_WHITE_LABEL struct (index 8)"]
+    #[inline(always)]
+    pub const fn wl_volume_label_strdef_valid(&self) -> bool {
+        let val = (self.0 >> 8usize) & 0x01;
+        val != 0
+    }
+    #[doc = "valid flag for VOLUME_LABEL_STRDEF entry of the USB_WHITE_LABEL struct (index 8)"]
+    #[inline(always)]
+    pub fn set_wl_volume_label_strdef_valid(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
+    }
+    #[doc = "valid flag for SCSI_INQUIRY_VENDOR_STRDEF entry of the USB_WHITE_LABEL struct (index 9)"]
+    #[inline(always)]
+    pub const fn wl_scsi_inquiry_vendor_strdef_valid(&self) -> bool {
+        let val = (self.0 >> 9usize) & 0x01;
+        val != 0
+    }
+    #[doc = "valid flag for SCSI_INQUIRY_VENDOR_STRDEF entry of the USB_WHITE_LABEL struct (index 9)"]
+    #[inline(always)]
+    pub fn set_wl_scsi_inquiry_vendor_strdef_valid(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
+    }
+    #[doc = "valid flag for SCSI_INQUIRY_PRODUCT_STRDEF entry of the USB_WHITE_LABEL struct (index 10)"]
+    #[inline(always)]
+    pub const fn wl_scsi_inquiry_product_strdef_valid(&self) -> bool {
+        let val = (self.0 >> 10usize) & 0x01;
+        val != 0
+    }
+    #[doc = "valid flag for SCSI_INQUIRY_PRODUCT_STRDEF entry of the USB_WHITE_LABEL struct (index 10)"]
+    #[inline(always)]
+    pub fn set_wl_scsi_inquiry_product_strdef_valid(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize);
+    }
+    #[doc = "valid flag for SCSI_INQUIRY_VERSION_STRDEF entry of the USB_WHITE_LABEL struct (index 11)"]
+    #[inline(always)]
+    pub const fn wl_scsi_inquiry_version_strdef_valid(&self) -> bool {
+        let val = (self.0 >> 11usize) & 0x01;
+        val != 0
+    }
+    #[doc = "valid flag for SCSI_INQUIRY_VERSION_STRDEF entry of the USB_WHITE_LABEL struct (index 11)"]
+    #[inline(always)]
+    pub fn set_wl_scsi_inquiry_version_strdef_valid(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
+    }
+    #[doc = "valid flag for INDEX_HTM_REDIRECT_URL_STRDEF entry of the USB_WHITE_LABEL struct (index 12)"]
+    #[inline(always)]
+    pub const fn wl_index_htm_redirect_url_strdef_valid(&self) -> bool {
+        let val = (self.0 >> 12usize) & 0x01;
+        val != 0
+    }
+    #[doc = "valid flag for INDEX_HTM_REDIRECT_URL_STRDEF entry of the USB_WHITE_LABEL struct (index 12)"]
+    #[inline(always)]
+    pub fn set_wl_index_htm_redirect_url_strdef_valid(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
+    }
+    #[doc = "valid flag for INDEX_HTM_REDIRECT_NAME_STRDEF entry of the USB_WHITE_LABEL struct (index 13)"]
+    #[inline(always)]
+    pub const fn wl_index_htm_redirect_name_strdef_valid(&self) -> bool {
+        let val = (self.0 >> 13usize) & 0x01;
+        val != 0
+    }
+    #[doc = "valid flag for INDEX_HTM_REDIRECT_NAME_STRDEF entry of the USB_WHITE_LABEL struct (index 13)"]
+    #[inline(always)]
+    pub fn set_wl_index_htm_redirect_name_strdef_valid(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize);
+    }
+    #[doc = "valid flag for INFO_UF2_TXT_MODEL_STRDEF entry of the USB_WHITE_LABEL struct (index 14)"]
+    #[inline(always)]
+    pub const fn wl_info_uf2_txt_model_strdef_valid(&self) -> bool {
+        let val = (self.0 >> 14usize) & 0x01;
+        val != 0
+    }
+    #[doc = "valid flag for INFO_UF2_TXT_MODEL_STRDEF entry of the USB_WHITE_LABEL struct (index 14)"]
+    #[inline(always)]
+    pub fn set_wl_info_uf2_txt_model_strdef_valid(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize);
+    }
+    #[doc = "valid flag for the USB_WHITE_LABEL_ADDR field"]
+    #[inline(always)]
+    pub const fn wl_info_uf2_txt_board_id_strdef_valid(&self) -> bool {
+        let val = (self.0 >> 15usize) & 0x01;
+        val != 0
+    }
+    #[doc = "valid flag for the USB_WHITE_LABEL_ADDR field"]
+    #[inline(always)]
+    pub fn set_wl_info_uf2_txt_board_id_strdef_valid(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize);
+    }
+    #[doc = "valid flag for INFO_UF2_TXT_BOARD_ID_STRDEF entry of the USB_WHITE_LABEL struct (index 15)"]
+    #[inline(always)]
+    pub const fn white_label_addr_valid(&self) -> bool {
+        let val = (self.0 >> 22usize) & 0x01;
+        val != 0
+    }
+    #[doc = "valid flag for INFO_UF2_TXT_BOARD_ID_STRDEF entry of the USB_WHITE_LABEL struct (index 15)"]
+    #[inline(always)]
+    pub fn set_white_label_addr_valid(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 22usize)) | (((val as u32) & 0x01) << 22usize);
+    }
+    #[doc = "Swap DM/DP during USB boot, to support board layouts with mirrored USB routing (deliberate or accidental)."]
+    #[inline(always)]
+    pub const fn dp_dm_swap(&self) -> bool {
+        let val = (self.0 >> 23usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Swap DM/DP during USB boot, to support board layouts with mirrored USB routing (deliberate or accidental)."]
+    #[inline(always)]
+    pub fn set_dp_dm_swap(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 23usize)) | (((val as u32) & 0x01) << 23usize);
+    }
+}
+impl Default for UsbBootFlags {
+    #[inline(always)]
+    fn default() -> UsbBootFlags {
+        UsbBootFlags(0)
+    }
+}
+#[doc = "Redundant copy of USB_BOOT_FLAGS"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct UsbBootFlagsR1(pub u32);
+impl UsbBootFlagsR1 {
+    #[inline(always)]
+    pub const fn usb_boot_flags_r1(&self) -> u32 {
+        let val = (self.0 >> 0usize) & 0x00ff_ffff;
+        val as u32
+    }
+    #[inline(always)]
+    pub fn set_usb_boot_flags_r1(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize);
+    }
+}
+impl Default for UsbBootFlagsR1 {
+    #[inline(always)]
+    fn default() -> UsbBootFlagsR1 {
+        UsbBootFlagsR1(0)
+    }
+}
+#[doc = "Redundant copy of USB_BOOT_FLAGS"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct UsbBootFlagsR2(pub u32);
+impl UsbBootFlagsR2 {
+    #[inline(always)]
+    pub const fn usb_boot_flags_r2(&self) -> u32 {
+        let val = (self.0 >> 0usize) & 0x00ff_ffff;
+        val as u32
+    }
+    #[inline(always)]
+    pub fn set_usb_boot_flags_r2(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize);
+    }
+}
+impl Default for UsbBootFlagsR2 {
+    #[inline(always)]
+    fn default() -> UsbBootFlagsR2 {
+        UsbBootFlagsR2(0)
+    }
+}
+#[doc = "Row index of the USB_WHITE_LABEL structure within OTP (ECC) The table has 16 rows, each of which are also ECC and marked valid by the corresponding valid bit in USB_BOOT_FLAGS (ECC). The entries are either _VALUEs where the 16 bit value is used as is, or _STRDEFs which acts as a pointers to a string value. The value stored in a _STRDEF is two separate bytes: The low seven bits of the first (LSB) byte indicates the number of characters in the string, and the top bit of the first (LSB) byte if set to indicate that each character in the string is two bytes (Unicode) versus one byte if unset. The second (MSB) byte represents the location of the string data, and is encoded as the number of rows from this USB_WHITE_LABEL_ADDR; i.e. the row of the start of the string is USB_WHITE_LABEL_ADDR value + msb_byte. In each case, the corresponding valid bit enables replacing the default value for the corresponding item provided by the boot rom. Note that Unicode _STRDEFs are only supported for USB_DEVICE_PRODUCT_STRDEF, USB_DEVICE_SERIAL_NUMBER_STRDEF and USB_DEVICE_MANUFACTURER_STRDEF. Unicode values will be ignored if specified for other fields, and non-unicode values for these three items will be converted to Unicode characters by setting the upper 8 bits to zero. Note that if the USB_WHITE_LABEL structure or the corresponding strings are not readable by BOOTSEL mode based on OTP permissions, or if alignment requirements are not met, then the corresponding default values are used. The index values indicate where each field is located (row USB_WHITE_LABEL_ADDR value + index):"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct UsbWhiteLabelAddr(pub u32);
+impl UsbWhiteLabelAddr {
+    #[inline(always)]
+    pub const fn usb_white_label_addr(&self) -> super::vals::UsbWhiteLabelAddr {
+        let val = (self.0 >> 0usize) & 0x00ff_ffff;
+        super::vals::UsbWhiteLabelAddr::from_bits(val as u32)
+    }
+    #[inline(always)]
+    pub fn set_usb_white_label_addr(&mut self, val: super::vals::UsbWhiteLabelAddr) {
+        self.0 = (self.0 & !(0x00ff_ffff << 0usize))
+            | (((val.to_bits() as u32) & 0x00ff_ffff) << 0usize);
+    }
+}
+impl Default for UsbWhiteLabelAddr {
+    #[inline(always)]
+    fn default() -> UsbWhiteLabelAddr {
+        UsbWhiteLabelAddr(0)
+    }
+}
diff --git a/src/rp2350/otp_data_raw/vals.rs b/src/rp2350/otp_data_raw/vals.rs
new file mode 100644
index 00000000..c6337e79
--- /dev/null
+++ b/src/rp2350/otp_data_raw/vals.rs
@@ -0,0 +1,8470 @@
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Cs0size {
+    NONE = 0,
+    _8K = 0x01,
+    _16K = 0x02,
+    _32K = 0x03,
+    _64K = 0x04,
+    _128K = 0x05,
+    _256K = 0x06,
+    _512K = 0x07,
+    _1M = 0x08,
+    _2M = 0x09,
+    _4M = 0x0a,
+    _8M = 0x0b,
+    _16M = 0x0c,
+    _RESERVED_d = 0x0d,
+    _RESERVED_e = 0x0e,
+    _RESERVED_f = 0x0f,
+}
+impl Cs0size {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Cs0size {
+        unsafe { core::mem::transmute(val & 0x0f) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Cs0size {
+    #[inline(always)]
+    fn from(val: u8) -> Cs0size {
+        Cs0size::from_bits(val)
+    }
+}
+impl From<Cs0size> for u8 {
+    #[inline(always)]
+    fn from(val: Cs0size) -> u8 {
+        Cs0size::to_bits(val)
+    }
+}
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub struct Cs1size(pub u16);
+impl Cs1size {
+    pub const NONE: Self = Self(0);
+    pub const _8K: Self = Self(0x01);
+    pub const _16K: Self = Self(0x02);
+    pub const _32K: Self = Self(0x03);
+    pub const _64K: Self = Self(0x04);
+    pub const _128K: Self = Self(0x05);
+    pub const _256K: Self = Self(0x06);
+    pub const _512K: Self = Self(0x07);
+    pub const _1M: Self = Self(0x08);
+    pub const _2M: Self = Self(0x09);
+    pub const _4M: Self = Self(0x0a);
+    pub const _8M: Self = Self(0x0b);
+    pub const _16M: Self = Self(0x0c);
+}
+impl Cs1size {
+    pub const fn from_bits(val: u16) -> Cs1size {
+        Self(val & 0x0fff)
+    }
+    pub const fn to_bits(self) -> u16 {
+        self.0
+    }
+}
+impl From<u16> for Cs1size {
+    #[inline(always)]
+    fn from(val: u16) -> Cs1size {
+        Cs1size::from_bits(val)
+    }
+}
+impl From<Cs1size> for u16 {
+    #[inline(always)]
+    fn from(val: Cs1size) -> u16 {
+        Cs1size::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page0lock0noKeyState {
+    READ_ONLY = 0,
+    INACCESSIBLE = 0x01,
+}
+impl Page0lock0noKeyState {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page0lock0noKeyState {
+        unsafe { core::mem::transmute(val & 0x01) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page0lock0noKeyState {
+    #[inline(always)]
+    fn from(val: u8) -> Page0lock0noKeyState {
+        Page0lock0noKeyState::from_bits(val)
+    }
+}
+impl From<Page0lock0noKeyState> for u8 {
+    #[inline(always)]
+    fn from(val: Page0lock0noKeyState) -> u8 {
+        Page0lock0noKeyState::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page0lock1lockBl {
+    #[doc = "Bootloader permits user reads and writes to this page"]
+    READ_WRITE = 0,
+    #[doc = "Bootloader permits user reads of this page"]
+    READ_ONLY = 0x01,
+    #[doc = "Do not use. Behaves the same as INACCESSIBLE"]
+    RESERVED = 0x02,
+    #[doc = "Bootloader does not permit user access to this page"]
+    INACCESSIBLE = 0x03,
+}
+impl Page0lock1lockBl {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page0lock1lockBl {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page0lock1lockBl {
+    #[inline(always)]
+    fn from(val: u8) -> Page0lock1lockBl {
+        Page0lock1lockBl::from_bits(val)
+    }
+}
+impl From<Page0lock1lockBl> for u8 {
+    #[inline(always)]
+    fn from(val: Page0lock1lockBl) -> u8 {
+        Page0lock1lockBl::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page0lock1lockNs {
+    #[doc = "Page can be read by Non-secure software, and Secure software may permit Non-secure writes."]
+    READ_WRITE = 0,
+    #[doc = "Page can be read by Non-secure software"]
+    READ_ONLY = 0x01,
+    #[doc = "Do not use. Behaves the same as INACCESSIBLE."]
+    RESERVED = 0x02,
+    #[doc = "Page can not be accessed by Non-secure software."]
+    INACCESSIBLE = 0x03,
+}
+impl Page0lock1lockNs {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page0lock1lockNs {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page0lock1lockNs {
+    #[inline(always)]
+    fn from(val: u8) -> Page0lock1lockNs {
+        Page0lock1lockNs::from_bits(val)
+    }
+}
+impl From<Page0lock1lockNs> for u8 {
+    #[inline(always)]
+    fn from(val: Page0lock1lockNs) -> u8 {
+        Page0lock1lockNs::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page0lock1lockS {
+    #[doc = "Page is fully accessible by Secure software."]
+    READ_WRITE = 0,
+    #[doc = "Page can be read by Secure software, but can not be written."]
+    READ_ONLY = 0x01,
+    #[doc = "Do not use. Behaves the same as INACCESSIBLE."]
+    RESERVED = 0x02,
+    #[doc = "Page can not be accessed by Secure software."]
+    INACCESSIBLE = 0x03,
+}
+impl Page0lock1lockS {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page0lock1lockS {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page0lock1lockS {
+    #[inline(always)]
+    fn from(val: u8) -> Page0lock1lockS {
+        Page0lock1lockS::from_bits(val)
+    }
+}
+impl From<Page0lock1lockS> for u8 {
+    #[inline(always)]
+    fn from(val: Page0lock1lockS) -> u8 {
+        Page0lock1lockS::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page10lock0noKeyState {
+    READ_ONLY = 0,
+    INACCESSIBLE = 0x01,
+}
+impl Page10lock0noKeyState {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page10lock0noKeyState {
+        unsafe { core::mem::transmute(val & 0x01) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page10lock0noKeyState {
+    #[inline(always)]
+    fn from(val: u8) -> Page10lock0noKeyState {
+        Page10lock0noKeyState::from_bits(val)
+    }
+}
+impl From<Page10lock0noKeyState> for u8 {
+    #[inline(always)]
+    fn from(val: Page10lock0noKeyState) -> u8 {
+        Page10lock0noKeyState::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page10lock1lockBl {
+    #[doc = "Bootloader permits user reads and writes to this page"]
+    READ_WRITE = 0,
+    #[doc = "Bootloader permits user reads of this page"]
+    READ_ONLY = 0x01,
+    #[doc = "Do not use. Behaves the same as INACCESSIBLE"]
+    RESERVED = 0x02,
+    #[doc = "Bootloader does not permit user access to this page"]
+    INACCESSIBLE = 0x03,
+}
+impl Page10lock1lockBl {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page10lock1lockBl {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page10lock1lockBl {
+    #[inline(always)]
+    fn from(val: u8) -> Page10lock1lockBl {
+        Page10lock1lockBl::from_bits(val)
+    }
+}
+impl From<Page10lock1lockBl> for u8 {
+    #[inline(always)]
+    fn from(val: Page10lock1lockBl) -> u8 {
+        Page10lock1lockBl::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page10lock1lockNs {
+    #[doc = "Page can be read by Non-secure software, and Secure software may permit Non-secure writes."]
+    READ_WRITE = 0,
+    #[doc = "Page can be read by Non-secure software"]
+    READ_ONLY = 0x01,
+    #[doc = "Do not use. Behaves the same as INACCESSIBLE."]
+    RESERVED = 0x02,
+    #[doc = "Page can not be accessed by Non-secure software."]
+    INACCESSIBLE = 0x03,
+}
+impl Page10lock1lockNs {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page10lock1lockNs {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page10lock1lockNs {
+    #[inline(always)]
+    fn from(val: u8) -> Page10lock1lockNs {
+        Page10lock1lockNs::from_bits(val)
+    }
+}
+impl From<Page10lock1lockNs> for u8 {
+    #[inline(always)]
+    fn from(val: Page10lock1lockNs) -> u8 {
+        Page10lock1lockNs::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page10lock1lockS {
+    #[doc = "Page is fully accessible by Secure software."]
+    READ_WRITE = 0,
+    #[doc = "Page can be read by Secure software, but can not be written."]
+    READ_ONLY = 0x01,
+    #[doc = "Do not use. Behaves the same as INACCESSIBLE."]
+    RESERVED = 0x02,
+    #[doc = "Page can not be accessed by Secure software."]
+    INACCESSIBLE = 0x03,
+}
+impl Page10lock1lockS {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page10lock1lockS {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page10lock1lockS {
+    #[inline(always)]
+    fn from(val: u8) -> Page10lock1lockS {
+        Page10lock1lockS::from_bits(val)
+    }
+}
+impl From<Page10lock1lockS> for u8 {
+    #[inline(always)]
+    fn from(val: Page10lock1lockS) -> u8 {
+        Page10lock1lockS::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page11lock0noKeyState {
+    READ_ONLY = 0,
+    INACCESSIBLE = 0x01,
+}
+impl Page11lock0noKeyState {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page11lock0noKeyState {
+        unsafe { core::mem::transmute(val & 0x01) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page11lock0noKeyState {
+    #[inline(always)]
+    fn from(val: u8) -> Page11lock0noKeyState {
+        Page11lock0noKeyState::from_bits(val)
+    }
+}
+impl From<Page11lock0noKeyState> for u8 {
+    #[inline(always)]
+    fn from(val: Page11lock0noKeyState) -> u8 {
+        Page11lock0noKeyState::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page11lock1lockBl {
+    #[doc = "Bootloader permits user reads and writes to this page"]
+    READ_WRITE = 0,
+    #[doc = "Bootloader permits user reads of this page"]
+    READ_ONLY = 0x01,
+    #[doc = "Do not use. Behaves the same as INACCESSIBLE"]
+    RESERVED = 0x02,
+    #[doc = "Bootloader does not permit user access to this page"]
+    INACCESSIBLE = 0x03,
+}
+impl Page11lock1lockBl {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page11lock1lockBl {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page11lock1lockBl {
+    #[inline(always)]
+    fn from(val: u8) -> Page11lock1lockBl {
+        Page11lock1lockBl::from_bits(val)
+    }
+}
+impl From<Page11lock1lockBl> for u8 {
+    #[inline(always)]
+    fn from(val: Page11lock1lockBl) -> u8 {
+        Page11lock1lockBl::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page11lock1lockNs {
+    #[doc = "Page can be read by Non-secure software, and Secure software may permit Non-secure writes."]
+    READ_WRITE = 0,
+    #[doc = "Page can be read by Non-secure software"]
+    READ_ONLY = 0x01,
+    #[doc = "Do not use. Behaves the same as INACCESSIBLE."]
+    RESERVED = 0x02,
+    #[doc = "Page can not be accessed by Non-secure software."]
+    INACCESSIBLE = 0x03,
+}
+impl Page11lock1lockNs {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page11lock1lockNs {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page11lock1lockNs {
+    #[inline(always)]
+    fn from(val: u8) -> Page11lock1lockNs {
+        Page11lock1lockNs::from_bits(val)
+    }
+}
+impl From<Page11lock1lockNs> for u8 {
+    #[inline(always)]
+    fn from(val: Page11lock1lockNs) -> u8 {
+        Page11lock1lockNs::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page11lock1lockS {
+    #[doc = "Page is fully accessible by Secure software."]
+    READ_WRITE = 0,
+    #[doc = "Page can be read by Secure software, but can not be written."]
+    READ_ONLY = 0x01,
+    #[doc = "Do not use. Behaves the same as INACCESSIBLE."]
+    RESERVED = 0x02,
+    #[doc = "Page can not be accessed by Secure software."]
+    INACCESSIBLE = 0x03,
+}
+impl Page11lock1lockS {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page11lock1lockS {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page11lock1lockS {
+    #[inline(always)]
+    fn from(val: u8) -> Page11lock1lockS {
+        Page11lock1lockS::from_bits(val)
+    }
+}
+impl From<Page11lock1lockS> for u8 {
+    #[inline(always)]
+    fn from(val: Page11lock1lockS) -> u8 {
+        Page11lock1lockS::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page12lock0noKeyState {
+    READ_ONLY = 0,
+    INACCESSIBLE = 0x01,
+}
+impl Page12lock0noKeyState {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page12lock0noKeyState {
+        unsafe { core::mem::transmute(val & 0x01) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page12lock0noKeyState {
+    #[inline(always)]
+    fn from(val: u8) -> Page12lock0noKeyState {
+        Page12lock0noKeyState::from_bits(val)
+    }
+}
+impl From<Page12lock0noKeyState> for u8 {
+    #[inline(always)]
+    fn from(val: Page12lock0noKeyState) -> u8 {
+        Page12lock0noKeyState::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page12lock1lockBl {
+    #[doc = "Bootloader permits user reads and writes to this page"]
+    READ_WRITE = 0,
+    #[doc = "Bootloader permits user reads of this page"]
+    READ_ONLY = 0x01,
+    #[doc = "Do not use. Behaves the same as INACCESSIBLE"]
+    RESERVED = 0x02,
+    #[doc = "Bootloader does not permit user access to this page"]
+    INACCESSIBLE = 0x03,
+}
+impl Page12lock1lockBl {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page12lock1lockBl {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page12lock1lockBl {
+    #[inline(always)]
+    fn from(val: u8) -> Page12lock1lockBl {
+        Page12lock1lockBl::from_bits(val)
+    }
+}
+impl From<Page12lock1lockBl> for u8 {
+    #[inline(always)]
+    fn from(val: Page12lock1lockBl) -> u8 {
+        Page12lock1lockBl::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page12lock1lockNs {
+    #[doc = "Page can be read by Non-secure software, and Secure software may permit Non-secure writes."]
+    READ_WRITE = 0,
+    #[doc = "Page can be read by Non-secure software"]
+    READ_ONLY = 0x01,
+    #[doc = "Do not use. Behaves the same as INACCESSIBLE."]
+    RESERVED = 0x02,
+    #[doc = "Page can not be accessed by Non-secure software."]
+    INACCESSIBLE = 0x03,
+}
+impl Page12lock1lockNs {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page12lock1lockNs {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page12lock1lockNs {
+    #[inline(always)]
+    fn from(val: u8) -> Page12lock1lockNs {
+        Page12lock1lockNs::from_bits(val)
+    }
+}
+impl From<Page12lock1lockNs> for u8 {
+    #[inline(always)]
+    fn from(val: Page12lock1lockNs) -> u8 {
+        Page12lock1lockNs::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page12lock1lockS {
+    #[doc = "Page is fully accessible by Secure software."]
+    READ_WRITE = 0,
+    #[doc = "Page can be read by Secure software, but can not be written."]
+    READ_ONLY = 0x01,
+    #[doc = "Do not use. Behaves the same as INACCESSIBLE."]
+    RESERVED = 0x02,
+    #[doc = "Page can not be accessed by Secure software."]
+    INACCESSIBLE = 0x03,
+}
+impl Page12lock1lockS {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page12lock1lockS {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page12lock1lockS {
+    #[inline(always)]
+    fn from(val: u8) -> Page12lock1lockS {
+        Page12lock1lockS::from_bits(val)
+    }
+}
+impl From<Page12lock1lockS> for u8 {
+    #[inline(always)]
+    fn from(val: Page12lock1lockS) -> u8 {
+        Page12lock1lockS::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page13lock0noKeyState {
+    READ_ONLY = 0,
+    INACCESSIBLE = 0x01,
+}
+impl Page13lock0noKeyState {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page13lock0noKeyState {
+        unsafe { core::mem::transmute(val & 0x01) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page13lock0noKeyState {
+    #[inline(always)]
+    fn from(val: u8) -> Page13lock0noKeyState {
+        Page13lock0noKeyState::from_bits(val)
+    }
+}
+impl From<Page13lock0noKeyState> for u8 {
+    #[inline(always)]
+    fn from(val: Page13lock0noKeyState) -> u8 {
+        Page13lock0noKeyState::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page13lock1lockBl {
+    #[doc = "Bootloader permits user reads and writes to this page"]
+    READ_WRITE = 0,
+    #[doc = "Bootloader permits user reads of this page"]
+    READ_ONLY = 0x01,
+    #[doc = "Do not use. Behaves the same as INACCESSIBLE"]
+    RESERVED = 0x02,
+    #[doc = "Bootloader does not permit user access to this page"]
+    INACCESSIBLE = 0x03,
+}
+impl Page13lock1lockBl {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page13lock1lockBl {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page13lock1lockBl {
+    #[inline(always)]
+    fn from(val: u8) -> Page13lock1lockBl {
+        Page13lock1lockBl::from_bits(val)
+    }
+}
+impl From<Page13lock1lockBl> for u8 {
+    #[inline(always)]
+    fn from(val: Page13lock1lockBl) -> u8 {
+        Page13lock1lockBl::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page13lock1lockNs {
+    #[doc = "Page can be read by Non-secure software, and Secure software may permit Non-secure writes."]
+    READ_WRITE = 0,
+    #[doc = "Page can be read by Non-secure software"]
+    READ_ONLY = 0x01,
+    #[doc = "Do not use. Behaves the same as INACCESSIBLE."]
+    RESERVED = 0x02,
+    #[doc = "Page can not be accessed by Non-secure software."]
+    INACCESSIBLE = 0x03,
+}
+impl Page13lock1lockNs {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page13lock1lockNs {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page13lock1lockNs {
+    #[inline(always)]
+    fn from(val: u8) -> Page13lock1lockNs {
+        Page13lock1lockNs::from_bits(val)
+    }
+}
+impl From<Page13lock1lockNs> for u8 {
+    #[inline(always)]
+    fn from(val: Page13lock1lockNs) -> u8 {
+        Page13lock1lockNs::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page13lock1lockS {
+    #[doc = "Page is fully accessible by Secure software."]
+    READ_WRITE = 0,
+    #[doc = "Page can be read by Secure software, but can not be written."]
+    READ_ONLY = 0x01,
+    #[doc = "Do not use. Behaves the same as INACCESSIBLE."]
+    RESERVED = 0x02,
+    #[doc = "Page can not be accessed by Secure software."]
+    INACCESSIBLE = 0x03,
+}
+impl Page13lock1lockS {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page13lock1lockS {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page13lock1lockS {
+    #[inline(always)]
+    fn from(val: u8) -> Page13lock1lockS {
+        Page13lock1lockS::from_bits(val)
+    }
+}
+impl From<Page13lock1lockS> for u8 {
+    #[inline(always)]
+    fn from(val: Page13lock1lockS) -> u8 {
+        Page13lock1lockS::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page14lock0noKeyState {
+    READ_ONLY = 0,
+    INACCESSIBLE = 0x01,
+}
+impl Page14lock0noKeyState {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page14lock0noKeyState {
+        unsafe { core::mem::transmute(val & 0x01) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page14lock0noKeyState {
+    #[inline(always)]
+    fn from(val: u8) -> Page14lock0noKeyState {
+        Page14lock0noKeyState::from_bits(val)
+    }
+}
+impl From<Page14lock0noKeyState> for u8 {
+    #[inline(always)]
+    fn from(val: Page14lock0noKeyState) -> u8 {
+        Page14lock0noKeyState::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page14lock1lockBl {
+    #[doc = "Bootloader permits user reads and writes to this page"]
+    READ_WRITE = 0,
+    #[doc = "Bootloader permits user reads of this page"]
+    READ_ONLY = 0x01,
+    #[doc = "Do not use. Behaves the same as INACCESSIBLE"]
+    RESERVED = 0x02,
+    #[doc = "Bootloader does not permit user access to this page"]
+    INACCESSIBLE = 0x03,
+}
+impl Page14lock1lockBl {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page14lock1lockBl {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page14lock1lockBl {
+    #[inline(always)]
+    fn from(val: u8) -> Page14lock1lockBl {
+        Page14lock1lockBl::from_bits(val)
+    }
+}
+impl From<Page14lock1lockBl> for u8 {
+    #[inline(always)]
+    fn from(val: Page14lock1lockBl) -> u8 {
+        Page14lock1lockBl::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page14lock1lockNs {
+    #[doc = "Page can be read by Non-secure software, and Secure software may permit Non-secure writes."]
+    READ_WRITE = 0,
+    #[doc = "Page can be read by Non-secure software"]
+    READ_ONLY = 0x01,
+    #[doc = "Do not use. Behaves the same as INACCESSIBLE."]
+    RESERVED = 0x02,
+    #[doc = "Page can not be accessed by Non-secure software."]
+    INACCESSIBLE = 0x03,
+}
+impl Page14lock1lockNs {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page14lock1lockNs {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page14lock1lockNs {
+    #[inline(always)]
+    fn from(val: u8) -> Page14lock1lockNs {
+        Page14lock1lockNs::from_bits(val)
+    }
+}
+impl From<Page14lock1lockNs> for u8 {
+    #[inline(always)]
+    fn from(val: Page14lock1lockNs) -> u8 {
+        Page14lock1lockNs::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page14lock1lockS {
+    #[doc = "Page is fully accessible by Secure software."]
+    READ_WRITE = 0,
+    #[doc = "Page can be read by Secure software, but can not be written."]
+    READ_ONLY = 0x01,
+    #[doc = "Do not use. Behaves the same as INACCESSIBLE."]
+    RESERVED = 0x02,
+    #[doc = "Page can not be accessed by Secure software."]
+    INACCESSIBLE = 0x03,
+}
+impl Page14lock1lockS {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page14lock1lockS {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page14lock1lockS {
+    #[inline(always)]
+    fn from(val: u8) -> Page14lock1lockS {
+        Page14lock1lockS::from_bits(val)
+    }
+}
+impl From<Page14lock1lockS> for u8 {
+    #[inline(always)]
+    fn from(val: Page14lock1lockS) -> u8 {
+        Page14lock1lockS::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page15lock0noKeyState {
+    READ_ONLY = 0,
+    INACCESSIBLE = 0x01,
+}
+impl Page15lock0noKeyState {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page15lock0noKeyState {
+        unsafe { core::mem::transmute(val & 0x01) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page15lock0noKeyState {
+    #[inline(always)]
+    fn from(val: u8) -> Page15lock0noKeyState {
+        Page15lock0noKeyState::from_bits(val)
+    }
+}
+impl From<Page15lock0noKeyState> for u8 {
+    #[inline(always)]
+    fn from(val: Page15lock0noKeyState) -> u8 {
+        Page15lock0noKeyState::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page15lock1lockBl {
+    #[doc = "Bootloader permits user reads and writes to this page"]
+    READ_WRITE = 0,
+    #[doc = "Bootloader permits user reads of this page"]
+    READ_ONLY = 0x01,
+    #[doc = "Do not use. Behaves the same as INACCESSIBLE"]
+    RESERVED = 0x02,
+    #[doc = "Bootloader does not permit user access to this page"]
+    INACCESSIBLE = 0x03,
+}
+impl Page15lock1lockBl {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page15lock1lockBl {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page15lock1lockBl {
+    #[inline(always)]
+    fn from(val: u8) -> Page15lock1lockBl {
+        Page15lock1lockBl::from_bits(val)
+    }
+}
+impl From<Page15lock1lockBl> for u8 {
+    #[inline(always)]
+    fn from(val: Page15lock1lockBl) -> u8 {
+        Page15lock1lockBl::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page15lock1lockNs {
+    #[doc = "Page can be read by Non-secure software, and Secure software may permit Non-secure writes."]
+    READ_WRITE = 0,
+    #[doc = "Page can be read by Non-secure software"]
+    READ_ONLY = 0x01,
+    #[doc = "Do not use. Behaves the same as INACCESSIBLE."]
+    RESERVED = 0x02,
+    #[doc = "Page can not be accessed by Non-secure software."]
+    INACCESSIBLE = 0x03,
+}
+impl Page15lock1lockNs {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page15lock1lockNs {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page15lock1lockNs {
+    #[inline(always)]
+    fn from(val: u8) -> Page15lock1lockNs {
+        Page15lock1lockNs::from_bits(val)
+    }
+}
+impl From<Page15lock1lockNs> for u8 {
+    #[inline(always)]
+    fn from(val: Page15lock1lockNs) -> u8 {
+        Page15lock1lockNs::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page15lock1lockS {
+    #[doc = "Page is fully accessible by Secure software."]
+    READ_WRITE = 0,
+    #[doc = "Page can be read by Secure software, but can not be written."]
+    READ_ONLY = 0x01,
+    #[doc = "Do not use. Behaves the same as INACCESSIBLE."]
+    RESERVED = 0x02,
+    #[doc = "Page can not be accessed by Secure software."]
+    INACCESSIBLE = 0x03,
+}
+impl Page15lock1lockS {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page15lock1lockS {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page15lock1lockS {
+    #[inline(always)]
+    fn from(val: u8) -> Page15lock1lockS {
+        Page15lock1lockS::from_bits(val)
+    }
+}
+impl From<Page15lock1lockS> for u8 {
+    #[inline(always)]
+    fn from(val: Page15lock1lockS) -> u8 {
+        Page15lock1lockS::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page16lock0noKeyState {
+    READ_ONLY = 0,
+    INACCESSIBLE = 0x01,
+}
+impl Page16lock0noKeyState {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page16lock0noKeyState {
+        unsafe { core::mem::transmute(val & 0x01) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page16lock0noKeyState {
+    #[inline(always)]
+    fn from(val: u8) -> Page16lock0noKeyState {
+        Page16lock0noKeyState::from_bits(val)
+    }
+}
+impl From<Page16lock0noKeyState> for u8 {
+    #[inline(always)]
+    fn from(val: Page16lock0noKeyState) -> u8 {
+        Page16lock0noKeyState::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page16lock1lockBl {
+    #[doc = "Bootloader permits user reads and writes to this page"]
+    READ_WRITE = 0,
+    #[doc = "Bootloader permits user reads of this page"]
+    READ_ONLY = 0x01,
+    #[doc = "Do not use. Behaves the same as INACCESSIBLE"]
+    RESERVED = 0x02,
+    #[doc = "Bootloader does not permit user access to this page"]
+    INACCESSIBLE = 0x03,
+}
+impl Page16lock1lockBl {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page16lock1lockBl {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page16lock1lockBl {
+    #[inline(always)]
+    fn from(val: u8) -> Page16lock1lockBl {
+        Page16lock1lockBl::from_bits(val)
+    }
+}
+impl From<Page16lock1lockBl> for u8 {
+    #[inline(always)]
+    fn from(val: Page16lock1lockBl) -> u8 {
+        Page16lock1lockBl::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page16lock1lockNs {
+    #[doc = "Page can be read by Non-secure software, and Secure software may permit Non-secure writes."]
+    READ_WRITE = 0,
+    #[doc = "Page can be read by Non-secure software"]
+    READ_ONLY = 0x01,
+    #[doc = "Do not use. Behaves the same as INACCESSIBLE."]
+    RESERVED = 0x02,
+    #[doc = "Page can not be accessed by Non-secure software."]
+    INACCESSIBLE = 0x03,
+}
+impl Page16lock1lockNs {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page16lock1lockNs {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page16lock1lockNs {
+    #[inline(always)]
+    fn from(val: u8) -> Page16lock1lockNs {
+        Page16lock1lockNs::from_bits(val)
+    }
+}
+impl From<Page16lock1lockNs> for u8 {
+    #[inline(always)]
+    fn from(val: Page16lock1lockNs) -> u8 {
+        Page16lock1lockNs::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page16lock1lockS {
+    #[doc = "Page is fully accessible by Secure software."]
+    READ_WRITE = 0,
+    #[doc = "Page can be read by Secure software, but can not be written."]
+    READ_ONLY = 0x01,
+    #[doc = "Do not use. Behaves the same as INACCESSIBLE."]
+    RESERVED = 0x02,
+    #[doc = "Page can not be accessed by Secure software."]
+    INACCESSIBLE = 0x03,
+}
+impl Page16lock1lockS {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page16lock1lockS {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page16lock1lockS {
+    #[inline(always)]
+    fn from(val: u8) -> Page16lock1lockS {
+        Page16lock1lockS::from_bits(val)
+    }
+}
+impl From<Page16lock1lockS> for u8 {
+    #[inline(always)]
+    fn from(val: Page16lock1lockS) -> u8 {
+        Page16lock1lockS::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page17lock0noKeyState {
+    READ_ONLY = 0,
+    INACCESSIBLE = 0x01,
+}
+impl Page17lock0noKeyState {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page17lock0noKeyState {
+        unsafe { core::mem::transmute(val & 0x01) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page17lock0noKeyState {
+    #[inline(always)]
+    fn from(val: u8) -> Page17lock0noKeyState {
+        Page17lock0noKeyState::from_bits(val)
+    }
+}
+impl From<Page17lock0noKeyState> for u8 {
+    #[inline(always)]
+    fn from(val: Page17lock0noKeyState) -> u8 {
+        Page17lock0noKeyState::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page17lock1lockBl {
+    #[doc = "Bootloader permits user reads and writes to this page"]
+    READ_WRITE = 0,
+    #[doc = "Bootloader permits user reads of this page"]
+    READ_ONLY = 0x01,
+    #[doc = "Do not use. Behaves the same as INACCESSIBLE"]
+    RESERVED = 0x02,
+    #[doc = "Bootloader does not permit user access to this page"]
+    INACCESSIBLE = 0x03,
+}
+impl Page17lock1lockBl {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page17lock1lockBl {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page17lock1lockBl {
+    #[inline(always)]
+    fn from(val: u8) -> Page17lock1lockBl {
+        Page17lock1lockBl::from_bits(val)
+    }
+}
+impl From<Page17lock1lockBl> for u8 {
+    #[inline(always)]
+    fn from(val: Page17lock1lockBl) -> u8 {
+        Page17lock1lockBl::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page17lock1lockNs {
+    #[doc = "Page can be read by Non-secure software, and Secure software may permit Non-secure writes."]
+    READ_WRITE = 0,
+    #[doc = "Page can be read by Non-secure software"]
+    READ_ONLY = 0x01,
+    #[doc = "Do not use. Behaves the same as INACCESSIBLE."]
+    RESERVED = 0x02,
+    #[doc = "Page can not be accessed by Non-secure software."]
+    INACCESSIBLE = 0x03,
+}
+impl Page17lock1lockNs {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page17lock1lockNs {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page17lock1lockNs {
+    #[inline(always)]
+    fn from(val: u8) -> Page17lock1lockNs {
+        Page17lock1lockNs::from_bits(val)
+    }
+}
+impl From<Page17lock1lockNs> for u8 {
+    #[inline(always)]
+    fn from(val: Page17lock1lockNs) -> u8 {
+        Page17lock1lockNs::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page17lock1lockS {
+    #[doc = "Page is fully accessible by Secure software."]
+    READ_WRITE = 0,
+    #[doc = "Page can be read by Secure software, but can not be written."]
+    READ_ONLY = 0x01,
+    #[doc = "Do not use. Behaves the same as INACCESSIBLE."]
+    RESERVED = 0x02,
+    #[doc = "Page can not be accessed by Secure software."]
+    INACCESSIBLE = 0x03,
+}
+impl Page17lock1lockS {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page17lock1lockS {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page17lock1lockS {
+    #[inline(always)]
+    fn from(val: u8) -> Page17lock1lockS {
+        Page17lock1lockS::from_bits(val)
+    }
+}
+impl From<Page17lock1lockS> for u8 {
+    #[inline(always)]
+    fn from(val: Page17lock1lockS) -> u8 {
+        Page17lock1lockS::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page18lock0noKeyState {
+    READ_ONLY = 0,
+    INACCESSIBLE = 0x01,
+}
+impl Page18lock0noKeyState {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page18lock0noKeyState {
+        unsafe { core::mem::transmute(val & 0x01) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page18lock0noKeyState {
+    #[inline(always)]
+    fn from(val: u8) -> Page18lock0noKeyState {
+        Page18lock0noKeyState::from_bits(val)
+    }
+}
+impl From<Page18lock0noKeyState> for u8 {
+    #[inline(always)]
+    fn from(val: Page18lock0noKeyState) -> u8 {
+        Page18lock0noKeyState::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page18lock1lockBl {
+    #[doc = "Bootloader permits user reads and writes to this page"]
+    READ_WRITE = 0,
+    #[doc = "Bootloader permits user reads of this page"]
+    READ_ONLY = 0x01,
+    #[doc = "Do not use. Behaves the same as INACCESSIBLE"]
+    RESERVED = 0x02,
+    #[doc = "Bootloader does not permit user access to this page"]
+    INACCESSIBLE = 0x03,
+}
+impl Page18lock1lockBl {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page18lock1lockBl {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page18lock1lockBl {
+    #[inline(always)]
+    fn from(val: u8) -> Page18lock1lockBl {
+        Page18lock1lockBl::from_bits(val)
+    }
+}
+impl From<Page18lock1lockBl> for u8 {
+    #[inline(always)]
+    fn from(val: Page18lock1lockBl) -> u8 {
+        Page18lock1lockBl::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page18lock1lockNs {
+    #[doc = "Page can be read by Non-secure software, and Secure software may permit Non-secure writes."]
+    READ_WRITE = 0,
+    #[doc = "Page can be read by Non-secure software"]
+    READ_ONLY = 0x01,
+    #[doc = "Do not use. Behaves the same as INACCESSIBLE."]
+    RESERVED = 0x02,
+    #[doc = "Page can not be accessed by Non-secure software."]
+    INACCESSIBLE = 0x03,
+}
+impl Page18lock1lockNs {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page18lock1lockNs {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page18lock1lockNs {
+    #[inline(always)]
+    fn from(val: u8) -> Page18lock1lockNs {
+        Page18lock1lockNs::from_bits(val)
+    }
+}
+impl From<Page18lock1lockNs> for u8 {
+    #[inline(always)]
+    fn from(val: Page18lock1lockNs) -> u8 {
+        Page18lock1lockNs::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page18lock1lockS {
+    #[doc = "Page is fully accessible by Secure software."]
+    READ_WRITE = 0,
+    #[doc = "Page can be read by Secure software, but can not be written."]
+    READ_ONLY = 0x01,
+    #[doc = "Do not use. Behaves the same as INACCESSIBLE."]
+    RESERVED = 0x02,
+    #[doc = "Page can not be accessed by Secure software."]
+    INACCESSIBLE = 0x03,
+}
+impl Page18lock1lockS {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page18lock1lockS {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page18lock1lockS {
+    #[inline(always)]
+    fn from(val: u8) -> Page18lock1lockS {
+        Page18lock1lockS::from_bits(val)
+    }
+}
+impl From<Page18lock1lockS> for u8 {
+    #[inline(always)]
+    fn from(val: Page18lock1lockS) -> u8 {
+        Page18lock1lockS::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page19lock0noKeyState {
+    READ_ONLY = 0,
+    INACCESSIBLE = 0x01,
+}
+impl Page19lock0noKeyState {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page19lock0noKeyState {
+        unsafe { core::mem::transmute(val & 0x01) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page19lock0noKeyState {
+    #[inline(always)]
+    fn from(val: u8) -> Page19lock0noKeyState {
+        Page19lock0noKeyState::from_bits(val)
+    }
+}
+impl From<Page19lock0noKeyState> for u8 {
+    #[inline(always)]
+    fn from(val: Page19lock0noKeyState) -> u8 {
+        Page19lock0noKeyState::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page19lock1lockBl {
+    #[doc = "Bootloader permits user reads and writes to this page"]
+    READ_WRITE = 0,
+    #[doc = "Bootloader permits user reads of this page"]
+    READ_ONLY = 0x01,
+    #[doc = "Do not use. Behaves the same as INACCESSIBLE"]
+    RESERVED = 0x02,
+    #[doc = "Bootloader does not permit user access to this page"]
+    INACCESSIBLE = 0x03,
+}
+impl Page19lock1lockBl {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page19lock1lockBl {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page19lock1lockBl {
+    #[inline(always)]
+    fn from(val: u8) -> Page19lock1lockBl {
+        Page19lock1lockBl::from_bits(val)
+    }
+}
+impl From<Page19lock1lockBl> for u8 {
+    #[inline(always)]
+    fn from(val: Page19lock1lockBl) -> u8 {
+        Page19lock1lockBl::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page19lock1lockNs {
+    #[doc = "Page can be read by Non-secure software, and Secure software may permit Non-secure writes."]
+    READ_WRITE = 0,
+    #[doc = "Page can be read by Non-secure software"]
+    READ_ONLY = 0x01,
+    #[doc = "Do not use. Behaves the same as INACCESSIBLE."]
+    RESERVED = 0x02,
+    #[doc = "Page can not be accessed by Non-secure software."]
+    INACCESSIBLE = 0x03,
+}
+impl Page19lock1lockNs {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page19lock1lockNs {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page19lock1lockNs {
+    #[inline(always)]
+    fn from(val: u8) -> Page19lock1lockNs {
+        Page19lock1lockNs::from_bits(val)
+    }
+}
+impl From<Page19lock1lockNs> for u8 {
+    #[inline(always)]
+    fn from(val: Page19lock1lockNs) -> u8 {
+        Page19lock1lockNs::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page19lock1lockS {
+    #[doc = "Page is fully accessible by Secure software."]
+    READ_WRITE = 0,
+    #[doc = "Page can be read by Secure software, but can not be written."]
+    READ_ONLY = 0x01,
+    #[doc = "Do not use. Behaves the same as INACCESSIBLE."]
+    RESERVED = 0x02,
+    #[doc = "Page can not be accessed by Secure software."]
+    INACCESSIBLE = 0x03,
+}
+impl Page19lock1lockS {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page19lock1lockS {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page19lock1lockS {
+    #[inline(always)]
+    fn from(val: u8) -> Page19lock1lockS {
+        Page19lock1lockS::from_bits(val)
+    }
+}
+impl From<Page19lock1lockS> for u8 {
+    #[inline(always)]
+    fn from(val: Page19lock1lockS) -> u8 {
+        Page19lock1lockS::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page1lock0noKeyState {
+    READ_ONLY = 0,
+    INACCESSIBLE = 0x01,
+}
+impl Page1lock0noKeyState {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page1lock0noKeyState {
+        unsafe { core::mem::transmute(val & 0x01) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page1lock0noKeyState {
+    #[inline(always)]
+    fn from(val: u8) -> Page1lock0noKeyState {
+        Page1lock0noKeyState::from_bits(val)
+    }
+}
+impl From<Page1lock0noKeyState> for u8 {
+    #[inline(always)]
+    fn from(val: Page1lock0noKeyState) -> u8 {
+        Page1lock0noKeyState::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page1lock1lockBl {
+    #[doc = "Bootloader permits user reads and writes to this page"]
+    READ_WRITE = 0,
+    #[doc = "Bootloader permits user reads of this page"]
+    READ_ONLY = 0x01,
+    #[doc = "Do not use. Behaves the same as INACCESSIBLE"]
+    RESERVED = 0x02,
+    #[doc = "Bootloader does not permit user access to this page"]
+    INACCESSIBLE = 0x03,
+}
+impl Page1lock1lockBl {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page1lock1lockBl {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page1lock1lockBl {
+    #[inline(always)]
+    fn from(val: u8) -> Page1lock1lockBl {
+        Page1lock1lockBl::from_bits(val)
+    }
+}
+impl From<Page1lock1lockBl> for u8 {
+    #[inline(always)]
+    fn from(val: Page1lock1lockBl) -> u8 {
+        Page1lock1lockBl::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page1lock1lockNs {
+    #[doc = "Page can be read by Non-secure software, and Secure software may permit Non-secure writes."]
+    READ_WRITE = 0,
+    #[doc = "Page can be read by Non-secure software"]
+    READ_ONLY = 0x01,
+    #[doc = "Do not use. Behaves the same as INACCESSIBLE."]
+    RESERVED = 0x02,
+    #[doc = "Page can not be accessed by Non-secure software."]
+    INACCESSIBLE = 0x03,
+}
+impl Page1lock1lockNs {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page1lock1lockNs {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page1lock1lockNs {
+    #[inline(always)]
+    fn from(val: u8) -> Page1lock1lockNs {
+        Page1lock1lockNs::from_bits(val)
+    }
+}
+impl From<Page1lock1lockNs> for u8 {
+    #[inline(always)]
+    fn from(val: Page1lock1lockNs) -> u8 {
+        Page1lock1lockNs::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page1lock1lockS {
+    #[doc = "Page is fully accessible by Secure software."]
+    READ_WRITE = 0,
+    #[doc = "Page can be read by Secure software, but can not be written."]
+    READ_ONLY = 0x01,
+    #[doc = "Do not use. Behaves the same as INACCESSIBLE."]
+    RESERVED = 0x02,
+    #[doc = "Page can not be accessed by Secure software."]
+    INACCESSIBLE = 0x03,
+}
+impl Page1lock1lockS {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page1lock1lockS {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page1lock1lockS {
+    #[inline(always)]
+    fn from(val: u8) -> Page1lock1lockS {
+        Page1lock1lockS::from_bits(val)
+    }
+}
+impl From<Page1lock1lockS> for u8 {
+    #[inline(always)]
+    fn from(val: Page1lock1lockS) -> u8 {
+        Page1lock1lockS::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page20lock0noKeyState {
+    READ_ONLY = 0,
+    INACCESSIBLE = 0x01,
+}
+impl Page20lock0noKeyState {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page20lock0noKeyState {
+        unsafe { core::mem::transmute(val & 0x01) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page20lock0noKeyState {
+    #[inline(always)]
+    fn from(val: u8) -> Page20lock0noKeyState {
+        Page20lock0noKeyState::from_bits(val)
+    }
+}
+impl From<Page20lock0noKeyState> for u8 {
+    #[inline(always)]
+    fn from(val: Page20lock0noKeyState) -> u8 {
+        Page20lock0noKeyState::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page20lock1lockBl {
+    #[doc = "Bootloader permits user reads and writes to this page"]
+    READ_WRITE = 0,
+    #[doc = "Bootloader permits user reads of this page"]
+    READ_ONLY = 0x01,
+    #[doc = "Do not use. Behaves the same as INACCESSIBLE"]
+    RESERVED = 0x02,
+    #[doc = "Bootloader does not permit user access to this page"]
+    INACCESSIBLE = 0x03,
+}
+impl Page20lock1lockBl {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page20lock1lockBl {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page20lock1lockBl {
+    #[inline(always)]
+    fn from(val: u8) -> Page20lock1lockBl {
+        Page20lock1lockBl::from_bits(val)
+    }
+}
+impl From<Page20lock1lockBl> for u8 {
+    #[inline(always)]
+    fn from(val: Page20lock1lockBl) -> u8 {
+        Page20lock1lockBl::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page20lock1lockNs {
+    #[doc = "Page can be read by Non-secure software, and Secure software may permit Non-secure writes."]
+    READ_WRITE = 0,
+    #[doc = "Page can be read by Non-secure software"]
+    READ_ONLY = 0x01,
+    #[doc = "Do not use. Behaves the same as INACCESSIBLE."]
+    RESERVED = 0x02,
+    #[doc = "Page can not be accessed by Non-secure software."]
+    INACCESSIBLE = 0x03,
+}
+impl Page20lock1lockNs {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page20lock1lockNs {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page20lock1lockNs {
+    #[inline(always)]
+    fn from(val: u8) -> Page20lock1lockNs {
+        Page20lock1lockNs::from_bits(val)
+    }
+}
+impl From<Page20lock1lockNs> for u8 {
+    #[inline(always)]
+    fn from(val: Page20lock1lockNs) -> u8 {
+        Page20lock1lockNs::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page20lock1lockS {
+    #[doc = "Page is fully accessible by Secure software."]
+    READ_WRITE = 0,
+    #[doc = "Page can be read by Secure software, but can not be written."]
+    READ_ONLY = 0x01,
+    #[doc = "Do not use. Behaves the same as INACCESSIBLE."]
+    RESERVED = 0x02,
+    #[doc = "Page can not be accessed by Secure software."]
+    INACCESSIBLE = 0x03,
+}
+impl Page20lock1lockS {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page20lock1lockS {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page20lock1lockS {
+    #[inline(always)]
+    fn from(val: u8) -> Page20lock1lockS {
+        Page20lock1lockS::from_bits(val)
+    }
+}
+impl From<Page20lock1lockS> for u8 {
+    #[inline(always)]
+    fn from(val: Page20lock1lockS) -> u8 {
+        Page20lock1lockS::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page21lock0noKeyState {
+    READ_ONLY = 0,
+    INACCESSIBLE = 0x01,
+}
+impl Page21lock0noKeyState {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page21lock0noKeyState {
+        unsafe { core::mem::transmute(val & 0x01) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page21lock0noKeyState {
+    #[inline(always)]
+    fn from(val: u8) -> Page21lock0noKeyState {
+        Page21lock0noKeyState::from_bits(val)
+    }
+}
+impl From<Page21lock0noKeyState> for u8 {
+    #[inline(always)]
+    fn from(val: Page21lock0noKeyState) -> u8 {
+        Page21lock0noKeyState::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page21lock1lockBl {
+    #[doc = "Bootloader permits user reads and writes to this page"]
+    READ_WRITE = 0,
+    #[doc = "Bootloader permits user reads of this page"]
+    READ_ONLY = 0x01,
+    #[doc = "Do not use. Behaves the same as INACCESSIBLE"]
+    RESERVED = 0x02,
+    #[doc = "Bootloader does not permit user access to this page"]
+    INACCESSIBLE = 0x03,
+}
+impl Page21lock1lockBl {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page21lock1lockBl {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page21lock1lockBl {
+    #[inline(always)]
+    fn from(val: u8) -> Page21lock1lockBl {
+        Page21lock1lockBl::from_bits(val)
+    }
+}
+impl From<Page21lock1lockBl> for u8 {
+    #[inline(always)]
+    fn from(val: Page21lock1lockBl) -> u8 {
+        Page21lock1lockBl::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page21lock1lockNs {
+    #[doc = "Page can be read by Non-secure software, and Secure software may permit Non-secure writes."]
+    READ_WRITE = 0,
+    #[doc = "Page can be read by Non-secure software"]
+    READ_ONLY = 0x01,
+    #[doc = "Do not use. Behaves the same as INACCESSIBLE."]
+    RESERVED = 0x02,
+    #[doc = "Page can not be accessed by Non-secure software."]
+    INACCESSIBLE = 0x03,
+}
+impl Page21lock1lockNs {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page21lock1lockNs {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page21lock1lockNs {
+    #[inline(always)]
+    fn from(val: u8) -> Page21lock1lockNs {
+        Page21lock1lockNs::from_bits(val)
+    }
+}
+impl From<Page21lock1lockNs> for u8 {
+    #[inline(always)]
+    fn from(val: Page21lock1lockNs) -> u8 {
+        Page21lock1lockNs::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page21lock1lockS {
+    #[doc = "Page is fully accessible by Secure software."]
+    READ_WRITE = 0,
+    #[doc = "Page can be read by Secure software, but can not be written."]
+    READ_ONLY = 0x01,
+    #[doc = "Do not use. Behaves the same as INACCESSIBLE."]
+    RESERVED = 0x02,
+    #[doc = "Page can not be accessed by Secure software."]
+    INACCESSIBLE = 0x03,
+}
+impl Page21lock1lockS {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page21lock1lockS {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page21lock1lockS {
+    #[inline(always)]
+    fn from(val: u8) -> Page21lock1lockS {
+        Page21lock1lockS::from_bits(val)
+    }
+}
+impl From<Page21lock1lockS> for u8 {
+    #[inline(always)]
+    fn from(val: Page21lock1lockS) -> u8 {
+        Page21lock1lockS::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page22lock0noKeyState {
+    READ_ONLY = 0,
+    INACCESSIBLE = 0x01,
+}
+impl Page22lock0noKeyState {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page22lock0noKeyState {
+        unsafe { core::mem::transmute(val & 0x01) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page22lock0noKeyState {
+    #[inline(always)]
+    fn from(val: u8) -> Page22lock0noKeyState {
+        Page22lock0noKeyState::from_bits(val)
+    }
+}
+impl From<Page22lock0noKeyState> for u8 {
+    #[inline(always)]
+    fn from(val: Page22lock0noKeyState) -> u8 {
+        Page22lock0noKeyState::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page22lock1lockBl {
+    #[doc = "Bootloader permits user reads and writes to this page"]
+    READ_WRITE = 0,
+    #[doc = "Bootloader permits user reads of this page"]
+    READ_ONLY = 0x01,
+    #[doc = "Do not use. Behaves the same as INACCESSIBLE"]
+    RESERVED = 0x02,
+    #[doc = "Bootloader does not permit user access to this page"]
+    INACCESSIBLE = 0x03,
+}
+impl Page22lock1lockBl {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page22lock1lockBl {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page22lock1lockBl {
+    #[inline(always)]
+    fn from(val: u8) -> Page22lock1lockBl {
+        Page22lock1lockBl::from_bits(val)
+    }
+}
+impl From<Page22lock1lockBl> for u8 {
+    #[inline(always)]
+    fn from(val: Page22lock1lockBl) -> u8 {
+        Page22lock1lockBl::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page22lock1lockNs {
+    #[doc = "Page can be read by Non-secure software, and Secure software may permit Non-secure writes."]
+    READ_WRITE = 0,
+    #[doc = "Page can be read by Non-secure software"]
+    READ_ONLY = 0x01,
+    #[doc = "Do not use. Behaves the same as INACCESSIBLE."]
+    RESERVED = 0x02,
+    #[doc = "Page can not be accessed by Non-secure software."]
+    INACCESSIBLE = 0x03,
+}
+impl Page22lock1lockNs {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page22lock1lockNs {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page22lock1lockNs {
+    #[inline(always)]
+    fn from(val: u8) -> Page22lock1lockNs {
+        Page22lock1lockNs::from_bits(val)
+    }
+}
+impl From<Page22lock1lockNs> for u8 {
+    #[inline(always)]
+    fn from(val: Page22lock1lockNs) -> u8 {
+        Page22lock1lockNs::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page22lock1lockS {
+    #[doc = "Page is fully accessible by Secure software."]
+    READ_WRITE = 0,
+    #[doc = "Page can be read by Secure software, but can not be written."]
+    READ_ONLY = 0x01,
+    #[doc = "Do not use. Behaves the same as INACCESSIBLE."]
+    RESERVED = 0x02,
+    #[doc = "Page can not be accessed by Secure software."]
+    INACCESSIBLE = 0x03,
+}
+impl Page22lock1lockS {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page22lock1lockS {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page22lock1lockS {
+    #[inline(always)]
+    fn from(val: u8) -> Page22lock1lockS {
+        Page22lock1lockS::from_bits(val)
+    }
+}
+impl From<Page22lock1lockS> for u8 {
+    #[inline(always)]
+    fn from(val: Page22lock1lockS) -> u8 {
+        Page22lock1lockS::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page23lock0noKeyState {
+    READ_ONLY = 0,
+    INACCESSIBLE = 0x01,
+}
+impl Page23lock0noKeyState {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page23lock0noKeyState {
+        unsafe { core::mem::transmute(val & 0x01) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page23lock0noKeyState {
+    #[inline(always)]
+    fn from(val: u8) -> Page23lock0noKeyState {
+        Page23lock0noKeyState::from_bits(val)
+    }
+}
+impl From<Page23lock0noKeyState> for u8 {
+    #[inline(always)]
+    fn from(val: Page23lock0noKeyState) -> u8 {
+        Page23lock0noKeyState::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page23lock1lockBl {
+    #[doc = "Bootloader permits user reads and writes to this page"]
+    READ_WRITE = 0,
+    #[doc = "Bootloader permits user reads of this page"]
+    READ_ONLY = 0x01,
+    #[doc = "Do not use. Behaves the same as INACCESSIBLE"]
+    RESERVED = 0x02,
+    #[doc = "Bootloader does not permit user access to this page"]
+    INACCESSIBLE = 0x03,
+}
+impl Page23lock1lockBl {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page23lock1lockBl {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page23lock1lockBl {
+    #[inline(always)]
+    fn from(val: u8) -> Page23lock1lockBl {
+        Page23lock1lockBl::from_bits(val)
+    }
+}
+impl From<Page23lock1lockBl> for u8 {
+    #[inline(always)]
+    fn from(val: Page23lock1lockBl) -> u8 {
+        Page23lock1lockBl::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page23lock1lockNs {
+    #[doc = "Page can be read by Non-secure software, and Secure software may permit Non-secure writes."]
+    READ_WRITE = 0,
+    #[doc = "Page can be read by Non-secure software"]
+    READ_ONLY = 0x01,
+    #[doc = "Do not use. Behaves the same as INACCESSIBLE."]
+    RESERVED = 0x02,
+    #[doc = "Page can not be accessed by Non-secure software."]
+    INACCESSIBLE = 0x03,
+}
+impl Page23lock1lockNs {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page23lock1lockNs {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page23lock1lockNs {
+    #[inline(always)]
+    fn from(val: u8) -> Page23lock1lockNs {
+        Page23lock1lockNs::from_bits(val)
+    }
+}
+impl From<Page23lock1lockNs> for u8 {
+    #[inline(always)]
+    fn from(val: Page23lock1lockNs) -> u8 {
+        Page23lock1lockNs::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page23lock1lockS {
+    #[doc = "Page is fully accessible by Secure software."]
+    READ_WRITE = 0,
+    #[doc = "Page can be read by Secure software, but can not be written."]
+    READ_ONLY = 0x01,
+    #[doc = "Do not use. Behaves the same as INACCESSIBLE."]
+    RESERVED = 0x02,
+    #[doc = "Page can not be accessed by Secure software."]
+    INACCESSIBLE = 0x03,
+}
+impl Page23lock1lockS {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page23lock1lockS {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page23lock1lockS {
+    #[inline(always)]
+    fn from(val: u8) -> Page23lock1lockS {
+        Page23lock1lockS::from_bits(val)
+    }
+}
+impl From<Page23lock1lockS> for u8 {
+    #[inline(always)]
+    fn from(val: Page23lock1lockS) -> u8 {
+        Page23lock1lockS::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page24lock0noKeyState {
+    READ_ONLY = 0,
+    INACCESSIBLE = 0x01,
+}
+impl Page24lock0noKeyState {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page24lock0noKeyState {
+        unsafe { core::mem::transmute(val & 0x01) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page24lock0noKeyState {
+    #[inline(always)]
+    fn from(val: u8) -> Page24lock0noKeyState {
+        Page24lock0noKeyState::from_bits(val)
+    }
+}
+impl From<Page24lock0noKeyState> for u8 {
+    #[inline(always)]
+    fn from(val: Page24lock0noKeyState) -> u8 {
+        Page24lock0noKeyState::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page24lock1lockBl {
+    #[doc = "Bootloader permits user reads and writes to this page"]
+    READ_WRITE = 0,
+    #[doc = "Bootloader permits user reads of this page"]
+    READ_ONLY = 0x01,
+    #[doc = "Do not use. Behaves the same as INACCESSIBLE"]
+    RESERVED = 0x02,
+    #[doc = "Bootloader does not permit user access to this page"]
+    INACCESSIBLE = 0x03,
+}
+impl Page24lock1lockBl {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page24lock1lockBl {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page24lock1lockBl {
+    #[inline(always)]
+    fn from(val: u8) -> Page24lock1lockBl {
+        Page24lock1lockBl::from_bits(val)
+    }
+}
+impl From<Page24lock1lockBl> for u8 {
+    #[inline(always)]
+    fn from(val: Page24lock1lockBl) -> u8 {
+        Page24lock1lockBl::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page24lock1lockNs {
+    #[doc = "Page can be read by Non-secure software, and Secure software may permit Non-secure writes."]
+    READ_WRITE = 0,
+    #[doc = "Page can be read by Non-secure software"]
+    READ_ONLY = 0x01,
+    #[doc = "Do not use. Behaves the same as INACCESSIBLE."]
+    RESERVED = 0x02,
+    #[doc = "Page can not be accessed by Non-secure software."]
+    INACCESSIBLE = 0x03,
+}
+impl Page24lock1lockNs {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page24lock1lockNs {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page24lock1lockNs {
+    #[inline(always)]
+    fn from(val: u8) -> Page24lock1lockNs {
+        Page24lock1lockNs::from_bits(val)
+    }
+}
+impl From<Page24lock1lockNs> for u8 {
+    #[inline(always)]
+    fn from(val: Page24lock1lockNs) -> u8 {
+        Page24lock1lockNs::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page24lock1lockS {
+    #[doc = "Page is fully accessible by Secure software."]
+    READ_WRITE = 0,
+    #[doc = "Page can be read by Secure software, but can not be written."]
+    READ_ONLY = 0x01,
+    #[doc = "Do not use. Behaves the same as INACCESSIBLE."]
+    RESERVED = 0x02,
+    #[doc = "Page can not be accessed by Secure software."]
+    INACCESSIBLE = 0x03,
+}
+impl Page24lock1lockS {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page24lock1lockS {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page24lock1lockS {
+    #[inline(always)]
+    fn from(val: u8) -> Page24lock1lockS {
+        Page24lock1lockS::from_bits(val)
+    }
+}
+impl From<Page24lock1lockS> for u8 {
+    #[inline(always)]
+    fn from(val: Page24lock1lockS) -> u8 {
+        Page24lock1lockS::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page25lock0noKeyState {
+    READ_ONLY = 0,
+    INACCESSIBLE = 0x01,
+}
+impl Page25lock0noKeyState {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page25lock0noKeyState {
+        unsafe { core::mem::transmute(val & 0x01) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page25lock0noKeyState {
+    #[inline(always)]
+    fn from(val: u8) -> Page25lock0noKeyState {
+        Page25lock0noKeyState::from_bits(val)
+    }
+}
+impl From<Page25lock0noKeyState> for u8 {
+    #[inline(always)]
+    fn from(val: Page25lock0noKeyState) -> u8 {
+        Page25lock0noKeyState::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page25lock1lockBl {
+    #[doc = "Bootloader permits user reads and writes to this page"]
+    READ_WRITE = 0,
+    #[doc = "Bootloader permits user reads of this page"]
+    READ_ONLY = 0x01,
+    #[doc = "Do not use. Behaves the same as INACCESSIBLE"]
+    RESERVED = 0x02,
+    #[doc = "Bootloader does not permit user access to this page"]
+    INACCESSIBLE = 0x03,
+}
+impl Page25lock1lockBl {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page25lock1lockBl {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page25lock1lockBl {
+    #[inline(always)]
+    fn from(val: u8) -> Page25lock1lockBl {
+        Page25lock1lockBl::from_bits(val)
+    }
+}
+impl From<Page25lock1lockBl> for u8 {
+    #[inline(always)]
+    fn from(val: Page25lock1lockBl) -> u8 {
+        Page25lock1lockBl::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page25lock1lockNs {
+    #[doc = "Page can be read by Non-secure software, and Secure software may permit Non-secure writes."]
+    READ_WRITE = 0,
+    #[doc = "Page can be read by Non-secure software"]
+    READ_ONLY = 0x01,
+    #[doc = "Do not use. Behaves the same as INACCESSIBLE."]
+    RESERVED = 0x02,
+    #[doc = "Page can not be accessed by Non-secure software."]
+    INACCESSIBLE = 0x03,
+}
+impl Page25lock1lockNs {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page25lock1lockNs {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page25lock1lockNs {
+    #[inline(always)]
+    fn from(val: u8) -> Page25lock1lockNs {
+        Page25lock1lockNs::from_bits(val)
+    }
+}
+impl From<Page25lock1lockNs> for u8 {
+    #[inline(always)]
+    fn from(val: Page25lock1lockNs) -> u8 {
+        Page25lock1lockNs::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page25lock1lockS {
+    #[doc = "Page is fully accessible by Secure software."]
+    READ_WRITE = 0,
+    #[doc = "Page can be read by Secure software, but can not be written."]
+    READ_ONLY = 0x01,
+    #[doc = "Do not use. Behaves the same as INACCESSIBLE."]
+    RESERVED = 0x02,
+    #[doc = "Page can not be accessed by Secure software."]
+    INACCESSIBLE = 0x03,
+}
+impl Page25lock1lockS {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page25lock1lockS {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page25lock1lockS {
+    #[inline(always)]
+    fn from(val: u8) -> Page25lock1lockS {
+        Page25lock1lockS::from_bits(val)
+    }
+}
+impl From<Page25lock1lockS> for u8 {
+    #[inline(always)]
+    fn from(val: Page25lock1lockS) -> u8 {
+        Page25lock1lockS::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page26lock0noKeyState {
+    READ_ONLY = 0,
+    INACCESSIBLE = 0x01,
+}
+impl Page26lock0noKeyState {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page26lock0noKeyState {
+        unsafe { core::mem::transmute(val & 0x01) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page26lock0noKeyState {
+    #[inline(always)]
+    fn from(val: u8) -> Page26lock0noKeyState {
+        Page26lock0noKeyState::from_bits(val)
+    }
+}
+impl From<Page26lock0noKeyState> for u8 {
+    #[inline(always)]
+    fn from(val: Page26lock0noKeyState) -> u8 {
+        Page26lock0noKeyState::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page26lock1lockBl {
+    #[doc = "Bootloader permits user reads and writes to this page"]
+    READ_WRITE = 0,
+    #[doc = "Bootloader permits user reads of this page"]
+    READ_ONLY = 0x01,
+    #[doc = "Do not use. Behaves the same as INACCESSIBLE"]
+    RESERVED = 0x02,
+    #[doc = "Bootloader does not permit user access to this page"]
+    INACCESSIBLE = 0x03,
+}
+impl Page26lock1lockBl {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page26lock1lockBl {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page26lock1lockBl {
+    #[inline(always)]
+    fn from(val: u8) -> Page26lock1lockBl {
+        Page26lock1lockBl::from_bits(val)
+    }
+}
+impl From<Page26lock1lockBl> for u8 {
+    #[inline(always)]
+    fn from(val: Page26lock1lockBl) -> u8 {
+        Page26lock1lockBl::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page26lock1lockNs {
+    #[doc = "Page can be read by Non-secure software, and Secure software may permit Non-secure writes."]
+    READ_WRITE = 0,
+    #[doc = "Page can be read by Non-secure software"]
+    READ_ONLY = 0x01,
+    #[doc = "Do not use. Behaves the same as INACCESSIBLE."]
+    RESERVED = 0x02,
+    #[doc = "Page can not be accessed by Non-secure software."]
+    INACCESSIBLE = 0x03,
+}
+impl Page26lock1lockNs {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page26lock1lockNs {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page26lock1lockNs {
+    #[inline(always)]
+    fn from(val: u8) -> Page26lock1lockNs {
+        Page26lock1lockNs::from_bits(val)
+    }
+}
+impl From<Page26lock1lockNs> for u8 {
+    #[inline(always)]
+    fn from(val: Page26lock1lockNs) -> u8 {
+        Page26lock1lockNs::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page26lock1lockS {
+    #[doc = "Page is fully accessible by Secure software."]
+    READ_WRITE = 0,
+    #[doc = "Page can be read by Secure software, but can not be written."]
+    READ_ONLY = 0x01,
+    #[doc = "Do not use. Behaves the same as INACCESSIBLE."]
+    RESERVED = 0x02,
+    #[doc = "Page can not be accessed by Secure software."]
+    INACCESSIBLE = 0x03,
+}
+impl Page26lock1lockS {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page26lock1lockS {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page26lock1lockS {
+    #[inline(always)]
+    fn from(val: u8) -> Page26lock1lockS {
+        Page26lock1lockS::from_bits(val)
+    }
+}
+impl From<Page26lock1lockS> for u8 {
+    #[inline(always)]
+    fn from(val: Page26lock1lockS) -> u8 {
+        Page26lock1lockS::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page27lock0noKeyState {
+    READ_ONLY = 0,
+    INACCESSIBLE = 0x01,
+}
+impl Page27lock0noKeyState {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page27lock0noKeyState {
+        unsafe { core::mem::transmute(val & 0x01) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page27lock0noKeyState {
+    #[inline(always)]
+    fn from(val: u8) -> Page27lock0noKeyState {
+        Page27lock0noKeyState::from_bits(val)
+    }
+}
+impl From<Page27lock0noKeyState> for u8 {
+    #[inline(always)]
+    fn from(val: Page27lock0noKeyState) -> u8 {
+        Page27lock0noKeyState::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page27lock1lockBl {
+    #[doc = "Bootloader permits user reads and writes to this page"]
+    READ_WRITE = 0,
+    #[doc = "Bootloader permits user reads of this page"]
+    READ_ONLY = 0x01,
+    #[doc = "Do not use. Behaves the same as INACCESSIBLE"]
+    RESERVED = 0x02,
+    #[doc = "Bootloader does not permit user access to this page"]
+    INACCESSIBLE = 0x03,
+}
+impl Page27lock1lockBl {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page27lock1lockBl {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page27lock1lockBl {
+    #[inline(always)]
+    fn from(val: u8) -> Page27lock1lockBl {
+        Page27lock1lockBl::from_bits(val)
+    }
+}
+impl From<Page27lock1lockBl> for u8 {
+    #[inline(always)]
+    fn from(val: Page27lock1lockBl) -> u8 {
+        Page27lock1lockBl::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page27lock1lockNs {
+    #[doc = "Page can be read by Non-secure software, and Secure software may permit Non-secure writes."]
+    READ_WRITE = 0,
+    #[doc = "Page can be read by Non-secure software"]
+    READ_ONLY = 0x01,
+    #[doc = "Do not use. Behaves the same as INACCESSIBLE."]
+    RESERVED = 0x02,
+    #[doc = "Page can not be accessed by Non-secure software."]
+    INACCESSIBLE = 0x03,
+}
+impl Page27lock1lockNs {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page27lock1lockNs {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page27lock1lockNs {
+    #[inline(always)]
+    fn from(val: u8) -> Page27lock1lockNs {
+        Page27lock1lockNs::from_bits(val)
+    }
+}
+impl From<Page27lock1lockNs> for u8 {
+    #[inline(always)]
+    fn from(val: Page27lock1lockNs) -> u8 {
+        Page27lock1lockNs::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page27lock1lockS {
+    #[doc = "Page is fully accessible by Secure software."]
+    READ_WRITE = 0,
+    #[doc = "Page can be read by Secure software, but can not be written."]
+    READ_ONLY = 0x01,
+    #[doc = "Do not use. Behaves the same as INACCESSIBLE."]
+    RESERVED = 0x02,
+    #[doc = "Page can not be accessed by Secure software."]
+    INACCESSIBLE = 0x03,
+}
+impl Page27lock1lockS {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page27lock1lockS {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page27lock1lockS {
+    #[inline(always)]
+    fn from(val: u8) -> Page27lock1lockS {
+        Page27lock1lockS::from_bits(val)
+    }
+}
+impl From<Page27lock1lockS> for u8 {
+    #[inline(always)]
+    fn from(val: Page27lock1lockS) -> u8 {
+        Page27lock1lockS::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page28lock0noKeyState {
+    READ_ONLY = 0,
+    INACCESSIBLE = 0x01,
+}
+impl Page28lock0noKeyState {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page28lock0noKeyState {
+        unsafe { core::mem::transmute(val & 0x01) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page28lock0noKeyState {
+    #[inline(always)]
+    fn from(val: u8) -> Page28lock0noKeyState {
+        Page28lock0noKeyState::from_bits(val)
+    }
+}
+impl From<Page28lock0noKeyState> for u8 {
+    #[inline(always)]
+    fn from(val: Page28lock0noKeyState) -> u8 {
+        Page28lock0noKeyState::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page28lock1lockBl {
+    #[doc = "Bootloader permits user reads and writes to this page"]
+    READ_WRITE = 0,
+    #[doc = "Bootloader permits user reads of this page"]
+    READ_ONLY = 0x01,
+    #[doc = "Do not use. Behaves the same as INACCESSIBLE"]
+    RESERVED = 0x02,
+    #[doc = "Bootloader does not permit user access to this page"]
+    INACCESSIBLE = 0x03,
+}
+impl Page28lock1lockBl {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page28lock1lockBl {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page28lock1lockBl {
+    #[inline(always)]
+    fn from(val: u8) -> Page28lock1lockBl {
+        Page28lock1lockBl::from_bits(val)
+    }
+}
+impl From<Page28lock1lockBl> for u8 {
+    #[inline(always)]
+    fn from(val: Page28lock1lockBl) -> u8 {
+        Page28lock1lockBl::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page28lock1lockNs {
+    #[doc = "Page can be read by Non-secure software, and Secure software may permit Non-secure writes."]
+    READ_WRITE = 0,
+    #[doc = "Page can be read by Non-secure software"]
+    READ_ONLY = 0x01,
+    #[doc = "Do not use. Behaves the same as INACCESSIBLE."]
+    RESERVED = 0x02,
+    #[doc = "Page can not be accessed by Non-secure software."]
+    INACCESSIBLE = 0x03,
+}
+impl Page28lock1lockNs {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page28lock1lockNs {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page28lock1lockNs {
+    #[inline(always)]
+    fn from(val: u8) -> Page28lock1lockNs {
+        Page28lock1lockNs::from_bits(val)
+    }
+}
+impl From<Page28lock1lockNs> for u8 {
+    #[inline(always)]
+    fn from(val: Page28lock1lockNs) -> u8 {
+        Page28lock1lockNs::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page28lock1lockS {
+    #[doc = "Page is fully accessible by Secure software."]
+    READ_WRITE = 0,
+    #[doc = "Page can be read by Secure software, but can not be written."]
+    READ_ONLY = 0x01,
+    #[doc = "Do not use. Behaves the same as INACCESSIBLE."]
+    RESERVED = 0x02,
+    #[doc = "Page can not be accessed by Secure software."]
+    INACCESSIBLE = 0x03,
+}
+impl Page28lock1lockS {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page28lock1lockS {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page28lock1lockS {
+    #[inline(always)]
+    fn from(val: u8) -> Page28lock1lockS {
+        Page28lock1lockS::from_bits(val)
+    }
+}
+impl From<Page28lock1lockS> for u8 {
+    #[inline(always)]
+    fn from(val: Page28lock1lockS) -> u8 {
+        Page28lock1lockS::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page29lock0noKeyState {
+    READ_ONLY = 0,
+    INACCESSIBLE = 0x01,
+}
+impl Page29lock0noKeyState {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page29lock0noKeyState {
+        unsafe { core::mem::transmute(val & 0x01) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page29lock0noKeyState {
+    #[inline(always)]
+    fn from(val: u8) -> Page29lock0noKeyState {
+        Page29lock0noKeyState::from_bits(val)
+    }
+}
+impl From<Page29lock0noKeyState> for u8 {
+    #[inline(always)]
+    fn from(val: Page29lock0noKeyState) -> u8 {
+        Page29lock0noKeyState::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page29lock1lockBl {
+    #[doc = "Bootloader permits user reads and writes to this page"]
+    READ_WRITE = 0,
+    #[doc = "Bootloader permits user reads of this page"]
+    READ_ONLY = 0x01,
+    #[doc = "Do not use. Behaves the same as INACCESSIBLE"]
+    RESERVED = 0x02,
+    #[doc = "Bootloader does not permit user access to this page"]
+    INACCESSIBLE = 0x03,
+}
+impl Page29lock1lockBl {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page29lock1lockBl {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page29lock1lockBl {
+    #[inline(always)]
+    fn from(val: u8) -> Page29lock1lockBl {
+        Page29lock1lockBl::from_bits(val)
+    }
+}
+impl From<Page29lock1lockBl> for u8 {
+    #[inline(always)]
+    fn from(val: Page29lock1lockBl) -> u8 {
+        Page29lock1lockBl::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page29lock1lockNs {
+    #[doc = "Page can be read by Non-secure software, and Secure software may permit Non-secure writes."]
+    READ_WRITE = 0,
+    #[doc = "Page can be read by Non-secure software"]
+    READ_ONLY = 0x01,
+    #[doc = "Do not use. Behaves the same as INACCESSIBLE."]
+    RESERVED = 0x02,
+    #[doc = "Page can not be accessed by Non-secure software."]
+    INACCESSIBLE = 0x03,
+}
+impl Page29lock1lockNs {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page29lock1lockNs {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page29lock1lockNs {
+    #[inline(always)]
+    fn from(val: u8) -> Page29lock1lockNs {
+        Page29lock1lockNs::from_bits(val)
+    }
+}
+impl From<Page29lock1lockNs> for u8 {
+    #[inline(always)]
+    fn from(val: Page29lock1lockNs) -> u8 {
+        Page29lock1lockNs::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page29lock1lockS {
+    #[doc = "Page is fully accessible by Secure software."]
+    READ_WRITE = 0,
+    #[doc = "Page can be read by Secure software, but can not be written."]
+    READ_ONLY = 0x01,
+    #[doc = "Do not use. Behaves the same as INACCESSIBLE."]
+    RESERVED = 0x02,
+    #[doc = "Page can not be accessed by Secure software."]
+    INACCESSIBLE = 0x03,
+}
+impl Page29lock1lockS {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page29lock1lockS {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page29lock1lockS {
+    #[inline(always)]
+    fn from(val: u8) -> Page29lock1lockS {
+        Page29lock1lockS::from_bits(val)
+    }
+}
+impl From<Page29lock1lockS> for u8 {
+    #[inline(always)]
+    fn from(val: Page29lock1lockS) -> u8 {
+        Page29lock1lockS::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page2lock0noKeyState {
+    READ_ONLY = 0,
+    INACCESSIBLE = 0x01,
+}
+impl Page2lock0noKeyState {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page2lock0noKeyState {
+        unsafe { core::mem::transmute(val & 0x01) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page2lock0noKeyState {
+    #[inline(always)]
+    fn from(val: u8) -> Page2lock0noKeyState {
+        Page2lock0noKeyState::from_bits(val)
+    }
+}
+impl From<Page2lock0noKeyState> for u8 {
+    #[inline(always)]
+    fn from(val: Page2lock0noKeyState) -> u8 {
+        Page2lock0noKeyState::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page2lock1lockBl {
+    #[doc = "Bootloader permits user reads and writes to this page"]
+    READ_WRITE = 0,
+    #[doc = "Bootloader permits user reads of this page"]
+    READ_ONLY = 0x01,
+    #[doc = "Do not use. Behaves the same as INACCESSIBLE"]
+    RESERVED = 0x02,
+    #[doc = "Bootloader does not permit user access to this page"]
+    INACCESSIBLE = 0x03,
+}
+impl Page2lock1lockBl {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page2lock1lockBl {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page2lock1lockBl {
+    #[inline(always)]
+    fn from(val: u8) -> Page2lock1lockBl {
+        Page2lock1lockBl::from_bits(val)
+    }
+}
+impl From<Page2lock1lockBl> for u8 {
+    #[inline(always)]
+    fn from(val: Page2lock1lockBl) -> u8 {
+        Page2lock1lockBl::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page2lock1lockNs {
+    #[doc = "Page can be read by Non-secure software, and Secure software may permit Non-secure writes."]
+    READ_WRITE = 0,
+    #[doc = "Page can be read by Non-secure software"]
+    READ_ONLY = 0x01,
+    #[doc = "Do not use. Behaves the same as INACCESSIBLE."]
+    RESERVED = 0x02,
+    #[doc = "Page can not be accessed by Non-secure software."]
+    INACCESSIBLE = 0x03,
+}
+impl Page2lock1lockNs {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page2lock1lockNs {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page2lock1lockNs {
+    #[inline(always)]
+    fn from(val: u8) -> Page2lock1lockNs {
+        Page2lock1lockNs::from_bits(val)
+    }
+}
+impl From<Page2lock1lockNs> for u8 {
+    #[inline(always)]
+    fn from(val: Page2lock1lockNs) -> u8 {
+        Page2lock1lockNs::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page2lock1lockS {
+    #[doc = "Page is fully accessible by Secure software."]
+    READ_WRITE = 0,
+    #[doc = "Page can be read by Secure software, but can not be written."]
+    READ_ONLY = 0x01,
+    #[doc = "Do not use. Behaves the same as INACCESSIBLE."]
+    RESERVED = 0x02,
+    #[doc = "Page can not be accessed by Secure software."]
+    INACCESSIBLE = 0x03,
+}
+impl Page2lock1lockS {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page2lock1lockS {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page2lock1lockS {
+    #[inline(always)]
+    fn from(val: u8) -> Page2lock1lockS {
+        Page2lock1lockS::from_bits(val)
+    }
+}
+impl From<Page2lock1lockS> for u8 {
+    #[inline(always)]
+    fn from(val: Page2lock1lockS) -> u8 {
+        Page2lock1lockS::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page30lock0noKeyState {
+    READ_ONLY = 0,
+    INACCESSIBLE = 0x01,
+}
+impl Page30lock0noKeyState {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page30lock0noKeyState {
+        unsafe { core::mem::transmute(val & 0x01) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page30lock0noKeyState {
+    #[inline(always)]
+    fn from(val: u8) -> Page30lock0noKeyState {
+        Page30lock0noKeyState::from_bits(val)
+    }
+}
+impl From<Page30lock0noKeyState> for u8 {
+    #[inline(always)]
+    fn from(val: Page30lock0noKeyState) -> u8 {
+        Page30lock0noKeyState::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page30lock1lockBl {
+    #[doc = "Bootloader permits user reads and writes to this page"]
+    READ_WRITE = 0,
+    #[doc = "Bootloader permits user reads of this page"]
+    READ_ONLY = 0x01,
+    #[doc = "Do not use. Behaves the same as INACCESSIBLE"]
+    RESERVED = 0x02,
+    #[doc = "Bootloader does not permit user access to this page"]
+    INACCESSIBLE = 0x03,
+}
+impl Page30lock1lockBl {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page30lock1lockBl {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page30lock1lockBl {
+    #[inline(always)]
+    fn from(val: u8) -> Page30lock1lockBl {
+        Page30lock1lockBl::from_bits(val)
+    }
+}
+impl From<Page30lock1lockBl> for u8 {
+    #[inline(always)]
+    fn from(val: Page30lock1lockBl) -> u8 {
+        Page30lock1lockBl::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page30lock1lockNs {
+    #[doc = "Page can be read by Non-secure software, and Secure software may permit Non-secure writes."]
+    READ_WRITE = 0,
+    #[doc = "Page can be read by Non-secure software"]
+    READ_ONLY = 0x01,
+    #[doc = "Do not use. Behaves the same as INACCESSIBLE."]
+    RESERVED = 0x02,
+    #[doc = "Page can not be accessed by Non-secure software."]
+    INACCESSIBLE = 0x03,
+}
+impl Page30lock1lockNs {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page30lock1lockNs {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page30lock1lockNs {
+    #[inline(always)]
+    fn from(val: u8) -> Page30lock1lockNs {
+        Page30lock1lockNs::from_bits(val)
+    }
+}
+impl From<Page30lock1lockNs> for u8 {
+    #[inline(always)]
+    fn from(val: Page30lock1lockNs) -> u8 {
+        Page30lock1lockNs::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page30lock1lockS {
+    #[doc = "Page is fully accessible by Secure software."]
+    READ_WRITE = 0,
+    #[doc = "Page can be read by Secure software, but can not be written."]
+    READ_ONLY = 0x01,
+    #[doc = "Do not use. Behaves the same as INACCESSIBLE."]
+    RESERVED = 0x02,
+    #[doc = "Page can not be accessed by Secure software."]
+    INACCESSIBLE = 0x03,
+}
+impl Page30lock1lockS {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page30lock1lockS {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page30lock1lockS {
+    #[inline(always)]
+    fn from(val: u8) -> Page30lock1lockS {
+        Page30lock1lockS::from_bits(val)
+    }
+}
+impl From<Page30lock1lockS> for u8 {
+    #[inline(always)]
+    fn from(val: Page30lock1lockS) -> u8 {
+        Page30lock1lockS::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page31lock0noKeyState {
+    READ_ONLY = 0,
+    INACCESSIBLE = 0x01,
+}
+impl Page31lock0noKeyState {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page31lock0noKeyState {
+        unsafe { core::mem::transmute(val & 0x01) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page31lock0noKeyState {
+    #[inline(always)]
+    fn from(val: u8) -> Page31lock0noKeyState {
+        Page31lock0noKeyState::from_bits(val)
+    }
+}
+impl From<Page31lock0noKeyState> for u8 {
+    #[inline(always)]
+    fn from(val: Page31lock0noKeyState) -> u8 {
+        Page31lock0noKeyState::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page31lock1lockBl {
+    #[doc = "Bootloader permits user reads and writes to this page"]
+    READ_WRITE = 0,
+    #[doc = "Bootloader permits user reads of this page"]
+    READ_ONLY = 0x01,
+    #[doc = "Do not use. Behaves the same as INACCESSIBLE"]
+    RESERVED = 0x02,
+    #[doc = "Bootloader does not permit user access to this page"]
+    INACCESSIBLE = 0x03,
+}
+impl Page31lock1lockBl {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page31lock1lockBl {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page31lock1lockBl {
+    #[inline(always)]
+    fn from(val: u8) -> Page31lock1lockBl {
+        Page31lock1lockBl::from_bits(val)
+    }
+}
+impl From<Page31lock1lockBl> for u8 {
+    #[inline(always)]
+    fn from(val: Page31lock1lockBl) -> u8 {
+        Page31lock1lockBl::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page31lock1lockNs {
+    #[doc = "Page can be read by Non-secure software, and Secure software may permit Non-secure writes."]
+    READ_WRITE = 0,
+    #[doc = "Page can be read by Non-secure software"]
+    READ_ONLY = 0x01,
+    #[doc = "Do not use. Behaves the same as INACCESSIBLE."]
+    RESERVED = 0x02,
+    #[doc = "Page can not be accessed by Non-secure software."]
+    INACCESSIBLE = 0x03,
+}
+impl Page31lock1lockNs {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page31lock1lockNs {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page31lock1lockNs {
+    #[inline(always)]
+    fn from(val: u8) -> Page31lock1lockNs {
+        Page31lock1lockNs::from_bits(val)
+    }
+}
+impl From<Page31lock1lockNs> for u8 {
+    #[inline(always)]
+    fn from(val: Page31lock1lockNs) -> u8 {
+        Page31lock1lockNs::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page31lock1lockS {
+    #[doc = "Page is fully accessible by Secure software."]
+    READ_WRITE = 0,
+    #[doc = "Page can be read by Secure software, but can not be written."]
+    READ_ONLY = 0x01,
+    #[doc = "Do not use. Behaves the same as INACCESSIBLE."]
+    RESERVED = 0x02,
+    #[doc = "Page can not be accessed by Secure software."]
+    INACCESSIBLE = 0x03,
+}
+impl Page31lock1lockS {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page31lock1lockS {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page31lock1lockS {
+    #[inline(always)]
+    fn from(val: u8) -> Page31lock1lockS {
+        Page31lock1lockS::from_bits(val)
+    }
+}
+impl From<Page31lock1lockS> for u8 {
+    #[inline(always)]
+    fn from(val: Page31lock1lockS) -> u8 {
+        Page31lock1lockS::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page32lock0noKeyState {
+    READ_ONLY = 0,
+    INACCESSIBLE = 0x01,
+}
+impl Page32lock0noKeyState {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page32lock0noKeyState {
+        unsafe { core::mem::transmute(val & 0x01) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page32lock0noKeyState {
+    #[inline(always)]
+    fn from(val: u8) -> Page32lock0noKeyState {
+        Page32lock0noKeyState::from_bits(val)
+    }
+}
+impl From<Page32lock0noKeyState> for u8 {
+    #[inline(always)]
+    fn from(val: Page32lock0noKeyState) -> u8 {
+        Page32lock0noKeyState::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page32lock1lockBl {
+    #[doc = "Bootloader permits user reads and writes to this page"]
+    READ_WRITE = 0,
+    #[doc = "Bootloader permits user reads of this page"]
+    READ_ONLY = 0x01,
+    #[doc = "Do not use. Behaves the same as INACCESSIBLE"]
+    RESERVED = 0x02,
+    #[doc = "Bootloader does not permit user access to this page"]
+    INACCESSIBLE = 0x03,
+}
+impl Page32lock1lockBl {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page32lock1lockBl {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page32lock1lockBl {
+    #[inline(always)]
+    fn from(val: u8) -> Page32lock1lockBl {
+        Page32lock1lockBl::from_bits(val)
+    }
+}
+impl From<Page32lock1lockBl> for u8 {
+    #[inline(always)]
+    fn from(val: Page32lock1lockBl) -> u8 {
+        Page32lock1lockBl::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page32lock1lockNs {
+    #[doc = "Page can be read by Non-secure software, and Secure software may permit Non-secure writes."]
+    READ_WRITE = 0,
+    #[doc = "Page can be read by Non-secure software"]
+    READ_ONLY = 0x01,
+    #[doc = "Do not use. Behaves the same as INACCESSIBLE."]
+    RESERVED = 0x02,
+    #[doc = "Page can not be accessed by Non-secure software."]
+    INACCESSIBLE = 0x03,
+}
+impl Page32lock1lockNs {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page32lock1lockNs {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page32lock1lockNs {
+    #[inline(always)]
+    fn from(val: u8) -> Page32lock1lockNs {
+        Page32lock1lockNs::from_bits(val)
+    }
+}
+impl From<Page32lock1lockNs> for u8 {
+    #[inline(always)]
+    fn from(val: Page32lock1lockNs) -> u8 {
+        Page32lock1lockNs::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page32lock1lockS {
+    #[doc = "Page is fully accessible by Secure software."]
+    READ_WRITE = 0,
+    #[doc = "Page can be read by Secure software, but can not be written."]
+    READ_ONLY = 0x01,
+    #[doc = "Do not use. Behaves the same as INACCESSIBLE."]
+    RESERVED = 0x02,
+    #[doc = "Page can not be accessed by Secure software."]
+    INACCESSIBLE = 0x03,
+}
+impl Page32lock1lockS {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page32lock1lockS {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page32lock1lockS {
+    #[inline(always)]
+    fn from(val: u8) -> Page32lock1lockS {
+        Page32lock1lockS::from_bits(val)
+    }
+}
+impl From<Page32lock1lockS> for u8 {
+    #[inline(always)]
+    fn from(val: Page32lock1lockS) -> u8 {
+        Page32lock1lockS::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page33lock0noKeyState {
+    READ_ONLY = 0,
+    INACCESSIBLE = 0x01,
+}
+impl Page33lock0noKeyState {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page33lock0noKeyState {
+        unsafe { core::mem::transmute(val & 0x01) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page33lock0noKeyState {
+    #[inline(always)]
+    fn from(val: u8) -> Page33lock0noKeyState {
+        Page33lock0noKeyState::from_bits(val)
+    }
+}
+impl From<Page33lock0noKeyState> for u8 {
+    #[inline(always)]
+    fn from(val: Page33lock0noKeyState) -> u8 {
+        Page33lock0noKeyState::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page33lock1lockBl {
+    #[doc = "Bootloader permits user reads and writes to this page"]
+    READ_WRITE = 0,
+    #[doc = "Bootloader permits user reads of this page"]
+    READ_ONLY = 0x01,
+    #[doc = "Do not use. Behaves the same as INACCESSIBLE"]
+    RESERVED = 0x02,
+    #[doc = "Bootloader does not permit user access to this page"]
+    INACCESSIBLE = 0x03,
+}
+impl Page33lock1lockBl {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page33lock1lockBl {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page33lock1lockBl {
+    #[inline(always)]
+    fn from(val: u8) -> Page33lock1lockBl {
+        Page33lock1lockBl::from_bits(val)
+    }
+}
+impl From<Page33lock1lockBl> for u8 {
+    #[inline(always)]
+    fn from(val: Page33lock1lockBl) -> u8 {
+        Page33lock1lockBl::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page33lock1lockNs {
+    #[doc = "Page can be read by Non-secure software, and Secure software may permit Non-secure writes."]
+    READ_WRITE = 0,
+    #[doc = "Page can be read by Non-secure software"]
+    READ_ONLY = 0x01,
+    #[doc = "Do not use. Behaves the same as INACCESSIBLE."]
+    RESERVED = 0x02,
+    #[doc = "Page can not be accessed by Non-secure software."]
+    INACCESSIBLE = 0x03,
+}
+impl Page33lock1lockNs {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page33lock1lockNs {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page33lock1lockNs {
+    #[inline(always)]
+    fn from(val: u8) -> Page33lock1lockNs {
+        Page33lock1lockNs::from_bits(val)
+    }
+}
+impl From<Page33lock1lockNs> for u8 {
+    #[inline(always)]
+    fn from(val: Page33lock1lockNs) -> u8 {
+        Page33lock1lockNs::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page33lock1lockS {
+    #[doc = "Page is fully accessible by Secure software."]
+    READ_WRITE = 0,
+    #[doc = "Page can be read by Secure software, but can not be written."]
+    READ_ONLY = 0x01,
+    #[doc = "Do not use. Behaves the same as INACCESSIBLE."]
+    RESERVED = 0x02,
+    #[doc = "Page can not be accessed by Secure software."]
+    INACCESSIBLE = 0x03,
+}
+impl Page33lock1lockS {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page33lock1lockS {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page33lock1lockS {
+    #[inline(always)]
+    fn from(val: u8) -> Page33lock1lockS {
+        Page33lock1lockS::from_bits(val)
+    }
+}
+impl From<Page33lock1lockS> for u8 {
+    #[inline(always)]
+    fn from(val: Page33lock1lockS) -> u8 {
+        Page33lock1lockS::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page34lock0noKeyState {
+    READ_ONLY = 0,
+    INACCESSIBLE = 0x01,
+}
+impl Page34lock0noKeyState {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page34lock0noKeyState {
+        unsafe { core::mem::transmute(val & 0x01) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page34lock0noKeyState {
+    #[inline(always)]
+    fn from(val: u8) -> Page34lock0noKeyState {
+        Page34lock0noKeyState::from_bits(val)
+    }
+}
+impl From<Page34lock0noKeyState> for u8 {
+    #[inline(always)]
+    fn from(val: Page34lock0noKeyState) -> u8 {
+        Page34lock0noKeyState::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page34lock1lockBl {
+    #[doc = "Bootloader permits user reads and writes to this page"]
+    READ_WRITE = 0,
+    #[doc = "Bootloader permits user reads of this page"]
+    READ_ONLY = 0x01,
+    #[doc = "Do not use. Behaves the same as INACCESSIBLE"]
+    RESERVED = 0x02,
+    #[doc = "Bootloader does not permit user access to this page"]
+    INACCESSIBLE = 0x03,
+}
+impl Page34lock1lockBl {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page34lock1lockBl {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page34lock1lockBl {
+    #[inline(always)]
+    fn from(val: u8) -> Page34lock1lockBl {
+        Page34lock1lockBl::from_bits(val)
+    }
+}
+impl From<Page34lock1lockBl> for u8 {
+    #[inline(always)]
+    fn from(val: Page34lock1lockBl) -> u8 {
+        Page34lock1lockBl::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page34lock1lockNs {
+    #[doc = "Page can be read by Non-secure software, and Secure software may permit Non-secure writes."]
+    READ_WRITE = 0,
+    #[doc = "Page can be read by Non-secure software"]
+    READ_ONLY = 0x01,
+    #[doc = "Do not use. Behaves the same as INACCESSIBLE."]
+    RESERVED = 0x02,
+    #[doc = "Page can not be accessed by Non-secure software."]
+    INACCESSIBLE = 0x03,
+}
+impl Page34lock1lockNs {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page34lock1lockNs {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page34lock1lockNs {
+    #[inline(always)]
+    fn from(val: u8) -> Page34lock1lockNs {
+        Page34lock1lockNs::from_bits(val)
+    }
+}
+impl From<Page34lock1lockNs> for u8 {
+    #[inline(always)]
+    fn from(val: Page34lock1lockNs) -> u8 {
+        Page34lock1lockNs::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page34lock1lockS {
+    #[doc = "Page is fully accessible by Secure software."]
+    READ_WRITE = 0,
+    #[doc = "Page can be read by Secure software, but can not be written."]
+    READ_ONLY = 0x01,
+    #[doc = "Do not use. Behaves the same as INACCESSIBLE."]
+    RESERVED = 0x02,
+    #[doc = "Page can not be accessed by Secure software."]
+    INACCESSIBLE = 0x03,
+}
+impl Page34lock1lockS {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page34lock1lockS {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page34lock1lockS {
+    #[inline(always)]
+    fn from(val: u8) -> Page34lock1lockS {
+        Page34lock1lockS::from_bits(val)
+    }
+}
+impl From<Page34lock1lockS> for u8 {
+    #[inline(always)]
+    fn from(val: Page34lock1lockS) -> u8 {
+        Page34lock1lockS::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page35lock0noKeyState {
+    READ_ONLY = 0,
+    INACCESSIBLE = 0x01,
+}
+impl Page35lock0noKeyState {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page35lock0noKeyState {
+        unsafe { core::mem::transmute(val & 0x01) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page35lock0noKeyState {
+    #[inline(always)]
+    fn from(val: u8) -> Page35lock0noKeyState {
+        Page35lock0noKeyState::from_bits(val)
+    }
+}
+impl From<Page35lock0noKeyState> for u8 {
+    #[inline(always)]
+    fn from(val: Page35lock0noKeyState) -> u8 {
+        Page35lock0noKeyState::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page35lock1lockBl {
+    #[doc = "Bootloader permits user reads and writes to this page"]
+    READ_WRITE = 0,
+    #[doc = "Bootloader permits user reads of this page"]
+    READ_ONLY = 0x01,
+    #[doc = "Do not use. Behaves the same as INACCESSIBLE"]
+    RESERVED = 0x02,
+    #[doc = "Bootloader does not permit user access to this page"]
+    INACCESSIBLE = 0x03,
+}
+impl Page35lock1lockBl {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page35lock1lockBl {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page35lock1lockBl {
+    #[inline(always)]
+    fn from(val: u8) -> Page35lock1lockBl {
+        Page35lock1lockBl::from_bits(val)
+    }
+}
+impl From<Page35lock1lockBl> for u8 {
+    #[inline(always)]
+    fn from(val: Page35lock1lockBl) -> u8 {
+        Page35lock1lockBl::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page35lock1lockNs {
+    #[doc = "Page can be read by Non-secure software, and Secure software may permit Non-secure writes."]
+    READ_WRITE = 0,
+    #[doc = "Page can be read by Non-secure software"]
+    READ_ONLY = 0x01,
+    #[doc = "Do not use. Behaves the same as INACCESSIBLE."]
+    RESERVED = 0x02,
+    #[doc = "Page can not be accessed by Non-secure software."]
+    INACCESSIBLE = 0x03,
+}
+impl Page35lock1lockNs {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page35lock1lockNs {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page35lock1lockNs {
+    #[inline(always)]
+    fn from(val: u8) -> Page35lock1lockNs {
+        Page35lock1lockNs::from_bits(val)
+    }
+}
+impl From<Page35lock1lockNs> for u8 {
+    #[inline(always)]
+    fn from(val: Page35lock1lockNs) -> u8 {
+        Page35lock1lockNs::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page35lock1lockS {
+    #[doc = "Page is fully accessible by Secure software."]
+    READ_WRITE = 0,
+    #[doc = "Page can be read by Secure software, but can not be written."]
+    READ_ONLY = 0x01,
+    #[doc = "Do not use. Behaves the same as INACCESSIBLE."]
+    RESERVED = 0x02,
+    #[doc = "Page can not be accessed by Secure software."]
+    INACCESSIBLE = 0x03,
+}
+impl Page35lock1lockS {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page35lock1lockS {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page35lock1lockS {
+    #[inline(always)]
+    fn from(val: u8) -> Page35lock1lockS {
+        Page35lock1lockS::from_bits(val)
+    }
+}
+impl From<Page35lock1lockS> for u8 {
+    #[inline(always)]
+    fn from(val: Page35lock1lockS) -> u8 {
+        Page35lock1lockS::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page36lock0noKeyState {
+    READ_ONLY = 0,
+    INACCESSIBLE = 0x01,
+}
+impl Page36lock0noKeyState {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page36lock0noKeyState {
+        unsafe { core::mem::transmute(val & 0x01) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page36lock0noKeyState {
+    #[inline(always)]
+    fn from(val: u8) -> Page36lock0noKeyState {
+        Page36lock0noKeyState::from_bits(val)
+    }
+}
+impl From<Page36lock0noKeyState> for u8 {
+    #[inline(always)]
+    fn from(val: Page36lock0noKeyState) -> u8 {
+        Page36lock0noKeyState::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page36lock1lockBl {
+    #[doc = "Bootloader permits user reads and writes to this page"]
+    READ_WRITE = 0,
+    #[doc = "Bootloader permits user reads of this page"]
+    READ_ONLY = 0x01,
+    #[doc = "Do not use. Behaves the same as INACCESSIBLE"]
+    RESERVED = 0x02,
+    #[doc = "Bootloader does not permit user access to this page"]
+    INACCESSIBLE = 0x03,
+}
+impl Page36lock1lockBl {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page36lock1lockBl {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page36lock1lockBl {
+    #[inline(always)]
+    fn from(val: u8) -> Page36lock1lockBl {
+        Page36lock1lockBl::from_bits(val)
+    }
+}
+impl From<Page36lock1lockBl> for u8 {
+    #[inline(always)]
+    fn from(val: Page36lock1lockBl) -> u8 {
+        Page36lock1lockBl::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page36lock1lockNs {
+    #[doc = "Page can be read by Non-secure software, and Secure software may permit Non-secure writes."]
+    READ_WRITE = 0,
+    #[doc = "Page can be read by Non-secure software"]
+    READ_ONLY = 0x01,
+    #[doc = "Do not use. Behaves the same as INACCESSIBLE."]
+    RESERVED = 0x02,
+    #[doc = "Page can not be accessed by Non-secure software."]
+    INACCESSIBLE = 0x03,
+}
+impl Page36lock1lockNs {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page36lock1lockNs {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page36lock1lockNs {
+    #[inline(always)]
+    fn from(val: u8) -> Page36lock1lockNs {
+        Page36lock1lockNs::from_bits(val)
+    }
+}
+impl From<Page36lock1lockNs> for u8 {
+    #[inline(always)]
+    fn from(val: Page36lock1lockNs) -> u8 {
+        Page36lock1lockNs::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page36lock1lockS {
+    #[doc = "Page is fully accessible by Secure software."]
+    READ_WRITE = 0,
+    #[doc = "Page can be read by Secure software, but can not be written."]
+    READ_ONLY = 0x01,
+    #[doc = "Do not use. Behaves the same as INACCESSIBLE."]
+    RESERVED = 0x02,
+    #[doc = "Page can not be accessed by Secure software."]
+    INACCESSIBLE = 0x03,
+}
+impl Page36lock1lockS {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page36lock1lockS {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page36lock1lockS {
+    #[inline(always)]
+    fn from(val: u8) -> Page36lock1lockS {
+        Page36lock1lockS::from_bits(val)
+    }
+}
+impl From<Page36lock1lockS> for u8 {
+    #[inline(always)]
+    fn from(val: Page36lock1lockS) -> u8 {
+        Page36lock1lockS::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page37lock0noKeyState {
+    READ_ONLY = 0,
+    INACCESSIBLE = 0x01,
+}
+impl Page37lock0noKeyState {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page37lock0noKeyState {
+        unsafe { core::mem::transmute(val & 0x01) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page37lock0noKeyState {
+    #[inline(always)]
+    fn from(val: u8) -> Page37lock0noKeyState {
+        Page37lock0noKeyState::from_bits(val)
+    }
+}
+impl From<Page37lock0noKeyState> for u8 {
+    #[inline(always)]
+    fn from(val: Page37lock0noKeyState) -> u8 {
+        Page37lock0noKeyState::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page37lock1lockBl {
+    #[doc = "Bootloader permits user reads and writes to this page"]
+    READ_WRITE = 0,
+    #[doc = "Bootloader permits user reads of this page"]
+    READ_ONLY = 0x01,
+    #[doc = "Do not use. Behaves the same as INACCESSIBLE"]
+    RESERVED = 0x02,
+    #[doc = "Bootloader does not permit user access to this page"]
+    INACCESSIBLE = 0x03,
+}
+impl Page37lock1lockBl {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page37lock1lockBl {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page37lock1lockBl {
+    #[inline(always)]
+    fn from(val: u8) -> Page37lock1lockBl {
+        Page37lock1lockBl::from_bits(val)
+    }
+}
+impl From<Page37lock1lockBl> for u8 {
+    #[inline(always)]
+    fn from(val: Page37lock1lockBl) -> u8 {
+        Page37lock1lockBl::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page37lock1lockNs {
+    #[doc = "Page can be read by Non-secure software, and Secure software may permit Non-secure writes."]
+    READ_WRITE = 0,
+    #[doc = "Page can be read by Non-secure software"]
+    READ_ONLY = 0x01,
+    #[doc = "Do not use. Behaves the same as INACCESSIBLE."]
+    RESERVED = 0x02,
+    #[doc = "Page can not be accessed by Non-secure software."]
+    INACCESSIBLE = 0x03,
+}
+impl Page37lock1lockNs {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page37lock1lockNs {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page37lock1lockNs {
+    #[inline(always)]
+    fn from(val: u8) -> Page37lock1lockNs {
+        Page37lock1lockNs::from_bits(val)
+    }
+}
+impl From<Page37lock1lockNs> for u8 {
+    #[inline(always)]
+    fn from(val: Page37lock1lockNs) -> u8 {
+        Page37lock1lockNs::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page37lock1lockS {
+    #[doc = "Page is fully accessible by Secure software."]
+    READ_WRITE = 0,
+    #[doc = "Page can be read by Secure software, but can not be written."]
+    READ_ONLY = 0x01,
+    #[doc = "Do not use. Behaves the same as INACCESSIBLE."]
+    RESERVED = 0x02,
+    #[doc = "Page can not be accessed by Secure software."]
+    INACCESSIBLE = 0x03,
+}
+impl Page37lock1lockS {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page37lock1lockS {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page37lock1lockS {
+    #[inline(always)]
+    fn from(val: u8) -> Page37lock1lockS {
+        Page37lock1lockS::from_bits(val)
+    }
+}
+impl From<Page37lock1lockS> for u8 {
+    #[inline(always)]
+    fn from(val: Page37lock1lockS) -> u8 {
+        Page37lock1lockS::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page38lock0noKeyState {
+    READ_ONLY = 0,
+    INACCESSIBLE = 0x01,
+}
+impl Page38lock0noKeyState {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page38lock0noKeyState {
+        unsafe { core::mem::transmute(val & 0x01) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page38lock0noKeyState {
+    #[inline(always)]
+    fn from(val: u8) -> Page38lock0noKeyState {
+        Page38lock0noKeyState::from_bits(val)
+    }
+}
+impl From<Page38lock0noKeyState> for u8 {
+    #[inline(always)]
+    fn from(val: Page38lock0noKeyState) -> u8 {
+        Page38lock0noKeyState::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page38lock1lockBl {
+    #[doc = "Bootloader permits user reads and writes to this page"]
+    READ_WRITE = 0,
+    #[doc = "Bootloader permits user reads of this page"]
+    READ_ONLY = 0x01,
+    #[doc = "Do not use. Behaves the same as INACCESSIBLE"]
+    RESERVED = 0x02,
+    #[doc = "Bootloader does not permit user access to this page"]
+    INACCESSIBLE = 0x03,
+}
+impl Page38lock1lockBl {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page38lock1lockBl {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page38lock1lockBl {
+    #[inline(always)]
+    fn from(val: u8) -> Page38lock1lockBl {
+        Page38lock1lockBl::from_bits(val)
+    }
+}
+impl From<Page38lock1lockBl> for u8 {
+    #[inline(always)]
+    fn from(val: Page38lock1lockBl) -> u8 {
+        Page38lock1lockBl::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page38lock1lockNs {
+    #[doc = "Page can be read by Non-secure software, and Secure software may permit Non-secure writes."]
+    READ_WRITE = 0,
+    #[doc = "Page can be read by Non-secure software"]
+    READ_ONLY = 0x01,
+    #[doc = "Do not use. Behaves the same as INACCESSIBLE."]
+    RESERVED = 0x02,
+    #[doc = "Page can not be accessed by Non-secure software."]
+    INACCESSIBLE = 0x03,
+}
+impl Page38lock1lockNs {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page38lock1lockNs {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page38lock1lockNs {
+    #[inline(always)]
+    fn from(val: u8) -> Page38lock1lockNs {
+        Page38lock1lockNs::from_bits(val)
+    }
+}
+impl From<Page38lock1lockNs> for u8 {
+    #[inline(always)]
+    fn from(val: Page38lock1lockNs) -> u8 {
+        Page38lock1lockNs::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page38lock1lockS {
+    #[doc = "Page is fully accessible by Secure software."]
+    READ_WRITE = 0,
+    #[doc = "Page can be read by Secure software, but can not be written."]
+    READ_ONLY = 0x01,
+    #[doc = "Do not use. Behaves the same as INACCESSIBLE."]
+    RESERVED = 0x02,
+    #[doc = "Page can not be accessed by Secure software."]
+    INACCESSIBLE = 0x03,
+}
+impl Page38lock1lockS {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page38lock1lockS {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page38lock1lockS {
+    #[inline(always)]
+    fn from(val: u8) -> Page38lock1lockS {
+        Page38lock1lockS::from_bits(val)
+    }
+}
+impl From<Page38lock1lockS> for u8 {
+    #[inline(always)]
+    fn from(val: Page38lock1lockS) -> u8 {
+        Page38lock1lockS::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page39lock0noKeyState {
+    READ_ONLY = 0,
+    INACCESSIBLE = 0x01,
+}
+impl Page39lock0noKeyState {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page39lock0noKeyState {
+        unsafe { core::mem::transmute(val & 0x01) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page39lock0noKeyState {
+    #[inline(always)]
+    fn from(val: u8) -> Page39lock0noKeyState {
+        Page39lock0noKeyState::from_bits(val)
+    }
+}
+impl From<Page39lock0noKeyState> for u8 {
+    #[inline(always)]
+    fn from(val: Page39lock0noKeyState) -> u8 {
+        Page39lock0noKeyState::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page39lock1lockBl {
+    #[doc = "Bootloader permits user reads and writes to this page"]
+    READ_WRITE = 0,
+    #[doc = "Bootloader permits user reads of this page"]
+    READ_ONLY = 0x01,
+    #[doc = "Do not use. Behaves the same as INACCESSIBLE"]
+    RESERVED = 0x02,
+    #[doc = "Bootloader does not permit user access to this page"]
+    INACCESSIBLE = 0x03,
+}
+impl Page39lock1lockBl {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page39lock1lockBl {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page39lock1lockBl {
+    #[inline(always)]
+    fn from(val: u8) -> Page39lock1lockBl {
+        Page39lock1lockBl::from_bits(val)
+    }
+}
+impl From<Page39lock1lockBl> for u8 {
+    #[inline(always)]
+    fn from(val: Page39lock1lockBl) -> u8 {
+        Page39lock1lockBl::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page39lock1lockNs {
+    #[doc = "Page can be read by Non-secure software, and Secure software may permit Non-secure writes."]
+    READ_WRITE = 0,
+    #[doc = "Page can be read by Non-secure software"]
+    READ_ONLY = 0x01,
+    #[doc = "Do not use. Behaves the same as INACCESSIBLE."]
+    RESERVED = 0x02,
+    #[doc = "Page can not be accessed by Non-secure software."]
+    INACCESSIBLE = 0x03,
+}
+impl Page39lock1lockNs {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page39lock1lockNs {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page39lock1lockNs {
+    #[inline(always)]
+    fn from(val: u8) -> Page39lock1lockNs {
+        Page39lock1lockNs::from_bits(val)
+    }
+}
+impl From<Page39lock1lockNs> for u8 {
+    #[inline(always)]
+    fn from(val: Page39lock1lockNs) -> u8 {
+        Page39lock1lockNs::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page39lock1lockS {
+    #[doc = "Page is fully accessible by Secure software."]
+    READ_WRITE = 0,
+    #[doc = "Page can be read by Secure software, but can not be written."]
+    READ_ONLY = 0x01,
+    #[doc = "Do not use. Behaves the same as INACCESSIBLE."]
+    RESERVED = 0x02,
+    #[doc = "Page can not be accessed by Secure software."]
+    INACCESSIBLE = 0x03,
+}
+impl Page39lock1lockS {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page39lock1lockS {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page39lock1lockS {
+    #[inline(always)]
+    fn from(val: u8) -> Page39lock1lockS {
+        Page39lock1lockS::from_bits(val)
+    }
+}
+impl From<Page39lock1lockS> for u8 {
+    #[inline(always)]
+    fn from(val: Page39lock1lockS) -> u8 {
+        Page39lock1lockS::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page3lock0noKeyState {
+    READ_ONLY = 0,
+    INACCESSIBLE = 0x01,
+}
+impl Page3lock0noKeyState {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page3lock0noKeyState {
+        unsafe { core::mem::transmute(val & 0x01) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page3lock0noKeyState {
+    #[inline(always)]
+    fn from(val: u8) -> Page3lock0noKeyState {
+        Page3lock0noKeyState::from_bits(val)
+    }
+}
+impl From<Page3lock0noKeyState> for u8 {
+    #[inline(always)]
+    fn from(val: Page3lock0noKeyState) -> u8 {
+        Page3lock0noKeyState::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page3lock1lockBl {
+    #[doc = "Bootloader permits user reads and writes to this page"]
+    READ_WRITE = 0,
+    #[doc = "Bootloader permits user reads of this page"]
+    READ_ONLY = 0x01,
+    #[doc = "Do not use. Behaves the same as INACCESSIBLE"]
+    RESERVED = 0x02,
+    #[doc = "Bootloader does not permit user access to this page"]
+    INACCESSIBLE = 0x03,
+}
+impl Page3lock1lockBl {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page3lock1lockBl {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page3lock1lockBl {
+    #[inline(always)]
+    fn from(val: u8) -> Page3lock1lockBl {
+        Page3lock1lockBl::from_bits(val)
+    }
+}
+impl From<Page3lock1lockBl> for u8 {
+    #[inline(always)]
+    fn from(val: Page3lock1lockBl) -> u8 {
+        Page3lock1lockBl::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page3lock1lockNs {
+    #[doc = "Page can be read by Non-secure software, and Secure software may permit Non-secure writes."]
+    READ_WRITE = 0,
+    #[doc = "Page can be read by Non-secure software"]
+    READ_ONLY = 0x01,
+    #[doc = "Do not use. Behaves the same as INACCESSIBLE."]
+    RESERVED = 0x02,
+    #[doc = "Page can not be accessed by Non-secure software."]
+    INACCESSIBLE = 0x03,
+}
+impl Page3lock1lockNs {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page3lock1lockNs {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page3lock1lockNs {
+    #[inline(always)]
+    fn from(val: u8) -> Page3lock1lockNs {
+        Page3lock1lockNs::from_bits(val)
+    }
+}
+impl From<Page3lock1lockNs> for u8 {
+    #[inline(always)]
+    fn from(val: Page3lock1lockNs) -> u8 {
+        Page3lock1lockNs::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page3lock1lockS {
+    #[doc = "Page is fully accessible by Secure software."]
+    READ_WRITE = 0,
+    #[doc = "Page can be read by Secure software, but can not be written."]
+    READ_ONLY = 0x01,
+    #[doc = "Do not use. Behaves the same as INACCESSIBLE."]
+    RESERVED = 0x02,
+    #[doc = "Page can not be accessed by Secure software."]
+    INACCESSIBLE = 0x03,
+}
+impl Page3lock1lockS {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page3lock1lockS {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page3lock1lockS {
+    #[inline(always)]
+    fn from(val: u8) -> Page3lock1lockS {
+        Page3lock1lockS::from_bits(val)
+    }
+}
+impl From<Page3lock1lockS> for u8 {
+    #[inline(always)]
+    fn from(val: Page3lock1lockS) -> u8 {
+        Page3lock1lockS::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page40lock0noKeyState {
+    READ_ONLY = 0,
+    INACCESSIBLE = 0x01,
+}
+impl Page40lock0noKeyState {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page40lock0noKeyState {
+        unsafe { core::mem::transmute(val & 0x01) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page40lock0noKeyState {
+    #[inline(always)]
+    fn from(val: u8) -> Page40lock0noKeyState {
+        Page40lock0noKeyState::from_bits(val)
+    }
+}
+impl From<Page40lock0noKeyState> for u8 {
+    #[inline(always)]
+    fn from(val: Page40lock0noKeyState) -> u8 {
+        Page40lock0noKeyState::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page40lock1lockBl {
+    #[doc = "Bootloader permits user reads and writes to this page"]
+    READ_WRITE = 0,
+    #[doc = "Bootloader permits user reads of this page"]
+    READ_ONLY = 0x01,
+    #[doc = "Do not use. Behaves the same as INACCESSIBLE"]
+    RESERVED = 0x02,
+    #[doc = "Bootloader does not permit user access to this page"]
+    INACCESSIBLE = 0x03,
+}
+impl Page40lock1lockBl {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page40lock1lockBl {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page40lock1lockBl {
+    #[inline(always)]
+    fn from(val: u8) -> Page40lock1lockBl {
+        Page40lock1lockBl::from_bits(val)
+    }
+}
+impl From<Page40lock1lockBl> for u8 {
+    #[inline(always)]
+    fn from(val: Page40lock1lockBl) -> u8 {
+        Page40lock1lockBl::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page40lock1lockNs {
+    #[doc = "Page can be read by Non-secure software, and Secure software may permit Non-secure writes."]
+    READ_WRITE = 0,
+    #[doc = "Page can be read by Non-secure software"]
+    READ_ONLY = 0x01,
+    #[doc = "Do not use. Behaves the same as INACCESSIBLE."]
+    RESERVED = 0x02,
+    #[doc = "Page can not be accessed by Non-secure software."]
+    INACCESSIBLE = 0x03,
+}
+impl Page40lock1lockNs {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page40lock1lockNs {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page40lock1lockNs {
+    #[inline(always)]
+    fn from(val: u8) -> Page40lock1lockNs {
+        Page40lock1lockNs::from_bits(val)
+    }
+}
+impl From<Page40lock1lockNs> for u8 {
+    #[inline(always)]
+    fn from(val: Page40lock1lockNs) -> u8 {
+        Page40lock1lockNs::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page40lock1lockS {
+    #[doc = "Page is fully accessible by Secure software."]
+    READ_WRITE = 0,
+    #[doc = "Page can be read by Secure software, but can not be written."]
+    READ_ONLY = 0x01,
+    #[doc = "Do not use. Behaves the same as INACCESSIBLE."]
+    RESERVED = 0x02,
+    #[doc = "Page can not be accessed by Secure software."]
+    INACCESSIBLE = 0x03,
+}
+impl Page40lock1lockS {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page40lock1lockS {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page40lock1lockS {
+    #[inline(always)]
+    fn from(val: u8) -> Page40lock1lockS {
+        Page40lock1lockS::from_bits(val)
+    }
+}
+impl From<Page40lock1lockS> for u8 {
+    #[inline(always)]
+    fn from(val: Page40lock1lockS) -> u8 {
+        Page40lock1lockS::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page41lock0noKeyState {
+    READ_ONLY = 0,
+    INACCESSIBLE = 0x01,
+}
+impl Page41lock0noKeyState {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page41lock0noKeyState {
+        unsafe { core::mem::transmute(val & 0x01) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page41lock0noKeyState {
+    #[inline(always)]
+    fn from(val: u8) -> Page41lock0noKeyState {
+        Page41lock0noKeyState::from_bits(val)
+    }
+}
+impl From<Page41lock0noKeyState> for u8 {
+    #[inline(always)]
+    fn from(val: Page41lock0noKeyState) -> u8 {
+        Page41lock0noKeyState::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page41lock1lockBl {
+    #[doc = "Bootloader permits user reads and writes to this page"]
+    READ_WRITE = 0,
+    #[doc = "Bootloader permits user reads of this page"]
+    READ_ONLY = 0x01,
+    #[doc = "Do not use. Behaves the same as INACCESSIBLE"]
+    RESERVED = 0x02,
+    #[doc = "Bootloader does not permit user access to this page"]
+    INACCESSIBLE = 0x03,
+}
+impl Page41lock1lockBl {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page41lock1lockBl {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page41lock1lockBl {
+    #[inline(always)]
+    fn from(val: u8) -> Page41lock1lockBl {
+        Page41lock1lockBl::from_bits(val)
+    }
+}
+impl From<Page41lock1lockBl> for u8 {
+    #[inline(always)]
+    fn from(val: Page41lock1lockBl) -> u8 {
+        Page41lock1lockBl::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page41lock1lockNs {
+    #[doc = "Page can be read by Non-secure software, and Secure software may permit Non-secure writes."]
+    READ_WRITE = 0,
+    #[doc = "Page can be read by Non-secure software"]
+    READ_ONLY = 0x01,
+    #[doc = "Do not use. Behaves the same as INACCESSIBLE."]
+    RESERVED = 0x02,
+    #[doc = "Page can not be accessed by Non-secure software."]
+    INACCESSIBLE = 0x03,
+}
+impl Page41lock1lockNs {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page41lock1lockNs {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page41lock1lockNs {
+    #[inline(always)]
+    fn from(val: u8) -> Page41lock1lockNs {
+        Page41lock1lockNs::from_bits(val)
+    }
+}
+impl From<Page41lock1lockNs> for u8 {
+    #[inline(always)]
+    fn from(val: Page41lock1lockNs) -> u8 {
+        Page41lock1lockNs::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page41lock1lockS {
+    #[doc = "Page is fully accessible by Secure software."]
+    READ_WRITE = 0,
+    #[doc = "Page can be read by Secure software, but can not be written."]
+    READ_ONLY = 0x01,
+    #[doc = "Do not use. Behaves the same as INACCESSIBLE."]
+    RESERVED = 0x02,
+    #[doc = "Page can not be accessed by Secure software."]
+    INACCESSIBLE = 0x03,
+}
+impl Page41lock1lockS {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page41lock1lockS {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page41lock1lockS {
+    #[inline(always)]
+    fn from(val: u8) -> Page41lock1lockS {
+        Page41lock1lockS::from_bits(val)
+    }
+}
+impl From<Page41lock1lockS> for u8 {
+    #[inline(always)]
+    fn from(val: Page41lock1lockS) -> u8 {
+        Page41lock1lockS::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page42lock0noKeyState {
+    READ_ONLY = 0,
+    INACCESSIBLE = 0x01,
+}
+impl Page42lock0noKeyState {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page42lock0noKeyState {
+        unsafe { core::mem::transmute(val & 0x01) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page42lock0noKeyState {
+    #[inline(always)]
+    fn from(val: u8) -> Page42lock0noKeyState {
+        Page42lock0noKeyState::from_bits(val)
+    }
+}
+impl From<Page42lock0noKeyState> for u8 {
+    #[inline(always)]
+    fn from(val: Page42lock0noKeyState) -> u8 {
+        Page42lock0noKeyState::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page42lock1lockBl {
+    #[doc = "Bootloader permits user reads and writes to this page"]
+    READ_WRITE = 0,
+    #[doc = "Bootloader permits user reads of this page"]
+    READ_ONLY = 0x01,
+    #[doc = "Do not use. Behaves the same as INACCESSIBLE"]
+    RESERVED = 0x02,
+    #[doc = "Bootloader does not permit user access to this page"]
+    INACCESSIBLE = 0x03,
+}
+impl Page42lock1lockBl {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page42lock1lockBl {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page42lock1lockBl {
+    #[inline(always)]
+    fn from(val: u8) -> Page42lock1lockBl {
+        Page42lock1lockBl::from_bits(val)
+    }
+}
+impl From<Page42lock1lockBl> for u8 {
+    #[inline(always)]
+    fn from(val: Page42lock1lockBl) -> u8 {
+        Page42lock1lockBl::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page42lock1lockNs {
+    #[doc = "Page can be read by Non-secure software, and Secure software may permit Non-secure writes."]
+    READ_WRITE = 0,
+    #[doc = "Page can be read by Non-secure software"]
+    READ_ONLY = 0x01,
+    #[doc = "Do not use. Behaves the same as INACCESSIBLE."]
+    RESERVED = 0x02,
+    #[doc = "Page can not be accessed by Non-secure software."]
+    INACCESSIBLE = 0x03,
+}
+impl Page42lock1lockNs {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page42lock1lockNs {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page42lock1lockNs {
+    #[inline(always)]
+    fn from(val: u8) -> Page42lock1lockNs {
+        Page42lock1lockNs::from_bits(val)
+    }
+}
+impl From<Page42lock1lockNs> for u8 {
+    #[inline(always)]
+    fn from(val: Page42lock1lockNs) -> u8 {
+        Page42lock1lockNs::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page42lock1lockS {
+    #[doc = "Page is fully accessible by Secure software."]
+    READ_WRITE = 0,
+    #[doc = "Page can be read by Secure software, but can not be written."]
+    READ_ONLY = 0x01,
+    #[doc = "Do not use. Behaves the same as INACCESSIBLE."]
+    RESERVED = 0x02,
+    #[doc = "Page can not be accessed by Secure software."]
+    INACCESSIBLE = 0x03,
+}
+impl Page42lock1lockS {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page42lock1lockS {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page42lock1lockS {
+    #[inline(always)]
+    fn from(val: u8) -> Page42lock1lockS {
+        Page42lock1lockS::from_bits(val)
+    }
+}
+impl From<Page42lock1lockS> for u8 {
+    #[inline(always)]
+    fn from(val: Page42lock1lockS) -> u8 {
+        Page42lock1lockS::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page43lock0noKeyState {
+    READ_ONLY = 0,
+    INACCESSIBLE = 0x01,
+}
+impl Page43lock0noKeyState {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page43lock0noKeyState {
+        unsafe { core::mem::transmute(val & 0x01) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page43lock0noKeyState {
+    #[inline(always)]
+    fn from(val: u8) -> Page43lock0noKeyState {
+        Page43lock0noKeyState::from_bits(val)
+    }
+}
+impl From<Page43lock0noKeyState> for u8 {
+    #[inline(always)]
+    fn from(val: Page43lock0noKeyState) -> u8 {
+        Page43lock0noKeyState::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page43lock1lockBl {
+    #[doc = "Bootloader permits user reads and writes to this page"]
+    READ_WRITE = 0,
+    #[doc = "Bootloader permits user reads of this page"]
+    READ_ONLY = 0x01,
+    #[doc = "Do not use. Behaves the same as INACCESSIBLE"]
+    RESERVED = 0x02,
+    #[doc = "Bootloader does not permit user access to this page"]
+    INACCESSIBLE = 0x03,
+}
+impl Page43lock1lockBl {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page43lock1lockBl {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page43lock1lockBl {
+    #[inline(always)]
+    fn from(val: u8) -> Page43lock1lockBl {
+        Page43lock1lockBl::from_bits(val)
+    }
+}
+impl From<Page43lock1lockBl> for u8 {
+    #[inline(always)]
+    fn from(val: Page43lock1lockBl) -> u8 {
+        Page43lock1lockBl::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page43lock1lockNs {
+    #[doc = "Page can be read by Non-secure software, and Secure software may permit Non-secure writes."]
+    READ_WRITE = 0,
+    #[doc = "Page can be read by Non-secure software"]
+    READ_ONLY = 0x01,
+    #[doc = "Do not use. Behaves the same as INACCESSIBLE."]
+    RESERVED = 0x02,
+    #[doc = "Page can not be accessed by Non-secure software."]
+    INACCESSIBLE = 0x03,
+}
+impl Page43lock1lockNs {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page43lock1lockNs {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page43lock1lockNs {
+    #[inline(always)]
+    fn from(val: u8) -> Page43lock1lockNs {
+        Page43lock1lockNs::from_bits(val)
+    }
+}
+impl From<Page43lock1lockNs> for u8 {
+    #[inline(always)]
+    fn from(val: Page43lock1lockNs) -> u8 {
+        Page43lock1lockNs::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page43lock1lockS {
+    #[doc = "Page is fully accessible by Secure software."]
+    READ_WRITE = 0,
+    #[doc = "Page can be read by Secure software, but can not be written."]
+    READ_ONLY = 0x01,
+    #[doc = "Do not use. Behaves the same as INACCESSIBLE."]
+    RESERVED = 0x02,
+    #[doc = "Page can not be accessed by Secure software."]
+    INACCESSIBLE = 0x03,
+}
+impl Page43lock1lockS {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page43lock1lockS {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page43lock1lockS {
+    #[inline(always)]
+    fn from(val: u8) -> Page43lock1lockS {
+        Page43lock1lockS::from_bits(val)
+    }
+}
+impl From<Page43lock1lockS> for u8 {
+    #[inline(always)]
+    fn from(val: Page43lock1lockS) -> u8 {
+        Page43lock1lockS::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page44lock0noKeyState {
+    READ_ONLY = 0,
+    INACCESSIBLE = 0x01,
+}
+impl Page44lock0noKeyState {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page44lock0noKeyState {
+        unsafe { core::mem::transmute(val & 0x01) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page44lock0noKeyState {
+    #[inline(always)]
+    fn from(val: u8) -> Page44lock0noKeyState {
+        Page44lock0noKeyState::from_bits(val)
+    }
+}
+impl From<Page44lock0noKeyState> for u8 {
+    #[inline(always)]
+    fn from(val: Page44lock0noKeyState) -> u8 {
+        Page44lock0noKeyState::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page44lock1lockBl {
+    #[doc = "Bootloader permits user reads and writes to this page"]
+    READ_WRITE = 0,
+    #[doc = "Bootloader permits user reads of this page"]
+    READ_ONLY = 0x01,
+    #[doc = "Do not use. Behaves the same as INACCESSIBLE"]
+    RESERVED = 0x02,
+    #[doc = "Bootloader does not permit user access to this page"]
+    INACCESSIBLE = 0x03,
+}
+impl Page44lock1lockBl {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page44lock1lockBl {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page44lock1lockBl {
+    #[inline(always)]
+    fn from(val: u8) -> Page44lock1lockBl {
+        Page44lock1lockBl::from_bits(val)
+    }
+}
+impl From<Page44lock1lockBl> for u8 {
+    #[inline(always)]
+    fn from(val: Page44lock1lockBl) -> u8 {
+        Page44lock1lockBl::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page44lock1lockNs {
+    #[doc = "Page can be read by Non-secure software, and Secure software may permit Non-secure writes."]
+    READ_WRITE = 0,
+    #[doc = "Page can be read by Non-secure software"]
+    READ_ONLY = 0x01,
+    #[doc = "Do not use. Behaves the same as INACCESSIBLE."]
+    RESERVED = 0x02,
+    #[doc = "Page can not be accessed by Non-secure software."]
+    INACCESSIBLE = 0x03,
+}
+impl Page44lock1lockNs {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page44lock1lockNs {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page44lock1lockNs {
+    #[inline(always)]
+    fn from(val: u8) -> Page44lock1lockNs {
+        Page44lock1lockNs::from_bits(val)
+    }
+}
+impl From<Page44lock1lockNs> for u8 {
+    #[inline(always)]
+    fn from(val: Page44lock1lockNs) -> u8 {
+        Page44lock1lockNs::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page44lock1lockS {
+    #[doc = "Page is fully accessible by Secure software."]
+    READ_WRITE = 0,
+    #[doc = "Page can be read by Secure software, but can not be written."]
+    READ_ONLY = 0x01,
+    #[doc = "Do not use. Behaves the same as INACCESSIBLE."]
+    RESERVED = 0x02,
+    #[doc = "Page can not be accessed by Secure software."]
+    INACCESSIBLE = 0x03,
+}
+impl Page44lock1lockS {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page44lock1lockS {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page44lock1lockS {
+    #[inline(always)]
+    fn from(val: u8) -> Page44lock1lockS {
+        Page44lock1lockS::from_bits(val)
+    }
+}
+impl From<Page44lock1lockS> for u8 {
+    #[inline(always)]
+    fn from(val: Page44lock1lockS) -> u8 {
+        Page44lock1lockS::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page45lock0noKeyState {
+    READ_ONLY = 0,
+    INACCESSIBLE = 0x01,
+}
+impl Page45lock0noKeyState {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page45lock0noKeyState {
+        unsafe { core::mem::transmute(val & 0x01) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page45lock0noKeyState {
+    #[inline(always)]
+    fn from(val: u8) -> Page45lock0noKeyState {
+        Page45lock0noKeyState::from_bits(val)
+    }
+}
+impl From<Page45lock0noKeyState> for u8 {
+    #[inline(always)]
+    fn from(val: Page45lock0noKeyState) -> u8 {
+        Page45lock0noKeyState::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page45lock1lockBl {
+    #[doc = "Bootloader permits user reads and writes to this page"]
+    READ_WRITE = 0,
+    #[doc = "Bootloader permits user reads of this page"]
+    READ_ONLY = 0x01,
+    #[doc = "Do not use. Behaves the same as INACCESSIBLE"]
+    RESERVED = 0x02,
+    #[doc = "Bootloader does not permit user access to this page"]
+    INACCESSIBLE = 0x03,
+}
+impl Page45lock1lockBl {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page45lock1lockBl {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page45lock1lockBl {
+    #[inline(always)]
+    fn from(val: u8) -> Page45lock1lockBl {
+        Page45lock1lockBl::from_bits(val)
+    }
+}
+impl From<Page45lock1lockBl> for u8 {
+    #[inline(always)]
+    fn from(val: Page45lock1lockBl) -> u8 {
+        Page45lock1lockBl::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page45lock1lockNs {
+    #[doc = "Page can be read by Non-secure software, and Secure software may permit Non-secure writes."]
+    READ_WRITE = 0,
+    #[doc = "Page can be read by Non-secure software"]
+    READ_ONLY = 0x01,
+    #[doc = "Do not use. Behaves the same as INACCESSIBLE."]
+    RESERVED = 0x02,
+    #[doc = "Page can not be accessed by Non-secure software."]
+    INACCESSIBLE = 0x03,
+}
+impl Page45lock1lockNs {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page45lock1lockNs {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page45lock1lockNs {
+    #[inline(always)]
+    fn from(val: u8) -> Page45lock1lockNs {
+        Page45lock1lockNs::from_bits(val)
+    }
+}
+impl From<Page45lock1lockNs> for u8 {
+    #[inline(always)]
+    fn from(val: Page45lock1lockNs) -> u8 {
+        Page45lock1lockNs::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page45lock1lockS {
+    #[doc = "Page is fully accessible by Secure software."]
+    READ_WRITE = 0,
+    #[doc = "Page can be read by Secure software, but can not be written."]
+    READ_ONLY = 0x01,
+    #[doc = "Do not use. Behaves the same as INACCESSIBLE."]
+    RESERVED = 0x02,
+    #[doc = "Page can not be accessed by Secure software."]
+    INACCESSIBLE = 0x03,
+}
+impl Page45lock1lockS {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page45lock1lockS {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page45lock1lockS {
+    #[inline(always)]
+    fn from(val: u8) -> Page45lock1lockS {
+        Page45lock1lockS::from_bits(val)
+    }
+}
+impl From<Page45lock1lockS> for u8 {
+    #[inline(always)]
+    fn from(val: Page45lock1lockS) -> u8 {
+        Page45lock1lockS::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page46lock0noKeyState {
+    READ_ONLY = 0,
+    INACCESSIBLE = 0x01,
+}
+impl Page46lock0noKeyState {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page46lock0noKeyState {
+        unsafe { core::mem::transmute(val & 0x01) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page46lock0noKeyState {
+    #[inline(always)]
+    fn from(val: u8) -> Page46lock0noKeyState {
+        Page46lock0noKeyState::from_bits(val)
+    }
+}
+impl From<Page46lock0noKeyState> for u8 {
+    #[inline(always)]
+    fn from(val: Page46lock0noKeyState) -> u8 {
+        Page46lock0noKeyState::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page46lock1lockBl {
+    #[doc = "Bootloader permits user reads and writes to this page"]
+    READ_WRITE = 0,
+    #[doc = "Bootloader permits user reads of this page"]
+    READ_ONLY = 0x01,
+    #[doc = "Do not use. Behaves the same as INACCESSIBLE"]
+    RESERVED = 0x02,
+    #[doc = "Bootloader does not permit user access to this page"]
+    INACCESSIBLE = 0x03,
+}
+impl Page46lock1lockBl {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page46lock1lockBl {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page46lock1lockBl {
+    #[inline(always)]
+    fn from(val: u8) -> Page46lock1lockBl {
+        Page46lock1lockBl::from_bits(val)
+    }
+}
+impl From<Page46lock1lockBl> for u8 {
+    #[inline(always)]
+    fn from(val: Page46lock1lockBl) -> u8 {
+        Page46lock1lockBl::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page46lock1lockNs {
+    #[doc = "Page can be read by Non-secure software, and Secure software may permit Non-secure writes."]
+    READ_WRITE = 0,
+    #[doc = "Page can be read by Non-secure software"]
+    READ_ONLY = 0x01,
+    #[doc = "Do not use. Behaves the same as INACCESSIBLE."]
+    RESERVED = 0x02,
+    #[doc = "Page can not be accessed by Non-secure software."]
+    INACCESSIBLE = 0x03,
+}
+impl Page46lock1lockNs {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page46lock1lockNs {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page46lock1lockNs {
+    #[inline(always)]
+    fn from(val: u8) -> Page46lock1lockNs {
+        Page46lock1lockNs::from_bits(val)
+    }
+}
+impl From<Page46lock1lockNs> for u8 {
+    #[inline(always)]
+    fn from(val: Page46lock1lockNs) -> u8 {
+        Page46lock1lockNs::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page46lock1lockS {
+    #[doc = "Page is fully accessible by Secure software."]
+    READ_WRITE = 0,
+    #[doc = "Page can be read by Secure software, but can not be written."]
+    READ_ONLY = 0x01,
+    #[doc = "Do not use. Behaves the same as INACCESSIBLE."]
+    RESERVED = 0x02,
+    #[doc = "Page can not be accessed by Secure software."]
+    INACCESSIBLE = 0x03,
+}
+impl Page46lock1lockS {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page46lock1lockS {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page46lock1lockS {
+    #[inline(always)]
+    fn from(val: u8) -> Page46lock1lockS {
+        Page46lock1lockS::from_bits(val)
+    }
+}
+impl From<Page46lock1lockS> for u8 {
+    #[inline(always)]
+    fn from(val: Page46lock1lockS) -> u8 {
+        Page46lock1lockS::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page47lock0noKeyState {
+    READ_ONLY = 0,
+    INACCESSIBLE = 0x01,
+}
+impl Page47lock0noKeyState {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page47lock0noKeyState {
+        unsafe { core::mem::transmute(val & 0x01) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page47lock0noKeyState {
+    #[inline(always)]
+    fn from(val: u8) -> Page47lock0noKeyState {
+        Page47lock0noKeyState::from_bits(val)
+    }
+}
+impl From<Page47lock0noKeyState> for u8 {
+    #[inline(always)]
+    fn from(val: Page47lock0noKeyState) -> u8 {
+        Page47lock0noKeyState::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page47lock1lockBl {
+    #[doc = "Bootloader permits user reads and writes to this page"]
+    READ_WRITE = 0,
+    #[doc = "Bootloader permits user reads of this page"]
+    READ_ONLY = 0x01,
+    #[doc = "Do not use. Behaves the same as INACCESSIBLE"]
+    RESERVED = 0x02,
+    #[doc = "Bootloader does not permit user access to this page"]
+    INACCESSIBLE = 0x03,
+}
+impl Page47lock1lockBl {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page47lock1lockBl {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page47lock1lockBl {
+    #[inline(always)]
+    fn from(val: u8) -> Page47lock1lockBl {
+        Page47lock1lockBl::from_bits(val)
+    }
+}
+impl From<Page47lock1lockBl> for u8 {
+    #[inline(always)]
+    fn from(val: Page47lock1lockBl) -> u8 {
+        Page47lock1lockBl::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page47lock1lockNs {
+    #[doc = "Page can be read by Non-secure software, and Secure software may permit Non-secure writes."]
+    READ_WRITE = 0,
+    #[doc = "Page can be read by Non-secure software"]
+    READ_ONLY = 0x01,
+    #[doc = "Do not use. Behaves the same as INACCESSIBLE."]
+    RESERVED = 0x02,
+    #[doc = "Page can not be accessed by Non-secure software."]
+    INACCESSIBLE = 0x03,
+}
+impl Page47lock1lockNs {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page47lock1lockNs {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page47lock1lockNs {
+    #[inline(always)]
+    fn from(val: u8) -> Page47lock1lockNs {
+        Page47lock1lockNs::from_bits(val)
+    }
+}
+impl From<Page47lock1lockNs> for u8 {
+    #[inline(always)]
+    fn from(val: Page47lock1lockNs) -> u8 {
+        Page47lock1lockNs::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page47lock1lockS {
+    #[doc = "Page is fully accessible by Secure software."]
+    READ_WRITE = 0,
+    #[doc = "Page can be read by Secure software, but can not be written."]
+    READ_ONLY = 0x01,
+    #[doc = "Do not use. Behaves the same as INACCESSIBLE."]
+    RESERVED = 0x02,
+    #[doc = "Page can not be accessed by Secure software."]
+    INACCESSIBLE = 0x03,
+}
+impl Page47lock1lockS {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page47lock1lockS {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page47lock1lockS {
+    #[inline(always)]
+    fn from(val: u8) -> Page47lock1lockS {
+        Page47lock1lockS::from_bits(val)
+    }
+}
+impl From<Page47lock1lockS> for u8 {
+    #[inline(always)]
+    fn from(val: Page47lock1lockS) -> u8 {
+        Page47lock1lockS::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page48lock0noKeyState {
+    READ_ONLY = 0,
+    INACCESSIBLE = 0x01,
+}
+impl Page48lock0noKeyState {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page48lock0noKeyState {
+        unsafe { core::mem::transmute(val & 0x01) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page48lock0noKeyState {
+    #[inline(always)]
+    fn from(val: u8) -> Page48lock0noKeyState {
+        Page48lock0noKeyState::from_bits(val)
+    }
+}
+impl From<Page48lock0noKeyState> for u8 {
+    #[inline(always)]
+    fn from(val: Page48lock0noKeyState) -> u8 {
+        Page48lock0noKeyState::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page48lock1lockBl {
+    #[doc = "Bootloader permits user reads and writes to this page"]
+    READ_WRITE = 0,
+    #[doc = "Bootloader permits user reads of this page"]
+    READ_ONLY = 0x01,
+    #[doc = "Do not use. Behaves the same as INACCESSIBLE"]
+    RESERVED = 0x02,
+    #[doc = "Bootloader does not permit user access to this page"]
+    INACCESSIBLE = 0x03,
+}
+impl Page48lock1lockBl {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page48lock1lockBl {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page48lock1lockBl {
+    #[inline(always)]
+    fn from(val: u8) -> Page48lock1lockBl {
+        Page48lock1lockBl::from_bits(val)
+    }
+}
+impl From<Page48lock1lockBl> for u8 {
+    #[inline(always)]
+    fn from(val: Page48lock1lockBl) -> u8 {
+        Page48lock1lockBl::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page48lock1lockNs {
+    #[doc = "Page can be read by Non-secure software, and Secure software may permit Non-secure writes."]
+    READ_WRITE = 0,
+    #[doc = "Page can be read by Non-secure software"]
+    READ_ONLY = 0x01,
+    #[doc = "Do not use. Behaves the same as INACCESSIBLE."]
+    RESERVED = 0x02,
+    #[doc = "Page can not be accessed by Non-secure software."]
+    INACCESSIBLE = 0x03,
+}
+impl Page48lock1lockNs {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page48lock1lockNs {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page48lock1lockNs {
+    #[inline(always)]
+    fn from(val: u8) -> Page48lock1lockNs {
+        Page48lock1lockNs::from_bits(val)
+    }
+}
+impl From<Page48lock1lockNs> for u8 {
+    #[inline(always)]
+    fn from(val: Page48lock1lockNs) -> u8 {
+        Page48lock1lockNs::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page48lock1lockS {
+    #[doc = "Page is fully accessible by Secure software."]
+    READ_WRITE = 0,
+    #[doc = "Page can be read by Secure software, but can not be written."]
+    READ_ONLY = 0x01,
+    #[doc = "Do not use. Behaves the same as INACCESSIBLE."]
+    RESERVED = 0x02,
+    #[doc = "Page can not be accessed by Secure software."]
+    INACCESSIBLE = 0x03,
+}
+impl Page48lock1lockS {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page48lock1lockS {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page48lock1lockS {
+    #[inline(always)]
+    fn from(val: u8) -> Page48lock1lockS {
+        Page48lock1lockS::from_bits(val)
+    }
+}
+impl From<Page48lock1lockS> for u8 {
+    #[inline(always)]
+    fn from(val: Page48lock1lockS) -> u8 {
+        Page48lock1lockS::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page49lock0noKeyState {
+    READ_ONLY = 0,
+    INACCESSIBLE = 0x01,
+}
+impl Page49lock0noKeyState {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page49lock0noKeyState {
+        unsafe { core::mem::transmute(val & 0x01) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page49lock0noKeyState {
+    #[inline(always)]
+    fn from(val: u8) -> Page49lock0noKeyState {
+        Page49lock0noKeyState::from_bits(val)
+    }
+}
+impl From<Page49lock0noKeyState> for u8 {
+    #[inline(always)]
+    fn from(val: Page49lock0noKeyState) -> u8 {
+        Page49lock0noKeyState::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page49lock1lockBl {
+    #[doc = "Bootloader permits user reads and writes to this page"]
+    READ_WRITE = 0,
+    #[doc = "Bootloader permits user reads of this page"]
+    READ_ONLY = 0x01,
+    #[doc = "Do not use. Behaves the same as INACCESSIBLE"]
+    RESERVED = 0x02,
+    #[doc = "Bootloader does not permit user access to this page"]
+    INACCESSIBLE = 0x03,
+}
+impl Page49lock1lockBl {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page49lock1lockBl {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page49lock1lockBl {
+    #[inline(always)]
+    fn from(val: u8) -> Page49lock1lockBl {
+        Page49lock1lockBl::from_bits(val)
+    }
+}
+impl From<Page49lock1lockBl> for u8 {
+    #[inline(always)]
+    fn from(val: Page49lock1lockBl) -> u8 {
+        Page49lock1lockBl::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page49lock1lockNs {
+    #[doc = "Page can be read by Non-secure software, and Secure software may permit Non-secure writes."]
+    READ_WRITE = 0,
+    #[doc = "Page can be read by Non-secure software"]
+    READ_ONLY = 0x01,
+    #[doc = "Do not use. Behaves the same as INACCESSIBLE."]
+    RESERVED = 0x02,
+    #[doc = "Page can not be accessed by Non-secure software."]
+    INACCESSIBLE = 0x03,
+}
+impl Page49lock1lockNs {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page49lock1lockNs {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page49lock1lockNs {
+    #[inline(always)]
+    fn from(val: u8) -> Page49lock1lockNs {
+        Page49lock1lockNs::from_bits(val)
+    }
+}
+impl From<Page49lock1lockNs> for u8 {
+    #[inline(always)]
+    fn from(val: Page49lock1lockNs) -> u8 {
+        Page49lock1lockNs::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page49lock1lockS {
+    #[doc = "Page is fully accessible by Secure software."]
+    READ_WRITE = 0,
+    #[doc = "Page can be read by Secure software, but can not be written."]
+    READ_ONLY = 0x01,
+    #[doc = "Do not use. Behaves the same as INACCESSIBLE."]
+    RESERVED = 0x02,
+    #[doc = "Page can not be accessed by Secure software."]
+    INACCESSIBLE = 0x03,
+}
+impl Page49lock1lockS {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page49lock1lockS {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page49lock1lockS {
+    #[inline(always)]
+    fn from(val: u8) -> Page49lock1lockS {
+        Page49lock1lockS::from_bits(val)
+    }
+}
+impl From<Page49lock1lockS> for u8 {
+    #[inline(always)]
+    fn from(val: Page49lock1lockS) -> u8 {
+        Page49lock1lockS::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page4lock0noKeyState {
+    READ_ONLY = 0,
+    INACCESSIBLE = 0x01,
+}
+impl Page4lock0noKeyState {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page4lock0noKeyState {
+        unsafe { core::mem::transmute(val & 0x01) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page4lock0noKeyState {
+    #[inline(always)]
+    fn from(val: u8) -> Page4lock0noKeyState {
+        Page4lock0noKeyState::from_bits(val)
+    }
+}
+impl From<Page4lock0noKeyState> for u8 {
+    #[inline(always)]
+    fn from(val: Page4lock0noKeyState) -> u8 {
+        Page4lock0noKeyState::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page4lock1lockBl {
+    #[doc = "Bootloader permits user reads and writes to this page"]
+    READ_WRITE = 0,
+    #[doc = "Bootloader permits user reads of this page"]
+    READ_ONLY = 0x01,
+    #[doc = "Do not use. Behaves the same as INACCESSIBLE"]
+    RESERVED = 0x02,
+    #[doc = "Bootloader does not permit user access to this page"]
+    INACCESSIBLE = 0x03,
+}
+impl Page4lock1lockBl {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page4lock1lockBl {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page4lock1lockBl {
+    #[inline(always)]
+    fn from(val: u8) -> Page4lock1lockBl {
+        Page4lock1lockBl::from_bits(val)
+    }
+}
+impl From<Page4lock1lockBl> for u8 {
+    #[inline(always)]
+    fn from(val: Page4lock1lockBl) -> u8 {
+        Page4lock1lockBl::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page4lock1lockNs {
+    #[doc = "Page can be read by Non-secure software, and Secure software may permit Non-secure writes."]
+    READ_WRITE = 0,
+    #[doc = "Page can be read by Non-secure software"]
+    READ_ONLY = 0x01,
+    #[doc = "Do not use. Behaves the same as INACCESSIBLE."]
+    RESERVED = 0x02,
+    #[doc = "Page can not be accessed by Non-secure software."]
+    INACCESSIBLE = 0x03,
+}
+impl Page4lock1lockNs {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page4lock1lockNs {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page4lock1lockNs {
+    #[inline(always)]
+    fn from(val: u8) -> Page4lock1lockNs {
+        Page4lock1lockNs::from_bits(val)
+    }
+}
+impl From<Page4lock1lockNs> for u8 {
+    #[inline(always)]
+    fn from(val: Page4lock1lockNs) -> u8 {
+        Page4lock1lockNs::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page4lock1lockS {
+    #[doc = "Page is fully accessible by Secure software."]
+    READ_WRITE = 0,
+    #[doc = "Page can be read by Secure software, but can not be written."]
+    READ_ONLY = 0x01,
+    #[doc = "Do not use. Behaves the same as INACCESSIBLE."]
+    RESERVED = 0x02,
+    #[doc = "Page can not be accessed by Secure software."]
+    INACCESSIBLE = 0x03,
+}
+impl Page4lock1lockS {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page4lock1lockS {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page4lock1lockS {
+    #[inline(always)]
+    fn from(val: u8) -> Page4lock1lockS {
+        Page4lock1lockS::from_bits(val)
+    }
+}
+impl From<Page4lock1lockS> for u8 {
+    #[inline(always)]
+    fn from(val: Page4lock1lockS) -> u8 {
+        Page4lock1lockS::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page50lock0noKeyState {
+    READ_ONLY = 0,
+    INACCESSIBLE = 0x01,
+}
+impl Page50lock0noKeyState {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page50lock0noKeyState {
+        unsafe { core::mem::transmute(val & 0x01) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page50lock0noKeyState {
+    #[inline(always)]
+    fn from(val: u8) -> Page50lock0noKeyState {
+        Page50lock0noKeyState::from_bits(val)
+    }
+}
+impl From<Page50lock0noKeyState> for u8 {
+    #[inline(always)]
+    fn from(val: Page50lock0noKeyState) -> u8 {
+        Page50lock0noKeyState::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page50lock1lockBl {
+    #[doc = "Bootloader permits user reads and writes to this page"]
+    READ_WRITE = 0,
+    #[doc = "Bootloader permits user reads of this page"]
+    READ_ONLY = 0x01,
+    #[doc = "Do not use. Behaves the same as INACCESSIBLE"]
+    RESERVED = 0x02,
+    #[doc = "Bootloader does not permit user access to this page"]
+    INACCESSIBLE = 0x03,
+}
+impl Page50lock1lockBl {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page50lock1lockBl {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page50lock1lockBl {
+    #[inline(always)]
+    fn from(val: u8) -> Page50lock1lockBl {
+        Page50lock1lockBl::from_bits(val)
+    }
+}
+impl From<Page50lock1lockBl> for u8 {
+    #[inline(always)]
+    fn from(val: Page50lock1lockBl) -> u8 {
+        Page50lock1lockBl::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page50lock1lockNs {
+    #[doc = "Page can be read by Non-secure software, and Secure software may permit Non-secure writes."]
+    READ_WRITE = 0,
+    #[doc = "Page can be read by Non-secure software"]
+    READ_ONLY = 0x01,
+    #[doc = "Do not use. Behaves the same as INACCESSIBLE."]
+    RESERVED = 0x02,
+    #[doc = "Page can not be accessed by Non-secure software."]
+    INACCESSIBLE = 0x03,
+}
+impl Page50lock1lockNs {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page50lock1lockNs {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page50lock1lockNs {
+    #[inline(always)]
+    fn from(val: u8) -> Page50lock1lockNs {
+        Page50lock1lockNs::from_bits(val)
+    }
+}
+impl From<Page50lock1lockNs> for u8 {
+    #[inline(always)]
+    fn from(val: Page50lock1lockNs) -> u8 {
+        Page50lock1lockNs::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page50lock1lockS {
+    #[doc = "Page is fully accessible by Secure software."]
+    READ_WRITE = 0,
+    #[doc = "Page can be read by Secure software, but can not be written."]
+    READ_ONLY = 0x01,
+    #[doc = "Do not use. Behaves the same as INACCESSIBLE."]
+    RESERVED = 0x02,
+    #[doc = "Page can not be accessed by Secure software."]
+    INACCESSIBLE = 0x03,
+}
+impl Page50lock1lockS {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page50lock1lockS {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page50lock1lockS {
+    #[inline(always)]
+    fn from(val: u8) -> Page50lock1lockS {
+        Page50lock1lockS::from_bits(val)
+    }
+}
+impl From<Page50lock1lockS> for u8 {
+    #[inline(always)]
+    fn from(val: Page50lock1lockS) -> u8 {
+        Page50lock1lockS::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page51lock0noKeyState {
+    READ_ONLY = 0,
+    INACCESSIBLE = 0x01,
+}
+impl Page51lock0noKeyState {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page51lock0noKeyState {
+        unsafe { core::mem::transmute(val & 0x01) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page51lock0noKeyState {
+    #[inline(always)]
+    fn from(val: u8) -> Page51lock0noKeyState {
+        Page51lock0noKeyState::from_bits(val)
+    }
+}
+impl From<Page51lock0noKeyState> for u8 {
+    #[inline(always)]
+    fn from(val: Page51lock0noKeyState) -> u8 {
+        Page51lock0noKeyState::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page51lock1lockBl {
+    #[doc = "Bootloader permits user reads and writes to this page"]
+    READ_WRITE = 0,
+    #[doc = "Bootloader permits user reads of this page"]
+    READ_ONLY = 0x01,
+    #[doc = "Do not use. Behaves the same as INACCESSIBLE"]
+    RESERVED = 0x02,
+    #[doc = "Bootloader does not permit user access to this page"]
+    INACCESSIBLE = 0x03,
+}
+impl Page51lock1lockBl {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page51lock1lockBl {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page51lock1lockBl {
+    #[inline(always)]
+    fn from(val: u8) -> Page51lock1lockBl {
+        Page51lock1lockBl::from_bits(val)
+    }
+}
+impl From<Page51lock1lockBl> for u8 {
+    #[inline(always)]
+    fn from(val: Page51lock1lockBl) -> u8 {
+        Page51lock1lockBl::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page51lock1lockNs {
+    #[doc = "Page can be read by Non-secure software, and Secure software may permit Non-secure writes."]
+    READ_WRITE = 0,
+    #[doc = "Page can be read by Non-secure software"]
+    READ_ONLY = 0x01,
+    #[doc = "Do not use. Behaves the same as INACCESSIBLE."]
+    RESERVED = 0x02,
+    #[doc = "Page can not be accessed by Non-secure software."]
+    INACCESSIBLE = 0x03,
+}
+impl Page51lock1lockNs {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page51lock1lockNs {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page51lock1lockNs {
+    #[inline(always)]
+    fn from(val: u8) -> Page51lock1lockNs {
+        Page51lock1lockNs::from_bits(val)
+    }
+}
+impl From<Page51lock1lockNs> for u8 {
+    #[inline(always)]
+    fn from(val: Page51lock1lockNs) -> u8 {
+        Page51lock1lockNs::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page51lock1lockS {
+    #[doc = "Page is fully accessible by Secure software."]
+    READ_WRITE = 0,
+    #[doc = "Page can be read by Secure software, but can not be written."]
+    READ_ONLY = 0x01,
+    #[doc = "Do not use. Behaves the same as INACCESSIBLE."]
+    RESERVED = 0x02,
+    #[doc = "Page can not be accessed by Secure software."]
+    INACCESSIBLE = 0x03,
+}
+impl Page51lock1lockS {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page51lock1lockS {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page51lock1lockS {
+    #[inline(always)]
+    fn from(val: u8) -> Page51lock1lockS {
+        Page51lock1lockS::from_bits(val)
+    }
+}
+impl From<Page51lock1lockS> for u8 {
+    #[inline(always)]
+    fn from(val: Page51lock1lockS) -> u8 {
+        Page51lock1lockS::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page52lock0noKeyState {
+    READ_ONLY = 0,
+    INACCESSIBLE = 0x01,
+}
+impl Page52lock0noKeyState {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page52lock0noKeyState {
+        unsafe { core::mem::transmute(val & 0x01) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page52lock0noKeyState {
+    #[inline(always)]
+    fn from(val: u8) -> Page52lock0noKeyState {
+        Page52lock0noKeyState::from_bits(val)
+    }
+}
+impl From<Page52lock0noKeyState> for u8 {
+    #[inline(always)]
+    fn from(val: Page52lock0noKeyState) -> u8 {
+        Page52lock0noKeyState::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page52lock1lockBl {
+    #[doc = "Bootloader permits user reads and writes to this page"]
+    READ_WRITE = 0,
+    #[doc = "Bootloader permits user reads of this page"]
+    READ_ONLY = 0x01,
+    #[doc = "Do not use. Behaves the same as INACCESSIBLE"]
+    RESERVED = 0x02,
+    #[doc = "Bootloader does not permit user access to this page"]
+    INACCESSIBLE = 0x03,
+}
+impl Page52lock1lockBl {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page52lock1lockBl {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page52lock1lockBl {
+    #[inline(always)]
+    fn from(val: u8) -> Page52lock1lockBl {
+        Page52lock1lockBl::from_bits(val)
+    }
+}
+impl From<Page52lock1lockBl> for u8 {
+    #[inline(always)]
+    fn from(val: Page52lock1lockBl) -> u8 {
+        Page52lock1lockBl::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page52lock1lockNs {
+    #[doc = "Page can be read by Non-secure software, and Secure software may permit Non-secure writes."]
+    READ_WRITE = 0,
+    #[doc = "Page can be read by Non-secure software"]
+    READ_ONLY = 0x01,
+    #[doc = "Do not use. Behaves the same as INACCESSIBLE."]
+    RESERVED = 0x02,
+    #[doc = "Page can not be accessed by Non-secure software."]
+    INACCESSIBLE = 0x03,
+}
+impl Page52lock1lockNs {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page52lock1lockNs {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page52lock1lockNs {
+    #[inline(always)]
+    fn from(val: u8) -> Page52lock1lockNs {
+        Page52lock1lockNs::from_bits(val)
+    }
+}
+impl From<Page52lock1lockNs> for u8 {
+    #[inline(always)]
+    fn from(val: Page52lock1lockNs) -> u8 {
+        Page52lock1lockNs::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page52lock1lockS {
+    #[doc = "Page is fully accessible by Secure software."]
+    READ_WRITE = 0,
+    #[doc = "Page can be read by Secure software, but can not be written."]
+    READ_ONLY = 0x01,
+    #[doc = "Do not use. Behaves the same as INACCESSIBLE."]
+    RESERVED = 0x02,
+    #[doc = "Page can not be accessed by Secure software."]
+    INACCESSIBLE = 0x03,
+}
+impl Page52lock1lockS {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page52lock1lockS {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page52lock1lockS {
+    #[inline(always)]
+    fn from(val: u8) -> Page52lock1lockS {
+        Page52lock1lockS::from_bits(val)
+    }
+}
+impl From<Page52lock1lockS> for u8 {
+    #[inline(always)]
+    fn from(val: Page52lock1lockS) -> u8 {
+        Page52lock1lockS::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page53lock0noKeyState {
+    READ_ONLY = 0,
+    INACCESSIBLE = 0x01,
+}
+impl Page53lock0noKeyState {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page53lock0noKeyState {
+        unsafe { core::mem::transmute(val & 0x01) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page53lock0noKeyState {
+    #[inline(always)]
+    fn from(val: u8) -> Page53lock0noKeyState {
+        Page53lock0noKeyState::from_bits(val)
+    }
+}
+impl From<Page53lock0noKeyState> for u8 {
+    #[inline(always)]
+    fn from(val: Page53lock0noKeyState) -> u8 {
+        Page53lock0noKeyState::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page53lock1lockBl {
+    #[doc = "Bootloader permits user reads and writes to this page"]
+    READ_WRITE = 0,
+    #[doc = "Bootloader permits user reads of this page"]
+    READ_ONLY = 0x01,
+    #[doc = "Do not use. Behaves the same as INACCESSIBLE"]
+    RESERVED = 0x02,
+    #[doc = "Bootloader does not permit user access to this page"]
+    INACCESSIBLE = 0x03,
+}
+impl Page53lock1lockBl {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page53lock1lockBl {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page53lock1lockBl {
+    #[inline(always)]
+    fn from(val: u8) -> Page53lock1lockBl {
+        Page53lock1lockBl::from_bits(val)
+    }
+}
+impl From<Page53lock1lockBl> for u8 {
+    #[inline(always)]
+    fn from(val: Page53lock1lockBl) -> u8 {
+        Page53lock1lockBl::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page53lock1lockNs {
+    #[doc = "Page can be read by Non-secure software, and Secure software may permit Non-secure writes."]
+    READ_WRITE = 0,
+    #[doc = "Page can be read by Non-secure software"]
+    READ_ONLY = 0x01,
+    #[doc = "Do not use. Behaves the same as INACCESSIBLE."]
+    RESERVED = 0x02,
+    #[doc = "Page can not be accessed by Non-secure software."]
+    INACCESSIBLE = 0x03,
+}
+impl Page53lock1lockNs {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page53lock1lockNs {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page53lock1lockNs {
+    #[inline(always)]
+    fn from(val: u8) -> Page53lock1lockNs {
+        Page53lock1lockNs::from_bits(val)
+    }
+}
+impl From<Page53lock1lockNs> for u8 {
+    #[inline(always)]
+    fn from(val: Page53lock1lockNs) -> u8 {
+        Page53lock1lockNs::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page53lock1lockS {
+    #[doc = "Page is fully accessible by Secure software."]
+    READ_WRITE = 0,
+    #[doc = "Page can be read by Secure software, but can not be written."]
+    READ_ONLY = 0x01,
+    #[doc = "Do not use. Behaves the same as INACCESSIBLE."]
+    RESERVED = 0x02,
+    #[doc = "Page can not be accessed by Secure software."]
+    INACCESSIBLE = 0x03,
+}
+impl Page53lock1lockS {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page53lock1lockS {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page53lock1lockS {
+    #[inline(always)]
+    fn from(val: u8) -> Page53lock1lockS {
+        Page53lock1lockS::from_bits(val)
+    }
+}
+impl From<Page53lock1lockS> for u8 {
+    #[inline(always)]
+    fn from(val: Page53lock1lockS) -> u8 {
+        Page53lock1lockS::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page54lock0noKeyState {
+    READ_ONLY = 0,
+    INACCESSIBLE = 0x01,
+}
+impl Page54lock0noKeyState {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page54lock0noKeyState {
+        unsafe { core::mem::transmute(val & 0x01) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page54lock0noKeyState {
+    #[inline(always)]
+    fn from(val: u8) -> Page54lock0noKeyState {
+        Page54lock0noKeyState::from_bits(val)
+    }
+}
+impl From<Page54lock0noKeyState> for u8 {
+    #[inline(always)]
+    fn from(val: Page54lock0noKeyState) -> u8 {
+        Page54lock0noKeyState::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page54lock1lockBl {
+    #[doc = "Bootloader permits user reads and writes to this page"]
+    READ_WRITE = 0,
+    #[doc = "Bootloader permits user reads of this page"]
+    READ_ONLY = 0x01,
+    #[doc = "Do not use. Behaves the same as INACCESSIBLE"]
+    RESERVED = 0x02,
+    #[doc = "Bootloader does not permit user access to this page"]
+    INACCESSIBLE = 0x03,
+}
+impl Page54lock1lockBl {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page54lock1lockBl {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page54lock1lockBl {
+    #[inline(always)]
+    fn from(val: u8) -> Page54lock1lockBl {
+        Page54lock1lockBl::from_bits(val)
+    }
+}
+impl From<Page54lock1lockBl> for u8 {
+    #[inline(always)]
+    fn from(val: Page54lock1lockBl) -> u8 {
+        Page54lock1lockBl::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page54lock1lockNs {
+    #[doc = "Page can be read by Non-secure software, and Secure software may permit Non-secure writes."]
+    READ_WRITE = 0,
+    #[doc = "Page can be read by Non-secure software"]
+    READ_ONLY = 0x01,
+    #[doc = "Do not use. Behaves the same as INACCESSIBLE."]
+    RESERVED = 0x02,
+    #[doc = "Page can not be accessed by Non-secure software."]
+    INACCESSIBLE = 0x03,
+}
+impl Page54lock1lockNs {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page54lock1lockNs {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page54lock1lockNs {
+    #[inline(always)]
+    fn from(val: u8) -> Page54lock1lockNs {
+        Page54lock1lockNs::from_bits(val)
+    }
+}
+impl From<Page54lock1lockNs> for u8 {
+    #[inline(always)]
+    fn from(val: Page54lock1lockNs) -> u8 {
+        Page54lock1lockNs::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page54lock1lockS {
+    #[doc = "Page is fully accessible by Secure software."]
+    READ_WRITE = 0,
+    #[doc = "Page can be read by Secure software, but can not be written."]
+    READ_ONLY = 0x01,
+    #[doc = "Do not use. Behaves the same as INACCESSIBLE."]
+    RESERVED = 0x02,
+    #[doc = "Page can not be accessed by Secure software."]
+    INACCESSIBLE = 0x03,
+}
+impl Page54lock1lockS {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page54lock1lockS {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page54lock1lockS {
+    #[inline(always)]
+    fn from(val: u8) -> Page54lock1lockS {
+        Page54lock1lockS::from_bits(val)
+    }
+}
+impl From<Page54lock1lockS> for u8 {
+    #[inline(always)]
+    fn from(val: Page54lock1lockS) -> u8 {
+        Page54lock1lockS::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page55lock0noKeyState {
+    READ_ONLY = 0,
+    INACCESSIBLE = 0x01,
+}
+impl Page55lock0noKeyState {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page55lock0noKeyState {
+        unsafe { core::mem::transmute(val & 0x01) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page55lock0noKeyState {
+    #[inline(always)]
+    fn from(val: u8) -> Page55lock0noKeyState {
+        Page55lock0noKeyState::from_bits(val)
+    }
+}
+impl From<Page55lock0noKeyState> for u8 {
+    #[inline(always)]
+    fn from(val: Page55lock0noKeyState) -> u8 {
+        Page55lock0noKeyState::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page55lock1lockBl {
+    #[doc = "Bootloader permits user reads and writes to this page"]
+    READ_WRITE = 0,
+    #[doc = "Bootloader permits user reads of this page"]
+    READ_ONLY = 0x01,
+    #[doc = "Do not use. Behaves the same as INACCESSIBLE"]
+    RESERVED = 0x02,
+    #[doc = "Bootloader does not permit user access to this page"]
+    INACCESSIBLE = 0x03,
+}
+impl Page55lock1lockBl {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page55lock1lockBl {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page55lock1lockBl {
+    #[inline(always)]
+    fn from(val: u8) -> Page55lock1lockBl {
+        Page55lock1lockBl::from_bits(val)
+    }
+}
+impl From<Page55lock1lockBl> for u8 {
+    #[inline(always)]
+    fn from(val: Page55lock1lockBl) -> u8 {
+        Page55lock1lockBl::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page55lock1lockNs {
+    #[doc = "Page can be read by Non-secure software, and Secure software may permit Non-secure writes."]
+    READ_WRITE = 0,
+    #[doc = "Page can be read by Non-secure software"]
+    READ_ONLY = 0x01,
+    #[doc = "Do not use. Behaves the same as INACCESSIBLE."]
+    RESERVED = 0x02,
+    #[doc = "Page can not be accessed by Non-secure software."]
+    INACCESSIBLE = 0x03,
+}
+impl Page55lock1lockNs {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page55lock1lockNs {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page55lock1lockNs {
+    #[inline(always)]
+    fn from(val: u8) -> Page55lock1lockNs {
+        Page55lock1lockNs::from_bits(val)
+    }
+}
+impl From<Page55lock1lockNs> for u8 {
+    #[inline(always)]
+    fn from(val: Page55lock1lockNs) -> u8 {
+        Page55lock1lockNs::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page55lock1lockS {
+    #[doc = "Page is fully accessible by Secure software."]
+    READ_WRITE = 0,
+    #[doc = "Page can be read by Secure software, but can not be written."]
+    READ_ONLY = 0x01,
+    #[doc = "Do not use. Behaves the same as INACCESSIBLE."]
+    RESERVED = 0x02,
+    #[doc = "Page can not be accessed by Secure software."]
+    INACCESSIBLE = 0x03,
+}
+impl Page55lock1lockS {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page55lock1lockS {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page55lock1lockS {
+    #[inline(always)]
+    fn from(val: u8) -> Page55lock1lockS {
+        Page55lock1lockS::from_bits(val)
+    }
+}
+impl From<Page55lock1lockS> for u8 {
+    #[inline(always)]
+    fn from(val: Page55lock1lockS) -> u8 {
+        Page55lock1lockS::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page56lock0noKeyState {
+    READ_ONLY = 0,
+    INACCESSIBLE = 0x01,
+}
+impl Page56lock0noKeyState {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page56lock0noKeyState {
+        unsafe { core::mem::transmute(val & 0x01) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page56lock0noKeyState {
+    #[inline(always)]
+    fn from(val: u8) -> Page56lock0noKeyState {
+        Page56lock0noKeyState::from_bits(val)
+    }
+}
+impl From<Page56lock0noKeyState> for u8 {
+    #[inline(always)]
+    fn from(val: Page56lock0noKeyState) -> u8 {
+        Page56lock0noKeyState::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page56lock1lockBl {
+    #[doc = "Bootloader permits user reads and writes to this page"]
+    READ_WRITE = 0,
+    #[doc = "Bootloader permits user reads of this page"]
+    READ_ONLY = 0x01,
+    #[doc = "Do not use. Behaves the same as INACCESSIBLE"]
+    RESERVED = 0x02,
+    #[doc = "Bootloader does not permit user access to this page"]
+    INACCESSIBLE = 0x03,
+}
+impl Page56lock1lockBl {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page56lock1lockBl {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page56lock1lockBl {
+    #[inline(always)]
+    fn from(val: u8) -> Page56lock1lockBl {
+        Page56lock1lockBl::from_bits(val)
+    }
+}
+impl From<Page56lock1lockBl> for u8 {
+    #[inline(always)]
+    fn from(val: Page56lock1lockBl) -> u8 {
+        Page56lock1lockBl::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page56lock1lockNs {
+    #[doc = "Page can be read by Non-secure software, and Secure software may permit Non-secure writes."]
+    READ_WRITE = 0,
+    #[doc = "Page can be read by Non-secure software"]
+    READ_ONLY = 0x01,
+    #[doc = "Do not use. Behaves the same as INACCESSIBLE."]
+    RESERVED = 0x02,
+    #[doc = "Page can not be accessed by Non-secure software."]
+    INACCESSIBLE = 0x03,
+}
+impl Page56lock1lockNs {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page56lock1lockNs {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page56lock1lockNs {
+    #[inline(always)]
+    fn from(val: u8) -> Page56lock1lockNs {
+        Page56lock1lockNs::from_bits(val)
+    }
+}
+impl From<Page56lock1lockNs> for u8 {
+    #[inline(always)]
+    fn from(val: Page56lock1lockNs) -> u8 {
+        Page56lock1lockNs::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page56lock1lockS {
+    #[doc = "Page is fully accessible by Secure software."]
+    READ_WRITE = 0,
+    #[doc = "Page can be read by Secure software, but can not be written."]
+    READ_ONLY = 0x01,
+    #[doc = "Do not use. Behaves the same as INACCESSIBLE."]
+    RESERVED = 0x02,
+    #[doc = "Page can not be accessed by Secure software."]
+    INACCESSIBLE = 0x03,
+}
+impl Page56lock1lockS {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page56lock1lockS {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page56lock1lockS {
+    #[inline(always)]
+    fn from(val: u8) -> Page56lock1lockS {
+        Page56lock1lockS::from_bits(val)
+    }
+}
+impl From<Page56lock1lockS> for u8 {
+    #[inline(always)]
+    fn from(val: Page56lock1lockS) -> u8 {
+        Page56lock1lockS::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page57lock0noKeyState {
+    READ_ONLY = 0,
+    INACCESSIBLE = 0x01,
+}
+impl Page57lock0noKeyState {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page57lock0noKeyState {
+        unsafe { core::mem::transmute(val & 0x01) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page57lock0noKeyState {
+    #[inline(always)]
+    fn from(val: u8) -> Page57lock0noKeyState {
+        Page57lock0noKeyState::from_bits(val)
+    }
+}
+impl From<Page57lock0noKeyState> for u8 {
+    #[inline(always)]
+    fn from(val: Page57lock0noKeyState) -> u8 {
+        Page57lock0noKeyState::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page57lock1lockBl {
+    #[doc = "Bootloader permits user reads and writes to this page"]
+    READ_WRITE = 0,
+    #[doc = "Bootloader permits user reads of this page"]
+    READ_ONLY = 0x01,
+    #[doc = "Do not use. Behaves the same as INACCESSIBLE"]
+    RESERVED = 0x02,
+    #[doc = "Bootloader does not permit user access to this page"]
+    INACCESSIBLE = 0x03,
+}
+impl Page57lock1lockBl {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page57lock1lockBl {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page57lock1lockBl {
+    #[inline(always)]
+    fn from(val: u8) -> Page57lock1lockBl {
+        Page57lock1lockBl::from_bits(val)
+    }
+}
+impl From<Page57lock1lockBl> for u8 {
+    #[inline(always)]
+    fn from(val: Page57lock1lockBl) -> u8 {
+        Page57lock1lockBl::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page57lock1lockNs {
+    #[doc = "Page can be read by Non-secure software, and Secure software may permit Non-secure writes."]
+    READ_WRITE = 0,
+    #[doc = "Page can be read by Non-secure software"]
+    READ_ONLY = 0x01,
+    #[doc = "Do not use. Behaves the same as INACCESSIBLE."]
+    RESERVED = 0x02,
+    #[doc = "Page can not be accessed by Non-secure software."]
+    INACCESSIBLE = 0x03,
+}
+impl Page57lock1lockNs {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page57lock1lockNs {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page57lock1lockNs {
+    #[inline(always)]
+    fn from(val: u8) -> Page57lock1lockNs {
+        Page57lock1lockNs::from_bits(val)
+    }
+}
+impl From<Page57lock1lockNs> for u8 {
+    #[inline(always)]
+    fn from(val: Page57lock1lockNs) -> u8 {
+        Page57lock1lockNs::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page57lock1lockS {
+    #[doc = "Page is fully accessible by Secure software."]
+    READ_WRITE = 0,
+    #[doc = "Page can be read by Secure software, but can not be written."]
+    READ_ONLY = 0x01,
+    #[doc = "Do not use. Behaves the same as INACCESSIBLE."]
+    RESERVED = 0x02,
+    #[doc = "Page can not be accessed by Secure software."]
+    INACCESSIBLE = 0x03,
+}
+impl Page57lock1lockS {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page57lock1lockS {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page57lock1lockS {
+    #[inline(always)]
+    fn from(val: u8) -> Page57lock1lockS {
+        Page57lock1lockS::from_bits(val)
+    }
+}
+impl From<Page57lock1lockS> for u8 {
+    #[inline(always)]
+    fn from(val: Page57lock1lockS) -> u8 {
+        Page57lock1lockS::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page58lock0noKeyState {
+    READ_ONLY = 0,
+    INACCESSIBLE = 0x01,
+}
+impl Page58lock0noKeyState {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page58lock0noKeyState {
+        unsafe { core::mem::transmute(val & 0x01) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page58lock0noKeyState {
+    #[inline(always)]
+    fn from(val: u8) -> Page58lock0noKeyState {
+        Page58lock0noKeyState::from_bits(val)
+    }
+}
+impl From<Page58lock0noKeyState> for u8 {
+    #[inline(always)]
+    fn from(val: Page58lock0noKeyState) -> u8 {
+        Page58lock0noKeyState::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page58lock1lockBl {
+    #[doc = "Bootloader permits user reads and writes to this page"]
+    READ_WRITE = 0,
+    #[doc = "Bootloader permits user reads of this page"]
+    READ_ONLY = 0x01,
+    #[doc = "Do not use. Behaves the same as INACCESSIBLE"]
+    RESERVED = 0x02,
+    #[doc = "Bootloader does not permit user access to this page"]
+    INACCESSIBLE = 0x03,
+}
+impl Page58lock1lockBl {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page58lock1lockBl {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page58lock1lockBl {
+    #[inline(always)]
+    fn from(val: u8) -> Page58lock1lockBl {
+        Page58lock1lockBl::from_bits(val)
+    }
+}
+impl From<Page58lock1lockBl> for u8 {
+    #[inline(always)]
+    fn from(val: Page58lock1lockBl) -> u8 {
+        Page58lock1lockBl::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page58lock1lockNs {
+    #[doc = "Page can be read by Non-secure software, and Secure software may permit Non-secure writes."]
+    READ_WRITE = 0,
+    #[doc = "Page can be read by Non-secure software"]
+    READ_ONLY = 0x01,
+    #[doc = "Do not use. Behaves the same as INACCESSIBLE."]
+    RESERVED = 0x02,
+    #[doc = "Page can not be accessed by Non-secure software."]
+    INACCESSIBLE = 0x03,
+}
+impl Page58lock1lockNs {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page58lock1lockNs {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page58lock1lockNs {
+    #[inline(always)]
+    fn from(val: u8) -> Page58lock1lockNs {
+        Page58lock1lockNs::from_bits(val)
+    }
+}
+impl From<Page58lock1lockNs> for u8 {
+    #[inline(always)]
+    fn from(val: Page58lock1lockNs) -> u8 {
+        Page58lock1lockNs::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page58lock1lockS {
+    #[doc = "Page is fully accessible by Secure software."]
+    READ_WRITE = 0,
+    #[doc = "Page can be read by Secure software, but can not be written."]
+    READ_ONLY = 0x01,
+    #[doc = "Do not use. Behaves the same as INACCESSIBLE."]
+    RESERVED = 0x02,
+    #[doc = "Page can not be accessed by Secure software."]
+    INACCESSIBLE = 0x03,
+}
+impl Page58lock1lockS {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page58lock1lockS {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page58lock1lockS {
+    #[inline(always)]
+    fn from(val: u8) -> Page58lock1lockS {
+        Page58lock1lockS::from_bits(val)
+    }
+}
+impl From<Page58lock1lockS> for u8 {
+    #[inline(always)]
+    fn from(val: Page58lock1lockS) -> u8 {
+        Page58lock1lockS::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page59lock0noKeyState {
+    READ_ONLY = 0,
+    INACCESSIBLE = 0x01,
+}
+impl Page59lock0noKeyState {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page59lock0noKeyState {
+        unsafe { core::mem::transmute(val & 0x01) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page59lock0noKeyState {
+    #[inline(always)]
+    fn from(val: u8) -> Page59lock0noKeyState {
+        Page59lock0noKeyState::from_bits(val)
+    }
+}
+impl From<Page59lock0noKeyState> for u8 {
+    #[inline(always)]
+    fn from(val: Page59lock0noKeyState) -> u8 {
+        Page59lock0noKeyState::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page59lock1lockBl {
+    #[doc = "Bootloader permits user reads and writes to this page"]
+    READ_WRITE = 0,
+    #[doc = "Bootloader permits user reads of this page"]
+    READ_ONLY = 0x01,
+    #[doc = "Do not use. Behaves the same as INACCESSIBLE"]
+    RESERVED = 0x02,
+    #[doc = "Bootloader does not permit user access to this page"]
+    INACCESSIBLE = 0x03,
+}
+impl Page59lock1lockBl {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page59lock1lockBl {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page59lock1lockBl {
+    #[inline(always)]
+    fn from(val: u8) -> Page59lock1lockBl {
+        Page59lock1lockBl::from_bits(val)
+    }
+}
+impl From<Page59lock1lockBl> for u8 {
+    #[inline(always)]
+    fn from(val: Page59lock1lockBl) -> u8 {
+        Page59lock1lockBl::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page59lock1lockNs {
+    #[doc = "Page can be read by Non-secure software, and Secure software may permit Non-secure writes."]
+    READ_WRITE = 0,
+    #[doc = "Page can be read by Non-secure software"]
+    READ_ONLY = 0x01,
+    #[doc = "Do not use. Behaves the same as INACCESSIBLE."]
+    RESERVED = 0x02,
+    #[doc = "Page can not be accessed by Non-secure software."]
+    INACCESSIBLE = 0x03,
+}
+impl Page59lock1lockNs {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page59lock1lockNs {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page59lock1lockNs {
+    #[inline(always)]
+    fn from(val: u8) -> Page59lock1lockNs {
+        Page59lock1lockNs::from_bits(val)
+    }
+}
+impl From<Page59lock1lockNs> for u8 {
+    #[inline(always)]
+    fn from(val: Page59lock1lockNs) -> u8 {
+        Page59lock1lockNs::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page59lock1lockS {
+    #[doc = "Page is fully accessible by Secure software."]
+    READ_WRITE = 0,
+    #[doc = "Page can be read by Secure software, but can not be written."]
+    READ_ONLY = 0x01,
+    #[doc = "Do not use. Behaves the same as INACCESSIBLE."]
+    RESERVED = 0x02,
+    #[doc = "Page can not be accessed by Secure software."]
+    INACCESSIBLE = 0x03,
+}
+impl Page59lock1lockS {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page59lock1lockS {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page59lock1lockS {
+    #[inline(always)]
+    fn from(val: u8) -> Page59lock1lockS {
+        Page59lock1lockS::from_bits(val)
+    }
+}
+impl From<Page59lock1lockS> for u8 {
+    #[inline(always)]
+    fn from(val: Page59lock1lockS) -> u8 {
+        Page59lock1lockS::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page5lock0noKeyState {
+    READ_ONLY = 0,
+    INACCESSIBLE = 0x01,
+}
+impl Page5lock0noKeyState {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page5lock0noKeyState {
+        unsafe { core::mem::transmute(val & 0x01) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page5lock0noKeyState {
+    #[inline(always)]
+    fn from(val: u8) -> Page5lock0noKeyState {
+        Page5lock0noKeyState::from_bits(val)
+    }
+}
+impl From<Page5lock0noKeyState> for u8 {
+    #[inline(always)]
+    fn from(val: Page5lock0noKeyState) -> u8 {
+        Page5lock0noKeyState::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page5lock1lockBl {
+    #[doc = "Bootloader permits user reads and writes to this page"]
+    READ_WRITE = 0,
+    #[doc = "Bootloader permits user reads of this page"]
+    READ_ONLY = 0x01,
+    #[doc = "Do not use. Behaves the same as INACCESSIBLE"]
+    RESERVED = 0x02,
+    #[doc = "Bootloader does not permit user access to this page"]
+    INACCESSIBLE = 0x03,
+}
+impl Page5lock1lockBl {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page5lock1lockBl {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page5lock1lockBl {
+    #[inline(always)]
+    fn from(val: u8) -> Page5lock1lockBl {
+        Page5lock1lockBl::from_bits(val)
+    }
+}
+impl From<Page5lock1lockBl> for u8 {
+    #[inline(always)]
+    fn from(val: Page5lock1lockBl) -> u8 {
+        Page5lock1lockBl::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page5lock1lockNs {
+    #[doc = "Page can be read by Non-secure software, and Secure software may permit Non-secure writes."]
+    READ_WRITE = 0,
+    #[doc = "Page can be read by Non-secure software"]
+    READ_ONLY = 0x01,
+    #[doc = "Do not use. Behaves the same as INACCESSIBLE."]
+    RESERVED = 0x02,
+    #[doc = "Page can not be accessed by Non-secure software."]
+    INACCESSIBLE = 0x03,
+}
+impl Page5lock1lockNs {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page5lock1lockNs {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page5lock1lockNs {
+    #[inline(always)]
+    fn from(val: u8) -> Page5lock1lockNs {
+        Page5lock1lockNs::from_bits(val)
+    }
+}
+impl From<Page5lock1lockNs> for u8 {
+    #[inline(always)]
+    fn from(val: Page5lock1lockNs) -> u8 {
+        Page5lock1lockNs::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page5lock1lockS {
+    #[doc = "Page is fully accessible by Secure software."]
+    READ_WRITE = 0,
+    #[doc = "Page can be read by Secure software, but can not be written."]
+    READ_ONLY = 0x01,
+    #[doc = "Do not use. Behaves the same as INACCESSIBLE."]
+    RESERVED = 0x02,
+    #[doc = "Page can not be accessed by Secure software."]
+    INACCESSIBLE = 0x03,
+}
+impl Page5lock1lockS {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page5lock1lockS {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page5lock1lockS {
+    #[inline(always)]
+    fn from(val: u8) -> Page5lock1lockS {
+        Page5lock1lockS::from_bits(val)
+    }
+}
+impl From<Page5lock1lockS> for u8 {
+    #[inline(always)]
+    fn from(val: Page5lock1lockS) -> u8 {
+        Page5lock1lockS::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page60lock0noKeyState {
+    READ_ONLY = 0,
+    INACCESSIBLE = 0x01,
+}
+impl Page60lock0noKeyState {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page60lock0noKeyState {
+        unsafe { core::mem::transmute(val & 0x01) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page60lock0noKeyState {
+    #[inline(always)]
+    fn from(val: u8) -> Page60lock0noKeyState {
+        Page60lock0noKeyState::from_bits(val)
+    }
+}
+impl From<Page60lock0noKeyState> for u8 {
+    #[inline(always)]
+    fn from(val: Page60lock0noKeyState) -> u8 {
+        Page60lock0noKeyState::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page60lock1lockBl {
+    #[doc = "Bootloader permits user reads and writes to this page"]
+    READ_WRITE = 0,
+    #[doc = "Bootloader permits user reads of this page"]
+    READ_ONLY = 0x01,
+    #[doc = "Do not use. Behaves the same as INACCESSIBLE"]
+    RESERVED = 0x02,
+    #[doc = "Bootloader does not permit user access to this page"]
+    INACCESSIBLE = 0x03,
+}
+impl Page60lock1lockBl {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page60lock1lockBl {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page60lock1lockBl {
+    #[inline(always)]
+    fn from(val: u8) -> Page60lock1lockBl {
+        Page60lock1lockBl::from_bits(val)
+    }
+}
+impl From<Page60lock1lockBl> for u8 {
+    #[inline(always)]
+    fn from(val: Page60lock1lockBl) -> u8 {
+        Page60lock1lockBl::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page60lock1lockNs {
+    #[doc = "Page can be read by Non-secure software, and Secure software may permit Non-secure writes."]
+    READ_WRITE = 0,
+    #[doc = "Page can be read by Non-secure software"]
+    READ_ONLY = 0x01,
+    #[doc = "Do not use. Behaves the same as INACCESSIBLE."]
+    RESERVED = 0x02,
+    #[doc = "Page can not be accessed by Non-secure software."]
+    INACCESSIBLE = 0x03,
+}
+impl Page60lock1lockNs {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page60lock1lockNs {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page60lock1lockNs {
+    #[inline(always)]
+    fn from(val: u8) -> Page60lock1lockNs {
+        Page60lock1lockNs::from_bits(val)
+    }
+}
+impl From<Page60lock1lockNs> for u8 {
+    #[inline(always)]
+    fn from(val: Page60lock1lockNs) -> u8 {
+        Page60lock1lockNs::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page60lock1lockS {
+    #[doc = "Page is fully accessible by Secure software."]
+    READ_WRITE = 0,
+    #[doc = "Page can be read by Secure software, but can not be written."]
+    READ_ONLY = 0x01,
+    #[doc = "Do not use. Behaves the same as INACCESSIBLE."]
+    RESERVED = 0x02,
+    #[doc = "Page can not be accessed by Secure software."]
+    INACCESSIBLE = 0x03,
+}
+impl Page60lock1lockS {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page60lock1lockS {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page60lock1lockS {
+    #[inline(always)]
+    fn from(val: u8) -> Page60lock1lockS {
+        Page60lock1lockS::from_bits(val)
+    }
+}
+impl From<Page60lock1lockS> for u8 {
+    #[inline(always)]
+    fn from(val: Page60lock1lockS) -> u8 {
+        Page60lock1lockS::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page61lock0noKeyState {
+    READ_ONLY = 0,
+    INACCESSIBLE = 0x01,
+}
+impl Page61lock0noKeyState {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page61lock0noKeyState {
+        unsafe { core::mem::transmute(val & 0x01) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page61lock0noKeyState {
+    #[inline(always)]
+    fn from(val: u8) -> Page61lock0noKeyState {
+        Page61lock0noKeyState::from_bits(val)
+    }
+}
+impl From<Page61lock0noKeyState> for u8 {
+    #[inline(always)]
+    fn from(val: Page61lock0noKeyState) -> u8 {
+        Page61lock0noKeyState::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page61lock1lockBl {
+    #[doc = "Bootloader permits user reads and writes to this page"]
+    READ_WRITE = 0,
+    #[doc = "Bootloader permits user reads of this page"]
+    READ_ONLY = 0x01,
+    #[doc = "Do not use. Behaves the same as INACCESSIBLE"]
+    RESERVED = 0x02,
+    #[doc = "Bootloader does not permit user access to this page"]
+    INACCESSIBLE = 0x03,
+}
+impl Page61lock1lockBl {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page61lock1lockBl {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page61lock1lockBl {
+    #[inline(always)]
+    fn from(val: u8) -> Page61lock1lockBl {
+        Page61lock1lockBl::from_bits(val)
+    }
+}
+impl From<Page61lock1lockBl> for u8 {
+    #[inline(always)]
+    fn from(val: Page61lock1lockBl) -> u8 {
+        Page61lock1lockBl::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page61lock1lockNs {
+    #[doc = "Page can be read by Non-secure software, and Secure software may permit Non-secure writes."]
+    READ_WRITE = 0,
+    #[doc = "Page can be read by Non-secure software"]
+    READ_ONLY = 0x01,
+    #[doc = "Do not use. Behaves the same as INACCESSIBLE."]
+    RESERVED = 0x02,
+    #[doc = "Page can not be accessed by Non-secure software."]
+    INACCESSIBLE = 0x03,
+}
+impl Page61lock1lockNs {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page61lock1lockNs {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page61lock1lockNs {
+    #[inline(always)]
+    fn from(val: u8) -> Page61lock1lockNs {
+        Page61lock1lockNs::from_bits(val)
+    }
+}
+impl From<Page61lock1lockNs> for u8 {
+    #[inline(always)]
+    fn from(val: Page61lock1lockNs) -> u8 {
+        Page61lock1lockNs::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page61lock1lockS {
+    #[doc = "Page is fully accessible by Secure software."]
+    READ_WRITE = 0,
+    #[doc = "Page can be read by Secure software, but can not be written."]
+    READ_ONLY = 0x01,
+    #[doc = "Do not use. Behaves the same as INACCESSIBLE."]
+    RESERVED = 0x02,
+    #[doc = "Page can not be accessed by Secure software."]
+    INACCESSIBLE = 0x03,
+}
+impl Page61lock1lockS {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page61lock1lockS {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page61lock1lockS {
+    #[inline(always)]
+    fn from(val: u8) -> Page61lock1lockS {
+        Page61lock1lockS::from_bits(val)
+    }
+}
+impl From<Page61lock1lockS> for u8 {
+    #[inline(always)]
+    fn from(val: Page61lock1lockS) -> u8 {
+        Page61lock1lockS::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page62lock0noKeyState {
+    READ_ONLY = 0,
+    INACCESSIBLE = 0x01,
+}
+impl Page62lock0noKeyState {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page62lock0noKeyState {
+        unsafe { core::mem::transmute(val & 0x01) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page62lock0noKeyState {
+    #[inline(always)]
+    fn from(val: u8) -> Page62lock0noKeyState {
+        Page62lock0noKeyState::from_bits(val)
+    }
+}
+impl From<Page62lock0noKeyState> for u8 {
+    #[inline(always)]
+    fn from(val: Page62lock0noKeyState) -> u8 {
+        Page62lock0noKeyState::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page62lock1lockBl {
+    #[doc = "Bootloader permits user reads and writes to this page"]
+    READ_WRITE = 0,
+    #[doc = "Bootloader permits user reads of this page"]
+    READ_ONLY = 0x01,
+    #[doc = "Do not use. Behaves the same as INACCESSIBLE"]
+    RESERVED = 0x02,
+    #[doc = "Bootloader does not permit user access to this page"]
+    INACCESSIBLE = 0x03,
+}
+impl Page62lock1lockBl {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page62lock1lockBl {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page62lock1lockBl {
+    #[inline(always)]
+    fn from(val: u8) -> Page62lock1lockBl {
+        Page62lock1lockBl::from_bits(val)
+    }
+}
+impl From<Page62lock1lockBl> for u8 {
+    #[inline(always)]
+    fn from(val: Page62lock1lockBl) -> u8 {
+        Page62lock1lockBl::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page62lock1lockNs {
+    #[doc = "Page can be read by Non-secure software, and Secure software may permit Non-secure writes."]
+    READ_WRITE = 0,
+    #[doc = "Page can be read by Non-secure software"]
+    READ_ONLY = 0x01,
+    #[doc = "Do not use. Behaves the same as INACCESSIBLE."]
+    RESERVED = 0x02,
+    #[doc = "Page can not be accessed by Non-secure software."]
+    INACCESSIBLE = 0x03,
+}
+impl Page62lock1lockNs {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page62lock1lockNs {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page62lock1lockNs {
+    #[inline(always)]
+    fn from(val: u8) -> Page62lock1lockNs {
+        Page62lock1lockNs::from_bits(val)
+    }
+}
+impl From<Page62lock1lockNs> for u8 {
+    #[inline(always)]
+    fn from(val: Page62lock1lockNs) -> u8 {
+        Page62lock1lockNs::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page62lock1lockS {
+    #[doc = "Page is fully accessible by Secure software."]
+    READ_WRITE = 0,
+    #[doc = "Page can be read by Secure software, but can not be written."]
+    READ_ONLY = 0x01,
+    #[doc = "Do not use. Behaves the same as INACCESSIBLE."]
+    RESERVED = 0x02,
+    #[doc = "Page can not be accessed by Secure software."]
+    INACCESSIBLE = 0x03,
+}
+impl Page62lock1lockS {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page62lock1lockS {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page62lock1lockS {
+    #[inline(always)]
+    fn from(val: u8) -> Page62lock1lockS {
+        Page62lock1lockS::from_bits(val)
+    }
+}
+impl From<Page62lock1lockS> for u8 {
+    #[inline(always)]
+    fn from(val: Page62lock1lockS) -> u8 {
+        Page62lock1lockS::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page63lock0noKeyState {
+    READ_ONLY = 0,
+    INACCESSIBLE = 0x01,
+}
+impl Page63lock0noKeyState {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page63lock0noKeyState {
+        unsafe { core::mem::transmute(val & 0x01) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page63lock0noKeyState {
+    #[inline(always)]
+    fn from(val: u8) -> Page63lock0noKeyState {
+        Page63lock0noKeyState::from_bits(val)
+    }
+}
+impl From<Page63lock0noKeyState> for u8 {
+    #[inline(always)]
+    fn from(val: Page63lock0noKeyState) -> u8 {
+        Page63lock0noKeyState::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page63lock1lockBl {
+    #[doc = "Bootloader permits user reads and writes to this page"]
+    READ_WRITE = 0,
+    #[doc = "Bootloader permits user reads of this page"]
+    READ_ONLY = 0x01,
+    #[doc = "Do not use. Behaves the same as INACCESSIBLE"]
+    RESERVED = 0x02,
+    #[doc = "Bootloader does not permit user access to this page"]
+    INACCESSIBLE = 0x03,
+}
+impl Page63lock1lockBl {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page63lock1lockBl {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page63lock1lockBl {
+    #[inline(always)]
+    fn from(val: u8) -> Page63lock1lockBl {
+        Page63lock1lockBl::from_bits(val)
+    }
+}
+impl From<Page63lock1lockBl> for u8 {
+    #[inline(always)]
+    fn from(val: Page63lock1lockBl) -> u8 {
+        Page63lock1lockBl::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page63lock1lockNs {
+    #[doc = "Page can be read by Non-secure software, and Secure software may permit Non-secure writes."]
+    READ_WRITE = 0,
+    #[doc = "Page can be read by Non-secure software"]
+    READ_ONLY = 0x01,
+    #[doc = "Do not use. Behaves the same as INACCESSIBLE."]
+    RESERVED = 0x02,
+    #[doc = "Page can not be accessed by Non-secure software."]
+    INACCESSIBLE = 0x03,
+}
+impl Page63lock1lockNs {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page63lock1lockNs {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page63lock1lockNs {
+    #[inline(always)]
+    fn from(val: u8) -> Page63lock1lockNs {
+        Page63lock1lockNs::from_bits(val)
+    }
+}
+impl From<Page63lock1lockNs> for u8 {
+    #[inline(always)]
+    fn from(val: Page63lock1lockNs) -> u8 {
+        Page63lock1lockNs::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page63lock1lockS {
+    #[doc = "Page is fully accessible by Secure software."]
+    READ_WRITE = 0,
+    #[doc = "Page can be read by Secure software, but can not be written."]
+    READ_ONLY = 0x01,
+    #[doc = "Do not use. Behaves the same as INACCESSIBLE."]
+    RESERVED = 0x02,
+    #[doc = "Page can not be accessed by Secure software."]
+    INACCESSIBLE = 0x03,
+}
+impl Page63lock1lockS {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page63lock1lockS {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page63lock1lockS {
+    #[inline(always)]
+    fn from(val: u8) -> Page63lock1lockS {
+        Page63lock1lockS::from_bits(val)
+    }
+}
+impl From<Page63lock1lockS> for u8 {
+    #[inline(always)]
+    fn from(val: Page63lock1lockS) -> u8 {
+        Page63lock1lockS::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page6lock0noKeyState {
+    READ_ONLY = 0,
+    INACCESSIBLE = 0x01,
+}
+impl Page6lock0noKeyState {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page6lock0noKeyState {
+        unsafe { core::mem::transmute(val & 0x01) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page6lock0noKeyState {
+    #[inline(always)]
+    fn from(val: u8) -> Page6lock0noKeyState {
+        Page6lock0noKeyState::from_bits(val)
+    }
+}
+impl From<Page6lock0noKeyState> for u8 {
+    #[inline(always)]
+    fn from(val: Page6lock0noKeyState) -> u8 {
+        Page6lock0noKeyState::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page6lock1lockBl {
+    #[doc = "Bootloader permits user reads and writes to this page"]
+    READ_WRITE = 0,
+    #[doc = "Bootloader permits user reads of this page"]
+    READ_ONLY = 0x01,
+    #[doc = "Do not use. Behaves the same as INACCESSIBLE"]
+    RESERVED = 0x02,
+    #[doc = "Bootloader does not permit user access to this page"]
+    INACCESSIBLE = 0x03,
+}
+impl Page6lock1lockBl {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page6lock1lockBl {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page6lock1lockBl {
+    #[inline(always)]
+    fn from(val: u8) -> Page6lock1lockBl {
+        Page6lock1lockBl::from_bits(val)
+    }
+}
+impl From<Page6lock1lockBl> for u8 {
+    #[inline(always)]
+    fn from(val: Page6lock1lockBl) -> u8 {
+        Page6lock1lockBl::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page6lock1lockNs {
+    #[doc = "Page can be read by Non-secure software, and Secure software may permit Non-secure writes."]
+    READ_WRITE = 0,
+    #[doc = "Page can be read by Non-secure software"]
+    READ_ONLY = 0x01,
+    #[doc = "Do not use. Behaves the same as INACCESSIBLE."]
+    RESERVED = 0x02,
+    #[doc = "Page can not be accessed by Non-secure software."]
+    INACCESSIBLE = 0x03,
+}
+impl Page6lock1lockNs {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page6lock1lockNs {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page6lock1lockNs {
+    #[inline(always)]
+    fn from(val: u8) -> Page6lock1lockNs {
+        Page6lock1lockNs::from_bits(val)
+    }
+}
+impl From<Page6lock1lockNs> for u8 {
+    #[inline(always)]
+    fn from(val: Page6lock1lockNs) -> u8 {
+        Page6lock1lockNs::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page6lock1lockS {
+    #[doc = "Page is fully accessible by Secure software."]
+    READ_WRITE = 0,
+    #[doc = "Page can be read by Secure software, but can not be written."]
+    READ_ONLY = 0x01,
+    #[doc = "Do not use. Behaves the same as INACCESSIBLE."]
+    RESERVED = 0x02,
+    #[doc = "Page can not be accessed by Secure software."]
+    INACCESSIBLE = 0x03,
+}
+impl Page6lock1lockS {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page6lock1lockS {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page6lock1lockS {
+    #[inline(always)]
+    fn from(val: u8) -> Page6lock1lockS {
+        Page6lock1lockS::from_bits(val)
+    }
+}
+impl From<Page6lock1lockS> for u8 {
+    #[inline(always)]
+    fn from(val: Page6lock1lockS) -> u8 {
+        Page6lock1lockS::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page7lock0noKeyState {
+    READ_ONLY = 0,
+    INACCESSIBLE = 0x01,
+}
+impl Page7lock0noKeyState {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page7lock0noKeyState {
+        unsafe { core::mem::transmute(val & 0x01) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page7lock0noKeyState {
+    #[inline(always)]
+    fn from(val: u8) -> Page7lock0noKeyState {
+        Page7lock0noKeyState::from_bits(val)
+    }
+}
+impl From<Page7lock0noKeyState> for u8 {
+    #[inline(always)]
+    fn from(val: Page7lock0noKeyState) -> u8 {
+        Page7lock0noKeyState::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page7lock1lockBl {
+    #[doc = "Bootloader permits user reads and writes to this page"]
+    READ_WRITE = 0,
+    #[doc = "Bootloader permits user reads of this page"]
+    READ_ONLY = 0x01,
+    #[doc = "Do not use. Behaves the same as INACCESSIBLE"]
+    RESERVED = 0x02,
+    #[doc = "Bootloader does not permit user access to this page"]
+    INACCESSIBLE = 0x03,
+}
+impl Page7lock1lockBl {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page7lock1lockBl {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page7lock1lockBl {
+    #[inline(always)]
+    fn from(val: u8) -> Page7lock1lockBl {
+        Page7lock1lockBl::from_bits(val)
+    }
+}
+impl From<Page7lock1lockBl> for u8 {
+    #[inline(always)]
+    fn from(val: Page7lock1lockBl) -> u8 {
+        Page7lock1lockBl::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page7lock1lockNs {
+    #[doc = "Page can be read by Non-secure software, and Secure software may permit Non-secure writes."]
+    READ_WRITE = 0,
+    #[doc = "Page can be read by Non-secure software"]
+    READ_ONLY = 0x01,
+    #[doc = "Do not use. Behaves the same as INACCESSIBLE."]
+    RESERVED = 0x02,
+    #[doc = "Page can not be accessed by Non-secure software."]
+    INACCESSIBLE = 0x03,
+}
+impl Page7lock1lockNs {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page7lock1lockNs {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page7lock1lockNs {
+    #[inline(always)]
+    fn from(val: u8) -> Page7lock1lockNs {
+        Page7lock1lockNs::from_bits(val)
+    }
+}
+impl From<Page7lock1lockNs> for u8 {
+    #[inline(always)]
+    fn from(val: Page7lock1lockNs) -> u8 {
+        Page7lock1lockNs::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page7lock1lockS {
+    #[doc = "Page is fully accessible by Secure software."]
+    READ_WRITE = 0,
+    #[doc = "Page can be read by Secure software, but can not be written."]
+    READ_ONLY = 0x01,
+    #[doc = "Do not use. Behaves the same as INACCESSIBLE."]
+    RESERVED = 0x02,
+    #[doc = "Page can not be accessed by Secure software."]
+    INACCESSIBLE = 0x03,
+}
+impl Page7lock1lockS {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page7lock1lockS {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page7lock1lockS {
+    #[inline(always)]
+    fn from(val: u8) -> Page7lock1lockS {
+        Page7lock1lockS::from_bits(val)
+    }
+}
+impl From<Page7lock1lockS> for u8 {
+    #[inline(always)]
+    fn from(val: Page7lock1lockS) -> u8 {
+        Page7lock1lockS::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page8lock0noKeyState {
+    READ_ONLY = 0,
+    INACCESSIBLE = 0x01,
+}
+impl Page8lock0noKeyState {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page8lock0noKeyState {
+        unsafe { core::mem::transmute(val & 0x01) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page8lock0noKeyState {
+    #[inline(always)]
+    fn from(val: u8) -> Page8lock0noKeyState {
+        Page8lock0noKeyState::from_bits(val)
+    }
+}
+impl From<Page8lock0noKeyState> for u8 {
+    #[inline(always)]
+    fn from(val: Page8lock0noKeyState) -> u8 {
+        Page8lock0noKeyState::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page8lock1lockBl {
+    #[doc = "Bootloader permits user reads and writes to this page"]
+    READ_WRITE = 0,
+    #[doc = "Bootloader permits user reads of this page"]
+    READ_ONLY = 0x01,
+    #[doc = "Do not use. Behaves the same as INACCESSIBLE"]
+    RESERVED = 0x02,
+    #[doc = "Bootloader does not permit user access to this page"]
+    INACCESSIBLE = 0x03,
+}
+impl Page8lock1lockBl {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page8lock1lockBl {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page8lock1lockBl {
+    #[inline(always)]
+    fn from(val: u8) -> Page8lock1lockBl {
+        Page8lock1lockBl::from_bits(val)
+    }
+}
+impl From<Page8lock1lockBl> for u8 {
+    #[inline(always)]
+    fn from(val: Page8lock1lockBl) -> u8 {
+        Page8lock1lockBl::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page8lock1lockNs {
+    #[doc = "Page can be read by Non-secure software, and Secure software may permit Non-secure writes."]
+    READ_WRITE = 0,
+    #[doc = "Page can be read by Non-secure software"]
+    READ_ONLY = 0x01,
+    #[doc = "Do not use. Behaves the same as INACCESSIBLE."]
+    RESERVED = 0x02,
+    #[doc = "Page can not be accessed by Non-secure software."]
+    INACCESSIBLE = 0x03,
+}
+impl Page8lock1lockNs {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page8lock1lockNs {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page8lock1lockNs {
+    #[inline(always)]
+    fn from(val: u8) -> Page8lock1lockNs {
+        Page8lock1lockNs::from_bits(val)
+    }
+}
+impl From<Page8lock1lockNs> for u8 {
+    #[inline(always)]
+    fn from(val: Page8lock1lockNs) -> u8 {
+        Page8lock1lockNs::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page8lock1lockS {
+    #[doc = "Page is fully accessible by Secure software."]
+    READ_WRITE = 0,
+    #[doc = "Page can be read by Secure software, but can not be written."]
+    READ_ONLY = 0x01,
+    #[doc = "Do not use. Behaves the same as INACCESSIBLE."]
+    RESERVED = 0x02,
+    #[doc = "Page can not be accessed by Secure software."]
+    INACCESSIBLE = 0x03,
+}
+impl Page8lock1lockS {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page8lock1lockS {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page8lock1lockS {
+    #[inline(always)]
+    fn from(val: u8) -> Page8lock1lockS {
+        Page8lock1lockS::from_bits(val)
+    }
+}
+impl From<Page8lock1lockS> for u8 {
+    #[inline(always)]
+    fn from(val: Page8lock1lockS) -> u8 {
+        Page8lock1lockS::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page9lock0noKeyState {
+    READ_ONLY = 0,
+    INACCESSIBLE = 0x01,
+}
+impl Page9lock0noKeyState {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page9lock0noKeyState {
+        unsafe { core::mem::transmute(val & 0x01) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page9lock0noKeyState {
+    #[inline(always)]
+    fn from(val: u8) -> Page9lock0noKeyState {
+        Page9lock0noKeyState::from_bits(val)
+    }
+}
+impl From<Page9lock0noKeyState> for u8 {
+    #[inline(always)]
+    fn from(val: Page9lock0noKeyState) -> u8 {
+        Page9lock0noKeyState::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page9lock1lockBl {
+    #[doc = "Bootloader permits user reads and writes to this page"]
+    READ_WRITE = 0,
+    #[doc = "Bootloader permits user reads of this page"]
+    READ_ONLY = 0x01,
+    #[doc = "Do not use. Behaves the same as INACCESSIBLE"]
+    RESERVED = 0x02,
+    #[doc = "Bootloader does not permit user access to this page"]
+    INACCESSIBLE = 0x03,
+}
+impl Page9lock1lockBl {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page9lock1lockBl {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page9lock1lockBl {
+    #[inline(always)]
+    fn from(val: u8) -> Page9lock1lockBl {
+        Page9lock1lockBl::from_bits(val)
+    }
+}
+impl From<Page9lock1lockBl> for u8 {
+    #[inline(always)]
+    fn from(val: Page9lock1lockBl) -> u8 {
+        Page9lock1lockBl::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page9lock1lockNs {
+    #[doc = "Page can be read by Non-secure software, and Secure software may permit Non-secure writes."]
+    READ_WRITE = 0,
+    #[doc = "Page can be read by Non-secure software"]
+    READ_ONLY = 0x01,
+    #[doc = "Do not use. Behaves the same as INACCESSIBLE."]
+    RESERVED = 0x02,
+    #[doc = "Page can not be accessed by Non-secure software."]
+    INACCESSIBLE = 0x03,
+}
+impl Page9lock1lockNs {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page9lock1lockNs {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page9lock1lockNs {
+    #[inline(always)]
+    fn from(val: u8) -> Page9lock1lockNs {
+        Page9lock1lockNs::from_bits(val)
+    }
+}
+impl From<Page9lock1lockNs> for u8 {
+    #[inline(always)]
+    fn from(val: Page9lock1lockNs) -> u8 {
+        Page9lock1lockNs::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Page9lock1lockS {
+    #[doc = "Page is fully accessible by Secure software."]
+    READ_WRITE = 0,
+    #[doc = "Page can be read by Secure software, but can not be written."]
+    READ_ONLY = 0x01,
+    #[doc = "Do not use. Behaves the same as INACCESSIBLE."]
+    RESERVED = 0x02,
+    #[doc = "Page can not be accessed by Secure software."]
+    INACCESSIBLE = 0x03,
+}
+impl Page9lock1lockS {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Page9lock1lockS {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Page9lock1lockS {
+    #[inline(always)]
+    fn from(val: u8) -> Page9lock1lockS {
+        Page9lock1lockS::from_bits(val)
+    }
+}
+impl From<Page9lock1lockS> for u8 {
+    #[inline(always)]
+    fn from(val: Page9lock1lockS) -> u8 {
+        Page9lock1lockS::to_bits(val)
+    }
+}
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub struct Range(pub u16);
+impl Range {
+    pub const _1_15MHZ: Self = Self(0);
+    pub const _10_30MHZ: Self = Self(0x01);
+    pub const _25_60MHZ: Self = Self(0x02);
+    pub const _40_100MHZ: Self = Self(0x03);
+}
+impl Range {
+    pub const fn from_bits(val: u16) -> Range {
+        Self(val & 0x03ff)
+    }
+    pub const fn to_bits(self) -> u16 {
+        self.0
+    }
+}
+impl From<u16> for Range {
+    #[inline(always)]
+    fn from(val: u16) -> Range {
+        Range::from_bits(val)
+    }
+}
+impl From<Range> for u16 {
+    #[inline(always)]
+    fn from(val: Range) -> u16 {
+        Range::to_bits(val)
+    }
+}
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub struct UsbWhiteLabelAddr(pub u32);
+impl UsbWhiteLabelAddr {
+    pub const INDEX_USB_DEVICE_VID_VALUE: Self = Self(0);
+    pub const INDEX_USB_DEVICE_PID_VALUE: Self = Self(0x01);
+    pub const INDEX_USB_DEVICE_BCD_DEVICE_VALUE: Self = Self(0x02);
+    pub const INDEX_USB_DEVICE_LANG_ID_VALUE: Self = Self(0x03);
+    pub const INDEX_USB_DEVICE_MANUFACTURER_STRDEF: Self = Self(0x04);
+    pub const INDEX_USB_DEVICE_PRODUCT_STRDEF: Self = Self(0x05);
+    pub const INDEX_USB_DEVICE_SERIAL_NUMBER_STRDEF: Self = Self(0x06);
+    pub const INDEX_USB_CONFIG_ATTRIBUTES_MAX_POWER_VALUES: Self = Self(0x07);
+    pub const INDEX_VOLUME_LABEL_STRDEF: Self = Self(0x08);
+    pub const INDEX_SCSI_INQUIRY_VENDOR_STRDEF: Self = Self(0x09);
+    pub const INDEX_SCSI_INQUIRY_PRODUCT_STRDEF: Self = Self(0x0a);
+    pub const INDEX_SCSI_INQUIRY_VERSION_STRDEF: Self = Self(0x0b);
+    pub const INDEX_INDEX_HTM_REDIRECT_URL_STRDEF: Self = Self(0x0c);
+    pub const INDEX_INDEX_HTM_REDIRECT_NAME_STRDEF: Self = Self(0x0d);
+    pub const INDEX_INFO_UF2_TXT_MODEL_STRDEF: Self = Self(0x0e);
+    pub const INDEX_INFO_UF2_TXT_BOARD_ID_STRDEF: Self = Self(0x0f);
+}
+impl UsbWhiteLabelAddr {
+    pub const fn from_bits(val: u32) -> UsbWhiteLabelAddr {
+        Self(val & 0x00ff_ffff)
+    }
+    pub const fn to_bits(self) -> u32 {
+        self.0
+    }
+}
+impl From<u32> for UsbWhiteLabelAddr {
+    #[inline(always)]
+    fn from(val: u32) -> UsbWhiteLabelAddr {
+        UsbWhiteLabelAddr::from_bits(val)
+    }
+}
+impl From<UsbWhiteLabelAddr> for u32 {
+    #[inline(always)]
+    fn from(val: UsbWhiteLabelAddr) -> u32 {
+        UsbWhiteLabelAddr::to_bits(val)
+    }
+}
diff --git a/src/rp2350/pads.rs b/src/rp2350/pads.rs
new file mode 100644
index 00000000..27767a6f
--- /dev/null
+++ b/src/rp2350/pads.rs
@@ -0,0 +1,30 @@
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Pads {
+    ptr: *mut u8,
+}
+unsafe impl Send for Pads {}
+unsafe impl Sync for Pads {}
+impl Pads {
+    #[inline(always)]
+    pub const unsafe fn from_ptr(ptr: *mut ()) -> Self {
+        Self { ptr: ptr as _ }
+    }
+    #[inline(always)]
+    pub const fn as_ptr(&self) -> *mut () {
+        self.ptr as _
+    }
+    #[doc = "Voltage select. Per bank control"]
+    #[inline(always)]
+    pub const fn voltage_select(
+        self,
+    ) -> crate::common::Reg<regs::VoltageSelect, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(0usize) as _) }
+    }
+    #[inline(always)]
+    pub const fn gpio(self, n: usize) -> crate::common::Reg<regs::GpioCtrl, crate::common::RW> {
+        assert!(n < 50usize);
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(4usize + n * 4usize) as _) }
+    }
+}
+pub mod regs;
+pub mod vals;
diff --git a/src/rp2350/pads/regs.rs b/src/rp2350/pads/regs.rs
new file mode 100644
index 00000000..ddb9275e
--- /dev/null
+++ b/src/rp2350/pads/regs.rs
@@ -0,0 +1,120 @@
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct GpioCtrl(pub u32);
+impl GpioCtrl {
+    #[doc = "Slew rate control. 1 = Fast, 0 = Slow"]
+    #[inline(always)]
+    pub const fn slewfast(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Slew rate control. 1 = Fast, 0 = Slow"]
+    #[inline(always)]
+    pub fn set_slewfast(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[doc = "Enable schmitt trigger"]
+    #[inline(always)]
+    pub const fn schmitt(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Enable schmitt trigger"]
+    #[inline(always)]
+    pub fn set_schmitt(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+    #[doc = "Pull down enable"]
+    #[inline(always)]
+    pub const fn pde(&self) -> bool {
+        let val = (self.0 >> 2usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Pull down enable"]
+    #[inline(always)]
+    pub fn set_pde(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+    }
+    #[doc = "Pull up enable"]
+    #[inline(always)]
+    pub const fn pue(&self) -> bool {
+        let val = (self.0 >> 3usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Pull up enable"]
+    #[inline(always)]
+    pub fn set_pue(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
+    }
+    #[doc = "Drive strength."]
+    #[inline(always)]
+    pub const fn drive(&self) -> super::vals::Drive {
+        let val = (self.0 >> 4usize) & 0x03;
+        super::vals::Drive::from_bits(val as u8)
+    }
+    #[doc = "Drive strength."]
+    #[inline(always)]
+    pub fn set_drive(&mut self, val: super::vals::Drive) {
+        self.0 = (self.0 & !(0x03 << 4usize)) | (((val.to_bits() as u32) & 0x03) << 4usize);
+    }
+    #[doc = "Input enable"]
+    #[inline(always)]
+    pub const fn ie(&self) -> bool {
+        let val = (self.0 >> 6usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Input enable"]
+    #[inline(always)]
+    pub fn set_ie(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
+    }
+    #[doc = "Output disable. Has priority over output enable from peripherals"]
+    #[inline(always)]
+    pub const fn od(&self) -> bool {
+        let val = (self.0 >> 7usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Output disable. Has priority over output enable from peripherals"]
+    #[inline(always)]
+    pub fn set_od(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
+    }
+    #[doc = "Pad isolation control. Remove this once the pad is configured by software."]
+    #[inline(always)]
+    pub const fn iso(&self) -> bool {
+        let val = (self.0 >> 8usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Pad isolation control. Remove this once the pad is configured by software."]
+    #[inline(always)]
+    pub fn set_iso(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
+    }
+}
+impl Default for GpioCtrl {
+    #[inline(always)]
+    fn default() -> GpioCtrl {
+        GpioCtrl(0)
+    }
+}
+#[doc = "Voltage select. Per bank control"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct VoltageSelect(pub u32);
+impl VoltageSelect {
+    #[inline(always)]
+    pub const fn voltage_select(&self) -> super::vals::VoltageSelect {
+        let val = (self.0 >> 0usize) & 0x01;
+        super::vals::VoltageSelect::from_bits(val as u8)
+    }
+    #[inline(always)]
+    pub fn set_voltage_select(&mut self, val: super::vals::VoltageSelect) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val.to_bits() as u32) & 0x01) << 0usize);
+    }
+}
+impl Default for VoltageSelect {
+    #[inline(always)]
+    fn default() -> VoltageSelect {
+        VoltageSelect(0)
+    }
+}
diff --git a/src/rp2350/pads/vals.rs b/src/rp2350/pads/vals.rs
new file mode 100644
index 00000000..f9e7d6c3
--- /dev/null
+++ b/src/rp2350/pads/vals.rs
@@ -0,0 +1,60 @@
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Drive {
+    _2MA = 0,
+    _4MA = 0x01,
+    _8MA = 0x02,
+    _12MA = 0x03,
+}
+impl Drive {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Drive {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Drive {
+    #[inline(always)]
+    fn from(val: u8) -> Drive {
+        Drive::from_bits(val)
+    }
+}
+impl From<Drive> for u8 {
+    #[inline(always)]
+    fn from(val: Drive) -> u8 {
+        Drive::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum VoltageSelect {
+    #[doc = "Set voltage to 3.3V (DVDD >= 2V5)"]
+    _3V3 = 0,
+    #[doc = "Set voltage to 1.8V (DVDD <= 1V8)"]
+    _1V8 = 0x01,
+}
+impl VoltageSelect {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> VoltageSelect {
+        unsafe { core::mem::transmute(val & 0x01) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for VoltageSelect {
+    #[inline(always)]
+    fn from(val: u8) -> VoltageSelect {
+        VoltageSelect::from_bits(val)
+    }
+}
+impl From<VoltageSelect> for u8 {
+    #[inline(always)]
+    fn from(val: VoltageSelect) -> u8 {
+        VoltageSelect::to_bits(val)
+    }
+}
diff --git a/src/rp2350/pio.rs b/src/rp2350/pio.rs
new file mode 100644
index 00000000..a30ccc0c
--- /dev/null
+++ b/src/rp2350/pio.rs
@@ -0,0 +1,267 @@
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Irq {
+    ptr: *mut u8,
+}
+unsafe impl Send for Irq {}
+unsafe impl Sync for Irq {}
+impl Irq {
+    #[inline(always)]
+    pub const unsafe fn from_ptr(ptr: *mut ()) -> Self {
+        Self { ptr: ptr as _ }
+    }
+    #[inline(always)]
+    pub const fn as_ptr(&self) -> *mut () {
+        self.ptr as _
+    }
+    #[doc = "Interrupt Enable for irq0"]
+    #[inline(always)]
+    pub const fn inte(self) -> crate::common::Reg<regs::Intr, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(0usize) as _) }
+    }
+    #[doc = "Interrupt Force for irq0"]
+    #[inline(always)]
+    pub const fn intf(self) -> crate::common::Reg<regs::Intr, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(4usize) as _) }
+    }
+    #[doc = "Interrupt status after masking & forcing for irq0"]
+    #[inline(always)]
+    pub const fn ints(self) -> crate::common::Reg<regs::Intr, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(8usize) as _) }
+    }
+}
+#[doc = "Programmable IO block"]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Pio {
+    ptr: *mut u8,
+}
+unsafe impl Send for Pio {}
+unsafe impl Sync for Pio {}
+impl Pio {
+    #[inline(always)]
+    pub const unsafe fn from_ptr(ptr: *mut ()) -> Self {
+        Self { ptr: ptr as _ }
+    }
+    #[inline(always)]
+    pub const fn as_ptr(&self) -> *mut () {
+        self.ptr as _
+    }
+    #[doc = "PIO control register"]
+    #[inline(always)]
+    pub const fn ctrl(self) -> crate::common::Reg<regs::Ctrl, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(0usize) as _) }
+    }
+    #[doc = "FIFO status register"]
+    #[inline(always)]
+    pub const fn fstat(self) -> crate::common::Reg<regs::Fstat, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(4usize) as _) }
+    }
+    #[doc = "FIFO debug register"]
+    #[inline(always)]
+    pub const fn fdebug(self) -> crate::common::Reg<regs::Fdebug, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(8usize) as _) }
+    }
+    #[doc = "FIFO levels"]
+    #[inline(always)]
+    pub const fn flevel(self) -> crate::common::Reg<regs::Flevel, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(12usize) as _) }
+    }
+    #[doc = "Direct write access to the TX FIFO for this state machine. Each write pushes one word to the FIFO. Attempting to write to a full FIFO has no effect on the FIFO state or contents, and sets the sticky FDEBUG_TXOVER error flag for this FIFO."]
+    #[inline(always)]
+    pub const fn txf(self, n: usize) -> crate::common::Reg<u32, crate::common::RW> {
+        assert!(n < 4usize);
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(16usize + n * 4usize) as _) }
+    }
+    #[doc = "Direct read access to the RX FIFO for this state machine. Each read pops one word from the FIFO. Attempting to read from an empty FIFO has no effect on the FIFO state, and sets the sticky FDEBUG_RXUNDER error flag for this FIFO. The data returned to the system on a read from an empty FIFO is undefined."]
+    #[inline(always)]
+    pub const fn rxf(self, n: usize) -> crate::common::Reg<u32, crate::common::RW> {
+        assert!(n < 4usize);
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(32usize + n * 4usize) as _) }
+    }
+    #[doc = "State machine IRQ flags register. Write 1 to clear. There are eight state machine IRQ flags, which can be set, cleared, and waited on by the state machines. There's no fixed association between flags and state machines -- any state machine can use any flag. Any of the eight flags can be used for timing synchronisation between state machines, using IRQ and WAIT instructions. Any combination of the eight flags can also routed out to either of the two system-level interrupt requests, alongside FIFO status interrupts -- see e.g. IRQ0_INTE."]
+    #[inline(always)]
+    pub const fn irq(self) -> crate::common::Reg<regs::Irq, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(48usize) as _) }
+    }
+    #[doc = "Writing a 1 to each of these bits will forcibly assert the corresponding IRQ. Note this is different to the INTF register: writing here affects PIO internal state. INTF just asserts the processor-facing IRQ signal for testing ISRs, and is not visible to the state machines."]
+    #[inline(always)]
+    pub const fn irq_force(self) -> crate::common::Reg<regs::IrqForce, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(52usize) as _) }
+    }
+    #[doc = "There is a 2-flipflop synchronizer on each GPIO input, which protects PIO logic from metastabilities. This increases input delay, and for fast synchronous IO (e.g. SPI) these synchronizers may need to be bypassed. Each bit in this register corresponds to one GPIO. 0 -> input is synchronized (default) 1 -> synchronizer is bypassed If in doubt, leave this register as all zeroes."]
+    #[inline(always)]
+    pub const fn input_sync_bypass(self) -> crate::common::Reg<u32, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(56usize) as _) }
+    }
+    #[doc = "Read to sample the pad output values PIO is currently driving to the GPIOs. On RP2040 there are 30 GPIOs, so the two most significant bits are hardwired to 0."]
+    #[inline(always)]
+    pub const fn dbg_padout(self) -> crate::common::Reg<u32, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(60usize) as _) }
+    }
+    #[doc = "Read to sample the pad output enables (direction) PIO is currently driving to the GPIOs. On RP2040 there are 30 GPIOs, so the two most significant bits are hardwired to 0."]
+    #[inline(always)]
+    pub const fn dbg_padoe(self) -> crate::common::Reg<u32, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(64usize) as _) }
+    }
+    #[doc = "The PIO hardware has some free parameters that may vary between chip products. These should be provided in the chip datasheet, but are also exposed here."]
+    #[inline(always)]
+    pub const fn dbg_cfginfo(self) -> crate::common::Reg<regs::DbgCfginfo, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(68usize) as _) }
+    }
+    #[doc = "Write-only access to instruction memory location 0"]
+    #[inline(always)]
+    pub const fn instr_mem(
+        self,
+        n: usize,
+    ) -> crate::common::Reg<regs::InstrMem, crate::common::RW> {
+        assert!(n < 32usize);
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(72usize + n * 4usize) as _) }
+    }
+    #[inline(always)]
+    pub const fn sm(self, n: usize) -> StateMachine {
+        assert!(n < 4usize);
+        unsafe { StateMachine::from_ptr(self.ptr.add(200usize + n * 24usize) as _) }
+    }
+    #[doc = "Direct read/write access to entry 0 of SM0's RX FIFO, if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set."]
+    #[inline(always)]
+    pub const fn rxf0_putget0(self) -> crate::common::Reg<u32, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(296usize) as _) }
+    }
+    #[doc = "Direct read/write access to entry 1 of SM0's RX FIFO, if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set."]
+    #[inline(always)]
+    pub const fn rxf0_putget1(self) -> crate::common::Reg<u32, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(300usize) as _) }
+    }
+    #[doc = "Direct read/write access to entry 2 of SM0's RX FIFO, if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set."]
+    #[inline(always)]
+    pub const fn rxf0_putget2(self) -> crate::common::Reg<u32, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(304usize) as _) }
+    }
+    #[doc = "Direct read/write access to entry 3 of SM0's RX FIFO, if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set."]
+    #[inline(always)]
+    pub const fn rxf0_putget3(self) -> crate::common::Reg<u32, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(308usize) as _) }
+    }
+    #[doc = "Direct read/write access to entry 0 of SM1's RX FIFO, if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set."]
+    #[inline(always)]
+    pub const fn rxf1_putget0(self) -> crate::common::Reg<u32, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(312usize) as _) }
+    }
+    #[doc = "Direct read/write access to entry 1 of SM1's RX FIFO, if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set."]
+    #[inline(always)]
+    pub const fn rxf1_putget1(self) -> crate::common::Reg<u32, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(316usize) as _) }
+    }
+    #[doc = "Direct read/write access to entry 2 of SM1's RX FIFO, if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set."]
+    #[inline(always)]
+    pub const fn rxf1_putget2(self) -> crate::common::Reg<u32, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(320usize) as _) }
+    }
+    #[doc = "Direct read/write access to entry 3 of SM1's RX FIFO, if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set."]
+    #[inline(always)]
+    pub const fn rxf1_putget3(self) -> crate::common::Reg<u32, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(324usize) as _) }
+    }
+    #[doc = "Direct read/write access to entry 0 of SM2's RX FIFO, if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set."]
+    #[inline(always)]
+    pub const fn rxf2_putget0(self) -> crate::common::Reg<u32, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(328usize) as _) }
+    }
+    #[doc = "Direct read/write access to entry 1 of SM2's RX FIFO, if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set."]
+    #[inline(always)]
+    pub const fn rxf2_putget1(self) -> crate::common::Reg<u32, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(332usize) as _) }
+    }
+    #[doc = "Direct read/write access to entry 2 of SM2's RX FIFO, if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set."]
+    #[inline(always)]
+    pub const fn rxf2_putget2(self) -> crate::common::Reg<u32, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(336usize) as _) }
+    }
+    #[doc = "Direct read/write access to entry 3 of SM2's RX FIFO, if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set."]
+    #[inline(always)]
+    pub const fn rxf2_putget3(self) -> crate::common::Reg<u32, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(340usize) as _) }
+    }
+    #[doc = "Direct read/write access to entry 0 of SM3's RX FIFO, if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set."]
+    #[inline(always)]
+    pub const fn rxf3_putget0(self) -> crate::common::Reg<u32, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(344usize) as _) }
+    }
+    #[doc = "Direct read/write access to entry 1 of SM3's RX FIFO, if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set."]
+    #[inline(always)]
+    pub const fn rxf3_putget1(self) -> crate::common::Reg<u32, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(348usize) as _) }
+    }
+    #[doc = "Direct read/write access to entry 2 of SM3's RX FIFO, if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set."]
+    #[inline(always)]
+    pub const fn rxf3_putget2(self) -> crate::common::Reg<u32, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(352usize) as _) }
+    }
+    #[doc = "Direct read/write access to entry 3 of SM3's RX FIFO, if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set."]
+    #[inline(always)]
+    pub const fn rxf3_putget3(self) -> crate::common::Reg<u32, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(356usize) as _) }
+    }
+    #[doc = "Relocate GPIO 0 (from PIO's point of view) in the system GPIO numbering, to access more than 32 GPIOs from PIO. Only the values 0 and 16 are supported (only bit 4 is writable)."]
+    #[inline(always)]
+    pub const fn gpiobase(self) -> crate::common::Reg<regs::Gpiobase, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(360usize) as _) }
+    }
+    #[doc = "Raw Interrupts"]
+    #[inline(always)]
+    pub const fn intr(self) -> crate::common::Reg<regs::Intr, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(364usize) as _) }
+    }
+    #[inline(always)]
+    pub const fn irqs(self, n: usize) -> Irq {
+        assert!(n < 2usize);
+        unsafe { Irq::from_ptr(self.ptr.add(368usize + n * 12usize) as _) }
+    }
+}
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct StateMachine {
+    ptr: *mut u8,
+}
+unsafe impl Send for StateMachine {}
+unsafe impl Sync for StateMachine {}
+impl StateMachine {
+    #[inline(always)]
+    pub const unsafe fn from_ptr(ptr: *mut ()) -> Self {
+        Self { ptr: ptr as _ }
+    }
+    #[inline(always)]
+    pub const fn as_ptr(&self) -> *mut () {
+        self.ptr as _
+    }
+    #[doc = "Clock divisor register for state machine 1 Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256)"]
+    #[inline(always)]
+    pub const fn clkdiv(self) -> crate::common::Reg<regs::SmClkdiv, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(0usize) as _) }
+    }
+    #[doc = "Execution/behavioural settings for state machine 1"]
+    #[inline(always)]
+    pub const fn execctrl(self) -> crate::common::Reg<regs::SmExecctrl, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(4usize) as _) }
+    }
+    #[doc = "Control behaviour of the input/output shift registers for state machine 1"]
+    #[inline(always)]
+    pub const fn shiftctrl(self) -> crate::common::Reg<regs::SmShiftctrl, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(8usize) as _) }
+    }
+    #[doc = "Current instruction address of state machine 1"]
+    #[inline(always)]
+    pub const fn addr(self) -> crate::common::Reg<regs::SmAddr, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(12usize) as _) }
+    }
+    #[doc = "Read to see the instruction currently addressed by state machine 1's program counter Write to execute an instruction immediately (including jumps) and then resume execution."]
+    #[inline(always)]
+    pub const fn instr(self) -> crate::common::Reg<regs::SmInstr, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(16usize) as _) }
+    }
+    #[doc = "State machine pin control"]
+    #[inline(always)]
+    pub const fn pinctrl(self) -> crate::common::Reg<regs::SmPinctrl, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(20usize) as _) }
+    }
+}
+pub mod regs;
+pub mod vals;
diff --git a/src/rp2350/pio/regs.rs b/src/rp2350/pio/regs.rs
new file mode 100644
index 00000000..5da9bccf
--- /dev/null
+++ b/src/rp2350/pio/regs.rs
@@ -0,0 +1,1023 @@
+#[doc = "PIO control register"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Ctrl(pub u32);
+impl Ctrl {
+    #[doc = "Enable/disable each of the four state machines by writing 1/0 to each of these four bits. When disabled, a state machine will cease executing instructions, except those written directly to SMx_INSTR by the system. Multiple bits can be set/cleared at once to run/halt multiple state machines simultaneously."]
+    #[inline(always)]
+    pub const fn sm_enable(&self) -> u8 {
+        let val = (self.0 >> 0usize) & 0x0f;
+        val as u8
+    }
+    #[doc = "Enable/disable each of the four state machines by writing 1/0 to each of these four bits. When disabled, a state machine will cease executing instructions, except those written directly to SMx_INSTR by the system. Multiple bits can be set/cleared at once to run/halt multiple state machines simultaneously."]
+    #[inline(always)]
+    pub fn set_sm_enable(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize);
+    }
+    #[doc = "Write 1 to instantly clear internal SM state which may be otherwise difficult to access and will affect future execution. Specifically, the following are cleared: input and output shift counters; the contents of the input shift register; the delay counter; the waiting-on-IRQ state; any stalled instruction written to SMx_INSTR or run by OUT/MOV EXEC; any pin write left asserted due to OUT_STICKY. The contents of the output shift register and the X/Y scratch registers are not affected."]
+    #[inline(always)]
+    pub const fn sm_restart(&self) -> u8 {
+        let val = (self.0 >> 4usize) & 0x0f;
+        val as u8
+    }
+    #[doc = "Write 1 to instantly clear internal SM state which may be otherwise difficult to access and will affect future execution. Specifically, the following are cleared: input and output shift counters; the contents of the input shift register; the delay counter; the waiting-on-IRQ state; any stalled instruction written to SMx_INSTR or run by OUT/MOV EXEC; any pin write left asserted due to OUT_STICKY. The contents of the output shift register and the X/Y scratch registers are not affected."]
+    #[inline(always)]
+    pub fn set_sm_restart(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x0f << 4usize)) | (((val as u32) & 0x0f) << 4usize);
+    }
+    #[doc = "Restart a state machine's clock divider from an initial phase of 0. Clock dividers are free-running, so once started, their output (including fractional jitter) is completely determined by the integer/fractional divisor configured in SMx_CLKDIV. This means that, if multiple clock dividers with the same divisor are restarted simultaneously, by writing multiple 1 bits to this field, the execution clocks of those state machines will run in precise lockstep. Note that setting/clearing SM_ENABLE does not stop the clock divider from running, so once multiple state machines' clocks are synchronised, it is safe to disable/reenable a state machine, whilst keeping the clock dividers in sync. Note also that CLKDIV_RESTART can be written to whilst the state machine is running, and this is useful to resynchronise clock dividers after the divisors (SMx_CLKDIV) have been changed on-the-fly."]
+    #[inline(always)]
+    pub const fn clkdiv_restart(&self) -> u8 {
+        let val = (self.0 >> 8usize) & 0x0f;
+        val as u8
+    }
+    #[doc = "Restart a state machine's clock divider from an initial phase of 0. Clock dividers are free-running, so once started, their output (including fractional jitter) is completely determined by the integer/fractional divisor configured in SMx_CLKDIV. This means that, if multiple clock dividers with the same divisor are restarted simultaneously, by writing multiple 1 bits to this field, the execution clocks of those state machines will run in precise lockstep. Note that setting/clearing SM_ENABLE does not stop the clock divider from running, so once multiple state machines' clocks are synchronised, it is safe to disable/reenable a state machine, whilst keeping the clock dividers in sync. Note also that CLKDIV_RESTART can be written to whilst the state machine is running, and this is useful to resynchronise clock dividers after the divisors (SMx_CLKDIV) have been changed on-the-fly."]
+    #[inline(always)]
+    pub fn set_clkdiv_restart(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x0f << 8usize)) | (((val as u32) & 0x0f) << 8usize);
+    }
+    #[doc = "A mask of state machines in the neighbouring lower-numbered PIO block in the system (or the highest-numbered PIO block if this is PIO block 0) to which to apply the operations specified by OP_CLKDIV_RESTART, OP_ENABLE, OP_DISABLE in the same write. This allows state machines in a neighbouring PIO block to be started/stopped/clock-synced exactly simultaneously with a write to this PIO block's CTRL register. Neighbouring PIO blocks are disconnected (status signals tied to 0 and control signals ignored) if one block is accessible to NonSecure code, and one is not."]
+    #[inline(always)]
+    pub const fn prev_pio_mask(&self) -> u8 {
+        let val = (self.0 >> 16usize) & 0x0f;
+        val as u8
+    }
+    #[doc = "A mask of state machines in the neighbouring lower-numbered PIO block in the system (or the highest-numbered PIO block if this is PIO block 0) to which to apply the operations specified by OP_CLKDIV_RESTART, OP_ENABLE, OP_DISABLE in the same write. This allows state machines in a neighbouring PIO block to be started/stopped/clock-synced exactly simultaneously with a write to this PIO block's CTRL register. Neighbouring PIO blocks are disconnected (status signals tied to 0 and control signals ignored) if one block is accessible to NonSecure code, and one is not."]
+    #[inline(always)]
+    pub fn set_prev_pio_mask(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x0f << 16usize)) | (((val as u32) & 0x0f) << 16usize);
+    }
+    #[doc = "A mask of state machines in the neighbouring higher-numbered PIO block in the system (or PIO block 0 if this is the highest-numbered PIO block) to which to apply the operations specified by NEXTPREV_CLKDIV_RESTART, NEXTPREV_SM_ENABLE, and NEXTPREV_SM_DISABLE in the same write. This allows state machines in a neighbouring PIO block to be started/stopped/clock-synced exactly simultaneously with a write to this PIO block's CTRL register. Note that in a system with two PIOs, NEXT_PIO_MASK and PREV_PIO_MASK actually indicate the same PIO block. In this case the effects are applied cumulatively (as though the masks were OR'd together). Neighbouring PIO blocks are disconnected (status signals tied to 0 and control signals ignored) if one block is accessible to NonSecure code, and one is not."]
+    #[inline(always)]
+    pub const fn next_pio_mask(&self) -> u8 {
+        let val = (self.0 >> 20usize) & 0x0f;
+        val as u8
+    }
+    #[doc = "A mask of state machines in the neighbouring higher-numbered PIO block in the system (or PIO block 0 if this is the highest-numbered PIO block) to which to apply the operations specified by NEXTPREV_CLKDIV_RESTART, NEXTPREV_SM_ENABLE, and NEXTPREV_SM_DISABLE in the same write. This allows state machines in a neighbouring PIO block to be started/stopped/clock-synced exactly simultaneously with a write to this PIO block's CTRL register. Note that in a system with two PIOs, NEXT_PIO_MASK and PREV_PIO_MASK actually indicate the same PIO block. In this case the effects are applied cumulatively (as though the masks were OR'd together). Neighbouring PIO blocks are disconnected (status signals tied to 0 and control signals ignored) if one block is accessible to NonSecure code, and one is not."]
+    #[inline(always)]
+    pub fn set_next_pio_mask(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x0f << 20usize)) | (((val as u32) & 0x0f) << 20usize);
+    }
+    #[doc = "Write 1 to enable state machines in neighbouring PIO blocks, as specified by NEXT_PIO_MASK and PREV_PIO_MASK in the same write. This is equivalent to setting the corresponding SM_ENABLE bits in those PIOs' CTRL registers. If both OTHERS_SM_ENABLE and OTHERS_SM_DISABLE are set, the disable takes precedence."]
+    #[inline(always)]
+    pub const fn nextprev_sm_enable(&self) -> bool {
+        let val = (self.0 >> 24usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Write 1 to enable state machines in neighbouring PIO blocks, as specified by NEXT_PIO_MASK and PREV_PIO_MASK in the same write. This is equivalent to setting the corresponding SM_ENABLE bits in those PIOs' CTRL registers. If both OTHERS_SM_ENABLE and OTHERS_SM_DISABLE are set, the disable takes precedence."]
+    #[inline(always)]
+    pub fn set_nextprev_sm_enable(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 24usize)) | (((val as u32) & 0x01) << 24usize);
+    }
+    #[doc = "Write 1 to disable state machines in neighbouring PIO blocks, as specified by NEXT_PIO_MASK and PREV_PIO_MASK in the same write. This is equivalent to clearing the corresponding SM_ENABLE bits in those PIOs' CTRL registers."]
+    #[inline(always)]
+    pub const fn nextprev_sm_disable(&self) -> bool {
+        let val = (self.0 >> 25usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Write 1 to disable state machines in neighbouring PIO blocks, as specified by NEXT_PIO_MASK and PREV_PIO_MASK in the same write. This is equivalent to clearing the corresponding SM_ENABLE bits in those PIOs' CTRL registers."]
+    #[inline(always)]
+    pub fn set_nextprev_sm_disable(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 25usize)) | (((val as u32) & 0x01) << 25usize);
+    }
+    #[doc = "Write 1 to restart the clock dividers of state machines in neighbouring PIO blocks, as specified by NEXT_PIO_MASK and PREV_PIO_MASK in the same write. This is equivalent to writing 1 to the corresponding CLKDIV_RESTART bits in those PIOs' CTRL registers."]
+    #[inline(always)]
+    pub const fn nextprev_clkdiv_restart(&self) -> bool {
+        let val = (self.0 >> 26usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Write 1 to restart the clock dividers of state machines in neighbouring PIO blocks, as specified by NEXT_PIO_MASK and PREV_PIO_MASK in the same write. This is equivalent to writing 1 to the corresponding CLKDIV_RESTART bits in those PIOs' CTRL registers."]
+    #[inline(always)]
+    pub fn set_nextprev_clkdiv_restart(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 26usize)) | (((val as u32) & 0x01) << 26usize);
+    }
+}
+impl Default for Ctrl {
+    #[inline(always)]
+    fn default() -> Ctrl {
+        Ctrl(0)
+    }
+}
+#[doc = "The PIO hardware has some free parameters that may vary between chip products. These should be provided in the chip datasheet, but are also exposed here."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct DbgCfginfo(pub u32);
+impl DbgCfginfo {
+    #[doc = "The depth of the state machine TX/RX FIFOs, measured in words. Joining fifos via SHIFTCTRL_FJOIN gives one FIFO with double this depth."]
+    #[inline(always)]
+    pub const fn fifo_depth(&self) -> u8 {
+        let val = (self.0 >> 0usize) & 0x3f;
+        val as u8
+    }
+    #[doc = "The depth of the state machine TX/RX FIFOs, measured in words. Joining fifos via SHIFTCTRL_FJOIN gives one FIFO with double this depth."]
+    #[inline(always)]
+    pub fn set_fifo_depth(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x3f << 0usize)) | (((val as u32) & 0x3f) << 0usize);
+    }
+    #[doc = "The number of state machines this PIO instance is equipped with."]
+    #[inline(always)]
+    pub const fn sm_count(&self) -> u8 {
+        let val = (self.0 >> 8usize) & 0x0f;
+        val as u8
+    }
+    #[doc = "The number of state machines this PIO instance is equipped with."]
+    #[inline(always)]
+    pub fn set_sm_count(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x0f << 8usize)) | (((val as u32) & 0x0f) << 8usize);
+    }
+    #[doc = "The size of the instruction memory, measured in units of one instruction"]
+    #[inline(always)]
+    pub const fn imem_size(&self) -> u8 {
+        let val = (self.0 >> 16usize) & 0x3f;
+        val as u8
+    }
+    #[doc = "The size of the instruction memory, measured in units of one instruction"]
+    #[inline(always)]
+    pub fn set_imem_size(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x3f << 16usize)) | (((val as u32) & 0x3f) << 16usize);
+    }
+    #[doc = "Version of the core PIO hardware."]
+    #[inline(always)]
+    pub const fn version(&self) -> super::vals::Version {
+        let val = (self.0 >> 28usize) & 0x0f;
+        super::vals::Version::from_bits(val as u8)
+    }
+    #[doc = "Version of the core PIO hardware."]
+    #[inline(always)]
+    pub fn set_version(&mut self, val: super::vals::Version) {
+        self.0 = (self.0 & !(0x0f << 28usize)) | (((val.to_bits() as u32) & 0x0f) << 28usize);
+    }
+}
+impl Default for DbgCfginfo {
+    #[inline(always)]
+    fn default() -> DbgCfginfo {
+        DbgCfginfo(0)
+    }
+}
+#[doc = "FIFO debug register"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Fdebug(pub u32);
+impl Fdebug {
+    #[doc = "State machine has stalled on full RX FIFO during a blocking PUSH, or an IN with autopush enabled. This flag is also set when a nonblocking PUSH to a full FIFO took place, in which case the state machine has dropped data. Write 1 to clear."]
+    #[inline(always)]
+    pub const fn rxstall(&self) -> u8 {
+        let val = (self.0 >> 0usize) & 0x0f;
+        val as u8
+    }
+    #[doc = "State machine has stalled on full RX FIFO during a blocking PUSH, or an IN with autopush enabled. This flag is also set when a nonblocking PUSH to a full FIFO took place, in which case the state machine has dropped data. Write 1 to clear."]
+    #[inline(always)]
+    pub fn set_rxstall(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize);
+    }
+    #[doc = "RX FIFO underflow (i.e. read-on-empty by the system) has occurred. Write 1 to clear. Note that read-on-empty does not perturb the state of the FIFO in any way, but the data returned by reading from an empty FIFO is undefined, so this flag generally only becomes set due to some kind of software error."]
+    #[inline(always)]
+    pub const fn rxunder(&self) -> u8 {
+        let val = (self.0 >> 8usize) & 0x0f;
+        val as u8
+    }
+    #[doc = "RX FIFO underflow (i.e. read-on-empty by the system) has occurred. Write 1 to clear. Note that read-on-empty does not perturb the state of the FIFO in any way, but the data returned by reading from an empty FIFO is undefined, so this flag generally only becomes set due to some kind of software error."]
+    #[inline(always)]
+    pub fn set_rxunder(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x0f << 8usize)) | (((val as u32) & 0x0f) << 8usize);
+    }
+    #[doc = "TX FIFO overflow (i.e. write-on-full by the system) has occurred. Write 1 to clear. Note that write-on-full does not alter the state or contents of the FIFO in any way, but the data that the system attempted to write is dropped, so if this flag is set, your software has quite likely dropped some data on the floor."]
+    #[inline(always)]
+    pub const fn txover(&self) -> u8 {
+        let val = (self.0 >> 16usize) & 0x0f;
+        val as u8
+    }
+    #[doc = "TX FIFO overflow (i.e. write-on-full by the system) has occurred. Write 1 to clear. Note that write-on-full does not alter the state or contents of the FIFO in any way, but the data that the system attempted to write is dropped, so if this flag is set, your software has quite likely dropped some data on the floor."]
+    #[inline(always)]
+    pub fn set_txover(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x0f << 16usize)) | (((val as u32) & 0x0f) << 16usize);
+    }
+    #[doc = "State machine has stalled on empty TX FIFO during a blocking PULL, or an OUT with autopull enabled. Write 1 to clear."]
+    #[inline(always)]
+    pub const fn txstall(&self) -> u8 {
+        let val = (self.0 >> 24usize) & 0x0f;
+        val as u8
+    }
+    #[doc = "State machine has stalled on empty TX FIFO during a blocking PULL, or an OUT with autopull enabled. Write 1 to clear."]
+    #[inline(always)]
+    pub fn set_txstall(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x0f << 24usize)) | (((val as u32) & 0x0f) << 24usize);
+    }
+}
+impl Default for Fdebug {
+    #[inline(always)]
+    fn default() -> Fdebug {
+        Fdebug(0)
+    }
+}
+#[doc = "FIFO levels"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Flevel(pub u32);
+impl Flevel {
+    #[inline(always)]
+    pub const fn tx0(&self) -> u8 {
+        let val = (self.0 >> 0usize) & 0x0f;
+        val as u8
+    }
+    #[inline(always)]
+    pub fn set_tx0(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize);
+    }
+    #[inline(always)]
+    pub const fn rx0(&self) -> u8 {
+        let val = (self.0 >> 4usize) & 0x0f;
+        val as u8
+    }
+    #[inline(always)]
+    pub fn set_rx0(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x0f << 4usize)) | (((val as u32) & 0x0f) << 4usize);
+    }
+    #[inline(always)]
+    pub const fn tx1(&self) -> u8 {
+        let val = (self.0 >> 8usize) & 0x0f;
+        val as u8
+    }
+    #[inline(always)]
+    pub fn set_tx1(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x0f << 8usize)) | (((val as u32) & 0x0f) << 8usize);
+    }
+    #[inline(always)]
+    pub const fn rx1(&self) -> u8 {
+        let val = (self.0 >> 12usize) & 0x0f;
+        val as u8
+    }
+    #[inline(always)]
+    pub fn set_rx1(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x0f << 12usize)) | (((val as u32) & 0x0f) << 12usize);
+    }
+    #[inline(always)]
+    pub const fn tx2(&self) -> u8 {
+        let val = (self.0 >> 16usize) & 0x0f;
+        val as u8
+    }
+    #[inline(always)]
+    pub fn set_tx2(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x0f << 16usize)) | (((val as u32) & 0x0f) << 16usize);
+    }
+    #[inline(always)]
+    pub const fn rx2(&self) -> u8 {
+        let val = (self.0 >> 20usize) & 0x0f;
+        val as u8
+    }
+    #[inline(always)]
+    pub fn set_rx2(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x0f << 20usize)) | (((val as u32) & 0x0f) << 20usize);
+    }
+    #[inline(always)]
+    pub const fn tx3(&self) -> u8 {
+        let val = (self.0 >> 24usize) & 0x0f;
+        val as u8
+    }
+    #[inline(always)]
+    pub fn set_tx3(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x0f << 24usize)) | (((val as u32) & 0x0f) << 24usize);
+    }
+    #[inline(always)]
+    pub const fn rx3(&self) -> u8 {
+        let val = (self.0 >> 28usize) & 0x0f;
+        val as u8
+    }
+    #[inline(always)]
+    pub fn set_rx3(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x0f << 28usize)) | (((val as u32) & 0x0f) << 28usize);
+    }
+}
+impl Default for Flevel {
+    #[inline(always)]
+    fn default() -> Flevel {
+        Flevel(0)
+    }
+}
+#[doc = "FIFO status register"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Fstat(pub u32);
+impl Fstat {
+    #[doc = "State machine RX FIFO is full"]
+    #[inline(always)]
+    pub const fn rxfull(&self) -> u8 {
+        let val = (self.0 >> 0usize) & 0x0f;
+        val as u8
+    }
+    #[doc = "State machine RX FIFO is full"]
+    #[inline(always)]
+    pub fn set_rxfull(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize);
+    }
+    #[doc = "State machine RX FIFO is empty"]
+    #[inline(always)]
+    pub const fn rxempty(&self) -> u8 {
+        let val = (self.0 >> 8usize) & 0x0f;
+        val as u8
+    }
+    #[doc = "State machine RX FIFO is empty"]
+    #[inline(always)]
+    pub fn set_rxempty(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x0f << 8usize)) | (((val as u32) & 0x0f) << 8usize);
+    }
+    #[doc = "State machine TX FIFO is full"]
+    #[inline(always)]
+    pub const fn txfull(&self) -> u8 {
+        let val = (self.0 >> 16usize) & 0x0f;
+        val as u8
+    }
+    #[doc = "State machine TX FIFO is full"]
+    #[inline(always)]
+    pub fn set_txfull(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x0f << 16usize)) | (((val as u32) & 0x0f) << 16usize);
+    }
+    #[doc = "State machine TX FIFO is empty"]
+    #[inline(always)]
+    pub const fn txempty(&self) -> u8 {
+        let val = (self.0 >> 24usize) & 0x0f;
+        val as u8
+    }
+    #[doc = "State machine TX FIFO is empty"]
+    #[inline(always)]
+    pub fn set_txempty(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x0f << 24usize)) | (((val as u32) & 0x0f) << 24usize);
+    }
+}
+impl Default for Fstat {
+    #[inline(always)]
+    fn default() -> Fstat {
+        Fstat(0)
+    }
+}
+#[doc = "Relocate GPIO 0 (from PIO's point of view) in the system GPIO numbering, to access more than 32 GPIOs from PIO. Only the values 0 and 16 are supported (only bit 4 is writable)."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Gpiobase(pub u32);
+impl Gpiobase {
+    #[inline(always)]
+    pub const fn gpiobase(&self) -> bool {
+        let val = (self.0 >> 4usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gpiobase(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
+    }
+}
+impl Default for Gpiobase {
+    #[inline(always)]
+    fn default() -> Gpiobase {
+        Gpiobase(0)
+    }
+}
+#[doc = "Write-only access to instruction memory location 19"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct InstrMem(pub u32);
+impl InstrMem {
+    #[inline(always)]
+    pub const fn instr_mem(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0xffff;
+        val as u16
+    }
+    #[inline(always)]
+    pub fn set_instr_mem(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+    }
+}
+impl Default for InstrMem {
+    #[inline(always)]
+    fn default() -> InstrMem {
+        InstrMem(0)
+    }
+}
+#[doc = "Interrupt Enable for irq1"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Intr(pub u32);
+impl Intr {
+    #[inline(always)]
+    pub const fn sm0_rxnempty(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_sm0_rxnempty(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[inline(always)]
+    pub const fn sm1_rxnempty(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_sm1_rxnempty(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+    #[inline(always)]
+    pub const fn sm2_rxnempty(&self) -> bool {
+        let val = (self.0 >> 2usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_sm2_rxnempty(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+    }
+    #[inline(always)]
+    pub const fn sm3_rxnempty(&self) -> bool {
+        let val = (self.0 >> 3usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_sm3_rxnempty(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
+    }
+    #[inline(always)]
+    pub const fn sm0_txnfull(&self) -> bool {
+        let val = (self.0 >> 4usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_sm0_txnfull(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
+    }
+    #[inline(always)]
+    pub const fn sm1_txnfull(&self) -> bool {
+        let val = (self.0 >> 5usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_sm1_txnfull(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
+    }
+    #[inline(always)]
+    pub const fn sm2_txnfull(&self) -> bool {
+        let val = (self.0 >> 6usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_sm2_txnfull(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
+    }
+    #[inline(always)]
+    pub const fn sm3_txnfull(&self) -> bool {
+        let val = (self.0 >> 7usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_sm3_txnfull(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
+    }
+    #[inline(always)]
+    pub const fn sm0(&self) -> bool {
+        let val = (self.0 >> 8usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_sm0(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
+    }
+    #[inline(always)]
+    pub const fn sm1(&self) -> bool {
+        let val = (self.0 >> 9usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_sm1(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
+    }
+    #[inline(always)]
+    pub const fn sm2(&self) -> bool {
+        let val = (self.0 >> 10usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_sm2(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize);
+    }
+    #[inline(always)]
+    pub const fn sm3(&self) -> bool {
+        let val = (self.0 >> 11usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_sm3(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
+    }
+    #[inline(always)]
+    pub const fn sm4(&self) -> bool {
+        let val = (self.0 >> 12usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_sm4(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
+    }
+    #[inline(always)]
+    pub const fn sm5(&self) -> bool {
+        let val = (self.0 >> 13usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_sm5(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize);
+    }
+    #[inline(always)]
+    pub const fn sm6(&self) -> bool {
+        let val = (self.0 >> 14usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_sm6(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize);
+    }
+    #[inline(always)]
+    pub const fn sm7(&self) -> bool {
+        let val = (self.0 >> 15usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_sm7(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize);
+    }
+}
+impl Default for Intr {
+    #[inline(always)]
+    fn default() -> Intr {
+        Intr(0)
+    }
+}
+#[doc = "State machine IRQ flags register. Write 1 to clear. There are eight state machine IRQ flags, which can be set, cleared, and waited on by the state machines. There's no fixed association between flags and state machines -- any state machine can use any flag. Any of the eight flags can be used for timing synchronisation between state machines, using IRQ and WAIT instructions. Any combination of the eight flags can also routed out to either of the two system-level interrupt requests, alongside FIFO status interrupts -- see e.g. IRQ0_INTE."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Irq(pub u32);
+impl Irq {
+    #[inline(always)]
+    pub const fn irq(&self) -> u8 {
+        let val = (self.0 >> 0usize) & 0xff;
+        val as u8
+    }
+    #[inline(always)]
+    pub fn set_irq(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize);
+    }
+}
+impl Default for Irq {
+    #[inline(always)]
+    fn default() -> Irq {
+        Irq(0)
+    }
+}
+#[doc = "Writing a 1 to each of these bits will forcibly assert the corresponding IRQ. Note this is different to the INTF register: writing here affects PIO internal state. INTF just asserts the processor-facing IRQ signal for testing ISRs, and is not visible to the state machines."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct IrqForce(pub u32);
+impl IrqForce {
+    #[inline(always)]
+    pub const fn irq_force(&self) -> u8 {
+        let val = (self.0 >> 0usize) & 0xff;
+        val as u8
+    }
+    #[inline(always)]
+    pub fn set_irq_force(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize);
+    }
+}
+impl Default for IrqForce {
+    #[inline(always)]
+    fn default() -> IrqForce {
+        IrqForce(0)
+    }
+}
+#[doc = "Current instruction address of state machine 3"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct SmAddr(pub u32);
+impl SmAddr {
+    #[inline(always)]
+    pub const fn addr(&self) -> u8 {
+        let val = (self.0 >> 0usize) & 0x1f;
+        val as u8
+    }
+    #[inline(always)]
+    pub fn set_addr(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x1f << 0usize)) | (((val as u32) & 0x1f) << 0usize);
+    }
+}
+impl Default for SmAddr {
+    #[inline(always)]
+    fn default() -> SmAddr {
+        SmAddr(0)
+    }
+}
+#[doc = "Clock divisor register for state machine 3 Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct SmClkdiv(pub u32);
+impl SmClkdiv {
+    #[doc = "Fractional part of clock divisor"]
+    #[inline(always)]
+    pub const fn frac(&self) -> u8 {
+        let val = (self.0 >> 8usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Fractional part of clock divisor"]
+    #[inline(always)]
+    pub fn set_frac(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize);
+    }
+    #[doc = "Effective frequency is sysclk/(int + frac/256). Value of 0 is interpreted as 65536. If INT is 0, FRAC must also be 0."]
+    #[inline(always)]
+    pub const fn int(&self) -> u16 {
+        let val = (self.0 >> 16usize) & 0xffff;
+        val as u16
+    }
+    #[doc = "Effective frequency is sysclk/(int + frac/256). Value of 0 is interpreted as 65536. If INT is 0, FRAC must also be 0."]
+    #[inline(always)]
+    pub fn set_int(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 16usize)) | (((val as u32) & 0xffff) << 16usize);
+    }
+}
+impl Default for SmClkdiv {
+    #[inline(always)]
+    fn default() -> SmClkdiv {
+        SmClkdiv(0)
+    }
+}
+#[doc = "Execution/behavioural settings for state machine 3"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct SmExecctrl(pub u32);
+impl SmExecctrl {
+    #[doc = "Comparison level or IRQ index for the MOV x, STATUS instruction. If STATUS_SEL is TXLEVEL or RXLEVEL, then values of STATUS_N greater than the current FIFO depth are reserved, and have undefined behaviour."]
+    #[inline(always)]
+    pub const fn status_n(&self) -> super::vals::ExecctrlStatusN {
+        let val = (self.0 >> 0usize) & 0x1f;
+        super::vals::ExecctrlStatusN::from_bits(val as u8)
+    }
+    #[doc = "Comparison level or IRQ index for the MOV x, STATUS instruction. If STATUS_SEL is TXLEVEL or RXLEVEL, then values of STATUS_N greater than the current FIFO depth are reserved, and have undefined behaviour."]
+    #[inline(always)]
+    pub fn set_status_n(&mut self, val: super::vals::ExecctrlStatusN) {
+        self.0 = (self.0 & !(0x1f << 0usize)) | (((val.to_bits() as u32) & 0x1f) << 0usize);
+    }
+    #[doc = "Comparison used for the MOV x, STATUS instruction."]
+    #[inline(always)]
+    pub const fn status_sel(&self) -> super::vals::ExecctrlStatusSel {
+        let val = (self.0 >> 5usize) & 0x03;
+        super::vals::ExecctrlStatusSel::from_bits(val as u8)
+    }
+    #[doc = "Comparison used for the MOV x, STATUS instruction."]
+    #[inline(always)]
+    pub fn set_status_sel(&mut self, val: super::vals::ExecctrlStatusSel) {
+        self.0 = (self.0 & !(0x03 << 5usize)) | (((val.to_bits() as u32) & 0x03) << 5usize);
+    }
+    #[doc = "After reaching wrap_top, execution is wrapped to this address."]
+    #[inline(always)]
+    pub const fn wrap_bottom(&self) -> u8 {
+        let val = (self.0 >> 7usize) & 0x1f;
+        val as u8
+    }
+    #[doc = "After reaching wrap_top, execution is wrapped to this address."]
+    #[inline(always)]
+    pub fn set_wrap_bottom(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x1f << 7usize)) | (((val as u32) & 0x1f) << 7usize);
+    }
+    #[doc = "After reaching this address, execution is wrapped to wrap_bottom. If the instruction is a jump, and the jump condition is true, the jump takes priority."]
+    #[inline(always)]
+    pub const fn wrap_top(&self) -> u8 {
+        let val = (self.0 >> 12usize) & 0x1f;
+        val as u8
+    }
+    #[doc = "After reaching this address, execution is wrapped to wrap_bottom. If the instruction is a jump, and the jump condition is true, the jump takes priority."]
+    #[inline(always)]
+    pub fn set_wrap_top(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x1f << 12usize)) | (((val as u32) & 0x1f) << 12usize);
+    }
+    #[doc = "Continuously assert the most recent OUT/SET to the pins"]
+    #[inline(always)]
+    pub const fn out_sticky(&self) -> bool {
+        let val = (self.0 >> 17usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Continuously assert the most recent OUT/SET to the pins"]
+    #[inline(always)]
+    pub fn set_out_sticky(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
+    }
+    #[doc = "If 1, use a bit of OUT data as an auxiliary write enable When used in conjunction with OUT_STICKY, writes with an enable of 0 will deassert the latest pin write. This can create useful masking/override behaviour due to the priority ordering of state machine pin writes (SM0 < SM1 < ...)"]
+    #[inline(always)]
+    pub const fn inline_out_en(&self) -> bool {
+        let val = (self.0 >> 18usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, use a bit of OUT data as an auxiliary write enable When used in conjunction with OUT_STICKY, writes with an enable of 0 will deassert the latest pin write. This can create useful masking/override behaviour due to the priority ordering of state machine pin writes (SM0 < SM1 < ...)"]
+    #[inline(always)]
+    pub fn set_inline_out_en(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize);
+    }
+    #[doc = "Which data bit to use for inline OUT enable"]
+    #[inline(always)]
+    pub const fn out_en_sel(&self) -> u8 {
+        let val = (self.0 >> 19usize) & 0x1f;
+        val as u8
+    }
+    #[doc = "Which data bit to use for inline OUT enable"]
+    #[inline(always)]
+    pub fn set_out_en_sel(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x1f << 19usize)) | (((val as u32) & 0x1f) << 19usize);
+    }
+    #[doc = "The GPIO number to use as condition for JMP PIN. Unaffected by input mapping."]
+    #[inline(always)]
+    pub const fn jmp_pin(&self) -> u8 {
+        let val = (self.0 >> 24usize) & 0x1f;
+        val as u8
+    }
+    #[doc = "The GPIO number to use as condition for JMP PIN. Unaffected by input mapping."]
+    #[inline(always)]
+    pub fn set_jmp_pin(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x1f << 24usize)) | (((val as u32) & 0x1f) << 24usize);
+    }
+    #[doc = "If 1, side-set data is asserted to pin directions, instead of pin values"]
+    #[inline(always)]
+    pub const fn side_pindir(&self) -> bool {
+        let val = (self.0 >> 29usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, side-set data is asserted to pin directions, instead of pin values"]
+    #[inline(always)]
+    pub fn set_side_pindir(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 29usize)) | (((val as u32) & 0x01) << 29usize);
+    }
+    #[doc = "If 1, the MSB of the Delay/Side-set instruction field is used as side-set enable, rather than a side-set data bit. This allows instructions to perform side-set optionally, rather than on every instruction, but the maximum possible side-set width is reduced from 5 to 4. Note that the value of PINCTRL_SIDESET_COUNT is inclusive of this enable bit."]
+    #[inline(always)]
+    pub const fn side_en(&self) -> bool {
+        let val = (self.0 >> 30usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, the MSB of the Delay/Side-set instruction field is used as side-set enable, rather than a side-set data bit. This allows instructions to perform side-set optionally, rather than on every instruction, but the maximum possible side-set width is reduced from 5 to 4. Note that the value of PINCTRL_SIDESET_COUNT is inclusive of this enable bit."]
+    #[inline(always)]
+    pub fn set_side_en(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 30usize)) | (((val as u32) & 0x01) << 30usize);
+    }
+    #[doc = "If 1, an instruction written to SMx_INSTR is stalled, and latched by the state machine. Will clear to 0 once this instruction completes."]
+    #[inline(always)]
+    pub const fn exec_stalled(&self) -> bool {
+        let val = (self.0 >> 31usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, an instruction written to SMx_INSTR is stalled, and latched by the state machine. Will clear to 0 once this instruction completes."]
+    #[inline(always)]
+    pub fn set_exec_stalled(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 31usize)) | (((val as u32) & 0x01) << 31usize);
+    }
+}
+impl Default for SmExecctrl {
+    #[inline(always)]
+    fn default() -> SmExecctrl {
+        SmExecctrl(0)
+    }
+}
+#[doc = "Read to see the instruction currently addressed by state machine 0's program counter Write to execute an instruction immediately (including jumps) and then resume execution."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct SmInstr(pub u32);
+impl SmInstr {
+    #[inline(always)]
+    pub const fn instr(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0xffff;
+        val as u16
+    }
+    #[inline(always)]
+    pub fn set_instr(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+    }
+}
+impl Default for SmInstr {
+    #[inline(always)]
+    fn default() -> SmInstr {
+        SmInstr(0)
+    }
+}
+#[doc = "State machine pin control"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct SmPinctrl(pub u32);
+impl SmPinctrl {
+    #[doc = "The lowest-numbered pin that will be affected by an OUT PINS, OUT PINDIRS or MOV PINS instruction. The data written to this pin will always be the least-significant bit of the OUT or MOV data."]
+    #[inline(always)]
+    pub const fn out_base(&self) -> u8 {
+        let val = (self.0 >> 0usize) & 0x1f;
+        val as u8
+    }
+    #[doc = "The lowest-numbered pin that will be affected by an OUT PINS, OUT PINDIRS or MOV PINS instruction. The data written to this pin will always be the least-significant bit of the OUT or MOV data."]
+    #[inline(always)]
+    pub fn set_out_base(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x1f << 0usize)) | (((val as u32) & 0x1f) << 0usize);
+    }
+    #[doc = "The lowest-numbered pin that will be affected by a SET PINS or SET PINDIRS instruction. The data written to this pin is the least-significant bit of the SET data."]
+    #[inline(always)]
+    pub const fn set_base(&self) -> u8 {
+        let val = (self.0 >> 5usize) & 0x1f;
+        val as u8
+    }
+    #[doc = "The lowest-numbered pin that will be affected by a SET PINS or SET PINDIRS instruction. The data written to this pin is the least-significant bit of the SET data."]
+    #[inline(always)]
+    pub fn set_set_base(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x1f << 5usize)) | (((val as u32) & 0x1f) << 5usize);
+    }
+    #[doc = "The lowest-numbered pin that will be affected by a side-set operation. The MSBs of an instruction's side-set/delay field (up to 5, determined by SIDESET_COUNT) are used for side-set data, with the remaining LSBs used for delay. The least-significant bit of the side-set portion is the bit written to this pin, with more-significant bits written to higher-numbered pins."]
+    #[inline(always)]
+    pub const fn sideset_base(&self) -> u8 {
+        let val = (self.0 >> 10usize) & 0x1f;
+        val as u8
+    }
+    #[doc = "The lowest-numbered pin that will be affected by a side-set operation. The MSBs of an instruction's side-set/delay field (up to 5, determined by SIDESET_COUNT) are used for side-set data, with the remaining LSBs used for delay. The least-significant bit of the side-set portion is the bit written to this pin, with more-significant bits written to higher-numbered pins."]
+    #[inline(always)]
+    pub fn set_sideset_base(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x1f << 10usize)) | (((val as u32) & 0x1f) << 10usize);
+    }
+    #[doc = "The pin which is mapped to the least-significant bit of a state machine's IN data bus. Higher-numbered pins are mapped to consecutively more-significant data bits, with a modulo of 32 applied to pin number."]
+    #[inline(always)]
+    pub const fn in_base(&self) -> u8 {
+        let val = (self.0 >> 15usize) & 0x1f;
+        val as u8
+    }
+    #[doc = "The pin which is mapped to the least-significant bit of a state machine's IN data bus. Higher-numbered pins are mapped to consecutively more-significant data bits, with a modulo of 32 applied to pin number."]
+    #[inline(always)]
+    pub fn set_in_base(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x1f << 15usize)) | (((val as u32) & 0x1f) << 15usize);
+    }
+    #[doc = "The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV PINS instruction. In the range 0 to 32 inclusive."]
+    #[inline(always)]
+    pub const fn out_count(&self) -> u8 {
+        let val = (self.0 >> 20usize) & 0x3f;
+        val as u8
+    }
+    #[doc = "The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV PINS instruction. In the range 0 to 32 inclusive."]
+    #[inline(always)]
+    pub fn set_out_count(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x3f << 20usize)) | (((val as u32) & 0x3f) << 20usize);
+    }
+    #[doc = "The number of pins asserted by a SET. In the range 0 to 5 inclusive."]
+    #[inline(always)]
+    pub const fn set_count(&self) -> u8 {
+        let val = (self.0 >> 26usize) & 0x07;
+        val as u8
+    }
+    #[doc = "The number of pins asserted by a SET. In the range 0 to 5 inclusive."]
+    #[inline(always)]
+    pub fn set_set_count(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x07 << 26usize)) | (((val as u32) & 0x07) << 26usize);
+    }
+    #[doc = "The number of MSBs of the Delay/Side-set instruction field which are used for side-set. Inclusive of the enable bit, if present. Minimum of 0 (all delay bits, no side-set) and maximum of 5 (all side-set, no delay)."]
+    #[inline(always)]
+    pub const fn sideset_count(&self) -> u8 {
+        let val = (self.0 >> 29usize) & 0x07;
+        val as u8
+    }
+    #[doc = "The number of MSBs of the Delay/Side-set instruction field which are used for side-set. Inclusive of the enable bit, if present. Minimum of 0 (all delay bits, no side-set) and maximum of 5 (all side-set, no delay)."]
+    #[inline(always)]
+    pub fn set_sideset_count(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x07 << 29usize)) | (((val as u32) & 0x07) << 29usize);
+    }
+}
+impl Default for SmPinctrl {
+    #[inline(always)]
+    fn default() -> SmPinctrl {
+        SmPinctrl(0)
+    }
+}
+#[doc = "Control behaviour of the input/output shift registers for state machine 3"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct SmShiftctrl(pub u32);
+impl SmShiftctrl {
+    #[doc = "Set the number of pins which are not masked to 0 when read by an IN PINS, WAIT PIN or MOV x, PINS instruction. For example, an IN_COUNT of 5 means that the 5 LSBs of the IN pin group are visible (bits 4:0), but the remaining 27 MSBs are masked to 0. A count of 32 is encoded with a field value of 0, so the default behaviour is to not perform any masking. Note this masking is applied in addition to the masking usually performed by the IN instruction. This is mainly useful for the MOV x, PINS instruction, which otherwise has no way of masking pins."]
+    #[inline(always)]
+    pub const fn in_count(&self) -> u8 {
+        let val = (self.0 >> 0usize) & 0x1f;
+        val as u8
+    }
+    #[doc = "Set the number of pins which are not masked to 0 when read by an IN PINS, WAIT PIN or MOV x, PINS instruction. For example, an IN_COUNT of 5 means that the 5 LSBs of the IN pin group are visible (bits 4:0), but the remaining 27 MSBs are masked to 0. A count of 32 is encoded with a field value of 0, so the default behaviour is to not perform any masking. Note this masking is applied in addition to the masking usually performed by the IN instruction. This is mainly useful for the MOV x, PINS instruction, which otherwise has no way of masking pins."]
+    #[inline(always)]
+    pub fn set_in_count(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x1f << 0usize)) | (((val as u32) & 0x1f) << 0usize);
+    }
+    #[doc = "If 1, disable this state machine's RX FIFO, make its storage available for random read access by the state machine (using the `get` instruction) and, unless FJOIN_RX_PUT is also set, random write access by the processor (through the RXFx_PUTGETy registers). If FJOIN_RX_PUT and FJOIN_RX_GET are both set, then the RX FIFO's registers can be randomly read/written by the state machine, but are completely inaccessible to the processor. Setting this bit will clear the FJOIN_TX and FJOIN_RX bits."]
+    #[inline(always)]
+    pub const fn fjoin_rx_get(&self) -> bool {
+        let val = (self.0 >> 14usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, disable this state machine's RX FIFO, make its storage available for random read access by the state machine (using the `get` instruction) and, unless FJOIN_RX_PUT is also set, random write access by the processor (through the RXFx_PUTGETy registers). If FJOIN_RX_PUT and FJOIN_RX_GET are both set, then the RX FIFO's registers can be randomly read/written by the state machine, but are completely inaccessible to the processor. Setting this bit will clear the FJOIN_TX and FJOIN_RX bits."]
+    #[inline(always)]
+    pub fn set_fjoin_rx_get(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize);
+    }
+    #[doc = "If 1, disable this state machine's RX FIFO, make its storage available for random write access by the state machine (using the `put` instruction) and, unless FJOIN_RX_GET is also set, random read access by the processor (through the RXFx_PUTGETy registers). If FJOIN_RX_PUT and FJOIN_RX_GET are both set, then the RX FIFO's registers can be randomly read/written by the state machine, but are completely inaccessible to the processor. Setting this bit will clear the FJOIN_TX and FJOIN_RX bits."]
+    #[inline(always)]
+    pub const fn fjoin_rx_put(&self) -> bool {
+        let val = (self.0 >> 15usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, disable this state machine's RX FIFO, make its storage available for random write access by the state machine (using the `put` instruction) and, unless FJOIN_RX_GET is also set, random read access by the processor (through the RXFx_PUTGETy registers). If FJOIN_RX_PUT and FJOIN_RX_GET are both set, then the RX FIFO's registers can be randomly read/written by the state machine, but are completely inaccessible to the processor. Setting this bit will clear the FJOIN_TX and FJOIN_RX bits."]
+    #[inline(always)]
+    pub fn set_fjoin_rx_put(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize);
+    }
+    #[doc = "Push automatically when the input shift register is filled, i.e. on an IN instruction which causes the input shift counter to reach or exceed PUSH_THRESH."]
+    #[inline(always)]
+    pub const fn autopush(&self) -> bool {
+        let val = (self.0 >> 16usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Push automatically when the input shift register is filled, i.e. on an IN instruction which causes the input shift counter to reach or exceed PUSH_THRESH."]
+    #[inline(always)]
+    pub fn set_autopush(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
+    }
+    #[doc = "Pull automatically when the output shift register is emptied, i.e. on or following an OUT instruction which causes the output shift counter to reach or exceed PULL_THRESH."]
+    #[inline(always)]
+    pub const fn autopull(&self) -> bool {
+        let val = (self.0 >> 17usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Pull automatically when the output shift register is emptied, i.e. on or following an OUT instruction which causes the output shift counter to reach or exceed PULL_THRESH."]
+    #[inline(always)]
+    pub fn set_autopull(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
+    }
+    #[doc = "1 = shift input shift register to right (data enters from left). 0 = to left."]
+    #[inline(always)]
+    pub const fn in_shiftdir(&self) -> bool {
+        let val = (self.0 >> 18usize) & 0x01;
+        val != 0
+    }
+    #[doc = "1 = shift input shift register to right (data enters from left). 0 = to left."]
+    #[inline(always)]
+    pub fn set_in_shiftdir(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize);
+    }
+    #[doc = "1 = shift out of output shift register to right. 0 = to left."]
+    #[inline(always)]
+    pub const fn out_shiftdir(&self) -> bool {
+        let val = (self.0 >> 19usize) & 0x01;
+        val != 0
+    }
+    #[doc = "1 = shift out of output shift register to right. 0 = to left."]
+    #[inline(always)]
+    pub fn set_out_shiftdir(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize);
+    }
+    #[doc = "Number of bits shifted into ISR before autopush, or conditional push (PUSH IFFULL), will take place. Write 0 for value of 32."]
+    #[inline(always)]
+    pub const fn push_thresh(&self) -> u8 {
+        let val = (self.0 >> 20usize) & 0x1f;
+        val as u8
+    }
+    #[doc = "Number of bits shifted into ISR before autopush, or conditional push (PUSH IFFULL), will take place. Write 0 for value of 32."]
+    #[inline(always)]
+    pub fn set_push_thresh(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x1f << 20usize)) | (((val as u32) & 0x1f) << 20usize);
+    }
+    #[doc = "Number of bits shifted out of OSR before autopull, or conditional pull (PULL IFEMPTY), will take place. Write 0 for value of 32."]
+    #[inline(always)]
+    pub const fn pull_thresh(&self) -> u8 {
+        let val = (self.0 >> 25usize) & 0x1f;
+        val as u8
+    }
+    #[doc = "Number of bits shifted out of OSR before autopull, or conditional pull (PULL IFEMPTY), will take place. Write 0 for value of 32."]
+    #[inline(always)]
+    pub fn set_pull_thresh(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x1f << 25usize)) | (((val as u32) & 0x1f) << 25usize);
+    }
+    #[doc = "When 1, TX FIFO steals the RX FIFO's storage, and becomes twice as deep. RX FIFO is disabled as a result (always reads as both full and empty). FIFOs are flushed when this bit is changed."]
+    #[inline(always)]
+    pub const fn fjoin_tx(&self) -> bool {
+        let val = (self.0 >> 30usize) & 0x01;
+        val != 0
+    }
+    #[doc = "When 1, TX FIFO steals the RX FIFO's storage, and becomes twice as deep. RX FIFO is disabled as a result (always reads as both full and empty). FIFOs are flushed when this bit is changed."]
+    #[inline(always)]
+    pub fn set_fjoin_tx(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 30usize)) | (((val as u32) & 0x01) << 30usize);
+    }
+    #[doc = "When 1, RX FIFO steals the TX FIFO's storage, and becomes twice as deep. TX FIFO is disabled as a result (always reads as both full and empty). FIFOs are flushed when this bit is changed."]
+    #[inline(always)]
+    pub const fn fjoin_rx(&self) -> bool {
+        let val = (self.0 >> 31usize) & 0x01;
+        val != 0
+    }
+    #[doc = "When 1, RX FIFO steals the TX FIFO's storage, and becomes twice as deep. TX FIFO is disabled as a result (always reads as both full and empty). FIFOs are flushed when this bit is changed."]
+    #[inline(always)]
+    pub fn set_fjoin_rx(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 31usize)) | (((val as u32) & 0x01) << 31usize);
+    }
+}
+impl Default for SmShiftctrl {
+    #[inline(always)]
+    fn default() -> SmShiftctrl {
+        SmShiftctrl(0)
+    }
+}
diff --git a/src/rp2350/pio/vals.rs b/src/rp2350/pio/vals.rs
new file mode 100644
index 00000000..9f61b3b2
--- /dev/null
+++ b/src/rp2350/pio/vals.rs
@@ -0,0 +1,108 @@
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub struct ExecctrlStatusN(pub u8);
+impl ExecctrlStatusN {
+    #[doc = "Index 0-7 of an IRQ flag in this PIO block"]
+    pub const IRQ: Self = Self(0);
+    #[doc = "Index 0-7 of an IRQ flag in the next lower-numbered PIO block"]
+    pub const IRQ_PREVPIO: Self = Self(0x08);
+    #[doc = "Index 0-7 of an IRQ flag in the next higher-numbered PIO block"]
+    pub const IRQ_NEXTPIO: Self = Self(0x10);
+}
+impl ExecctrlStatusN {
+    pub const fn from_bits(val: u8) -> ExecctrlStatusN {
+        Self(val & 0x1f)
+    }
+    pub const fn to_bits(self) -> u8 {
+        self.0
+    }
+}
+impl From<u8> for ExecctrlStatusN {
+    #[inline(always)]
+    fn from(val: u8) -> ExecctrlStatusN {
+        ExecctrlStatusN::from_bits(val)
+    }
+}
+impl From<ExecctrlStatusN> for u8 {
+    #[inline(always)]
+    fn from(val: ExecctrlStatusN) -> u8 {
+        ExecctrlStatusN::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum ExecctrlStatusSel {
+    #[doc = "All-ones if TX FIFO level < N, otherwise all-zeroes"]
+    TXLEVEL = 0,
+    #[doc = "All-ones if RX FIFO level < N, otherwise all-zeroes"]
+    RXLEVEL = 0x01,
+    #[doc = "All-ones if the indexed IRQ flag is raised, otherwise all-zeroes"]
+    IRQ = 0x02,
+    _RESERVED_3 = 0x03,
+}
+impl ExecctrlStatusSel {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> ExecctrlStatusSel {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for ExecctrlStatusSel {
+    #[inline(always)]
+    fn from(val: u8) -> ExecctrlStatusSel {
+        ExecctrlStatusSel::from_bits(val)
+    }
+}
+impl From<ExecctrlStatusSel> for u8 {
+    #[inline(always)]
+    fn from(val: ExecctrlStatusSel) -> u8 {
+        ExecctrlStatusSel::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Version {
+    #[doc = "Version 0 (RP2040)"]
+    V0 = 0,
+    #[doc = "Version 1 (RP2350)"]
+    V1 = 0x01,
+    _RESERVED_2 = 0x02,
+    _RESERVED_3 = 0x03,
+    _RESERVED_4 = 0x04,
+    _RESERVED_5 = 0x05,
+    _RESERVED_6 = 0x06,
+    _RESERVED_7 = 0x07,
+    _RESERVED_8 = 0x08,
+    _RESERVED_9 = 0x09,
+    _RESERVED_a = 0x0a,
+    _RESERVED_b = 0x0b,
+    _RESERVED_c = 0x0c,
+    _RESERVED_d = 0x0d,
+    _RESERVED_e = 0x0e,
+    _RESERVED_f = 0x0f,
+}
+impl Version {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Version {
+        unsafe { core::mem::transmute(val & 0x0f) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Version {
+    #[inline(always)]
+    fn from(val: u8) -> Version {
+        Version::from_bits(val)
+    }
+}
+impl From<Version> for u8 {
+    #[inline(always)]
+    fn from(val: Version) -> u8 {
+        Version::to_bits(val)
+    }
+}
diff --git a/src/rp2350/pll.rs b/src/rp2350/pll.rs
new file mode 100644
index 00000000..db4207bc
--- /dev/null
+++ b/src/rp2350/pll.rs
@@ -0,0 +1,57 @@
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Pll {
+    ptr: *mut u8,
+}
+unsafe impl Send for Pll {}
+unsafe impl Sync for Pll {}
+impl Pll {
+    #[inline(always)]
+    pub const unsafe fn from_ptr(ptr: *mut ()) -> Self {
+        Self { ptr: ptr as _ }
+    }
+    #[inline(always)]
+    pub const fn as_ptr(&self) -> *mut () {
+        self.ptr as _
+    }
+    #[doc = "Control and Status GENERAL CONSTRAINTS: Reference clock frequency min=5MHz, max=800MHz Feedback divider min=16, max=320 VCO frequency min=750MHz, max=1600MHz"]
+    #[inline(always)]
+    pub const fn cs(self) -> crate::common::Reg<regs::Cs, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(0usize) as _) }
+    }
+    #[doc = "Controls the PLL power modes."]
+    #[inline(always)]
+    pub const fn pwr(self) -> crate::common::Reg<regs::Pwr, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(4usize) as _) }
+    }
+    #[doc = "Feedback divisor (note: this PLL does not support fractional division)"]
+    #[inline(always)]
+    pub const fn fbdiv_int(self) -> crate::common::Reg<regs::FbdivInt, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(8usize) as _) }
+    }
+    #[doc = "Controls the PLL post dividers for the primary output (note: this PLL does not have a secondary output) the primary output is driven from VCO divided by postdiv1*postdiv2"]
+    #[inline(always)]
+    pub const fn prim(self) -> crate::common::Reg<regs::Prim, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(12usize) as _) }
+    }
+    #[doc = "Raw Interrupts"]
+    #[inline(always)]
+    pub const fn intr(self) -> crate::common::Reg<regs::Intr, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(16usize) as _) }
+    }
+    #[doc = "Interrupt Enable"]
+    #[inline(always)]
+    pub const fn inte(self) -> crate::common::Reg<regs::Inte, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(20usize) as _) }
+    }
+    #[doc = "Interrupt Force"]
+    #[inline(always)]
+    pub const fn intf(self) -> crate::common::Reg<regs::Intf, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(24usize) as _) }
+    }
+    #[doc = "Interrupt status after masking & forcing"]
+    #[inline(always)]
+    pub const fn ints(self) -> crate::common::Reg<regs::Ints, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(28usize) as _) }
+    }
+}
+pub mod regs;
diff --git a/src/rp2350/pll/regs.rs b/src/rp2350/pll/regs.rs
new file mode 100644
index 00000000..92d95d02
--- /dev/null
+++ b/src/rp2350/pll/regs.rs
@@ -0,0 +1,253 @@
+#[doc = "Control and Status GENERAL CONSTRAINTS: Reference clock frequency min=5MHz, max=800MHz Feedback divider min=16, max=320 VCO frequency min=750MHz, max=1600MHz"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Cs(pub u32);
+impl Cs {
+    #[doc = "Divides the PLL input reference clock. Behaviour is undefined for div=0. PLL output will be unpredictable during refdiv changes, wait for lock=1 before using it."]
+    #[inline(always)]
+    pub const fn refdiv(&self) -> u8 {
+        let val = (self.0 >> 0usize) & 0x3f;
+        val as u8
+    }
+    #[doc = "Divides the PLL input reference clock. Behaviour is undefined for div=0. PLL output will be unpredictable during refdiv changes, wait for lock=1 before using it."]
+    #[inline(always)]
+    pub fn set_refdiv(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x3f << 0usize)) | (((val as u32) & 0x3f) << 0usize);
+    }
+    #[doc = "Passes the reference clock to the output instead of the divided VCO. The VCO continues to run so the user can switch between the reference clock and the divided VCO but the output will glitch when doing so."]
+    #[inline(always)]
+    pub const fn bypass(&self) -> bool {
+        let val = (self.0 >> 8usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Passes the reference clock to the output instead of the divided VCO. The VCO continues to run so the user can switch between the reference clock and the divided VCO but the output will glitch when doing so."]
+    #[inline(always)]
+    pub fn set_bypass(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
+    }
+    #[doc = "PLL is not locked Ideally this is cleared when PLL lock is seen and this should never normally be set"]
+    #[inline(always)]
+    pub const fn lock_n(&self) -> bool {
+        let val = (self.0 >> 30usize) & 0x01;
+        val != 0
+    }
+    #[doc = "PLL is not locked Ideally this is cleared when PLL lock is seen and this should never normally be set"]
+    #[inline(always)]
+    pub fn set_lock_n(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 30usize)) | (((val as u32) & 0x01) << 30usize);
+    }
+    #[doc = "PLL is locked"]
+    #[inline(always)]
+    pub const fn lock(&self) -> bool {
+        let val = (self.0 >> 31usize) & 0x01;
+        val != 0
+    }
+    #[doc = "PLL is locked"]
+    #[inline(always)]
+    pub fn set_lock(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 31usize)) | (((val as u32) & 0x01) << 31usize);
+    }
+}
+impl Default for Cs {
+    #[inline(always)]
+    fn default() -> Cs {
+        Cs(0)
+    }
+}
+#[doc = "Feedback divisor (note: this PLL does not support fractional division)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct FbdivInt(pub u32);
+impl FbdivInt {
+    #[doc = "see ctrl reg description for constraints"]
+    #[inline(always)]
+    pub const fn fbdiv_int(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0x0fff;
+        val as u16
+    }
+    #[doc = "see ctrl reg description for constraints"]
+    #[inline(always)]
+    pub fn set_fbdiv_int(&mut self, val: u16) {
+        self.0 = (self.0 & !(0x0fff << 0usize)) | (((val as u32) & 0x0fff) << 0usize);
+    }
+}
+impl Default for FbdivInt {
+    #[inline(always)]
+    fn default() -> FbdivInt {
+        FbdivInt(0)
+    }
+}
+#[doc = "Interrupt Enable"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Inte(pub u32);
+impl Inte {
+    #[inline(always)]
+    pub const fn lock_n_sticky(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_lock_n_sticky(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+}
+impl Default for Inte {
+    #[inline(always)]
+    fn default() -> Inte {
+        Inte(0)
+    }
+}
+#[doc = "Interrupt Force"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Intf(pub u32);
+impl Intf {
+    #[inline(always)]
+    pub const fn lock_n_sticky(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_lock_n_sticky(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+}
+impl Default for Intf {
+    #[inline(always)]
+    fn default() -> Intf {
+        Intf(0)
+    }
+}
+#[doc = "Raw Interrupts"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Intr(pub u32);
+impl Intr {
+    #[inline(always)]
+    pub const fn lock_n_sticky(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_lock_n_sticky(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+}
+impl Default for Intr {
+    #[inline(always)]
+    fn default() -> Intr {
+        Intr(0)
+    }
+}
+#[doc = "Interrupt status after masking & forcing"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Ints(pub u32);
+impl Ints {
+    #[inline(always)]
+    pub const fn lock_n_sticky(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_lock_n_sticky(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+}
+impl Default for Ints {
+    #[inline(always)]
+    fn default() -> Ints {
+        Ints(0)
+    }
+}
+#[doc = "Controls the PLL post dividers for the primary output (note: this PLL does not have a secondary output) the primary output is driven from VCO divided by postdiv1*postdiv2"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Prim(pub u32);
+impl Prim {
+    #[doc = "divide by 1-7"]
+    #[inline(always)]
+    pub const fn postdiv2(&self) -> u8 {
+        let val = (self.0 >> 12usize) & 0x07;
+        val as u8
+    }
+    #[doc = "divide by 1-7"]
+    #[inline(always)]
+    pub fn set_postdiv2(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x07 << 12usize)) | (((val as u32) & 0x07) << 12usize);
+    }
+    #[doc = "divide by 1-7"]
+    #[inline(always)]
+    pub const fn postdiv1(&self) -> u8 {
+        let val = (self.0 >> 16usize) & 0x07;
+        val as u8
+    }
+    #[doc = "divide by 1-7"]
+    #[inline(always)]
+    pub fn set_postdiv1(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x07 << 16usize)) | (((val as u32) & 0x07) << 16usize);
+    }
+}
+impl Default for Prim {
+    #[inline(always)]
+    fn default() -> Prim {
+        Prim(0)
+    }
+}
+#[doc = "Controls the PLL power modes."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Pwr(pub u32);
+impl Pwr {
+    #[doc = "PLL powerdown To save power set high when PLL output not required."]
+    #[inline(always)]
+    pub const fn pd(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "PLL powerdown To save power set high when PLL output not required."]
+    #[inline(always)]
+    pub fn set_pd(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[doc = "PLL DSM powerdown Nothing is achieved by setting this low."]
+    #[inline(always)]
+    pub const fn dsmpd(&self) -> bool {
+        let val = (self.0 >> 2usize) & 0x01;
+        val != 0
+    }
+    #[doc = "PLL DSM powerdown Nothing is achieved by setting this low."]
+    #[inline(always)]
+    pub fn set_dsmpd(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+    }
+    #[doc = "PLL post divider powerdown To save power set high when PLL output not required or bypass=1."]
+    #[inline(always)]
+    pub const fn postdivpd(&self) -> bool {
+        let val = (self.0 >> 3usize) & 0x01;
+        val != 0
+    }
+    #[doc = "PLL post divider powerdown To save power set high when PLL output not required or bypass=1."]
+    #[inline(always)]
+    pub fn set_postdivpd(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
+    }
+    #[doc = "PLL VCO powerdown To save power set high when PLL output not required or bypass=1."]
+    #[inline(always)]
+    pub const fn vcopd(&self) -> bool {
+        let val = (self.0 >> 5usize) & 0x01;
+        val != 0
+    }
+    #[doc = "PLL VCO powerdown To save power set high when PLL output not required or bypass=1."]
+    #[inline(always)]
+    pub fn set_vcopd(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
+    }
+}
+impl Default for Pwr {
+    #[inline(always)]
+    fn default() -> Pwr {
+        Pwr(0)
+    }
+}
diff --git a/src/rp2350/powman.rs b/src/rp2350/powman.rs
new file mode 100644
index 00000000..e321669a
--- /dev/null
+++ b/src/rp2350/powman.rs
@@ -0,0 +1,331 @@
+#[doc = "Controls vreg, bor, lposc, chip resets & xosc startup, powman and provides scratch register for general use and for bootcode use"]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Powman {
+    ptr: *mut u8,
+}
+unsafe impl Send for Powman {}
+unsafe impl Sync for Powman {}
+impl Powman {
+    #[inline(always)]
+    pub const unsafe fn from_ptr(ptr: *mut ()) -> Self {
+        Self { ptr: ptr as _ }
+    }
+    #[inline(always)]
+    pub const fn as_ptr(&self) -> *mut () {
+        self.ptr as _
+    }
+    #[doc = "Indicates a bad password has been used"]
+    #[inline(always)]
+    pub const fn badpasswd(self) -> crate::common::Reg<regs::Badpasswd, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(0usize) as _) }
+    }
+    #[doc = "Voltage Regulator Control"]
+    #[inline(always)]
+    pub const fn vreg_ctrl(self) -> crate::common::Reg<regs::VregCtrl, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(4usize) as _) }
+    }
+    #[doc = "Voltage Regulator Status"]
+    #[inline(always)]
+    pub const fn vreg_sts(self) -> crate::common::Reg<regs::VregSts, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(8usize) as _) }
+    }
+    #[doc = "Voltage Regulator Settings"]
+    #[inline(always)]
+    pub const fn vreg(self) -> crate::common::Reg<regs::Vreg, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(12usize) as _) }
+    }
+    #[doc = "Voltage Regulator Low Power Entry Settings"]
+    #[inline(always)]
+    pub const fn vreg_lp_entry(self) -> crate::common::Reg<regs::VregLpEntry, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(16usize) as _) }
+    }
+    #[doc = "Voltage Regulator Low Power Exit Settings"]
+    #[inline(always)]
+    pub const fn vreg_lp_exit(self) -> crate::common::Reg<regs::VregLpExit, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(20usize) as _) }
+    }
+    #[doc = "Brown-out Detection Control"]
+    #[inline(always)]
+    pub const fn bod_ctrl(self) -> crate::common::Reg<regs::BodCtrl, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(24usize) as _) }
+    }
+    #[doc = "Brown-out Detection Settings"]
+    #[inline(always)]
+    pub const fn bod(self) -> crate::common::Reg<regs::Bod, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(28usize) as _) }
+    }
+    #[doc = "Brown-out Detection Low Power Entry Settings"]
+    #[inline(always)]
+    pub const fn bod_lp_entry(self) -> crate::common::Reg<regs::BodLpEntry, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(32usize) as _) }
+    }
+    #[doc = "Brown-out Detection Low Power Exit Settings"]
+    #[inline(always)]
+    pub const fn bod_lp_exit(self) -> crate::common::Reg<regs::BodLpExit, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(36usize) as _) }
+    }
+    #[doc = "Low power oscillator control register."]
+    #[inline(always)]
+    pub const fn lposc(self) -> crate::common::Reg<regs::Lposc, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(40usize) as _) }
+    }
+    #[doc = "Chip reset control and status"]
+    #[inline(always)]
+    pub const fn chip_reset(self) -> crate::common::Reg<regs::ChipReset, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(44usize) as _) }
+    }
+    #[doc = "Allows a watchdog reset to reset the internal state of powman in addition to the power-on state machine (PSM). Note that powman ignores watchdog resets that do not select at least the CLOCKS stage or earlier stages in the PSM. If using these bits, it's recommended to set PSM_WDSEL to all-ones in addition to the desired bits in this register. Failing to select CLOCKS or earlier will result in the POWMAN_WDSEL register having no effect."]
+    #[inline(always)]
+    pub const fn wdsel(self) -> crate::common::Reg<regs::Wdsel, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(48usize) as _) }
+    }
+    #[doc = "For configuration of the power sequencer Writes are ignored while POWMAN_STATE_CHANGING=1"]
+    #[inline(always)]
+    pub const fn seq_cfg(self) -> crate::common::Reg<regs::SeqCfg, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(52usize) as _) }
+    }
+    #[doc = "This register controls the power state of the 4 power domains. The current power state is indicated in POWMAN_STATE_CURRENT which is read-only. To change the state, write to POWMAN_STATE_REQ. The coding of POWMAN_STATE_CURRENT & POWMAN_STATE_REQ corresponds to the power states defined in the datasheet: bit 3 = SWCORE bit 2 = XIP cache bit 1 = SRAM0 bit 0 = SRAM1 0 = powered up 1 = powered down When POWMAN_STATE_REQ is written, the POWMAN_STATE_WAITING flag is set while the Power Manager determines what is required. If an invalid transition is requested the Power Manager will still register the request in POWMAN_STATE_REQ but will also set the POWMAN_BAD_REQ flag. It will then implement the power-up requests and ignore the power down requests. To do nothing would risk entering an unrecoverable lock-up state. Invalid requests are: any combination of power up and power down requests any request that results in swcore boing powered and xip unpowered If the request is to power down the switched-core domain then POWMAN_STATE_WAITING stays active until the processors halt. During this time the POWMAN_STATE_REQ field can be re-written to change or cancel the request. When the power state transition begins the POWMAN_STATE_WAITING_flag is cleared, the POWMAN_STATE_CHANGING flag is set and POWMAN register writes are ignored until the transition completes."]
+    #[inline(always)]
+    pub const fn state(self) -> crate::common::Reg<regs::State, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(56usize) as _) }
+    }
+    #[inline(always)]
+    pub const fn pow_fastdiv(self) -> crate::common::Reg<regs::PowFastdiv, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(60usize) as _) }
+    }
+    #[doc = "power state machine delays"]
+    #[inline(always)]
+    pub const fn pow_delay(self) -> crate::common::Reg<regs::PowDelay, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(64usize) as _) }
+    }
+    #[doc = "Configures a gpio as a power mode aware control output"]
+    #[inline(always)]
+    pub const fn ext_ctrl0(self) -> crate::common::Reg<regs::ExtCtrl0, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(68usize) as _) }
+    }
+    #[doc = "Configures a gpio as a power mode aware control output"]
+    #[inline(always)]
+    pub const fn ext_ctrl1(self) -> crate::common::Reg<regs::ExtCtrl1, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(72usize) as _) }
+    }
+    #[doc = "Select a GPIO to use as a time reference, the source can be used to drive the low power clock at 32kHz, or to provide a 1ms tick to the timer, or provide a 1Hz tick to the timer. The tick selection is controlled by the POWMAN_TIMER register."]
+    #[inline(always)]
+    pub const fn ext_time_ref(self) -> crate::common::Reg<regs::ExtTimeRef, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(76usize) as _) }
+    }
+    #[doc = "Informs the AON Timer of the integer component of the clock frequency when running off the LPOSC."]
+    #[inline(always)]
+    pub const fn lposc_freq_khz_int(
+        self,
+    ) -> crate::common::Reg<regs::LposcFreqKhzInt, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(80usize) as _) }
+    }
+    #[doc = "Informs the AON Timer of the fractional component of the clock frequency when running off the LPOSC."]
+    #[inline(always)]
+    pub const fn lposc_freq_khz_frac(
+        self,
+    ) -> crate::common::Reg<regs::LposcFreqKhzFrac, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(84usize) as _) }
+    }
+    #[doc = "Informs the AON Timer of the integer component of the clock frequency when running off the XOSC."]
+    #[inline(always)]
+    pub const fn xosc_freq_khz_int(
+        self,
+    ) -> crate::common::Reg<regs::XoscFreqKhzInt, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(88usize) as _) }
+    }
+    #[doc = "Informs the AON Timer of the fractional component of the clock frequency when running off the XOSC."]
+    #[inline(always)]
+    pub const fn xosc_freq_khz_frac(
+        self,
+    ) -> crate::common::Reg<regs::XoscFreqKhzFrac, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(92usize) as _) }
+    }
+    #[inline(always)]
+    pub const fn set_time_63to48(
+        self,
+    ) -> crate::common::Reg<regs::SetTime63to48, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(96usize) as _) }
+    }
+    #[inline(always)]
+    pub const fn set_time_47to32(
+        self,
+    ) -> crate::common::Reg<regs::SetTime47to32, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(100usize) as _) }
+    }
+    #[inline(always)]
+    pub const fn set_time_31to16(
+        self,
+    ) -> crate::common::Reg<regs::SetTime31to16, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(104usize) as _) }
+    }
+    #[inline(always)]
+    pub const fn set_time_15to0(self) -> crate::common::Reg<regs::SetTime15to0, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(108usize) as _) }
+    }
+    #[inline(always)]
+    pub const fn read_time_upper(self) -> crate::common::Reg<u32, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(112usize) as _) }
+    }
+    #[inline(always)]
+    pub const fn read_time_lower(self) -> crate::common::Reg<u32, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(116usize) as _) }
+    }
+    #[inline(always)]
+    pub const fn alarm_time_63to48(
+        self,
+    ) -> crate::common::Reg<regs::AlarmTime63to48, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(120usize) as _) }
+    }
+    #[inline(always)]
+    pub const fn alarm_time_47to32(
+        self,
+    ) -> crate::common::Reg<regs::AlarmTime47to32, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(124usize) as _) }
+    }
+    #[inline(always)]
+    pub const fn alarm_time_31to16(
+        self,
+    ) -> crate::common::Reg<regs::AlarmTime31to16, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(128usize) as _) }
+    }
+    #[inline(always)]
+    pub const fn alarm_time_15to0(
+        self,
+    ) -> crate::common::Reg<regs::AlarmTime15to0, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(132usize) as _) }
+    }
+    #[inline(always)]
+    pub const fn timer(self) -> crate::common::Reg<regs::Timer, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(136usize) as _) }
+    }
+    #[doc = "4 GPIO powerup events can be configured to wake the chip up from a low power state. The pwrups are level/edge sensitive and can be set to trigger on a high/rising or low/falling event The number of gpios available depends on the package option. An invalid selection will be ignored source = 0 selects gpio0 . . source = 47 selects gpio47 source = 48 selects qspi_ss source = 49 selects qspi_sd0 source = 50 selects qspi_sd1 source = 51 selects qspi_sd2 source = 52 selects qspi_sd3 source = 53 selects qspi_sclk level = 0 triggers the pwrup when the source is low level = 1 triggers the pwrup when the source is high"]
+    #[inline(always)]
+    pub const fn pwrup0(self) -> crate::common::Reg<regs::Pwrup0, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(140usize) as _) }
+    }
+    #[doc = "4 GPIO powerup events can be configured to wake the chip up from a low power state. The pwrups are level/edge sensitive and can be set to trigger on a high/rising or low/falling event The number of gpios available depends on the package option. An invalid selection will be ignored source = 0 selects gpio0 . . source = 47 selects gpio47 source = 48 selects qspi_ss source = 49 selects qspi_sd0 source = 50 selects qspi_sd1 source = 51 selects qspi_sd2 source = 52 selects qspi_sd3 source = 53 selects qspi_sclk level = 0 triggers the pwrup when the source is low level = 1 triggers the pwrup when the source is high"]
+    #[inline(always)]
+    pub const fn pwrup1(self) -> crate::common::Reg<regs::Pwrup1, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(144usize) as _) }
+    }
+    #[doc = "4 GPIO powerup events can be configured to wake the chip up from a low power state. The pwrups are level/edge sensitive and can be set to trigger on a high/rising or low/falling event The number of gpios available depends on the package option. An invalid selection will be ignored source = 0 selects gpio0 . . source = 47 selects gpio47 source = 48 selects qspi_ss source = 49 selects qspi_sd0 source = 50 selects qspi_sd1 source = 51 selects qspi_sd2 source = 52 selects qspi_sd3 source = 53 selects qspi_sclk level = 0 triggers the pwrup when the source is low level = 1 triggers the pwrup when the source is high"]
+    #[inline(always)]
+    pub const fn pwrup2(self) -> crate::common::Reg<regs::Pwrup2, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(148usize) as _) }
+    }
+    #[doc = "4 GPIO powerup events can be configured to wake the chip up from a low power state. The pwrups are level/edge sensitive and can be set to trigger on a high/rising or low/falling event The number of gpios available depends on the package option. An invalid selection will be ignored source = 0 selects gpio0 . . source = 47 selects gpio47 source = 48 selects qspi_ss source = 49 selects qspi_sd0 source = 50 selects qspi_sd1 source = 51 selects qspi_sd2 source = 52 selects qspi_sd3 source = 53 selects qspi_sclk level = 0 triggers the pwrup when the source is low level = 1 triggers the pwrup when the source is high"]
+    #[inline(always)]
+    pub const fn pwrup3(self) -> crate::common::Reg<regs::Pwrup3, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(152usize) as _) }
+    }
+    #[doc = "Indicates current powerup request state pwrup events can be cleared by removing the enable from the pwrup register. The alarm pwrup req can be cleared by clearing timer.alarm_enab 0 = chip reset, for the source of the last reset see POWMAN_CHIP_RESET 1 = pwrup0 2 = pwrup1 3 = pwrup2 4 = pwrup3 5 = coresight_pwrup 6 = alarm_pwrup"]
+    #[inline(always)]
+    pub const fn current_pwrup_req(
+        self,
+    ) -> crate::common::Reg<regs::CurrentPwrupReq, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(156usize) as _) }
+    }
+    #[doc = "Indicates which pwrup source triggered the last switched-core power up 0 = chip reset, for the source of the last reset see POWMAN_CHIP_RESET 1 = pwrup0 2 = pwrup1 3 = pwrup2 4 = pwrup3 5 = coresight_pwrup 6 = alarm_pwrup"]
+    #[inline(always)]
+    pub const fn last_swcore_pwrup(
+        self,
+    ) -> crate::common::Reg<regs::LastSwcorePwrup, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(160usize) as _) }
+    }
+    #[inline(always)]
+    pub const fn dbg_pwrcfg(self) -> crate::common::Reg<regs::DbgPwrcfg, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(164usize) as _) }
+    }
+    #[doc = "Tell the bootrom to ignore the BOOT0..3 registers following the next RSM reset (e.g. the next core power down/up). If an early boot stage has soft-locked some OTP pages in order to protect their contents from later stages, there is a risk that Secure code running at a later stage can unlock the pages by powering the core up and down. This register can be used to ensure that the bootloader runs as normal on the next power up, preventing Secure code at a later stage from accessing OTP in its unlocked state. Should be used in conjunction with the OTP BOOTDIS register."]
+    #[inline(always)]
+    pub const fn bootdis(self) -> crate::common::Reg<regs::Bootdis, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(168usize) as _) }
+    }
+    #[inline(always)]
+    pub const fn dbgconfig(self) -> crate::common::Reg<regs::Dbgconfig, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(172usize) as _) }
+    }
+    #[doc = "Scratch register. Information persists in low power mode"]
+    #[inline(always)]
+    pub const fn scratch0(self) -> crate::common::Reg<u32, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(176usize) as _) }
+    }
+    #[doc = "Scratch register. Information persists in low power mode"]
+    #[inline(always)]
+    pub const fn scratch1(self) -> crate::common::Reg<u32, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(180usize) as _) }
+    }
+    #[doc = "Scratch register. Information persists in low power mode"]
+    #[inline(always)]
+    pub const fn scratch2(self) -> crate::common::Reg<u32, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(184usize) as _) }
+    }
+    #[doc = "Scratch register. Information persists in low power mode"]
+    #[inline(always)]
+    pub const fn scratch3(self) -> crate::common::Reg<u32, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(188usize) as _) }
+    }
+    #[doc = "Scratch register. Information persists in low power mode"]
+    #[inline(always)]
+    pub const fn scratch4(self) -> crate::common::Reg<u32, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(192usize) as _) }
+    }
+    #[doc = "Scratch register. Information persists in low power mode"]
+    #[inline(always)]
+    pub const fn scratch5(self) -> crate::common::Reg<u32, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(196usize) as _) }
+    }
+    #[doc = "Scratch register. Information persists in low power mode"]
+    #[inline(always)]
+    pub const fn scratch6(self) -> crate::common::Reg<u32, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(200usize) as _) }
+    }
+    #[doc = "Scratch register. Information persists in low power mode"]
+    #[inline(always)]
+    pub const fn scratch7(self) -> crate::common::Reg<u32, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(204usize) as _) }
+    }
+    #[doc = "Scratch register. Information persists in low power mode"]
+    #[inline(always)]
+    pub const fn boot0(self) -> crate::common::Reg<u32, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(208usize) as _) }
+    }
+    #[doc = "Scratch register. Information persists in low power mode"]
+    #[inline(always)]
+    pub const fn boot1(self) -> crate::common::Reg<u32, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(212usize) as _) }
+    }
+    #[doc = "Scratch register. Information persists in low power mode"]
+    #[inline(always)]
+    pub const fn boot2(self) -> crate::common::Reg<u32, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(216usize) as _) }
+    }
+    #[doc = "Scratch register. Information persists in low power mode"]
+    #[inline(always)]
+    pub const fn boot3(self) -> crate::common::Reg<u32, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(220usize) as _) }
+    }
+    #[doc = "Raw Interrupts"]
+    #[inline(always)]
+    pub const fn intr(self) -> crate::common::Reg<regs::Intr, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(224usize) as _) }
+    }
+    #[doc = "Interrupt Enable"]
+    #[inline(always)]
+    pub const fn inte(self) -> crate::common::Reg<regs::Inte, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(228usize) as _) }
+    }
+    #[doc = "Interrupt Force"]
+    #[inline(always)]
+    pub const fn intf(self) -> crate::common::Reg<regs::Intf, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(232usize) as _) }
+    }
+    #[doc = "Interrupt status after masking & forcing"]
+    #[inline(always)]
+    pub const fn ints(self) -> crate::common::Reg<regs::Ints, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(236usize) as _) }
+    }
+}
+pub mod regs;
+pub mod vals;
diff --git a/src/rp2350/powman/regs.rs b/src/rp2350/powman/regs.rs
new file mode 100644
index 00000000..059ae24a
--- /dev/null
+++ b/src/rp2350/powman/regs.rs
@@ -0,0 +1,2145 @@
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct AlarmTime15to0(pub u32);
+impl AlarmTime15to0 {
+    #[doc = "This field must only be written when POWMAN_ALARM_ENAB=0"]
+    #[inline(always)]
+    pub const fn alarm_time_15to0(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0xffff;
+        val as u16
+    }
+    #[doc = "This field must only be written when POWMAN_ALARM_ENAB=0"]
+    #[inline(always)]
+    pub fn set_alarm_time_15to0(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+    }
+}
+impl Default for AlarmTime15to0 {
+    #[inline(always)]
+    fn default() -> AlarmTime15to0 {
+        AlarmTime15to0(0)
+    }
+}
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct AlarmTime31to16(pub u32);
+impl AlarmTime31to16 {
+    #[doc = "This field must only be written when POWMAN_ALARM_ENAB=0"]
+    #[inline(always)]
+    pub const fn alarm_time_31to16(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0xffff;
+        val as u16
+    }
+    #[doc = "This field must only be written when POWMAN_ALARM_ENAB=0"]
+    #[inline(always)]
+    pub fn set_alarm_time_31to16(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+    }
+}
+impl Default for AlarmTime31to16 {
+    #[inline(always)]
+    fn default() -> AlarmTime31to16 {
+        AlarmTime31to16(0)
+    }
+}
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct AlarmTime47to32(pub u32);
+impl AlarmTime47to32 {
+    #[doc = "This field must only be written when POWMAN_ALARM_ENAB=0"]
+    #[inline(always)]
+    pub const fn alarm_time_47to32(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0xffff;
+        val as u16
+    }
+    #[doc = "This field must only be written when POWMAN_ALARM_ENAB=0"]
+    #[inline(always)]
+    pub fn set_alarm_time_47to32(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+    }
+}
+impl Default for AlarmTime47to32 {
+    #[inline(always)]
+    fn default() -> AlarmTime47to32 {
+        AlarmTime47to32(0)
+    }
+}
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct AlarmTime63to48(pub u32);
+impl AlarmTime63to48 {
+    #[doc = "This field must only be written when POWMAN_ALARM_ENAB=0"]
+    #[inline(always)]
+    pub const fn alarm_time_63to48(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0xffff;
+        val as u16
+    }
+    #[doc = "This field must only be written when POWMAN_ALARM_ENAB=0"]
+    #[inline(always)]
+    pub fn set_alarm_time_63to48(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+    }
+}
+impl Default for AlarmTime63to48 {
+    #[inline(always)]
+    fn default() -> AlarmTime63to48 {
+        AlarmTime63to48(0)
+    }
+}
+#[doc = "Indicates a bad password has been used"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Badpasswd(pub u32);
+impl Badpasswd {
+    #[inline(always)]
+    pub const fn badpasswd(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_badpasswd(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+}
+impl Default for Badpasswd {
+    #[inline(always)]
+    fn default() -> Badpasswd {
+        Badpasswd(0)
+    }
+}
+#[doc = "Brown-out Detection Settings"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Bod(pub u32);
+impl Bod {
+    #[doc = "enable brown-out detection 0=not enabled, 1=enabled"]
+    #[inline(always)]
+    pub const fn en(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "enable brown-out detection 0=not enabled, 1=enabled"]
+    #[inline(always)]
+    pub fn set_en(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[doc = "threshold select 00000 - 0.473V 00001 - 0.516V 00010 - 0.559V 00011 - 0.602V 00100 - 0.645VS 00101 - 0.688V 00110 - 0.731V 00111 - 0.774V 01000 - 0.817V 01001 - 0.860V (default) 01010 - 0.903V 01011 - 0.946V 01100 - 0.989V 01101 - 1.032V 01110 - 1.075V 01111 - 1.118V 10000 - 1.161 10001 - 1.204V"]
+    #[inline(always)]
+    pub const fn vsel(&self) -> u8 {
+        let val = (self.0 >> 4usize) & 0x1f;
+        val as u8
+    }
+    #[doc = "threshold select 00000 - 0.473V 00001 - 0.516V 00010 - 0.559V 00011 - 0.602V 00100 - 0.645VS 00101 - 0.688V 00110 - 0.731V 00111 - 0.774V 01000 - 0.817V 01001 - 0.860V (default) 01010 - 0.903V 01011 - 0.946V 01100 - 0.989V 01101 - 1.032V 01110 - 1.075V 01111 - 1.118V 10000 - 1.161 10001 - 1.204V"]
+    #[inline(always)]
+    pub fn set_vsel(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x1f << 4usize)) | (((val as u32) & 0x1f) << 4usize);
+    }
+}
+impl Default for Bod {
+    #[inline(always)]
+    fn default() -> Bod {
+        Bod(0)
+    }
+}
+#[doc = "Brown-out Detection Control"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct BodCtrl(pub u32);
+impl BodCtrl {
+    #[doc = "isolates the brown-out detection control interface 0 - not isolated (default) 1 - isolated"]
+    #[inline(always)]
+    pub const fn isolate(&self) -> bool {
+        let val = (self.0 >> 12usize) & 0x01;
+        val != 0
+    }
+    #[doc = "isolates the brown-out detection control interface 0 - not isolated (default) 1 - isolated"]
+    #[inline(always)]
+    pub fn set_isolate(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
+    }
+}
+impl Default for BodCtrl {
+    #[inline(always)]
+    fn default() -> BodCtrl {
+        BodCtrl(0)
+    }
+}
+#[doc = "Brown-out Detection Low Power Entry Settings"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct BodLpEntry(pub u32);
+impl BodLpEntry {
+    #[doc = "enable brown-out detection 0=not enabled, 1=enabled"]
+    #[inline(always)]
+    pub const fn en(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "enable brown-out detection 0=not enabled, 1=enabled"]
+    #[inline(always)]
+    pub fn set_en(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[doc = "threshold select 00000 - 0.473V 00001 - 0.516V 00010 - 0.559V 00011 - 0.602V 00100 - 0.645VS 00101 - 0.688V 00110 - 0.731V 00111 - 0.774V 01000 - 0.817V 01001 - 0.860V (default) 01010 - 0.903V 01011 - 0.946V 01100 - 0.989V 01101 - 1.032V 01110 - 1.075V 01111 - 1.118V 10000 - 1.161 10001 - 1.204V"]
+    #[inline(always)]
+    pub const fn vsel(&self) -> u8 {
+        let val = (self.0 >> 4usize) & 0x1f;
+        val as u8
+    }
+    #[doc = "threshold select 00000 - 0.473V 00001 - 0.516V 00010 - 0.559V 00011 - 0.602V 00100 - 0.645VS 00101 - 0.688V 00110 - 0.731V 00111 - 0.774V 01000 - 0.817V 01001 - 0.860V (default) 01010 - 0.903V 01011 - 0.946V 01100 - 0.989V 01101 - 1.032V 01110 - 1.075V 01111 - 1.118V 10000 - 1.161 10001 - 1.204V"]
+    #[inline(always)]
+    pub fn set_vsel(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x1f << 4usize)) | (((val as u32) & 0x1f) << 4usize);
+    }
+}
+impl Default for BodLpEntry {
+    #[inline(always)]
+    fn default() -> BodLpEntry {
+        BodLpEntry(0)
+    }
+}
+#[doc = "Brown-out Detection Low Power Exit Settings"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct BodLpExit(pub u32);
+impl BodLpExit {
+    #[doc = "enable brown-out detection 0=not enabled, 1=enabled"]
+    #[inline(always)]
+    pub const fn en(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "enable brown-out detection 0=not enabled, 1=enabled"]
+    #[inline(always)]
+    pub fn set_en(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[doc = "threshold select 00000 - 0.473V 00001 - 0.516V 00010 - 0.559V 00011 - 0.602V 00100 - 0.645VS 00101 - 0.688V 00110 - 0.731V 00111 - 0.774V 01000 - 0.817V 01001 - 0.860V (default) 01010 - 0.903V 01011 - 0.946V 01100 - 0.989V 01101 - 1.032V 01110 - 1.075V 01111 - 1.118V 10000 - 1.161 10001 - 1.204V"]
+    #[inline(always)]
+    pub const fn vsel(&self) -> u8 {
+        let val = (self.0 >> 4usize) & 0x1f;
+        val as u8
+    }
+    #[doc = "threshold select 00000 - 0.473V 00001 - 0.516V 00010 - 0.559V 00011 - 0.602V 00100 - 0.645VS 00101 - 0.688V 00110 - 0.731V 00111 - 0.774V 01000 - 0.817V 01001 - 0.860V (default) 01010 - 0.903V 01011 - 0.946V 01100 - 0.989V 01101 - 1.032V 01110 - 1.075V 01111 - 1.118V 10000 - 1.161 10001 - 1.204V"]
+    #[inline(always)]
+    pub fn set_vsel(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x1f << 4usize)) | (((val as u32) & 0x1f) << 4usize);
+    }
+}
+impl Default for BodLpExit {
+    #[inline(always)]
+    fn default() -> BodLpExit {
+        BodLpExit(0)
+    }
+}
+#[doc = "Tell the bootrom to ignore the BOOT0..3 registers following the next RSM reset (e.g. the next core power down/up). If an early boot stage has soft-locked some OTP pages in order to protect their contents from later stages, there is a risk that Secure code running at a later stage can unlock the pages by powering the core up and down. This register can be used to ensure that the bootloader runs as normal on the next power up, preventing Secure code at a later stage from accessing OTP in its unlocked state. Should be used in conjunction with the OTP BOOTDIS register."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Bootdis(pub u32);
+impl Bootdis {
+    #[doc = "When powman resets the RSM, the current value of BOOTDIS_NEXT is OR'd into BOOTDIS_NOW, and BOOTDIS_NEXT is cleared. The bootrom checks this flag before reading the BOOT0..3 registers. If it is set, the bootrom clears it, and ignores the BOOT registers. This prevents Secure software from diverting the boot path before a bootloader has had the chance to soft lock OTP pages containing sensitive data."]
+    #[inline(always)]
+    pub const fn now(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "When powman resets the RSM, the current value of BOOTDIS_NEXT is OR'd into BOOTDIS_NOW, and BOOTDIS_NEXT is cleared. The bootrom checks this flag before reading the BOOT0..3 registers. If it is set, the bootrom clears it, and ignores the BOOT registers. This prevents Secure software from diverting the boot path before a bootloader has had the chance to soft lock OTP pages containing sensitive data."]
+    #[inline(always)]
+    pub fn set_now(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[doc = "This flag always ORs writes into its current contents. It can be set but not cleared by software. The BOOTDIS_NEXT bit is OR'd into the BOOTDIS_NOW bit when the core is powered down. Simultaneously, the BOOTDIS_NEXT bit is cleared. Setting this bit means that the BOOT0..3 registers will be ignored following the next reset of the RSM by powman. This flag should be set by an early boot stage that has soft-locked OTP pages, to prevent later stages from unlocking it by power cycling."]
+    #[inline(always)]
+    pub const fn next(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[doc = "This flag always ORs writes into its current contents. It can be set but not cleared by software. The BOOTDIS_NEXT bit is OR'd into the BOOTDIS_NOW bit when the core is powered down. Simultaneously, the BOOTDIS_NEXT bit is cleared. Setting this bit means that the BOOT0..3 registers will be ignored following the next reset of the RSM by powman. This flag should be set by an early boot stage that has soft-locked OTP pages, to prevent later stages from unlocking it by power cycling."]
+    #[inline(always)]
+    pub fn set_next(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+}
+impl Default for Bootdis {
+    #[inline(always)]
+    fn default() -> Bootdis {
+        Bootdis(0)
+    }
+}
+#[doc = "Chip reset control and status"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct ChipReset(pub u32);
+impl ChipReset {
+    #[doc = "This flag is set by double-tapping RUN. It tells bootcode to go into the bootloader."]
+    #[inline(always)]
+    pub const fn double_tap(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "This flag is set by double-tapping RUN. It tells bootcode to go into the bootloader."]
+    #[inline(always)]
+    pub fn set_double_tap(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[doc = "This is set by a rescue reset from the RP-AP. Its purpose is to halt before the bootrom before booting from flash in order to recover from a boot lock-up. The debugger can then attach once the bootrom has been halted and flash some working code that does not lock up."]
+    #[inline(always)]
+    pub const fn rescue_flag(&self) -> bool {
+        let val = (self.0 >> 4usize) & 0x01;
+        val != 0
+    }
+    #[doc = "This is set by a rescue reset from the RP-AP. Its purpose is to halt before the bootrom before booting from flash in order to recover from a boot lock-up. The debugger can then attach once the bootrom has been halted and flash some working code that does not lock up."]
+    #[inline(always)]
+    pub fn set_rescue_flag(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
+    }
+    #[doc = "Last reset was from the power-on reset This resets: double_tap flag yes DP yes RPAP yes rescue_flag yes timer yes powman yes swcore yes psm yes then starts the power sequencer"]
+    #[inline(always)]
+    pub const fn had_por(&self) -> bool {
+        let val = (self.0 >> 16usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Last reset was from the power-on reset This resets: double_tap flag yes DP yes RPAP yes rescue_flag yes timer yes powman yes swcore yes psm yes then starts the power sequencer"]
+    #[inline(always)]
+    pub fn set_had_por(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
+    }
+    #[doc = "Last reset was from the brown-out detection block This resets: double_tap flag yes DP yes RPAP yes rescue_flag yes timer yes powman yes swcore yes psm yes then starts the power sequencer"]
+    #[inline(always)]
+    pub const fn had_bor(&self) -> bool {
+        let val = (self.0 >> 17usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Last reset was from the brown-out detection block This resets: double_tap flag yes DP yes RPAP yes rescue_flag yes timer yes powman yes swcore yes psm yes then starts the power sequencer"]
+    #[inline(always)]
+    pub fn set_had_bor(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
+    }
+    #[doc = "Last reset was from the RUN pin This resets: double_tap flag no DP yes RPAP yes rescue_flag yes timer yes powman yes swcore yes psm yes then starts the power sequencer"]
+    #[inline(always)]
+    pub const fn had_run_low(&self) -> bool {
+        let val = (self.0 >> 18usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Last reset was from the RUN pin This resets: double_tap flag no DP yes RPAP yes rescue_flag yes timer yes powman yes swcore yes psm yes then starts the power sequencer"]
+    #[inline(always)]
+    pub fn set_had_run_low(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize);
+    }
+    #[doc = "Last reset was an reset request from the arm debugger This resets: double_tap flag no DP no RPAP no rescue_flag yes timer yes powman yes swcore yes psm yes then starts the power sequencer"]
+    #[inline(always)]
+    pub const fn had_dp_reset_req(&self) -> bool {
+        let val = (self.0 >> 19usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Last reset was an reset request from the arm debugger This resets: double_tap flag no DP no RPAP no rescue_flag yes timer yes powman yes swcore yes psm yes then starts the power sequencer"]
+    #[inline(always)]
+    pub fn set_had_dp_reset_req(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize);
+    }
+    #[doc = "Last reset was a rescue reset from the debugger This resets: double_tap flag no DP no RPAP no rescue_flag no, it sets this flag timer yes powman yes swcore yes psm yes then starts the power sequencer"]
+    #[inline(always)]
+    pub const fn had_rescue(&self) -> bool {
+        let val = (self.0 >> 21usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Last reset was a rescue reset from the debugger This resets: double_tap flag no DP no RPAP no rescue_flag no, it sets this flag timer yes powman yes swcore yes psm yes then starts the power sequencer"]
+    #[inline(always)]
+    pub fn set_had_rescue(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 21usize)) | (((val as u32) & 0x01) << 21usize);
+    }
+    #[doc = "Last reset was a watchdog timeout which was configured to reset the power manager asynchronously This resets: double_tap flag no DP no RPAP no rescue_flag no timer yes powman yes swcore yes psm yes then starts the power sequencer"]
+    #[inline(always)]
+    pub const fn had_watchdog_reset_powman_async(&self) -> bool {
+        let val = (self.0 >> 22usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Last reset was a watchdog timeout which was configured to reset the power manager asynchronously This resets: double_tap flag no DP no RPAP no rescue_flag no timer yes powman yes swcore yes psm yes then starts the power sequencer"]
+    #[inline(always)]
+    pub fn set_had_watchdog_reset_powman_async(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 22usize)) | (((val as u32) & 0x01) << 22usize);
+    }
+    #[doc = "Last reset was a watchdog timeout which was configured to reset the power manager This resets: double_tap flag no DP no RPAP no rescue_flag no timer yes powman yes swcore yes psm yes then starts the power sequencer"]
+    #[inline(always)]
+    pub const fn had_watchdog_reset_powman(&self) -> bool {
+        let val = (self.0 >> 23usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Last reset was a watchdog timeout which was configured to reset the power manager This resets: double_tap flag no DP no RPAP no rescue_flag no timer yes powman yes swcore yes psm yes then starts the power sequencer"]
+    #[inline(always)]
+    pub fn set_had_watchdog_reset_powman(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 23usize)) | (((val as u32) & 0x01) << 23usize);
+    }
+    #[doc = "Last reset was a watchdog timeout which was configured to reset the switched-core This resets: double_tap flag no DP no RPAP no rescue_flag no timer no powman no swcore yes psm yes then starts the power sequencer"]
+    #[inline(always)]
+    pub const fn had_watchdog_reset_swcore(&self) -> bool {
+        let val = (self.0 >> 24usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Last reset was a watchdog timeout which was configured to reset the switched-core This resets: double_tap flag no DP no RPAP no rescue_flag no timer no powman no swcore yes psm yes then starts the power sequencer"]
+    #[inline(always)]
+    pub fn set_had_watchdog_reset_swcore(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 24usize)) | (((val as u32) & 0x01) << 24usize);
+    }
+    #[doc = "Last reset was a switched core powerdown This resets: double_tap flag no DP no RPAP no rescue_flag no timer no powman no swcore yes psm yes then starts the power sequencer"]
+    #[inline(always)]
+    pub const fn had_swcore_pd(&self) -> bool {
+        let val = (self.0 >> 25usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Last reset was a switched core powerdown This resets: double_tap flag no DP no RPAP no rescue_flag no timer no powman no swcore yes psm yes then starts the power sequencer"]
+    #[inline(always)]
+    pub fn set_had_swcore_pd(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 25usize)) | (((val as u32) & 0x01) << 25usize);
+    }
+    #[doc = "Last reset was due to a power supply glitch This resets: double_tap flag no DP no RPAP no rescue_flag no timer no powman no swcore no psm yes and does not change the power state"]
+    #[inline(always)]
+    pub const fn had_glitch_detect(&self) -> bool {
+        let val = (self.0 >> 26usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Last reset was due to a power supply glitch This resets: double_tap flag no DP no RPAP no rescue_flag no timer no powman no swcore no psm yes and does not change the power state"]
+    #[inline(always)]
+    pub fn set_had_glitch_detect(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 26usize)) | (((val as u32) & 0x01) << 26usize);
+    }
+    #[doc = "Last reset was a system reset from the hazard debugger This resets: double_tap flag no DP no RPAP no rescue_flag no timer no powman no swcore no psm yes and does not change the power state"]
+    #[inline(always)]
+    pub const fn had_hzd_sys_reset_req(&self) -> bool {
+        let val = (self.0 >> 27usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Last reset was a system reset from the hazard debugger This resets: double_tap flag no DP no RPAP no rescue_flag no timer no powman no swcore no psm yes and does not change the power state"]
+    #[inline(always)]
+    pub fn set_had_hzd_sys_reset_req(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 27usize)) | (((val as u32) & 0x01) << 27usize);
+    }
+    #[doc = "Last reset was a watchdog timeout which was configured to reset the power-on state machine This resets: double_tap flag no DP no RPAP no rescue_flag no timer no powman no swcore no psm yes and does not change the power state"]
+    #[inline(always)]
+    pub const fn had_watchdog_reset_rsm(&self) -> bool {
+        let val = (self.0 >> 28usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Last reset was a watchdog timeout which was configured to reset the power-on state machine This resets: double_tap flag no DP no RPAP no rescue_flag no timer no powman no swcore no psm yes and does not change the power state"]
+    #[inline(always)]
+    pub fn set_had_watchdog_reset_rsm(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 28usize)) | (((val as u32) & 0x01) << 28usize);
+    }
+}
+impl Default for ChipReset {
+    #[inline(always)]
+    fn default() -> ChipReset {
+        ChipReset(0)
+    }
+}
+#[doc = "Indicates current powerup request state pwrup events can be cleared by removing the enable from the pwrup register. The alarm pwrup req can be cleared by clearing timer.alarm_enab 0 = chip reset, for the source of the last reset see POWMAN_CHIP_RESET 1 = pwrup0 2 = pwrup1 3 = pwrup2 4 = pwrup3 5 = coresight_pwrup 6 = alarm_pwrup"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct CurrentPwrupReq(pub u32);
+impl CurrentPwrupReq {
+    #[inline(always)]
+    pub const fn current_pwrup_req(&self) -> u8 {
+        let val = (self.0 >> 0usize) & 0x7f;
+        val as u8
+    }
+    #[inline(always)]
+    pub fn set_current_pwrup_req(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x7f << 0usize)) | (((val as u32) & 0x7f) << 0usize);
+    }
+}
+impl Default for CurrentPwrupReq {
+    #[inline(always)]
+    fn default() -> CurrentPwrupReq {
+        CurrentPwrupReq(0)
+    }
+}
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct DbgPwrcfg(pub u32);
+impl DbgPwrcfg {
+    #[doc = "Ignore pwrup req from debugger. If pwrup req is asserted then this will prevent power down and set powerdown blocked. Set ignore to stop paying attention to pwrup_req"]
+    #[inline(always)]
+    pub const fn ignore(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Ignore pwrup req from debugger. If pwrup req is asserted then this will prevent power down and set powerdown blocked. Set ignore to stop paying attention to pwrup_req"]
+    #[inline(always)]
+    pub fn set_ignore(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+}
+impl Default for DbgPwrcfg {
+    #[inline(always)]
+    fn default() -> DbgPwrcfg {
+        DbgPwrcfg(0)
+    }
+}
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Dbgconfig(pub u32);
+impl Dbgconfig {
+    #[doc = "Configure DP instance ID for SWD multidrop selection. Recommend that this is NOT changed until you require debug access in multi-chip environment"]
+    #[inline(always)]
+    pub const fn dp_instid(&self) -> u8 {
+        let val = (self.0 >> 0usize) & 0x0f;
+        val as u8
+    }
+    #[doc = "Configure DP instance ID for SWD multidrop selection. Recommend that this is NOT changed until you require debug access in multi-chip environment"]
+    #[inline(always)]
+    pub fn set_dp_instid(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize);
+    }
+}
+impl Default for Dbgconfig {
+    #[inline(always)]
+    fn default() -> Dbgconfig {
+        Dbgconfig(0)
+    }
+}
+#[doc = "Configures a gpio as a power mode aware control output"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct ExtCtrl0(pub u32);
+impl ExtCtrl0 {
+    #[doc = "selects from gpio 0->30 set to 31 to disable this feature"]
+    #[inline(always)]
+    pub const fn gpio_select(&self) -> u8 {
+        let val = (self.0 >> 0usize) & 0x3f;
+        val as u8
+    }
+    #[doc = "selects from gpio 0->30 set to 31 to disable this feature"]
+    #[inline(always)]
+    pub fn set_gpio_select(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x3f << 0usize)) | (((val as u32) & 0x3f) << 0usize);
+    }
+    #[inline(always)]
+    pub const fn init(&self) -> bool {
+        let val = (self.0 >> 8usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_init(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
+    }
+    #[inline(always)]
+    pub const fn init_state(&self) -> bool {
+        let val = (self.0 >> 12usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_init_state(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
+    }
+    #[doc = "output level when entering the low power state"]
+    #[inline(always)]
+    pub const fn lp_entry_state(&self) -> bool {
+        let val = (self.0 >> 13usize) & 0x01;
+        val != 0
+    }
+    #[doc = "output level when entering the low power state"]
+    #[inline(always)]
+    pub fn set_lp_entry_state(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize);
+    }
+    #[doc = "output level when exiting the low power state"]
+    #[inline(always)]
+    pub const fn lp_exit_state(&self) -> bool {
+        let val = (self.0 >> 14usize) & 0x01;
+        val != 0
+    }
+    #[doc = "output level when exiting the low power state"]
+    #[inline(always)]
+    pub fn set_lp_exit_state(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize);
+    }
+}
+impl Default for ExtCtrl0 {
+    #[inline(always)]
+    fn default() -> ExtCtrl0 {
+        ExtCtrl0(0)
+    }
+}
+#[doc = "Configures a gpio as a power mode aware control output"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct ExtCtrl1(pub u32);
+impl ExtCtrl1 {
+    #[doc = "selects from gpio 0->30 set to 31 to disable this feature"]
+    #[inline(always)]
+    pub const fn gpio_select(&self) -> u8 {
+        let val = (self.0 >> 0usize) & 0x3f;
+        val as u8
+    }
+    #[doc = "selects from gpio 0->30 set to 31 to disable this feature"]
+    #[inline(always)]
+    pub fn set_gpio_select(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x3f << 0usize)) | (((val as u32) & 0x3f) << 0usize);
+    }
+    #[inline(always)]
+    pub const fn init(&self) -> bool {
+        let val = (self.0 >> 8usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_init(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
+    }
+    #[inline(always)]
+    pub const fn init_state(&self) -> bool {
+        let val = (self.0 >> 12usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_init_state(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
+    }
+    #[doc = "output level when entering the low power state"]
+    #[inline(always)]
+    pub const fn lp_entry_state(&self) -> bool {
+        let val = (self.0 >> 13usize) & 0x01;
+        val != 0
+    }
+    #[doc = "output level when entering the low power state"]
+    #[inline(always)]
+    pub fn set_lp_entry_state(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize);
+    }
+    #[doc = "output level when exiting the low power state"]
+    #[inline(always)]
+    pub const fn lp_exit_state(&self) -> bool {
+        let val = (self.0 >> 14usize) & 0x01;
+        val != 0
+    }
+    #[doc = "output level when exiting the low power state"]
+    #[inline(always)]
+    pub fn set_lp_exit_state(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize);
+    }
+}
+impl Default for ExtCtrl1 {
+    #[inline(always)]
+    fn default() -> ExtCtrl1 {
+        ExtCtrl1(0)
+    }
+}
+#[doc = "Select a GPIO to use as a time reference, the source can be used to drive the low power clock at 32kHz, or to provide a 1ms tick to the timer, or provide a 1Hz tick to the timer. The tick selection is controlled by the POWMAN_TIMER register."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct ExtTimeRef(pub u32);
+impl ExtTimeRef {
+    #[doc = "0 -> gpio12 1 -> gpio20 2 -> gpio14 3 -> gpio22"]
+    #[inline(always)]
+    pub const fn source_sel(&self) -> u8 {
+        let val = (self.0 >> 0usize) & 0x03;
+        val as u8
+    }
+    #[doc = "0 -> gpio12 1 -> gpio20 2 -> gpio14 3 -> gpio22"]
+    #[inline(always)]
+    pub fn set_source_sel(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x03 << 0usize)) | (((val as u32) & 0x03) << 0usize);
+    }
+    #[doc = "Use the selected GPIO to drive the 32kHz low power clock, in place of LPOSC. This field must only be written when POWMAN_TIMER_RUN=0"]
+    #[inline(always)]
+    pub const fn drive_lpck(&self) -> bool {
+        let val = (self.0 >> 4usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Use the selected GPIO to drive the 32kHz low power clock, in place of LPOSC. This field must only be written when POWMAN_TIMER_RUN=0"]
+    #[inline(always)]
+    pub fn set_drive_lpck(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
+    }
+}
+impl Default for ExtTimeRef {
+    #[inline(always)]
+    fn default() -> ExtTimeRef {
+        ExtTimeRef(0)
+    }
+}
+#[doc = "Interrupt Enable"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Inte(pub u32);
+impl Inte {
+    #[inline(always)]
+    pub const fn vreg_output_low(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_vreg_output_low(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[inline(always)]
+    pub const fn timer(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_timer(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+    #[doc = "Source is state.req_ignored"]
+    #[inline(always)]
+    pub const fn state_req_ignored(&self) -> bool {
+        let val = (self.0 >> 2usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Source is state.req_ignored"]
+    #[inline(always)]
+    pub fn set_state_req_ignored(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+    }
+    #[doc = "Source is state.pwrup_while_waiting"]
+    #[inline(always)]
+    pub const fn pwrup_while_waiting(&self) -> bool {
+        let val = (self.0 >> 3usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Source is state.pwrup_while_waiting"]
+    #[inline(always)]
+    pub fn set_pwrup_while_waiting(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
+    }
+}
+impl Default for Inte {
+    #[inline(always)]
+    fn default() -> Inte {
+        Inte(0)
+    }
+}
+#[doc = "Interrupt Force"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Intf(pub u32);
+impl Intf {
+    #[inline(always)]
+    pub const fn vreg_output_low(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_vreg_output_low(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[inline(always)]
+    pub const fn timer(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_timer(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+    #[doc = "Source is state.req_ignored"]
+    #[inline(always)]
+    pub const fn state_req_ignored(&self) -> bool {
+        let val = (self.0 >> 2usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Source is state.req_ignored"]
+    #[inline(always)]
+    pub fn set_state_req_ignored(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+    }
+    #[doc = "Source is state.pwrup_while_waiting"]
+    #[inline(always)]
+    pub const fn pwrup_while_waiting(&self) -> bool {
+        let val = (self.0 >> 3usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Source is state.pwrup_while_waiting"]
+    #[inline(always)]
+    pub fn set_pwrup_while_waiting(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
+    }
+}
+impl Default for Intf {
+    #[inline(always)]
+    fn default() -> Intf {
+        Intf(0)
+    }
+}
+#[doc = "Raw Interrupts"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Intr(pub u32);
+impl Intr {
+    #[inline(always)]
+    pub const fn vreg_output_low(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_vreg_output_low(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[inline(always)]
+    pub const fn timer(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_timer(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+    #[doc = "Source is state.req_ignored"]
+    #[inline(always)]
+    pub const fn state_req_ignored(&self) -> bool {
+        let val = (self.0 >> 2usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Source is state.req_ignored"]
+    #[inline(always)]
+    pub fn set_state_req_ignored(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+    }
+    #[doc = "Source is state.pwrup_while_waiting"]
+    #[inline(always)]
+    pub const fn pwrup_while_waiting(&self) -> bool {
+        let val = (self.0 >> 3usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Source is state.pwrup_while_waiting"]
+    #[inline(always)]
+    pub fn set_pwrup_while_waiting(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
+    }
+}
+impl Default for Intr {
+    #[inline(always)]
+    fn default() -> Intr {
+        Intr(0)
+    }
+}
+#[doc = "Interrupt status after masking & forcing"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Ints(pub u32);
+impl Ints {
+    #[inline(always)]
+    pub const fn vreg_output_low(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_vreg_output_low(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[inline(always)]
+    pub const fn timer(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_timer(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+    #[doc = "Source is state.req_ignored"]
+    #[inline(always)]
+    pub const fn state_req_ignored(&self) -> bool {
+        let val = (self.0 >> 2usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Source is state.req_ignored"]
+    #[inline(always)]
+    pub fn set_state_req_ignored(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+    }
+    #[doc = "Source is state.pwrup_while_waiting"]
+    #[inline(always)]
+    pub const fn pwrup_while_waiting(&self) -> bool {
+        let val = (self.0 >> 3usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Source is state.pwrup_while_waiting"]
+    #[inline(always)]
+    pub fn set_pwrup_while_waiting(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
+    }
+}
+impl Default for Ints {
+    #[inline(always)]
+    fn default() -> Ints {
+        Ints(0)
+    }
+}
+#[doc = "Indicates which pwrup source triggered the last switched-core power up 0 = chip reset, for the source of the last reset see POWMAN_CHIP_RESET 1 = pwrup0 2 = pwrup1 3 = pwrup2 4 = pwrup3 5 = coresight_pwrup 6 = alarm_pwrup"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct LastSwcorePwrup(pub u32);
+impl LastSwcorePwrup {
+    #[inline(always)]
+    pub const fn last_swcore_pwrup(&self) -> u8 {
+        let val = (self.0 >> 0usize) & 0x7f;
+        val as u8
+    }
+    #[inline(always)]
+    pub fn set_last_swcore_pwrup(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x7f << 0usize)) | (((val as u32) & 0x7f) << 0usize);
+    }
+}
+impl Default for LastSwcorePwrup {
+    #[inline(always)]
+    fn default() -> LastSwcorePwrup {
+        LastSwcorePwrup(0)
+    }
+}
+#[doc = "Low power oscillator control register."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Lposc(pub u32);
+impl Lposc {
+    #[doc = "This feature has been removed"]
+    #[inline(always)]
+    pub const fn mode(&self) -> u8 {
+        let val = (self.0 >> 0usize) & 0x03;
+        val as u8
+    }
+    #[doc = "This feature has been removed"]
+    #[inline(always)]
+    pub fn set_mode(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x03 << 0usize)) | (((val as u32) & 0x03) << 0usize);
+    }
+    #[doc = "Frequency trim - the trim step is typically 1% of the reset frequency, but can be up to 3%"]
+    #[inline(always)]
+    pub const fn trim(&self) -> u8 {
+        let val = (self.0 >> 4usize) & 0x3f;
+        val as u8
+    }
+    #[doc = "Frequency trim - the trim step is typically 1% of the reset frequency, but can be up to 3%"]
+    #[inline(always)]
+    pub fn set_trim(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x3f << 4usize)) | (((val as u32) & 0x3f) << 4usize);
+    }
+}
+impl Default for Lposc {
+    #[inline(always)]
+    fn default() -> Lposc {
+        Lposc(0)
+    }
+}
+#[doc = "Informs the AON Timer of the fractional component of the clock frequency when running off the LPOSC."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct LposcFreqKhzFrac(pub u32);
+impl LposcFreqKhzFrac {
+    #[doc = "Fractional component of the LPOSC or GPIO clock source frequency in kHz. Default = 0.768 This field must only be written when POWMAN_TIMER_RUN=0 or POWMAN_TIMER_USING_XOSC=1"]
+    #[inline(always)]
+    pub const fn lposc_freq_khz_frac(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0xffff;
+        val as u16
+    }
+    #[doc = "Fractional component of the LPOSC or GPIO clock source frequency in kHz. Default = 0.768 This field must only be written when POWMAN_TIMER_RUN=0 or POWMAN_TIMER_USING_XOSC=1"]
+    #[inline(always)]
+    pub fn set_lposc_freq_khz_frac(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+    }
+}
+impl Default for LposcFreqKhzFrac {
+    #[inline(always)]
+    fn default() -> LposcFreqKhzFrac {
+        LposcFreqKhzFrac(0)
+    }
+}
+#[doc = "Informs the AON Timer of the integer component of the clock frequency when running off the LPOSC."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct LposcFreqKhzInt(pub u32);
+impl LposcFreqKhzInt {
+    #[doc = "Integer component of the LPOSC or GPIO clock source frequency in kHz. Default = 32 This field must only be written when POWMAN_TIMER_RUN=0 or POWMAN_TIMER_USING_XOSC=1"]
+    #[inline(always)]
+    pub const fn lposc_freq_khz_int(&self) -> u8 {
+        let val = (self.0 >> 0usize) & 0x3f;
+        val as u8
+    }
+    #[doc = "Integer component of the LPOSC or GPIO clock source frequency in kHz. Default = 32 This field must only be written when POWMAN_TIMER_RUN=0 or POWMAN_TIMER_USING_XOSC=1"]
+    #[inline(always)]
+    pub fn set_lposc_freq_khz_int(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x3f << 0usize)) | (((val as u32) & 0x3f) << 0usize);
+    }
+}
+impl Default for LposcFreqKhzInt {
+    #[inline(always)]
+    fn default() -> LposcFreqKhzInt {
+        LposcFreqKhzInt(0)
+    }
+}
+#[doc = "power state machine delays"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct PowDelay(pub u32);
+impl PowDelay {
+    #[doc = "timing between the swcore power state machine steps measured in units of the lposc period, 0 gives a delay of 1 unit"]
+    #[inline(always)]
+    pub const fn swcore_step(&self) -> u8 {
+        let val = (self.0 >> 0usize) & 0x0f;
+        val as u8
+    }
+    #[doc = "timing between the swcore power state machine steps measured in units of the lposc period, 0 gives a delay of 1 unit"]
+    #[inline(always)]
+    pub fn set_swcore_step(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize);
+    }
+    #[doc = "timing between the xip power state machine steps measured in units of the lposc period, 0 gives a delay of 1 unit"]
+    #[inline(always)]
+    pub const fn xip_step(&self) -> u8 {
+        let val = (self.0 >> 4usize) & 0x0f;
+        val as u8
+    }
+    #[doc = "timing between the xip power state machine steps measured in units of the lposc period, 0 gives a delay of 1 unit"]
+    #[inline(always)]
+    pub fn set_xip_step(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x0f << 4usize)) | (((val as u32) & 0x0f) << 4usize);
+    }
+    #[doc = "timing between the sram0 and sram1 power state machine steps measured in units of the powman tick period (>=1us), 0 gives a delay of 1 unit"]
+    #[inline(always)]
+    pub const fn sram_step(&self) -> u8 {
+        let val = (self.0 >> 8usize) & 0xff;
+        val as u8
+    }
+    #[doc = "timing between the sram0 and sram1 power state machine steps measured in units of the powman tick period (>=1us), 0 gives a delay of 1 unit"]
+    #[inline(always)]
+    pub fn set_sram_step(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize);
+    }
+}
+impl Default for PowDelay {
+    #[inline(always)]
+    fn default() -> PowDelay {
+        PowDelay(0)
+    }
+}
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct PowFastdiv(pub u32);
+impl PowFastdiv {
+    #[doc = "divides the POWMAN clock to provide a tick for the delay module and state machines when clk_pow is running from the slow clock it is not divided when clk_pow is running from the fast clock it is divided by tick_div"]
+    #[inline(always)]
+    pub const fn pow_fastdiv(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0x07ff;
+        val as u16
+    }
+    #[doc = "divides the POWMAN clock to provide a tick for the delay module and state machines when clk_pow is running from the slow clock it is not divided when clk_pow is running from the fast clock it is divided by tick_div"]
+    #[inline(always)]
+    pub fn set_pow_fastdiv(&mut self, val: u16) {
+        self.0 = (self.0 & !(0x07ff << 0usize)) | (((val as u32) & 0x07ff) << 0usize);
+    }
+}
+impl Default for PowFastdiv {
+    #[inline(always)]
+    fn default() -> PowFastdiv {
+        PowFastdiv(0)
+    }
+}
+#[doc = "4 GPIO powerup events can be configured to wake the chip up from a low power state. The pwrups are level/edge sensitive and can be set to trigger on a high/rising or low/falling event The number of gpios available depends on the package option. An invalid selection will be ignored source = 0 selects gpio0 . . source = 47 selects gpio47 source = 48 selects qspi_ss source = 49 selects qspi_sd0 source = 50 selects qspi_sd1 source = 51 selects qspi_sd2 source = 52 selects qspi_sd3 source = 53 selects qspi_sclk level = 0 triggers the pwrup when the source is low level = 1 triggers the pwrup when the source is high"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Pwrup0(pub u32);
+impl Pwrup0 {
+    #[inline(always)]
+    pub const fn source(&self) -> u8 {
+        let val = (self.0 >> 0usize) & 0x3f;
+        val as u8
+    }
+    #[inline(always)]
+    pub fn set_source(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x3f << 0usize)) | (((val as u32) & 0x3f) << 0usize);
+    }
+    #[doc = "Set to 1 to enable the wakeup source. Set to 0 to disable the wakeup source and clear a pending wakeup event. If using edge detect a latched edge needs to be cleared by writing 1 to the status register also."]
+    #[inline(always)]
+    pub const fn enable(&self) -> bool {
+        let val = (self.0 >> 6usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Set to 1 to enable the wakeup source. Set to 0 to disable the wakeup source and clear a pending wakeup event. If using edge detect a latched edge needs to be cleared by writing 1 to the status register also."]
+    #[inline(always)]
+    pub fn set_enable(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
+    }
+    #[inline(always)]
+    pub const fn direction(&self) -> super::vals::Pwrup0direction {
+        let val = (self.0 >> 7usize) & 0x01;
+        super::vals::Pwrup0direction::from_bits(val as u8)
+    }
+    #[inline(always)]
+    pub fn set_direction(&mut self, val: super::vals::Pwrup0direction) {
+        self.0 = (self.0 & !(0x01 << 7usize)) | (((val.to_bits() as u32) & 0x01) << 7usize);
+    }
+    #[doc = "Edge or level detect. Edge will detect a 0 to 1 transition (or 1 to 0 transition). Level will detect a 1 or 0. Both types of event get latched into the current_pwrup_req register."]
+    #[inline(always)]
+    pub const fn mode(&self) -> super::vals::Pwrup0mode {
+        let val = (self.0 >> 8usize) & 0x01;
+        super::vals::Pwrup0mode::from_bits(val as u8)
+    }
+    #[doc = "Edge or level detect. Edge will detect a 0 to 1 transition (or 1 to 0 transition). Level will detect a 1 or 0. Both types of event get latched into the current_pwrup_req register."]
+    #[inline(always)]
+    pub fn set_mode(&mut self, val: super::vals::Pwrup0mode) {
+        self.0 = (self.0 & !(0x01 << 8usize)) | (((val.to_bits() as u32) & 0x01) << 8usize);
+    }
+    #[doc = "Status of gpio wakeup. Write to 1 to clear a latched edge detect."]
+    #[inline(always)]
+    pub const fn status(&self) -> bool {
+        let val = (self.0 >> 9usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Status of gpio wakeup. Write to 1 to clear a latched edge detect."]
+    #[inline(always)]
+    pub fn set_status(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
+    }
+    #[doc = "Value of selected gpio pin (only if enable == 1)"]
+    #[inline(always)]
+    pub const fn raw_status(&self) -> bool {
+        let val = (self.0 >> 10usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Value of selected gpio pin (only if enable == 1)"]
+    #[inline(always)]
+    pub fn set_raw_status(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize);
+    }
+}
+impl Default for Pwrup0 {
+    #[inline(always)]
+    fn default() -> Pwrup0 {
+        Pwrup0(0)
+    }
+}
+#[doc = "4 GPIO powerup events can be configured to wake the chip up from a low power state. The pwrups are level/edge sensitive and can be set to trigger on a high/rising or low/falling event The number of gpios available depends on the package option. An invalid selection will be ignored source = 0 selects gpio0 . . source = 47 selects gpio47 source = 48 selects qspi_ss source = 49 selects qspi_sd0 source = 50 selects qspi_sd1 source = 51 selects qspi_sd2 source = 52 selects qspi_sd3 source = 53 selects qspi_sclk level = 0 triggers the pwrup when the source is low level = 1 triggers the pwrup when the source is high"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Pwrup1(pub u32);
+impl Pwrup1 {
+    #[inline(always)]
+    pub const fn source(&self) -> u8 {
+        let val = (self.0 >> 0usize) & 0x3f;
+        val as u8
+    }
+    #[inline(always)]
+    pub fn set_source(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x3f << 0usize)) | (((val as u32) & 0x3f) << 0usize);
+    }
+    #[doc = "Set to 1 to enable the wakeup source. Set to 0 to disable the wakeup source and clear a pending wakeup event. If using edge detect a latched edge needs to be cleared by writing 1 to the status register also."]
+    #[inline(always)]
+    pub const fn enable(&self) -> bool {
+        let val = (self.0 >> 6usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Set to 1 to enable the wakeup source. Set to 0 to disable the wakeup source and clear a pending wakeup event. If using edge detect a latched edge needs to be cleared by writing 1 to the status register also."]
+    #[inline(always)]
+    pub fn set_enable(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
+    }
+    #[inline(always)]
+    pub const fn direction(&self) -> super::vals::Pwrup1direction {
+        let val = (self.0 >> 7usize) & 0x01;
+        super::vals::Pwrup1direction::from_bits(val as u8)
+    }
+    #[inline(always)]
+    pub fn set_direction(&mut self, val: super::vals::Pwrup1direction) {
+        self.0 = (self.0 & !(0x01 << 7usize)) | (((val.to_bits() as u32) & 0x01) << 7usize);
+    }
+    #[doc = "Edge or level detect. Edge will detect a 0 to 1 transition (or 1 to 0 transition). Level will detect a 1 or 0. Both types of event get latched into the current_pwrup_req register."]
+    #[inline(always)]
+    pub const fn mode(&self) -> super::vals::Pwrup1mode {
+        let val = (self.0 >> 8usize) & 0x01;
+        super::vals::Pwrup1mode::from_bits(val as u8)
+    }
+    #[doc = "Edge or level detect. Edge will detect a 0 to 1 transition (or 1 to 0 transition). Level will detect a 1 or 0. Both types of event get latched into the current_pwrup_req register."]
+    #[inline(always)]
+    pub fn set_mode(&mut self, val: super::vals::Pwrup1mode) {
+        self.0 = (self.0 & !(0x01 << 8usize)) | (((val.to_bits() as u32) & 0x01) << 8usize);
+    }
+    #[doc = "Status of gpio wakeup. Write to 1 to clear a latched edge detect."]
+    #[inline(always)]
+    pub const fn status(&self) -> bool {
+        let val = (self.0 >> 9usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Status of gpio wakeup. Write to 1 to clear a latched edge detect."]
+    #[inline(always)]
+    pub fn set_status(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
+    }
+    #[doc = "Value of selected gpio pin (only if enable == 1)"]
+    #[inline(always)]
+    pub const fn raw_status(&self) -> bool {
+        let val = (self.0 >> 10usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Value of selected gpio pin (only if enable == 1)"]
+    #[inline(always)]
+    pub fn set_raw_status(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize);
+    }
+}
+impl Default for Pwrup1 {
+    #[inline(always)]
+    fn default() -> Pwrup1 {
+        Pwrup1(0)
+    }
+}
+#[doc = "4 GPIO powerup events can be configured to wake the chip up from a low power state. The pwrups are level/edge sensitive and can be set to trigger on a high/rising or low/falling event The number of gpios available depends on the package option. An invalid selection will be ignored source = 0 selects gpio0 . . source = 47 selects gpio47 source = 48 selects qspi_ss source = 49 selects qspi_sd0 source = 50 selects qspi_sd1 source = 51 selects qspi_sd2 source = 52 selects qspi_sd3 source = 53 selects qspi_sclk level = 0 triggers the pwrup when the source is low level = 1 triggers the pwrup when the source is high"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Pwrup2(pub u32);
+impl Pwrup2 {
+    #[inline(always)]
+    pub const fn source(&self) -> u8 {
+        let val = (self.0 >> 0usize) & 0x3f;
+        val as u8
+    }
+    #[inline(always)]
+    pub fn set_source(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x3f << 0usize)) | (((val as u32) & 0x3f) << 0usize);
+    }
+    #[doc = "Set to 1 to enable the wakeup source. Set to 0 to disable the wakeup source and clear a pending wakeup event. If using edge detect a latched edge needs to be cleared by writing 1 to the status register also."]
+    #[inline(always)]
+    pub const fn enable(&self) -> bool {
+        let val = (self.0 >> 6usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Set to 1 to enable the wakeup source. Set to 0 to disable the wakeup source and clear a pending wakeup event. If using edge detect a latched edge needs to be cleared by writing 1 to the status register also."]
+    #[inline(always)]
+    pub fn set_enable(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
+    }
+    #[inline(always)]
+    pub const fn direction(&self) -> super::vals::Pwrup2direction {
+        let val = (self.0 >> 7usize) & 0x01;
+        super::vals::Pwrup2direction::from_bits(val as u8)
+    }
+    #[inline(always)]
+    pub fn set_direction(&mut self, val: super::vals::Pwrup2direction) {
+        self.0 = (self.0 & !(0x01 << 7usize)) | (((val.to_bits() as u32) & 0x01) << 7usize);
+    }
+    #[doc = "Edge or level detect. Edge will detect a 0 to 1 transition (or 1 to 0 transition). Level will detect a 1 or 0. Both types of event get latched into the current_pwrup_req register."]
+    #[inline(always)]
+    pub const fn mode(&self) -> super::vals::Pwrup2mode {
+        let val = (self.0 >> 8usize) & 0x01;
+        super::vals::Pwrup2mode::from_bits(val as u8)
+    }
+    #[doc = "Edge or level detect. Edge will detect a 0 to 1 transition (or 1 to 0 transition). Level will detect a 1 or 0. Both types of event get latched into the current_pwrup_req register."]
+    #[inline(always)]
+    pub fn set_mode(&mut self, val: super::vals::Pwrup2mode) {
+        self.0 = (self.0 & !(0x01 << 8usize)) | (((val.to_bits() as u32) & 0x01) << 8usize);
+    }
+    #[doc = "Status of gpio wakeup. Write to 1 to clear a latched edge detect."]
+    #[inline(always)]
+    pub const fn status(&self) -> bool {
+        let val = (self.0 >> 9usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Status of gpio wakeup. Write to 1 to clear a latched edge detect."]
+    #[inline(always)]
+    pub fn set_status(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
+    }
+    #[doc = "Value of selected gpio pin (only if enable == 1)"]
+    #[inline(always)]
+    pub const fn raw_status(&self) -> bool {
+        let val = (self.0 >> 10usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Value of selected gpio pin (only if enable == 1)"]
+    #[inline(always)]
+    pub fn set_raw_status(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize);
+    }
+}
+impl Default for Pwrup2 {
+    #[inline(always)]
+    fn default() -> Pwrup2 {
+        Pwrup2(0)
+    }
+}
+#[doc = "4 GPIO powerup events can be configured to wake the chip up from a low power state. The pwrups are level/edge sensitive and can be set to trigger on a high/rising or low/falling event The number of gpios available depends on the package option. An invalid selection will be ignored source = 0 selects gpio0 . . source = 47 selects gpio47 source = 48 selects qspi_ss source = 49 selects qspi_sd0 source = 50 selects qspi_sd1 source = 51 selects qspi_sd2 source = 52 selects qspi_sd3 source = 53 selects qspi_sclk level = 0 triggers the pwrup when the source is low level = 1 triggers the pwrup when the source is high"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Pwrup3(pub u32);
+impl Pwrup3 {
+    #[inline(always)]
+    pub const fn source(&self) -> u8 {
+        let val = (self.0 >> 0usize) & 0x3f;
+        val as u8
+    }
+    #[inline(always)]
+    pub fn set_source(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x3f << 0usize)) | (((val as u32) & 0x3f) << 0usize);
+    }
+    #[doc = "Set to 1 to enable the wakeup source. Set to 0 to disable the wakeup source and clear a pending wakeup event. If using edge detect a latched edge needs to be cleared by writing 1 to the status register also."]
+    #[inline(always)]
+    pub const fn enable(&self) -> bool {
+        let val = (self.0 >> 6usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Set to 1 to enable the wakeup source. Set to 0 to disable the wakeup source and clear a pending wakeup event. If using edge detect a latched edge needs to be cleared by writing 1 to the status register also."]
+    #[inline(always)]
+    pub fn set_enable(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
+    }
+    #[inline(always)]
+    pub const fn direction(&self) -> super::vals::Pwrup3direction {
+        let val = (self.0 >> 7usize) & 0x01;
+        super::vals::Pwrup3direction::from_bits(val as u8)
+    }
+    #[inline(always)]
+    pub fn set_direction(&mut self, val: super::vals::Pwrup3direction) {
+        self.0 = (self.0 & !(0x01 << 7usize)) | (((val.to_bits() as u32) & 0x01) << 7usize);
+    }
+    #[doc = "Edge or level detect. Edge will detect a 0 to 1 transition (or 1 to 0 transition). Level will detect a 1 or 0. Both types of event get latched into the current_pwrup_req register."]
+    #[inline(always)]
+    pub const fn mode(&self) -> super::vals::Pwrup3mode {
+        let val = (self.0 >> 8usize) & 0x01;
+        super::vals::Pwrup3mode::from_bits(val as u8)
+    }
+    #[doc = "Edge or level detect. Edge will detect a 0 to 1 transition (or 1 to 0 transition). Level will detect a 1 or 0. Both types of event get latched into the current_pwrup_req register."]
+    #[inline(always)]
+    pub fn set_mode(&mut self, val: super::vals::Pwrup3mode) {
+        self.0 = (self.0 & !(0x01 << 8usize)) | (((val.to_bits() as u32) & 0x01) << 8usize);
+    }
+    #[doc = "Status of gpio wakeup. Write to 1 to clear a latched edge detect."]
+    #[inline(always)]
+    pub const fn status(&self) -> bool {
+        let val = (self.0 >> 9usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Status of gpio wakeup. Write to 1 to clear a latched edge detect."]
+    #[inline(always)]
+    pub fn set_status(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
+    }
+    #[doc = "Value of selected gpio pin (only if enable == 1)"]
+    #[inline(always)]
+    pub const fn raw_status(&self) -> bool {
+        let val = (self.0 >> 10usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Value of selected gpio pin (only if enable == 1)"]
+    #[inline(always)]
+    pub fn set_raw_status(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize);
+    }
+}
+impl Default for Pwrup3 {
+    #[inline(always)]
+    fn default() -> Pwrup3 {
+        Pwrup3(0)
+    }
+}
+#[doc = "For configuration of the power sequencer Writes are ignored while POWMAN_STATE_CHANGING=1"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct SeqCfg(pub u32);
+impl SeqCfg {
+    #[doc = "Specifies the power state of SRAM1 when powering up swcore from a low power state (P1.xxx) to a high power state (P0.0xx). 0=power-up 1=no change"]
+    #[inline(always)]
+    pub const fn hw_pwrup_sram1(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Specifies the power state of SRAM1 when powering up swcore from a low power state (P1.xxx) to a high power state (P0.0xx). 0=power-up 1=no change"]
+    #[inline(always)]
+    pub fn set_hw_pwrup_sram1(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[doc = "Specifies the power state of SRAM0 when powering up swcore from a low power state (P1.xxx) to a high power state (P0.0xx). 0=power-up 1=no change"]
+    #[inline(always)]
+    pub const fn hw_pwrup_sram0(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Specifies the power state of SRAM0 when powering up swcore from a low power state (P1.xxx) to a high power state (P0.0xx). 0=power-up 1=no change"]
+    #[inline(always)]
+    pub fn set_hw_pwrup_sram0(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+    #[doc = "Set to 0 to prevent automatic switching to vreg low power mode when switched-core is powered down This setting takes effect when the swcore is next powered down"]
+    #[inline(always)]
+    pub const fn use_vreg_lp(&self) -> bool {
+        let val = (self.0 >> 4usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Set to 0 to prevent automatic switching to vreg low power mode when switched-core is powered down This setting takes effect when the swcore is next powered down"]
+    #[inline(always)]
+    pub fn set_use_vreg_lp(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
+    }
+    #[doc = "Set to 0 to prevent automatic switching to vreg high power mode when switched-core is powered up This setting takes effect when the swcore is next powered up"]
+    #[inline(always)]
+    pub const fn use_vreg_hp(&self) -> bool {
+        let val = (self.0 >> 5usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Set to 0 to prevent automatic switching to vreg high power mode when switched-core is powered up This setting takes effect when the swcore is next powered up"]
+    #[inline(always)]
+    pub fn set_use_vreg_hp(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
+    }
+    #[doc = "Set to 0 to prevent automatic switching to bod low power mode when switched-core is powered down This setting takes effect when the swcore is next powered down"]
+    #[inline(always)]
+    pub const fn use_bod_lp(&self) -> bool {
+        let val = (self.0 >> 6usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Set to 0 to prevent automatic switching to bod low power mode when switched-core is powered down This setting takes effect when the swcore is next powered down"]
+    #[inline(always)]
+    pub fn set_use_bod_lp(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
+    }
+    #[doc = "Set to 0 to prevent automatic switching to bod high power mode when switched-core is powered up This setting takes effect when the swcore is next powered up"]
+    #[inline(always)]
+    pub const fn use_bod_hp(&self) -> bool {
+        let val = (self.0 >> 7usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Set to 0 to prevent automatic switching to bod high power mode when switched-core is powered up This setting takes effect when the swcore is next powered up"]
+    #[inline(always)]
+    pub fn set_use_bod_hp(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
+    }
+    #[doc = "Set to 0 to stop the low power osc when the switched-core is powered down, which is unwise if using it to clock the timer This setting takes effect when the swcore is next powered down"]
+    #[inline(always)]
+    pub const fn run_lposc_in_lp(&self) -> bool {
+        let val = (self.0 >> 8usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Set to 0 to stop the low power osc when the switched-core is powered down, which is unwise if using it to clock the timer This setting takes effect when the swcore is next powered down"]
+    #[inline(always)]
+    pub fn set_run_lposc_in_lp(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
+    }
+    #[doc = "selects the reference clock (clk_ref) as the source of the POWMAN clock when switched-core is powered. The POWMAN clock always switches to the slow clock (lposc) when switched-core is powered down because the fast clock stops running. 0 always run the POWMAN clock from the slow clock (lposc) 1 run the POWMAN clock from the fast clock when available This setting takes effect when a power up sequence is next run"]
+    #[inline(always)]
+    pub const fn use_fast_powck(&self) -> bool {
+        let val = (self.0 >> 12usize) & 0x01;
+        val != 0
+    }
+    #[doc = "selects the reference clock (clk_ref) as the source of the POWMAN clock when switched-core is powered. The POWMAN clock always switches to the slow clock (lposc) when switched-core is powered down because the fast clock stops running. 0 always run the POWMAN clock from the slow clock (lposc) 1 run the POWMAN clock from the fast clock when available This setting takes effect when a power up sequence is next run"]
+    #[inline(always)]
+    pub fn set_use_fast_powck(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
+    }
+    #[doc = "Indicates the voltage regulator (VREG) mode 0 = VREG high power mode which is the default 1 = VREG low power mode"]
+    #[inline(always)]
+    pub const fn using_vreg_lp(&self) -> bool {
+        let val = (self.0 >> 16usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Indicates the voltage regulator (VREG) mode 0 = VREG high power mode which is the default 1 = VREG low power mode"]
+    #[inline(always)]
+    pub fn set_using_vreg_lp(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
+    }
+    #[doc = "Indicates the brown-out detector (BOD) mode 0 = BOD high power mode which is the default 1 = BOD low power mode"]
+    #[inline(always)]
+    pub const fn using_bod_lp(&self) -> bool {
+        let val = (self.0 >> 17usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Indicates the brown-out detector (BOD) mode 0 = BOD high power mode which is the default 1 = BOD low power mode"]
+    #[inline(always)]
+    pub fn set_using_bod_lp(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
+    }
+    #[doc = "0 indicates the POWMAN clock is running from the low power oscillator (32kHz) 1 indicates the POWMAN clock is running from the reference clock (2-50MHz)"]
+    #[inline(always)]
+    pub const fn using_fast_powck(&self) -> bool {
+        let val = (self.0 >> 20usize) & 0x01;
+        val != 0
+    }
+    #[doc = "0 indicates the POWMAN clock is running from the low power oscillator (32kHz) 1 indicates the POWMAN clock is running from the reference clock (2-50MHz)"]
+    #[inline(always)]
+    pub fn set_using_fast_powck(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize);
+    }
+}
+impl Default for SeqCfg {
+    #[inline(always)]
+    fn default() -> SeqCfg {
+        SeqCfg(0)
+    }
+}
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct SetTime15to0(pub u32);
+impl SetTime15to0 {
+    #[doc = "For setting the time, do not use for reading the time, use POWMAN_READ_TIME_UPPER and POWMAN_READ_TIME_LOWER. This field must only be written when POWMAN_TIMER_RUN=0"]
+    #[inline(always)]
+    pub const fn set_time_15to0(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0xffff;
+        val as u16
+    }
+    #[doc = "For setting the time, do not use for reading the time, use POWMAN_READ_TIME_UPPER and POWMAN_READ_TIME_LOWER. This field must only be written when POWMAN_TIMER_RUN=0"]
+    #[inline(always)]
+    pub fn set_set_time_15to0(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+    }
+}
+impl Default for SetTime15to0 {
+    #[inline(always)]
+    fn default() -> SetTime15to0 {
+        SetTime15to0(0)
+    }
+}
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct SetTime31to16(pub u32);
+impl SetTime31to16 {
+    #[doc = "For setting the time, do not use for reading the time, use POWMAN_READ_TIME_UPPER and POWMAN_READ_TIME_LOWER. This field must only be written when POWMAN_TIMER_RUN=0"]
+    #[inline(always)]
+    pub const fn set_time_31to16(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0xffff;
+        val as u16
+    }
+    #[doc = "For setting the time, do not use for reading the time, use POWMAN_READ_TIME_UPPER and POWMAN_READ_TIME_LOWER. This field must only be written when POWMAN_TIMER_RUN=0"]
+    #[inline(always)]
+    pub fn set_set_time_31to16(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+    }
+}
+impl Default for SetTime31to16 {
+    #[inline(always)]
+    fn default() -> SetTime31to16 {
+        SetTime31to16(0)
+    }
+}
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct SetTime47to32(pub u32);
+impl SetTime47to32 {
+    #[doc = "For setting the time, do not use for reading the time, use POWMAN_READ_TIME_UPPER and POWMAN_READ_TIME_LOWER. This field must only be written when POWMAN_TIMER_RUN=0"]
+    #[inline(always)]
+    pub const fn set_time_47to32(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0xffff;
+        val as u16
+    }
+    #[doc = "For setting the time, do not use for reading the time, use POWMAN_READ_TIME_UPPER and POWMAN_READ_TIME_LOWER. This field must only be written when POWMAN_TIMER_RUN=0"]
+    #[inline(always)]
+    pub fn set_set_time_47to32(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+    }
+}
+impl Default for SetTime47to32 {
+    #[inline(always)]
+    fn default() -> SetTime47to32 {
+        SetTime47to32(0)
+    }
+}
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct SetTime63to48(pub u32);
+impl SetTime63to48 {
+    #[doc = "For setting the time, do not use for reading the time, use POWMAN_READ_TIME_UPPER and POWMAN_READ_TIME_LOWER. This field must only be written when POWMAN_TIMER_RUN=0"]
+    #[inline(always)]
+    pub const fn set_time_63to48(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0xffff;
+        val as u16
+    }
+    #[doc = "For setting the time, do not use for reading the time, use POWMAN_READ_TIME_UPPER and POWMAN_READ_TIME_LOWER. This field must only be written when POWMAN_TIMER_RUN=0"]
+    #[inline(always)]
+    pub fn set_set_time_63to48(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+    }
+}
+impl Default for SetTime63to48 {
+    #[inline(always)]
+    fn default() -> SetTime63to48 {
+        SetTime63to48(0)
+    }
+}
+#[doc = "This register controls the power state of the 4 power domains. The current power state is indicated in POWMAN_STATE_CURRENT which is read-only. To change the state, write to POWMAN_STATE_REQ. The coding of POWMAN_STATE_CURRENT & POWMAN_STATE_REQ corresponds to the power states defined in the datasheet: bit 3 = SWCORE bit 2 = XIP cache bit 1 = SRAM0 bit 0 = SRAM1 0 = powered up 1 = powered down When POWMAN_STATE_REQ is written, the POWMAN_STATE_WAITING flag is set while the Power Manager determines what is required. If an invalid transition is requested the Power Manager will still register the request in POWMAN_STATE_REQ but will also set the POWMAN_BAD_REQ flag. It will then implement the power-up requests and ignore the power down requests. To do nothing would risk entering an unrecoverable lock-up state. Invalid requests are: any combination of power up and power down requests any request that results in swcore boing powered and xip unpowered If the request is to power down the switched-core domain then POWMAN_STATE_WAITING stays active until the processors halt. During this time the POWMAN_STATE_REQ field can be re-written to change or cancel the request. When the power state transition begins the POWMAN_STATE_WAITING_flag is cleared, the POWMAN_STATE_CHANGING flag is set and POWMAN register writes are ignored until the transition completes."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct State(pub u32);
+impl State {
+    #[inline(always)]
+    pub const fn current(&self) -> u8 {
+        let val = (self.0 >> 0usize) & 0x0f;
+        val as u8
+    }
+    #[inline(always)]
+    pub fn set_current(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize);
+    }
+    #[inline(always)]
+    pub const fn req(&self) -> u8 {
+        let val = (self.0 >> 4usize) & 0x0f;
+        val as u8
+    }
+    #[inline(always)]
+    pub fn set_req(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x0f << 4usize)) | (((val as u32) & 0x0f) << 4usize);
+    }
+    #[inline(always)]
+    pub const fn req_ignored(&self) -> bool {
+        let val = (self.0 >> 8usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_req_ignored(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
+    }
+    #[doc = "Request ignored because of a pending pwrup request. See current_pwrup_req. Note this blocks powering up AND powering down."]
+    #[inline(always)]
+    pub const fn pwrup_while_waiting(&self) -> bool {
+        let val = (self.0 >> 9usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Request ignored because of a pending pwrup request. See current_pwrup_req. Note this blocks powering up AND powering down."]
+    #[inline(always)]
+    pub fn set_pwrup_while_waiting(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
+    }
+    #[doc = "Bad software initiated state request. No action taken."]
+    #[inline(always)]
+    pub const fn bad_sw_req(&self) -> bool {
+        let val = (self.0 >> 10usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Bad software initiated state request. No action taken."]
+    #[inline(always)]
+    pub fn set_bad_sw_req(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize);
+    }
+    #[doc = "Bad hardware initiated state request. Went back to state 0 (i.e. everything powered up)"]
+    #[inline(always)]
+    pub const fn bad_hw_req(&self) -> bool {
+        let val = (self.0 >> 11usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Bad hardware initiated state request. Went back to state 0 (i.e. everything powered up)"]
+    #[inline(always)]
+    pub fn set_bad_hw_req(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
+    }
+    #[inline(always)]
+    pub const fn waiting(&self) -> bool {
+        let val = (self.0 >> 12usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_waiting(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
+    }
+    #[inline(always)]
+    pub const fn changing(&self) -> bool {
+        let val = (self.0 >> 13usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_changing(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize);
+    }
+}
+impl Default for State {
+    #[inline(always)]
+    fn default() -> State {
+        State(0)
+    }
+}
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Timer(pub u32);
+impl Timer {
+    #[doc = "Control whether Non-secure software can write to the timer registers. All other registers are hardwired to be inaccessible to Non-secure."]
+    #[inline(always)]
+    pub const fn nonsec_write(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Control whether Non-secure software can write to the timer registers. All other registers are hardwired to be inaccessible to Non-secure."]
+    #[inline(always)]
+    pub fn set_nonsec_write(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[doc = "Timer enable. Setting this bit causes the timer to begin counting up from its current value. Clearing this bit stops the timer from counting. Before enabling the timer, set the POWMAN_LPOSC_FREQ* and POWMAN_XOSC_FREQ* registers to configure the count rate, and initialise the current time by writing to SET_TIME_63TO48 through SET_TIME_15TO0. You must not write to the SET_TIME_x registers when the timer is running. Once configured, start the timer by setting POWMAN_TIMER_RUN=1. This will start the timer running from the LPOSC. When the XOSC is available switch the reference clock to XOSC then select it as the timer clock by setting POWMAN_TIMER_USE_XOSC=1"]
+    #[inline(always)]
+    pub const fn run(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Timer enable. Setting this bit causes the timer to begin counting up from its current value. Clearing this bit stops the timer from counting. Before enabling the timer, set the POWMAN_LPOSC_FREQ* and POWMAN_XOSC_FREQ* registers to configure the count rate, and initialise the current time by writing to SET_TIME_63TO48 through SET_TIME_15TO0. You must not write to the SET_TIME_x registers when the timer is running. Once configured, start the timer by setting POWMAN_TIMER_RUN=1. This will start the timer running from the LPOSC. When the XOSC is available switch the reference clock to XOSC then select it as the timer clock by setting POWMAN_TIMER_USE_XOSC=1"]
+    #[inline(always)]
+    pub fn set_run(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+    #[doc = "Clears the timer, does not disable the timer and does not affect the alarm. This control can be written at any time."]
+    #[inline(always)]
+    pub const fn clear(&self) -> bool {
+        let val = (self.0 >> 2usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Clears the timer, does not disable the timer and does not affect the alarm. This control can be written at any time."]
+    #[inline(always)]
+    pub fn set_clear(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+    }
+    #[doc = "Enables the alarm. The alarm must be disabled while writing the alarm time."]
+    #[inline(always)]
+    pub const fn alarm_enab(&self) -> bool {
+        let val = (self.0 >> 4usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Enables the alarm. The alarm must be disabled while writing the alarm time."]
+    #[inline(always)]
+    pub fn set_alarm_enab(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
+    }
+    #[doc = "Alarm wakes the chip from low power mode"]
+    #[inline(always)]
+    pub const fn pwrup_on_alarm(&self) -> bool {
+        let val = (self.0 >> 5usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Alarm wakes the chip from low power mode"]
+    #[inline(always)]
+    pub fn set_pwrup_on_alarm(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
+    }
+    #[doc = "Alarm has fired. Write to 1 to clear the alarm."]
+    #[inline(always)]
+    pub const fn alarm(&self) -> bool {
+        let val = (self.0 >> 6usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Alarm has fired. Write to 1 to clear the alarm."]
+    #[inline(always)]
+    pub fn set_alarm(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
+    }
+    #[doc = "Switch to lposc as the source of the 1kHz timer tick"]
+    #[inline(always)]
+    pub const fn use_lposc(&self) -> bool {
+        let val = (self.0 >> 8usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Switch to lposc as the source of the 1kHz timer tick"]
+    #[inline(always)]
+    pub fn set_use_lposc(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
+    }
+    #[doc = "switch to xosc as the source of the 1kHz timer tick"]
+    #[inline(always)]
+    pub const fn use_xosc(&self) -> bool {
+        let val = (self.0 >> 9usize) & 0x01;
+        val != 0
+    }
+    #[doc = "switch to xosc as the source of the 1kHz timer tick"]
+    #[inline(always)]
+    pub fn set_use_xosc(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
+    }
+    #[doc = "switch to gpio as the source of the 1kHz timer tick"]
+    #[inline(always)]
+    pub const fn use_gpio_1khz(&self) -> bool {
+        let val = (self.0 >> 10usize) & 0x01;
+        val != 0
+    }
+    #[doc = "switch to gpio as the source of the 1kHz timer tick"]
+    #[inline(always)]
+    pub fn set_use_gpio_1khz(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize);
+    }
+    #[doc = "Selects the gpio source as the reference for the sec counter. The msec counter will continue to use the lposc or xosc reference."]
+    #[inline(always)]
+    pub const fn use_gpio_1hz(&self) -> bool {
+        let val = (self.0 >> 13usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Selects the gpio source as the reference for the sec counter. The msec counter will continue to use the lposc or xosc reference."]
+    #[inline(always)]
+    pub fn set_use_gpio_1hz(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize);
+    }
+    #[doc = "Timer is running from xosc"]
+    #[inline(always)]
+    pub const fn using_xosc(&self) -> bool {
+        let val = (self.0 >> 16usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Timer is running from xosc"]
+    #[inline(always)]
+    pub fn set_using_xosc(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
+    }
+    #[doc = "Timer is running from lposc"]
+    #[inline(always)]
+    pub const fn using_lposc(&self) -> bool {
+        let val = (self.0 >> 17usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Timer is running from lposc"]
+    #[inline(always)]
+    pub fn set_using_lposc(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
+    }
+    #[doc = "Timer is running from a 1khz gpio source"]
+    #[inline(always)]
+    pub const fn using_gpio_1khz(&self) -> bool {
+        let val = (self.0 >> 18usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Timer is running from a 1khz gpio source"]
+    #[inline(always)]
+    pub fn set_using_gpio_1khz(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize);
+    }
+    #[doc = "Timer is synchronised to a 1hz gpio source"]
+    #[inline(always)]
+    pub const fn using_gpio_1hz(&self) -> bool {
+        let val = (self.0 >> 19usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Timer is synchronised to a 1hz gpio source"]
+    #[inline(always)]
+    pub fn set_using_gpio_1hz(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize);
+    }
+}
+impl Default for Timer {
+    #[inline(always)]
+    fn default() -> Timer {
+        Timer(0)
+    }
+}
+#[doc = "Voltage Regulator Settings"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Vreg(pub u32);
+impl Vreg {
+    #[doc = "high impedance mode select 0=not in high impedance mode, 1=in high impedance mode"]
+    #[inline(always)]
+    pub const fn hiz(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[doc = "high impedance mode select 0=not in high impedance mode, 1=in high impedance mode"]
+    #[inline(always)]
+    pub fn set_hiz(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+    #[doc = "output voltage select the regulator output voltage is limited to 1.3V unless the voltage limit is disabled using the disable_voltage_limit field in the vreg_ctrl register 00000 - 0.55V 00001 - 0.60V 00010 - 0.65V 00011 - 0.70V 00100 - 0.75V 00101 - 0.80V 00110 - 0.85V 00111 - 0.90V 01000 - 0.95V 01001 - 1.00V 01010 - 1.05V 01011 - 1.10V (default) 01100 - 1.15V 01101 - 1.20V 01110 - 1.25V 01111 - 1.30V 10000 - 1.35V 10001 - 1.40V 10010 - 1.50V 10011 - 1.60V 10100 - 1.65V 10101 - 1.70V 10110 - 1.80V 10111 - 1.90V 11000 - 2.00V 11001 - 2.35V 11010 - 2.50V 11011 - 2.65V 11100 - 2.80V 11101 - 3.00V 11110 - 3.15V 11111 - 3.30V"]
+    #[inline(always)]
+    pub const fn vsel(&self) -> u8 {
+        let val = (self.0 >> 4usize) & 0x1f;
+        val as u8
+    }
+    #[doc = "output voltage select the regulator output voltage is limited to 1.3V unless the voltage limit is disabled using the disable_voltage_limit field in the vreg_ctrl register 00000 - 0.55V 00001 - 0.60V 00010 - 0.65V 00011 - 0.70V 00100 - 0.75V 00101 - 0.80V 00110 - 0.85V 00111 - 0.90V 01000 - 0.95V 01001 - 1.00V 01010 - 1.05V 01011 - 1.10V (default) 01100 - 1.15V 01101 - 1.20V 01110 - 1.25V 01111 - 1.30V 10000 - 1.35V 10001 - 1.40V 10010 - 1.50V 10011 - 1.60V 10100 - 1.65V 10101 - 1.70V 10110 - 1.80V 10111 - 1.90V 11000 - 2.00V 11001 - 2.35V 11010 - 2.50V 11011 - 2.65V 11100 - 2.80V 11101 - 3.00V 11110 - 3.15V 11111 - 3.30V"]
+    #[inline(always)]
+    pub fn set_vsel(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x1f << 4usize)) | (((val as u32) & 0x1f) << 4usize);
+    }
+    #[doc = "regulator state is being updated writes to the vreg register will be ignored when this field is set"]
+    #[inline(always)]
+    pub const fn update_in_progress(&self) -> bool {
+        let val = (self.0 >> 15usize) & 0x01;
+        val != 0
+    }
+    #[doc = "regulator state is being updated writes to the vreg register will be ignored when this field is set"]
+    #[inline(always)]
+    pub fn set_update_in_progress(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize);
+    }
+}
+impl Default for Vreg {
+    #[inline(always)]
+    fn default() -> Vreg {
+        Vreg(0)
+    }
+}
+#[doc = "Voltage Regulator Control"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct VregCtrl(pub u32);
+impl VregCtrl {
+    #[doc = "high temperature protection threshold regulator power transistors are disabled when junction temperature exceeds threshold 000 - 100C 001 - 105C 010 - 110C 011 - 115C 100 - 120C 101 - 125C 110 - 135C 111 - 150C"]
+    #[inline(always)]
+    pub const fn ht_th(&self) -> u8 {
+        let val = (self.0 >> 4usize) & 0x07;
+        val as u8
+    }
+    #[doc = "high temperature protection threshold regulator power transistors are disabled when junction temperature exceeds threshold 000 - 100C 001 - 105C 010 - 110C 011 - 115C 100 - 120C 101 - 125C 110 - 135C 111 - 150C"]
+    #[inline(always)]
+    pub fn set_ht_th(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x07 << 4usize)) | (((val as u32) & 0x07) << 4usize);
+    }
+    #[doc = "0=not disabled, 1=enabled"]
+    #[inline(always)]
+    pub const fn disable_voltage_limit(&self) -> bool {
+        let val = (self.0 >> 8usize) & 0x01;
+        val != 0
+    }
+    #[doc = "0=not disabled, 1=enabled"]
+    #[inline(always)]
+    pub fn set_disable_voltage_limit(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
+    }
+    #[doc = "isolates the VREG control interface 0 - not isolated (default) 1 - isolated"]
+    #[inline(always)]
+    pub const fn isolate(&self) -> bool {
+        let val = (self.0 >> 12usize) & 0x01;
+        val != 0
+    }
+    #[doc = "isolates the VREG control interface 0 - not isolated (default) 1 - isolated"]
+    #[inline(always)]
+    pub fn set_isolate(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
+    }
+    #[doc = "unlocks the VREG control interface after power up 0 - Locked (default) 1 - Unlocked It cannot be relocked when it is unlocked."]
+    #[inline(always)]
+    pub const fn unlock(&self) -> bool {
+        let val = (self.0 >> 13usize) & 0x01;
+        val != 0
+    }
+    #[doc = "unlocks the VREG control interface after power up 0 - Locked (default) 1 - Unlocked It cannot be relocked when it is unlocked."]
+    #[inline(always)]
+    pub fn set_unlock(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize);
+    }
+    #[doc = "returns the regulator to its startup settings 0 - reset 1 - not reset (default)"]
+    #[inline(always)]
+    pub const fn rst_n(&self) -> bool {
+        let val = (self.0 >> 15usize) & 0x01;
+        val != 0
+    }
+    #[doc = "returns the regulator to its startup settings 0 - reset 1 - not reset (default)"]
+    #[inline(always)]
+    pub fn set_rst_n(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize);
+    }
+}
+impl Default for VregCtrl {
+    #[inline(always)]
+    fn default() -> VregCtrl {
+        VregCtrl(0)
+    }
+}
+#[doc = "Voltage Regulator Low Power Entry Settings"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct VregLpEntry(pub u32);
+impl VregLpEntry {
+    #[doc = "high impedance mode select 0=not in high impedance mode, 1=in high impedance mode"]
+    #[inline(always)]
+    pub const fn hiz(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[doc = "high impedance mode select 0=not in high impedance mode, 1=in high impedance mode"]
+    #[inline(always)]
+    pub fn set_hiz(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+    #[doc = "selects either normal (switching) mode or low power (linear) mode low power mode can only be selected for output voltages up to 1.3V 0 = normal mode (switching) 1 = low power mode (linear)"]
+    #[inline(always)]
+    pub const fn mode(&self) -> bool {
+        let val = (self.0 >> 2usize) & 0x01;
+        val != 0
+    }
+    #[doc = "selects either normal (switching) mode or low power (linear) mode low power mode can only be selected for output voltages up to 1.3V 0 = normal mode (switching) 1 = low power mode (linear)"]
+    #[inline(always)]
+    pub fn set_mode(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+    }
+    #[doc = "output voltage select the regulator output voltage is limited to 1.3V unless the voltage limit is disabled using the disable_voltage_limit field in the vreg_ctrl register 00000 - 0.55V 00001 - 0.60V 00010 - 0.65V 00011 - 0.70V 00100 - 0.75V 00101 - 0.80V 00110 - 0.85V 00111 - 0.90V 01000 - 0.95V 01001 - 1.00V 01010 - 1.05V 01011 - 1.10V (default) 01100 - 1.15V 01101 - 1.20V 01110 - 1.25V 01111 - 1.30V 10000 - 1.35V 10001 - 1.40V 10010 - 1.50V 10011 - 1.60V 10100 - 1.65V 10101 - 1.70V 10110 - 1.80V 10111 - 1.90V 11000 - 2.00V 11001 - 2.35V 11010 - 2.50V 11011 - 2.65V 11100 - 2.80V 11101 - 3.00V 11110 - 3.15V 11111 - 3.30V"]
+    #[inline(always)]
+    pub const fn vsel(&self) -> u8 {
+        let val = (self.0 >> 4usize) & 0x1f;
+        val as u8
+    }
+    #[doc = "output voltage select the regulator output voltage is limited to 1.3V unless the voltage limit is disabled using the disable_voltage_limit field in the vreg_ctrl register 00000 - 0.55V 00001 - 0.60V 00010 - 0.65V 00011 - 0.70V 00100 - 0.75V 00101 - 0.80V 00110 - 0.85V 00111 - 0.90V 01000 - 0.95V 01001 - 1.00V 01010 - 1.05V 01011 - 1.10V (default) 01100 - 1.15V 01101 - 1.20V 01110 - 1.25V 01111 - 1.30V 10000 - 1.35V 10001 - 1.40V 10010 - 1.50V 10011 - 1.60V 10100 - 1.65V 10101 - 1.70V 10110 - 1.80V 10111 - 1.90V 11000 - 2.00V 11001 - 2.35V 11010 - 2.50V 11011 - 2.65V 11100 - 2.80V 11101 - 3.00V 11110 - 3.15V 11111 - 3.30V"]
+    #[inline(always)]
+    pub fn set_vsel(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x1f << 4usize)) | (((val as u32) & 0x1f) << 4usize);
+    }
+}
+impl Default for VregLpEntry {
+    #[inline(always)]
+    fn default() -> VregLpEntry {
+        VregLpEntry(0)
+    }
+}
+#[doc = "Voltage Regulator Low Power Exit Settings"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct VregLpExit(pub u32);
+impl VregLpExit {
+    #[doc = "high impedance mode select 0=not in high impedance mode, 1=in high impedance mode"]
+    #[inline(always)]
+    pub const fn hiz(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[doc = "high impedance mode select 0=not in high impedance mode, 1=in high impedance mode"]
+    #[inline(always)]
+    pub fn set_hiz(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+    #[doc = "selects either normal (switching) mode or low power (linear) mode low power mode can only be selected for output voltages up to 1.3V 0 = normal mode (switching) 1 = low power mode (linear)"]
+    #[inline(always)]
+    pub const fn mode(&self) -> bool {
+        let val = (self.0 >> 2usize) & 0x01;
+        val != 0
+    }
+    #[doc = "selects either normal (switching) mode or low power (linear) mode low power mode can only be selected for output voltages up to 1.3V 0 = normal mode (switching) 1 = low power mode (linear)"]
+    #[inline(always)]
+    pub fn set_mode(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+    }
+    #[doc = "output voltage select the regulator output voltage is limited to 1.3V unless the voltage limit is disabled using the disable_voltage_limit field in the vreg_ctrl register 00000 - 0.55V 00001 - 0.60V 00010 - 0.65V 00011 - 0.70V 00100 - 0.75V 00101 - 0.80V 00110 - 0.85V 00111 - 0.90V 01000 - 0.95V 01001 - 1.00V 01010 - 1.05V 01011 - 1.10V (default) 01100 - 1.15V 01101 - 1.20V 01110 - 1.25V 01111 - 1.30V 10000 - 1.35V 10001 - 1.40V 10010 - 1.50V 10011 - 1.60V 10100 - 1.65V 10101 - 1.70V 10110 - 1.80V 10111 - 1.90V 11000 - 2.00V 11001 - 2.35V 11010 - 2.50V 11011 - 2.65V 11100 - 2.80V 11101 - 3.00V 11110 - 3.15V 11111 - 3.30V"]
+    #[inline(always)]
+    pub const fn vsel(&self) -> u8 {
+        let val = (self.0 >> 4usize) & 0x1f;
+        val as u8
+    }
+    #[doc = "output voltage select the regulator output voltage is limited to 1.3V unless the voltage limit is disabled using the disable_voltage_limit field in the vreg_ctrl register 00000 - 0.55V 00001 - 0.60V 00010 - 0.65V 00011 - 0.70V 00100 - 0.75V 00101 - 0.80V 00110 - 0.85V 00111 - 0.90V 01000 - 0.95V 01001 - 1.00V 01010 - 1.05V 01011 - 1.10V (default) 01100 - 1.15V 01101 - 1.20V 01110 - 1.25V 01111 - 1.30V 10000 - 1.35V 10001 - 1.40V 10010 - 1.50V 10011 - 1.60V 10100 - 1.65V 10101 - 1.70V 10110 - 1.80V 10111 - 1.90V 11000 - 2.00V 11001 - 2.35V 11010 - 2.50V 11011 - 2.65V 11100 - 2.80V 11101 - 3.00V 11110 - 3.15V 11111 - 3.30V"]
+    #[inline(always)]
+    pub fn set_vsel(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x1f << 4usize)) | (((val as u32) & 0x1f) << 4usize);
+    }
+}
+impl Default for VregLpExit {
+    #[inline(always)]
+    fn default() -> VregLpExit {
+        VregLpExit(0)
+    }
+}
+#[doc = "Voltage Regulator Status"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct VregSts(pub u32);
+impl VregSts {
+    #[doc = "startup status 0=startup complete, 1=starting up"]
+    #[inline(always)]
+    pub const fn startup(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "startup status 0=startup complete, 1=starting up"]
+    #[inline(always)]
+    pub fn set_startup(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[doc = "output regulation status 0=not in regulation, 1=in regulation"]
+    #[inline(always)]
+    pub const fn vout_ok(&self) -> bool {
+        let val = (self.0 >> 4usize) & 0x01;
+        val != 0
+    }
+    #[doc = "output regulation status 0=not in regulation, 1=in regulation"]
+    #[inline(always)]
+    pub fn set_vout_ok(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
+    }
+}
+impl Default for VregSts {
+    #[inline(always)]
+    fn default() -> VregSts {
+        VregSts(0)
+    }
+}
+#[doc = "Allows a watchdog reset to reset the internal state of powman in addition to the power-on state machine (PSM). Note that powman ignores watchdog resets that do not select at least the CLOCKS stage or earlier stages in the PSM. If using these bits, it's recommended to set PSM_WDSEL to all-ones in addition to the desired bits in this register. Failing to select CLOCKS or earlier will result in the POWMAN_WDSEL register having no effect."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Wdsel(pub u32);
+impl Wdsel {
+    #[doc = "If set to 1, a watchdog reset will restore powman defaults, reset the timer, reset the switched core domain and run the full power-on state machine (PSM) sequence This does not rely on clk_ref running"]
+    #[inline(always)]
+    pub const fn reset_powman_async(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If set to 1, a watchdog reset will restore powman defaults, reset the timer, reset the switched core domain and run the full power-on state machine (PSM) sequence This does not rely on clk_ref running"]
+    #[inline(always)]
+    pub fn set_reset_powman_async(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[doc = "If set to 1, a watchdog reset will restore powman defaults, reset the timer, reset the switched core power domain and run the full power-on state machine (PSM) sequence This relies on clk_ref running. Use reset_powman_async if that may not be true"]
+    #[inline(always)]
+    pub const fn reset_powman(&self) -> bool {
+        let val = (self.0 >> 4usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If set to 1, a watchdog reset will restore powman defaults, reset the timer, reset the switched core power domain and run the full power-on state machine (PSM) sequence This relies on clk_ref running. Use reset_powman_async if that may not be true"]
+    #[inline(always)]
+    pub fn set_reset_powman(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
+    }
+    #[doc = "If set to 1, a watchdog reset will reset the switched core power domain and run the full power-on state machine (PSM) sequence From a user perspective it is the same as setting RSM_WDSEL_PROC_COLD From a hardware debug perspective it has the same effect as a power-on reset for the switched core power domain"]
+    #[inline(always)]
+    pub const fn reset_swcore(&self) -> bool {
+        let val = (self.0 >> 8usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If set to 1, a watchdog reset will reset the switched core power domain and run the full power-on state machine (PSM) sequence From a user perspective it is the same as setting RSM_WDSEL_PROC_COLD From a hardware debug perspective it has the same effect as a power-on reset for the switched core power domain"]
+    #[inline(always)]
+    pub fn set_reset_swcore(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
+    }
+    #[doc = "If set to 1, a watchdog reset will run the full power-on state machine (PSM) sequence From a user perspective it is the same as setting RSM_WDSEL_PROC_COLD From a hardware debug perspective it has the same effect as a reset from a glitch detector"]
+    #[inline(always)]
+    pub const fn reset_rsm(&self) -> bool {
+        let val = (self.0 >> 12usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If set to 1, a watchdog reset will run the full power-on state machine (PSM) sequence From a user perspective it is the same as setting RSM_WDSEL_PROC_COLD From a hardware debug perspective it has the same effect as a reset from a glitch detector"]
+    #[inline(always)]
+    pub fn set_reset_rsm(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
+    }
+}
+impl Default for Wdsel {
+    #[inline(always)]
+    fn default() -> Wdsel {
+        Wdsel(0)
+    }
+}
+#[doc = "Informs the AON Timer of the fractional component of the clock frequency when running off the XOSC."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct XoscFreqKhzFrac(pub u32);
+impl XoscFreqKhzFrac {
+    #[doc = "Fractional component of the XOSC frequency in kHz. This field must only be written when POWMAN_TIMER_RUN=0 or POWMAN_TIMER_USING_XOSC=0"]
+    #[inline(always)]
+    pub const fn xosc_freq_khz_frac(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0xffff;
+        val as u16
+    }
+    #[doc = "Fractional component of the XOSC frequency in kHz. This field must only be written when POWMAN_TIMER_RUN=0 or POWMAN_TIMER_USING_XOSC=0"]
+    #[inline(always)]
+    pub fn set_xosc_freq_khz_frac(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+    }
+}
+impl Default for XoscFreqKhzFrac {
+    #[inline(always)]
+    fn default() -> XoscFreqKhzFrac {
+        XoscFreqKhzFrac(0)
+    }
+}
+#[doc = "Informs the AON Timer of the integer component of the clock frequency when running off the XOSC."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct XoscFreqKhzInt(pub u32);
+impl XoscFreqKhzInt {
+    #[doc = "Integer component of the XOSC frequency in kHz. Default = 12000 Must be >1 This field must only be written when POWMAN_TIMER_RUN=0 or POWMAN_TIMER_USING_XOSC=0"]
+    #[inline(always)]
+    pub const fn xosc_freq_khz_int(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0xffff;
+        val as u16
+    }
+    #[doc = "Integer component of the XOSC frequency in kHz. Default = 12000 Must be >1 This field must only be written when POWMAN_TIMER_RUN=0 or POWMAN_TIMER_USING_XOSC=0"]
+    #[inline(always)]
+    pub fn set_xosc_freq_khz_int(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+    }
+}
+impl Default for XoscFreqKhzInt {
+    #[inline(always)]
+    fn default() -> XoscFreqKhzInt {
+        XoscFreqKhzInt(0)
+    }
+}
diff --git a/src/rp2350/powman/vals.rs b/src/rp2350/powman/vals.rs
new file mode 100644
index 00000000..22a4e0ce
--- /dev/null
+++ b/src/rp2350/powman/vals.rs
@@ -0,0 +1,224 @@
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Pwrup0direction {
+    LOW_FALLING = 0,
+    HIGH_RISING = 0x01,
+}
+impl Pwrup0direction {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Pwrup0direction {
+        unsafe { core::mem::transmute(val & 0x01) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Pwrup0direction {
+    #[inline(always)]
+    fn from(val: u8) -> Pwrup0direction {
+        Pwrup0direction::from_bits(val)
+    }
+}
+impl From<Pwrup0direction> for u8 {
+    #[inline(always)]
+    fn from(val: Pwrup0direction) -> u8 {
+        Pwrup0direction::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Pwrup0mode {
+    LEVEL = 0,
+    EDGE = 0x01,
+}
+impl Pwrup0mode {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Pwrup0mode {
+        unsafe { core::mem::transmute(val & 0x01) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Pwrup0mode {
+    #[inline(always)]
+    fn from(val: u8) -> Pwrup0mode {
+        Pwrup0mode::from_bits(val)
+    }
+}
+impl From<Pwrup0mode> for u8 {
+    #[inline(always)]
+    fn from(val: Pwrup0mode) -> u8 {
+        Pwrup0mode::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Pwrup1direction {
+    LOW_FALLING = 0,
+    HIGH_RISING = 0x01,
+}
+impl Pwrup1direction {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Pwrup1direction {
+        unsafe { core::mem::transmute(val & 0x01) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Pwrup1direction {
+    #[inline(always)]
+    fn from(val: u8) -> Pwrup1direction {
+        Pwrup1direction::from_bits(val)
+    }
+}
+impl From<Pwrup1direction> for u8 {
+    #[inline(always)]
+    fn from(val: Pwrup1direction) -> u8 {
+        Pwrup1direction::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Pwrup1mode {
+    LEVEL = 0,
+    EDGE = 0x01,
+}
+impl Pwrup1mode {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Pwrup1mode {
+        unsafe { core::mem::transmute(val & 0x01) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Pwrup1mode {
+    #[inline(always)]
+    fn from(val: u8) -> Pwrup1mode {
+        Pwrup1mode::from_bits(val)
+    }
+}
+impl From<Pwrup1mode> for u8 {
+    #[inline(always)]
+    fn from(val: Pwrup1mode) -> u8 {
+        Pwrup1mode::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Pwrup2direction {
+    LOW_FALLING = 0,
+    HIGH_RISING = 0x01,
+}
+impl Pwrup2direction {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Pwrup2direction {
+        unsafe { core::mem::transmute(val & 0x01) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Pwrup2direction {
+    #[inline(always)]
+    fn from(val: u8) -> Pwrup2direction {
+        Pwrup2direction::from_bits(val)
+    }
+}
+impl From<Pwrup2direction> for u8 {
+    #[inline(always)]
+    fn from(val: Pwrup2direction) -> u8 {
+        Pwrup2direction::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Pwrup2mode {
+    LEVEL = 0,
+    EDGE = 0x01,
+}
+impl Pwrup2mode {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Pwrup2mode {
+        unsafe { core::mem::transmute(val & 0x01) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Pwrup2mode {
+    #[inline(always)]
+    fn from(val: u8) -> Pwrup2mode {
+        Pwrup2mode::from_bits(val)
+    }
+}
+impl From<Pwrup2mode> for u8 {
+    #[inline(always)]
+    fn from(val: Pwrup2mode) -> u8 {
+        Pwrup2mode::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Pwrup3direction {
+    LOW_FALLING = 0,
+    HIGH_RISING = 0x01,
+}
+impl Pwrup3direction {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Pwrup3direction {
+        unsafe { core::mem::transmute(val & 0x01) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Pwrup3direction {
+    #[inline(always)]
+    fn from(val: u8) -> Pwrup3direction {
+        Pwrup3direction::from_bits(val)
+    }
+}
+impl From<Pwrup3direction> for u8 {
+    #[inline(always)]
+    fn from(val: Pwrup3direction) -> u8 {
+        Pwrup3direction::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Pwrup3mode {
+    LEVEL = 0,
+    EDGE = 0x01,
+}
+impl Pwrup3mode {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Pwrup3mode {
+        unsafe { core::mem::transmute(val & 0x01) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Pwrup3mode {
+    #[inline(always)]
+    fn from(val: u8) -> Pwrup3mode {
+        Pwrup3mode::from_bits(val)
+    }
+}
+impl From<Pwrup3mode> for u8 {
+    #[inline(always)]
+    fn from(val: Pwrup3mode) -> u8 {
+        Pwrup3mode::to_bits(val)
+    }
+}
diff --git a/src/rp2350/psm.rs b/src/rp2350/psm.rs
new file mode 100644
index 00000000..17805bc3
--- /dev/null
+++ b/src/rp2350/psm.rs
@@ -0,0 +1,37 @@
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Psm {
+    ptr: *mut u8,
+}
+unsafe impl Send for Psm {}
+unsafe impl Sync for Psm {}
+impl Psm {
+    #[inline(always)]
+    pub const unsafe fn from_ptr(ptr: *mut ()) -> Self {
+        Self { ptr: ptr as _ }
+    }
+    #[inline(always)]
+    pub const fn as_ptr(&self) -> *mut () {
+        self.ptr as _
+    }
+    #[doc = "Force block out of reset (i.e. power it on)"]
+    #[inline(always)]
+    pub const fn frce_on(self) -> crate::common::Reg<regs::FrceOn, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(0usize) as _) }
+    }
+    #[doc = "Force into reset (i.e. power it off)"]
+    #[inline(always)]
+    pub const fn frce_off(self) -> crate::common::Reg<regs::FrceOff, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(4usize) as _) }
+    }
+    #[doc = "Set to 1 if the watchdog should reset this"]
+    #[inline(always)]
+    pub const fn wdsel(self) -> crate::common::Reg<regs::Wdsel, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(8usize) as _) }
+    }
+    #[doc = "Is the subsystem ready?"]
+    #[inline(always)]
+    pub const fn done(self) -> crate::common::Reg<regs::Done, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(12usize) as _) }
+    }
+}
+pub mod regs;
diff --git a/src/rp2350/psm/regs.rs b/src/rp2350/psm/regs.rs
new file mode 100644
index 00000000..8c862ee6
--- /dev/null
+++ b/src/rp2350/psm/regs.rs
@@ -0,0 +1,948 @@
+#[doc = "Is the subsystem ready?"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Done(pub u32);
+impl Done {
+    #[inline(always)]
+    pub const fn proc_cold(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_proc_cold(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[inline(always)]
+    pub const fn otp(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_otp(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+    #[inline(always)]
+    pub const fn rosc(&self) -> bool {
+        let val = (self.0 >> 2usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_rosc(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+    }
+    #[inline(always)]
+    pub const fn xosc(&self) -> bool {
+        let val = (self.0 >> 3usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_xosc(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
+    }
+    #[inline(always)]
+    pub const fn resets(&self) -> bool {
+        let val = (self.0 >> 4usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_resets(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
+    }
+    #[inline(always)]
+    pub const fn clocks(&self) -> bool {
+        let val = (self.0 >> 5usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_clocks(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
+    }
+    #[inline(always)]
+    pub const fn psm_ready(&self) -> bool {
+        let val = (self.0 >> 6usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_psm_ready(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
+    }
+    #[inline(always)]
+    pub const fn busfabric(&self) -> bool {
+        let val = (self.0 >> 7usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_busfabric(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
+    }
+    #[inline(always)]
+    pub const fn rom(&self) -> bool {
+        let val = (self.0 >> 8usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_rom(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
+    }
+    #[inline(always)]
+    pub const fn bootram(&self) -> bool {
+        let val = (self.0 >> 9usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_bootram(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
+    }
+    #[inline(always)]
+    pub const fn sram0(&self) -> bool {
+        let val = (self.0 >> 10usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_sram0(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize);
+    }
+    #[inline(always)]
+    pub const fn sram1(&self) -> bool {
+        let val = (self.0 >> 11usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_sram1(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
+    }
+    #[inline(always)]
+    pub const fn sram2(&self) -> bool {
+        let val = (self.0 >> 12usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_sram2(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
+    }
+    #[inline(always)]
+    pub const fn sram3(&self) -> bool {
+        let val = (self.0 >> 13usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_sram3(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize);
+    }
+    #[inline(always)]
+    pub const fn sram4(&self) -> bool {
+        let val = (self.0 >> 14usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_sram4(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize);
+    }
+    #[inline(always)]
+    pub const fn sram5(&self) -> bool {
+        let val = (self.0 >> 15usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_sram5(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize);
+    }
+    #[inline(always)]
+    pub const fn sram6(&self) -> bool {
+        let val = (self.0 >> 16usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_sram6(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
+    }
+    #[inline(always)]
+    pub const fn sram7(&self) -> bool {
+        let val = (self.0 >> 17usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_sram7(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
+    }
+    #[inline(always)]
+    pub const fn sram8(&self) -> bool {
+        let val = (self.0 >> 18usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_sram8(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize);
+    }
+    #[inline(always)]
+    pub const fn sram9(&self) -> bool {
+        let val = (self.0 >> 19usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_sram9(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize);
+    }
+    #[inline(always)]
+    pub const fn xip(&self) -> bool {
+        let val = (self.0 >> 20usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_xip(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize);
+    }
+    #[inline(always)]
+    pub const fn sio(&self) -> bool {
+        let val = (self.0 >> 21usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_sio(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 21usize)) | (((val as u32) & 0x01) << 21usize);
+    }
+    #[inline(always)]
+    pub const fn accessctrl(&self) -> bool {
+        let val = (self.0 >> 22usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_accessctrl(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 22usize)) | (((val as u32) & 0x01) << 22usize);
+    }
+    #[inline(always)]
+    pub const fn proc0(&self) -> bool {
+        let val = (self.0 >> 23usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_proc0(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 23usize)) | (((val as u32) & 0x01) << 23usize);
+    }
+    #[inline(always)]
+    pub const fn proc1(&self) -> bool {
+        let val = (self.0 >> 24usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_proc1(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 24usize)) | (((val as u32) & 0x01) << 24usize);
+    }
+}
+impl Default for Done {
+    #[inline(always)]
+    fn default() -> Done {
+        Done(0)
+    }
+}
+#[doc = "Force into reset (i.e. power it off)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct FrceOff(pub u32);
+impl FrceOff {
+    #[inline(always)]
+    pub const fn proc_cold(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_proc_cold(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[inline(always)]
+    pub const fn otp(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_otp(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+    #[inline(always)]
+    pub const fn rosc(&self) -> bool {
+        let val = (self.0 >> 2usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_rosc(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+    }
+    #[inline(always)]
+    pub const fn xosc(&self) -> bool {
+        let val = (self.0 >> 3usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_xosc(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
+    }
+    #[inline(always)]
+    pub const fn resets(&self) -> bool {
+        let val = (self.0 >> 4usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_resets(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
+    }
+    #[inline(always)]
+    pub const fn clocks(&self) -> bool {
+        let val = (self.0 >> 5usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_clocks(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
+    }
+    #[inline(always)]
+    pub const fn psm_ready(&self) -> bool {
+        let val = (self.0 >> 6usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_psm_ready(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
+    }
+    #[inline(always)]
+    pub const fn busfabric(&self) -> bool {
+        let val = (self.0 >> 7usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_busfabric(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
+    }
+    #[inline(always)]
+    pub const fn rom(&self) -> bool {
+        let val = (self.0 >> 8usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_rom(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
+    }
+    #[inline(always)]
+    pub const fn bootram(&self) -> bool {
+        let val = (self.0 >> 9usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_bootram(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
+    }
+    #[inline(always)]
+    pub const fn sram0(&self) -> bool {
+        let val = (self.0 >> 10usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_sram0(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize);
+    }
+    #[inline(always)]
+    pub const fn sram1(&self) -> bool {
+        let val = (self.0 >> 11usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_sram1(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
+    }
+    #[inline(always)]
+    pub const fn sram2(&self) -> bool {
+        let val = (self.0 >> 12usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_sram2(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
+    }
+    #[inline(always)]
+    pub const fn sram3(&self) -> bool {
+        let val = (self.0 >> 13usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_sram3(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize);
+    }
+    #[inline(always)]
+    pub const fn sram4(&self) -> bool {
+        let val = (self.0 >> 14usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_sram4(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize);
+    }
+    #[inline(always)]
+    pub const fn sram5(&self) -> bool {
+        let val = (self.0 >> 15usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_sram5(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize);
+    }
+    #[inline(always)]
+    pub const fn sram6(&self) -> bool {
+        let val = (self.0 >> 16usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_sram6(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
+    }
+    #[inline(always)]
+    pub const fn sram7(&self) -> bool {
+        let val = (self.0 >> 17usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_sram7(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
+    }
+    #[inline(always)]
+    pub const fn sram8(&self) -> bool {
+        let val = (self.0 >> 18usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_sram8(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize);
+    }
+    #[inline(always)]
+    pub const fn sram9(&self) -> bool {
+        let val = (self.0 >> 19usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_sram9(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize);
+    }
+    #[inline(always)]
+    pub const fn xip(&self) -> bool {
+        let val = (self.0 >> 20usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_xip(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize);
+    }
+    #[inline(always)]
+    pub const fn sio(&self) -> bool {
+        let val = (self.0 >> 21usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_sio(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 21usize)) | (((val as u32) & 0x01) << 21usize);
+    }
+    #[inline(always)]
+    pub const fn accessctrl(&self) -> bool {
+        let val = (self.0 >> 22usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_accessctrl(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 22usize)) | (((val as u32) & 0x01) << 22usize);
+    }
+    #[inline(always)]
+    pub const fn proc0(&self) -> bool {
+        let val = (self.0 >> 23usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_proc0(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 23usize)) | (((val as u32) & 0x01) << 23usize);
+    }
+    #[inline(always)]
+    pub const fn proc1(&self) -> bool {
+        let val = (self.0 >> 24usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_proc1(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 24usize)) | (((val as u32) & 0x01) << 24usize);
+    }
+}
+impl Default for FrceOff {
+    #[inline(always)]
+    fn default() -> FrceOff {
+        FrceOff(0)
+    }
+}
+#[doc = "Force block out of reset (i.e. power it on)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct FrceOn(pub u32);
+impl FrceOn {
+    #[inline(always)]
+    pub const fn proc_cold(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_proc_cold(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[inline(always)]
+    pub const fn otp(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_otp(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+    #[inline(always)]
+    pub const fn rosc(&self) -> bool {
+        let val = (self.0 >> 2usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_rosc(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+    }
+    #[inline(always)]
+    pub const fn xosc(&self) -> bool {
+        let val = (self.0 >> 3usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_xosc(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
+    }
+    #[inline(always)]
+    pub const fn resets(&self) -> bool {
+        let val = (self.0 >> 4usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_resets(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
+    }
+    #[inline(always)]
+    pub const fn clocks(&self) -> bool {
+        let val = (self.0 >> 5usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_clocks(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
+    }
+    #[inline(always)]
+    pub const fn psm_ready(&self) -> bool {
+        let val = (self.0 >> 6usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_psm_ready(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
+    }
+    #[inline(always)]
+    pub const fn busfabric(&self) -> bool {
+        let val = (self.0 >> 7usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_busfabric(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
+    }
+    #[inline(always)]
+    pub const fn rom(&self) -> bool {
+        let val = (self.0 >> 8usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_rom(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
+    }
+    #[inline(always)]
+    pub const fn bootram(&self) -> bool {
+        let val = (self.0 >> 9usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_bootram(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
+    }
+    #[inline(always)]
+    pub const fn sram0(&self) -> bool {
+        let val = (self.0 >> 10usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_sram0(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize);
+    }
+    #[inline(always)]
+    pub const fn sram1(&self) -> bool {
+        let val = (self.0 >> 11usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_sram1(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
+    }
+    #[inline(always)]
+    pub const fn sram2(&self) -> bool {
+        let val = (self.0 >> 12usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_sram2(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
+    }
+    #[inline(always)]
+    pub const fn sram3(&self) -> bool {
+        let val = (self.0 >> 13usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_sram3(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize);
+    }
+    #[inline(always)]
+    pub const fn sram4(&self) -> bool {
+        let val = (self.0 >> 14usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_sram4(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize);
+    }
+    #[inline(always)]
+    pub const fn sram5(&self) -> bool {
+        let val = (self.0 >> 15usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_sram5(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize);
+    }
+    #[inline(always)]
+    pub const fn sram6(&self) -> bool {
+        let val = (self.0 >> 16usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_sram6(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
+    }
+    #[inline(always)]
+    pub const fn sram7(&self) -> bool {
+        let val = (self.0 >> 17usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_sram7(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
+    }
+    #[inline(always)]
+    pub const fn sram8(&self) -> bool {
+        let val = (self.0 >> 18usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_sram8(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize);
+    }
+    #[inline(always)]
+    pub const fn sram9(&self) -> bool {
+        let val = (self.0 >> 19usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_sram9(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize);
+    }
+    #[inline(always)]
+    pub const fn xip(&self) -> bool {
+        let val = (self.0 >> 20usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_xip(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize);
+    }
+    #[inline(always)]
+    pub const fn sio(&self) -> bool {
+        let val = (self.0 >> 21usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_sio(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 21usize)) | (((val as u32) & 0x01) << 21usize);
+    }
+    #[inline(always)]
+    pub const fn accessctrl(&self) -> bool {
+        let val = (self.0 >> 22usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_accessctrl(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 22usize)) | (((val as u32) & 0x01) << 22usize);
+    }
+    #[inline(always)]
+    pub const fn proc0(&self) -> bool {
+        let val = (self.0 >> 23usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_proc0(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 23usize)) | (((val as u32) & 0x01) << 23usize);
+    }
+    #[inline(always)]
+    pub const fn proc1(&self) -> bool {
+        let val = (self.0 >> 24usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_proc1(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 24usize)) | (((val as u32) & 0x01) << 24usize);
+    }
+}
+impl Default for FrceOn {
+    #[inline(always)]
+    fn default() -> FrceOn {
+        FrceOn(0)
+    }
+}
+#[doc = "Set to 1 if the watchdog should reset this"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Wdsel(pub u32);
+impl Wdsel {
+    #[inline(always)]
+    pub const fn proc_cold(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_proc_cold(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[inline(always)]
+    pub const fn otp(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_otp(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+    #[inline(always)]
+    pub const fn rosc(&self) -> bool {
+        let val = (self.0 >> 2usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_rosc(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+    }
+    #[inline(always)]
+    pub const fn xosc(&self) -> bool {
+        let val = (self.0 >> 3usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_xosc(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
+    }
+    #[inline(always)]
+    pub const fn resets(&self) -> bool {
+        let val = (self.0 >> 4usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_resets(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
+    }
+    #[inline(always)]
+    pub const fn clocks(&self) -> bool {
+        let val = (self.0 >> 5usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_clocks(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
+    }
+    #[inline(always)]
+    pub const fn psm_ready(&self) -> bool {
+        let val = (self.0 >> 6usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_psm_ready(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
+    }
+    #[inline(always)]
+    pub const fn busfabric(&self) -> bool {
+        let val = (self.0 >> 7usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_busfabric(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
+    }
+    #[inline(always)]
+    pub const fn rom(&self) -> bool {
+        let val = (self.0 >> 8usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_rom(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
+    }
+    #[inline(always)]
+    pub const fn bootram(&self) -> bool {
+        let val = (self.0 >> 9usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_bootram(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
+    }
+    #[inline(always)]
+    pub const fn sram0(&self) -> bool {
+        let val = (self.0 >> 10usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_sram0(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize);
+    }
+    #[inline(always)]
+    pub const fn sram1(&self) -> bool {
+        let val = (self.0 >> 11usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_sram1(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
+    }
+    #[inline(always)]
+    pub const fn sram2(&self) -> bool {
+        let val = (self.0 >> 12usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_sram2(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
+    }
+    #[inline(always)]
+    pub const fn sram3(&self) -> bool {
+        let val = (self.0 >> 13usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_sram3(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize);
+    }
+    #[inline(always)]
+    pub const fn sram4(&self) -> bool {
+        let val = (self.0 >> 14usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_sram4(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize);
+    }
+    #[inline(always)]
+    pub const fn sram5(&self) -> bool {
+        let val = (self.0 >> 15usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_sram5(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize);
+    }
+    #[inline(always)]
+    pub const fn sram6(&self) -> bool {
+        let val = (self.0 >> 16usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_sram6(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
+    }
+    #[inline(always)]
+    pub const fn sram7(&self) -> bool {
+        let val = (self.0 >> 17usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_sram7(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
+    }
+    #[inline(always)]
+    pub const fn sram8(&self) -> bool {
+        let val = (self.0 >> 18usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_sram8(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize);
+    }
+    #[inline(always)]
+    pub const fn sram9(&self) -> bool {
+        let val = (self.0 >> 19usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_sram9(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize);
+    }
+    #[inline(always)]
+    pub const fn xip(&self) -> bool {
+        let val = (self.0 >> 20usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_xip(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize);
+    }
+    #[inline(always)]
+    pub const fn sio(&self) -> bool {
+        let val = (self.0 >> 21usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_sio(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 21usize)) | (((val as u32) & 0x01) << 21usize);
+    }
+    #[inline(always)]
+    pub const fn accessctrl(&self) -> bool {
+        let val = (self.0 >> 22usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_accessctrl(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 22usize)) | (((val as u32) & 0x01) << 22usize);
+    }
+    #[inline(always)]
+    pub const fn proc0(&self) -> bool {
+        let val = (self.0 >> 23usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_proc0(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 23usize)) | (((val as u32) & 0x01) << 23usize);
+    }
+    #[inline(always)]
+    pub const fn proc1(&self) -> bool {
+        let val = (self.0 >> 24usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_proc1(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 24usize)) | (((val as u32) & 0x01) << 24usize);
+    }
+}
+impl Default for Wdsel {
+    #[inline(always)]
+    fn default() -> Wdsel {
+        Wdsel(0)
+    }
+}
diff --git a/src/rp2350/pwm.rs b/src/rp2350/pwm.rs
new file mode 100644
index 00000000..12164a7d
--- /dev/null
+++ b/src/rp2350/pwm.rs
@@ -0,0 +1,105 @@
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Channel {
+    ptr: *mut u8,
+}
+unsafe impl Send for Channel {}
+unsafe impl Sync for Channel {}
+impl Channel {
+    #[inline(always)]
+    pub const unsafe fn from_ptr(ptr: *mut ()) -> Self {
+        Self { ptr: ptr as _ }
+    }
+    #[inline(always)]
+    pub const fn as_ptr(&self) -> *mut () {
+        self.ptr as _
+    }
+    #[doc = "Control and status register"]
+    #[inline(always)]
+    pub const fn csr(self) -> crate::common::Reg<regs::ChCsr, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(0usize) as _) }
+    }
+    #[doc = "INT and FRAC form a fixed-point fractional number. Counting rate is system clock frequency divided by this number. Fractional division uses simple 1st-order sigma-delta."]
+    #[inline(always)]
+    pub const fn div(self) -> crate::common::Reg<regs::ChDiv, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(4usize) as _) }
+    }
+    #[doc = "Direct access to the PWM counter"]
+    #[inline(always)]
+    pub const fn ctr(self) -> crate::common::Reg<regs::ChCtr, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(8usize) as _) }
+    }
+    #[doc = "Counter compare values"]
+    #[inline(always)]
+    pub const fn cc(self) -> crate::common::Reg<regs::ChCc, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(12usize) as _) }
+    }
+    #[doc = "Counter wrap value"]
+    #[inline(always)]
+    pub const fn top(self) -> crate::common::Reg<regs::ChTop, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(16usize) as _) }
+    }
+}
+#[doc = "Simple PWM"]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Pwm {
+    ptr: *mut u8,
+}
+unsafe impl Send for Pwm {}
+unsafe impl Sync for Pwm {}
+impl Pwm {
+    #[inline(always)]
+    pub const unsafe fn from_ptr(ptr: *mut ()) -> Self {
+        Self { ptr: ptr as _ }
+    }
+    #[inline(always)]
+    pub const fn as_ptr(&self) -> *mut () {
+        self.ptr as _
+    }
+    #[inline(always)]
+    pub const fn ch(self, n: usize) -> Channel {
+        assert!(n < 12usize);
+        unsafe { Channel::from_ptr(self.ptr.add(0usize + n * 20usize) as _) }
+    }
+    #[doc = "This register aliases the CSR_EN bits for all channels. Writing to this register allows multiple channels to be enabled or disabled simultaneously, so they can run in perfect sync. For each channel, there is only one physical EN register bit, which can be accessed through here or CHx_CSR."]
+    #[inline(always)]
+    pub const fn en(self) -> crate::common::Reg<regs::En, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(240usize) as _) }
+    }
+    #[doc = "Raw Interrupts"]
+    #[inline(always)]
+    pub const fn intr(self) -> crate::common::Reg<regs::Intr, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(244usize) as _) }
+    }
+    #[doc = "Interrupt Enable for irq0"]
+    #[inline(always)]
+    pub const fn irq0_inte(self) -> crate::common::Reg<regs::Irq0inte, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(248usize) as _) }
+    }
+    #[doc = "Interrupt Force for irq0"]
+    #[inline(always)]
+    pub const fn irq0_intf(self) -> crate::common::Reg<regs::Irq0intf, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(252usize) as _) }
+    }
+    #[doc = "Interrupt status after masking & forcing for irq0"]
+    #[inline(always)]
+    pub const fn irq0_ints(self) -> crate::common::Reg<regs::Irq0ints, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(256usize) as _) }
+    }
+    #[doc = "Interrupt Enable for irq1"]
+    #[inline(always)]
+    pub const fn irq1_inte(self) -> crate::common::Reg<regs::Irq1inte, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(260usize) as _) }
+    }
+    #[doc = "Interrupt Force for irq1"]
+    #[inline(always)]
+    pub const fn irq1_intf(self) -> crate::common::Reg<regs::Irq1intf, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(264usize) as _) }
+    }
+    #[doc = "Interrupt status after masking & forcing for irq1"]
+    #[inline(always)]
+    pub const fn irq1_ints(self) -> crate::common::Reg<regs::Irq1ints, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(268usize) as _) }
+    }
+}
+pub mod regs;
+pub mod vals;
diff --git a/src/rp2350/pwm/regs.rs b/src/rp2350/pwm/regs.rs
new file mode 100644
index 00000000..3bcf2aa3
--- /dev/null
+++ b/src/rp2350/pwm/regs.rs
@@ -0,0 +1,1149 @@
+#[doc = "Counter compare values"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct ChCc(pub u32);
+impl ChCc {
+    #[inline(always)]
+    pub const fn a(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0xffff;
+        val as u16
+    }
+    #[inline(always)]
+    pub fn set_a(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+    }
+    #[inline(always)]
+    pub const fn b(&self) -> u16 {
+        let val = (self.0 >> 16usize) & 0xffff;
+        val as u16
+    }
+    #[inline(always)]
+    pub fn set_b(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 16usize)) | (((val as u32) & 0xffff) << 16usize);
+    }
+}
+impl Default for ChCc {
+    #[inline(always)]
+    fn default() -> ChCc {
+        ChCc(0)
+    }
+}
+#[doc = "Control and status register"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct ChCsr(pub u32);
+impl ChCsr {
+    #[doc = "Enable the PWM channel."]
+    #[inline(always)]
+    pub const fn en(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Enable the PWM channel."]
+    #[inline(always)]
+    pub fn set_en(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[doc = "1: Enable phase-correct modulation. 0: Trailing-edge"]
+    #[inline(always)]
+    pub const fn ph_correct(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[doc = "1: Enable phase-correct modulation. 0: Trailing-edge"]
+    #[inline(always)]
+    pub fn set_ph_correct(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+    #[doc = "Invert output A"]
+    #[inline(always)]
+    pub const fn a_inv(&self) -> bool {
+        let val = (self.0 >> 2usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Invert output A"]
+    #[inline(always)]
+    pub fn set_a_inv(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+    }
+    #[doc = "Invert output B"]
+    #[inline(always)]
+    pub const fn b_inv(&self) -> bool {
+        let val = (self.0 >> 3usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Invert output B"]
+    #[inline(always)]
+    pub fn set_b_inv(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
+    }
+    #[inline(always)]
+    pub const fn divmode(&self) -> super::vals::Divmode {
+        let val = (self.0 >> 4usize) & 0x03;
+        super::vals::Divmode::from_bits(val as u8)
+    }
+    #[inline(always)]
+    pub fn set_divmode(&mut self, val: super::vals::Divmode) {
+        self.0 = (self.0 & !(0x03 << 4usize)) | (((val.to_bits() as u32) & 0x03) << 4usize);
+    }
+    #[doc = "Retard the phase of the counter by 1 count, while it is running. Self-clearing. Write a 1, and poll until low. Counter must be running."]
+    #[inline(always)]
+    pub const fn ph_ret(&self) -> bool {
+        let val = (self.0 >> 6usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Retard the phase of the counter by 1 count, while it is running. Self-clearing. Write a 1, and poll until low. Counter must be running."]
+    #[inline(always)]
+    pub fn set_ph_ret(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
+    }
+    #[doc = "Advance the phase of the counter by 1 count, while it is running. Self-clearing. Write a 1, and poll until low. Counter must be running at less than full speed (div_int + div_frac / 16 > 1)"]
+    #[inline(always)]
+    pub const fn ph_adv(&self) -> bool {
+        let val = (self.0 >> 7usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Advance the phase of the counter by 1 count, while it is running. Self-clearing. Write a 1, and poll until low. Counter must be running at less than full speed (div_int + div_frac / 16 > 1)"]
+    #[inline(always)]
+    pub fn set_ph_adv(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
+    }
+}
+impl Default for ChCsr {
+    #[inline(always)]
+    fn default() -> ChCsr {
+        ChCsr(0)
+    }
+}
+#[doc = "Direct access to the PWM counter"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct ChCtr(pub u32);
+impl ChCtr {
+    #[inline(always)]
+    pub const fn ctr(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0xffff;
+        val as u16
+    }
+    #[inline(always)]
+    pub fn set_ctr(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+    }
+}
+impl Default for ChCtr {
+    #[inline(always)]
+    fn default() -> ChCtr {
+        ChCtr(0)
+    }
+}
+#[doc = "INT and FRAC form a fixed-point fractional number. Counting rate is system clock frequency divided by this number. Fractional division uses simple 1st-order sigma-delta."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct ChDiv(pub u32);
+impl ChDiv {
+    #[inline(always)]
+    pub const fn frac(&self) -> u8 {
+        let val = (self.0 >> 0usize) & 0x0f;
+        val as u8
+    }
+    #[inline(always)]
+    pub fn set_frac(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize);
+    }
+    #[inline(always)]
+    pub const fn int(&self) -> u8 {
+        let val = (self.0 >> 4usize) & 0xff;
+        val as u8
+    }
+    #[inline(always)]
+    pub fn set_int(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 4usize)) | (((val as u32) & 0xff) << 4usize);
+    }
+}
+impl Default for ChDiv {
+    #[inline(always)]
+    fn default() -> ChDiv {
+        ChDiv(0)
+    }
+}
+#[doc = "Counter wrap value"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct ChTop(pub u32);
+impl ChTop {
+    #[inline(always)]
+    pub const fn top(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0xffff;
+        val as u16
+    }
+    #[inline(always)]
+    pub fn set_top(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+    }
+}
+impl Default for ChTop {
+    #[inline(always)]
+    fn default() -> ChTop {
+        ChTop(0)
+    }
+}
+#[doc = "This register aliases the CSR_EN bits for all channels. Writing to this register allows multiple channels to be enabled or disabled simultaneously, so they can run in perfect sync. For each channel, there is only one physical EN register bit, which can be accessed through here or CHx_CSR."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct En(pub u32);
+impl En {
+    #[inline(always)]
+    pub const fn ch0(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_ch0(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[inline(always)]
+    pub const fn ch1(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_ch1(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+    #[inline(always)]
+    pub const fn ch2(&self) -> bool {
+        let val = (self.0 >> 2usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_ch2(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+    }
+    #[inline(always)]
+    pub const fn ch3(&self) -> bool {
+        let val = (self.0 >> 3usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_ch3(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
+    }
+    #[inline(always)]
+    pub const fn ch4(&self) -> bool {
+        let val = (self.0 >> 4usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_ch4(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
+    }
+    #[inline(always)]
+    pub const fn ch5(&self) -> bool {
+        let val = (self.0 >> 5usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_ch5(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
+    }
+    #[inline(always)]
+    pub const fn ch6(&self) -> bool {
+        let val = (self.0 >> 6usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_ch6(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
+    }
+    #[inline(always)]
+    pub const fn ch7(&self) -> bool {
+        let val = (self.0 >> 7usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_ch7(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
+    }
+    #[inline(always)]
+    pub const fn ch8(&self) -> bool {
+        let val = (self.0 >> 8usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_ch8(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
+    }
+    #[inline(always)]
+    pub const fn ch9(&self) -> bool {
+        let val = (self.0 >> 9usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_ch9(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
+    }
+    #[inline(always)]
+    pub const fn ch10(&self) -> bool {
+        let val = (self.0 >> 10usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_ch10(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize);
+    }
+    #[inline(always)]
+    pub const fn ch11(&self) -> bool {
+        let val = (self.0 >> 11usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_ch11(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
+    }
+}
+impl Default for En {
+    #[inline(always)]
+    fn default() -> En {
+        En(0)
+    }
+}
+#[doc = "Raw Interrupts"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Intr(pub u32);
+impl Intr {
+    #[inline(always)]
+    pub const fn ch0(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_ch0(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[inline(always)]
+    pub const fn ch1(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_ch1(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+    #[inline(always)]
+    pub const fn ch2(&self) -> bool {
+        let val = (self.0 >> 2usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_ch2(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+    }
+    #[inline(always)]
+    pub const fn ch3(&self) -> bool {
+        let val = (self.0 >> 3usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_ch3(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
+    }
+    #[inline(always)]
+    pub const fn ch4(&self) -> bool {
+        let val = (self.0 >> 4usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_ch4(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
+    }
+    #[inline(always)]
+    pub const fn ch5(&self) -> bool {
+        let val = (self.0 >> 5usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_ch5(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
+    }
+    #[inline(always)]
+    pub const fn ch6(&self) -> bool {
+        let val = (self.0 >> 6usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_ch6(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
+    }
+    #[inline(always)]
+    pub const fn ch7(&self) -> bool {
+        let val = (self.0 >> 7usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_ch7(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
+    }
+    #[inline(always)]
+    pub const fn ch8(&self) -> bool {
+        let val = (self.0 >> 8usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_ch8(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
+    }
+    #[inline(always)]
+    pub const fn ch9(&self) -> bool {
+        let val = (self.0 >> 9usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_ch9(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
+    }
+    #[inline(always)]
+    pub const fn ch10(&self) -> bool {
+        let val = (self.0 >> 10usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_ch10(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize);
+    }
+    #[inline(always)]
+    pub const fn ch11(&self) -> bool {
+        let val = (self.0 >> 11usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_ch11(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
+    }
+}
+impl Default for Intr {
+    #[inline(always)]
+    fn default() -> Intr {
+        Intr(0)
+    }
+}
+#[doc = "Interrupt Enable for irq0"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Irq0inte(pub u32);
+impl Irq0inte {
+    #[inline(always)]
+    pub const fn ch0(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_ch0(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[inline(always)]
+    pub const fn ch1(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_ch1(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+    #[inline(always)]
+    pub const fn ch2(&self) -> bool {
+        let val = (self.0 >> 2usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_ch2(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+    }
+    #[inline(always)]
+    pub const fn ch3(&self) -> bool {
+        let val = (self.0 >> 3usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_ch3(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
+    }
+    #[inline(always)]
+    pub const fn ch4(&self) -> bool {
+        let val = (self.0 >> 4usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_ch4(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
+    }
+    #[inline(always)]
+    pub const fn ch5(&self) -> bool {
+        let val = (self.0 >> 5usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_ch5(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
+    }
+    #[inline(always)]
+    pub const fn ch6(&self) -> bool {
+        let val = (self.0 >> 6usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_ch6(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
+    }
+    #[inline(always)]
+    pub const fn ch7(&self) -> bool {
+        let val = (self.0 >> 7usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_ch7(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
+    }
+    #[inline(always)]
+    pub const fn ch8(&self) -> bool {
+        let val = (self.0 >> 8usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_ch8(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
+    }
+    #[inline(always)]
+    pub const fn ch9(&self) -> bool {
+        let val = (self.0 >> 9usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_ch9(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
+    }
+    #[inline(always)]
+    pub const fn ch10(&self) -> bool {
+        let val = (self.0 >> 10usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_ch10(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize);
+    }
+    #[inline(always)]
+    pub const fn ch11(&self) -> bool {
+        let val = (self.0 >> 11usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_ch11(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
+    }
+}
+impl Default for Irq0inte {
+    #[inline(always)]
+    fn default() -> Irq0inte {
+        Irq0inte(0)
+    }
+}
+#[doc = "Interrupt Force for irq0"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Irq0intf(pub u32);
+impl Irq0intf {
+    #[inline(always)]
+    pub const fn ch0(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_ch0(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[inline(always)]
+    pub const fn ch1(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_ch1(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+    #[inline(always)]
+    pub const fn ch2(&self) -> bool {
+        let val = (self.0 >> 2usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_ch2(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+    }
+    #[inline(always)]
+    pub const fn ch3(&self) -> bool {
+        let val = (self.0 >> 3usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_ch3(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
+    }
+    #[inline(always)]
+    pub const fn ch4(&self) -> bool {
+        let val = (self.0 >> 4usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_ch4(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
+    }
+    #[inline(always)]
+    pub const fn ch5(&self) -> bool {
+        let val = (self.0 >> 5usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_ch5(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
+    }
+    #[inline(always)]
+    pub const fn ch6(&self) -> bool {
+        let val = (self.0 >> 6usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_ch6(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
+    }
+    #[inline(always)]
+    pub const fn ch7(&self) -> bool {
+        let val = (self.0 >> 7usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_ch7(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
+    }
+    #[inline(always)]
+    pub const fn ch8(&self) -> bool {
+        let val = (self.0 >> 8usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_ch8(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
+    }
+    #[inline(always)]
+    pub const fn ch9(&self) -> bool {
+        let val = (self.0 >> 9usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_ch9(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
+    }
+    #[inline(always)]
+    pub const fn ch10(&self) -> bool {
+        let val = (self.0 >> 10usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_ch10(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize);
+    }
+    #[inline(always)]
+    pub const fn ch11(&self) -> bool {
+        let val = (self.0 >> 11usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_ch11(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
+    }
+}
+impl Default for Irq0intf {
+    #[inline(always)]
+    fn default() -> Irq0intf {
+        Irq0intf(0)
+    }
+}
+#[doc = "Interrupt status after masking & forcing for irq0"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Irq0ints(pub u32);
+impl Irq0ints {
+    #[inline(always)]
+    pub const fn ch0(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_ch0(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[inline(always)]
+    pub const fn ch1(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_ch1(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+    #[inline(always)]
+    pub const fn ch2(&self) -> bool {
+        let val = (self.0 >> 2usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_ch2(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+    }
+    #[inline(always)]
+    pub const fn ch3(&self) -> bool {
+        let val = (self.0 >> 3usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_ch3(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
+    }
+    #[inline(always)]
+    pub const fn ch4(&self) -> bool {
+        let val = (self.0 >> 4usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_ch4(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
+    }
+    #[inline(always)]
+    pub const fn ch5(&self) -> bool {
+        let val = (self.0 >> 5usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_ch5(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
+    }
+    #[inline(always)]
+    pub const fn ch6(&self) -> bool {
+        let val = (self.0 >> 6usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_ch6(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
+    }
+    #[inline(always)]
+    pub const fn ch7(&self) -> bool {
+        let val = (self.0 >> 7usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_ch7(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
+    }
+    #[inline(always)]
+    pub const fn ch8(&self) -> bool {
+        let val = (self.0 >> 8usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_ch8(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
+    }
+    #[inline(always)]
+    pub const fn ch9(&self) -> bool {
+        let val = (self.0 >> 9usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_ch9(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
+    }
+    #[inline(always)]
+    pub const fn ch10(&self) -> bool {
+        let val = (self.0 >> 10usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_ch10(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize);
+    }
+    #[inline(always)]
+    pub const fn ch11(&self) -> bool {
+        let val = (self.0 >> 11usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_ch11(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
+    }
+}
+impl Default for Irq0ints {
+    #[inline(always)]
+    fn default() -> Irq0ints {
+        Irq0ints(0)
+    }
+}
+#[doc = "Interrupt Enable for irq1"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Irq1inte(pub u32);
+impl Irq1inte {
+    #[inline(always)]
+    pub const fn ch0(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_ch0(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[inline(always)]
+    pub const fn ch1(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_ch1(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+    #[inline(always)]
+    pub const fn ch2(&self) -> bool {
+        let val = (self.0 >> 2usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_ch2(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+    }
+    #[inline(always)]
+    pub const fn ch3(&self) -> bool {
+        let val = (self.0 >> 3usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_ch3(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
+    }
+    #[inline(always)]
+    pub const fn ch4(&self) -> bool {
+        let val = (self.0 >> 4usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_ch4(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
+    }
+    #[inline(always)]
+    pub const fn ch5(&self) -> bool {
+        let val = (self.0 >> 5usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_ch5(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
+    }
+    #[inline(always)]
+    pub const fn ch6(&self) -> bool {
+        let val = (self.0 >> 6usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_ch6(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
+    }
+    #[inline(always)]
+    pub const fn ch7(&self) -> bool {
+        let val = (self.0 >> 7usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_ch7(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
+    }
+    #[inline(always)]
+    pub const fn ch8(&self) -> bool {
+        let val = (self.0 >> 8usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_ch8(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
+    }
+    #[inline(always)]
+    pub const fn ch9(&self) -> bool {
+        let val = (self.0 >> 9usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_ch9(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
+    }
+    #[inline(always)]
+    pub const fn ch10(&self) -> bool {
+        let val = (self.0 >> 10usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_ch10(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize);
+    }
+    #[inline(always)]
+    pub const fn ch11(&self) -> bool {
+        let val = (self.0 >> 11usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_ch11(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
+    }
+}
+impl Default for Irq1inte {
+    #[inline(always)]
+    fn default() -> Irq1inte {
+        Irq1inte(0)
+    }
+}
+#[doc = "Interrupt Force for irq1"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Irq1intf(pub u32);
+impl Irq1intf {
+    #[inline(always)]
+    pub const fn ch0(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_ch0(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[inline(always)]
+    pub const fn ch1(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_ch1(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+    #[inline(always)]
+    pub const fn ch2(&self) -> bool {
+        let val = (self.0 >> 2usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_ch2(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+    }
+    #[inline(always)]
+    pub const fn ch3(&self) -> bool {
+        let val = (self.0 >> 3usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_ch3(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
+    }
+    #[inline(always)]
+    pub const fn ch4(&self) -> bool {
+        let val = (self.0 >> 4usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_ch4(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
+    }
+    #[inline(always)]
+    pub const fn ch5(&self) -> bool {
+        let val = (self.0 >> 5usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_ch5(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
+    }
+    #[inline(always)]
+    pub const fn ch6(&self) -> bool {
+        let val = (self.0 >> 6usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_ch6(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
+    }
+    #[inline(always)]
+    pub const fn ch7(&self) -> bool {
+        let val = (self.0 >> 7usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_ch7(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
+    }
+    #[inline(always)]
+    pub const fn ch8(&self) -> bool {
+        let val = (self.0 >> 8usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_ch8(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
+    }
+    #[inline(always)]
+    pub const fn ch9(&self) -> bool {
+        let val = (self.0 >> 9usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_ch9(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
+    }
+    #[inline(always)]
+    pub const fn ch10(&self) -> bool {
+        let val = (self.0 >> 10usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_ch10(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize);
+    }
+    #[inline(always)]
+    pub const fn ch11(&self) -> bool {
+        let val = (self.0 >> 11usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_ch11(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
+    }
+}
+impl Default for Irq1intf {
+    #[inline(always)]
+    fn default() -> Irq1intf {
+        Irq1intf(0)
+    }
+}
+#[doc = "Interrupt status after masking & forcing for irq1"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Irq1ints(pub u32);
+impl Irq1ints {
+    #[inline(always)]
+    pub const fn ch0(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_ch0(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[inline(always)]
+    pub const fn ch1(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_ch1(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+    #[inline(always)]
+    pub const fn ch2(&self) -> bool {
+        let val = (self.0 >> 2usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_ch2(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+    }
+    #[inline(always)]
+    pub const fn ch3(&self) -> bool {
+        let val = (self.0 >> 3usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_ch3(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
+    }
+    #[inline(always)]
+    pub const fn ch4(&self) -> bool {
+        let val = (self.0 >> 4usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_ch4(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
+    }
+    #[inline(always)]
+    pub const fn ch5(&self) -> bool {
+        let val = (self.0 >> 5usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_ch5(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
+    }
+    #[inline(always)]
+    pub const fn ch6(&self) -> bool {
+        let val = (self.0 >> 6usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_ch6(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
+    }
+    #[inline(always)]
+    pub const fn ch7(&self) -> bool {
+        let val = (self.0 >> 7usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_ch7(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
+    }
+    #[inline(always)]
+    pub const fn ch8(&self) -> bool {
+        let val = (self.0 >> 8usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_ch8(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
+    }
+    #[inline(always)]
+    pub const fn ch9(&self) -> bool {
+        let val = (self.0 >> 9usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_ch9(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
+    }
+    #[inline(always)]
+    pub const fn ch10(&self) -> bool {
+        let val = (self.0 >> 10usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_ch10(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize);
+    }
+    #[inline(always)]
+    pub const fn ch11(&self) -> bool {
+        let val = (self.0 >> 11usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_ch11(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
+    }
+}
+impl Default for Irq1ints {
+    #[inline(always)]
+    fn default() -> Irq1ints {
+        Irq1ints(0)
+    }
+}
diff --git a/src/rp2350/pwm/vals.rs b/src/rp2350/pwm/vals.rs
new file mode 100644
index 00000000..cd8bad90
--- /dev/null
+++ b/src/rp2350/pwm/vals.rs
@@ -0,0 +1,102 @@
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Ch10csrDivmode {
+    #[doc = "Free-running counting at rate dictated by fractional divider"]
+    DIV = 0,
+    #[doc = "Fractional divider operation is gated by the PWM B pin."]
+    LEVEL = 0x01,
+    #[doc = "Counter advances with each rising edge of the PWM B pin."]
+    RISE = 0x02,
+    #[doc = "Counter advances with each falling edge of the PWM B pin."]
+    FALL = 0x03,
+}
+impl Ch10csrDivmode {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Ch10csrDivmode {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Ch10csrDivmode {
+    #[inline(always)]
+    fn from(val: u8) -> Ch10csrDivmode {
+        Ch10csrDivmode::from_bits(val)
+    }
+}
+impl From<Ch10csrDivmode> for u8 {
+    #[inline(always)]
+    fn from(val: Ch10csrDivmode) -> u8 {
+        Ch10csrDivmode::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Ch11csrDivmode {
+    #[doc = "Free-running counting at rate dictated by fractional divider"]
+    DIV = 0,
+    #[doc = "Fractional divider operation is gated by the PWM B pin."]
+    LEVEL = 0x01,
+    #[doc = "Counter advances with each rising edge of the PWM B pin."]
+    RISE = 0x02,
+    #[doc = "Counter advances with each falling edge of the PWM B pin."]
+    FALL = 0x03,
+}
+impl Ch11csrDivmode {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Ch11csrDivmode {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Ch11csrDivmode {
+    #[inline(always)]
+    fn from(val: u8) -> Ch11csrDivmode {
+        Ch11csrDivmode::from_bits(val)
+    }
+}
+impl From<Ch11csrDivmode> for u8 {
+    #[inline(always)]
+    fn from(val: Ch11csrDivmode) -> u8 {
+        Ch11csrDivmode::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Divmode {
+    #[doc = "Free-running counting at rate dictated by fractional divider"]
+    DIV = 0,
+    #[doc = "Fractional divider operation is gated by the PWM B pin."]
+    LEVEL = 0x01,
+    #[doc = "Counter advances with each rising edge of the PWM B pin."]
+    RISE = 0x02,
+    #[doc = "Counter advances with each falling edge of the PWM B pin."]
+    FALL = 0x03,
+}
+impl Divmode {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Divmode {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Divmode {
+    #[inline(always)]
+    fn from(val: u8) -> Divmode {
+        Divmode::from_bits(val)
+    }
+}
+impl From<Divmode> for u8 {
+    #[inline(always)]
+    fn from(val: Divmode) -> u8 {
+        Divmode::to_bits(val)
+    }
+}
diff --git a/src/rp2350/qmi.rs b/src/rp2350/qmi.rs
new file mode 100644
index 00000000..c1730113
--- /dev/null
+++ b/src/rp2350/qmi.rs
@@ -0,0 +1,124 @@
+#[doc = "QSPI Memory Interface. Provides a memory-mapped interface to up to two SPI/DSPI/QSPI flash or PSRAM devices. Also provides a serial interface for programming and configuration of the external device."]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Qmi {
+    ptr: *mut u8,
+}
+unsafe impl Send for Qmi {}
+unsafe impl Sync for Qmi {}
+impl Qmi {
+    #[inline(always)]
+    pub const unsafe fn from_ptr(ptr: *mut ()) -> Self {
+        Self { ptr: ptr as _ }
+    }
+    #[inline(always)]
+    pub const fn as_ptr(&self) -> *mut () {
+        self.ptr as _
+    }
+    #[doc = "Control and status for direct serial mode Direct serial mode allows the processor to send and receive raw serial frames, for programming, configuration and control of the external memory devices. Only SPI mode 0 (CPOL=0 CPHA=0) is supported."]
+    #[inline(always)]
+    pub const fn direct_csr(self) -> crate::common::Reg<regs::DirectCsr, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(0usize) as _) }
+    }
+    #[doc = "Transmit FIFO for direct mode"]
+    #[inline(always)]
+    pub const fn direct_tx(self) -> crate::common::Reg<regs::DirectTx, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(4usize) as _) }
+    }
+    #[doc = "Receive FIFO for direct mode"]
+    #[inline(always)]
+    pub const fn direct_rx(self) -> crate::common::Reg<regs::DirectRx, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(8usize) as _) }
+    }
+    #[doc = "Timing configuration register for memory address window 0."]
+    #[inline(always)]
+    pub const fn m0_timing(self) -> crate::common::Reg<regs::M0timing, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(12usize) as _) }
+    }
+    #[doc = "Read transfer format configuration for memory address window 0. Configure the bus width of each transfer phase individually, and configure the length or presence of the command prefix, command suffix and dummy/turnaround transfer phases. Only 24-bit addresses are supported. The reset value of the M0_RFMT register is configured to support a basic 03h serial read transfer with no additional configuration."]
+    #[inline(always)]
+    pub const fn m0_rfmt(self) -> crate::common::Reg<regs::M0rfmt, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(16usize) as _) }
+    }
+    #[doc = "Command constants used for reads from memory address window 0. The reset value of the M0_RCMD register is configured to support a basic 03h serial read transfer with no additional configuration."]
+    #[inline(always)]
+    pub const fn m0_rcmd(self) -> crate::common::Reg<regs::M0rcmd, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(20usize) as _) }
+    }
+    #[doc = "Write transfer format configuration for memory address window 0. Configure the bus width of each transfer phase individually, and configure the length or presence of the command prefix, command suffix and dummy/turnaround transfer phases. Only 24-bit addresses are supported. The reset value of the M0_WFMT register is configured to support a basic 02h serial write transfer. However, writes to this window must first be enabled via the XIP_CTRL_WRITABLE_M0 bit, as XIP memory is read-only by default."]
+    #[inline(always)]
+    pub const fn m0_wfmt(self) -> crate::common::Reg<regs::M0wfmt, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(24usize) as _) }
+    }
+    #[doc = "Command constants used for writes to memory address window 0. The reset value of the M0_WCMD register is configured to support a basic 02h serial write transfer with no additional configuration."]
+    #[inline(always)]
+    pub const fn m0_wcmd(self) -> crate::common::Reg<regs::M0wcmd, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(28usize) as _) }
+    }
+    #[doc = "Timing configuration register for memory address window 1."]
+    #[inline(always)]
+    pub const fn m1_timing(self) -> crate::common::Reg<regs::M1timing, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(32usize) as _) }
+    }
+    #[doc = "Read transfer format configuration for memory address window 1. Configure the bus width of each transfer phase individually, and configure the length or presence of the command prefix, command suffix and dummy/turnaround transfer phases. Only 24-bit addresses are supported. The reset value of the M1_RFMT register is configured to support a basic 03h serial read transfer with no additional configuration."]
+    #[inline(always)]
+    pub const fn m1_rfmt(self) -> crate::common::Reg<regs::M1rfmt, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(36usize) as _) }
+    }
+    #[doc = "Command constants used for reads from memory address window 1. The reset value of the M1_RCMD register is configured to support a basic 03h serial read transfer with no additional configuration."]
+    #[inline(always)]
+    pub const fn m1_rcmd(self) -> crate::common::Reg<regs::M1rcmd, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(40usize) as _) }
+    }
+    #[doc = "Write transfer format configuration for memory address window 1. Configure the bus width of each transfer phase individually, and configure the length or presence of the command prefix, command suffix and dummy/turnaround transfer phases. Only 24-bit addresses are supported. The reset value of the M1_WFMT register is configured to support a basic 02h serial write transfer. However, writes to this window must first be enabled via the XIP_CTRL_WRITABLE_M1 bit, as XIP memory is read-only by default."]
+    #[inline(always)]
+    pub const fn m1_wfmt(self) -> crate::common::Reg<regs::M1wfmt, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(44usize) as _) }
+    }
+    #[doc = "Command constants used for writes to memory address window 1. The reset value of the M1_WCMD register is configured to support a basic 02h serial write transfer with no additional configuration."]
+    #[inline(always)]
+    pub const fn m1_wcmd(self) -> crate::common::Reg<regs::M1wcmd, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(48usize) as _) }
+    }
+    #[doc = "Configure address translation for XIP virtual addresses 0x000000 through 0x3fffff (a 4 MiB window starting at +0 MiB). Address translation allows a program image to be executed in place at multiple physical flash addresses (for example, a double-buffered flash image for over-the-air updates), without the overhead of position-independent code. At reset, the address translation registers are initialised to an identity mapping, so that they can be ignored if address translation is not required. Note that the XIP cache is fully virtually addressed, so a cache flush is required after changing the address translation."]
+    #[inline(always)]
+    pub const fn atrans0(self) -> crate::common::Reg<regs::Atrans0, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(52usize) as _) }
+    }
+    #[doc = "Configure address translation for XIP virtual addresses 0x400000 through 0x7fffff (a 4 MiB window starting at +4 MiB). Address translation allows a program image to be executed in place at multiple physical flash addresses (for example, a double-buffered flash image for over-the-air updates), without the overhead of position-independent code. At reset, the address translation registers are initialised to an identity mapping, so that they can be ignored if address translation is not required. Note that the XIP cache is fully virtually addressed, so a cache flush is required after changing the address translation."]
+    #[inline(always)]
+    pub const fn atrans1(self) -> crate::common::Reg<regs::Atrans1, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(56usize) as _) }
+    }
+    #[doc = "Configure address translation for XIP virtual addresses 0x800000 through 0xbfffff (a 4 MiB window starting at +8 MiB). Address translation allows a program image to be executed in place at multiple physical flash addresses (for example, a double-buffered flash image for over-the-air updates), without the overhead of position-independent code. At reset, the address translation registers are initialised to an identity mapping, so that they can be ignored if address translation is not required. Note that the XIP cache is fully virtually addressed, so a cache flush is required after changing the address translation."]
+    #[inline(always)]
+    pub const fn atrans2(self) -> crate::common::Reg<regs::Atrans2, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(60usize) as _) }
+    }
+    #[doc = "Configure address translation for XIP virtual addresses 0xc00000 through 0xffffff (a 4 MiB window starting at +12 MiB). Address translation allows a program image to be executed in place at multiple physical flash addresses (for example, a double-buffered flash image for over-the-air updates), without the overhead of position-independent code. At reset, the address translation registers are initialised to an identity mapping, so that they can be ignored if address translation is not required. Note that the XIP cache is fully virtually addressed, so a cache flush is required after changing the address translation."]
+    #[inline(always)]
+    pub const fn atrans3(self) -> crate::common::Reg<regs::Atrans3, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(64usize) as _) }
+    }
+    #[doc = "Configure address translation for XIP virtual addresses 0x1000000 through 0x13fffff (a 4 MiB window starting at +16 MiB). Address translation allows a program image to be executed in place at multiple physical flash addresses (for example, a double-buffered flash image for over-the-air updates), without the overhead of position-independent code. At reset, the address translation registers are initialised to an identity mapping, so that they can be ignored if address translation is not required. Note that the XIP cache is fully virtually addressed, so a cache flush is required after changing the address translation."]
+    #[inline(always)]
+    pub const fn atrans4(self) -> crate::common::Reg<regs::Atrans4, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(68usize) as _) }
+    }
+    #[doc = "Configure address translation for XIP virtual addresses 0x1400000 through 0x17fffff (a 4 MiB window starting at +20 MiB). Address translation allows a program image to be executed in place at multiple physical flash addresses (for example, a double-buffered flash image for over-the-air updates), without the overhead of position-independent code. At reset, the address translation registers are initialised to an identity mapping, so that they can be ignored if address translation is not required. Note that the XIP cache is fully virtually addressed, so a cache flush is required after changing the address translation."]
+    #[inline(always)]
+    pub const fn atrans5(self) -> crate::common::Reg<regs::Atrans5, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(72usize) as _) }
+    }
+    #[doc = "Configure address translation for XIP virtual addresses 0x1800000 through 0x1bfffff (a 4 MiB window starting at +24 MiB). Address translation allows a program image to be executed in place at multiple physical flash addresses (for example, a double-buffered flash image for over-the-air updates), without the overhead of position-independent code. At reset, the address translation registers are initialised to an identity mapping, so that they can be ignored if address translation is not required. Note that the XIP cache is fully virtually addressed, so a cache flush is required after changing the address translation."]
+    #[inline(always)]
+    pub const fn atrans6(self) -> crate::common::Reg<regs::Atrans6, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(76usize) as _) }
+    }
+    #[doc = "Configure address translation for XIP virtual addresses 0x1c00000 through 0x1ffffff (a 4 MiB window starting at +28 MiB). Address translation allows a program image to be executed in place at multiple physical flash addresses (for example, a double-buffered flash image for over-the-air updates), without the overhead of position-independent code. At reset, the address translation registers are initialised to an identity mapping, so that they can be ignored if address translation is not required. Note that the XIP cache is fully virtually addressed, so a cache flush is required after changing the address translation."]
+    #[inline(always)]
+    pub const fn atrans7(self) -> crate::common::Reg<regs::Atrans7, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(80usize) as _) }
+    }
+}
+pub mod regs;
+pub mod vals;
diff --git a/src/rp2350/qmi/regs.rs b/src/rp2350/qmi/regs.rs
new file mode 100644
index 00000000..db508fe6
--- /dev/null
+++ b/src/rp2350/qmi/regs.rs
@@ -0,0 +1,1308 @@
+#[doc = "Configure address translation for XIP virtual addresses 0x000000 through 0x3fffff (a 4 MiB window starting at +0 MiB). Address translation allows a program image to be executed in place at multiple physical flash addresses (for example, a double-buffered flash image for over-the-air updates), without the overhead of position-independent code. At reset, the address translation registers are initialised to an identity mapping, so that they can be ignored if address translation is not required. Note that the XIP cache is fully virtually addressed, so a cache flush is required after changing the address translation."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Atrans0(pub u32);
+impl Atrans0 {
+    #[doc = "Physical address base for this virtual address range, in units of 4 kiB (one flash sector). Taking a 24-bit virtual address, firstly bits 23:22 (the two MSBs) are masked to zero, and then BASE is added to bits 23:12 (the upper 12 bits) to form the physical address. Translation wraps on a 16 MiB boundary."]
+    #[inline(always)]
+    pub const fn base(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0x0fff;
+        val as u16
+    }
+    #[doc = "Physical address base for this virtual address range, in units of 4 kiB (one flash sector). Taking a 24-bit virtual address, firstly bits 23:22 (the two MSBs) are masked to zero, and then BASE is added to bits 23:12 (the upper 12 bits) to form the physical address. Translation wraps on a 16 MiB boundary."]
+    #[inline(always)]
+    pub fn set_base(&mut self, val: u16) {
+        self.0 = (self.0 & !(0x0fff << 0usize)) | (((val as u32) & 0x0fff) << 0usize);
+    }
+    #[doc = "Translation aperture size for this virtual address range, in units of 4 kiB (one flash sector). Bits 21:12 of the virtual address are compared to SIZE. Offsets greater than SIZE return a bus error, and do not cause a QSPI access."]
+    #[inline(always)]
+    pub const fn size(&self) -> u16 {
+        let val = (self.0 >> 16usize) & 0x07ff;
+        val as u16
+    }
+    #[doc = "Translation aperture size for this virtual address range, in units of 4 kiB (one flash sector). Bits 21:12 of the virtual address are compared to SIZE. Offsets greater than SIZE return a bus error, and do not cause a QSPI access."]
+    #[inline(always)]
+    pub fn set_size(&mut self, val: u16) {
+        self.0 = (self.0 & !(0x07ff << 16usize)) | (((val as u32) & 0x07ff) << 16usize);
+    }
+}
+impl Default for Atrans0 {
+    #[inline(always)]
+    fn default() -> Atrans0 {
+        Atrans0(0)
+    }
+}
+#[doc = "Configure address translation for XIP virtual addresses 0x400000 through 0x7fffff (a 4 MiB window starting at +4 MiB). Address translation allows a program image to be executed in place at multiple physical flash addresses (for example, a double-buffered flash image for over-the-air updates), without the overhead of position-independent code. At reset, the address translation registers are initialised to an identity mapping, so that they can be ignored if address translation is not required. Note that the XIP cache is fully virtually addressed, so a cache flush is required after changing the address translation."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Atrans1(pub u32);
+impl Atrans1 {
+    #[doc = "Physical address base for this virtual address range, in units of 4 kiB (one flash sector). Taking a 24-bit virtual address, firstly bits 23:22 (the two MSBs) are masked to zero, and then BASE is added to bits 23:12 (the upper 12 bits) to form the physical address. Translation wraps on a 16 MiB boundary."]
+    #[inline(always)]
+    pub const fn base(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0x0fff;
+        val as u16
+    }
+    #[doc = "Physical address base for this virtual address range, in units of 4 kiB (one flash sector). Taking a 24-bit virtual address, firstly bits 23:22 (the two MSBs) are masked to zero, and then BASE is added to bits 23:12 (the upper 12 bits) to form the physical address. Translation wraps on a 16 MiB boundary."]
+    #[inline(always)]
+    pub fn set_base(&mut self, val: u16) {
+        self.0 = (self.0 & !(0x0fff << 0usize)) | (((val as u32) & 0x0fff) << 0usize);
+    }
+    #[doc = "Translation aperture size for this virtual address range, in units of 4 kiB (one flash sector). Bits 21:12 of the virtual address are compared to SIZE. Offsets greater than SIZE return a bus error, and do not cause a QSPI access."]
+    #[inline(always)]
+    pub const fn size(&self) -> u16 {
+        let val = (self.0 >> 16usize) & 0x07ff;
+        val as u16
+    }
+    #[doc = "Translation aperture size for this virtual address range, in units of 4 kiB (one flash sector). Bits 21:12 of the virtual address are compared to SIZE. Offsets greater than SIZE return a bus error, and do not cause a QSPI access."]
+    #[inline(always)]
+    pub fn set_size(&mut self, val: u16) {
+        self.0 = (self.0 & !(0x07ff << 16usize)) | (((val as u32) & 0x07ff) << 16usize);
+    }
+}
+impl Default for Atrans1 {
+    #[inline(always)]
+    fn default() -> Atrans1 {
+        Atrans1(0)
+    }
+}
+#[doc = "Configure address translation for XIP virtual addresses 0x800000 through 0xbfffff (a 4 MiB window starting at +8 MiB). Address translation allows a program image to be executed in place at multiple physical flash addresses (for example, a double-buffered flash image for over-the-air updates), without the overhead of position-independent code. At reset, the address translation registers are initialised to an identity mapping, so that they can be ignored if address translation is not required. Note that the XIP cache is fully virtually addressed, so a cache flush is required after changing the address translation."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Atrans2(pub u32);
+impl Atrans2 {
+    #[doc = "Physical address base for this virtual address range, in units of 4 kiB (one flash sector). Taking a 24-bit virtual address, firstly bits 23:22 (the two MSBs) are masked to zero, and then BASE is added to bits 23:12 (the upper 12 bits) to form the physical address. Translation wraps on a 16 MiB boundary."]
+    #[inline(always)]
+    pub const fn base(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0x0fff;
+        val as u16
+    }
+    #[doc = "Physical address base for this virtual address range, in units of 4 kiB (one flash sector). Taking a 24-bit virtual address, firstly bits 23:22 (the two MSBs) are masked to zero, and then BASE is added to bits 23:12 (the upper 12 bits) to form the physical address. Translation wraps on a 16 MiB boundary."]
+    #[inline(always)]
+    pub fn set_base(&mut self, val: u16) {
+        self.0 = (self.0 & !(0x0fff << 0usize)) | (((val as u32) & 0x0fff) << 0usize);
+    }
+    #[doc = "Translation aperture size for this virtual address range, in units of 4 kiB (one flash sector). Bits 21:12 of the virtual address are compared to SIZE. Offsets greater than SIZE return a bus error, and do not cause a QSPI access."]
+    #[inline(always)]
+    pub const fn size(&self) -> u16 {
+        let val = (self.0 >> 16usize) & 0x07ff;
+        val as u16
+    }
+    #[doc = "Translation aperture size for this virtual address range, in units of 4 kiB (one flash sector). Bits 21:12 of the virtual address are compared to SIZE. Offsets greater than SIZE return a bus error, and do not cause a QSPI access."]
+    #[inline(always)]
+    pub fn set_size(&mut self, val: u16) {
+        self.0 = (self.0 & !(0x07ff << 16usize)) | (((val as u32) & 0x07ff) << 16usize);
+    }
+}
+impl Default for Atrans2 {
+    #[inline(always)]
+    fn default() -> Atrans2 {
+        Atrans2(0)
+    }
+}
+#[doc = "Configure address translation for XIP virtual addresses 0xc00000 through 0xffffff (a 4 MiB window starting at +12 MiB). Address translation allows a program image to be executed in place at multiple physical flash addresses (for example, a double-buffered flash image for over-the-air updates), without the overhead of position-independent code. At reset, the address translation registers are initialised to an identity mapping, so that they can be ignored if address translation is not required. Note that the XIP cache is fully virtually addressed, so a cache flush is required after changing the address translation."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Atrans3(pub u32);
+impl Atrans3 {
+    #[doc = "Physical address base for this virtual address range, in units of 4 kiB (one flash sector). Taking a 24-bit virtual address, firstly bits 23:22 (the two MSBs) are masked to zero, and then BASE is added to bits 23:12 (the upper 12 bits) to form the physical address. Translation wraps on a 16 MiB boundary."]
+    #[inline(always)]
+    pub const fn base(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0x0fff;
+        val as u16
+    }
+    #[doc = "Physical address base for this virtual address range, in units of 4 kiB (one flash sector). Taking a 24-bit virtual address, firstly bits 23:22 (the two MSBs) are masked to zero, and then BASE is added to bits 23:12 (the upper 12 bits) to form the physical address. Translation wraps on a 16 MiB boundary."]
+    #[inline(always)]
+    pub fn set_base(&mut self, val: u16) {
+        self.0 = (self.0 & !(0x0fff << 0usize)) | (((val as u32) & 0x0fff) << 0usize);
+    }
+    #[doc = "Translation aperture size for this virtual address range, in units of 4 kiB (one flash sector). Bits 21:12 of the virtual address are compared to SIZE. Offsets greater than SIZE return a bus error, and do not cause a QSPI access."]
+    #[inline(always)]
+    pub const fn size(&self) -> u16 {
+        let val = (self.0 >> 16usize) & 0x07ff;
+        val as u16
+    }
+    #[doc = "Translation aperture size for this virtual address range, in units of 4 kiB (one flash sector). Bits 21:12 of the virtual address are compared to SIZE. Offsets greater than SIZE return a bus error, and do not cause a QSPI access."]
+    #[inline(always)]
+    pub fn set_size(&mut self, val: u16) {
+        self.0 = (self.0 & !(0x07ff << 16usize)) | (((val as u32) & 0x07ff) << 16usize);
+    }
+}
+impl Default for Atrans3 {
+    #[inline(always)]
+    fn default() -> Atrans3 {
+        Atrans3(0)
+    }
+}
+#[doc = "Configure address translation for XIP virtual addresses 0x1000000 through 0x13fffff (a 4 MiB window starting at +16 MiB). Address translation allows a program image to be executed in place at multiple physical flash addresses (for example, a double-buffered flash image for over-the-air updates), without the overhead of position-independent code. At reset, the address translation registers are initialised to an identity mapping, so that they can be ignored if address translation is not required. Note that the XIP cache is fully virtually addressed, so a cache flush is required after changing the address translation."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Atrans4(pub u32);
+impl Atrans4 {
+    #[doc = "Physical address base for this virtual address range, in units of 4 kiB (one flash sector). Taking a 24-bit virtual address, firstly bits 23:22 (the two MSBs) are masked to zero, and then BASE is added to bits 23:12 (the upper 12 bits) to form the physical address. Translation wraps on a 16 MiB boundary."]
+    #[inline(always)]
+    pub const fn base(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0x0fff;
+        val as u16
+    }
+    #[doc = "Physical address base for this virtual address range, in units of 4 kiB (one flash sector). Taking a 24-bit virtual address, firstly bits 23:22 (the two MSBs) are masked to zero, and then BASE is added to bits 23:12 (the upper 12 bits) to form the physical address. Translation wraps on a 16 MiB boundary."]
+    #[inline(always)]
+    pub fn set_base(&mut self, val: u16) {
+        self.0 = (self.0 & !(0x0fff << 0usize)) | (((val as u32) & 0x0fff) << 0usize);
+    }
+    #[doc = "Translation aperture size for this virtual address range, in units of 4 kiB (one flash sector). Bits 21:12 of the virtual address are compared to SIZE. Offsets greater than SIZE return a bus error, and do not cause a QSPI access."]
+    #[inline(always)]
+    pub const fn size(&self) -> u16 {
+        let val = (self.0 >> 16usize) & 0x07ff;
+        val as u16
+    }
+    #[doc = "Translation aperture size for this virtual address range, in units of 4 kiB (one flash sector). Bits 21:12 of the virtual address are compared to SIZE. Offsets greater than SIZE return a bus error, and do not cause a QSPI access."]
+    #[inline(always)]
+    pub fn set_size(&mut self, val: u16) {
+        self.0 = (self.0 & !(0x07ff << 16usize)) | (((val as u32) & 0x07ff) << 16usize);
+    }
+}
+impl Default for Atrans4 {
+    #[inline(always)]
+    fn default() -> Atrans4 {
+        Atrans4(0)
+    }
+}
+#[doc = "Configure address translation for XIP virtual addresses 0x1400000 through 0x17fffff (a 4 MiB window starting at +20 MiB). Address translation allows a program image to be executed in place at multiple physical flash addresses (for example, a double-buffered flash image for over-the-air updates), without the overhead of position-independent code. At reset, the address translation registers are initialised to an identity mapping, so that they can be ignored if address translation is not required. Note that the XIP cache is fully virtually addressed, so a cache flush is required after changing the address translation."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Atrans5(pub u32);
+impl Atrans5 {
+    #[doc = "Physical address base for this virtual address range, in units of 4 kiB (one flash sector). Taking a 24-bit virtual address, firstly bits 23:22 (the two MSBs) are masked to zero, and then BASE is added to bits 23:12 (the upper 12 bits) to form the physical address. Translation wraps on a 16 MiB boundary."]
+    #[inline(always)]
+    pub const fn base(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0x0fff;
+        val as u16
+    }
+    #[doc = "Physical address base for this virtual address range, in units of 4 kiB (one flash sector). Taking a 24-bit virtual address, firstly bits 23:22 (the two MSBs) are masked to zero, and then BASE is added to bits 23:12 (the upper 12 bits) to form the physical address. Translation wraps on a 16 MiB boundary."]
+    #[inline(always)]
+    pub fn set_base(&mut self, val: u16) {
+        self.0 = (self.0 & !(0x0fff << 0usize)) | (((val as u32) & 0x0fff) << 0usize);
+    }
+    #[doc = "Translation aperture size for this virtual address range, in units of 4 kiB (one flash sector). Bits 21:12 of the virtual address are compared to SIZE. Offsets greater than SIZE return a bus error, and do not cause a QSPI access."]
+    #[inline(always)]
+    pub const fn size(&self) -> u16 {
+        let val = (self.0 >> 16usize) & 0x07ff;
+        val as u16
+    }
+    #[doc = "Translation aperture size for this virtual address range, in units of 4 kiB (one flash sector). Bits 21:12 of the virtual address are compared to SIZE. Offsets greater than SIZE return a bus error, and do not cause a QSPI access."]
+    #[inline(always)]
+    pub fn set_size(&mut self, val: u16) {
+        self.0 = (self.0 & !(0x07ff << 16usize)) | (((val as u32) & 0x07ff) << 16usize);
+    }
+}
+impl Default for Atrans5 {
+    #[inline(always)]
+    fn default() -> Atrans5 {
+        Atrans5(0)
+    }
+}
+#[doc = "Configure address translation for XIP virtual addresses 0x1800000 through 0x1bfffff (a 4 MiB window starting at +24 MiB). Address translation allows a program image to be executed in place at multiple physical flash addresses (for example, a double-buffered flash image for over-the-air updates), without the overhead of position-independent code. At reset, the address translation registers are initialised to an identity mapping, so that they can be ignored if address translation is not required. Note that the XIP cache is fully virtually addressed, so a cache flush is required after changing the address translation."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Atrans6(pub u32);
+impl Atrans6 {
+    #[doc = "Physical address base for this virtual address range, in units of 4 kiB (one flash sector). Taking a 24-bit virtual address, firstly bits 23:22 (the two MSBs) are masked to zero, and then BASE is added to bits 23:12 (the upper 12 bits) to form the physical address. Translation wraps on a 16 MiB boundary."]
+    #[inline(always)]
+    pub const fn base(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0x0fff;
+        val as u16
+    }
+    #[doc = "Physical address base for this virtual address range, in units of 4 kiB (one flash sector). Taking a 24-bit virtual address, firstly bits 23:22 (the two MSBs) are masked to zero, and then BASE is added to bits 23:12 (the upper 12 bits) to form the physical address. Translation wraps on a 16 MiB boundary."]
+    #[inline(always)]
+    pub fn set_base(&mut self, val: u16) {
+        self.0 = (self.0 & !(0x0fff << 0usize)) | (((val as u32) & 0x0fff) << 0usize);
+    }
+    #[doc = "Translation aperture size for this virtual address range, in units of 4 kiB (one flash sector). Bits 21:12 of the virtual address are compared to SIZE. Offsets greater than SIZE return a bus error, and do not cause a QSPI access."]
+    #[inline(always)]
+    pub const fn size(&self) -> u16 {
+        let val = (self.0 >> 16usize) & 0x07ff;
+        val as u16
+    }
+    #[doc = "Translation aperture size for this virtual address range, in units of 4 kiB (one flash sector). Bits 21:12 of the virtual address are compared to SIZE. Offsets greater than SIZE return a bus error, and do not cause a QSPI access."]
+    #[inline(always)]
+    pub fn set_size(&mut self, val: u16) {
+        self.0 = (self.0 & !(0x07ff << 16usize)) | (((val as u32) & 0x07ff) << 16usize);
+    }
+}
+impl Default for Atrans6 {
+    #[inline(always)]
+    fn default() -> Atrans6 {
+        Atrans6(0)
+    }
+}
+#[doc = "Configure address translation for XIP virtual addresses 0x1c00000 through 0x1ffffff (a 4 MiB window starting at +28 MiB). Address translation allows a program image to be executed in place at multiple physical flash addresses (for example, a double-buffered flash image for over-the-air updates), without the overhead of position-independent code. At reset, the address translation registers are initialised to an identity mapping, so that they can be ignored if address translation is not required. Note that the XIP cache is fully virtually addressed, so a cache flush is required after changing the address translation."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Atrans7(pub u32);
+impl Atrans7 {
+    #[doc = "Physical address base for this virtual address range, in units of 4 kiB (one flash sector). Taking a 24-bit virtual address, firstly bits 23:22 (the two MSBs) are masked to zero, and then BASE is added to bits 23:12 (the upper 12 bits) to form the physical address. Translation wraps on a 16 MiB boundary."]
+    #[inline(always)]
+    pub const fn base(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0x0fff;
+        val as u16
+    }
+    #[doc = "Physical address base for this virtual address range, in units of 4 kiB (one flash sector). Taking a 24-bit virtual address, firstly bits 23:22 (the two MSBs) are masked to zero, and then BASE is added to bits 23:12 (the upper 12 bits) to form the physical address. Translation wraps on a 16 MiB boundary."]
+    #[inline(always)]
+    pub fn set_base(&mut self, val: u16) {
+        self.0 = (self.0 & !(0x0fff << 0usize)) | (((val as u32) & 0x0fff) << 0usize);
+    }
+    #[doc = "Translation aperture size for this virtual address range, in units of 4 kiB (one flash sector). Bits 21:12 of the virtual address are compared to SIZE. Offsets greater than SIZE return a bus error, and do not cause a QSPI access."]
+    #[inline(always)]
+    pub const fn size(&self) -> u16 {
+        let val = (self.0 >> 16usize) & 0x07ff;
+        val as u16
+    }
+    #[doc = "Translation aperture size for this virtual address range, in units of 4 kiB (one flash sector). Bits 21:12 of the virtual address are compared to SIZE. Offsets greater than SIZE return a bus error, and do not cause a QSPI access."]
+    #[inline(always)]
+    pub fn set_size(&mut self, val: u16) {
+        self.0 = (self.0 & !(0x07ff << 16usize)) | (((val as u32) & 0x07ff) << 16usize);
+    }
+}
+impl Default for Atrans7 {
+    #[inline(always)]
+    fn default() -> Atrans7 {
+        Atrans7(0)
+    }
+}
+#[doc = "Control and status for direct serial mode Direct serial mode allows the processor to send and receive raw serial frames, for programming, configuration and control of the external memory devices. Only SPI mode 0 (CPOL=0 CPHA=0) is supported."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct DirectCsr(pub u32);
+impl DirectCsr {
+    #[doc = "Enable direct mode. In direct mode, software controls the chip select lines, and can perform direct SPI transfers by pushing data to the DIRECT_TX FIFO, and popping the same amount of data from the DIRECT_RX FIFO. Memory-mapped accesses will generate bus errors when direct serial mode is enabled."]
+    #[inline(always)]
+    pub const fn en(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Enable direct mode. In direct mode, software controls the chip select lines, and can perform direct SPI transfers by pushing data to the DIRECT_TX FIFO, and popping the same amount of data from the DIRECT_RX FIFO. Memory-mapped accesses will generate bus errors when direct serial mode is enabled."]
+    #[inline(always)]
+    pub fn set_en(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[doc = "Direct mode busy flag. If 1, data is currently being shifted in/out (or would be if the interface were not stalled on the RX FIFO), and the chip select must not yet be deasserted. The busy flag will also be set to 1 if a memory-mapped transfer is still in progress when direct mode is enabled. Direct mode blocks new memory-mapped transfers, but can't halt a transfer that is already in progress. If there is a chance that memory-mapped transfers may be in progress, the busy flag should be polled for 0 before asserting the chip select. (In practice you will usually discover this timing condition through other means, because any subsequent memory-mapped transfers when direct mode is enabled will return bus errors, which are difficult to ignore.)"]
+    #[inline(always)]
+    pub const fn busy(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Direct mode busy flag. If 1, data is currently being shifted in/out (or would be if the interface were not stalled on the RX FIFO), and the chip select must not yet be deasserted. The busy flag will also be set to 1 if a memory-mapped transfer is still in progress when direct mode is enabled. Direct mode blocks new memory-mapped transfers, but can't halt a transfer that is already in progress. If there is a chance that memory-mapped transfers may be in progress, the busy flag should be polled for 0 before asserting the chip select. (In practice you will usually discover this timing condition through other means, because any subsequent memory-mapped transfers when direct mode is enabled will return bus errors, which are difficult to ignore.)"]
+    #[inline(always)]
+    pub fn set_busy(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+    #[doc = "When 1, assert (i.e. drive low) the CS0n chip select line. Note that this applies even when DIRECT_CSR_EN is 0."]
+    #[inline(always)]
+    pub const fn assert_cs0n(&self) -> bool {
+        let val = (self.0 >> 2usize) & 0x01;
+        val != 0
+    }
+    #[doc = "When 1, assert (i.e. drive low) the CS0n chip select line. Note that this applies even when DIRECT_CSR_EN is 0."]
+    #[inline(always)]
+    pub fn set_assert_cs0n(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+    }
+    #[doc = "When 1, assert (i.e. drive low) the CS1n chip select line. Note that this applies even when DIRECT_CSR_EN is 0."]
+    #[inline(always)]
+    pub const fn assert_cs1n(&self) -> bool {
+        let val = (self.0 >> 3usize) & 0x01;
+        val != 0
+    }
+    #[doc = "When 1, assert (i.e. drive low) the CS1n chip select line. Note that this applies even when DIRECT_CSR_EN is 0."]
+    #[inline(always)]
+    pub fn set_assert_cs1n(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
+    }
+    #[doc = "When 1, automatically assert the CS0n chip select line whenever the BUSY flag is set."]
+    #[inline(always)]
+    pub const fn auto_cs0n(&self) -> bool {
+        let val = (self.0 >> 6usize) & 0x01;
+        val != 0
+    }
+    #[doc = "When 1, automatically assert the CS0n chip select line whenever the BUSY flag is set."]
+    #[inline(always)]
+    pub fn set_auto_cs0n(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
+    }
+    #[doc = "When 1, automatically assert the CS1n chip select line whenever the BUSY flag is set."]
+    #[inline(always)]
+    pub const fn auto_cs1n(&self) -> bool {
+        let val = (self.0 >> 7usize) & 0x01;
+        val != 0
+    }
+    #[doc = "When 1, automatically assert the CS1n chip select line whenever the BUSY flag is set."]
+    #[inline(always)]
+    pub fn set_auto_cs1n(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
+    }
+    #[doc = "When 1, the DIRECT_TX FIFO is currently full. If the processor tries to write more data, that data will be ignored."]
+    #[inline(always)]
+    pub const fn txfull(&self) -> bool {
+        let val = (self.0 >> 10usize) & 0x01;
+        val != 0
+    }
+    #[doc = "When 1, the DIRECT_TX FIFO is currently full. If the processor tries to write more data, that data will be ignored."]
+    #[inline(always)]
+    pub fn set_txfull(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize);
+    }
+    #[doc = "When 1, the DIRECT_TX FIFO is currently empty. Unless the processor pushes more data, transmission will stop and BUSY will go low once the current 8-bit serial frame completes."]
+    #[inline(always)]
+    pub const fn txempty(&self) -> bool {
+        let val = (self.0 >> 11usize) & 0x01;
+        val != 0
+    }
+    #[doc = "When 1, the DIRECT_TX FIFO is currently empty. Unless the processor pushes more data, transmission will stop and BUSY will go low once the current 8-bit serial frame completes."]
+    #[inline(always)]
+    pub fn set_txempty(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
+    }
+    #[doc = "Current level of DIRECT_TX FIFO"]
+    #[inline(always)]
+    pub const fn txlevel(&self) -> u8 {
+        let val = (self.0 >> 12usize) & 0x07;
+        val as u8
+    }
+    #[doc = "Current level of DIRECT_TX FIFO"]
+    #[inline(always)]
+    pub fn set_txlevel(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x07 << 12usize)) | (((val as u32) & 0x07) << 12usize);
+    }
+    #[doc = "When 1, the DIRECT_RX FIFO is currently empty. If the processor attempts to read more data, the FIFO state is not affected, but the value returned to the processor is undefined."]
+    #[inline(always)]
+    pub const fn rxempty(&self) -> bool {
+        let val = (self.0 >> 16usize) & 0x01;
+        val != 0
+    }
+    #[doc = "When 1, the DIRECT_RX FIFO is currently empty. If the processor attempts to read more data, the FIFO state is not affected, but the value returned to the processor is undefined."]
+    #[inline(always)]
+    pub fn set_rxempty(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
+    }
+    #[doc = "When 1, the DIRECT_RX FIFO is currently full. The serial interface will be stalled until data is popped; the interface will not begin a new serial frame when the DIRECT_TX FIFO is empty or the DIRECT_RX FIFO is full."]
+    #[inline(always)]
+    pub const fn rxfull(&self) -> bool {
+        let val = (self.0 >> 17usize) & 0x01;
+        val != 0
+    }
+    #[doc = "When 1, the DIRECT_RX FIFO is currently full. The serial interface will be stalled until data is popped; the interface will not begin a new serial frame when the DIRECT_TX FIFO is empty or the DIRECT_RX FIFO is full."]
+    #[inline(always)]
+    pub fn set_rxfull(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
+    }
+    #[doc = "Current level of DIRECT_RX FIFO"]
+    #[inline(always)]
+    pub const fn rxlevel(&self) -> u8 {
+        let val = (self.0 >> 18usize) & 0x07;
+        val as u8
+    }
+    #[doc = "Current level of DIRECT_RX FIFO"]
+    #[inline(always)]
+    pub fn set_rxlevel(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x07 << 18usize)) | (((val as u32) & 0x07) << 18usize);
+    }
+    #[doc = "Clock divisor for direct serial mode. Divisors of 1..255 are encoded directly, and the maximum divisor of 256 is encoded by a value of CLKDIV=0. The clock divisor can be changed on-the-fly by software, without halting or otherwise coordinating with the serial interface. The serial interface will sample the latest clock divisor each time it begins the transmission of a new byte."]
+    #[inline(always)]
+    pub const fn clkdiv(&self) -> u8 {
+        let val = (self.0 >> 22usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Clock divisor for direct serial mode. Divisors of 1..255 are encoded directly, and the maximum divisor of 256 is encoded by a value of CLKDIV=0. The clock divisor can be changed on-the-fly by software, without halting or otherwise coordinating with the serial interface. The serial interface will sample the latest clock divisor each time it begins the transmission of a new byte."]
+    #[inline(always)]
+    pub fn set_clkdiv(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 22usize)) | (((val as u32) & 0xff) << 22usize);
+    }
+    #[doc = "Delay the read data sample timing, in units of one half of a system clock cycle. (Not necessarily half of an SCK cycle.)"]
+    #[inline(always)]
+    pub const fn rxdelay(&self) -> u8 {
+        let val = (self.0 >> 30usize) & 0x03;
+        val as u8
+    }
+    #[doc = "Delay the read data sample timing, in units of one half of a system clock cycle. (Not necessarily half of an SCK cycle.)"]
+    #[inline(always)]
+    pub fn set_rxdelay(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x03 << 30usize)) | (((val as u32) & 0x03) << 30usize);
+    }
+}
+impl Default for DirectCsr {
+    #[inline(always)]
+    fn default() -> DirectCsr {
+        DirectCsr(0)
+    }
+}
+#[doc = "Receive FIFO for direct mode"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct DirectRx(pub u32);
+impl DirectRx {
+    #[doc = "With each byte clocked out on the serial interface, one byte will simultaneously be clocked in, and will appear in this FIFO. The serial interface will stall when this FIFO is full, to avoid dropping data. When 16-bit data is pushed into the TX FIFO, the corresponding RX FIFO push will also contain 16 bits of data. The least-significant byte is the first one received."]
+    #[inline(always)]
+    pub const fn direct_rx(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0xffff;
+        val as u16
+    }
+    #[doc = "With each byte clocked out on the serial interface, one byte will simultaneously be clocked in, and will appear in this FIFO. The serial interface will stall when this FIFO is full, to avoid dropping data. When 16-bit data is pushed into the TX FIFO, the corresponding RX FIFO push will also contain 16 bits of data. The least-significant byte is the first one received."]
+    #[inline(always)]
+    pub fn set_direct_rx(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+    }
+}
+impl Default for DirectRx {
+    #[inline(always)]
+    fn default() -> DirectRx {
+        DirectRx(0)
+    }
+}
+#[doc = "Transmit FIFO for direct mode"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct DirectTx(pub u32);
+impl DirectTx {
+    #[doc = "Data pushed here will be clocked out falling edges of SCK (or before the very first rising edge of SCK, if this is the first pulse). For each byte clocked out, the interface will simultaneously sample one byte, on rising edges of SCK, and push this to the DIRECT_RX FIFO. For 16-bit data, the least-significant byte is transmitted first."]
+    #[inline(always)]
+    pub const fn data(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0xffff;
+        val as u16
+    }
+    #[doc = "Data pushed here will be clocked out falling edges of SCK (or before the very first rising edge of SCK, if this is the first pulse). For each byte clocked out, the interface will simultaneously sample one byte, on rising edges of SCK, and push this to the DIRECT_RX FIFO. For 16-bit data, the least-significant byte is transmitted first."]
+    #[inline(always)]
+    pub fn set_data(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+    }
+    #[doc = "Configure whether this FIFO record is transferred with single/dual/quad interface width (0/1/2). Different widths can be mixed freely."]
+    #[inline(always)]
+    pub const fn iwidth(&self) -> super::vals::Iwidth {
+        let val = (self.0 >> 16usize) & 0x03;
+        super::vals::Iwidth::from_bits(val as u8)
+    }
+    #[doc = "Configure whether this FIFO record is transferred with single/dual/quad interface width (0/1/2). Different widths can be mixed freely."]
+    #[inline(always)]
+    pub fn set_iwidth(&mut self, val: super::vals::Iwidth) {
+        self.0 = (self.0 & !(0x03 << 16usize)) | (((val.to_bits() as u32) & 0x03) << 16usize);
+    }
+    #[doc = "Data width. If 0, hardware will transmit the 8 LSBs of the DIRECT_TX DATA field, and return an 8-bit value in the 8 LSBs of DIRECT_RX. If 1, the full 16-bit width is used. 8-bit and 16-bit transfers can be mixed freely."]
+    #[inline(always)]
+    pub const fn dwidth(&self) -> bool {
+        let val = (self.0 >> 18usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Data width. If 0, hardware will transmit the 8 LSBs of the DIRECT_TX DATA field, and return an 8-bit value in the 8 LSBs of DIRECT_RX. If 1, the full 16-bit width is used. 8-bit and 16-bit transfers can be mixed freely."]
+    #[inline(always)]
+    pub fn set_dwidth(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize);
+    }
+    #[doc = "Output enable (active-high). For single width (SPI), this field is ignored, and SD0 is always set to output, with SD1 always set to input. For dual and quad width (DSPI/QSPI), this sets whether the relevant SDx pads are set to output whilst transferring this FIFO record. In this case the command/address should have OE set, and the data transfer should have OE set or clear depending on the direction of the transfer."]
+    #[inline(always)]
+    pub const fn oe(&self) -> bool {
+        let val = (self.0 >> 19usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Output enable (active-high). For single width (SPI), this field is ignored, and SD0 is always set to output, with SD1 always set to input. For dual and quad width (DSPI/QSPI), this sets whether the relevant SDx pads are set to output whilst transferring this FIFO record. In this case the command/address should have OE set, and the data transfer should have OE set or clear depending on the direction of the transfer."]
+    #[inline(always)]
+    pub fn set_oe(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize);
+    }
+    #[doc = "Inhibit the RX FIFO push that would correspond to this TX FIFO entry. Useful to avoid garbage appearing in the RX FIFO when pushing the command at the beginning of a SPI transfer."]
+    #[inline(always)]
+    pub const fn nopush(&self) -> bool {
+        let val = (self.0 >> 20usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Inhibit the RX FIFO push that would correspond to this TX FIFO entry. Useful to avoid garbage appearing in the RX FIFO when pushing the command at the beginning of a SPI transfer."]
+    #[inline(always)]
+    pub fn set_nopush(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize);
+    }
+}
+impl Default for DirectTx {
+    #[inline(always)]
+    fn default() -> DirectTx {
+        DirectTx(0)
+    }
+}
+#[doc = "Command constants used for reads from memory address window 0. The reset value of the M0_RCMD register is configured to support a basic 03h serial read transfer with no additional configuration."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct M0rcmd(pub u32);
+impl M0rcmd {
+    #[doc = "The command prefix bits to prepend on each new transfer, if Mx_RFMT_PREFIX_LEN is nonzero."]
+    #[inline(always)]
+    pub const fn prefix(&self) -> u8 {
+        let val = (self.0 >> 0usize) & 0xff;
+        val as u8
+    }
+    #[doc = "The command prefix bits to prepend on each new transfer, if Mx_RFMT_PREFIX_LEN is nonzero."]
+    #[inline(always)]
+    pub fn set_prefix(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize);
+    }
+    #[doc = "The command suffix bits following the address, if Mx_RFMT_SUFFIX_LEN is nonzero."]
+    #[inline(always)]
+    pub const fn suffix(&self) -> u8 {
+        let val = (self.0 >> 8usize) & 0xff;
+        val as u8
+    }
+    #[doc = "The command suffix bits following the address, if Mx_RFMT_SUFFIX_LEN is nonzero."]
+    #[inline(always)]
+    pub fn set_suffix(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize);
+    }
+}
+impl Default for M0rcmd {
+    #[inline(always)]
+    fn default() -> M0rcmd {
+        M0rcmd(0)
+    }
+}
+#[doc = "Read transfer format configuration for memory address window 0. Configure the bus width of each transfer phase individually, and configure the length or presence of the command prefix, command suffix and dummy/turnaround transfer phases. Only 24-bit addresses are supported. The reset value of the M0_RFMT register is configured to support a basic 03h serial read transfer with no additional configuration."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct M0rfmt(pub u32);
+impl M0rfmt {
+    #[doc = "The transfer width used for the command prefix, if any"]
+    #[inline(always)]
+    pub const fn prefix_width(&self) -> super::vals::M0rfmtPrefixWidth {
+        let val = (self.0 >> 0usize) & 0x03;
+        super::vals::M0rfmtPrefixWidth::from_bits(val as u8)
+    }
+    #[doc = "The transfer width used for the command prefix, if any"]
+    #[inline(always)]
+    pub fn set_prefix_width(&mut self, val: super::vals::M0rfmtPrefixWidth) {
+        self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize);
+    }
+    #[doc = "The transfer width used for the address. The address phase always transfers 24 bits in total."]
+    #[inline(always)]
+    pub const fn addr_width(&self) -> super::vals::M0rfmtAddrWidth {
+        let val = (self.0 >> 2usize) & 0x03;
+        super::vals::M0rfmtAddrWidth::from_bits(val as u8)
+    }
+    #[doc = "The transfer width used for the address. The address phase always transfers 24 bits in total."]
+    #[inline(always)]
+    pub fn set_addr_width(&mut self, val: super::vals::M0rfmtAddrWidth) {
+        self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize);
+    }
+    #[doc = "The width used for the post-address command suffix, if any"]
+    #[inline(always)]
+    pub const fn suffix_width(&self) -> super::vals::M0rfmtSuffixWidth {
+        let val = (self.0 >> 4usize) & 0x03;
+        super::vals::M0rfmtSuffixWidth::from_bits(val as u8)
+    }
+    #[doc = "The width used for the post-address command suffix, if any"]
+    #[inline(always)]
+    pub fn set_suffix_width(&mut self, val: super::vals::M0rfmtSuffixWidth) {
+        self.0 = (self.0 & !(0x03 << 4usize)) | (((val.to_bits() as u32) & 0x03) << 4usize);
+    }
+    #[doc = "The width used for the dummy phase, if any. If width is single, SD0/MOSI is held asserted low during the dummy phase, and SD1...SD3 are tristated. If width is dual/quad, all IOs are tristated during the dummy phase."]
+    #[inline(always)]
+    pub const fn dummy_width(&self) -> super::vals::M0rfmtDummyWidth {
+        let val = (self.0 >> 6usize) & 0x03;
+        super::vals::M0rfmtDummyWidth::from_bits(val as u8)
+    }
+    #[doc = "The width used for the dummy phase, if any. If width is single, SD0/MOSI is held asserted low during the dummy phase, and SD1...SD3 are tristated. If width is dual/quad, all IOs are tristated during the dummy phase."]
+    #[inline(always)]
+    pub fn set_dummy_width(&mut self, val: super::vals::M0rfmtDummyWidth) {
+        self.0 = (self.0 & !(0x03 << 6usize)) | (((val.to_bits() as u32) & 0x03) << 6usize);
+    }
+    #[doc = "The width used for the data transfer"]
+    #[inline(always)]
+    pub const fn data_width(&self) -> super::vals::M0rfmtDataWidth {
+        let val = (self.0 >> 8usize) & 0x03;
+        super::vals::M0rfmtDataWidth::from_bits(val as u8)
+    }
+    #[doc = "The width used for the data transfer"]
+    #[inline(always)]
+    pub fn set_data_width(&mut self, val: super::vals::M0rfmtDataWidth) {
+        self.0 = (self.0 & !(0x03 << 8usize)) | (((val.to_bits() as u32) & 0x03) << 8usize);
+    }
+    #[doc = "Length of command prefix, in units of 8 bits. (i.e. 2 cycles for quad width, 4 for dual, 8 for single)"]
+    #[inline(always)]
+    pub const fn prefix_len(&self) -> super::vals::M0rfmtPrefixLen {
+        let val = (self.0 >> 12usize) & 0x01;
+        super::vals::M0rfmtPrefixLen::from_bits(val as u8)
+    }
+    #[doc = "Length of command prefix, in units of 8 bits. (i.e. 2 cycles for quad width, 4 for dual, 8 for single)"]
+    #[inline(always)]
+    pub fn set_prefix_len(&mut self, val: super::vals::M0rfmtPrefixLen) {
+        self.0 = (self.0 & !(0x01 << 12usize)) | (((val.to_bits() as u32) & 0x01) << 12usize);
+    }
+    #[doc = "Length of post-address command suffix, in units of 4 bits. (i.e. 1 cycle for quad width, 2 for dual, 4 for single) Only values of 0 and 8 bits are supported."]
+    #[inline(always)]
+    pub const fn suffix_len(&self) -> super::vals::M0rfmtSuffixLen {
+        let val = (self.0 >> 14usize) & 0x03;
+        super::vals::M0rfmtSuffixLen::from_bits(val as u8)
+    }
+    #[doc = "Length of post-address command suffix, in units of 4 bits. (i.e. 1 cycle for quad width, 2 for dual, 4 for single) Only values of 0 and 8 bits are supported."]
+    #[inline(always)]
+    pub fn set_suffix_len(&mut self, val: super::vals::M0rfmtSuffixLen) {
+        self.0 = (self.0 & !(0x03 << 14usize)) | (((val.to_bits() as u32) & 0x03) << 14usize);
+    }
+    #[doc = "Length of dummy phase between command suffix and data phase, in units of 4 bits. (i.e. 1 cycle for quad width, 2 for dual, 4 for single)"]
+    #[inline(always)]
+    pub const fn dummy_len(&self) -> super::vals::M0rfmtDummyLen {
+        let val = (self.0 >> 16usize) & 0x07;
+        super::vals::M0rfmtDummyLen::from_bits(val as u8)
+    }
+    #[doc = "Length of dummy phase between command suffix and data phase, in units of 4 bits. (i.e. 1 cycle for quad width, 2 for dual, 4 for single)"]
+    #[inline(always)]
+    pub fn set_dummy_len(&mut self, val: super::vals::M0rfmtDummyLen) {
+        self.0 = (self.0 & !(0x07 << 16usize)) | (((val.to_bits() as u32) & 0x07) << 16usize);
+    }
+    #[doc = "Enable double transfer rate (DTR) for read commands: address, suffix and read data phases are active on both edges of SCK. SDO data is launched centre-aligned on each SCK edge, and SDI data is captured on the SCK edge that follows its launch. DTR is implemented by halving the clock rate; SCK has a period of 2 x CLK_DIV throughout the transfer. The prefix and dummy phases are still single transfer rate. If the suffix is quad-width, it must be 0 or 8 bits in length, to ensure an even number of SCK edges."]
+    #[inline(always)]
+    pub const fn dtr(&self) -> bool {
+        let val = (self.0 >> 28usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Enable double transfer rate (DTR) for read commands: address, suffix and read data phases are active on both edges of SCK. SDO data is launched centre-aligned on each SCK edge, and SDI data is captured on the SCK edge that follows its launch. DTR is implemented by halving the clock rate; SCK has a period of 2 x CLK_DIV throughout the transfer. The prefix and dummy phases are still single transfer rate. If the suffix is quad-width, it must be 0 or 8 bits in length, to ensure an even number of SCK edges."]
+    #[inline(always)]
+    pub fn set_dtr(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 28usize)) | (((val as u32) & 0x01) << 28usize);
+    }
+}
+impl Default for M0rfmt {
+    #[inline(always)]
+    fn default() -> M0rfmt {
+        M0rfmt(0)
+    }
+}
+#[doc = "Timing configuration register for memory address window 0."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct M0timing(pub u32);
+impl M0timing {
+    #[doc = "Clock divisor. Odd and even divisors are supported. Defines the SCK clock period in units of 1 system clock cycle. Divisors 1..255 are encoded directly, and a divisor of 256 is encoded with a value of CLKDIV=0. The clock divisor can be changed on-the-fly, even when the QMI is currently accessing memory in this address window. All other parameters must only be changed when the QMI is idle. If software is increasing CLKDIV in anticipation of an increase in the system clock frequency, a dummy access to either memory window (and appropriate processor barriers/fences) must be inserted after the Mx_TIMING write to ensure the SCK divisor change is in effect _before_ the system clock is changed."]
+    #[inline(always)]
+    pub const fn clkdiv(&self) -> u8 {
+        let val = (self.0 >> 0usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Clock divisor. Odd and even divisors are supported. Defines the SCK clock period in units of 1 system clock cycle. Divisors 1..255 are encoded directly, and a divisor of 256 is encoded with a value of CLKDIV=0. The clock divisor can be changed on-the-fly, even when the QMI is currently accessing memory in this address window. All other parameters must only be changed when the QMI is idle. If software is increasing CLKDIV in anticipation of an increase in the system clock frequency, a dummy access to either memory window (and appropriate processor barriers/fences) must be inserted after the Mx_TIMING write to ensure the SCK divisor change is in effect _before_ the system clock is changed."]
+    #[inline(always)]
+    pub fn set_clkdiv(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize);
+    }
+    #[doc = "Delay the read data sample timing, in units of one half of a system clock cycle. (Not necessarily half of an SCK cycle.) An RXDELAY of 0 means the sample is captured at the SDI input registers simultaneously with the rising edge of SCK launched from the SCK output register. At higher SCK frequencies, RXDELAY may need to be increased to account for the round trip delay of the pads, and the clock-to-Q delay of the QSPI memory device."]
+    #[inline(always)]
+    pub const fn rxdelay(&self) -> u8 {
+        let val = (self.0 >> 8usize) & 0x07;
+        val as u8
+    }
+    #[doc = "Delay the read data sample timing, in units of one half of a system clock cycle. (Not necessarily half of an SCK cycle.) An RXDELAY of 0 means the sample is captured at the SDI input registers simultaneously with the rising edge of SCK launched from the SCK output register. At higher SCK frequencies, RXDELAY may need to be increased to account for the round trip delay of the pads, and the clock-to-Q delay of the QSPI memory device."]
+    #[inline(always)]
+    pub fn set_rxdelay(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x07 << 8usize)) | (((val as u32) & 0x07) << 8usize);
+    }
+    #[doc = "After this window's chip select is deasserted, it remains deasserted for half an SCK cycle (rounded up to an integer number of system clock cycles), plus MIN_DESELECT additional system clock cycles, before the QMI reasserts either chip select pin. Nonzero values may be required for PSRAM devices which enforce a longer minimum CS deselect time, so that they can perform internal DRAM refresh cycles whilst deselected."]
+    #[inline(always)]
+    pub const fn min_deselect(&self) -> u8 {
+        let val = (self.0 >> 12usize) & 0x1f;
+        val as u8
+    }
+    #[doc = "After this window's chip select is deasserted, it remains deasserted for half an SCK cycle (rounded up to an integer number of system clock cycles), plus MIN_DESELECT additional system clock cycles, before the QMI reasserts either chip select pin. Nonzero values may be required for PSRAM devices which enforce a longer minimum CS deselect time, so that they can perform internal DRAM refresh cycles whilst deselected."]
+    #[inline(always)]
+    pub fn set_min_deselect(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x1f << 12usize)) | (((val as u32) & 0x1f) << 12usize);
+    }
+    #[doc = "Enforce a maximum assertion duration for this window's chip select, in units of 64 system clock cycles. If 0, the QMI is permitted to keep the chip select asserted indefinitely when servicing sequential memory accesses (see COOLDOWN). This feature is required to meet timing constraints of PSRAM devices, which specify a maximum chip select assertion so they can perform DRAM refresh cycles. See also MIN_DESELECT, which can enforce a minimum deselect time. If a memory access is in progress at the time MAX_SELECT is reached, the QMI will wait for the access to complete before deasserting the chip select. This additional time must be accounted for to calculate a safe MAX_SELECT value. In the worst case, this may be a fully-formed serial transfer, including command prefix and address, with a data payload as large as one cache line."]
+    #[inline(always)]
+    pub const fn max_select(&self) -> u8 {
+        let val = (self.0 >> 17usize) & 0x3f;
+        val as u8
+    }
+    #[doc = "Enforce a maximum assertion duration for this window's chip select, in units of 64 system clock cycles. If 0, the QMI is permitted to keep the chip select asserted indefinitely when servicing sequential memory accesses (see COOLDOWN). This feature is required to meet timing constraints of PSRAM devices, which specify a maximum chip select assertion so they can perform DRAM refresh cycles. See also MIN_DESELECT, which can enforce a minimum deselect time. If a memory access is in progress at the time MAX_SELECT is reached, the QMI will wait for the access to complete before deasserting the chip select. This additional time must be accounted for to calculate a safe MAX_SELECT value. In the worst case, this may be a fully-formed serial transfer, including command prefix and address, with a data payload as large as one cache line."]
+    #[inline(always)]
+    pub fn set_max_select(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x3f << 17usize)) | (((val as u32) & 0x3f) << 17usize);
+    }
+    #[doc = "Add up to three additional system clock cycles of active hold between the last falling edge of SCK and the deassertion of this window's chip select. The default hold time is one system clock cycle. Note that flash datasheets usually give chip select active hold time from the last *rising* edge of SCK, and so even zero hold from the last falling edge would be safe. Note that this is a minimum hold time guaranteed by the QMI: the actual chip select active hold may be slightly longer for read transfers with low clock divisors and/or high sample delays. Specifically, if the point two cycles after the last RX data sample is later than the last SCK falling edge, then the hold time is measured from *this* point. Note also that, in case the final SCK pulse is masked to save energy (true for non-DTR reads when COOLDOWN is disabled or PAGE_BREAK is reached), all of QMI's timing logic behaves as though the clock pulse were still present. The SELECT_HOLD time is applied from the point where the last SCK falling edge would be if the clock pulse were not masked."]
+    #[inline(always)]
+    pub const fn select_hold(&self) -> u8 {
+        let val = (self.0 >> 23usize) & 0x03;
+        val as u8
+    }
+    #[doc = "Add up to three additional system clock cycles of active hold between the last falling edge of SCK and the deassertion of this window's chip select. The default hold time is one system clock cycle. Note that flash datasheets usually give chip select active hold time from the last *rising* edge of SCK, and so even zero hold from the last falling edge would be safe. Note that this is a minimum hold time guaranteed by the QMI: the actual chip select active hold may be slightly longer for read transfers with low clock divisors and/or high sample delays. Specifically, if the point two cycles after the last RX data sample is later than the last SCK falling edge, then the hold time is measured from *this* point. Note also that, in case the final SCK pulse is masked to save energy (true for non-DTR reads when COOLDOWN is disabled or PAGE_BREAK is reached), all of QMI's timing logic behaves as though the clock pulse were still present. The SELECT_HOLD time is applied from the point where the last SCK falling edge would be if the clock pulse were not masked."]
+    #[inline(always)]
+    pub fn set_select_hold(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x03 << 23usize)) | (((val as u32) & 0x03) << 23usize);
+    }
+    #[doc = "Add up to one additional system clock cycle of setup between chip select assertion and the first rising edge of SCK. The default setup time is one half SCK period, which is usually sufficient except for very high SCK frequencies with some flash devices."]
+    #[inline(always)]
+    pub const fn select_setup(&self) -> bool {
+        let val = (self.0 >> 25usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Add up to one additional system clock cycle of setup between chip select assertion and the first rising edge of SCK. The default setup time is one half SCK period, which is usually sufficient except for very high SCK frequencies with some flash devices."]
+    #[inline(always)]
+    pub fn set_select_setup(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 25usize)) | (((val as u32) & 0x01) << 25usize);
+    }
+    #[doc = "When page break is enabled, chip select will automatically deassert when crossing certain power-of-2-aligned address boundaries. The next access will always begin a new read/write SPI burst, even if the address of the next access follows in sequence with the last access before the page boundary. Some flash and PSRAM devices forbid crossing page boundaries with a single read/write transfer, or restrict the operating frequency for transfers that do cross page a boundary. This option allows the QMI to safely support those devices. This field has no effect when COOLDOWN is disabled."]
+    #[inline(always)]
+    pub const fn pagebreak(&self) -> super::vals::M0timingPagebreak {
+        let val = (self.0 >> 28usize) & 0x03;
+        super::vals::M0timingPagebreak::from_bits(val as u8)
+    }
+    #[doc = "When page break is enabled, chip select will automatically deassert when crossing certain power-of-2-aligned address boundaries. The next access will always begin a new read/write SPI burst, even if the address of the next access follows in sequence with the last access before the page boundary. Some flash and PSRAM devices forbid crossing page boundaries with a single read/write transfer, or restrict the operating frequency for transfers that do cross page a boundary. This option allows the QMI to safely support those devices. This field has no effect when COOLDOWN is disabled."]
+    #[inline(always)]
+    pub fn set_pagebreak(&mut self, val: super::vals::M0timingPagebreak) {
+        self.0 = (self.0 & !(0x03 << 28usize)) | (((val.to_bits() as u32) & 0x03) << 28usize);
+    }
+    #[doc = "Chip select cooldown period. When a memory transfer finishes, the chip select remains asserted for 64 x COOLDOWN system clock cycles, plus half an SCK clock period (rounded up for odd SCK divisors). After this cooldown expires, the chip select is always deasserted to save power. If the next memory access arrives within the cooldown period, the QMI may be able to append more SCK cycles to the currently ongoing SPI transfer, rather than starting a new transfer. This reduces access latency and increases bus throughput. Specifically, the next access must be in the same direction (read/write), access the same memory window (chip select 0/1), and follow sequentially the address of the last transfer. If any of these are false, the new access will first deassert the chip select, then begin a new transfer. If COOLDOWN is 0, the address alignment configured by PAGEBREAK has been reached, or the total chip select assertion limit MAX_SELECT has been reached, the cooldown period is skipped, and the chip select will always be deasserted one half SCK period after the transfer finishes."]
+    #[inline(always)]
+    pub const fn cooldown(&self) -> u8 {
+        let val = (self.0 >> 30usize) & 0x03;
+        val as u8
+    }
+    #[doc = "Chip select cooldown period. When a memory transfer finishes, the chip select remains asserted for 64 x COOLDOWN system clock cycles, plus half an SCK clock period (rounded up for odd SCK divisors). After this cooldown expires, the chip select is always deasserted to save power. If the next memory access arrives within the cooldown period, the QMI may be able to append more SCK cycles to the currently ongoing SPI transfer, rather than starting a new transfer. This reduces access latency and increases bus throughput. Specifically, the next access must be in the same direction (read/write), access the same memory window (chip select 0/1), and follow sequentially the address of the last transfer. If any of these are false, the new access will first deassert the chip select, then begin a new transfer. If COOLDOWN is 0, the address alignment configured by PAGEBREAK has been reached, or the total chip select assertion limit MAX_SELECT has been reached, the cooldown period is skipped, and the chip select will always be deasserted one half SCK period after the transfer finishes."]
+    #[inline(always)]
+    pub fn set_cooldown(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x03 << 30usize)) | (((val as u32) & 0x03) << 30usize);
+    }
+}
+impl Default for M0timing {
+    #[inline(always)]
+    fn default() -> M0timing {
+        M0timing(0)
+    }
+}
+#[doc = "Command constants used for writes to memory address window 0. The reset value of the M0_WCMD register is configured to support a basic 02h serial write transfer with no additional configuration."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct M0wcmd(pub u32);
+impl M0wcmd {
+    #[doc = "The command prefix bits to prepend on each new transfer, if Mx_WFMT_PREFIX_LEN is nonzero."]
+    #[inline(always)]
+    pub const fn prefix(&self) -> u8 {
+        let val = (self.0 >> 0usize) & 0xff;
+        val as u8
+    }
+    #[doc = "The command prefix bits to prepend on each new transfer, if Mx_WFMT_PREFIX_LEN is nonzero."]
+    #[inline(always)]
+    pub fn set_prefix(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize);
+    }
+    #[doc = "The command suffix bits following the address, if Mx_WFMT_SUFFIX_LEN is nonzero."]
+    #[inline(always)]
+    pub const fn suffix(&self) -> u8 {
+        let val = (self.0 >> 8usize) & 0xff;
+        val as u8
+    }
+    #[doc = "The command suffix bits following the address, if Mx_WFMT_SUFFIX_LEN is nonzero."]
+    #[inline(always)]
+    pub fn set_suffix(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize);
+    }
+}
+impl Default for M0wcmd {
+    #[inline(always)]
+    fn default() -> M0wcmd {
+        M0wcmd(0)
+    }
+}
+#[doc = "Write transfer format configuration for memory address window 0. Configure the bus width of each transfer phase individually, and configure the length or presence of the command prefix, command suffix and dummy/turnaround transfer phases. Only 24-bit addresses are supported. The reset value of the M0_WFMT register is configured to support a basic 02h serial write transfer. However, writes to this window must first be enabled via the XIP_CTRL_WRITABLE_M0 bit, as XIP memory is read-only by default."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct M0wfmt(pub u32);
+impl M0wfmt {
+    #[doc = "The transfer width used for the command prefix, if any"]
+    #[inline(always)]
+    pub const fn prefix_width(&self) -> super::vals::M0wfmtPrefixWidth {
+        let val = (self.0 >> 0usize) & 0x03;
+        super::vals::M0wfmtPrefixWidth::from_bits(val as u8)
+    }
+    #[doc = "The transfer width used for the command prefix, if any"]
+    #[inline(always)]
+    pub fn set_prefix_width(&mut self, val: super::vals::M0wfmtPrefixWidth) {
+        self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize);
+    }
+    #[doc = "The transfer width used for the address. The address phase always transfers 24 bits in total."]
+    #[inline(always)]
+    pub const fn addr_width(&self) -> super::vals::M0wfmtAddrWidth {
+        let val = (self.0 >> 2usize) & 0x03;
+        super::vals::M0wfmtAddrWidth::from_bits(val as u8)
+    }
+    #[doc = "The transfer width used for the address. The address phase always transfers 24 bits in total."]
+    #[inline(always)]
+    pub fn set_addr_width(&mut self, val: super::vals::M0wfmtAddrWidth) {
+        self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize);
+    }
+    #[doc = "The width used for the post-address command suffix, if any"]
+    #[inline(always)]
+    pub const fn suffix_width(&self) -> super::vals::M0wfmtSuffixWidth {
+        let val = (self.0 >> 4usize) & 0x03;
+        super::vals::M0wfmtSuffixWidth::from_bits(val as u8)
+    }
+    #[doc = "The width used for the post-address command suffix, if any"]
+    #[inline(always)]
+    pub fn set_suffix_width(&mut self, val: super::vals::M0wfmtSuffixWidth) {
+        self.0 = (self.0 & !(0x03 << 4usize)) | (((val.to_bits() as u32) & 0x03) << 4usize);
+    }
+    #[doc = "The width used for the dummy phase, if any. If width is single, SD0/MOSI is held asserted low during the dummy phase, and SD1...SD3 are tristated. If width is dual/quad, all IOs are tristated during the dummy phase."]
+    #[inline(always)]
+    pub const fn dummy_width(&self) -> super::vals::M0wfmtDummyWidth {
+        let val = (self.0 >> 6usize) & 0x03;
+        super::vals::M0wfmtDummyWidth::from_bits(val as u8)
+    }
+    #[doc = "The width used for the dummy phase, if any. If width is single, SD0/MOSI is held asserted low during the dummy phase, and SD1...SD3 are tristated. If width is dual/quad, all IOs are tristated during the dummy phase."]
+    #[inline(always)]
+    pub fn set_dummy_width(&mut self, val: super::vals::M0wfmtDummyWidth) {
+        self.0 = (self.0 & !(0x03 << 6usize)) | (((val.to_bits() as u32) & 0x03) << 6usize);
+    }
+    #[doc = "The width used for the data transfer"]
+    #[inline(always)]
+    pub const fn data_width(&self) -> super::vals::M0wfmtDataWidth {
+        let val = (self.0 >> 8usize) & 0x03;
+        super::vals::M0wfmtDataWidth::from_bits(val as u8)
+    }
+    #[doc = "The width used for the data transfer"]
+    #[inline(always)]
+    pub fn set_data_width(&mut self, val: super::vals::M0wfmtDataWidth) {
+        self.0 = (self.0 & !(0x03 << 8usize)) | (((val.to_bits() as u32) & 0x03) << 8usize);
+    }
+    #[doc = "Length of command prefix, in units of 8 bits. (i.e. 2 cycles for quad width, 4 for dual, 8 for single)"]
+    #[inline(always)]
+    pub const fn prefix_len(&self) -> super::vals::M0wfmtPrefixLen {
+        let val = (self.0 >> 12usize) & 0x01;
+        super::vals::M0wfmtPrefixLen::from_bits(val as u8)
+    }
+    #[doc = "Length of command prefix, in units of 8 bits. (i.e. 2 cycles for quad width, 4 for dual, 8 for single)"]
+    #[inline(always)]
+    pub fn set_prefix_len(&mut self, val: super::vals::M0wfmtPrefixLen) {
+        self.0 = (self.0 & !(0x01 << 12usize)) | (((val.to_bits() as u32) & 0x01) << 12usize);
+    }
+    #[doc = "Length of post-address command suffix, in units of 4 bits. (i.e. 1 cycle for quad width, 2 for dual, 4 for single) Only values of 0 and 8 bits are supported."]
+    #[inline(always)]
+    pub const fn suffix_len(&self) -> super::vals::M0wfmtSuffixLen {
+        let val = (self.0 >> 14usize) & 0x03;
+        super::vals::M0wfmtSuffixLen::from_bits(val as u8)
+    }
+    #[doc = "Length of post-address command suffix, in units of 4 bits. (i.e. 1 cycle for quad width, 2 for dual, 4 for single) Only values of 0 and 8 bits are supported."]
+    #[inline(always)]
+    pub fn set_suffix_len(&mut self, val: super::vals::M0wfmtSuffixLen) {
+        self.0 = (self.0 & !(0x03 << 14usize)) | (((val.to_bits() as u32) & 0x03) << 14usize);
+    }
+    #[doc = "Length of dummy phase between command suffix and data phase, in units of 4 bits. (i.e. 1 cycle for quad width, 2 for dual, 4 for single)"]
+    #[inline(always)]
+    pub const fn dummy_len(&self) -> super::vals::M0wfmtDummyLen {
+        let val = (self.0 >> 16usize) & 0x07;
+        super::vals::M0wfmtDummyLen::from_bits(val as u8)
+    }
+    #[doc = "Length of dummy phase between command suffix and data phase, in units of 4 bits. (i.e. 1 cycle for quad width, 2 for dual, 4 for single)"]
+    #[inline(always)]
+    pub fn set_dummy_len(&mut self, val: super::vals::M0wfmtDummyLen) {
+        self.0 = (self.0 & !(0x07 << 16usize)) | (((val.to_bits() as u32) & 0x07) << 16usize);
+    }
+    #[doc = "Enable double transfer rate (DTR) for write commands: address, suffix and write data phases are active on both edges of SCK. SDO data is launched centre-aligned on each SCK edge, and SDI data is captured on the SCK edge that follows its launch. DTR is implemented by halving the clock rate; SCK has a period of 2 x CLK_DIV throughout the transfer. The prefix and dummy phases are still single transfer rate. If the suffix is quad-width, it must be 0 or 8 bits in length, to ensure an even number of SCK edges."]
+    #[inline(always)]
+    pub const fn dtr(&self) -> bool {
+        let val = (self.0 >> 28usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Enable double transfer rate (DTR) for write commands: address, suffix and write data phases are active on both edges of SCK. SDO data is launched centre-aligned on each SCK edge, and SDI data is captured on the SCK edge that follows its launch. DTR is implemented by halving the clock rate; SCK has a period of 2 x CLK_DIV throughout the transfer. The prefix and dummy phases are still single transfer rate. If the suffix is quad-width, it must be 0 or 8 bits in length, to ensure an even number of SCK edges."]
+    #[inline(always)]
+    pub fn set_dtr(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 28usize)) | (((val as u32) & 0x01) << 28usize);
+    }
+}
+impl Default for M0wfmt {
+    #[inline(always)]
+    fn default() -> M0wfmt {
+        M0wfmt(0)
+    }
+}
+#[doc = "Command constants used for reads from memory address window 1. The reset value of the M1_RCMD register is configured to support a basic 03h serial read transfer with no additional configuration."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct M1rcmd(pub u32);
+impl M1rcmd {
+    #[doc = "The command prefix bits to prepend on each new transfer, if Mx_RFMT_PREFIX_LEN is nonzero."]
+    #[inline(always)]
+    pub const fn prefix(&self) -> u8 {
+        let val = (self.0 >> 0usize) & 0xff;
+        val as u8
+    }
+    #[doc = "The command prefix bits to prepend on each new transfer, if Mx_RFMT_PREFIX_LEN is nonzero."]
+    #[inline(always)]
+    pub fn set_prefix(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize);
+    }
+    #[doc = "The command suffix bits following the address, if Mx_RFMT_SUFFIX_LEN is nonzero."]
+    #[inline(always)]
+    pub const fn suffix(&self) -> u8 {
+        let val = (self.0 >> 8usize) & 0xff;
+        val as u8
+    }
+    #[doc = "The command suffix bits following the address, if Mx_RFMT_SUFFIX_LEN is nonzero."]
+    #[inline(always)]
+    pub fn set_suffix(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize);
+    }
+}
+impl Default for M1rcmd {
+    #[inline(always)]
+    fn default() -> M1rcmd {
+        M1rcmd(0)
+    }
+}
+#[doc = "Read transfer format configuration for memory address window 1. Configure the bus width of each transfer phase individually, and configure the length or presence of the command prefix, command suffix and dummy/turnaround transfer phases. Only 24-bit addresses are supported. The reset value of the M1_RFMT register is configured to support a basic 03h serial read transfer with no additional configuration."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct M1rfmt(pub u32);
+impl M1rfmt {
+    #[doc = "The transfer width used for the command prefix, if any"]
+    #[inline(always)]
+    pub const fn prefix_width(&self) -> super::vals::M1rfmtPrefixWidth {
+        let val = (self.0 >> 0usize) & 0x03;
+        super::vals::M1rfmtPrefixWidth::from_bits(val as u8)
+    }
+    #[doc = "The transfer width used for the command prefix, if any"]
+    #[inline(always)]
+    pub fn set_prefix_width(&mut self, val: super::vals::M1rfmtPrefixWidth) {
+        self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize);
+    }
+    #[doc = "The transfer width used for the address. The address phase always transfers 24 bits in total."]
+    #[inline(always)]
+    pub const fn addr_width(&self) -> super::vals::M1rfmtAddrWidth {
+        let val = (self.0 >> 2usize) & 0x03;
+        super::vals::M1rfmtAddrWidth::from_bits(val as u8)
+    }
+    #[doc = "The transfer width used for the address. The address phase always transfers 24 bits in total."]
+    #[inline(always)]
+    pub fn set_addr_width(&mut self, val: super::vals::M1rfmtAddrWidth) {
+        self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize);
+    }
+    #[doc = "The width used for the post-address command suffix, if any"]
+    #[inline(always)]
+    pub const fn suffix_width(&self) -> super::vals::M1rfmtSuffixWidth {
+        let val = (self.0 >> 4usize) & 0x03;
+        super::vals::M1rfmtSuffixWidth::from_bits(val as u8)
+    }
+    #[doc = "The width used for the post-address command suffix, if any"]
+    #[inline(always)]
+    pub fn set_suffix_width(&mut self, val: super::vals::M1rfmtSuffixWidth) {
+        self.0 = (self.0 & !(0x03 << 4usize)) | (((val.to_bits() as u32) & 0x03) << 4usize);
+    }
+    #[doc = "The width used for the dummy phase, if any. If width is single, SD0/MOSI is held asserted low during the dummy phase, and SD1...SD3 are tristated. If width is dual/quad, all IOs are tristated during the dummy phase."]
+    #[inline(always)]
+    pub const fn dummy_width(&self) -> super::vals::M1rfmtDummyWidth {
+        let val = (self.0 >> 6usize) & 0x03;
+        super::vals::M1rfmtDummyWidth::from_bits(val as u8)
+    }
+    #[doc = "The width used for the dummy phase, if any. If width is single, SD0/MOSI is held asserted low during the dummy phase, and SD1...SD3 are tristated. If width is dual/quad, all IOs are tristated during the dummy phase."]
+    #[inline(always)]
+    pub fn set_dummy_width(&mut self, val: super::vals::M1rfmtDummyWidth) {
+        self.0 = (self.0 & !(0x03 << 6usize)) | (((val.to_bits() as u32) & 0x03) << 6usize);
+    }
+    #[doc = "The width used for the data transfer"]
+    #[inline(always)]
+    pub const fn data_width(&self) -> super::vals::M1rfmtDataWidth {
+        let val = (self.0 >> 8usize) & 0x03;
+        super::vals::M1rfmtDataWidth::from_bits(val as u8)
+    }
+    #[doc = "The width used for the data transfer"]
+    #[inline(always)]
+    pub fn set_data_width(&mut self, val: super::vals::M1rfmtDataWidth) {
+        self.0 = (self.0 & !(0x03 << 8usize)) | (((val.to_bits() as u32) & 0x03) << 8usize);
+    }
+    #[doc = "Length of command prefix, in units of 8 bits. (i.e. 2 cycles for quad width, 4 for dual, 8 for single)"]
+    #[inline(always)]
+    pub const fn prefix_len(&self) -> super::vals::M1rfmtPrefixLen {
+        let val = (self.0 >> 12usize) & 0x01;
+        super::vals::M1rfmtPrefixLen::from_bits(val as u8)
+    }
+    #[doc = "Length of command prefix, in units of 8 bits. (i.e. 2 cycles for quad width, 4 for dual, 8 for single)"]
+    #[inline(always)]
+    pub fn set_prefix_len(&mut self, val: super::vals::M1rfmtPrefixLen) {
+        self.0 = (self.0 & !(0x01 << 12usize)) | (((val.to_bits() as u32) & 0x01) << 12usize);
+    }
+    #[doc = "Length of post-address command suffix, in units of 4 bits. (i.e. 1 cycle for quad width, 2 for dual, 4 for single) Only values of 0 and 8 bits are supported."]
+    #[inline(always)]
+    pub const fn suffix_len(&self) -> super::vals::M1rfmtSuffixLen {
+        let val = (self.0 >> 14usize) & 0x03;
+        super::vals::M1rfmtSuffixLen::from_bits(val as u8)
+    }
+    #[doc = "Length of post-address command suffix, in units of 4 bits. (i.e. 1 cycle for quad width, 2 for dual, 4 for single) Only values of 0 and 8 bits are supported."]
+    #[inline(always)]
+    pub fn set_suffix_len(&mut self, val: super::vals::M1rfmtSuffixLen) {
+        self.0 = (self.0 & !(0x03 << 14usize)) | (((val.to_bits() as u32) & 0x03) << 14usize);
+    }
+    #[doc = "Length of dummy phase between command suffix and data phase, in units of 4 bits. (i.e. 1 cycle for quad width, 2 for dual, 4 for single)"]
+    #[inline(always)]
+    pub const fn dummy_len(&self) -> super::vals::M1rfmtDummyLen {
+        let val = (self.0 >> 16usize) & 0x07;
+        super::vals::M1rfmtDummyLen::from_bits(val as u8)
+    }
+    #[doc = "Length of dummy phase between command suffix and data phase, in units of 4 bits. (i.e. 1 cycle for quad width, 2 for dual, 4 for single)"]
+    #[inline(always)]
+    pub fn set_dummy_len(&mut self, val: super::vals::M1rfmtDummyLen) {
+        self.0 = (self.0 & !(0x07 << 16usize)) | (((val.to_bits() as u32) & 0x07) << 16usize);
+    }
+    #[doc = "Enable double transfer rate (DTR) for read commands: address, suffix and read data phases are active on both edges of SCK. SDO data is launched centre-aligned on each SCK edge, and SDI data is captured on the SCK edge that follows its launch. DTR is implemented by halving the clock rate; SCK has a period of 2 x CLK_DIV throughout the transfer. The prefix and dummy phases are still single transfer rate. If the suffix is quad-width, it must be 0 or 8 bits in length, to ensure an even number of SCK edges."]
+    #[inline(always)]
+    pub const fn dtr(&self) -> bool {
+        let val = (self.0 >> 28usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Enable double transfer rate (DTR) for read commands: address, suffix and read data phases are active on both edges of SCK. SDO data is launched centre-aligned on each SCK edge, and SDI data is captured on the SCK edge that follows its launch. DTR is implemented by halving the clock rate; SCK has a period of 2 x CLK_DIV throughout the transfer. The prefix and dummy phases are still single transfer rate. If the suffix is quad-width, it must be 0 or 8 bits in length, to ensure an even number of SCK edges."]
+    #[inline(always)]
+    pub fn set_dtr(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 28usize)) | (((val as u32) & 0x01) << 28usize);
+    }
+}
+impl Default for M1rfmt {
+    #[inline(always)]
+    fn default() -> M1rfmt {
+        M1rfmt(0)
+    }
+}
+#[doc = "Timing configuration register for memory address window 1."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct M1timing(pub u32);
+impl M1timing {
+    #[doc = "Clock divisor. Odd and even divisors are supported. Defines the SCK clock period in units of 1 system clock cycle. Divisors 1..255 are encoded directly, and a divisor of 256 is encoded with a value of CLKDIV=0. The clock divisor can be changed on-the-fly, even when the QMI is currently accessing memory in this address window. All other parameters must only be changed when the QMI is idle. If software is increasing CLKDIV in anticipation of an increase in the system clock frequency, a dummy access to either memory window (and appropriate processor barriers/fences) must be inserted after the Mx_TIMING write to ensure the SCK divisor change is in effect _before_ the system clock is changed."]
+    #[inline(always)]
+    pub const fn clkdiv(&self) -> u8 {
+        let val = (self.0 >> 0usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Clock divisor. Odd and even divisors are supported. Defines the SCK clock period in units of 1 system clock cycle. Divisors 1..255 are encoded directly, and a divisor of 256 is encoded with a value of CLKDIV=0. The clock divisor can be changed on-the-fly, even when the QMI is currently accessing memory in this address window. All other parameters must only be changed when the QMI is idle. If software is increasing CLKDIV in anticipation of an increase in the system clock frequency, a dummy access to either memory window (and appropriate processor barriers/fences) must be inserted after the Mx_TIMING write to ensure the SCK divisor change is in effect _before_ the system clock is changed."]
+    #[inline(always)]
+    pub fn set_clkdiv(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize);
+    }
+    #[doc = "Delay the read data sample timing, in units of one half of a system clock cycle. (Not necessarily half of an SCK cycle.) An RXDELAY of 0 means the sample is captured at the SDI input registers simultaneously with the rising edge of SCK launched from the SCK output register. At higher SCK frequencies, RXDELAY may need to be increased to account for the round trip delay of the pads, and the clock-to-Q delay of the QSPI memory device."]
+    #[inline(always)]
+    pub const fn rxdelay(&self) -> u8 {
+        let val = (self.0 >> 8usize) & 0x07;
+        val as u8
+    }
+    #[doc = "Delay the read data sample timing, in units of one half of a system clock cycle. (Not necessarily half of an SCK cycle.) An RXDELAY of 0 means the sample is captured at the SDI input registers simultaneously with the rising edge of SCK launched from the SCK output register. At higher SCK frequencies, RXDELAY may need to be increased to account for the round trip delay of the pads, and the clock-to-Q delay of the QSPI memory device."]
+    #[inline(always)]
+    pub fn set_rxdelay(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x07 << 8usize)) | (((val as u32) & 0x07) << 8usize);
+    }
+    #[doc = "After this window's chip select is deasserted, it remains deasserted for half an SCK cycle (rounded up to an integer number of system clock cycles), plus MIN_DESELECT additional system clock cycles, before the QMI reasserts either chip select pin. Nonzero values may be required for PSRAM devices which enforce a longer minimum CS deselect time, so that they can perform internal DRAM refresh cycles whilst deselected."]
+    #[inline(always)]
+    pub const fn min_deselect(&self) -> u8 {
+        let val = (self.0 >> 12usize) & 0x1f;
+        val as u8
+    }
+    #[doc = "After this window's chip select is deasserted, it remains deasserted for half an SCK cycle (rounded up to an integer number of system clock cycles), plus MIN_DESELECT additional system clock cycles, before the QMI reasserts either chip select pin. Nonzero values may be required for PSRAM devices which enforce a longer minimum CS deselect time, so that they can perform internal DRAM refresh cycles whilst deselected."]
+    #[inline(always)]
+    pub fn set_min_deselect(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x1f << 12usize)) | (((val as u32) & 0x1f) << 12usize);
+    }
+    #[doc = "Enforce a maximum assertion duration for this window's chip select, in units of 64 system clock cycles. If 0, the QMI is permitted to keep the chip select asserted indefinitely when servicing sequential memory accesses (see COOLDOWN). This feature is required to meet timing constraints of PSRAM devices, which specify a maximum chip select assertion so they can perform DRAM refresh cycles. See also MIN_DESELECT, which can enforce a minimum deselect time. If a memory access is in progress at the time MAX_SELECT is reached, the QMI will wait for the access to complete before deasserting the chip select. This additional time must be accounted for to calculate a safe MAX_SELECT value. In the worst case, this may be a fully-formed serial transfer, including command prefix and address, with a data payload as large as one cache line."]
+    #[inline(always)]
+    pub const fn max_select(&self) -> u8 {
+        let val = (self.0 >> 17usize) & 0x3f;
+        val as u8
+    }
+    #[doc = "Enforce a maximum assertion duration for this window's chip select, in units of 64 system clock cycles. If 0, the QMI is permitted to keep the chip select asserted indefinitely when servicing sequential memory accesses (see COOLDOWN). This feature is required to meet timing constraints of PSRAM devices, which specify a maximum chip select assertion so they can perform DRAM refresh cycles. See also MIN_DESELECT, which can enforce a minimum deselect time. If a memory access is in progress at the time MAX_SELECT is reached, the QMI will wait for the access to complete before deasserting the chip select. This additional time must be accounted for to calculate a safe MAX_SELECT value. In the worst case, this may be a fully-formed serial transfer, including command prefix and address, with a data payload as large as one cache line."]
+    #[inline(always)]
+    pub fn set_max_select(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x3f << 17usize)) | (((val as u32) & 0x3f) << 17usize);
+    }
+    #[doc = "Add up to three additional system clock cycles of active hold between the last falling edge of SCK and the deassertion of this window's chip select. The default hold time is one system clock cycle. Note that flash datasheets usually give chip select active hold time from the last *rising* edge of SCK, and so even zero hold from the last falling edge would be safe. Note that this is a minimum hold time guaranteed by the QMI: the actual chip select active hold may be slightly longer for read transfers with low clock divisors and/or high sample delays. Specifically, if the point two cycles after the last RX data sample is later than the last SCK falling edge, then the hold time is measured from *this* point. Note also that, in case the final SCK pulse is masked to save energy (true for non-DTR reads when COOLDOWN is disabled or PAGE_BREAK is reached), all of QMI's timing logic behaves as though the clock pulse were still present. The SELECT_HOLD time is applied from the point where the last SCK falling edge would be if the clock pulse were not masked."]
+    #[inline(always)]
+    pub const fn select_hold(&self) -> u8 {
+        let val = (self.0 >> 23usize) & 0x03;
+        val as u8
+    }
+    #[doc = "Add up to three additional system clock cycles of active hold between the last falling edge of SCK and the deassertion of this window's chip select. The default hold time is one system clock cycle. Note that flash datasheets usually give chip select active hold time from the last *rising* edge of SCK, and so even zero hold from the last falling edge would be safe. Note that this is a minimum hold time guaranteed by the QMI: the actual chip select active hold may be slightly longer for read transfers with low clock divisors and/or high sample delays. Specifically, if the point two cycles after the last RX data sample is later than the last SCK falling edge, then the hold time is measured from *this* point. Note also that, in case the final SCK pulse is masked to save energy (true for non-DTR reads when COOLDOWN is disabled or PAGE_BREAK is reached), all of QMI's timing logic behaves as though the clock pulse were still present. The SELECT_HOLD time is applied from the point where the last SCK falling edge would be if the clock pulse were not masked."]
+    #[inline(always)]
+    pub fn set_select_hold(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x03 << 23usize)) | (((val as u32) & 0x03) << 23usize);
+    }
+    #[doc = "Add up to one additional system clock cycle of setup between chip select assertion and the first rising edge of SCK. The default setup time is one half SCK period, which is usually sufficient except for very high SCK frequencies with some flash devices."]
+    #[inline(always)]
+    pub const fn select_setup(&self) -> bool {
+        let val = (self.0 >> 25usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Add up to one additional system clock cycle of setup between chip select assertion and the first rising edge of SCK. The default setup time is one half SCK period, which is usually sufficient except for very high SCK frequencies with some flash devices."]
+    #[inline(always)]
+    pub fn set_select_setup(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 25usize)) | (((val as u32) & 0x01) << 25usize);
+    }
+    #[doc = "When page break is enabled, chip select will automatically deassert when crossing certain power-of-2-aligned address boundaries. The next access will always begin a new read/write SPI burst, even if the address of the next access follows in sequence with the last access before the page boundary. Some flash and PSRAM devices forbid crossing page boundaries with a single read/write transfer, or restrict the operating frequency for transfers that do cross page a boundary. This option allows the QMI to safely support those devices. This field has no effect when COOLDOWN is disabled."]
+    #[inline(always)]
+    pub const fn pagebreak(&self) -> super::vals::M1timingPagebreak {
+        let val = (self.0 >> 28usize) & 0x03;
+        super::vals::M1timingPagebreak::from_bits(val as u8)
+    }
+    #[doc = "When page break is enabled, chip select will automatically deassert when crossing certain power-of-2-aligned address boundaries. The next access will always begin a new read/write SPI burst, even if the address of the next access follows in sequence with the last access before the page boundary. Some flash and PSRAM devices forbid crossing page boundaries with a single read/write transfer, or restrict the operating frequency for transfers that do cross page a boundary. This option allows the QMI to safely support those devices. This field has no effect when COOLDOWN is disabled."]
+    #[inline(always)]
+    pub fn set_pagebreak(&mut self, val: super::vals::M1timingPagebreak) {
+        self.0 = (self.0 & !(0x03 << 28usize)) | (((val.to_bits() as u32) & 0x03) << 28usize);
+    }
+    #[doc = "Chip select cooldown period. When a memory transfer finishes, the chip select remains asserted for 64 x COOLDOWN system clock cycles, plus half an SCK clock period (rounded up for odd SCK divisors). After this cooldown expires, the chip select is always deasserted to save power. If the next memory access arrives within the cooldown period, the QMI may be able to append more SCK cycles to the currently ongoing SPI transfer, rather than starting a new transfer. This reduces access latency and increases bus throughput. Specifically, the next access must be in the same direction (read/write), access the same memory window (chip select 0/1), and follow sequentially the address of the last transfer. If any of these are false, the new access will first deassert the chip select, then begin a new transfer. If COOLDOWN is 0, the address alignment configured by PAGEBREAK has been reached, or the total chip select assertion limit MAX_SELECT has been reached, the cooldown period is skipped, and the chip select will always be deasserted one half SCK period after the transfer finishes."]
+    #[inline(always)]
+    pub const fn cooldown(&self) -> u8 {
+        let val = (self.0 >> 30usize) & 0x03;
+        val as u8
+    }
+    #[doc = "Chip select cooldown period. When a memory transfer finishes, the chip select remains asserted for 64 x COOLDOWN system clock cycles, plus half an SCK clock period (rounded up for odd SCK divisors). After this cooldown expires, the chip select is always deasserted to save power. If the next memory access arrives within the cooldown period, the QMI may be able to append more SCK cycles to the currently ongoing SPI transfer, rather than starting a new transfer. This reduces access latency and increases bus throughput. Specifically, the next access must be in the same direction (read/write), access the same memory window (chip select 0/1), and follow sequentially the address of the last transfer. If any of these are false, the new access will first deassert the chip select, then begin a new transfer. If COOLDOWN is 0, the address alignment configured by PAGEBREAK has been reached, or the total chip select assertion limit MAX_SELECT has been reached, the cooldown period is skipped, and the chip select will always be deasserted one half SCK period after the transfer finishes."]
+    #[inline(always)]
+    pub fn set_cooldown(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x03 << 30usize)) | (((val as u32) & 0x03) << 30usize);
+    }
+}
+impl Default for M1timing {
+    #[inline(always)]
+    fn default() -> M1timing {
+        M1timing(0)
+    }
+}
+#[doc = "Command constants used for writes to memory address window 1. The reset value of the M1_WCMD register is configured to support a basic 02h serial write transfer with no additional configuration."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct M1wcmd(pub u32);
+impl M1wcmd {
+    #[doc = "The command prefix bits to prepend on each new transfer, if Mx_WFMT_PREFIX_LEN is nonzero."]
+    #[inline(always)]
+    pub const fn prefix(&self) -> u8 {
+        let val = (self.0 >> 0usize) & 0xff;
+        val as u8
+    }
+    #[doc = "The command prefix bits to prepend on each new transfer, if Mx_WFMT_PREFIX_LEN is nonzero."]
+    #[inline(always)]
+    pub fn set_prefix(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize);
+    }
+    #[doc = "The command suffix bits following the address, if Mx_WFMT_SUFFIX_LEN is nonzero."]
+    #[inline(always)]
+    pub const fn suffix(&self) -> u8 {
+        let val = (self.0 >> 8usize) & 0xff;
+        val as u8
+    }
+    #[doc = "The command suffix bits following the address, if Mx_WFMT_SUFFIX_LEN is nonzero."]
+    #[inline(always)]
+    pub fn set_suffix(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize);
+    }
+}
+impl Default for M1wcmd {
+    #[inline(always)]
+    fn default() -> M1wcmd {
+        M1wcmd(0)
+    }
+}
+#[doc = "Write transfer format configuration for memory address window 1. Configure the bus width of each transfer phase individually, and configure the length or presence of the command prefix, command suffix and dummy/turnaround transfer phases. Only 24-bit addresses are supported. The reset value of the M1_WFMT register is configured to support a basic 02h serial write transfer. However, writes to this window must first be enabled via the XIP_CTRL_WRITABLE_M1 bit, as XIP memory is read-only by default."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct M1wfmt(pub u32);
+impl M1wfmt {
+    #[doc = "The transfer width used for the command prefix, if any"]
+    #[inline(always)]
+    pub const fn prefix_width(&self) -> super::vals::M1wfmtPrefixWidth {
+        let val = (self.0 >> 0usize) & 0x03;
+        super::vals::M1wfmtPrefixWidth::from_bits(val as u8)
+    }
+    #[doc = "The transfer width used for the command prefix, if any"]
+    #[inline(always)]
+    pub fn set_prefix_width(&mut self, val: super::vals::M1wfmtPrefixWidth) {
+        self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize);
+    }
+    #[doc = "The transfer width used for the address. The address phase always transfers 24 bits in total."]
+    #[inline(always)]
+    pub const fn addr_width(&self) -> super::vals::M1wfmtAddrWidth {
+        let val = (self.0 >> 2usize) & 0x03;
+        super::vals::M1wfmtAddrWidth::from_bits(val as u8)
+    }
+    #[doc = "The transfer width used for the address. The address phase always transfers 24 bits in total."]
+    #[inline(always)]
+    pub fn set_addr_width(&mut self, val: super::vals::M1wfmtAddrWidth) {
+        self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize);
+    }
+    #[doc = "The width used for the post-address command suffix, if any"]
+    #[inline(always)]
+    pub const fn suffix_width(&self) -> super::vals::M1wfmtSuffixWidth {
+        let val = (self.0 >> 4usize) & 0x03;
+        super::vals::M1wfmtSuffixWidth::from_bits(val as u8)
+    }
+    #[doc = "The width used for the post-address command suffix, if any"]
+    #[inline(always)]
+    pub fn set_suffix_width(&mut self, val: super::vals::M1wfmtSuffixWidth) {
+        self.0 = (self.0 & !(0x03 << 4usize)) | (((val.to_bits() as u32) & 0x03) << 4usize);
+    }
+    #[doc = "The width used for the dummy phase, if any. If width is single, SD0/MOSI is held asserted low during the dummy phase, and SD1...SD3 are tristated. If width is dual/quad, all IOs are tristated during the dummy phase."]
+    #[inline(always)]
+    pub const fn dummy_width(&self) -> super::vals::M1wfmtDummyWidth {
+        let val = (self.0 >> 6usize) & 0x03;
+        super::vals::M1wfmtDummyWidth::from_bits(val as u8)
+    }
+    #[doc = "The width used for the dummy phase, if any. If width is single, SD0/MOSI is held asserted low during the dummy phase, and SD1...SD3 are tristated. If width is dual/quad, all IOs are tristated during the dummy phase."]
+    #[inline(always)]
+    pub fn set_dummy_width(&mut self, val: super::vals::M1wfmtDummyWidth) {
+        self.0 = (self.0 & !(0x03 << 6usize)) | (((val.to_bits() as u32) & 0x03) << 6usize);
+    }
+    #[doc = "The width used for the data transfer"]
+    #[inline(always)]
+    pub const fn data_width(&self) -> super::vals::M1wfmtDataWidth {
+        let val = (self.0 >> 8usize) & 0x03;
+        super::vals::M1wfmtDataWidth::from_bits(val as u8)
+    }
+    #[doc = "The width used for the data transfer"]
+    #[inline(always)]
+    pub fn set_data_width(&mut self, val: super::vals::M1wfmtDataWidth) {
+        self.0 = (self.0 & !(0x03 << 8usize)) | (((val.to_bits() as u32) & 0x03) << 8usize);
+    }
+    #[doc = "Length of command prefix, in units of 8 bits. (i.e. 2 cycles for quad width, 4 for dual, 8 for single)"]
+    #[inline(always)]
+    pub const fn prefix_len(&self) -> super::vals::M1wfmtPrefixLen {
+        let val = (self.0 >> 12usize) & 0x01;
+        super::vals::M1wfmtPrefixLen::from_bits(val as u8)
+    }
+    #[doc = "Length of command prefix, in units of 8 bits. (i.e. 2 cycles for quad width, 4 for dual, 8 for single)"]
+    #[inline(always)]
+    pub fn set_prefix_len(&mut self, val: super::vals::M1wfmtPrefixLen) {
+        self.0 = (self.0 & !(0x01 << 12usize)) | (((val.to_bits() as u32) & 0x01) << 12usize);
+    }
+    #[doc = "Length of post-address command suffix, in units of 4 bits. (i.e. 1 cycle for quad width, 2 for dual, 4 for single) Only values of 0 and 8 bits are supported."]
+    #[inline(always)]
+    pub const fn suffix_len(&self) -> super::vals::M1wfmtSuffixLen {
+        let val = (self.0 >> 14usize) & 0x03;
+        super::vals::M1wfmtSuffixLen::from_bits(val as u8)
+    }
+    #[doc = "Length of post-address command suffix, in units of 4 bits. (i.e. 1 cycle for quad width, 2 for dual, 4 for single) Only values of 0 and 8 bits are supported."]
+    #[inline(always)]
+    pub fn set_suffix_len(&mut self, val: super::vals::M1wfmtSuffixLen) {
+        self.0 = (self.0 & !(0x03 << 14usize)) | (((val.to_bits() as u32) & 0x03) << 14usize);
+    }
+    #[doc = "Length of dummy phase between command suffix and data phase, in units of 4 bits. (i.e. 1 cycle for quad width, 2 for dual, 4 for single)"]
+    #[inline(always)]
+    pub const fn dummy_len(&self) -> super::vals::M1wfmtDummyLen {
+        let val = (self.0 >> 16usize) & 0x07;
+        super::vals::M1wfmtDummyLen::from_bits(val as u8)
+    }
+    #[doc = "Length of dummy phase between command suffix and data phase, in units of 4 bits. (i.e. 1 cycle for quad width, 2 for dual, 4 for single)"]
+    #[inline(always)]
+    pub fn set_dummy_len(&mut self, val: super::vals::M1wfmtDummyLen) {
+        self.0 = (self.0 & !(0x07 << 16usize)) | (((val.to_bits() as u32) & 0x07) << 16usize);
+    }
+    #[doc = "Enable double transfer rate (DTR) for write commands: address, suffix and write data phases are active on both edges of SCK. SDO data is launched centre-aligned on each SCK edge, and SDI data is captured on the SCK edge that follows its launch. DTR is implemented by halving the clock rate; SCK has a period of 2 x CLK_DIV throughout the transfer. The prefix and dummy phases are still single transfer rate. If the suffix is quad-width, it must be 0 or 8 bits in length, to ensure an even number of SCK edges."]
+    #[inline(always)]
+    pub const fn dtr(&self) -> bool {
+        let val = (self.0 >> 28usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Enable double transfer rate (DTR) for write commands: address, suffix and write data phases are active on both edges of SCK. SDO data is launched centre-aligned on each SCK edge, and SDI data is captured on the SCK edge that follows its launch. DTR is implemented by halving the clock rate; SCK has a period of 2 x CLK_DIV throughout the transfer. The prefix and dummy phases are still single transfer rate. If the suffix is quad-width, it must be 0 or 8 bits in length, to ensure an even number of SCK edges."]
+    #[inline(always)]
+    pub fn set_dtr(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 28usize)) | (((val as u32) & 0x01) << 28usize);
+    }
+}
+impl Default for M1wfmt {
+    #[inline(always)]
+    fn default() -> M1wfmt {
+        M1wfmt(0)
+    }
+}
diff --git a/src/rp2350/qmi/vals.rs b/src/rp2350/qmi/vals.rs
new file mode 100644
index 00000000..937d94a4
--- /dev/null
+++ b/src/rp2350/qmi/vals.rs
@@ -0,0 +1,1177 @@
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Iwidth {
+    #[doc = "Single width"]
+    S = 0,
+    #[doc = "Dual width"]
+    D = 0x01,
+    #[doc = "Quad width"]
+    Q = 0x02,
+    _RESERVED_3 = 0x03,
+}
+impl Iwidth {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Iwidth {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Iwidth {
+    #[inline(always)]
+    fn from(val: u8) -> Iwidth {
+        Iwidth::from_bits(val)
+    }
+}
+impl From<Iwidth> for u8 {
+    #[inline(always)]
+    fn from(val: Iwidth) -> u8 {
+        Iwidth::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum M0rfmtAddrWidth {
+    #[doc = "Single width"]
+    S = 0,
+    #[doc = "Dual width"]
+    D = 0x01,
+    #[doc = "Quad width"]
+    Q = 0x02,
+    _RESERVED_3 = 0x03,
+}
+impl M0rfmtAddrWidth {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> M0rfmtAddrWidth {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for M0rfmtAddrWidth {
+    #[inline(always)]
+    fn from(val: u8) -> M0rfmtAddrWidth {
+        M0rfmtAddrWidth::from_bits(val)
+    }
+}
+impl From<M0rfmtAddrWidth> for u8 {
+    #[inline(always)]
+    fn from(val: M0rfmtAddrWidth) -> u8 {
+        M0rfmtAddrWidth::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum M0rfmtDataWidth {
+    #[doc = "Single width"]
+    S = 0,
+    #[doc = "Dual width"]
+    D = 0x01,
+    #[doc = "Quad width"]
+    Q = 0x02,
+    _RESERVED_3 = 0x03,
+}
+impl M0rfmtDataWidth {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> M0rfmtDataWidth {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for M0rfmtDataWidth {
+    #[inline(always)]
+    fn from(val: u8) -> M0rfmtDataWidth {
+        M0rfmtDataWidth::from_bits(val)
+    }
+}
+impl From<M0rfmtDataWidth> for u8 {
+    #[inline(always)]
+    fn from(val: M0rfmtDataWidth) -> u8 {
+        M0rfmtDataWidth::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum M0rfmtDummyLen {
+    #[doc = "No dummy phase"]
+    NONE = 0,
+    #[doc = "4 dummy bits"]
+    _4 = 0x01,
+    #[doc = "8 dummy bits"]
+    _8 = 0x02,
+    #[doc = "12 dummy bits"]
+    _12 = 0x03,
+    #[doc = "16 dummy bits"]
+    _16 = 0x04,
+    #[doc = "20 dummy bits"]
+    _20 = 0x05,
+    #[doc = "24 dummy bits"]
+    _24 = 0x06,
+    #[doc = "28 dummy bits"]
+    _28 = 0x07,
+}
+impl M0rfmtDummyLen {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> M0rfmtDummyLen {
+        unsafe { core::mem::transmute(val & 0x07) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for M0rfmtDummyLen {
+    #[inline(always)]
+    fn from(val: u8) -> M0rfmtDummyLen {
+        M0rfmtDummyLen::from_bits(val)
+    }
+}
+impl From<M0rfmtDummyLen> for u8 {
+    #[inline(always)]
+    fn from(val: M0rfmtDummyLen) -> u8 {
+        M0rfmtDummyLen::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum M0rfmtDummyWidth {
+    #[doc = "Single width"]
+    S = 0,
+    #[doc = "Dual width"]
+    D = 0x01,
+    #[doc = "Quad width"]
+    Q = 0x02,
+    _RESERVED_3 = 0x03,
+}
+impl M0rfmtDummyWidth {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> M0rfmtDummyWidth {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for M0rfmtDummyWidth {
+    #[inline(always)]
+    fn from(val: u8) -> M0rfmtDummyWidth {
+        M0rfmtDummyWidth::from_bits(val)
+    }
+}
+impl From<M0rfmtDummyWidth> for u8 {
+    #[inline(always)]
+    fn from(val: M0rfmtDummyWidth) -> u8 {
+        M0rfmtDummyWidth::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum M0rfmtPrefixLen {
+    #[doc = "No prefix"]
+    NONE = 0,
+    #[doc = "8-bit prefix"]
+    _8 = 0x01,
+}
+impl M0rfmtPrefixLen {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> M0rfmtPrefixLen {
+        unsafe { core::mem::transmute(val & 0x01) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for M0rfmtPrefixLen {
+    #[inline(always)]
+    fn from(val: u8) -> M0rfmtPrefixLen {
+        M0rfmtPrefixLen::from_bits(val)
+    }
+}
+impl From<M0rfmtPrefixLen> for u8 {
+    #[inline(always)]
+    fn from(val: M0rfmtPrefixLen) -> u8 {
+        M0rfmtPrefixLen::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum M0rfmtPrefixWidth {
+    #[doc = "Single width"]
+    S = 0,
+    #[doc = "Dual width"]
+    D = 0x01,
+    #[doc = "Quad width"]
+    Q = 0x02,
+    _RESERVED_3 = 0x03,
+}
+impl M0rfmtPrefixWidth {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> M0rfmtPrefixWidth {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for M0rfmtPrefixWidth {
+    #[inline(always)]
+    fn from(val: u8) -> M0rfmtPrefixWidth {
+        M0rfmtPrefixWidth::from_bits(val)
+    }
+}
+impl From<M0rfmtPrefixWidth> for u8 {
+    #[inline(always)]
+    fn from(val: M0rfmtPrefixWidth) -> u8 {
+        M0rfmtPrefixWidth::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum M0rfmtSuffixLen {
+    #[doc = "No suffix"]
+    NONE = 0,
+    _RESERVED_1 = 0x01,
+    #[doc = "8-bit suffix"]
+    _8 = 0x02,
+    _RESERVED_3 = 0x03,
+}
+impl M0rfmtSuffixLen {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> M0rfmtSuffixLen {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for M0rfmtSuffixLen {
+    #[inline(always)]
+    fn from(val: u8) -> M0rfmtSuffixLen {
+        M0rfmtSuffixLen::from_bits(val)
+    }
+}
+impl From<M0rfmtSuffixLen> for u8 {
+    #[inline(always)]
+    fn from(val: M0rfmtSuffixLen) -> u8 {
+        M0rfmtSuffixLen::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum M0rfmtSuffixWidth {
+    #[doc = "Single width"]
+    S = 0,
+    #[doc = "Dual width"]
+    D = 0x01,
+    #[doc = "Quad width"]
+    Q = 0x02,
+    _RESERVED_3 = 0x03,
+}
+impl M0rfmtSuffixWidth {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> M0rfmtSuffixWidth {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for M0rfmtSuffixWidth {
+    #[inline(always)]
+    fn from(val: u8) -> M0rfmtSuffixWidth {
+        M0rfmtSuffixWidth::from_bits(val)
+    }
+}
+impl From<M0rfmtSuffixWidth> for u8 {
+    #[inline(always)]
+    fn from(val: M0rfmtSuffixWidth) -> u8 {
+        M0rfmtSuffixWidth::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum M0timingPagebreak {
+    #[doc = "No page boundary is enforced"]
+    NONE = 0,
+    #[doc = "Break bursts crossing a 256-byte page boundary"]
+    _256 = 0x01,
+    #[doc = "Break bursts crossing a 1024-byte quad-page boundary"]
+    _1024 = 0x02,
+    #[doc = "Break bursts crossing a 4096-byte sector boundary"]
+    _4096 = 0x03,
+}
+impl M0timingPagebreak {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> M0timingPagebreak {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for M0timingPagebreak {
+    #[inline(always)]
+    fn from(val: u8) -> M0timingPagebreak {
+        M0timingPagebreak::from_bits(val)
+    }
+}
+impl From<M0timingPagebreak> for u8 {
+    #[inline(always)]
+    fn from(val: M0timingPagebreak) -> u8 {
+        M0timingPagebreak::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum M0wfmtAddrWidth {
+    #[doc = "Single width"]
+    S = 0,
+    #[doc = "Dual width"]
+    D = 0x01,
+    #[doc = "Quad width"]
+    Q = 0x02,
+    _RESERVED_3 = 0x03,
+}
+impl M0wfmtAddrWidth {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> M0wfmtAddrWidth {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for M0wfmtAddrWidth {
+    #[inline(always)]
+    fn from(val: u8) -> M0wfmtAddrWidth {
+        M0wfmtAddrWidth::from_bits(val)
+    }
+}
+impl From<M0wfmtAddrWidth> for u8 {
+    #[inline(always)]
+    fn from(val: M0wfmtAddrWidth) -> u8 {
+        M0wfmtAddrWidth::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum M0wfmtDataWidth {
+    #[doc = "Single width"]
+    S = 0,
+    #[doc = "Dual width"]
+    D = 0x01,
+    #[doc = "Quad width"]
+    Q = 0x02,
+    _RESERVED_3 = 0x03,
+}
+impl M0wfmtDataWidth {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> M0wfmtDataWidth {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for M0wfmtDataWidth {
+    #[inline(always)]
+    fn from(val: u8) -> M0wfmtDataWidth {
+        M0wfmtDataWidth::from_bits(val)
+    }
+}
+impl From<M0wfmtDataWidth> for u8 {
+    #[inline(always)]
+    fn from(val: M0wfmtDataWidth) -> u8 {
+        M0wfmtDataWidth::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum M0wfmtDummyLen {
+    #[doc = "No dummy phase"]
+    NONE = 0,
+    #[doc = "4 dummy bits"]
+    _4 = 0x01,
+    #[doc = "8 dummy bits"]
+    _8 = 0x02,
+    #[doc = "12 dummy bits"]
+    _12 = 0x03,
+    #[doc = "16 dummy bits"]
+    _16 = 0x04,
+    #[doc = "20 dummy bits"]
+    _20 = 0x05,
+    #[doc = "24 dummy bits"]
+    _24 = 0x06,
+    #[doc = "28 dummy bits"]
+    _28 = 0x07,
+}
+impl M0wfmtDummyLen {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> M0wfmtDummyLen {
+        unsafe { core::mem::transmute(val & 0x07) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for M0wfmtDummyLen {
+    #[inline(always)]
+    fn from(val: u8) -> M0wfmtDummyLen {
+        M0wfmtDummyLen::from_bits(val)
+    }
+}
+impl From<M0wfmtDummyLen> for u8 {
+    #[inline(always)]
+    fn from(val: M0wfmtDummyLen) -> u8 {
+        M0wfmtDummyLen::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum M0wfmtDummyWidth {
+    #[doc = "Single width"]
+    S = 0,
+    #[doc = "Dual width"]
+    D = 0x01,
+    #[doc = "Quad width"]
+    Q = 0x02,
+    _RESERVED_3 = 0x03,
+}
+impl M0wfmtDummyWidth {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> M0wfmtDummyWidth {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for M0wfmtDummyWidth {
+    #[inline(always)]
+    fn from(val: u8) -> M0wfmtDummyWidth {
+        M0wfmtDummyWidth::from_bits(val)
+    }
+}
+impl From<M0wfmtDummyWidth> for u8 {
+    #[inline(always)]
+    fn from(val: M0wfmtDummyWidth) -> u8 {
+        M0wfmtDummyWidth::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum M0wfmtPrefixLen {
+    #[doc = "No prefix"]
+    NONE = 0,
+    #[doc = "8-bit prefix"]
+    _8 = 0x01,
+}
+impl M0wfmtPrefixLen {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> M0wfmtPrefixLen {
+        unsafe { core::mem::transmute(val & 0x01) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for M0wfmtPrefixLen {
+    #[inline(always)]
+    fn from(val: u8) -> M0wfmtPrefixLen {
+        M0wfmtPrefixLen::from_bits(val)
+    }
+}
+impl From<M0wfmtPrefixLen> for u8 {
+    #[inline(always)]
+    fn from(val: M0wfmtPrefixLen) -> u8 {
+        M0wfmtPrefixLen::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum M0wfmtPrefixWidth {
+    #[doc = "Single width"]
+    S = 0,
+    #[doc = "Dual width"]
+    D = 0x01,
+    #[doc = "Quad width"]
+    Q = 0x02,
+    _RESERVED_3 = 0x03,
+}
+impl M0wfmtPrefixWidth {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> M0wfmtPrefixWidth {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for M0wfmtPrefixWidth {
+    #[inline(always)]
+    fn from(val: u8) -> M0wfmtPrefixWidth {
+        M0wfmtPrefixWidth::from_bits(val)
+    }
+}
+impl From<M0wfmtPrefixWidth> for u8 {
+    #[inline(always)]
+    fn from(val: M0wfmtPrefixWidth) -> u8 {
+        M0wfmtPrefixWidth::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum M0wfmtSuffixLen {
+    #[doc = "No suffix"]
+    NONE = 0,
+    _RESERVED_1 = 0x01,
+    #[doc = "8-bit suffix"]
+    _8 = 0x02,
+    _RESERVED_3 = 0x03,
+}
+impl M0wfmtSuffixLen {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> M0wfmtSuffixLen {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for M0wfmtSuffixLen {
+    #[inline(always)]
+    fn from(val: u8) -> M0wfmtSuffixLen {
+        M0wfmtSuffixLen::from_bits(val)
+    }
+}
+impl From<M0wfmtSuffixLen> for u8 {
+    #[inline(always)]
+    fn from(val: M0wfmtSuffixLen) -> u8 {
+        M0wfmtSuffixLen::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum M0wfmtSuffixWidth {
+    #[doc = "Single width"]
+    S = 0,
+    #[doc = "Dual width"]
+    D = 0x01,
+    #[doc = "Quad width"]
+    Q = 0x02,
+    _RESERVED_3 = 0x03,
+}
+impl M0wfmtSuffixWidth {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> M0wfmtSuffixWidth {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for M0wfmtSuffixWidth {
+    #[inline(always)]
+    fn from(val: u8) -> M0wfmtSuffixWidth {
+        M0wfmtSuffixWidth::from_bits(val)
+    }
+}
+impl From<M0wfmtSuffixWidth> for u8 {
+    #[inline(always)]
+    fn from(val: M0wfmtSuffixWidth) -> u8 {
+        M0wfmtSuffixWidth::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum M1rfmtAddrWidth {
+    #[doc = "Single width"]
+    S = 0,
+    #[doc = "Dual width"]
+    D = 0x01,
+    #[doc = "Quad width"]
+    Q = 0x02,
+    _RESERVED_3 = 0x03,
+}
+impl M1rfmtAddrWidth {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> M1rfmtAddrWidth {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for M1rfmtAddrWidth {
+    #[inline(always)]
+    fn from(val: u8) -> M1rfmtAddrWidth {
+        M1rfmtAddrWidth::from_bits(val)
+    }
+}
+impl From<M1rfmtAddrWidth> for u8 {
+    #[inline(always)]
+    fn from(val: M1rfmtAddrWidth) -> u8 {
+        M1rfmtAddrWidth::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum M1rfmtDataWidth {
+    #[doc = "Single width"]
+    S = 0,
+    #[doc = "Dual width"]
+    D = 0x01,
+    #[doc = "Quad width"]
+    Q = 0x02,
+    _RESERVED_3 = 0x03,
+}
+impl M1rfmtDataWidth {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> M1rfmtDataWidth {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for M1rfmtDataWidth {
+    #[inline(always)]
+    fn from(val: u8) -> M1rfmtDataWidth {
+        M1rfmtDataWidth::from_bits(val)
+    }
+}
+impl From<M1rfmtDataWidth> for u8 {
+    #[inline(always)]
+    fn from(val: M1rfmtDataWidth) -> u8 {
+        M1rfmtDataWidth::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum M1rfmtDummyLen {
+    #[doc = "No dummy phase"]
+    NONE = 0,
+    #[doc = "4 dummy bits"]
+    _4 = 0x01,
+    #[doc = "8 dummy bits"]
+    _8 = 0x02,
+    #[doc = "12 dummy bits"]
+    _12 = 0x03,
+    #[doc = "16 dummy bits"]
+    _16 = 0x04,
+    #[doc = "20 dummy bits"]
+    _20 = 0x05,
+    #[doc = "24 dummy bits"]
+    _24 = 0x06,
+    #[doc = "28 dummy bits"]
+    _28 = 0x07,
+}
+impl M1rfmtDummyLen {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> M1rfmtDummyLen {
+        unsafe { core::mem::transmute(val & 0x07) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for M1rfmtDummyLen {
+    #[inline(always)]
+    fn from(val: u8) -> M1rfmtDummyLen {
+        M1rfmtDummyLen::from_bits(val)
+    }
+}
+impl From<M1rfmtDummyLen> for u8 {
+    #[inline(always)]
+    fn from(val: M1rfmtDummyLen) -> u8 {
+        M1rfmtDummyLen::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum M1rfmtDummyWidth {
+    #[doc = "Single width"]
+    S = 0,
+    #[doc = "Dual width"]
+    D = 0x01,
+    #[doc = "Quad width"]
+    Q = 0x02,
+    _RESERVED_3 = 0x03,
+}
+impl M1rfmtDummyWidth {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> M1rfmtDummyWidth {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for M1rfmtDummyWidth {
+    #[inline(always)]
+    fn from(val: u8) -> M1rfmtDummyWidth {
+        M1rfmtDummyWidth::from_bits(val)
+    }
+}
+impl From<M1rfmtDummyWidth> for u8 {
+    #[inline(always)]
+    fn from(val: M1rfmtDummyWidth) -> u8 {
+        M1rfmtDummyWidth::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum M1rfmtPrefixLen {
+    #[doc = "No prefix"]
+    NONE = 0,
+    #[doc = "8-bit prefix"]
+    _8 = 0x01,
+}
+impl M1rfmtPrefixLen {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> M1rfmtPrefixLen {
+        unsafe { core::mem::transmute(val & 0x01) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for M1rfmtPrefixLen {
+    #[inline(always)]
+    fn from(val: u8) -> M1rfmtPrefixLen {
+        M1rfmtPrefixLen::from_bits(val)
+    }
+}
+impl From<M1rfmtPrefixLen> for u8 {
+    #[inline(always)]
+    fn from(val: M1rfmtPrefixLen) -> u8 {
+        M1rfmtPrefixLen::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum M1rfmtPrefixWidth {
+    #[doc = "Single width"]
+    S = 0,
+    #[doc = "Dual width"]
+    D = 0x01,
+    #[doc = "Quad width"]
+    Q = 0x02,
+    _RESERVED_3 = 0x03,
+}
+impl M1rfmtPrefixWidth {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> M1rfmtPrefixWidth {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for M1rfmtPrefixWidth {
+    #[inline(always)]
+    fn from(val: u8) -> M1rfmtPrefixWidth {
+        M1rfmtPrefixWidth::from_bits(val)
+    }
+}
+impl From<M1rfmtPrefixWidth> for u8 {
+    #[inline(always)]
+    fn from(val: M1rfmtPrefixWidth) -> u8 {
+        M1rfmtPrefixWidth::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum M1rfmtSuffixLen {
+    #[doc = "No suffix"]
+    NONE = 0,
+    _RESERVED_1 = 0x01,
+    #[doc = "8-bit suffix"]
+    _8 = 0x02,
+    _RESERVED_3 = 0x03,
+}
+impl M1rfmtSuffixLen {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> M1rfmtSuffixLen {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for M1rfmtSuffixLen {
+    #[inline(always)]
+    fn from(val: u8) -> M1rfmtSuffixLen {
+        M1rfmtSuffixLen::from_bits(val)
+    }
+}
+impl From<M1rfmtSuffixLen> for u8 {
+    #[inline(always)]
+    fn from(val: M1rfmtSuffixLen) -> u8 {
+        M1rfmtSuffixLen::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum M1rfmtSuffixWidth {
+    #[doc = "Single width"]
+    S = 0,
+    #[doc = "Dual width"]
+    D = 0x01,
+    #[doc = "Quad width"]
+    Q = 0x02,
+    _RESERVED_3 = 0x03,
+}
+impl M1rfmtSuffixWidth {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> M1rfmtSuffixWidth {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for M1rfmtSuffixWidth {
+    #[inline(always)]
+    fn from(val: u8) -> M1rfmtSuffixWidth {
+        M1rfmtSuffixWidth::from_bits(val)
+    }
+}
+impl From<M1rfmtSuffixWidth> for u8 {
+    #[inline(always)]
+    fn from(val: M1rfmtSuffixWidth) -> u8 {
+        M1rfmtSuffixWidth::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum M1timingPagebreak {
+    #[doc = "No page boundary is enforced"]
+    NONE = 0,
+    #[doc = "Break bursts crossing a 256-byte page boundary"]
+    _256 = 0x01,
+    #[doc = "Break bursts crossing a 1024-byte quad-page boundary"]
+    _1024 = 0x02,
+    #[doc = "Break bursts crossing a 4096-byte sector boundary"]
+    _4096 = 0x03,
+}
+impl M1timingPagebreak {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> M1timingPagebreak {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for M1timingPagebreak {
+    #[inline(always)]
+    fn from(val: u8) -> M1timingPagebreak {
+        M1timingPagebreak::from_bits(val)
+    }
+}
+impl From<M1timingPagebreak> for u8 {
+    #[inline(always)]
+    fn from(val: M1timingPagebreak) -> u8 {
+        M1timingPagebreak::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum M1wfmtAddrWidth {
+    #[doc = "Single width"]
+    S = 0,
+    #[doc = "Dual width"]
+    D = 0x01,
+    #[doc = "Quad width"]
+    Q = 0x02,
+    _RESERVED_3 = 0x03,
+}
+impl M1wfmtAddrWidth {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> M1wfmtAddrWidth {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for M1wfmtAddrWidth {
+    #[inline(always)]
+    fn from(val: u8) -> M1wfmtAddrWidth {
+        M1wfmtAddrWidth::from_bits(val)
+    }
+}
+impl From<M1wfmtAddrWidth> for u8 {
+    #[inline(always)]
+    fn from(val: M1wfmtAddrWidth) -> u8 {
+        M1wfmtAddrWidth::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum M1wfmtDataWidth {
+    #[doc = "Single width"]
+    S = 0,
+    #[doc = "Dual width"]
+    D = 0x01,
+    #[doc = "Quad width"]
+    Q = 0x02,
+    _RESERVED_3 = 0x03,
+}
+impl M1wfmtDataWidth {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> M1wfmtDataWidth {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for M1wfmtDataWidth {
+    #[inline(always)]
+    fn from(val: u8) -> M1wfmtDataWidth {
+        M1wfmtDataWidth::from_bits(val)
+    }
+}
+impl From<M1wfmtDataWidth> for u8 {
+    #[inline(always)]
+    fn from(val: M1wfmtDataWidth) -> u8 {
+        M1wfmtDataWidth::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum M1wfmtDummyLen {
+    #[doc = "No dummy phase"]
+    NONE = 0,
+    #[doc = "4 dummy bits"]
+    _4 = 0x01,
+    #[doc = "8 dummy bits"]
+    _8 = 0x02,
+    #[doc = "12 dummy bits"]
+    _12 = 0x03,
+    #[doc = "16 dummy bits"]
+    _16 = 0x04,
+    #[doc = "20 dummy bits"]
+    _20 = 0x05,
+    #[doc = "24 dummy bits"]
+    _24 = 0x06,
+    #[doc = "28 dummy bits"]
+    _28 = 0x07,
+}
+impl M1wfmtDummyLen {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> M1wfmtDummyLen {
+        unsafe { core::mem::transmute(val & 0x07) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for M1wfmtDummyLen {
+    #[inline(always)]
+    fn from(val: u8) -> M1wfmtDummyLen {
+        M1wfmtDummyLen::from_bits(val)
+    }
+}
+impl From<M1wfmtDummyLen> for u8 {
+    #[inline(always)]
+    fn from(val: M1wfmtDummyLen) -> u8 {
+        M1wfmtDummyLen::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum M1wfmtDummyWidth {
+    #[doc = "Single width"]
+    S = 0,
+    #[doc = "Dual width"]
+    D = 0x01,
+    #[doc = "Quad width"]
+    Q = 0x02,
+    _RESERVED_3 = 0x03,
+}
+impl M1wfmtDummyWidth {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> M1wfmtDummyWidth {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for M1wfmtDummyWidth {
+    #[inline(always)]
+    fn from(val: u8) -> M1wfmtDummyWidth {
+        M1wfmtDummyWidth::from_bits(val)
+    }
+}
+impl From<M1wfmtDummyWidth> for u8 {
+    #[inline(always)]
+    fn from(val: M1wfmtDummyWidth) -> u8 {
+        M1wfmtDummyWidth::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum M1wfmtPrefixLen {
+    #[doc = "No prefix"]
+    NONE = 0,
+    #[doc = "8-bit prefix"]
+    _8 = 0x01,
+}
+impl M1wfmtPrefixLen {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> M1wfmtPrefixLen {
+        unsafe { core::mem::transmute(val & 0x01) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for M1wfmtPrefixLen {
+    #[inline(always)]
+    fn from(val: u8) -> M1wfmtPrefixLen {
+        M1wfmtPrefixLen::from_bits(val)
+    }
+}
+impl From<M1wfmtPrefixLen> for u8 {
+    #[inline(always)]
+    fn from(val: M1wfmtPrefixLen) -> u8 {
+        M1wfmtPrefixLen::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum M1wfmtPrefixWidth {
+    #[doc = "Single width"]
+    S = 0,
+    #[doc = "Dual width"]
+    D = 0x01,
+    #[doc = "Quad width"]
+    Q = 0x02,
+    _RESERVED_3 = 0x03,
+}
+impl M1wfmtPrefixWidth {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> M1wfmtPrefixWidth {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for M1wfmtPrefixWidth {
+    #[inline(always)]
+    fn from(val: u8) -> M1wfmtPrefixWidth {
+        M1wfmtPrefixWidth::from_bits(val)
+    }
+}
+impl From<M1wfmtPrefixWidth> for u8 {
+    #[inline(always)]
+    fn from(val: M1wfmtPrefixWidth) -> u8 {
+        M1wfmtPrefixWidth::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum M1wfmtSuffixLen {
+    #[doc = "No suffix"]
+    NONE = 0,
+    _RESERVED_1 = 0x01,
+    #[doc = "8-bit suffix"]
+    _8 = 0x02,
+    _RESERVED_3 = 0x03,
+}
+impl M1wfmtSuffixLen {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> M1wfmtSuffixLen {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for M1wfmtSuffixLen {
+    #[inline(always)]
+    fn from(val: u8) -> M1wfmtSuffixLen {
+        M1wfmtSuffixLen::from_bits(val)
+    }
+}
+impl From<M1wfmtSuffixLen> for u8 {
+    #[inline(always)]
+    fn from(val: M1wfmtSuffixLen) -> u8 {
+        M1wfmtSuffixLen::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum M1wfmtSuffixWidth {
+    #[doc = "Single width"]
+    S = 0,
+    #[doc = "Dual width"]
+    D = 0x01,
+    #[doc = "Quad width"]
+    Q = 0x02,
+    _RESERVED_3 = 0x03,
+}
+impl M1wfmtSuffixWidth {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> M1wfmtSuffixWidth {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for M1wfmtSuffixWidth {
+    #[inline(always)]
+    fn from(val: u8) -> M1wfmtSuffixWidth {
+        M1wfmtSuffixWidth::from_bits(val)
+    }
+}
+impl From<M1wfmtSuffixWidth> for u8 {
+    #[inline(always)]
+    fn from(val: M1wfmtSuffixWidth) -> u8 {
+        M1wfmtSuffixWidth::to_bits(val)
+    }
+}
diff --git a/src/rp2350/resets.rs b/src/rp2350/resets.rs
new file mode 100644
index 00000000..334731d1
--- /dev/null
+++ b/src/rp2350/resets.rs
@@ -0,0 +1,29 @@
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Resets {
+    ptr: *mut u8,
+}
+unsafe impl Send for Resets {}
+unsafe impl Sync for Resets {}
+impl Resets {
+    #[inline(always)]
+    pub const unsafe fn from_ptr(ptr: *mut ()) -> Self {
+        Self { ptr: ptr as _ }
+    }
+    #[inline(always)]
+    pub const fn as_ptr(&self) -> *mut () {
+        self.ptr as _
+    }
+    #[inline(always)]
+    pub const fn reset(self) -> crate::common::Reg<regs::Peripherals, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(0usize) as _) }
+    }
+    #[inline(always)]
+    pub const fn wdsel(self) -> crate::common::Reg<regs::Wdsel, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(4usize) as _) }
+    }
+    #[inline(always)]
+    pub const fn reset_done(self) -> crate::common::Reg<regs::Peripherals, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(8usize) as _) }
+    }
+}
+pub mod regs;
diff --git a/src/rp2350/resets/regs.rs b/src/rp2350/resets/regs.rs
new file mode 100644
index 00000000..bac5ba85
--- /dev/null
+++ b/src/rp2350/resets/regs.rs
@@ -0,0 +1,544 @@
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Peripherals(pub u32);
+impl Peripherals {
+    #[inline(always)]
+    pub const fn adc(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_adc(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[inline(always)]
+    pub const fn busctrl(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_busctrl(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+    #[inline(always)]
+    pub const fn dma(&self) -> bool {
+        let val = (self.0 >> 2usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_dma(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+    }
+    #[inline(always)]
+    pub const fn hstx(&self) -> bool {
+        let val = (self.0 >> 3usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_hstx(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
+    }
+    #[inline(always)]
+    pub const fn i2c0(&self) -> bool {
+        let val = (self.0 >> 4usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_i2c0(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
+    }
+    #[inline(always)]
+    pub const fn i2c1(&self) -> bool {
+        let val = (self.0 >> 5usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_i2c1(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
+    }
+    #[inline(always)]
+    pub const fn io_bank0(&self) -> bool {
+        let val = (self.0 >> 6usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_io_bank0(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
+    }
+    #[inline(always)]
+    pub const fn io_qspi(&self) -> bool {
+        let val = (self.0 >> 7usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_io_qspi(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
+    }
+    #[inline(always)]
+    pub const fn jtag(&self) -> bool {
+        let val = (self.0 >> 8usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_jtag(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
+    }
+    #[inline(always)]
+    pub const fn pads_bank0(&self) -> bool {
+        let val = (self.0 >> 9usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_pads_bank0(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
+    }
+    #[inline(always)]
+    pub const fn pads_qspi(&self) -> bool {
+        let val = (self.0 >> 10usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_pads_qspi(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize);
+    }
+    #[inline(always)]
+    pub const fn pio0(&self) -> bool {
+        let val = (self.0 >> 11usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_pio0(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
+    }
+    #[inline(always)]
+    pub const fn pio1(&self) -> bool {
+        let val = (self.0 >> 12usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_pio1(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
+    }
+    #[inline(always)]
+    pub const fn pio2(&self) -> bool {
+        let val = (self.0 >> 13usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_pio2(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize);
+    }
+    #[inline(always)]
+    pub const fn pll_sys(&self) -> bool {
+        let val = (self.0 >> 14usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_pll_sys(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize);
+    }
+    #[inline(always)]
+    pub const fn pll_usb(&self) -> bool {
+        let val = (self.0 >> 15usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_pll_usb(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize);
+    }
+    #[inline(always)]
+    pub const fn pwm(&self) -> bool {
+        let val = (self.0 >> 16usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_pwm(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
+    }
+    #[inline(always)]
+    pub const fn sha256(&self) -> bool {
+        let val = (self.0 >> 17usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_sha256(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
+    }
+    #[inline(always)]
+    pub const fn spi0(&self) -> bool {
+        let val = (self.0 >> 18usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_spi0(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize);
+    }
+    #[inline(always)]
+    pub const fn spi1(&self) -> bool {
+        let val = (self.0 >> 19usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_spi1(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize);
+    }
+    #[inline(always)]
+    pub const fn syscfg(&self) -> bool {
+        let val = (self.0 >> 20usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_syscfg(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize);
+    }
+    #[inline(always)]
+    pub const fn sysinfo(&self) -> bool {
+        let val = (self.0 >> 21usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_sysinfo(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 21usize)) | (((val as u32) & 0x01) << 21usize);
+    }
+    #[inline(always)]
+    pub const fn tbman(&self) -> bool {
+        let val = (self.0 >> 22usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_tbman(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 22usize)) | (((val as u32) & 0x01) << 22usize);
+    }
+    #[inline(always)]
+    pub const fn timer0(&self) -> bool {
+        let val = (self.0 >> 23usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_timer0(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 23usize)) | (((val as u32) & 0x01) << 23usize);
+    }
+    #[inline(always)]
+    pub const fn timer1(&self) -> bool {
+        let val = (self.0 >> 24usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_timer1(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 24usize)) | (((val as u32) & 0x01) << 24usize);
+    }
+    #[inline(always)]
+    pub const fn trng(&self) -> bool {
+        let val = (self.0 >> 25usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_trng(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 25usize)) | (((val as u32) & 0x01) << 25usize);
+    }
+    #[inline(always)]
+    pub const fn uart0(&self) -> bool {
+        let val = (self.0 >> 26usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_uart0(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 26usize)) | (((val as u32) & 0x01) << 26usize);
+    }
+    #[inline(always)]
+    pub const fn uart1(&self) -> bool {
+        let val = (self.0 >> 27usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_uart1(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 27usize)) | (((val as u32) & 0x01) << 27usize);
+    }
+    #[inline(always)]
+    pub const fn usbctrl(&self) -> bool {
+        let val = (self.0 >> 28usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_usbctrl(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 28usize)) | (((val as u32) & 0x01) << 28usize);
+    }
+}
+impl Default for Peripherals {
+    #[inline(always)]
+    fn default() -> Peripherals {
+        Peripherals(0)
+    }
+}
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Wdsel(pub u32);
+impl Wdsel {
+    #[inline(always)]
+    pub const fn adc(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_adc(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[inline(always)]
+    pub const fn busctrl(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_busctrl(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+    #[inline(always)]
+    pub const fn dma(&self) -> bool {
+        let val = (self.0 >> 2usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_dma(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+    }
+    #[inline(always)]
+    pub const fn hstx(&self) -> bool {
+        let val = (self.0 >> 3usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_hstx(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
+    }
+    #[inline(always)]
+    pub const fn i2c0(&self) -> bool {
+        let val = (self.0 >> 4usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_i2c0(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
+    }
+    #[inline(always)]
+    pub const fn i2c1(&self) -> bool {
+        let val = (self.0 >> 5usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_i2c1(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
+    }
+    #[inline(always)]
+    pub const fn io_bank0(&self) -> bool {
+        let val = (self.0 >> 6usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_io_bank0(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
+    }
+    #[inline(always)]
+    pub const fn io_qspi(&self) -> bool {
+        let val = (self.0 >> 7usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_io_qspi(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
+    }
+    #[inline(always)]
+    pub const fn jtag(&self) -> bool {
+        let val = (self.0 >> 8usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_jtag(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
+    }
+    #[inline(always)]
+    pub const fn pads_bank0(&self) -> bool {
+        let val = (self.0 >> 9usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_pads_bank0(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
+    }
+    #[inline(always)]
+    pub const fn pads_qspi(&self) -> bool {
+        let val = (self.0 >> 10usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_pads_qspi(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize);
+    }
+    #[inline(always)]
+    pub const fn pio0(&self) -> bool {
+        let val = (self.0 >> 11usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_pio0(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
+    }
+    #[inline(always)]
+    pub const fn pio1(&self) -> bool {
+        let val = (self.0 >> 12usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_pio1(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
+    }
+    #[inline(always)]
+    pub const fn pio2(&self) -> bool {
+        let val = (self.0 >> 13usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_pio2(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize);
+    }
+    #[inline(always)]
+    pub const fn pll_sys(&self) -> bool {
+        let val = (self.0 >> 14usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_pll_sys(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize);
+    }
+    #[inline(always)]
+    pub const fn pll_usb(&self) -> bool {
+        let val = (self.0 >> 15usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_pll_usb(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize);
+    }
+    #[inline(always)]
+    pub const fn pwm(&self) -> bool {
+        let val = (self.0 >> 16usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_pwm(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
+    }
+    #[inline(always)]
+    pub const fn sha256(&self) -> bool {
+        let val = (self.0 >> 17usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_sha256(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
+    }
+    #[inline(always)]
+    pub const fn spi0(&self) -> bool {
+        let val = (self.0 >> 18usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_spi0(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize);
+    }
+    #[inline(always)]
+    pub const fn spi1(&self) -> bool {
+        let val = (self.0 >> 19usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_spi1(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize);
+    }
+    #[inline(always)]
+    pub const fn syscfg(&self) -> bool {
+        let val = (self.0 >> 20usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_syscfg(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize);
+    }
+    #[inline(always)]
+    pub const fn sysinfo(&self) -> bool {
+        let val = (self.0 >> 21usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_sysinfo(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 21usize)) | (((val as u32) & 0x01) << 21usize);
+    }
+    #[inline(always)]
+    pub const fn tbman(&self) -> bool {
+        let val = (self.0 >> 22usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_tbman(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 22usize)) | (((val as u32) & 0x01) << 22usize);
+    }
+    #[inline(always)]
+    pub const fn timer0(&self) -> bool {
+        let val = (self.0 >> 23usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_timer0(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 23usize)) | (((val as u32) & 0x01) << 23usize);
+    }
+    #[inline(always)]
+    pub const fn timer1(&self) -> bool {
+        let val = (self.0 >> 24usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_timer1(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 24usize)) | (((val as u32) & 0x01) << 24usize);
+    }
+    #[inline(always)]
+    pub const fn trng(&self) -> bool {
+        let val = (self.0 >> 25usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_trng(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 25usize)) | (((val as u32) & 0x01) << 25usize);
+    }
+    #[inline(always)]
+    pub const fn uart0(&self) -> bool {
+        let val = (self.0 >> 26usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_uart0(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 26usize)) | (((val as u32) & 0x01) << 26usize);
+    }
+    #[inline(always)]
+    pub const fn uart1(&self) -> bool {
+        let val = (self.0 >> 27usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_uart1(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 27usize)) | (((val as u32) & 0x01) << 27usize);
+    }
+    #[inline(always)]
+    pub const fn usbctrl(&self) -> bool {
+        let val = (self.0 >> 28usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_usbctrl(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 28usize)) | (((val as u32) & 0x01) << 28usize);
+    }
+}
+impl Default for Wdsel {
+    #[inline(always)]
+    fn default() -> Wdsel {
+        Wdsel(0)
+    }
+}
diff --git a/src/rp2350/rosc.rs b/src/rp2350/rosc.rs
new file mode 100644
index 00000000..b3772cec
--- /dev/null
+++ b/src/rp2350/rosc.rs
@@ -0,0 +1,68 @@
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Rosc {
+    ptr: *mut u8,
+}
+unsafe impl Send for Rosc {}
+unsafe impl Sync for Rosc {}
+impl Rosc {
+    #[inline(always)]
+    pub const unsafe fn from_ptr(ptr: *mut ()) -> Self {
+        Self { ptr: ptr as _ }
+    }
+    #[inline(always)]
+    pub const fn as_ptr(&self) -> *mut () {
+        self.ptr as _
+    }
+    #[doc = "Ring Oscillator control"]
+    #[inline(always)]
+    pub const fn ctrl(self) -> crate::common::Reg<regs::Ctrl, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(0usize) as _) }
+    }
+    #[doc = "The FREQA & FREQB registers control the frequency by controlling the drive strength of each stage The drive strength has 4 levels determined by the number of bits set Increasing the number of bits set increases the drive strength and increases the oscillation frequency 0 bits set is the default drive strength 1 bit set doubles the drive strength 2 bits set triples drive strength 3 bits set quadruples drive strength For frequency randomisation set both DS0_RANDOM=1 & DS1_RANDOM=1"]
+    #[inline(always)]
+    pub const fn freqa(self) -> crate::common::Reg<regs::Freqa, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(4usize) as _) }
+    }
+    #[doc = "For a detailed description see freqa register"]
+    #[inline(always)]
+    pub const fn freqb(self) -> crate::common::Reg<regs::Freqb, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(8usize) as _) }
+    }
+    #[doc = "Loads a value to the LFSR randomiser"]
+    #[inline(always)]
+    pub const fn random(self) -> crate::common::Reg<u32, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(12usize) as _) }
+    }
+    #[doc = "Ring Oscillator pause control"]
+    #[inline(always)]
+    pub const fn dormant(self) -> crate::common::Reg<regs::Dormant, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(16usize) as _) }
+    }
+    #[doc = "Controls the output divider"]
+    #[inline(always)]
+    pub const fn div(self) -> crate::common::Reg<regs::Div, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(20usize) as _) }
+    }
+    #[doc = "Controls the phase shifted output"]
+    #[inline(always)]
+    pub const fn phase(self) -> crate::common::Reg<regs::Phase, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(24usize) as _) }
+    }
+    #[doc = "Ring Oscillator Status"]
+    #[inline(always)]
+    pub const fn status(self) -> crate::common::Reg<regs::Status, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(28usize) as _) }
+    }
+    #[doc = "This just reads the state of the oscillator output so randomness is compromised if the ring oscillator is stopped or run at a harmonic of the bus frequency"]
+    #[inline(always)]
+    pub const fn randombit(self) -> crate::common::Reg<regs::Randombit, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(32usize) as _) }
+    }
+    #[doc = "A down counter running at the ROSC frequency which counts to zero and stops. To start the counter write a non-zero value. Can be used for short software pauses when setting up time sensitive hardware."]
+    #[inline(always)]
+    pub const fn count(self) -> crate::common::Reg<regs::Count, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(36usize) as _) }
+    }
+}
+pub mod regs;
+pub mod vals;
diff --git a/src/rp2350/rosc/regs.rs b/src/rp2350/rosc/regs.rs
new file mode 100644
index 00000000..d28e0151
--- /dev/null
+++ b/src/rp2350/rosc/regs.rs
@@ -0,0 +1,391 @@
+#[doc = "A down counter running at the ROSC frequency which counts to zero and stops. To start the counter write a non-zero value. Can be used for short software pauses when setting up time sensitive hardware."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Count(pub u32);
+impl Count {
+    #[inline(always)]
+    pub const fn count(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0xffff;
+        val as u16
+    }
+    #[inline(always)]
+    pub fn set_count(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+    }
+}
+impl Default for Count {
+    #[inline(always)]
+    fn default() -> Count {
+        Count(0)
+    }
+}
+#[doc = "Ring Oscillator control"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Ctrl(pub u32);
+impl Ctrl {
+    #[doc = "Controls the number of delay stages in the ROSC ring LOW uses stages 0 to 7 MEDIUM uses stages 2 to 7 HIGH uses stages 4 to 7 TOOHIGH uses stages 6 to 7 and should not be used because its frequency exceeds design specifications The clock output will not glitch when changing the range up one step at a time The clock output will glitch when changing the range down Note: the values here are gray coded which is why HIGH comes before TOOHIGH"]
+    #[inline(always)]
+    pub const fn freq_range(&self) -> super::vals::FreqRange {
+        let val = (self.0 >> 0usize) & 0x0fff;
+        super::vals::FreqRange::from_bits(val as u16)
+    }
+    #[doc = "Controls the number of delay stages in the ROSC ring LOW uses stages 0 to 7 MEDIUM uses stages 2 to 7 HIGH uses stages 4 to 7 TOOHIGH uses stages 6 to 7 and should not be used because its frequency exceeds design specifications The clock output will not glitch when changing the range up one step at a time The clock output will glitch when changing the range down Note: the values here are gray coded which is why HIGH comes before TOOHIGH"]
+    #[inline(always)]
+    pub fn set_freq_range(&mut self, val: super::vals::FreqRange) {
+        self.0 = (self.0 & !(0x0fff << 0usize)) | (((val.to_bits() as u32) & 0x0fff) << 0usize);
+    }
+    #[doc = "On power-up this field is initialised to ENABLE The system clock must be switched to another source before setting this field to DISABLE otherwise the chip will lock up The 12-bit code is intended to give some protection against accidental writes. An invalid setting will enable the oscillator."]
+    #[inline(always)]
+    pub const fn enable(&self) -> super::vals::Enable {
+        let val = (self.0 >> 12usize) & 0x0fff;
+        super::vals::Enable::from_bits(val as u16)
+    }
+    #[doc = "On power-up this field is initialised to ENABLE The system clock must be switched to another source before setting this field to DISABLE otherwise the chip will lock up The 12-bit code is intended to give some protection against accidental writes. An invalid setting will enable the oscillator."]
+    #[inline(always)]
+    pub fn set_enable(&mut self, val: super::vals::Enable) {
+        self.0 = (self.0 & !(0x0fff << 12usize)) | (((val.to_bits() as u32) & 0x0fff) << 12usize);
+    }
+}
+impl Default for Ctrl {
+    #[inline(always)]
+    fn default() -> Ctrl {
+        Ctrl(0)
+    }
+}
+#[doc = "Controls the output divider"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Div(pub u32);
+impl Div {
+    #[doc = "set to 0xaa00 + div where div = 0 divides by 128 div = 1-127 divides by div any other value sets div=128 this register resets to div=32"]
+    #[inline(always)]
+    pub const fn div(&self) -> super::vals::Div {
+        let val = (self.0 >> 0usize) & 0xffff;
+        super::vals::Div::from_bits(val as u16)
+    }
+    #[doc = "set to 0xaa00 + div where div = 0 divides by 128 div = 1-127 divides by div any other value sets div=128 this register resets to div=32"]
+    #[inline(always)]
+    pub fn set_div(&mut self, val: super::vals::Div) {
+        self.0 = (self.0 & !(0xffff << 0usize)) | (((val.to_bits() as u32) & 0xffff) << 0usize);
+    }
+}
+impl Default for Div {
+    #[inline(always)]
+    fn default() -> Div {
+        Div(0)
+    }
+}
+#[doc = "Ring Oscillator pause control"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Dormant(pub u32);
+impl Dormant {
+    #[doc = "This is used to save power by pausing the ROSC On power-up this field is initialised to WAKE An invalid write will also select WAKE Warning: setup the irq before selecting dormant mode"]
+    #[inline(always)]
+    pub const fn dormant(&self) -> super::vals::Dormant {
+        let val = (self.0 >> 0usize) & 0xffff_ffff;
+        super::vals::Dormant::from_bits(val as u32)
+    }
+    #[doc = "This is used to save power by pausing the ROSC On power-up this field is initialised to WAKE An invalid write will also select WAKE Warning: setup the irq before selecting dormant mode"]
+    #[inline(always)]
+    pub fn set_dormant(&mut self, val: super::vals::Dormant) {
+        self.0 = (self.0 & !(0xffff_ffff << 0usize))
+            | (((val.to_bits() as u32) & 0xffff_ffff) << 0usize);
+    }
+}
+impl Default for Dormant {
+    #[inline(always)]
+    fn default() -> Dormant {
+        Dormant(0)
+    }
+}
+#[doc = "The FREQA & FREQB registers control the frequency by controlling the drive strength of each stage The drive strength has 4 levels determined by the number of bits set Increasing the number of bits set increases the drive strength and increases the oscillation frequency 0 bits set is the default drive strength 1 bit set doubles the drive strength 2 bits set triples drive strength 3 bits set quadruples drive strength For frequency randomisation set both DS0_RANDOM=1 & DS1_RANDOM=1"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Freqa(pub u32);
+impl Freqa {
+    #[doc = "Stage 0 drive strength"]
+    #[inline(always)]
+    pub const fn ds0(&self) -> u8 {
+        let val = (self.0 >> 0usize) & 0x07;
+        val as u8
+    }
+    #[doc = "Stage 0 drive strength"]
+    #[inline(always)]
+    pub fn set_ds0(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x07 << 0usize)) | (((val as u32) & 0x07) << 0usize);
+    }
+    #[doc = "Randomises the stage 0 drive strength"]
+    #[inline(always)]
+    pub const fn ds0_random(&self) -> bool {
+        let val = (self.0 >> 3usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Randomises the stage 0 drive strength"]
+    #[inline(always)]
+    pub fn set_ds0_random(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
+    }
+    #[doc = "Stage 1 drive strength"]
+    #[inline(always)]
+    pub const fn ds1(&self) -> u8 {
+        let val = (self.0 >> 4usize) & 0x07;
+        val as u8
+    }
+    #[doc = "Stage 1 drive strength"]
+    #[inline(always)]
+    pub fn set_ds1(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x07 << 4usize)) | (((val as u32) & 0x07) << 4usize);
+    }
+    #[doc = "Randomises the stage 1 drive strength"]
+    #[inline(always)]
+    pub const fn ds1_random(&self) -> bool {
+        let val = (self.0 >> 7usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Randomises the stage 1 drive strength"]
+    #[inline(always)]
+    pub fn set_ds1_random(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
+    }
+    #[doc = "Stage 2 drive strength"]
+    #[inline(always)]
+    pub const fn ds2(&self) -> u8 {
+        let val = (self.0 >> 8usize) & 0x07;
+        val as u8
+    }
+    #[doc = "Stage 2 drive strength"]
+    #[inline(always)]
+    pub fn set_ds2(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x07 << 8usize)) | (((val as u32) & 0x07) << 8usize);
+    }
+    #[doc = "Stage 3 drive strength"]
+    #[inline(always)]
+    pub const fn ds3(&self) -> u8 {
+        let val = (self.0 >> 12usize) & 0x07;
+        val as u8
+    }
+    #[doc = "Stage 3 drive strength"]
+    #[inline(always)]
+    pub fn set_ds3(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x07 << 12usize)) | (((val as u32) & 0x07) << 12usize);
+    }
+    #[doc = "Set to 0x9696 to apply the settings Any other value in this field will set all drive strengths to 0"]
+    #[inline(always)]
+    pub const fn passwd(&self) -> super::vals::Passwd {
+        let val = (self.0 >> 16usize) & 0xffff;
+        super::vals::Passwd::from_bits(val as u16)
+    }
+    #[doc = "Set to 0x9696 to apply the settings Any other value in this field will set all drive strengths to 0"]
+    #[inline(always)]
+    pub fn set_passwd(&mut self, val: super::vals::Passwd) {
+        self.0 = (self.0 & !(0xffff << 16usize)) | (((val.to_bits() as u32) & 0xffff) << 16usize);
+    }
+}
+impl Default for Freqa {
+    #[inline(always)]
+    fn default() -> Freqa {
+        Freqa(0)
+    }
+}
+#[doc = "For a detailed description see freqa register"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Freqb(pub u32);
+impl Freqb {
+    #[doc = "Stage 4 drive strength"]
+    #[inline(always)]
+    pub const fn ds4(&self) -> u8 {
+        let val = (self.0 >> 0usize) & 0x07;
+        val as u8
+    }
+    #[doc = "Stage 4 drive strength"]
+    #[inline(always)]
+    pub fn set_ds4(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x07 << 0usize)) | (((val as u32) & 0x07) << 0usize);
+    }
+    #[doc = "Stage 5 drive strength"]
+    #[inline(always)]
+    pub const fn ds5(&self) -> u8 {
+        let val = (self.0 >> 4usize) & 0x07;
+        val as u8
+    }
+    #[doc = "Stage 5 drive strength"]
+    #[inline(always)]
+    pub fn set_ds5(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x07 << 4usize)) | (((val as u32) & 0x07) << 4usize);
+    }
+    #[doc = "Stage 6 drive strength"]
+    #[inline(always)]
+    pub const fn ds6(&self) -> u8 {
+        let val = (self.0 >> 8usize) & 0x07;
+        val as u8
+    }
+    #[doc = "Stage 6 drive strength"]
+    #[inline(always)]
+    pub fn set_ds6(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x07 << 8usize)) | (((val as u32) & 0x07) << 8usize);
+    }
+    #[doc = "Stage 7 drive strength"]
+    #[inline(always)]
+    pub const fn ds7(&self) -> u8 {
+        let val = (self.0 >> 12usize) & 0x07;
+        val as u8
+    }
+    #[doc = "Stage 7 drive strength"]
+    #[inline(always)]
+    pub fn set_ds7(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x07 << 12usize)) | (((val as u32) & 0x07) << 12usize);
+    }
+    #[doc = "Set to 0x9696 to apply the settings Any other value in this field will set all drive strengths to 0"]
+    #[inline(always)]
+    pub const fn passwd(&self) -> super::vals::Passwd {
+        let val = (self.0 >> 16usize) & 0xffff;
+        super::vals::Passwd::from_bits(val as u16)
+    }
+    #[doc = "Set to 0x9696 to apply the settings Any other value in this field will set all drive strengths to 0"]
+    #[inline(always)]
+    pub fn set_passwd(&mut self, val: super::vals::Passwd) {
+        self.0 = (self.0 & !(0xffff << 16usize)) | (((val.to_bits() as u32) & 0xffff) << 16usize);
+    }
+}
+impl Default for Freqb {
+    #[inline(always)]
+    fn default() -> Freqb {
+        Freqb(0)
+    }
+}
+#[doc = "Controls the phase shifted output"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Phase(pub u32);
+impl Phase {
+    #[doc = "phase shift the phase-shifted output by SHIFT input clocks this can be changed on-the-fly must be set to 0 before setting div=1"]
+    #[inline(always)]
+    pub const fn shift(&self) -> u8 {
+        let val = (self.0 >> 0usize) & 0x03;
+        val as u8
+    }
+    #[doc = "phase shift the phase-shifted output by SHIFT input clocks this can be changed on-the-fly must be set to 0 before setting div=1"]
+    #[inline(always)]
+    pub fn set_shift(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x03 << 0usize)) | (((val as u32) & 0x03) << 0usize);
+    }
+    #[doc = "invert the phase-shifted output this is ignored when div=1"]
+    #[inline(always)]
+    pub const fn flip(&self) -> bool {
+        let val = (self.0 >> 2usize) & 0x01;
+        val != 0
+    }
+    #[doc = "invert the phase-shifted output this is ignored when div=1"]
+    #[inline(always)]
+    pub fn set_flip(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+    }
+    #[doc = "enable the phase-shifted output this can be changed on-the-fly"]
+    #[inline(always)]
+    pub const fn enable(&self) -> bool {
+        let val = (self.0 >> 3usize) & 0x01;
+        val != 0
+    }
+    #[doc = "enable the phase-shifted output this can be changed on-the-fly"]
+    #[inline(always)]
+    pub fn set_enable(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
+    }
+    #[doc = "set to 0xaa any other value enables the output with shift=0"]
+    #[inline(always)]
+    pub const fn passwd(&self) -> u8 {
+        let val = (self.0 >> 4usize) & 0xff;
+        val as u8
+    }
+    #[doc = "set to 0xaa any other value enables the output with shift=0"]
+    #[inline(always)]
+    pub fn set_passwd(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 4usize)) | (((val as u32) & 0xff) << 4usize);
+    }
+}
+impl Default for Phase {
+    #[inline(always)]
+    fn default() -> Phase {
+        Phase(0)
+    }
+}
+#[doc = "This just reads the state of the oscillator output so randomness is compromised if the ring oscillator is stopped or run at a harmonic of the bus frequency"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Randombit(pub u32);
+impl Randombit {
+    #[inline(always)]
+    pub const fn randombit(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_randombit(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+}
+impl Default for Randombit {
+    #[inline(always)]
+    fn default() -> Randombit {
+        Randombit(0)
+    }
+}
+#[doc = "Ring Oscillator Status"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Status(pub u32);
+impl Status {
+    #[doc = "Oscillator is enabled but not necessarily running and stable this resets to 0 but transitions to 1 during chip startup"]
+    #[inline(always)]
+    pub const fn enabled(&self) -> bool {
+        let val = (self.0 >> 12usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Oscillator is enabled but not necessarily running and stable this resets to 0 but transitions to 1 during chip startup"]
+    #[inline(always)]
+    pub fn set_enabled(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
+    }
+    #[doc = "post-divider is running this resets to 0 but transitions to 1 during chip startup"]
+    #[inline(always)]
+    pub const fn div_running(&self) -> bool {
+        let val = (self.0 >> 16usize) & 0x01;
+        val != 0
+    }
+    #[doc = "post-divider is running this resets to 0 but transitions to 1 during chip startup"]
+    #[inline(always)]
+    pub fn set_div_running(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
+    }
+    #[doc = "An invalid value has been written to CTRL_ENABLE or CTRL_FREQ_RANGE or FREQA or FREQB or DIV or PHASE or DORMANT"]
+    #[inline(always)]
+    pub const fn badwrite(&self) -> bool {
+        let val = (self.0 >> 24usize) & 0x01;
+        val != 0
+    }
+    #[doc = "An invalid value has been written to CTRL_ENABLE or CTRL_FREQ_RANGE or FREQA or FREQB or DIV or PHASE or DORMANT"]
+    #[inline(always)]
+    pub fn set_badwrite(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 24usize)) | (((val as u32) & 0x01) << 24usize);
+    }
+    #[doc = "Oscillator is running and stable"]
+    #[inline(always)]
+    pub const fn stable(&self) -> bool {
+        let val = (self.0 >> 31usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Oscillator is running and stable"]
+    #[inline(always)]
+    pub fn set_stable(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 31usize)) | (((val as u32) & 0x01) << 31usize);
+    }
+}
+impl Default for Status {
+    #[inline(always)]
+    fn default() -> Status {
+        Status(0)
+    }
+}
diff --git a/src/rp2350/rosc/vals.rs b/src/rp2350/rosc/vals.rs
new file mode 100644
index 00000000..7e19fc7e
--- /dev/null
+++ b/src/rp2350/rosc/vals.rs
@@ -0,0 +1,135 @@
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub struct Div(pub u16);
+impl Div {
+    pub const PASS: Self = Self(0xaa00);
+}
+impl Div {
+    pub const fn from_bits(val: u16) -> Div {
+        Self(val & 0xffff)
+    }
+    pub const fn to_bits(self) -> u16 {
+        self.0
+    }
+}
+impl From<u16> for Div {
+    #[inline(always)]
+    fn from(val: u16) -> Div {
+        Div::from_bits(val)
+    }
+}
+impl From<Div> for u16 {
+    #[inline(always)]
+    fn from(val: Div) -> u16 {
+        Div::to_bits(val)
+    }
+}
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub struct Dormant(pub u32);
+impl Dormant {
+    pub const DORMANT: Self = Self(0x636f_6d61);
+    pub const WAKE: Self = Self(0x7761_6b65);
+}
+impl Dormant {
+    pub const fn from_bits(val: u32) -> Dormant {
+        Self(val & 0xffff_ffff)
+    }
+    pub const fn to_bits(self) -> u32 {
+        self.0
+    }
+}
+impl From<u32> for Dormant {
+    #[inline(always)]
+    fn from(val: u32) -> Dormant {
+        Dormant::from_bits(val)
+    }
+}
+impl From<Dormant> for u32 {
+    #[inline(always)]
+    fn from(val: Dormant) -> u32 {
+        Dormant::to_bits(val)
+    }
+}
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub struct Enable(pub u16);
+impl Enable {
+    pub const DISABLE: Self = Self(0x0d1e);
+    pub const ENABLE: Self = Self(0x0fab);
+}
+impl Enable {
+    pub const fn from_bits(val: u16) -> Enable {
+        Self(val & 0x0fff)
+    }
+    pub const fn to_bits(self) -> u16 {
+        self.0
+    }
+}
+impl From<u16> for Enable {
+    #[inline(always)]
+    fn from(val: u16) -> Enable {
+        Enable::from_bits(val)
+    }
+}
+impl From<Enable> for u16 {
+    #[inline(always)]
+    fn from(val: Enable) -> u16 {
+        Enable::to_bits(val)
+    }
+}
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub struct FreqRange(pub u16);
+impl FreqRange {
+    pub const LOW: Self = Self(0x0fa4);
+    pub const MEDIUM: Self = Self(0x0fa5);
+    pub const TOOHIGH: Self = Self(0x0fa6);
+    pub const HIGH: Self = Self(0x0fa7);
+}
+impl FreqRange {
+    pub const fn from_bits(val: u16) -> FreqRange {
+        Self(val & 0x0fff)
+    }
+    pub const fn to_bits(self) -> u16 {
+        self.0
+    }
+}
+impl From<u16> for FreqRange {
+    #[inline(always)]
+    fn from(val: u16) -> FreqRange {
+        FreqRange::from_bits(val)
+    }
+}
+impl From<FreqRange> for u16 {
+    #[inline(always)]
+    fn from(val: FreqRange) -> u16 {
+        FreqRange::to_bits(val)
+    }
+}
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub struct Passwd(pub u16);
+impl Passwd {
+    pub const PASS: Self = Self(0x9696);
+}
+impl Passwd {
+    pub const fn from_bits(val: u16) -> Passwd {
+        Self(val & 0xffff)
+    }
+    pub const fn to_bits(self) -> u16 {
+        self.0
+    }
+}
+impl From<u16> for Passwd {
+    #[inline(always)]
+    fn from(val: u16) -> Passwd {
+        Passwd::from_bits(val)
+    }
+}
+impl From<Passwd> for u16 {
+    #[inline(always)]
+    fn from(val: Passwd) -> u16 {
+        Passwd::to_bits(val)
+    }
+}
diff --git a/src/rp2350/sha256.rs b/src/rp2350/sha256.rs
new file mode 100644
index 00000000..5dd83fbd
--- /dev/null
+++ b/src/rp2350/sha256.rs
@@ -0,0 +1,69 @@
+#[doc = "SHA-256 hash function implementation"]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Sha256 {
+    ptr: *mut u8,
+}
+unsafe impl Send for Sha256 {}
+unsafe impl Sync for Sha256 {}
+impl Sha256 {
+    #[inline(always)]
+    pub const unsafe fn from_ptr(ptr: *mut ()) -> Self {
+        Self { ptr: ptr as _ }
+    }
+    #[inline(always)]
+    pub const fn as_ptr(&self) -> *mut () {
+        self.ptr as _
+    }
+    #[doc = "Control and status register"]
+    #[inline(always)]
+    pub const fn csr(self) -> crate::common::Reg<regs::Csr, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(0usize) as _) }
+    }
+    #[doc = "Write data register"]
+    #[inline(always)]
+    pub const fn wdata(self) -> crate::common::Reg<u32, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(4usize) as _) }
+    }
+    #[doc = "256-bit checksum result. Contents are undefined when CSR_SUM_VLD is 0."]
+    #[inline(always)]
+    pub const fn sum0(self) -> crate::common::Reg<u32, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(8usize) as _) }
+    }
+    #[doc = "256-bit checksum result. Contents are undefined when CSR_SUM_VLD is 0."]
+    #[inline(always)]
+    pub const fn sum1(self) -> crate::common::Reg<u32, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(12usize) as _) }
+    }
+    #[doc = "256-bit checksum result. Contents are undefined when CSR_SUM_VLD is 0."]
+    #[inline(always)]
+    pub const fn sum2(self) -> crate::common::Reg<u32, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(16usize) as _) }
+    }
+    #[doc = "256-bit checksum result. Contents are undefined when CSR_SUM_VLD is 0."]
+    #[inline(always)]
+    pub const fn sum3(self) -> crate::common::Reg<u32, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(20usize) as _) }
+    }
+    #[doc = "256-bit checksum result. Contents are undefined when CSR_SUM_VLD is 0."]
+    #[inline(always)]
+    pub const fn sum4(self) -> crate::common::Reg<u32, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(24usize) as _) }
+    }
+    #[doc = "256-bit checksum result. Contents are undefined when CSR_SUM_VLD is 0."]
+    #[inline(always)]
+    pub const fn sum5(self) -> crate::common::Reg<u32, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(28usize) as _) }
+    }
+    #[doc = "256-bit checksum result. Contents are undefined when CSR_SUM_VLD is 0."]
+    #[inline(always)]
+    pub const fn sum6(self) -> crate::common::Reg<u32, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(32usize) as _) }
+    }
+    #[doc = "256-bit checksum result. Contents are undefined when CSR_SUM_VLD is 0."]
+    #[inline(always)]
+    pub const fn sum7(self) -> crate::common::Reg<u32, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(36usize) as _) }
+    }
+}
+pub mod regs;
+pub mod vals;
diff --git a/src/rp2350/sha256/regs.rs b/src/rp2350/sha256/regs.rs
new file mode 100644
index 00000000..0226d156
--- /dev/null
+++ b/src/rp2350/sha256/regs.rs
@@ -0,0 +1,78 @@
+#[doc = "Control and status register"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Csr(pub u32);
+impl Csr {
+    #[doc = "Write 1 to prepare the SHA-256 core for a new checksum. The SUMx registers are initialised to the proper values (fractional bits of square roots of first 8 primes) and internal counters are cleared. This immediately forces WDATA_RDY and SUM_VLD high. START must be written before initiating a DMA transfer to the SHA-256 core, because the core will always request 16 transfers at a time (1 512-bit block). Additionally, the DMA channel should be configured for a multiple of 16 32-bit transfers."]
+    #[inline(always)]
+    pub const fn start(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Write 1 to prepare the SHA-256 core for a new checksum. The SUMx registers are initialised to the proper values (fractional bits of square roots of first 8 primes) and internal counters are cleared. This immediately forces WDATA_RDY and SUM_VLD high. START must be written before initiating a DMA transfer to the SHA-256 core, because the core will always request 16 transfers at a time (1 512-bit block). Additionally, the DMA channel should be configured for a multiple of 16 32-bit transfers."]
+    #[inline(always)]
+    pub fn set_start(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[doc = "If 1, the SHA-256 core is ready to accept more data through the WDATA register. After writing 16 words, this flag will go low for 57 cycles whilst the core completes its digest."]
+    #[inline(always)]
+    pub const fn wdata_rdy(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, the SHA-256 core is ready to accept more data through the WDATA register. After writing 16 words, this flag will go low for 57 cycles whilst the core completes its digest."]
+    #[inline(always)]
+    pub fn set_wdata_rdy(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+    #[doc = "If 1, the SHA-256 checksum presented in registers SUM0 through SUM7 is currently valid. Goes low when WDATA is first written, then returns high once 16 words have been written and the digest of the current 512-bit block has subsequently completed."]
+    #[inline(always)]
+    pub const fn sum_vld(&self) -> bool {
+        let val = (self.0 >> 2usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, the SHA-256 checksum presented in registers SUM0 through SUM7 is currently valid. Goes low when WDATA is first written, then returns high once 16 words have been written and the digest of the current 512-bit block has subsequently completed."]
+    #[inline(always)]
+    pub fn set_sum_vld(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+    }
+    #[doc = "Set when a write occurs whilst the SHA-256 core is not ready for data (WDATA_RDY is low). Write one to clear."]
+    #[inline(always)]
+    pub const fn err_wdata_not_rdy(&self) -> bool {
+        let val = (self.0 >> 4usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Set when a write occurs whilst the SHA-256 core is not ready for data (WDATA_RDY is low). Write one to clear."]
+    #[inline(always)]
+    pub fn set_err_wdata_not_rdy(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
+    }
+    #[doc = "Configure DREQ logic for the correct DMA data size. Must be configured before the DMA channel is triggered. The SHA-256 core's DREQ logic requests one entire block of data at once, since there is no FIFO, and data goes straight into the core's message schedule and digest hardware. Therefore, when transferring data with DMA, CSR_DMA_SIZE must be configured in advance so that the correct number of transfers can be requested per block."]
+    #[inline(always)]
+    pub const fn dma_size(&self) -> super::vals::DmaSize {
+        let val = (self.0 >> 8usize) & 0x03;
+        super::vals::DmaSize::from_bits(val as u8)
+    }
+    #[doc = "Configure DREQ logic for the correct DMA data size. Must be configured before the DMA channel is triggered. The SHA-256 core's DREQ logic requests one entire block of data at once, since there is no FIFO, and data goes straight into the core's message schedule and digest hardware. Therefore, when transferring data with DMA, CSR_DMA_SIZE must be configured in advance so that the correct number of transfers can be requested per block."]
+    #[inline(always)]
+    pub fn set_dma_size(&mut self, val: super::vals::DmaSize) {
+        self.0 = (self.0 & !(0x03 << 8usize)) | (((val.to_bits() as u32) & 0x03) << 8usize);
+    }
+    #[doc = "Enable byte swapping of 32-bit values at the point they are committed to the SHA message scheduler. This block's bus interface assembles byte/halfword data into message words in little-endian order, so that DMAing the same buffer with different transfer sizes always gives the same result on a little-endian system like RP2350. However, when marshalling bytes into blocks, SHA expects that the first byte is the *most significant* in each message word. To resolve this, once the bus interface has accumulated 32 bits of data (either a word write, two halfword writes in little-endian order, or four byte writes in little-endian order) the final value can be byte-swapped before passing to the actual SHA core. This feature is enabled by default because using the SHA core to checksum byte buffers is expected to be more common than having preformatted SHA message words lying around."]
+    #[inline(always)]
+    pub const fn bswap(&self) -> bool {
+        let val = (self.0 >> 12usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Enable byte swapping of 32-bit values at the point they are committed to the SHA message scheduler. This block's bus interface assembles byte/halfword data into message words in little-endian order, so that DMAing the same buffer with different transfer sizes always gives the same result on a little-endian system like RP2350. However, when marshalling bytes into blocks, SHA expects that the first byte is the *most significant* in each message word. To resolve this, once the bus interface has accumulated 32 bits of data (either a word write, two halfword writes in little-endian order, or four byte writes in little-endian order) the final value can be byte-swapped before passing to the actual SHA core. This feature is enabled by default because using the SHA core to checksum byte buffers is expected to be more common than having preformatted SHA message words lying around."]
+    #[inline(always)]
+    pub fn set_bswap(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
+    }
+}
+impl Default for Csr {
+    #[inline(always)]
+    fn default() -> Csr {
+        Csr(0)
+    }
+}
diff --git a/src/rp2350/sha256/vals.rs b/src/rp2350/sha256/vals.rs
new file mode 100644
index 00000000..a35fc835
--- /dev/null
+++ b/src/rp2350/sha256/vals.rs
@@ -0,0 +1,30 @@
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum DmaSize {
+    _8BIT = 0,
+    _16BIT = 0x01,
+    _32BIT = 0x02,
+    _RESERVED_3 = 0x03,
+}
+impl DmaSize {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> DmaSize {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for DmaSize {
+    #[inline(always)]
+    fn from(val: u8) -> DmaSize {
+        DmaSize::from_bits(val)
+    }
+}
+impl From<DmaSize> for u8 {
+    #[inline(always)]
+    fn from(val: DmaSize) -> u8 {
+        DmaSize::to_bits(val)
+    }
+}
diff --git a/src/rp2350/sio.rs b/src/rp2350/sio.rs
new file mode 100644
index 00000000..039e2360
--- /dev/null
+++ b/src/rp2350/sio.rs
@@ -0,0 +1,336 @@
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Fifo {
+    ptr: *mut u8,
+}
+unsafe impl Send for Fifo {}
+unsafe impl Sync for Fifo {}
+impl Fifo {
+    #[inline(always)]
+    pub const unsafe fn from_ptr(ptr: *mut ()) -> Self {
+        Self { ptr: ptr as _ }
+    }
+    #[inline(always)]
+    pub const fn as_ptr(&self) -> *mut () {
+        self.ptr as _
+    }
+    #[doc = "Status register for inter-core FIFOs (mailboxes). There is one FIFO in the core 0 -> core 1 direction, and one core 1 -> core 0. Both are 32 bits wide and 8 words deep. Core 0 can see the read side of the 1->0 FIFO (RX), and the write side of 0->1 FIFO (TX). Core 1 can see the read side of the 0->1 FIFO (RX), and the write side of 1->0 FIFO (TX). The SIO IRQ for each core is the logical OR of the VLD, WOF and ROE fields of its FIFO_ST register."]
+    #[inline(always)]
+    pub const fn st(self) -> crate::common::Reg<regs::FifoSt, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(0usize) as _) }
+    }
+    #[doc = "Write access to this core's TX FIFO"]
+    #[inline(always)]
+    pub const fn wr(self) -> crate::common::Reg<u32, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(4usize) as _) }
+    }
+    #[doc = "Read access to this core's RX FIFO"]
+    #[inline(always)]
+    pub const fn rd(self) -> crate::common::Reg<u32, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(8usize) as _) }
+    }
+}
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Gpio {
+    ptr: *mut u8,
+}
+unsafe impl Send for Gpio {}
+unsafe impl Sync for Gpio {}
+impl Gpio {
+    #[inline(always)]
+    pub const unsafe fn from_ptr(ptr: *mut ()) -> Self {
+        Self { ptr: ptr as _ }
+    }
+    #[inline(always)]
+    pub const fn as_ptr(&self) -> *mut () {
+        self.ptr as _
+    }
+    #[doc = "GPIO0...31 output value"]
+    #[inline(always)]
+    pub const fn value(self) -> crate::common::Reg<u32, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(0usize) as _) }
+    }
+    #[doc = "GPIO0...31 output value set"]
+    #[inline(always)]
+    pub const fn value_set(self) -> crate::common::Reg<u32, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(8usize) as _) }
+    }
+    #[doc = "GPIO0...31 output value clear"]
+    #[inline(always)]
+    pub const fn value_clr(self) -> crate::common::Reg<u32, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(16usize) as _) }
+    }
+    #[doc = "GPIO0...31 output value XOR"]
+    #[inline(always)]
+    pub const fn value_xor(self) -> crate::common::Reg<u32, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(24usize) as _) }
+    }
+}
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Interp {
+    ptr: *mut u8,
+}
+unsafe impl Send for Interp {}
+unsafe impl Sync for Interp {}
+impl Interp {
+    #[inline(always)]
+    pub const unsafe fn from_ptr(ptr: *mut ()) -> Self {
+        Self { ptr: ptr as _ }
+    }
+    #[inline(always)]
+    pub const fn as_ptr(&self) -> *mut () {
+        self.ptr as _
+    }
+    #[doc = "Read/write access to accumulator 0"]
+    #[inline(always)]
+    pub const fn accum0(self) -> crate::common::Reg<u32, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(0usize) as _) }
+    }
+    #[doc = "Read/write access to accumulator 1"]
+    #[inline(always)]
+    pub const fn accum1(self) -> crate::common::Reg<u32, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(4usize) as _) }
+    }
+    #[doc = "Read/write access to BASE0 register."]
+    #[inline(always)]
+    pub const fn base0(self) -> crate::common::Reg<u32, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(8usize) as _) }
+    }
+    #[doc = "Read/write access to BASE1 register."]
+    #[inline(always)]
+    pub const fn base1(self) -> crate::common::Reg<u32, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(12usize) as _) }
+    }
+    #[doc = "Read/write access to BASE2 register."]
+    #[inline(always)]
+    pub const fn base2(self) -> crate::common::Reg<u32, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(16usize) as _) }
+    }
+    #[doc = "Read LANE0 result, and simultaneously write lane results to both accumulators (POP)."]
+    #[inline(always)]
+    pub const fn pop_lane0(self) -> crate::common::Reg<u32, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(20usize) as _) }
+    }
+    #[doc = "Read LANE1 result, and simultaneously write lane results to both accumulators (POP)."]
+    #[inline(always)]
+    pub const fn pop_lane1(self) -> crate::common::Reg<u32, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(24usize) as _) }
+    }
+    #[doc = "Read FULL result, and simultaneously write lane results to both accumulators (POP)."]
+    #[inline(always)]
+    pub const fn pop_full(self) -> crate::common::Reg<u32, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(28usize) as _) }
+    }
+    #[doc = "Read LANE0 result, without altering any internal state (PEEK)."]
+    #[inline(always)]
+    pub const fn peek_lane0(self) -> crate::common::Reg<u32, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(32usize) as _) }
+    }
+    #[doc = "Read LANE1 result, without altering any internal state (PEEK)."]
+    #[inline(always)]
+    pub const fn peek_lane1(self) -> crate::common::Reg<u32, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(36usize) as _) }
+    }
+    #[doc = "Read FULL result, without altering any internal state (PEEK)."]
+    #[inline(always)]
+    pub const fn peek_full(self) -> crate::common::Reg<u32, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(40usize) as _) }
+    }
+    #[doc = "Control register for lane 0"]
+    #[inline(always)]
+    pub const fn ctrl_lane0(self) -> crate::common::Reg<regs::Interp0ctrlLane0, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(44usize) as _) }
+    }
+    #[doc = "Control register for lane 1"]
+    #[inline(always)]
+    pub const fn ctrl_lane1(self) -> crate::common::Reg<regs::Interp0ctrlLane1, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(48usize) as _) }
+    }
+    #[doc = "Values written here are atomically added to ACCUM0 Reading yields lane 0's raw shift and mask value (BASE0 not added)."]
+    #[inline(always)]
+    pub const fn accum0_add(self) -> crate::common::Reg<regs::Interp0accum0add, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(52usize) as _) }
+    }
+    #[doc = "Values written here are atomically added to ACCUM1 Reading yields lane 1's raw shift and mask value (BASE1 not added)."]
+    #[inline(always)]
+    pub const fn accum1_add(self) -> crate::common::Reg<regs::Interp0accum1add, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(56usize) as _) }
+    }
+    #[doc = "On write, the lower 16 bits go to BASE0, upper bits to BASE1 simultaneously. Each half is sign-extended to 32 bits if that lane's SIGNED flag is set."]
+    #[inline(always)]
+    pub const fn base_1and0(self) -> crate::common::Reg<u32, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(60usize) as _) }
+    }
+}
+#[doc = "Single-cycle IO block Provides core-local and inter-core hardware for the two processors, with single-cycle access."]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Sio {
+    ptr: *mut u8,
+}
+unsafe impl Send for Sio {}
+unsafe impl Sync for Sio {}
+impl Sio {
+    #[inline(always)]
+    pub const unsafe fn from_ptr(ptr: *mut ()) -> Self {
+        Self { ptr: ptr as _ }
+    }
+    #[inline(always)]
+    pub const fn as_ptr(&self) -> *mut () {
+        self.ptr as _
+    }
+    #[doc = "Processor core identifier"]
+    #[inline(always)]
+    pub const fn cpuid(self) -> crate::common::Reg<u32, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(0usize) as _) }
+    }
+    #[doc = "Input value for GPIO0...31. In the Non-secure SIO, Secure-only GPIOs (as per ACCESSCTRL) appear as zero."]
+    #[inline(always)]
+    pub const fn gpio_in(self, n: usize) -> crate::common::Reg<u32, crate::common::RW> {
+        assert!(n < 2usize);
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(4usize + n * 4usize) as _) }
+    }
+    #[inline(always)]
+    pub const fn gpio_out(self, n: usize) -> Gpio {
+        assert!(n < 2usize);
+        unsafe { Gpio::from_ptr(self.ptr.add(16usize + n * 4usize) as _) }
+    }
+    #[inline(always)]
+    pub const fn gpio_oe(self, n: usize) -> Gpio {
+        assert!(n < 2usize);
+        unsafe { Gpio::from_ptr(self.ptr.add(48usize + n * 4usize) as _) }
+    }
+    #[inline(always)]
+    pub const fn fifo(self) -> Fifo {
+        unsafe { Fifo::from_ptr(self.ptr.add(80usize) as _) }
+    }
+    #[doc = "Spinlock state A bitmap containing the state of all 32 spinlocks (1=locked). Mainly intended for debugging."]
+    #[inline(always)]
+    pub const fn spinlock_st(self) -> crate::common::Reg<u32, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(92usize) as _) }
+    }
+    #[inline(always)]
+    pub const fn interp(self, n: usize) -> Interp {
+        assert!(n < 2usize);
+        unsafe { Interp::from_ptr(self.ptr.add(128usize + n * 64usize) as _) }
+    }
+    #[doc = "Reading from a spinlock address will: - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock Writing (any value) releases the lock. If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. The value returned on success is 0x1 << lock number."]
+    #[inline(always)]
+    pub const fn spinlock(self, n: usize) -> crate::common::Reg<u32, crate::common::RW> {
+        assert!(n < 32usize);
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(256usize + n * 4usize) as _) }
+    }
+    #[doc = "Trigger a doorbell interrupt on the opposite core. Write 1 to a bit to set the corresponding bit in DOORBELL_IN on the opposite core. This raises the opposite core's doorbell interrupt. Read to get the status of the doorbells currently asserted on the opposite core. This is equivalent to that core reading its own DOORBELL_IN status."]
+    #[inline(always)]
+    pub const fn doorbell_out_set(
+        self,
+    ) -> crate::common::Reg<regs::DoorbellOutSet, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(384usize) as _) }
+    }
+    #[doc = "Clear doorbells which have been posted to the opposite core. This register is intended for debugging and initialisation purposes. Writing 1 to a bit in DOORBELL_OUT_CLR clears the corresponding bit in DOORBELL_IN on the opposite core. Clearing all bits will cause that core's doorbell interrupt to deassert. Since the usual order of events is for software to send events using DOORBELL_OUT_SET, and acknowledge incoming events by writing to DOORBELL_IN_CLR, this register should be used with caution to avoid race conditions. Reading returns the status of the doorbells currently asserted on the other core, i.e. is equivalent to that core reading its own DOORBELL_IN status."]
+    #[inline(always)]
+    pub const fn doorbell_out_clr(
+        self,
+    ) -> crate::common::Reg<regs::DoorbellOutClr, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(388usize) as _) }
+    }
+    #[doc = "Write 1s to trigger doorbell interrupts on this core. Read to get status of doorbells currently asserted on this core."]
+    #[inline(always)]
+    pub const fn doorbell_in_set(
+        self,
+    ) -> crate::common::Reg<regs::DoorbellInSet, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(392usize) as _) }
+    }
+    #[doc = "Check and acknowledge doorbells posted to this core. This core's doorbell interrupt is asserted when any bit in this register is 1. Write 1 to each bit to clear that bit. The doorbell interrupt deasserts once all bits are cleared. Read to get status of doorbells currently asserted on this core."]
+    #[inline(always)]
+    pub const fn doorbell_in_clr(
+        self,
+    ) -> crate::common::Reg<regs::DoorbellInClr, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(396usize) as _) }
+    }
+    #[doc = "Detach certain core-local peripherals from Secure SIO, and attach them to Non-secure SIO, so that Non-secure software can use them. Attempting to access one of these peripherals from the Secure SIO when it is attached to the Non-secure SIO, or vice versa, will generate a bus error. This register is per-core, and is only present on the Secure SIO. Most SIO hardware is duplicated across the Secure and Non-secure SIO, so is not listed in this register."]
+    #[inline(always)]
+    pub const fn peri_nonsec(self) -> crate::common::Reg<regs::PeriNonsec, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(400usize) as _) }
+    }
+    #[doc = "Control the assertion of the standard software interrupt (MIP.MSIP) on the RISC-V cores. Unlike the RISC-V timer, this interrupt is not routed to a normal system-level interrupt line, so can not be used by the Arm cores. It is safe for both cores to write to this register on the same cycle. The set/clear effect is accumulated across both cores, and then applied. If a flag is both set and cleared on the same cycle, only the set takes effect."]
+    #[inline(always)]
+    pub const fn riscv_softirq(self) -> crate::common::Reg<regs::RiscvSoftirq, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(416usize) as _) }
+    }
+    #[doc = "Control register for the RISC-V 64-bit Machine-mode timer. This timer is only present in the Secure SIO, so is only accessible to an Arm core in Secure mode or a RISC-V core in Machine mode. Note whilst this timer follows the RISC-V privileged specification, it is equally usable by the Arm cores. The interrupts are routed to normal system-level interrupt lines as well as to the MIP.MTIP inputs on the RISC-V cores."]
+    #[inline(always)]
+    pub const fn mtime_ctrl(self) -> crate::common::Reg<regs::MtimeCtrl, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(420usize) as _) }
+    }
+    #[doc = "Read/write access to the high half of RISC-V Machine-mode timer. This register is shared between both cores. If both cores write on the same cycle, core 1 takes precedence."]
+    #[inline(always)]
+    pub const fn mtime(self) -> crate::common::Reg<u32, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(432usize) as _) }
+    }
+    #[doc = "Read/write access to the high half of RISC-V Machine-mode timer. This register is shared between both cores. If both cores write on the same cycle, core 1 takes precedence."]
+    #[inline(always)]
+    pub const fn mtimeh(self) -> crate::common::Reg<u32, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(436usize) as _) }
+    }
+    #[doc = "Low half of RISC-V Machine-mode timer comparator. This register is core-local, i.e., each core gets a copy of this register, with the comparison result routed to its own interrupt line. The timer interrupt is asserted whenever MTIME is greater than or equal to MTIMECMP. This comparison is unsigned, and performed on the full 64-bit values."]
+    #[inline(always)]
+    pub const fn mtimecmp(self) -> crate::common::Reg<u32, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(440usize) as _) }
+    }
+    #[doc = "High half of RISC-V Machine-mode timer comparator. This register is core-local. The timer interrupt is asserted whenever MTIME is greater than or equal to MTIMECMP. This comparison is unsigned, and performed on the full 64-bit values."]
+    #[inline(always)]
+    pub const fn mtimecmph(self) -> crate::common::Reg<u32, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(444usize) as _) }
+    }
+    #[doc = "Control register for TMDS encoder."]
+    #[inline(always)]
+    pub const fn tmds_ctrl(self) -> crate::common::Reg<regs::TmdsCtrl, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(448usize) as _) }
+    }
+    #[doc = "Write-only access to the TMDS colour data register."]
+    #[inline(always)]
+    pub const fn tmds_wdata(self) -> crate::common::Reg<u32, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(452usize) as _) }
+    }
+    #[doc = "Get the encoding of one pixel's worth of colour data, packed into a 32-bit value (3x10-bit symbols). The PEEK alias does not shift the colour register when read, but still advances the running DC balance state of each encoder. This is useful for pixel doubling."]
+    #[inline(always)]
+    pub const fn tmds_peek_single(self) -> crate::common::Reg<u32, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(456usize) as _) }
+    }
+    #[doc = "Get the encoding of one pixel's worth of colour data, packed into a 32-bit value. The packing is 5 chunks of 3 lanes times 2 bits (30 bits total). Each chunk contains two bits of a TMDS symbol per lane. This format is intended for shifting out with the HSTX peripheral on RP2350. The POP alias shifts the colour register when read, as well as advancing the running DC balance state of each encoder."]
+    #[inline(always)]
+    pub const fn tmds_pop_single(self) -> crate::common::Reg<u32, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(460usize) as _) }
+    }
+    #[doc = "Get lane 0 of the encoding of two pixels' worth of colour data. Two 10-bit TMDS symbols are packed at the bottom of a 32-bit word. The PEEK alias does not shift the colour register when read, but still advances the lane 0 DC balance state. This is useful if all 3 lanes' worth of encode are to be read at once, rather than processing the entire scanline for one lane before moving to the next lane."]
+    #[inline(always)]
+    pub const fn tmds_peek_double_l0(self) -> crate::common::Reg<u32, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(464usize) as _) }
+    }
+    #[doc = "Get lane 0 of the encoding of two pixels' worth of colour data. Two 10-bit TMDS symbols are packed at the bottom of a 32-bit word. The POP alias shifts the colour register when read, according to the values of PIX_SHIFT and PIX2_NOSHIFT."]
+    #[inline(always)]
+    pub const fn tmds_pop_double_l0(self) -> crate::common::Reg<u32, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(468usize) as _) }
+    }
+    #[doc = "Get lane 1 of the encoding of two pixels' worth of colour data. Two 10-bit TMDS symbols are packed at the bottom of a 32-bit word. The PEEK alias does not shift the colour register when read, but still advances the lane 1 DC balance state. This is useful if all 3 lanes' worth of encode are to be read at once, rather than processing the entire scanline for one lane before moving to the next lane."]
+    #[inline(always)]
+    pub const fn tmds_peek_double_l1(self) -> crate::common::Reg<u32, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(472usize) as _) }
+    }
+    #[doc = "Get lane 1 of the encoding of two pixels' worth of colour data. Two 10-bit TMDS symbols are packed at the bottom of a 32-bit word. The POP alias shifts the colour register when read, according to the values of PIX_SHIFT and PIX2_NOSHIFT."]
+    #[inline(always)]
+    pub const fn tmds_pop_double_l1(self) -> crate::common::Reg<u32, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(476usize) as _) }
+    }
+    #[doc = "Get lane 2 of the encoding of two pixels' worth of colour data. Two 10-bit TMDS symbols are packed at the bottom of a 32-bit word. The PEEK alias does not shift the colour register when read, but still advances the lane 2 DC balance state. This is useful if all 3 lanes' worth of encode are to be read at once, rather than processing the entire scanline for one lane before moving to the next lane."]
+    #[inline(always)]
+    pub const fn tmds_peek_double_l2(self) -> crate::common::Reg<u32, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(480usize) as _) }
+    }
+    #[doc = "Get lane 2 of the encoding of two pixels' worth of colour data. Two 10-bit TMDS symbols are packed at the bottom of a 32-bit word. The POP alias shifts the colour register when read, according to the values of PIX_SHIFT and PIX2_NOSHIFT."]
+    #[inline(always)]
+    pub const fn tmds_pop_double_l2(self) -> crate::common::Reg<u32, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(484usize) as _) }
+    }
+}
+pub mod regs;
+pub mod vals;
diff --git a/src/rp2350/sio/regs.rs b/src/rp2350/sio/regs.rs
new file mode 100644
index 00000000..623f3c5d
--- /dev/null
+++ b/src/rp2350/sio/regs.rs
@@ -0,0 +1,991 @@
+#[doc = "Check and acknowledge doorbells posted to this core. This core's doorbell interrupt is asserted when any bit in this register is 1. Write 1 to each bit to clear that bit. The doorbell interrupt deasserts once all bits are cleared. Read to get status of doorbells currently asserted on this core."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct DoorbellInClr(pub u32);
+impl DoorbellInClr {
+    #[inline(always)]
+    pub const fn doorbell_in_clr(&self) -> u8 {
+        let val = (self.0 >> 0usize) & 0xff;
+        val as u8
+    }
+    #[inline(always)]
+    pub fn set_doorbell_in_clr(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize);
+    }
+}
+impl Default for DoorbellInClr {
+    #[inline(always)]
+    fn default() -> DoorbellInClr {
+        DoorbellInClr(0)
+    }
+}
+#[doc = "Write 1s to trigger doorbell interrupts on this core. Read to get status of doorbells currently asserted on this core."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct DoorbellInSet(pub u32);
+impl DoorbellInSet {
+    #[inline(always)]
+    pub const fn doorbell_in_set(&self) -> u8 {
+        let val = (self.0 >> 0usize) & 0xff;
+        val as u8
+    }
+    #[inline(always)]
+    pub fn set_doorbell_in_set(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize);
+    }
+}
+impl Default for DoorbellInSet {
+    #[inline(always)]
+    fn default() -> DoorbellInSet {
+        DoorbellInSet(0)
+    }
+}
+#[doc = "Clear doorbells which have been posted to the opposite core. This register is intended for debugging and initialisation purposes. Writing 1 to a bit in DOORBELL_OUT_CLR clears the corresponding bit in DOORBELL_IN on the opposite core. Clearing all bits will cause that core's doorbell interrupt to deassert. Since the usual order of events is for software to send events using DOORBELL_OUT_SET, and acknowledge incoming events by writing to DOORBELL_IN_CLR, this register should be used with caution to avoid race conditions. Reading returns the status of the doorbells currently asserted on the other core, i.e. is equivalent to that core reading its own DOORBELL_IN status."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct DoorbellOutClr(pub u32);
+impl DoorbellOutClr {
+    #[inline(always)]
+    pub const fn doorbell_out_clr(&self) -> u8 {
+        let val = (self.0 >> 0usize) & 0xff;
+        val as u8
+    }
+    #[inline(always)]
+    pub fn set_doorbell_out_clr(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize);
+    }
+}
+impl Default for DoorbellOutClr {
+    #[inline(always)]
+    fn default() -> DoorbellOutClr {
+        DoorbellOutClr(0)
+    }
+}
+#[doc = "Trigger a doorbell interrupt on the opposite core. Write 1 to a bit to set the corresponding bit in DOORBELL_IN on the opposite core. This raises the opposite core's doorbell interrupt. Read to get the status of the doorbells currently asserted on the opposite core. This is equivalent to that core reading its own DOORBELL_IN status."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct DoorbellOutSet(pub u32);
+impl DoorbellOutSet {
+    #[inline(always)]
+    pub const fn doorbell_out_set(&self) -> u8 {
+        let val = (self.0 >> 0usize) & 0xff;
+        val as u8
+    }
+    #[inline(always)]
+    pub fn set_doorbell_out_set(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize);
+    }
+}
+impl Default for DoorbellOutSet {
+    #[inline(always)]
+    fn default() -> DoorbellOutSet {
+        DoorbellOutSet(0)
+    }
+}
+#[doc = "Status register for inter-core FIFOs (mailboxes). There is one FIFO in the core 0 -> core 1 direction, and one core 1 -> core 0. Both are 32 bits wide and 8 words deep. Core 0 can see the read side of the 1->0 FIFO (RX), and the write side of 0->1 FIFO (TX). Core 1 can see the read side of the 0->1 FIFO (RX), and the write side of 1->0 FIFO (TX). The SIO IRQ for each core is the logical OR of the VLD, WOF and ROE fields of its FIFO_ST register."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct FifoSt(pub u32);
+impl FifoSt {
+    #[doc = "Value is 1 if this core's RX FIFO is not empty (i.e. if FIFO_RD is valid)"]
+    #[inline(always)]
+    pub const fn vld(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Value is 1 if this core's RX FIFO is not empty (i.e. if FIFO_RD is valid)"]
+    #[inline(always)]
+    pub fn set_vld(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[doc = "Value is 1 if this core's TX FIFO is not full (i.e. if FIFO_WR is ready for more data)"]
+    #[inline(always)]
+    pub const fn rdy(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Value is 1 if this core's TX FIFO is not full (i.e. if FIFO_WR is ready for more data)"]
+    #[inline(always)]
+    pub fn set_rdy(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+    #[doc = "Sticky flag indicating the TX FIFO was written when full. This write was ignored by the FIFO."]
+    #[inline(always)]
+    pub const fn wof(&self) -> bool {
+        let val = (self.0 >> 2usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Sticky flag indicating the TX FIFO was written when full. This write was ignored by the FIFO."]
+    #[inline(always)]
+    pub fn set_wof(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+    }
+    #[doc = "Sticky flag indicating the RX FIFO was read when empty. This read was ignored by the FIFO."]
+    #[inline(always)]
+    pub const fn roe(&self) -> bool {
+        let val = (self.0 >> 3usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Sticky flag indicating the RX FIFO was read when empty. This read was ignored by the FIFO."]
+    #[inline(always)]
+    pub fn set_roe(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
+    }
+}
+impl Default for FifoSt {
+    #[inline(always)]
+    fn default() -> FifoSt {
+        FifoSt(0)
+    }
+}
+#[doc = "Values written here are atomically added to ACCUM0 Reading yields lane 0's raw shift and mask value (BASE0 not added)."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Interp0accum0add(pub u32);
+impl Interp0accum0add {
+    #[inline(always)]
+    pub const fn interp0_accum0_add(&self) -> u32 {
+        let val = (self.0 >> 0usize) & 0x00ff_ffff;
+        val as u32
+    }
+    #[inline(always)]
+    pub fn set_interp0_accum0_add(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize);
+    }
+}
+impl Default for Interp0accum0add {
+    #[inline(always)]
+    fn default() -> Interp0accum0add {
+        Interp0accum0add(0)
+    }
+}
+#[doc = "Values written here are atomically added to ACCUM1 Reading yields lane 1's raw shift and mask value (BASE1 not added)."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Interp0accum1add(pub u32);
+impl Interp0accum1add {
+    #[inline(always)]
+    pub const fn interp0_accum1_add(&self) -> u32 {
+        let val = (self.0 >> 0usize) & 0x00ff_ffff;
+        val as u32
+    }
+    #[inline(always)]
+    pub fn set_interp0_accum1_add(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize);
+    }
+}
+impl Default for Interp0accum1add {
+    #[inline(always)]
+    fn default() -> Interp0accum1add {
+        Interp0accum1add(0)
+    }
+}
+#[doc = "Control register for lane 0"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Interp0ctrlLane0(pub u32);
+impl Interp0ctrlLane0 {
+    #[doc = "Right-rotate applied to accumulator before masking. By appropriately configuring the masks, left and right shifts can be synthesised."]
+    #[inline(always)]
+    pub const fn shift(&self) -> u8 {
+        let val = (self.0 >> 0usize) & 0x1f;
+        val as u8
+    }
+    #[doc = "Right-rotate applied to accumulator before masking. By appropriately configuring the masks, left and right shifts can be synthesised."]
+    #[inline(always)]
+    pub fn set_shift(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x1f << 0usize)) | (((val as u32) & 0x1f) << 0usize);
+    }
+    #[doc = "The least-significant bit allowed to pass by the mask (inclusive)"]
+    #[inline(always)]
+    pub const fn mask_lsb(&self) -> u8 {
+        let val = (self.0 >> 5usize) & 0x1f;
+        val as u8
+    }
+    #[doc = "The least-significant bit allowed to pass by the mask (inclusive)"]
+    #[inline(always)]
+    pub fn set_mask_lsb(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x1f << 5usize)) | (((val as u32) & 0x1f) << 5usize);
+    }
+    #[doc = "The most-significant bit allowed to pass by the mask (inclusive) Setting MSB < LSB may cause chip to turn inside-out"]
+    #[inline(always)]
+    pub const fn mask_msb(&self) -> u8 {
+        let val = (self.0 >> 10usize) & 0x1f;
+        val as u8
+    }
+    #[doc = "The most-significant bit allowed to pass by the mask (inclusive) Setting MSB < LSB may cause chip to turn inside-out"]
+    #[inline(always)]
+    pub fn set_mask_msb(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x1f << 10usize)) | (((val as u32) & 0x1f) << 10usize);
+    }
+    #[doc = "If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits before adding to BASE0, and LANE0 PEEK/POP appear extended to 32 bits when read by processor."]
+    #[inline(always)]
+    pub const fn signed(&self) -> bool {
+        let val = (self.0 >> 15usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits before adding to BASE0, and LANE0 PEEK/POP appear extended to 32 bits when read by processor."]
+    #[inline(always)]
+    pub fn set_signed(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize);
+    }
+    #[doc = "If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware. Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass)"]
+    #[inline(always)]
+    pub const fn cross_input(&self) -> bool {
+        let val = (self.0 >> 16usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware. Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass)"]
+    #[inline(always)]
+    pub fn set_cross_input(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
+    }
+    #[doc = "If 1, feed the opposite lane's result into this lane's accumulator on POP."]
+    #[inline(always)]
+    pub const fn cross_result(&self) -> bool {
+        let val = (self.0 >> 17usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, feed the opposite lane's result into this lane's accumulator on POP."]
+    #[inline(always)]
+    pub fn set_cross_result(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
+    }
+    #[doc = "If 1, mask + shift is bypassed for LANE0 result. This does not affect FULL result."]
+    #[inline(always)]
+    pub const fn add_raw(&self) -> bool {
+        let val = (self.0 >> 18usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, mask + shift is bypassed for LANE0 result. This does not affect FULL result."]
+    #[inline(always)]
+    pub fn set_add_raw(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize);
+    }
+    #[doc = "ORed into bits 29:28 of the lane result presented to the processor on the bus. No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence of pointers into flash or SRAM."]
+    #[inline(always)]
+    pub const fn force_msb(&self) -> u8 {
+        let val = (self.0 >> 19usize) & 0x03;
+        val as u8
+    }
+    #[doc = "ORed into bits 29:28 of the lane result presented to the processor on the bus. No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence of pointers into flash or SRAM."]
+    #[inline(always)]
+    pub fn set_force_msb(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x03 << 19usize)) | (((val as u32) & 0x03) << 19usize);
+    }
+    #[doc = "Only present on INTERP0 on each core. If BLEND mode is enabled: - LANE1 result is a linear interpolation between BASE0 and BASE1, controlled by the 8 LSBs of lane 1 shift and mask value (a fractional number between 0 and 255/256ths) - LANE0 result does not have BASE0 added (yields only the 8 LSBs of lane 1 shift+mask value) - FULL result does not have lane 1 shift+mask value added (BASE2 + lane 0 shift+mask) LANE1 SIGNED flag controls whether the interpolation is signed or unsigned."]
+    #[inline(always)]
+    pub const fn blend(&self) -> bool {
+        let val = (self.0 >> 21usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Only present on INTERP0 on each core. If BLEND mode is enabled: - LANE1 result is a linear interpolation between BASE0 and BASE1, controlled by the 8 LSBs of lane 1 shift and mask value (a fractional number between 0 and 255/256ths) - LANE0 result does not have BASE0 added (yields only the 8 LSBs of lane 1 shift+mask value) - FULL result does not have lane 1 shift+mask value added (BASE2 + lane 0 shift+mask) LANE1 SIGNED flag controls whether the interpolation is signed or unsigned."]
+    #[inline(always)]
+    pub fn set_blend(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 21usize)) | (((val as u32) & 0x01) << 21usize);
+    }
+    #[doc = "Indicates if any masked-off MSBs in ACCUM0 are set."]
+    #[inline(always)]
+    pub const fn overf0(&self) -> bool {
+        let val = (self.0 >> 23usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Indicates if any masked-off MSBs in ACCUM0 are set."]
+    #[inline(always)]
+    pub fn set_overf0(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 23usize)) | (((val as u32) & 0x01) << 23usize);
+    }
+    #[doc = "Indicates if any masked-off MSBs in ACCUM1 are set."]
+    #[inline(always)]
+    pub const fn overf1(&self) -> bool {
+        let val = (self.0 >> 24usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Indicates if any masked-off MSBs in ACCUM1 are set."]
+    #[inline(always)]
+    pub fn set_overf1(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 24usize)) | (((val as u32) & 0x01) << 24usize);
+    }
+    #[doc = "Set if either OVERF0 or OVERF1 is set."]
+    #[inline(always)]
+    pub const fn overf(&self) -> bool {
+        let val = (self.0 >> 25usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Set if either OVERF0 or OVERF1 is set."]
+    #[inline(always)]
+    pub fn set_overf(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 25usize)) | (((val as u32) & 0x01) << 25usize);
+    }
+}
+impl Default for Interp0ctrlLane0 {
+    #[inline(always)]
+    fn default() -> Interp0ctrlLane0 {
+        Interp0ctrlLane0(0)
+    }
+}
+#[doc = "Control register for lane 1"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Interp0ctrlLane1(pub u32);
+impl Interp0ctrlLane1 {
+    #[doc = "Right-rotate applied to accumulator before masking. By appropriately configuring the masks, left and right shifts can be synthesised."]
+    #[inline(always)]
+    pub const fn shift(&self) -> u8 {
+        let val = (self.0 >> 0usize) & 0x1f;
+        val as u8
+    }
+    #[doc = "Right-rotate applied to accumulator before masking. By appropriately configuring the masks, left and right shifts can be synthesised."]
+    #[inline(always)]
+    pub fn set_shift(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x1f << 0usize)) | (((val as u32) & 0x1f) << 0usize);
+    }
+    #[doc = "The least-significant bit allowed to pass by the mask (inclusive)"]
+    #[inline(always)]
+    pub const fn mask_lsb(&self) -> u8 {
+        let val = (self.0 >> 5usize) & 0x1f;
+        val as u8
+    }
+    #[doc = "The least-significant bit allowed to pass by the mask (inclusive)"]
+    #[inline(always)]
+    pub fn set_mask_lsb(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x1f << 5usize)) | (((val as u32) & 0x1f) << 5usize);
+    }
+    #[doc = "The most-significant bit allowed to pass by the mask (inclusive) Setting MSB < LSB may cause chip to turn inside-out"]
+    #[inline(always)]
+    pub const fn mask_msb(&self) -> u8 {
+        let val = (self.0 >> 10usize) & 0x1f;
+        val as u8
+    }
+    #[doc = "The most-significant bit allowed to pass by the mask (inclusive) Setting MSB < LSB may cause chip to turn inside-out"]
+    #[inline(always)]
+    pub fn set_mask_msb(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x1f << 10usize)) | (((val as u32) & 0x1f) << 10usize);
+    }
+    #[doc = "If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits before adding to BASE1, and LANE1 PEEK/POP appear extended to 32 bits when read by processor."]
+    #[inline(always)]
+    pub const fn signed(&self) -> bool {
+        let val = (self.0 >> 15usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits before adding to BASE1, and LANE1 PEEK/POP appear extended to 32 bits when read by processor."]
+    #[inline(always)]
+    pub fn set_signed(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize);
+    }
+    #[doc = "If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware. Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass)"]
+    #[inline(always)]
+    pub const fn cross_input(&self) -> bool {
+        let val = (self.0 >> 16usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware. Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass)"]
+    #[inline(always)]
+    pub fn set_cross_input(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
+    }
+    #[doc = "If 1, feed the opposite lane's result into this lane's accumulator on POP."]
+    #[inline(always)]
+    pub const fn cross_result(&self) -> bool {
+        let val = (self.0 >> 17usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, feed the opposite lane's result into this lane's accumulator on POP."]
+    #[inline(always)]
+    pub fn set_cross_result(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
+    }
+    #[doc = "If 1, mask + shift is bypassed for LANE1 result. This does not affect FULL result."]
+    #[inline(always)]
+    pub const fn add_raw(&self) -> bool {
+        let val = (self.0 >> 18usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, mask + shift is bypassed for LANE1 result. This does not affect FULL result."]
+    #[inline(always)]
+    pub fn set_add_raw(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize);
+    }
+    #[doc = "ORed into bits 29:28 of the lane result presented to the processor on the bus. No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence of pointers into flash or SRAM."]
+    #[inline(always)]
+    pub const fn force_msb(&self) -> u8 {
+        let val = (self.0 >> 19usize) & 0x03;
+        val as u8
+    }
+    #[doc = "ORed into bits 29:28 of the lane result presented to the processor on the bus. No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence of pointers into flash or SRAM."]
+    #[inline(always)]
+    pub fn set_force_msb(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x03 << 19usize)) | (((val as u32) & 0x03) << 19usize);
+    }
+}
+impl Default for Interp0ctrlLane1 {
+    #[inline(always)]
+    fn default() -> Interp0ctrlLane1 {
+        Interp0ctrlLane1(0)
+    }
+}
+#[doc = "Values written here are atomically added to ACCUM0 Reading yields lane 0's raw shift and mask value (BASE0 not added)."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Interp1accum0add(pub u32);
+impl Interp1accum0add {
+    #[inline(always)]
+    pub const fn interp1_accum0_add(&self) -> u32 {
+        let val = (self.0 >> 0usize) & 0x00ff_ffff;
+        val as u32
+    }
+    #[inline(always)]
+    pub fn set_interp1_accum0_add(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize);
+    }
+}
+impl Default for Interp1accum0add {
+    #[inline(always)]
+    fn default() -> Interp1accum0add {
+        Interp1accum0add(0)
+    }
+}
+#[doc = "Values written here are atomically added to ACCUM1 Reading yields lane 1's raw shift and mask value (BASE1 not added)."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Interp1accum1add(pub u32);
+impl Interp1accum1add {
+    #[inline(always)]
+    pub const fn interp1_accum1_add(&self) -> u32 {
+        let val = (self.0 >> 0usize) & 0x00ff_ffff;
+        val as u32
+    }
+    #[inline(always)]
+    pub fn set_interp1_accum1_add(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize);
+    }
+}
+impl Default for Interp1accum1add {
+    #[inline(always)]
+    fn default() -> Interp1accum1add {
+        Interp1accum1add(0)
+    }
+}
+#[doc = "Control register for lane 0"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Interp1ctrlLane0(pub u32);
+impl Interp1ctrlLane0 {
+    #[doc = "Right-rotate applied to accumulator before masking. By appropriately configuring the masks, left and right shifts can be synthesised."]
+    #[inline(always)]
+    pub const fn shift(&self) -> u8 {
+        let val = (self.0 >> 0usize) & 0x1f;
+        val as u8
+    }
+    #[doc = "Right-rotate applied to accumulator before masking. By appropriately configuring the masks, left and right shifts can be synthesised."]
+    #[inline(always)]
+    pub fn set_shift(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x1f << 0usize)) | (((val as u32) & 0x1f) << 0usize);
+    }
+    #[doc = "The least-significant bit allowed to pass by the mask (inclusive)"]
+    #[inline(always)]
+    pub const fn mask_lsb(&self) -> u8 {
+        let val = (self.0 >> 5usize) & 0x1f;
+        val as u8
+    }
+    #[doc = "The least-significant bit allowed to pass by the mask (inclusive)"]
+    #[inline(always)]
+    pub fn set_mask_lsb(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x1f << 5usize)) | (((val as u32) & 0x1f) << 5usize);
+    }
+    #[doc = "The most-significant bit allowed to pass by the mask (inclusive) Setting MSB < LSB may cause chip to turn inside-out"]
+    #[inline(always)]
+    pub const fn mask_msb(&self) -> u8 {
+        let val = (self.0 >> 10usize) & 0x1f;
+        val as u8
+    }
+    #[doc = "The most-significant bit allowed to pass by the mask (inclusive) Setting MSB < LSB may cause chip to turn inside-out"]
+    #[inline(always)]
+    pub fn set_mask_msb(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x1f << 10usize)) | (((val as u32) & 0x1f) << 10usize);
+    }
+    #[doc = "If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits before adding to BASE0, and LANE0 PEEK/POP appear extended to 32 bits when read by processor."]
+    #[inline(always)]
+    pub const fn signed(&self) -> bool {
+        let val = (self.0 >> 15usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits before adding to BASE0, and LANE0 PEEK/POP appear extended to 32 bits when read by processor."]
+    #[inline(always)]
+    pub fn set_signed(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize);
+    }
+    #[doc = "If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware. Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass)"]
+    #[inline(always)]
+    pub const fn cross_input(&self) -> bool {
+        let val = (self.0 >> 16usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware. Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass)"]
+    #[inline(always)]
+    pub fn set_cross_input(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
+    }
+    #[doc = "If 1, feed the opposite lane's result into this lane's accumulator on POP."]
+    #[inline(always)]
+    pub const fn cross_result(&self) -> bool {
+        let val = (self.0 >> 17usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, feed the opposite lane's result into this lane's accumulator on POP."]
+    #[inline(always)]
+    pub fn set_cross_result(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
+    }
+    #[doc = "If 1, mask + shift is bypassed for LANE0 result. This does not affect FULL result."]
+    #[inline(always)]
+    pub const fn add_raw(&self) -> bool {
+        let val = (self.0 >> 18usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, mask + shift is bypassed for LANE0 result. This does not affect FULL result."]
+    #[inline(always)]
+    pub fn set_add_raw(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize);
+    }
+    #[doc = "ORed into bits 29:28 of the lane result presented to the processor on the bus. No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence of pointers into flash or SRAM."]
+    #[inline(always)]
+    pub const fn force_msb(&self) -> u8 {
+        let val = (self.0 >> 19usize) & 0x03;
+        val as u8
+    }
+    #[doc = "ORed into bits 29:28 of the lane result presented to the processor on the bus. No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence of pointers into flash or SRAM."]
+    #[inline(always)]
+    pub fn set_force_msb(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x03 << 19usize)) | (((val as u32) & 0x03) << 19usize);
+    }
+    #[doc = "Only present on INTERP1 on each core. If CLAMP mode is enabled: - LANE0 result is shifted and masked ACCUM0, clamped by a lower bound of BASE0 and an upper bound of BASE1. - Signedness of these comparisons is determined by LANE0_CTRL_SIGNED"]
+    #[inline(always)]
+    pub const fn clamp(&self) -> bool {
+        let val = (self.0 >> 22usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Only present on INTERP1 on each core. If CLAMP mode is enabled: - LANE0 result is shifted and masked ACCUM0, clamped by a lower bound of BASE0 and an upper bound of BASE1. - Signedness of these comparisons is determined by LANE0_CTRL_SIGNED"]
+    #[inline(always)]
+    pub fn set_clamp(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 22usize)) | (((val as u32) & 0x01) << 22usize);
+    }
+    #[doc = "Indicates if any masked-off MSBs in ACCUM0 are set."]
+    #[inline(always)]
+    pub const fn overf0(&self) -> bool {
+        let val = (self.0 >> 23usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Indicates if any masked-off MSBs in ACCUM0 are set."]
+    #[inline(always)]
+    pub fn set_overf0(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 23usize)) | (((val as u32) & 0x01) << 23usize);
+    }
+    #[doc = "Indicates if any masked-off MSBs in ACCUM1 are set."]
+    #[inline(always)]
+    pub const fn overf1(&self) -> bool {
+        let val = (self.0 >> 24usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Indicates if any masked-off MSBs in ACCUM1 are set."]
+    #[inline(always)]
+    pub fn set_overf1(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 24usize)) | (((val as u32) & 0x01) << 24usize);
+    }
+    #[doc = "Set if either OVERF0 or OVERF1 is set."]
+    #[inline(always)]
+    pub const fn overf(&self) -> bool {
+        let val = (self.0 >> 25usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Set if either OVERF0 or OVERF1 is set."]
+    #[inline(always)]
+    pub fn set_overf(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 25usize)) | (((val as u32) & 0x01) << 25usize);
+    }
+}
+impl Default for Interp1ctrlLane0 {
+    #[inline(always)]
+    fn default() -> Interp1ctrlLane0 {
+        Interp1ctrlLane0(0)
+    }
+}
+#[doc = "Control register for lane 1"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Interp1ctrlLane1(pub u32);
+impl Interp1ctrlLane1 {
+    #[doc = "Right-rotate applied to accumulator before masking. By appropriately configuring the masks, left and right shifts can be synthesised."]
+    #[inline(always)]
+    pub const fn shift(&self) -> u8 {
+        let val = (self.0 >> 0usize) & 0x1f;
+        val as u8
+    }
+    #[doc = "Right-rotate applied to accumulator before masking. By appropriately configuring the masks, left and right shifts can be synthesised."]
+    #[inline(always)]
+    pub fn set_shift(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x1f << 0usize)) | (((val as u32) & 0x1f) << 0usize);
+    }
+    #[doc = "The least-significant bit allowed to pass by the mask (inclusive)"]
+    #[inline(always)]
+    pub const fn mask_lsb(&self) -> u8 {
+        let val = (self.0 >> 5usize) & 0x1f;
+        val as u8
+    }
+    #[doc = "The least-significant bit allowed to pass by the mask (inclusive)"]
+    #[inline(always)]
+    pub fn set_mask_lsb(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x1f << 5usize)) | (((val as u32) & 0x1f) << 5usize);
+    }
+    #[doc = "The most-significant bit allowed to pass by the mask (inclusive) Setting MSB < LSB may cause chip to turn inside-out"]
+    #[inline(always)]
+    pub const fn mask_msb(&self) -> u8 {
+        let val = (self.0 >> 10usize) & 0x1f;
+        val as u8
+    }
+    #[doc = "The most-significant bit allowed to pass by the mask (inclusive) Setting MSB < LSB may cause chip to turn inside-out"]
+    #[inline(always)]
+    pub fn set_mask_msb(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x1f << 10usize)) | (((val as u32) & 0x1f) << 10usize);
+    }
+    #[doc = "If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits before adding to BASE1, and LANE1 PEEK/POP appear extended to 32 bits when read by processor."]
+    #[inline(always)]
+    pub const fn signed(&self) -> bool {
+        let val = (self.0 >> 15usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits before adding to BASE1, and LANE1 PEEK/POP appear extended to 32 bits when read by processor."]
+    #[inline(always)]
+    pub fn set_signed(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize);
+    }
+    #[doc = "If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware. Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass)"]
+    #[inline(always)]
+    pub const fn cross_input(&self) -> bool {
+        let val = (self.0 >> 16usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware. Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass)"]
+    #[inline(always)]
+    pub fn set_cross_input(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
+    }
+    #[doc = "If 1, feed the opposite lane's result into this lane's accumulator on POP."]
+    #[inline(always)]
+    pub const fn cross_result(&self) -> bool {
+        let val = (self.0 >> 17usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, feed the opposite lane's result into this lane's accumulator on POP."]
+    #[inline(always)]
+    pub fn set_cross_result(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
+    }
+    #[doc = "If 1, mask + shift is bypassed for LANE1 result. This does not affect FULL result."]
+    #[inline(always)]
+    pub const fn add_raw(&self) -> bool {
+        let val = (self.0 >> 18usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, mask + shift is bypassed for LANE1 result. This does not affect FULL result."]
+    #[inline(always)]
+    pub fn set_add_raw(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize);
+    }
+    #[doc = "ORed into bits 29:28 of the lane result presented to the processor on the bus. No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence of pointers into flash or SRAM."]
+    #[inline(always)]
+    pub const fn force_msb(&self) -> u8 {
+        let val = (self.0 >> 19usize) & 0x03;
+        val as u8
+    }
+    #[doc = "ORed into bits 29:28 of the lane result presented to the processor on the bus. No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence of pointers into flash or SRAM."]
+    #[inline(always)]
+    pub fn set_force_msb(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x03 << 19usize)) | (((val as u32) & 0x03) << 19usize);
+    }
+}
+impl Default for Interp1ctrlLane1 {
+    #[inline(always)]
+    fn default() -> Interp1ctrlLane1 {
+        Interp1ctrlLane1(0)
+    }
+}
+#[doc = "Control register for the RISC-V 64-bit Machine-mode timer. This timer is only present in the Secure SIO, so is only accessible to an Arm core in Secure mode or a RISC-V core in Machine mode. Note whilst this timer follows the RISC-V privileged specification, it is equally usable by the Arm cores. The interrupts are routed to normal system-level interrupt lines as well as to the MIP.MTIP inputs on the RISC-V cores."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct MtimeCtrl(pub u32);
+impl MtimeCtrl {
+    #[doc = "Timer enable bit. When 0, the timer will not increment automatically."]
+    #[inline(always)]
+    pub const fn en(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Timer enable bit. When 0, the timer will not increment automatically."]
+    #[inline(always)]
+    pub fn set_en(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[doc = "If 1, increment the timer every cycle (i.e. run directly from the system clock), rather than incrementing on the system-level timer tick input."]
+    #[inline(always)]
+    pub const fn fullspeed(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, increment the timer every cycle (i.e. run directly from the system clock), rather than incrementing on the system-level timer tick input."]
+    #[inline(always)]
+    pub fn set_fullspeed(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+    #[doc = "If 1, the timer pauses when core 0 is in the debug halt state."]
+    #[inline(always)]
+    pub const fn dbgpause_core0(&self) -> bool {
+        let val = (self.0 >> 2usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, the timer pauses when core 0 is in the debug halt state."]
+    #[inline(always)]
+    pub fn set_dbgpause_core0(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+    }
+    #[doc = "If 1, the timer pauses when core 1 is in the debug halt state."]
+    #[inline(always)]
+    pub const fn dbgpause_core1(&self) -> bool {
+        let val = (self.0 >> 3usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, the timer pauses when core 1 is in the debug halt state."]
+    #[inline(always)]
+    pub fn set_dbgpause_core1(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
+    }
+}
+impl Default for MtimeCtrl {
+    #[inline(always)]
+    fn default() -> MtimeCtrl {
+        MtimeCtrl(0)
+    }
+}
+#[doc = "Detach certain core-local peripherals from Secure SIO, and attach them to Non-secure SIO, so that Non-secure software can use them. Attempting to access one of these peripherals from the Secure SIO when it is attached to the Non-secure SIO, or vice versa, will generate a bus error. This register is per-core, and is only present on the Secure SIO. Most SIO hardware is duplicated across the Secure and Non-secure SIO, so is not listed in this register."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct PeriNonsec(pub u32);
+impl PeriNonsec {
+    #[doc = "If 1, detach interpolator 0 (of this core) from the Secure SIO, and attach to the Non-secure SIO."]
+    #[inline(always)]
+    pub const fn interp0(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, detach interpolator 0 (of this core) from the Secure SIO, and attach to the Non-secure SIO."]
+    #[inline(always)]
+    pub fn set_interp0(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[doc = "If 1, detach interpolator 1 (of this core) from the Secure SIO, and attach to the Non-secure SIO."]
+    #[inline(always)]
+    pub const fn interp1(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, detach interpolator 1 (of this core) from the Secure SIO, and attach to the Non-secure SIO."]
+    #[inline(always)]
+    pub fn set_interp1(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+    #[doc = "IF 1, detach TMDS encoder (of this core) from the Secure SIO, and attach to the Non-secure SIO."]
+    #[inline(always)]
+    pub const fn tmds(&self) -> bool {
+        let val = (self.0 >> 5usize) & 0x01;
+        val != 0
+    }
+    #[doc = "IF 1, detach TMDS encoder (of this core) from the Secure SIO, and attach to the Non-secure SIO."]
+    #[inline(always)]
+    pub fn set_tmds(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
+    }
+}
+impl Default for PeriNonsec {
+    #[inline(always)]
+    fn default() -> PeriNonsec {
+        PeriNonsec(0)
+    }
+}
+#[doc = "Control the assertion of the standard software interrupt (MIP.MSIP) on the RISC-V cores. Unlike the RISC-V timer, this interrupt is not routed to a normal system-level interrupt line, so can not be used by the Arm cores. It is safe for both cores to write to this register on the same cycle. The set/clear effect is accumulated across both cores, and then applied. If a flag is both set and cleared on the same cycle, only the set takes effect."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct RiscvSoftirq(pub u32);
+impl RiscvSoftirq {
+    #[doc = "Write 1 to atomically set the core 0 software interrupt flag. Read to get the status of this flag."]
+    #[inline(always)]
+    pub const fn core0_set(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Write 1 to atomically set the core 0 software interrupt flag. Read to get the status of this flag."]
+    #[inline(always)]
+    pub fn set_core0_set(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[doc = "Write 1 to atomically set the core 1 software interrupt flag. Read to get the status of this flag."]
+    #[inline(always)]
+    pub const fn core1_set(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Write 1 to atomically set the core 1 software interrupt flag. Read to get the status of this flag."]
+    #[inline(always)]
+    pub fn set_core1_set(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+    #[doc = "Write 1 to atomically clear the core 0 software interrupt flag. Read to get the status of this flag."]
+    #[inline(always)]
+    pub const fn core0_clr(&self) -> bool {
+        let val = (self.0 >> 8usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Write 1 to atomically clear the core 0 software interrupt flag. Read to get the status of this flag."]
+    #[inline(always)]
+    pub fn set_core0_clr(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
+    }
+    #[doc = "Write 1 to atomically clear the core 1 software interrupt flag. Read to get the status of this flag."]
+    #[inline(always)]
+    pub const fn core1_clr(&self) -> bool {
+        let val = (self.0 >> 9usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Write 1 to atomically clear the core 1 software interrupt flag. Read to get the status of this flag."]
+    #[inline(always)]
+    pub fn set_core1_clr(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
+    }
+}
+impl Default for RiscvSoftirq {
+    #[inline(always)]
+    fn default() -> RiscvSoftirq {
+        RiscvSoftirq(0)
+    }
+}
+#[doc = "Control register for TMDS encoder."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct TmdsCtrl(pub u32);
+impl TmdsCtrl {
+    #[doc = "Right-rotate the 16 LSBs of the colour accumulator by 0-15 bits, in order to get the MSB of the lane 0 (blue) colour data aligned with the MSB of the 8-bit encoder input. For example, for RGB565 (red most significant), blue is bits 4:0, so should be right-rotated by 13 to align with bits 7:3 of the encoder input."]
+    #[inline(always)]
+    pub const fn l0_rot(&self) -> u8 {
+        let val = (self.0 >> 0usize) & 0x0f;
+        val as u8
+    }
+    #[doc = "Right-rotate the 16 LSBs of the colour accumulator by 0-15 bits, in order to get the MSB of the lane 0 (blue) colour data aligned with the MSB of the 8-bit encoder input. For example, for RGB565 (red most significant), blue is bits 4:0, so should be right-rotated by 13 to align with bits 7:3 of the encoder input."]
+    #[inline(always)]
+    pub fn set_l0_rot(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize);
+    }
+    #[doc = "Right-rotate the 16 LSBs of the colour accumulator by 0-15 bits, in order to get the MSB of the lane 1 (green) colour data aligned with the MSB of the 8-bit encoder input. For example, for RGB565, green is bits 10:5, so should be right-rotated by 3 bits to align with bits 7:2 of the encoder input."]
+    #[inline(always)]
+    pub const fn l1_rot(&self) -> u8 {
+        let val = (self.0 >> 4usize) & 0x0f;
+        val as u8
+    }
+    #[doc = "Right-rotate the 16 LSBs of the colour accumulator by 0-15 bits, in order to get the MSB of the lane 1 (green) colour data aligned with the MSB of the 8-bit encoder input. For example, for RGB565, green is bits 10:5, so should be right-rotated by 3 bits to align with bits 7:2 of the encoder input."]
+    #[inline(always)]
+    pub fn set_l1_rot(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x0f << 4usize)) | (((val as u32) & 0x0f) << 4usize);
+    }
+    #[doc = "Right-rotate the 16 LSBs of the colour accumulator by 0-15 bits, in order to get the MSB of the lane 2 (red) colour data aligned with the MSB of the 8-bit encoder input. For example, for RGB565 (red most significant), red is bits 15:11, so should be right-rotated by 8 bits to align with bits 7:3 of the encoder input."]
+    #[inline(always)]
+    pub const fn l2_rot(&self) -> u8 {
+        let val = (self.0 >> 8usize) & 0x0f;
+        val as u8
+    }
+    #[doc = "Right-rotate the 16 LSBs of the colour accumulator by 0-15 bits, in order to get the MSB of the lane 2 (red) colour data aligned with the MSB of the 8-bit encoder input. For example, for RGB565 (red most significant), red is bits 15:11, so should be right-rotated by 8 bits to align with bits 7:3 of the encoder input."]
+    #[inline(always)]
+    pub fn set_l2_rot(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x0f << 8usize)) | (((val as u32) & 0x0f) << 8usize);
+    }
+    #[doc = "Number of valid colour MSBs for lane 0 (1-8 bits, encoded as 0 through 7). Remaining LSBs are masked to 0 after the rotate."]
+    #[inline(always)]
+    pub const fn l0_nbits(&self) -> u8 {
+        let val = (self.0 >> 12usize) & 0x07;
+        val as u8
+    }
+    #[doc = "Number of valid colour MSBs for lane 0 (1-8 bits, encoded as 0 through 7). Remaining LSBs are masked to 0 after the rotate."]
+    #[inline(always)]
+    pub fn set_l0_nbits(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x07 << 12usize)) | (((val as u32) & 0x07) << 12usize);
+    }
+    #[doc = "Number of valid colour MSBs for lane 1 (1-8 bits, encoded as 0 through 7). Remaining LSBs are masked to 0 after the rotate."]
+    #[inline(always)]
+    pub const fn l1_nbits(&self) -> u8 {
+        let val = (self.0 >> 15usize) & 0x07;
+        val as u8
+    }
+    #[doc = "Number of valid colour MSBs for lane 1 (1-8 bits, encoded as 0 through 7). Remaining LSBs are masked to 0 after the rotate."]
+    #[inline(always)]
+    pub fn set_l1_nbits(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x07 << 15usize)) | (((val as u32) & 0x07) << 15usize);
+    }
+    #[doc = "Number of valid colour MSBs for lane 2 (1-8 bits, encoded as 0 through 7). Remaining LSBs are masked to 0 after the rotate."]
+    #[inline(always)]
+    pub const fn l2_nbits(&self) -> u8 {
+        let val = (self.0 >> 18usize) & 0x07;
+        val as u8
+    }
+    #[doc = "Number of valid colour MSBs for lane 2 (1-8 bits, encoded as 0 through 7). Remaining LSBs are masked to 0 after the rotate."]
+    #[inline(always)]
+    pub fn set_l2_nbits(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x07 << 18usize)) | (((val as u32) & 0x07) << 18usize);
+    }
+    #[doc = "Enable lane interleaving for reads of PEEK_SINGLE/POP_SINGLE. When interleaving is disabled, each of the 3 symbols appears as a contiguous 10-bit field, with lane 0 being the least-significant and starting at bit 0 of the register. When interleaving is enabled, the symbols are packed into 5 chunks of 3 lanes times 2 bits (30 bits total). Each chunk contains two bits of a TMDS symbol per lane, with lane 0 being the least significant."]
+    #[inline(always)]
+    pub const fn interleave(&self) -> bool {
+        let val = (self.0 >> 23usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Enable lane interleaving for reads of PEEK_SINGLE/POP_SINGLE. When interleaving is disabled, each of the 3 symbols appears as a contiguous 10-bit field, with lane 0 being the least-significant and starting at bit 0 of the register. When interleaving is enabled, the symbols are packed into 5 chunks of 3 lanes times 2 bits (30 bits total). Each chunk contains two bits of a TMDS symbol per lane, with lane 0 being the least significant."]
+    #[inline(always)]
+    pub fn set_interleave(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 23usize)) | (((val as u32) & 0x01) << 23usize);
+    }
+    #[doc = "Shift applied to the colour data register with each read of a POP alias register. Reading from the POP_SINGLE register, or reading from the POP_DOUBLE register with PIX2_NOSHIFT set (for pixel doubling), shifts by the indicated amount. Reading from a POP_DOUBLE register when PIX2_NOSHIFT is clear will shift by double the indicated amount. (Shift by 32 means no shift.)"]
+    #[inline(always)]
+    pub const fn pix_shift(&self) -> super::vals::PixShift {
+        let val = (self.0 >> 24usize) & 0x07;
+        super::vals::PixShift::from_bits(val as u8)
+    }
+    #[doc = "Shift applied to the colour data register with each read of a POP alias register. Reading from the POP_SINGLE register, or reading from the POP_DOUBLE register with PIX2_NOSHIFT set (for pixel doubling), shifts by the indicated amount. Reading from a POP_DOUBLE register when PIX2_NOSHIFT is clear will shift by double the indicated amount. (Shift by 32 means no shift.)"]
+    #[inline(always)]
+    pub fn set_pix_shift(&mut self, val: super::vals::PixShift) {
+        self.0 = (self.0 & !(0x07 << 24usize)) | (((val.to_bits() as u32) & 0x07) << 24usize);
+    }
+    #[doc = "When encoding two pixels's worth of symbols in one cycle (a read of a PEEK/POP_DOUBLE register), the second encoder sees a shifted version of the colour data register. This control disables that shift, so that both encoder layers see the same pixel data. This is used for pixel doubling."]
+    #[inline(always)]
+    pub const fn pix2_noshift(&self) -> bool {
+        let val = (self.0 >> 27usize) & 0x01;
+        val != 0
+    }
+    #[doc = "When encoding two pixels's worth of symbols in one cycle (a read of a PEEK/POP_DOUBLE register), the second encoder sees a shifted version of the colour data register. This control disables that shift, so that both encoder layers see the same pixel data. This is used for pixel doubling."]
+    #[inline(always)]
+    pub fn set_pix2_noshift(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 27usize)) | (((val as u32) & 0x01) << 27usize);
+    }
+    #[doc = "Clear the running DC balance state of the TMDS encoders. This bit should be written once at the beginning of each scanline."]
+    #[inline(always)]
+    pub const fn clear_balance(&self) -> bool {
+        let val = (self.0 >> 28usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Clear the running DC balance state of the TMDS encoders. This bit should be written once at the beginning of each scanline."]
+    #[inline(always)]
+    pub fn set_clear_balance(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 28usize)) | (((val as u32) & 0x01) << 28usize);
+    }
+}
+impl Default for TmdsCtrl {
+    #[inline(always)]
+    fn default() -> TmdsCtrl {
+        TmdsCtrl(0)
+    }
+}
diff --git a/src/rp2350/sio/vals.rs b/src/rp2350/sio/vals.rs
new file mode 100644
index 00000000..1ffa3eac
--- /dev/null
+++ b/src/rp2350/sio/vals.rs
@@ -0,0 +1,40 @@
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum PixShift {
+    #[doc = "Do not shift the colour data register."]
+    _0 = 0,
+    #[doc = "Shift the colour data register by 1 bit"]
+    _1 = 0x01,
+    #[doc = "Shift the colour data register by 2 bits"]
+    _2 = 0x02,
+    #[doc = "Shift the colour data register by 4 bits"]
+    _4 = 0x03,
+    #[doc = "Shift the colour data register by 8 bits"]
+    _8 = 0x04,
+    #[doc = "Shift the colour data register by 16 bits"]
+    _16 = 0x05,
+    _RESERVED_6 = 0x06,
+    _RESERVED_7 = 0x07,
+}
+impl PixShift {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> PixShift {
+        unsafe { core::mem::transmute(val & 0x07) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for PixShift {
+    #[inline(always)]
+    fn from(val: u8) -> PixShift {
+        PixShift::from_bits(val)
+    }
+}
+impl From<PixShift> for u8 {
+    #[inline(always)]
+    fn from(val: PixShift) -> u8 {
+        PixShift::to_bits(val)
+    }
+}
diff --git a/src/rp2350/spi.rs b/src/rp2350/spi.rs
new file mode 100644
index 00000000..0a4f215e
--- /dev/null
+++ b/src/rp2350/spi.rs
@@ -0,0 +1,107 @@
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Spi {
+    ptr: *mut u8,
+}
+unsafe impl Send for Spi {}
+unsafe impl Sync for Spi {}
+impl Spi {
+    #[inline(always)]
+    pub const unsafe fn from_ptr(ptr: *mut ()) -> Self {
+        Self { ptr: ptr as _ }
+    }
+    #[inline(always)]
+    pub const fn as_ptr(&self) -> *mut () {
+        self.ptr as _
+    }
+    #[doc = "Control register 0, SSPCR0 on page 3-4"]
+    #[inline(always)]
+    pub const fn cr0(self) -> crate::common::Reg<regs::Cr0, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(0usize) as _) }
+    }
+    #[doc = "Control register 1, SSPCR1 on page 3-5"]
+    #[inline(always)]
+    pub const fn cr1(self) -> crate::common::Reg<regs::Cr1, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(4usize) as _) }
+    }
+    #[doc = "Data register, SSPDR on page 3-6"]
+    #[inline(always)]
+    pub const fn dr(self) -> crate::common::Reg<regs::Dr, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(8usize) as _) }
+    }
+    #[doc = "Status register, SSPSR on page 3-7"]
+    #[inline(always)]
+    pub const fn sr(self) -> crate::common::Reg<regs::Sr, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(12usize) as _) }
+    }
+    #[doc = "Clock prescale register, SSPCPSR on page 3-8"]
+    #[inline(always)]
+    pub const fn cpsr(self) -> crate::common::Reg<regs::Cpsr, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(16usize) as _) }
+    }
+    #[doc = "Interrupt mask set or clear register, SSPIMSC on page 3-9"]
+    #[inline(always)]
+    pub const fn imsc(self) -> crate::common::Reg<regs::Imsc, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(20usize) as _) }
+    }
+    #[doc = "Raw interrupt status register, SSPRIS on page 3-10"]
+    #[inline(always)]
+    pub const fn ris(self) -> crate::common::Reg<regs::Ris, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(24usize) as _) }
+    }
+    #[doc = "Masked interrupt status register, SSPMIS on page 3-11"]
+    #[inline(always)]
+    pub const fn mis(self) -> crate::common::Reg<regs::Mis, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(28usize) as _) }
+    }
+    #[doc = "Interrupt clear register, SSPICR on page 3-11"]
+    #[inline(always)]
+    pub const fn icr(self) -> crate::common::Reg<regs::Icr, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(32usize) as _) }
+    }
+    #[doc = "DMA control register, SSPDMACR on page 3-12"]
+    #[inline(always)]
+    pub const fn dmacr(self) -> crate::common::Reg<regs::Dmacr, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(36usize) as _) }
+    }
+    #[doc = "Peripheral identification registers, SSPPeriphID0-3 on page 3-13"]
+    #[inline(always)]
+    pub const fn periphid0(self) -> crate::common::Reg<regs::Periphid0, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(4064usize) as _) }
+    }
+    #[doc = "Peripheral identification registers, SSPPeriphID0-3 on page 3-13"]
+    #[inline(always)]
+    pub const fn periphid1(self) -> crate::common::Reg<regs::Periphid1, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(4068usize) as _) }
+    }
+    #[doc = "Peripheral identification registers, SSPPeriphID0-3 on page 3-13"]
+    #[inline(always)]
+    pub const fn periphid2(self) -> crate::common::Reg<regs::Periphid2, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(4072usize) as _) }
+    }
+    #[doc = "Peripheral identification registers, SSPPeriphID0-3 on page 3-13"]
+    #[inline(always)]
+    pub const fn periphid3(self) -> crate::common::Reg<regs::Periphid3, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(4076usize) as _) }
+    }
+    #[doc = "PrimeCell identification registers, SSPPCellID0-3 on page 3-16"]
+    #[inline(always)]
+    pub const fn pcellid0(self) -> crate::common::Reg<regs::Pcellid0, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(4080usize) as _) }
+    }
+    #[doc = "PrimeCell identification registers, SSPPCellID0-3 on page 3-16"]
+    #[inline(always)]
+    pub const fn pcellid1(self) -> crate::common::Reg<regs::Pcellid1, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(4084usize) as _) }
+    }
+    #[doc = "PrimeCell identification registers, SSPPCellID0-3 on page 3-16"]
+    #[inline(always)]
+    pub const fn pcellid2(self) -> crate::common::Reg<regs::Pcellid2, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(4088usize) as _) }
+    }
+    #[doc = "PrimeCell identification registers, SSPPCellID0-3 on page 3-16"]
+    #[inline(always)]
+    pub const fn pcellid3(self) -> crate::common::Reg<regs::Pcellid3, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(4092usize) as _) }
+    }
+}
+pub mod regs;
diff --git a/src/rp2350/spi/regs.rs b/src/rp2350/spi/regs.rs
new file mode 100644
index 00000000..f41451de
--- /dev/null
+++ b/src/rp2350/spi/regs.rs
@@ -0,0 +1,678 @@
+#[doc = "Clock prescale register, SSPCPSR on page 3-8"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Cpsr(pub u32);
+impl Cpsr {
+    #[doc = "Clock prescale divisor. Must be an even number from 2-254, depending on the frequency of SSPCLK. The least significant bit always returns zero on reads."]
+    #[inline(always)]
+    pub const fn cpsdvsr(&self) -> u8 {
+        let val = (self.0 >> 0usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Clock prescale divisor. Must be an even number from 2-254, depending on the frequency of SSPCLK. The least significant bit always returns zero on reads."]
+    #[inline(always)]
+    pub fn set_cpsdvsr(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize);
+    }
+}
+impl Default for Cpsr {
+    #[inline(always)]
+    fn default() -> Cpsr {
+        Cpsr(0)
+    }
+}
+#[doc = "Control register 0, SSPCR0 on page 3-4"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Cr0(pub u32);
+impl Cr0 {
+    #[doc = "Data Size Select: 0000 Reserved, undefined operation. 0001 Reserved, undefined operation. 0010 Reserved, undefined operation. 0011 4-bit data. 0100 5-bit data. 0101 6-bit data. 0110 7-bit data. 0111 8-bit data. 1000 9-bit data. 1001 10-bit data. 1010 11-bit data. 1011 12-bit data. 1100 13-bit data. 1101 14-bit data. 1110 15-bit data. 1111 16-bit data."]
+    #[inline(always)]
+    pub const fn dss(&self) -> u8 {
+        let val = (self.0 >> 0usize) & 0x0f;
+        val as u8
+    }
+    #[doc = "Data Size Select: 0000 Reserved, undefined operation. 0001 Reserved, undefined operation. 0010 Reserved, undefined operation. 0011 4-bit data. 0100 5-bit data. 0101 6-bit data. 0110 7-bit data. 0111 8-bit data. 1000 9-bit data. 1001 10-bit data. 1010 11-bit data. 1011 12-bit data. 1100 13-bit data. 1101 14-bit data. 1110 15-bit data. 1111 16-bit data."]
+    #[inline(always)]
+    pub fn set_dss(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize);
+    }
+    #[doc = "Frame format: 00 Motorola SPI frame format. 01 TI synchronous serial frame format. 10 National Microwire frame format. 11 Reserved, undefined operation."]
+    #[inline(always)]
+    pub const fn frf(&self) -> u8 {
+        let val = (self.0 >> 4usize) & 0x03;
+        val as u8
+    }
+    #[doc = "Frame format: 00 Motorola SPI frame format. 01 TI synchronous serial frame format. 10 National Microwire frame format. 11 Reserved, undefined operation."]
+    #[inline(always)]
+    pub fn set_frf(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x03 << 4usize)) | (((val as u32) & 0x03) << 4usize);
+    }
+    #[doc = "SSPCLKOUT polarity, applicable to Motorola SPI frame format only. See Motorola SPI frame format on page 2-10."]
+    #[inline(always)]
+    pub const fn spo(&self) -> bool {
+        let val = (self.0 >> 6usize) & 0x01;
+        val != 0
+    }
+    #[doc = "SSPCLKOUT polarity, applicable to Motorola SPI frame format only. See Motorola SPI frame format on page 2-10."]
+    #[inline(always)]
+    pub fn set_spo(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
+    }
+    #[doc = "SSPCLKOUT phase, applicable to Motorola SPI frame format only. See Motorola SPI frame format on page 2-10."]
+    #[inline(always)]
+    pub const fn sph(&self) -> bool {
+        let val = (self.0 >> 7usize) & 0x01;
+        val != 0
+    }
+    #[doc = "SSPCLKOUT phase, applicable to Motorola SPI frame format only. See Motorola SPI frame format on page 2-10."]
+    #[inline(always)]
+    pub fn set_sph(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
+    }
+    #[doc = "Serial clock rate. The value SCR is used to generate the transmit and receive bit rate of the PrimeCell SSP. The bit rate is: F SSPCLK CPSDVSR x (1+SCR) where CPSDVSR is an even value from 2-254, programmed through the SSPCPSR register and SCR is a value from 0-255."]
+    #[inline(always)]
+    pub const fn scr(&self) -> u8 {
+        let val = (self.0 >> 8usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Serial clock rate. The value SCR is used to generate the transmit and receive bit rate of the PrimeCell SSP. The bit rate is: F SSPCLK CPSDVSR x (1+SCR) where CPSDVSR is an even value from 2-254, programmed through the SSPCPSR register and SCR is a value from 0-255."]
+    #[inline(always)]
+    pub fn set_scr(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize);
+    }
+}
+impl Default for Cr0 {
+    #[inline(always)]
+    fn default() -> Cr0 {
+        Cr0(0)
+    }
+}
+#[doc = "Control register 1, SSPCR1 on page 3-5"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Cr1(pub u32);
+impl Cr1 {
+    #[doc = "Loop back mode: 0 Normal serial port operation enabled. 1 Output of transmit serial shifter is connected to input of receive serial shifter internally."]
+    #[inline(always)]
+    pub const fn lbm(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Loop back mode: 0 Normal serial port operation enabled. 1 Output of transmit serial shifter is connected to input of receive serial shifter internally."]
+    #[inline(always)]
+    pub fn set_lbm(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[doc = "Synchronous serial port enable: 0 SSP operation disabled. 1 SSP operation enabled."]
+    #[inline(always)]
+    pub const fn sse(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Synchronous serial port enable: 0 SSP operation disabled. 1 SSP operation enabled."]
+    #[inline(always)]
+    pub fn set_sse(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+    #[doc = "Master or slave mode select. This bit can be modified only when the PrimeCell SSP is disabled, SSE=0: 0 Device configured as master, default. 1 Device configured as slave."]
+    #[inline(always)]
+    pub const fn ms(&self) -> bool {
+        let val = (self.0 >> 2usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Master or slave mode select. This bit can be modified only when the PrimeCell SSP is disabled, SSE=0: 0 Device configured as master, default. 1 Device configured as slave."]
+    #[inline(always)]
+    pub fn set_ms(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+    }
+    #[doc = "Slave-mode output disable. This bit is relevant only in the slave mode, MS=1. In multiple-slave systems, it is possible for an PrimeCell SSP master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto its serial output line. In such systems the RXD lines from multiple slaves could be tied together. To operate in such systems, the SOD bit can be set if the PrimeCell SSP slave is not supposed to drive the SSPTXD line: 0 SSP can drive the SSPTXD output in slave mode. 1 SSP must not drive the SSPTXD output in slave mode."]
+    #[inline(always)]
+    pub const fn sod(&self) -> bool {
+        let val = (self.0 >> 3usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Slave-mode output disable. This bit is relevant only in the slave mode, MS=1. In multiple-slave systems, it is possible for an PrimeCell SSP master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto its serial output line. In such systems the RXD lines from multiple slaves could be tied together. To operate in such systems, the SOD bit can be set if the PrimeCell SSP slave is not supposed to drive the SSPTXD line: 0 SSP can drive the SSPTXD output in slave mode. 1 SSP must not drive the SSPTXD output in slave mode."]
+    #[inline(always)]
+    pub fn set_sod(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
+    }
+}
+impl Default for Cr1 {
+    #[inline(always)]
+    fn default() -> Cr1 {
+        Cr1(0)
+    }
+}
+#[doc = "DMA control register, SSPDMACR on page 3-12"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Dmacr(pub u32);
+impl Dmacr {
+    #[doc = "Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO is enabled."]
+    #[inline(always)]
+    pub const fn rxdmae(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO is enabled."]
+    #[inline(always)]
+    pub fn set_rxdmae(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[doc = "Transmit DMA Enable. If this bit is set to 1, DMA for the transmit FIFO is enabled."]
+    #[inline(always)]
+    pub const fn txdmae(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Transmit DMA Enable. If this bit is set to 1, DMA for the transmit FIFO is enabled."]
+    #[inline(always)]
+    pub fn set_txdmae(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+}
+impl Default for Dmacr {
+    #[inline(always)]
+    fn default() -> Dmacr {
+        Dmacr(0)
+    }
+}
+#[doc = "Data register, SSPDR on page 3-6"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Dr(pub u32);
+impl Dr {
+    #[doc = "Transmit/Receive FIFO: Read Receive FIFO. Write Transmit FIFO. You must right-justify data when the PrimeCell SSP is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies."]
+    #[inline(always)]
+    pub const fn data(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0xffff;
+        val as u16
+    }
+    #[doc = "Transmit/Receive FIFO: Read Receive FIFO. Write Transmit FIFO. You must right-justify data when the PrimeCell SSP is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies."]
+    #[inline(always)]
+    pub fn set_data(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+    }
+}
+impl Default for Dr {
+    #[inline(always)]
+    fn default() -> Dr {
+        Dr(0)
+    }
+}
+#[doc = "Interrupt clear register, SSPICR on page 3-11"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Icr(pub u32);
+impl Icr {
+    #[doc = "Clears the SSPRORINTR interrupt"]
+    #[inline(always)]
+    pub const fn roric(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Clears the SSPRORINTR interrupt"]
+    #[inline(always)]
+    pub fn set_roric(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[doc = "Clears the SSPRTINTR interrupt"]
+    #[inline(always)]
+    pub const fn rtic(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Clears the SSPRTINTR interrupt"]
+    #[inline(always)]
+    pub fn set_rtic(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+}
+impl Default for Icr {
+    #[inline(always)]
+    fn default() -> Icr {
+        Icr(0)
+    }
+}
+#[doc = "Interrupt mask set or clear register, SSPIMSC on page 3-9"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Imsc(pub u32);
+impl Imsc {
+    #[doc = "Receive overrun interrupt mask: 0 Receive FIFO written to while full condition interrupt is masked. 1 Receive FIFO written to while full condition interrupt is not masked."]
+    #[inline(always)]
+    pub const fn rorim(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Receive overrun interrupt mask: 0 Receive FIFO written to while full condition interrupt is masked. 1 Receive FIFO written to while full condition interrupt is not masked."]
+    #[inline(always)]
+    pub fn set_rorim(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[doc = "Receive timeout interrupt mask: 0 Receive FIFO not empty and no read prior to timeout period interrupt is masked. 1 Receive FIFO not empty and no read prior to timeout period interrupt is not masked."]
+    #[inline(always)]
+    pub const fn rtim(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Receive timeout interrupt mask: 0 Receive FIFO not empty and no read prior to timeout period interrupt is masked. 1 Receive FIFO not empty and no read prior to timeout period interrupt is not masked."]
+    #[inline(always)]
+    pub fn set_rtim(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+    #[doc = "Receive FIFO interrupt mask: 0 Receive FIFO half full or less condition interrupt is masked. 1 Receive FIFO half full or less condition interrupt is not masked."]
+    #[inline(always)]
+    pub const fn rxim(&self) -> bool {
+        let val = (self.0 >> 2usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Receive FIFO interrupt mask: 0 Receive FIFO half full or less condition interrupt is masked. 1 Receive FIFO half full or less condition interrupt is not masked."]
+    #[inline(always)]
+    pub fn set_rxim(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+    }
+    #[doc = "Transmit FIFO interrupt mask: 0 Transmit FIFO half empty or less condition interrupt is masked. 1 Transmit FIFO half empty or less condition interrupt is not masked."]
+    #[inline(always)]
+    pub const fn txim(&self) -> bool {
+        let val = (self.0 >> 3usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Transmit FIFO interrupt mask: 0 Transmit FIFO half empty or less condition interrupt is masked. 1 Transmit FIFO half empty or less condition interrupt is not masked."]
+    #[inline(always)]
+    pub fn set_txim(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
+    }
+}
+impl Default for Imsc {
+    #[inline(always)]
+    fn default() -> Imsc {
+        Imsc(0)
+    }
+}
+#[doc = "Masked interrupt status register, SSPMIS on page 3-11"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Mis(pub u32);
+impl Mis {
+    #[doc = "Gives the receive over run masked interrupt status, after masking, of the SSPRORINTR interrupt"]
+    #[inline(always)]
+    pub const fn rormis(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Gives the receive over run masked interrupt status, after masking, of the SSPRORINTR interrupt"]
+    #[inline(always)]
+    pub fn set_rormis(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[doc = "Gives the receive timeout masked interrupt state, after masking, of the SSPRTINTR interrupt"]
+    #[inline(always)]
+    pub const fn rtmis(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Gives the receive timeout masked interrupt state, after masking, of the SSPRTINTR interrupt"]
+    #[inline(always)]
+    pub fn set_rtmis(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+    #[doc = "Gives the receive FIFO masked interrupt state, after masking, of the SSPRXINTR interrupt"]
+    #[inline(always)]
+    pub const fn rxmis(&self) -> bool {
+        let val = (self.0 >> 2usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Gives the receive FIFO masked interrupt state, after masking, of the SSPRXINTR interrupt"]
+    #[inline(always)]
+    pub fn set_rxmis(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+    }
+    #[doc = "Gives the transmit FIFO masked interrupt state, after masking, of the SSPTXINTR interrupt"]
+    #[inline(always)]
+    pub const fn txmis(&self) -> bool {
+        let val = (self.0 >> 3usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Gives the transmit FIFO masked interrupt state, after masking, of the SSPTXINTR interrupt"]
+    #[inline(always)]
+    pub fn set_txmis(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
+    }
+}
+impl Default for Mis {
+    #[inline(always)]
+    fn default() -> Mis {
+        Mis(0)
+    }
+}
+#[doc = "PrimeCell identification registers, SSPPCellID0-3 on page 3-16"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Pcellid0(pub u32);
+impl Pcellid0 {
+    #[doc = "These bits read back as 0x0D"]
+    #[inline(always)]
+    pub const fn ssppcellid0(&self) -> u8 {
+        let val = (self.0 >> 0usize) & 0xff;
+        val as u8
+    }
+    #[doc = "These bits read back as 0x0D"]
+    #[inline(always)]
+    pub fn set_ssppcellid0(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize);
+    }
+}
+impl Default for Pcellid0 {
+    #[inline(always)]
+    fn default() -> Pcellid0 {
+        Pcellid0(0)
+    }
+}
+#[doc = "PrimeCell identification registers, SSPPCellID0-3 on page 3-16"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Pcellid1(pub u32);
+impl Pcellid1 {
+    #[doc = "These bits read back as 0xF0"]
+    #[inline(always)]
+    pub const fn ssppcellid1(&self) -> u8 {
+        let val = (self.0 >> 0usize) & 0xff;
+        val as u8
+    }
+    #[doc = "These bits read back as 0xF0"]
+    #[inline(always)]
+    pub fn set_ssppcellid1(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize);
+    }
+}
+impl Default for Pcellid1 {
+    #[inline(always)]
+    fn default() -> Pcellid1 {
+        Pcellid1(0)
+    }
+}
+#[doc = "PrimeCell identification registers, SSPPCellID0-3 on page 3-16"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Pcellid2(pub u32);
+impl Pcellid2 {
+    #[doc = "These bits read back as 0x05"]
+    #[inline(always)]
+    pub const fn ssppcellid2(&self) -> u8 {
+        let val = (self.0 >> 0usize) & 0xff;
+        val as u8
+    }
+    #[doc = "These bits read back as 0x05"]
+    #[inline(always)]
+    pub fn set_ssppcellid2(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize);
+    }
+}
+impl Default for Pcellid2 {
+    #[inline(always)]
+    fn default() -> Pcellid2 {
+        Pcellid2(0)
+    }
+}
+#[doc = "PrimeCell identification registers, SSPPCellID0-3 on page 3-16"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Pcellid3(pub u32);
+impl Pcellid3 {
+    #[doc = "These bits read back as 0xB1"]
+    #[inline(always)]
+    pub const fn ssppcellid3(&self) -> u8 {
+        let val = (self.0 >> 0usize) & 0xff;
+        val as u8
+    }
+    #[doc = "These bits read back as 0xB1"]
+    #[inline(always)]
+    pub fn set_ssppcellid3(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize);
+    }
+}
+impl Default for Pcellid3 {
+    #[inline(always)]
+    fn default() -> Pcellid3 {
+        Pcellid3(0)
+    }
+}
+#[doc = "Peripheral identification registers, SSPPeriphID0-3 on page 3-13"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Periphid0(pub u32);
+impl Periphid0 {
+    #[doc = "These bits read back as 0x22"]
+    #[inline(always)]
+    pub const fn partnumber0(&self) -> u8 {
+        let val = (self.0 >> 0usize) & 0xff;
+        val as u8
+    }
+    #[doc = "These bits read back as 0x22"]
+    #[inline(always)]
+    pub fn set_partnumber0(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize);
+    }
+}
+impl Default for Periphid0 {
+    #[inline(always)]
+    fn default() -> Periphid0 {
+        Periphid0(0)
+    }
+}
+#[doc = "Peripheral identification registers, SSPPeriphID0-3 on page 3-13"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Periphid1(pub u32);
+impl Periphid1 {
+    #[doc = "These bits read back as 0x0"]
+    #[inline(always)]
+    pub const fn partnumber1(&self) -> u8 {
+        let val = (self.0 >> 0usize) & 0x0f;
+        val as u8
+    }
+    #[doc = "These bits read back as 0x0"]
+    #[inline(always)]
+    pub fn set_partnumber1(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize);
+    }
+    #[doc = "These bits read back as 0x1"]
+    #[inline(always)]
+    pub const fn designer0(&self) -> u8 {
+        let val = (self.0 >> 4usize) & 0x0f;
+        val as u8
+    }
+    #[doc = "These bits read back as 0x1"]
+    #[inline(always)]
+    pub fn set_designer0(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x0f << 4usize)) | (((val as u32) & 0x0f) << 4usize);
+    }
+}
+impl Default for Periphid1 {
+    #[inline(always)]
+    fn default() -> Periphid1 {
+        Periphid1(0)
+    }
+}
+#[doc = "Peripheral identification registers, SSPPeriphID0-3 on page 3-13"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Periphid2(pub u32);
+impl Periphid2 {
+    #[doc = "These bits read back as 0x4"]
+    #[inline(always)]
+    pub const fn designer1(&self) -> u8 {
+        let val = (self.0 >> 0usize) & 0x0f;
+        val as u8
+    }
+    #[doc = "These bits read back as 0x4"]
+    #[inline(always)]
+    pub fn set_designer1(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize);
+    }
+    #[doc = "These bits return the peripheral revision"]
+    #[inline(always)]
+    pub const fn revision(&self) -> u8 {
+        let val = (self.0 >> 4usize) & 0x0f;
+        val as u8
+    }
+    #[doc = "These bits return the peripheral revision"]
+    #[inline(always)]
+    pub fn set_revision(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x0f << 4usize)) | (((val as u32) & 0x0f) << 4usize);
+    }
+}
+impl Default for Periphid2 {
+    #[inline(always)]
+    fn default() -> Periphid2 {
+        Periphid2(0)
+    }
+}
+#[doc = "Peripheral identification registers, SSPPeriphID0-3 on page 3-13"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Periphid3(pub u32);
+impl Periphid3 {
+    #[doc = "These bits read back as 0x00"]
+    #[inline(always)]
+    pub const fn configuration(&self) -> u8 {
+        let val = (self.0 >> 0usize) & 0xff;
+        val as u8
+    }
+    #[doc = "These bits read back as 0x00"]
+    #[inline(always)]
+    pub fn set_configuration(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize);
+    }
+}
+impl Default for Periphid3 {
+    #[inline(always)]
+    fn default() -> Periphid3 {
+        Periphid3(0)
+    }
+}
+#[doc = "Raw interrupt status register, SSPRIS on page 3-10"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Ris(pub u32);
+impl Ris {
+    #[doc = "Gives the raw interrupt state, prior to masking, of the SSPRORINTR interrupt"]
+    #[inline(always)]
+    pub const fn rorris(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Gives the raw interrupt state, prior to masking, of the SSPRORINTR interrupt"]
+    #[inline(always)]
+    pub fn set_rorris(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[doc = "Gives the raw interrupt state, prior to masking, of the SSPRTINTR interrupt"]
+    #[inline(always)]
+    pub const fn rtris(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Gives the raw interrupt state, prior to masking, of the SSPRTINTR interrupt"]
+    #[inline(always)]
+    pub fn set_rtris(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+    #[doc = "Gives the raw interrupt state, prior to masking, of the SSPRXINTR interrupt"]
+    #[inline(always)]
+    pub const fn rxris(&self) -> bool {
+        let val = (self.0 >> 2usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Gives the raw interrupt state, prior to masking, of the SSPRXINTR interrupt"]
+    #[inline(always)]
+    pub fn set_rxris(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+    }
+    #[doc = "Gives the raw interrupt state, prior to masking, of the SSPTXINTR interrupt"]
+    #[inline(always)]
+    pub const fn txris(&self) -> bool {
+        let val = (self.0 >> 3usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Gives the raw interrupt state, prior to masking, of the SSPTXINTR interrupt"]
+    #[inline(always)]
+    pub fn set_txris(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
+    }
+}
+impl Default for Ris {
+    #[inline(always)]
+    fn default() -> Ris {
+        Ris(0)
+    }
+}
+#[doc = "Status register, SSPSR on page 3-7"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Sr(pub u32);
+impl Sr {
+    #[doc = "Transmit FIFO empty, RO: 0 Transmit FIFO is not empty. 1 Transmit FIFO is empty."]
+    #[inline(always)]
+    pub const fn tfe(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Transmit FIFO empty, RO: 0 Transmit FIFO is not empty. 1 Transmit FIFO is empty."]
+    #[inline(always)]
+    pub fn set_tfe(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[doc = "Transmit FIFO not full, RO: 0 Transmit FIFO is full. 1 Transmit FIFO is not full."]
+    #[inline(always)]
+    pub const fn tnf(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Transmit FIFO not full, RO: 0 Transmit FIFO is full. 1 Transmit FIFO is not full."]
+    #[inline(always)]
+    pub fn set_tnf(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+    #[doc = "Receive FIFO not empty, RO: 0 Receive FIFO is empty. 1 Receive FIFO is not empty."]
+    #[inline(always)]
+    pub const fn rne(&self) -> bool {
+        let val = (self.0 >> 2usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Receive FIFO not empty, RO: 0 Receive FIFO is empty. 1 Receive FIFO is not empty."]
+    #[inline(always)]
+    pub fn set_rne(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+    }
+    #[doc = "Receive FIFO full, RO: 0 Receive FIFO is not full. 1 Receive FIFO is full."]
+    #[inline(always)]
+    pub const fn rff(&self) -> bool {
+        let val = (self.0 >> 3usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Receive FIFO full, RO: 0 Receive FIFO is not full. 1 Receive FIFO is full."]
+    #[inline(always)]
+    pub fn set_rff(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
+    }
+    #[doc = "PrimeCell SSP busy flag, RO: 0 SSP is idle. 1 SSP is currently transmitting and/or receiving a frame or the transmit FIFO is not empty."]
+    #[inline(always)]
+    pub const fn bsy(&self) -> bool {
+        let val = (self.0 >> 4usize) & 0x01;
+        val != 0
+    }
+    #[doc = "PrimeCell SSP busy flag, RO: 0 SSP is idle. 1 SSP is currently transmitting and/or receiving a frame or the transmit FIFO is not empty."]
+    #[inline(always)]
+    pub fn set_bsy(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
+    }
+}
+impl Default for Sr {
+    #[inline(always)]
+    fn default() -> Sr {
+        Sr(0)
+    }
+}
diff --git a/src/rp2350/syscfg.rs b/src/rp2350/syscfg.rs
new file mode 100644
index 00000000..e770429c
--- /dev/null
+++ b/src/rp2350/syscfg.rs
@@ -0,0 +1,50 @@
+#[doc = "Register block for various chip control signals"]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Syscfg {
+    ptr: *mut u8,
+}
+unsafe impl Send for Syscfg {}
+unsafe impl Sync for Syscfg {}
+impl Syscfg {
+    #[inline(always)]
+    pub const unsafe fn from_ptr(ptr: *mut ()) -> Self {
+        Self { ptr: ptr as _ }
+    }
+    #[inline(always)]
+    pub const fn as_ptr(&self) -> *mut () {
+        self.ptr as _
+    }
+    #[doc = "Configuration for processors"]
+    #[inline(always)]
+    pub const fn proc_config(self) -> crate::common::Reg<regs::ProcConfig, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(0usize) as _) }
+    }
+    #[doc = "For each bit, if 1, bypass the input synchronizer between that GPIO and the GPIO input register in the SIO. The input synchronizers should generally be unbypassed, to avoid injecting metastabilities into processors. If you're feeling brave, you can bypass to save two cycles of input latency. This register applies to GPIO 0...31."]
+    #[inline(always)]
+    pub const fn proc_in_sync_bypass(self) -> crate::common::Reg<u32, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(4usize) as _) }
+    }
+    #[doc = "For each bit, if 1, bypass the input synchronizer between that GPIO and the GPIO input register in the SIO. The input synchronizers should generally be unbypassed, to avoid injecting metastabilities into processors. If you're feeling brave, you can bypass to save two cycles of input latency. This register applies to GPIO 32...47. USB GPIO 56..57 QSPI GPIO 58..63"]
+    #[inline(always)]
+    pub const fn proc_in_sync_bypass_hi(
+        self,
+    ) -> crate::common::Reg<regs::ProcInSyncBypassHi, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(8usize) as _) }
+    }
+    #[doc = "Directly control the chip SWD debug port"]
+    #[inline(always)]
+    pub const fn dbgforce(self) -> crate::common::Reg<regs::Dbgforce, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(12usize) as _) }
+    }
+    #[doc = "Control PD pins to memories. Set high to put memories to a low power state. In this state the memories will retain contents but not be accessible Use with caution"]
+    #[inline(always)]
+    pub const fn mempowerdown(self) -> crate::common::Reg<regs::Mempowerdown, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(16usize) as _) }
+    }
+    #[doc = "Auxiliary system control register"]
+    #[inline(always)]
+    pub const fn auxctrl(self) -> crate::common::Reg<regs::Auxctrl, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(20usize) as _) }
+    }
+}
+pub mod regs;
diff --git a/src/rp2350/syscfg/regs.rs b/src/rp2350/syscfg/regs.rs
new file mode 100644
index 00000000..9a92b99d
--- /dev/null
+++ b/src/rp2350/syscfg/regs.rs
@@ -0,0 +1,308 @@
+#[doc = "Auxiliary system control register"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Auxctrl(pub u32);
+impl Auxctrl {
+    #[doc = "* Bits 7:2: Reserved * Bit 1: When clear, the LPOSC output is XORed into the TRNG ROSC output as an additional, uncorrelated entropy source. When set, this behaviour is disabled. * Bit 0: Force POWMAN clock to switch to LPOSC, by asserting its WDRESET input. This must be set before initiating a watchdog reset of the RSM from a stage that includes CLOCKS, if POWMAN is running from clk_ref at the point that the watchdog reset takes place. Otherwise, the short pulse generated on clk_ref by the reset of the CLOCKS block may affect POWMAN register state."]
+    #[inline(always)]
+    pub const fn auxctrl(&self) -> u8 {
+        let val = (self.0 >> 0usize) & 0xff;
+        val as u8
+    }
+    #[doc = "* Bits 7:2: Reserved * Bit 1: When clear, the LPOSC output is XORed into the TRNG ROSC output as an additional, uncorrelated entropy source. When set, this behaviour is disabled. * Bit 0: Force POWMAN clock to switch to LPOSC, by asserting its WDRESET input. This must be set before initiating a watchdog reset of the RSM from a stage that includes CLOCKS, if POWMAN is running from clk_ref at the point that the watchdog reset takes place. Otherwise, the short pulse generated on clk_ref by the reset of the CLOCKS block may affect POWMAN register state."]
+    #[inline(always)]
+    pub fn set_auxctrl(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize);
+    }
+}
+impl Default for Auxctrl {
+    #[inline(always)]
+    fn default() -> Auxctrl {
+        Auxctrl(0)
+    }
+}
+#[doc = "Directly control the chip SWD debug port"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Dbgforce(pub u32);
+impl Dbgforce {
+    #[doc = "Observe the value of SWDIO output."]
+    #[inline(always)]
+    pub const fn swdo(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Observe the value of SWDIO output."]
+    #[inline(always)]
+    pub fn set_swdo(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[doc = "Directly drive SWDIO input, if ATTACH is set"]
+    #[inline(always)]
+    pub const fn swdi(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Directly drive SWDIO input, if ATTACH is set"]
+    #[inline(always)]
+    pub fn set_swdi(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+    #[doc = "Directly drive SWCLK, if ATTACH is set"]
+    #[inline(always)]
+    pub const fn swclk(&self) -> bool {
+        let val = (self.0 >> 2usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Directly drive SWCLK, if ATTACH is set"]
+    #[inline(always)]
+    pub fn set_swclk(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+    }
+    #[doc = "Attach chip debug port to syscfg controls, and disconnect it from external SWD pads."]
+    #[inline(always)]
+    pub const fn attach(&self) -> bool {
+        let val = (self.0 >> 3usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Attach chip debug port to syscfg controls, and disconnect it from external SWD pads."]
+    #[inline(always)]
+    pub fn set_attach(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
+    }
+}
+impl Default for Dbgforce {
+    #[inline(always)]
+    fn default() -> Dbgforce {
+        Dbgforce(0)
+    }
+}
+#[doc = "Control PD pins to memories. Set high to put memories to a low power state. In this state the memories will retain contents but not be accessible Use with caution"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Mempowerdown(pub u32);
+impl Mempowerdown {
+    #[inline(always)]
+    pub const fn sram0(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_sram0(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[inline(always)]
+    pub const fn sram1(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_sram1(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+    #[inline(always)]
+    pub const fn sram2(&self) -> bool {
+        let val = (self.0 >> 2usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_sram2(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+    }
+    #[inline(always)]
+    pub const fn sram3(&self) -> bool {
+        let val = (self.0 >> 3usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_sram3(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
+    }
+    #[inline(always)]
+    pub const fn sram4(&self) -> bool {
+        let val = (self.0 >> 4usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_sram4(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
+    }
+    #[inline(always)]
+    pub const fn sram5(&self) -> bool {
+        let val = (self.0 >> 5usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_sram5(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
+    }
+    #[inline(always)]
+    pub const fn sram6(&self) -> bool {
+        let val = (self.0 >> 6usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_sram6(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
+    }
+    #[inline(always)]
+    pub const fn sram7(&self) -> bool {
+        let val = (self.0 >> 7usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_sram7(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
+    }
+    #[inline(always)]
+    pub const fn sram8(&self) -> bool {
+        let val = (self.0 >> 8usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_sram8(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
+    }
+    #[inline(always)]
+    pub const fn sram9(&self) -> bool {
+        let val = (self.0 >> 9usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_sram9(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
+    }
+    #[inline(always)]
+    pub const fn usb(&self) -> bool {
+        let val = (self.0 >> 10usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_usb(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize);
+    }
+    #[inline(always)]
+    pub const fn rom(&self) -> bool {
+        let val = (self.0 >> 11usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_rom(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
+    }
+    #[inline(always)]
+    pub const fn bootram(&self) -> bool {
+        let val = (self.0 >> 12usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_bootram(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
+    }
+}
+impl Default for Mempowerdown {
+    #[inline(always)]
+    fn default() -> Mempowerdown {
+        Mempowerdown(0)
+    }
+}
+#[doc = "Configuration for processors"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct ProcConfig(pub u32);
+impl ProcConfig {
+    #[doc = "Indication that proc0 has halted"]
+    #[inline(always)]
+    pub const fn proc0_halted(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Indication that proc0 has halted"]
+    #[inline(always)]
+    pub fn set_proc0_halted(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[doc = "Indication that proc1 has halted"]
+    #[inline(always)]
+    pub const fn proc1_halted(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Indication that proc1 has halted"]
+    #[inline(always)]
+    pub fn set_proc1_halted(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+}
+impl Default for ProcConfig {
+    #[inline(always)]
+    fn default() -> ProcConfig {
+        ProcConfig(0)
+    }
+}
+#[doc = "For each bit, if 1, bypass the input synchronizer between that GPIO and the GPIO input register in the SIO. The input synchronizers should generally be unbypassed, to avoid injecting metastabilities into processors. If you're feeling brave, you can bypass to save two cycles of input latency. This register applies to GPIO 32...47. USB GPIO 56..57 QSPI GPIO 58..63"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct ProcInSyncBypassHi(pub u32);
+impl ProcInSyncBypassHi {
+    #[inline(always)]
+    pub const fn gpio(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0xffff;
+        val as u16
+    }
+    #[inline(always)]
+    pub fn set_gpio(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+    }
+    #[inline(always)]
+    pub const fn usb_dp(&self) -> bool {
+        let val = (self.0 >> 24usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_usb_dp(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 24usize)) | (((val as u32) & 0x01) << 24usize);
+    }
+    #[inline(always)]
+    pub const fn usb_dm(&self) -> bool {
+        let val = (self.0 >> 25usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_usb_dm(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 25usize)) | (((val as u32) & 0x01) << 25usize);
+    }
+    #[inline(always)]
+    pub const fn qspi_sck(&self) -> bool {
+        let val = (self.0 >> 26usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_qspi_sck(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 26usize)) | (((val as u32) & 0x01) << 26usize);
+    }
+    #[inline(always)]
+    pub const fn qspi_csn(&self) -> bool {
+        let val = (self.0 >> 27usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_qspi_csn(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 27usize)) | (((val as u32) & 0x01) << 27usize);
+    }
+    #[inline(always)]
+    pub const fn qspi_sd(&self) -> u8 {
+        let val = (self.0 >> 28usize) & 0x0f;
+        val as u8
+    }
+    #[inline(always)]
+    pub fn set_qspi_sd(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x0f << 28usize)) | (((val as u32) & 0x0f) << 28usize);
+    }
+}
+impl Default for ProcInSyncBypassHi {
+    #[inline(always)]
+    fn default() -> ProcInSyncBypassHi {
+        ProcInSyncBypassHi(0)
+    }
+}
diff --git a/src/rp2350/sysinfo.rs b/src/rp2350/sysinfo.rs
new file mode 100644
index 00000000..5a7dff28
--- /dev/null
+++ b/src/rp2350/sysinfo.rs
@@ -0,0 +1,36 @@
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Sysinfo {
+    ptr: *mut u8,
+}
+unsafe impl Send for Sysinfo {}
+unsafe impl Sync for Sysinfo {}
+impl Sysinfo {
+    #[inline(always)]
+    pub const unsafe fn from_ptr(ptr: *mut ()) -> Self {
+        Self { ptr: ptr as _ }
+    }
+    #[inline(always)]
+    pub const fn as_ptr(&self) -> *mut () {
+        self.ptr as _
+    }
+    #[doc = "JEDEC JEP-106 compliant chip identifier."]
+    #[inline(always)]
+    pub const fn chip_id(self) -> crate::common::Reg<regs::ChipId, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(0usize) as _) }
+    }
+    #[inline(always)]
+    pub const fn package_sel(self) -> crate::common::Reg<regs::PackageSel, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(4usize) as _) }
+    }
+    #[doc = "Platform register. Allows software to know what environment it is running in during pre-production development. Post-production, the PLATFORM is always ASIC, non-SIM."]
+    #[inline(always)]
+    pub const fn platform(self) -> crate::common::Reg<regs::Platform, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(8usize) as _) }
+    }
+    #[doc = "Git hash of the chip source. Used to identify chip version."]
+    #[inline(always)]
+    pub const fn gitref_rp2350(self) -> crate::common::Reg<u32, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(20usize) as _) }
+    }
+}
+pub mod regs;
diff --git a/src/rp2350/sysinfo/regs.rs b/src/rp2350/sysinfo/regs.rs
new file mode 100644
index 00000000..7b6babf2
--- /dev/null
+++ b/src/rp2350/sysinfo/regs.rs
@@ -0,0 +1,125 @@
+#[doc = "JEDEC JEP-106 compliant chip identifier."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct ChipId(pub u32);
+impl ChipId {
+    #[inline(always)]
+    pub const fn stop_bit(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_stop_bit(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[inline(always)]
+    pub const fn manufacturer(&self) -> u16 {
+        let val = (self.0 >> 1usize) & 0x07ff;
+        val as u16
+    }
+    #[inline(always)]
+    pub fn set_manufacturer(&mut self, val: u16) {
+        self.0 = (self.0 & !(0x07ff << 1usize)) | (((val as u32) & 0x07ff) << 1usize);
+    }
+    #[inline(always)]
+    pub const fn part(&self) -> u16 {
+        let val = (self.0 >> 12usize) & 0xffff;
+        val as u16
+    }
+    #[inline(always)]
+    pub fn set_part(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 12usize)) | (((val as u32) & 0xffff) << 12usize);
+    }
+    #[inline(always)]
+    pub const fn revision(&self) -> u8 {
+        let val = (self.0 >> 28usize) & 0x0f;
+        val as u8
+    }
+    #[inline(always)]
+    pub fn set_revision(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x0f << 28usize)) | (((val as u32) & 0x0f) << 28usize);
+    }
+}
+impl Default for ChipId {
+    #[inline(always)]
+    fn default() -> ChipId {
+        ChipId(0)
+    }
+}
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct PackageSel(pub u32);
+impl PackageSel {
+    #[inline(always)]
+    pub const fn package_sel(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_package_sel(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+}
+impl Default for PackageSel {
+    #[inline(always)]
+    fn default() -> PackageSel {
+        PackageSel(0)
+    }
+}
+#[doc = "Platform register. Allows software to know what environment it is running in during pre-production development. Post-production, the PLATFORM is always ASIC, non-SIM."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Platform(pub u32);
+impl Platform {
+    #[inline(always)]
+    pub const fn fpga(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_fpga(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[inline(always)]
+    pub const fn asic(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_asic(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+    #[inline(always)]
+    pub const fn hdlsim(&self) -> bool {
+        let val = (self.0 >> 2usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_hdlsim(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+    }
+    #[inline(always)]
+    pub const fn batchsim(&self) -> bool {
+        let val = (self.0 >> 3usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_batchsim(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
+    }
+    #[inline(always)]
+    pub const fn gatesim(&self) -> bool {
+        let val = (self.0 >> 4usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_gatesim(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
+    }
+}
+impl Default for Platform {
+    #[inline(always)]
+    fn default() -> Platform {
+        Platform(0)
+    }
+}
diff --git a/src/rp2350/tbman.rs b/src/rp2350/tbman.rs
new file mode 100644
index 00000000..f3d65156
--- /dev/null
+++ b/src/rp2350/tbman.rs
@@ -0,0 +1,23 @@
+#[doc = "For managing simulation testbenches"]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Tbman {
+    ptr: *mut u8,
+}
+unsafe impl Send for Tbman {}
+unsafe impl Sync for Tbman {}
+impl Tbman {
+    #[inline(always)]
+    pub const unsafe fn from_ptr(ptr: *mut ()) -> Self {
+        Self { ptr: ptr as _ }
+    }
+    #[inline(always)]
+    pub const fn as_ptr(&self) -> *mut () {
+        self.ptr as _
+    }
+    #[doc = "Indicates the type of platform in use"]
+    #[inline(always)]
+    pub const fn platform(self) -> crate::common::Reg<regs::Platform, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(0usize) as _) }
+    }
+}
+pub mod regs;
diff --git a/src/rp2350/tbman/regs.rs b/src/rp2350/tbman/regs.rs
new file mode 100644
index 00000000..fd318142
--- /dev/null
+++ b/src/rp2350/tbman/regs.rs
@@ -0,0 +1,45 @@
+#[doc = "Indicates the type of platform in use"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Platform(pub u32);
+impl Platform {
+    #[doc = "Indicates the platform is an ASIC"]
+    #[inline(always)]
+    pub const fn asic(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Indicates the platform is an ASIC"]
+    #[inline(always)]
+    pub fn set_asic(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[doc = "Indicates the platform is an FPGA"]
+    #[inline(always)]
+    pub const fn fpga(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Indicates the platform is an FPGA"]
+    #[inline(always)]
+    pub fn set_fpga(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+    #[doc = "Indicates the platform is a simulation"]
+    #[inline(always)]
+    pub const fn hdlsim(&self) -> bool {
+        let val = (self.0 >> 2usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Indicates the platform is a simulation"]
+    #[inline(always)]
+    pub fn set_hdlsim(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+    }
+}
+impl Default for Platform {
+    #[inline(always)]
+    fn default() -> Platform {
+        Platform(0)
+    }
+}
diff --git a/src/rp2350/ticks.rs b/src/rp2350/ticks.rs
new file mode 100644
index 00000000..98f86780
--- /dev/null
+++ b/src/rp2350/ticks.rs
@@ -0,0 +1,99 @@
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Ticks {
+    ptr: *mut u8,
+}
+unsafe impl Send for Ticks {}
+unsafe impl Sync for Ticks {}
+impl Ticks {
+    #[inline(always)]
+    pub const unsafe fn from_ptr(ptr: *mut ()) -> Self {
+        Self { ptr: ptr as _ }
+    }
+    #[inline(always)]
+    pub const fn as_ptr(&self) -> *mut () {
+        self.ptr as _
+    }
+    #[doc = "Controls the tick generator"]
+    #[inline(always)]
+    pub const fn proc0_ctrl(self) -> crate::common::Reg<regs::Proc0ctrl, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(0usize) as _) }
+    }
+    #[inline(always)]
+    pub const fn proc0_cycles(self) -> crate::common::Reg<regs::Proc0cycles, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(4usize) as _) }
+    }
+    #[inline(always)]
+    pub const fn proc0_count(self) -> crate::common::Reg<regs::Proc0count, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(8usize) as _) }
+    }
+    #[doc = "Controls the tick generator"]
+    #[inline(always)]
+    pub const fn proc1_ctrl(self) -> crate::common::Reg<regs::Proc1ctrl, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(12usize) as _) }
+    }
+    #[inline(always)]
+    pub const fn proc1_cycles(self) -> crate::common::Reg<regs::Proc1cycles, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(16usize) as _) }
+    }
+    #[inline(always)]
+    pub const fn proc1_count(self) -> crate::common::Reg<regs::Proc1count, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(20usize) as _) }
+    }
+    #[doc = "Controls the tick generator"]
+    #[inline(always)]
+    pub const fn timer0_ctrl(self) -> crate::common::Reg<regs::Timer0ctrl, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(24usize) as _) }
+    }
+    #[inline(always)]
+    pub const fn timer0_cycles(self) -> crate::common::Reg<regs::Timer0cycles, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(28usize) as _) }
+    }
+    #[inline(always)]
+    pub const fn timer0_count(self) -> crate::common::Reg<regs::Timer0count, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(32usize) as _) }
+    }
+    #[doc = "Controls the tick generator"]
+    #[inline(always)]
+    pub const fn timer1_ctrl(self) -> crate::common::Reg<regs::Timer1ctrl, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(36usize) as _) }
+    }
+    #[inline(always)]
+    pub const fn timer1_cycles(self) -> crate::common::Reg<regs::Timer1cycles, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(40usize) as _) }
+    }
+    #[inline(always)]
+    pub const fn timer1_count(self) -> crate::common::Reg<regs::Timer1count, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(44usize) as _) }
+    }
+    #[doc = "Controls the tick generator"]
+    #[inline(always)]
+    pub const fn watchdog_ctrl(self) -> crate::common::Reg<regs::WatchdogCtrl, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(48usize) as _) }
+    }
+    #[inline(always)]
+    pub const fn watchdog_cycles(
+        self,
+    ) -> crate::common::Reg<regs::WatchdogCycles, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(52usize) as _) }
+    }
+    #[inline(always)]
+    pub const fn watchdog_count(
+        self,
+    ) -> crate::common::Reg<regs::WatchdogCount, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(56usize) as _) }
+    }
+    #[doc = "Controls the tick generator"]
+    #[inline(always)]
+    pub const fn riscv_ctrl(self) -> crate::common::Reg<regs::RiscvCtrl, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(60usize) as _) }
+    }
+    #[inline(always)]
+    pub const fn riscv_cycles(self) -> crate::common::Reg<regs::RiscvCycles, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(64usize) as _) }
+    }
+    #[inline(always)]
+    pub const fn riscv_count(self) -> crate::common::Reg<regs::RiscvCount, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(68usize) as _) }
+    }
+}
+pub mod regs;
diff --git a/src/rp2350/ticks/regs.rs b/src/rp2350/ticks/regs.rs
new file mode 100644
index 00000000..fe7b526d
--- /dev/null
+++ b/src/rp2350/ticks/regs.rs
@@ -0,0 +1,468 @@
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Proc0count(pub u32);
+impl Proc0count {
+    #[doc = "Count down timer: the remaining number clk_tick cycles before the next tick is generated."]
+    #[inline(always)]
+    pub const fn proc0_count(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0x01ff;
+        val as u16
+    }
+    #[doc = "Count down timer: the remaining number clk_tick cycles before the next tick is generated."]
+    #[inline(always)]
+    pub fn set_proc0_count(&mut self, val: u16) {
+        self.0 = (self.0 & !(0x01ff << 0usize)) | (((val as u32) & 0x01ff) << 0usize);
+    }
+}
+impl Default for Proc0count {
+    #[inline(always)]
+    fn default() -> Proc0count {
+        Proc0count(0)
+    }
+}
+#[doc = "Controls the tick generator"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Proc0ctrl(pub u32);
+impl Proc0ctrl {
+    #[doc = "start / stop tick generation"]
+    #[inline(always)]
+    pub const fn enable(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "start / stop tick generation"]
+    #[inline(always)]
+    pub fn set_enable(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[doc = "Is the tick generator running?"]
+    #[inline(always)]
+    pub const fn running(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Is the tick generator running?"]
+    #[inline(always)]
+    pub fn set_running(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+}
+impl Default for Proc0ctrl {
+    #[inline(always)]
+    fn default() -> Proc0ctrl {
+        Proc0ctrl(0)
+    }
+}
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Proc0cycles(pub u32);
+impl Proc0cycles {
+    #[doc = "Total number of clk_tick cycles before the next tick."]
+    #[inline(always)]
+    pub const fn proc0_cycles(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0x01ff;
+        val as u16
+    }
+    #[doc = "Total number of clk_tick cycles before the next tick."]
+    #[inline(always)]
+    pub fn set_proc0_cycles(&mut self, val: u16) {
+        self.0 = (self.0 & !(0x01ff << 0usize)) | (((val as u32) & 0x01ff) << 0usize);
+    }
+}
+impl Default for Proc0cycles {
+    #[inline(always)]
+    fn default() -> Proc0cycles {
+        Proc0cycles(0)
+    }
+}
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Proc1count(pub u32);
+impl Proc1count {
+    #[doc = "Count down timer: the remaining number clk_tick cycles before the next tick is generated."]
+    #[inline(always)]
+    pub const fn proc1_count(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0x01ff;
+        val as u16
+    }
+    #[doc = "Count down timer: the remaining number clk_tick cycles before the next tick is generated."]
+    #[inline(always)]
+    pub fn set_proc1_count(&mut self, val: u16) {
+        self.0 = (self.0 & !(0x01ff << 0usize)) | (((val as u32) & 0x01ff) << 0usize);
+    }
+}
+impl Default for Proc1count {
+    #[inline(always)]
+    fn default() -> Proc1count {
+        Proc1count(0)
+    }
+}
+#[doc = "Controls the tick generator"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Proc1ctrl(pub u32);
+impl Proc1ctrl {
+    #[doc = "start / stop tick generation"]
+    #[inline(always)]
+    pub const fn enable(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "start / stop tick generation"]
+    #[inline(always)]
+    pub fn set_enable(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[doc = "Is the tick generator running?"]
+    #[inline(always)]
+    pub const fn running(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Is the tick generator running?"]
+    #[inline(always)]
+    pub fn set_running(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+}
+impl Default for Proc1ctrl {
+    #[inline(always)]
+    fn default() -> Proc1ctrl {
+        Proc1ctrl(0)
+    }
+}
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Proc1cycles(pub u32);
+impl Proc1cycles {
+    #[doc = "Total number of clk_tick cycles before the next tick."]
+    #[inline(always)]
+    pub const fn proc1_cycles(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0x01ff;
+        val as u16
+    }
+    #[doc = "Total number of clk_tick cycles before the next tick."]
+    #[inline(always)]
+    pub fn set_proc1_cycles(&mut self, val: u16) {
+        self.0 = (self.0 & !(0x01ff << 0usize)) | (((val as u32) & 0x01ff) << 0usize);
+    }
+}
+impl Default for Proc1cycles {
+    #[inline(always)]
+    fn default() -> Proc1cycles {
+        Proc1cycles(0)
+    }
+}
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct RiscvCount(pub u32);
+impl RiscvCount {
+    #[doc = "Count down timer: the remaining number clk_tick cycles before the next tick is generated."]
+    #[inline(always)]
+    pub const fn riscv_count(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0x01ff;
+        val as u16
+    }
+    #[doc = "Count down timer: the remaining number clk_tick cycles before the next tick is generated."]
+    #[inline(always)]
+    pub fn set_riscv_count(&mut self, val: u16) {
+        self.0 = (self.0 & !(0x01ff << 0usize)) | (((val as u32) & 0x01ff) << 0usize);
+    }
+}
+impl Default for RiscvCount {
+    #[inline(always)]
+    fn default() -> RiscvCount {
+        RiscvCount(0)
+    }
+}
+#[doc = "Controls the tick generator"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct RiscvCtrl(pub u32);
+impl RiscvCtrl {
+    #[doc = "start / stop tick generation"]
+    #[inline(always)]
+    pub const fn enable(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "start / stop tick generation"]
+    #[inline(always)]
+    pub fn set_enable(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[doc = "Is the tick generator running?"]
+    #[inline(always)]
+    pub const fn running(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Is the tick generator running?"]
+    #[inline(always)]
+    pub fn set_running(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+}
+impl Default for RiscvCtrl {
+    #[inline(always)]
+    fn default() -> RiscvCtrl {
+        RiscvCtrl(0)
+    }
+}
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct RiscvCycles(pub u32);
+impl RiscvCycles {
+    #[doc = "Total number of clk_tick cycles before the next tick."]
+    #[inline(always)]
+    pub const fn riscv_cycles(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0x01ff;
+        val as u16
+    }
+    #[doc = "Total number of clk_tick cycles before the next tick."]
+    #[inline(always)]
+    pub fn set_riscv_cycles(&mut self, val: u16) {
+        self.0 = (self.0 & !(0x01ff << 0usize)) | (((val as u32) & 0x01ff) << 0usize);
+    }
+}
+impl Default for RiscvCycles {
+    #[inline(always)]
+    fn default() -> RiscvCycles {
+        RiscvCycles(0)
+    }
+}
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Timer0count(pub u32);
+impl Timer0count {
+    #[doc = "Count down timer: the remaining number clk_tick cycles before the next tick is generated."]
+    #[inline(always)]
+    pub const fn timer0_count(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0x01ff;
+        val as u16
+    }
+    #[doc = "Count down timer: the remaining number clk_tick cycles before the next tick is generated."]
+    #[inline(always)]
+    pub fn set_timer0_count(&mut self, val: u16) {
+        self.0 = (self.0 & !(0x01ff << 0usize)) | (((val as u32) & 0x01ff) << 0usize);
+    }
+}
+impl Default for Timer0count {
+    #[inline(always)]
+    fn default() -> Timer0count {
+        Timer0count(0)
+    }
+}
+#[doc = "Controls the tick generator"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Timer0ctrl(pub u32);
+impl Timer0ctrl {
+    #[doc = "start / stop tick generation"]
+    #[inline(always)]
+    pub const fn enable(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "start / stop tick generation"]
+    #[inline(always)]
+    pub fn set_enable(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[doc = "Is the tick generator running?"]
+    #[inline(always)]
+    pub const fn running(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Is the tick generator running?"]
+    #[inline(always)]
+    pub fn set_running(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+}
+impl Default for Timer0ctrl {
+    #[inline(always)]
+    fn default() -> Timer0ctrl {
+        Timer0ctrl(0)
+    }
+}
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Timer0cycles(pub u32);
+impl Timer0cycles {
+    #[doc = "Total number of clk_tick cycles before the next tick."]
+    #[inline(always)]
+    pub const fn timer0_cycles(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0x01ff;
+        val as u16
+    }
+    #[doc = "Total number of clk_tick cycles before the next tick."]
+    #[inline(always)]
+    pub fn set_timer0_cycles(&mut self, val: u16) {
+        self.0 = (self.0 & !(0x01ff << 0usize)) | (((val as u32) & 0x01ff) << 0usize);
+    }
+}
+impl Default for Timer0cycles {
+    #[inline(always)]
+    fn default() -> Timer0cycles {
+        Timer0cycles(0)
+    }
+}
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Timer1count(pub u32);
+impl Timer1count {
+    #[doc = "Count down timer: the remaining number clk_tick cycles before the next tick is generated."]
+    #[inline(always)]
+    pub const fn timer1_count(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0x01ff;
+        val as u16
+    }
+    #[doc = "Count down timer: the remaining number clk_tick cycles before the next tick is generated."]
+    #[inline(always)]
+    pub fn set_timer1_count(&mut self, val: u16) {
+        self.0 = (self.0 & !(0x01ff << 0usize)) | (((val as u32) & 0x01ff) << 0usize);
+    }
+}
+impl Default for Timer1count {
+    #[inline(always)]
+    fn default() -> Timer1count {
+        Timer1count(0)
+    }
+}
+#[doc = "Controls the tick generator"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Timer1ctrl(pub u32);
+impl Timer1ctrl {
+    #[doc = "start / stop tick generation"]
+    #[inline(always)]
+    pub const fn enable(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "start / stop tick generation"]
+    #[inline(always)]
+    pub fn set_enable(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[doc = "Is the tick generator running?"]
+    #[inline(always)]
+    pub const fn running(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Is the tick generator running?"]
+    #[inline(always)]
+    pub fn set_running(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+}
+impl Default for Timer1ctrl {
+    #[inline(always)]
+    fn default() -> Timer1ctrl {
+        Timer1ctrl(0)
+    }
+}
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Timer1cycles(pub u32);
+impl Timer1cycles {
+    #[doc = "Total number of clk_tick cycles before the next tick."]
+    #[inline(always)]
+    pub const fn timer1_cycles(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0x01ff;
+        val as u16
+    }
+    #[doc = "Total number of clk_tick cycles before the next tick."]
+    #[inline(always)]
+    pub fn set_timer1_cycles(&mut self, val: u16) {
+        self.0 = (self.0 & !(0x01ff << 0usize)) | (((val as u32) & 0x01ff) << 0usize);
+    }
+}
+impl Default for Timer1cycles {
+    #[inline(always)]
+    fn default() -> Timer1cycles {
+        Timer1cycles(0)
+    }
+}
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct WatchdogCount(pub u32);
+impl WatchdogCount {
+    #[doc = "Count down timer: the remaining number clk_tick cycles before the next tick is generated."]
+    #[inline(always)]
+    pub const fn watchdog_count(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0x01ff;
+        val as u16
+    }
+    #[doc = "Count down timer: the remaining number clk_tick cycles before the next tick is generated."]
+    #[inline(always)]
+    pub fn set_watchdog_count(&mut self, val: u16) {
+        self.0 = (self.0 & !(0x01ff << 0usize)) | (((val as u32) & 0x01ff) << 0usize);
+    }
+}
+impl Default for WatchdogCount {
+    #[inline(always)]
+    fn default() -> WatchdogCount {
+        WatchdogCount(0)
+    }
+}
+#[doc = "Controls the tick generator"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct WatchdogCtrl(pub u32);
+impl WatchdogCtrl {
+    #[doc = "start / stop tick generation"]
+    #[inline(always)]
+    pub const fn enable(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "start / stop tick generation"]
+    #[inline(always)]
+    pub fn set_enable(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[doc = "Is the tick generator running?"]
+    #[inline(always)]
+    pub const fn running(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Is the tick generator running?"]
+    #[inline(always)]
+    pub fn set_running(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+}
+impl Default for WatchdogCtrl {
+    #[inline(always)]
+    fn default() -> WatchdogCtrl {
+        WatchdogCtrl(0)
+    }
+}
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct WatchdogCycles(pub u32);
+impl WatchdogCycles {
+    #[doc = "Total number of clk_tick cycles before the next tick."]
+    #[inline(always)]
+    pub const fn watchdog_cycles(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0x01ff;
+        val as u16
+    }
+    #[doc = "Total number of clk_tick cycles before the next tick."]
+    #[inline(always)]
+    pub fn set_watchdog_cycles(&mut self, val: u16) {
+        self.0 = (self.0 & !(0x01ff << 0usize)) | (((val as u32) & 0x01ff) << 0usize);
+    }
+}
+impl Default for WatchdogCycles {
+    #[inline(always)]
+    fn default() -> WatchdogCycles {
+        WatchdogCycles(0)
+    }
+}
diff --git a/src/rp2350/timer.rs b/src/rp2350/timer.rs
new file mode 100644
index 00000000..2a795aca
--- /dev/null
+++ b/src/rp2350/timer.rs
@@ -0,0 +1,100 @@
+#[doc = "Controls time and alarms time is a 64 bit value indicating the time since power-on timeh is the top 32 bits of time & timel is the bottom 32 bits to change time write to timelw before timehw to read time read from timelr before timehr An alarm is set by setting alarm_enable and writing to the corresponding alarm register When an alarm is pending, the corresponding alarm_running signal will be high An alarm can be cancelled before it has finished by clearing the alarm_enable When an alarm fires, the corresponding alarm_irq is set and alarm_running is cleared To clear the interrupt write a 1 to the corresponding alarm_irq The timer can be locked to prevent writing"]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Timer {
+    ptr: *mut u8,
+}
+unsafe impl Send for Timer {}
+unsafe impl Sync for Timer {}
+impl Timer {
+    #[inline(always)]
+    pub const unsafe fn from_ptr(ptr: *mut ()) -> Self {
+        Self { ptr: ptr as _ }
+    }
+    #[inline(always)]
+    pub const fn as_ptr(&self) -> *mut () {
+        self.ptr as _
+    }
+    #[doc = "Write to bits 63:32 of time always write timelw before timehw"]
+    #[inline(always)]
+    pub const fn timehw(self) -> crate::common::Reg<u32, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(0usize) as _) }
+    }
+    #[doc = "Write to bits 31:0 of time writes do not get copied to time until timehw is written"]
+    #[inline(always)]
+    pub const fn timelw(self) -> crate::common::Reg<u32, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(4usize) as _) }
+    }
+    #[doc = "Read from bits 63:32 of time always read timelr before timehr"]
+    #[inline(always)]
+    pub const fn timehr(self) -> crate::common::Reg<u32, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(8usize) as _) }
+    }
+    #[doc = "Read from bits 31:0 of time"]
+    #[inline(always)]
+    pub const fn timelr(self) -> crate::common::Reg<u32, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(12usize) as _) }
+    }
+    #[doc = "Arm alarm 0, and configure the time it will fire. Once armed, the alarm fires when TIMER_ALARM0 == TIMELR. The alarm will disarm itself once it fires, and can be disarmed early using the ARMED status register."]
+    #[inline(always)]
+    pub const fn alarm(self, n: usize) -> crate::common::Reg<u32, crate::common::RW> {
+        assert!(n < 4usize);
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(16usize + n * 4usize) as _) }
+    }
+    #[doc = "Indicates the armed/disarmed status of each alarm. A write to the corresponding ALARMx register arms the alarm. Alarms automatically disarm upon firing, but writing ones here will disarm immediately without waiting to fire."]
+    #[inline(always)]
+    pub const fn armed(self) -> crate::common::Reg<regs::Armed, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(32usize) as _) }
+    }
+    #[doc = "Raw read from bits 63:32 of time (no side effects)"]
+    #[inline(always)]
+    pub const fn timerawh(self) -> crate::common::Reg<u32, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(36usize) as _) }
+    }
+    #[doc = "Raw read from bits 31:0 of time (no side effects)"]
+    #[inline(always)]
+    pub const fn timerawl(self) -> crate::common::Reg<u32, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(40usize) as _) }
+    }
+    #[doc = "Set bits high to enable pause when the corresponding debug ports are active"]
+    #[inline(always)]
+    pub const fn dbgpause(self) -> crate::common::Reg<regs::Dbgpause, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(44usize) as _) }
+    }
+    #[doc = "Set high to pause the timer"]
+    #[inline(always)]
+    pub const fn pause(self) -> crate::common::Reg<regs::Pause, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(48usize) as _) }
+    }
+    #[doc = "Set locked bit to disable write access to timer Once set, cannot be cleared (without a reset)"]
+    #[inline(always)]
+    pub const fn locked(self) -> crate::common::Reg<regs::Locked, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(52usize) as _) }
+    }
+    #[doc = "Selects the source for the timer. Defaults to the normal tick configured in the ticks block (typically configured to 1 microsecond). Writing to 1 will ignore the tick and count clk_sys cycles instead."]
+    #[inline(always)]
+    pub const fn source(self) -> crate::common::Reg<regs::Source, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(56usize) as _) }
+    }
+    #[doc = "Raw Interrupts"]
+    #[inline(always)]
+    pub const fn intr(self) -> crate::common::Reg<regs::Int, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(60usize) as _) }
+    }
+    #[doc = "Interrupt Enable"]
+    #[inline(always)]
+    pub const fn inte(self) -> crate::common::Reg<regs::Int, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(64usize) as _) }
+    }
+    #[doc = "Interrupt Force"]
+    #[inline(always)]
+    pub const fn intf(self) -> crate::common::Reg<regs::Int, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(68usize) as _) }
+    }
+    #[doc = "Interrupt status after masking & forcing"]
+    #[inline(always)]
+    pub const fn ints(self) -> crate::common::Reg<regs::Int, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(72usize) as _) }
+    }
+}
+pub mod regs;
+pub mod vals;
diff --git a/src/rp2350/timer/regs.rs b/src/rp2350/timer/regs.rs
new file mode 100644
index 00000000..37212c31
--- /dev/null
+++ b/src/rp2350/timer/regs.rs
@@ -0,0 +1,143 @@
+#[doc = "Indicates the armed/disarmed status of each alarm. A write to the corresponding ALARMx register arms the alarm. Alarms automatically disarm upon firing, but writing ones here will disarm immediately without waiting to fire."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Armed(pub u32);
+impl Armed {
+    #[inline(always)]
+    pub const fn armed(&self) -> u8 {
+        let val = (self.0 >> 0usize) & 0x0f;
+        val as u8
+    }
+    #[inline(always)]
+    pub fn set_armed(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize);
+    }
+}
+impl Default for Armed {
+    #[inline(always)]
+    fn default() -> Armed {
+        Armed(0)
+    }
+}
+#[doc = "Set bits high to enable pause when the corresponding debug ports are active"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Dbgpause(pub u32);
+impl Dbgpause {
+    #[doc = "Pause when processor 0 is in debug mode"]
+    #[inline(always)]
+    pub const fn dbg0(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Pause when processor 0 is in debug mode"]
+    #[inline(always)]
+    pub fn set_dbg0(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+    #[doc = "Pause when processor 1 is in debug mode"]
+    #[inline(always)]
+    pub const fn dbg1(&self) -> bool {
+        let val = (self.0 >> 2usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Pause when processor 1 is in debug mode"]
+    #[inline(always)]
+    pub fn set_dbg1(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+    }
+}
+impl Default for Dbgpause {
+    #[inline(always)]
+    fn default() -> Dbgpause {
+        Dbgpause(0)
+    }
+}
+#[doc = "Interrupt Force"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Int(pub u32);
+impl Int {
+    #[inline(always)]
+    pub const fn alarm(&self, n: usize) -> bool {
+        assert!(n < 4usize);
+        let offs = 0usize + n * 1usize;
+        let val = (self.0 >> offs) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_alarm(&mut self, n: usize, val: bool) {
+        assert!(n < 4usize);
+        let offs = 0usize + n * 1usize;
+        self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
+    }
+}
+impl Default for Int {
+    #[inline(always)]
+    fn default() -> Int {
+        Int(0)
+    }
+}
+#[doc = "Set locked bit to disable write access to timer Once set, cannot be cleared (without a reset)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Locked(pub u32);
+impl Locked {
+    #[inline(always)]
+    pub const fn locked(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_locked(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+}
+impl Default for Locked {
+    #[inline(always)]
+    fn default() -> Locked {
+        Locked(0)
+    }
+}
+#[doc = "Set high to pause the timer"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Pause(pub u32);
+impl Pause {
+    #[inline(always)]
+    pub const fn pause(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_pause(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+}
+impl Default for Pause {
+    #[inline(always)]
+    fn default() -> Pause {
+        Pause(0)
+    }
+}
+#[doc = "Selects the source for the timer. Defaults to the normal tick configured in the ticks block (typically configured to 1 microsecond). Writing to 1 will ignore the tick and count clk_sys cycles instead."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Source(pub u32);
+impl Source {
+    #[inline(always)]
+    pub const fn clk_sys(&self) -> super::vals::ClkSys {
+        let val = (self.0 >> 0usize) & 0x01;
+        super::vals::ClkSys::from_bits(val as u8)
+    }
+    #[inline(always)]
+    pub fn set_clk_sys(&mut self, val: super::vals::ClkSys) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val.to_bits() as u32) & 0x01) << 0usize);
+    }
+}
+impl Default for Source {
+    #[inline(always)]
+    fn default() -> Source {
+        Source(0)
+    }
+}
diff --git a/src/rp2350/timer/vals.rs b/src/rp2350/timer/vals.rs
new file mode 100644
index 00000000..0c506c29
--- /dev/null
+++ b/src/rp2350/timer/vals.rs
@@ -0,0 +1,28 @@
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum ClkSys {
+    TICK = 0,
+    CLK_SYS = 0x01,
+}
+impl ClkSys {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> ClkSys {
+        unsafe { core::mem::transmute(val & 0x01) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for ClkSys {
+    #[inline(always)]
+    fn from(val: u8) -> ClkSys {
+        ClkSys::from_bits(val)
+    }
+}
+impl From<ClkSys> for u8 {
+    #[inline(always)]
+    fn from(val: ClkSys) -> u8 {
+        ClkSys::to_bits(val)
+    }
+}
diff --git a/src/rp2350/trng.rs b/src/rp2350/trng.rs
new file mode 100644
index 00000000..08b8ce85
--- /dev/null
+++ b/src/rp2350/trng.rs
@@ -0,0 +1,149 @@
+#[doc = "ARM TrustZone RNG register block"]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Trng {
+    ptr: *mut u8,
+}
+unsafe impl Send for Trng {}
+unsafe impl Sync for Trng {}
+impl Trng {
+    #[inline(always)]
+    pub const unsafe fn from_ptr(ptr: *mut ()) -> Self {
+        Self { ptr: ptr as _ }
+    }
+    #[inline(always)]
+    pub const fn as_ptr(&self) -> *mut () {
+        self.ptr as _
+    }
+    #[doc = "Interrupt masking."]
+    #[inline(always)]
+    pub const fn rng_imr(self) -> crate::common::Reg<regs::RngImr, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(256usize) as _) }
+    }
+    #[doc = "RNG status register. If corresponding RNG_IMR bit is unmasked, an interrupt will be generated."]
+    #[inline(always)]
+    pub const fn rng_isr(self) -> crate::common::Reg<regs::RngIsr, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(260usize) as _) }
+    }
+    #[doc = "Interrupt/status bit clear Register."]
+    #[inline(always)]
+    pub const fn rng_icr(self) -> crate::common::Reg<regs::RngIcr, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(264usize) as _) }
+    }
+    #[doc = "Selecting the inverter-chain length."]
+    #[inline(always)]
+    pub const fn trng_config(self) -> crate::common::Reg<regs::TrngConfig, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(268usize) as _) }
+    }
+    #[doc = "192 bit collection indication."]
+    #[inline(always)]
+    pub const fn trng_valid(self) -> crate::common::Reg<regs::TrngValid, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(272usize) as _) }
+    }
+    #[doc = "RNG collected bits."]
+    #[inline(always)]
+    pub const fn ehr_data0(self) -> crate::common::Reg<u32, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(276usize) as _) }
+    }
+    #[doc = "RNG collected bits."]
+    #[inline(always)]
+    pub const fn ehr_data1(self) -> crate::common::Reg<u32, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(280usize) as _) }
+    }
+    #[doc = "RNG collected bits."]
+    #[inline(always)]
+    pub const fn ehr_data2(self) -> crate::common::Reg<u32, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(284usize) as _) }
+    }
+    #[doc = "RNG collected bits."]
+    #[inline(always)]
+    pub const fn ehr_data3(self) -> crate::common::Reg<u32, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(288usize) as _) }
+    }
+    #[doc = "RNG collected bits."]
+    #[inline(always)]
+    pub const fn ehr_data4(self) -> crate::common::Reg<u32, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(292usize) as _) }
+    }
+    #[doc = "RNG collected bits."]
+    #[inline(always)]
+    pub const fn ehr_data5(self) -> crate::common::Reg<u32, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(296usize) as _) }
+    }
+    #[doc = "Enable signal for the random source."]
+    #[inline(always)]
+    pub const fn rnd_source_enable(
+        self,
+    ) -> crate::common::Reg<regs::RndSourceEnable, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(300usize) as _) }
+    }
+    #[doc = "Counts clocks between sampling of random bit."]
+    #[inline(always)]
+    pub const fn sample_cnt1(self) -> crate::common::Reg<u32, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(304usize) as _) }
+    }
+    #[doc = "Statistic about Autocorrelation test activations."]
+    #[inline(always)]
+    pub const fn autocorr_statistic(
+        self,
+    ) -> crate::common::Reg<regs::AutocorrStatistic, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(308usize) as _) }
+    }
+    #[doc = "Debug register."]
+    #[inline(always)]
+    pub const fn trng_debug_control(
+        self,
+    ) -> crate::common::Reg<regs::TrngDebugControl, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(312usize) as _) }
+    }
+    #[doc = "Generate internal SW reset within the RNG block."]
+    #[inline(always)]
+    pub const fn trng_sw_reset(self) -> crate::common::Reg<regs::TrngSwReset, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(320usize) as _) }
+    }
+    #[doc = "Enable the RNG debug mode"]
+    #[inline(always)]
+    pub const fn rng_debug_en_input(
+        self,
+    ) -> crate::common::Reg<regs::RngDebugEnInput, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(436usize) as _) }
+    }
+    #[doc = "RNG Busy indication."]
+    #[inline(always)]
+    pub const fn trng_busy(self) -> crate::common::Reg<regs::TrngBusy, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(440usize) as _) }
+    }
+    #[doc = "Reset the counter of collected bits in the RNG."]
+    #[inline(always)]
+    pub const fn rst_bits_counter(
+        self,
+    ) -> crate::common::Reg<regs::RstBitsCounter, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(444usize) as _) }
+    }
+    #[doc = "Displays the version settings of the TRNG."]
+    #[inline(always)]
+    pub const fn rng_version(self) -> crate::common::Reg<regs::RngVersion, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(448usize) as _) }
+    }
+    #[doc = "Collected BIST results."]
+    #[inline(always)]
+    pub const fn rng_bist_cntr_0(
+        self,
+    ) -> crate::common::Reg<regs::RngBistCntr0, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(480usize) as _) }
+    }
+    #[doc = "Collected BIST results."]
+    #[inline(always)]
+    pub const fn rng_bist_cntr_1(
+        self,
+    ) -> crate::common::Reg<regs::RngBistCntr1, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(484usize) as _) }
+    }
+    #[doc = "Collected BIST results."]
+    #[inline(always)]
+    pub const fn rng_bist_cntr_2(
+        self,
+    ) -> crate::common::Reg<regs::RngBistCntr2, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(488usize) as _) }
+    }
+}
+pub mod regs;
diff --git a/src/rp2350/trng/regs.rs b/src/rp2350/trng/regs.rs
new file mode 100644
index 00000000..fdb174e3
--- /dev/null
+++ b/src/rp2350/trng/regs.rs
@@ -0,0 +1,753 @@
+#[doc = "Statistic about Autocorrelation test activations."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct AutocorrStatistic(pub u32);
+impl AutocorrStatistic {
+    #[doc = "Count each time an autocorrelation test starts. Any write to the register reset the counter. Stop collecting statistic if one of the counters reached the limit."]
+    #[inline(always)]
+    pub const fn autocorr_trys(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0x3fff;
+        val as u16
+    }
+    #[doc = "Count each time an autocorrelation test starts. Any write to the register reset the counter. Stop collecting statistic if one of the counters reached the limit."]
+    #[inline(always)]
+    pub fn set_autocorr_trys(&mut self, val: u16) {
+        self.0 = (self.0 & !(0x3fff << 0usize)) | (((val as u32) & 0x3fff) << 0usize);
+    }
+    #[doc = "Count each time an autocorrelation test fails. Any write to the register reset the counter. Stop collecting statistic if one of the counters reached the limit."]
+    #[inline(always)]
+    pub const fn autocorr_fails(&self) -> u8 {
+        let val = (self.0 >> 14usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Count each time an autocorrelation test fails. Any write to the register reset the counter. Stop collecting statistic if one of the counters reached the limit."]
+    #[inline(always)]
+    pub fn set_autocorr_fails(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 14usize)) | (((val as u32) & 0xff) << 14usize);
+    }
+    #[doc = "RESERVED"]
+    #[inline(always)]
+    pub const fn reserved(&self) -> u16 {
+        let val = (self.0 >> 22usize) & 0x03ff;
+        val as u16
+    }
+    #[doc = "RESERVED"]
+    #[inline(always)]
+    pub fn set_reserved(&mut self, val: u16) {
+        self.0 = (self.0 & !(0x03ff << 22usize)) | (((val as u32) & 0x03ff) << 22usize);
+    }
+}
+impl Default for AutocorrStatistic {
+    #[inline(always)]
+    fn default() -> AutocorrStatistic {
+        AutocorrStatistic(0)
+    }
+}
+#[doc = "Enable signal for the random source."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct RndSourceEnable(pub u32);
+impl RndSourceEnable {
+    #[doc = "* 1'b1 - entropy source is enabled. *1'b0 - entropy source is disabled"]
+    #[inline(always)]
+    pub const fn rnd_src_en(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "* 1'b1 - entropy source is enabled. *1'b0 - entropy source is disabled"]
+    #[inline(always)]
+    pub fn set_rnd_src_en(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[doc = "RESERVED"]
+    #[inline(always)]
+    pub const fn reserved(&self) -> u32 {
+        let val = (self.0 >> 1usize) & 0x7fff_ffff;
+        val as u32
+    }
+    #[doc = "RESERVED"]
+    #[inline(always)]
+    pub fn set_reserved(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x7fff_ffff << 1usize)) | (((val as u32) & 0x7fff_ffff) << 1usize);
+    }
+}
+impl Default for RndSourceEnable {
+    #[inline(always)]
+    fn default() -> RndSourceEnable {
+        RndSourceEnable(0)
+    }
+}
+#[doc = "Collected BIST results."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct RngBistCntr0(pub u32);
+impl RngBistCntr0 {
+    #[doc = "Reflects the results of RNG BIST counter."]
+    #[inline(always)]
+    pub const fn rosc_cntr_val(&self) -> u32 {
+        let val = (self.0 >> 0usize) & 0x003f_ffff;
+        val as u32
+    }
+    #[doc = "Reflects the results of RNG BIST counter."]
+    #[inline(always)]
+    pub fn set_rosc_cntr_val(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x003f_ffff << 0usize)) | (((val as u32) & 0x003f_ffff) << 0usize);
+    }
+    #[doc = "RESERVED"]
+    #[inline(always)]
+    pub const fn reserved(&self) -> u16 {
+        let val = (self.0 >> 22usize) & 0x03ff;
+        val as u16
+    }
+    #[doc = "RESERVED"]
+    #[inline(always)]
+    pub fn set_reserved(&mut self, val: u16) {
+        self.0 = (self.0 & !(0x03ff << 22usize)) | (((val as u32) & 0x03ff) << 22usize);
+    }
+}
+impl Default for RngBistCntr0 {
+    #[inline(always)]
+    fn default() -> RngBistCntr0 {
+        RngBistCntr0(0)
+    }
+}
+#[doc = "Collected BIST results."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct RngBistCntr1(pub u32);
+impl RngBistCntr1 {
+    #[doc = "Reflects the results of RNG BIST counter."]
+    #[inline(always)]
+    pub const fn rosc_cntr_val(&self) -> u32 {
+        let val = (self.0 >> 0usize) & 0x003f_ffff;
+        val as u32
+    }
+    #[doc = "Reflects the results of RNG BIST counter."]
+    #[inline(always)]
+    pub fn set_rosc_cntr_val(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x003f_ffff << 0usize)) | (((val as u32) & 0x003f_ffff) << 0usize);
+    }
+    #[doc = "RESERVED"]
+    #[inline(always)]
+    pub const fn reserved(&self) -> u16 {
+        let val = (self.0 >> 22usize) & 0x03ff;
+        val as u16
+    }
+    #[doc = "RESERVED"]
+    #[inline(always)]
+    pub fn set_reserved(&mut self, val: u16) {
+        self.0 = (self.0 & !(0x03ff << 22usize)) | (((val as u32) & 0x03ff) << 22usize);
+    }
+}
+impl Default for RngBistCntr1 {
+    #[inline(always)]
+    fn default() -> RngBistCntr1 {
+        RngBistCntr1(0)
+    }
+}
+#[doc = "Collected BIST results."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct RngBistCntr2(pub u32);
+impl RngBistCntr2 {
+    #[doc = "Reflects the results of RNG BIST counter."]
+    #[inline(always)]
+    pub const fn rosc_cntr_val(&self) -> u32 {
+        let val = (self.0 >> 0usize) & 0x003f_ffff;
+        val as u32
+    }
+    #[doc = "Reflects the results of RNG BIST counter."]
+    #[inline(always)]
+    pub fn set_rosc_cntr_val(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x003f_ffff << 0usize)) | (((val as u32) & 0x003f_ffff) << 0usize);
+    }
+    #[doc = "RESERVED"]
+    #[inline(always)]
+    pub const fn reserved(&self) -> u16 {
+        let val = (self.0 >> 22usize) & 0x03ff;
+        val as u16
+    }
+    #[doc = "RESERVED"]
+    #[inline(always)]
+    pub fn set_reserved(&mut self, val: u16) {
+        self.0 = (self.0 & !(0x03ff << 22usize)) | (((val as u32) & 0x03ff) << 22usize);
+    }
+}
+impl Default for RngBistCntr2 {
+    #[inline(always)]
+    fn default() -> RngBistCntr2 {
+        RngBistCntr2(0)
+    }
+}
+#[doc = "Enable the RNG debug mode"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct RngDebugEnInput(pub u32);
+impl RngDebugEnInput {
+    #[doc = "* 1'b1 - debug mode is enabled. *1'b0 - debug mode is disabled"]
+    #[inline(always)]
+    pub const fn rng_debug_en(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "* 1'b1 - debug mode is enabled. *1'b0 - debug mode is disabled"]
+    #[inline(always)]
+    pub fn set_rng_debug_en(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[doc = "RESERVED"]
+    #[inline(always)]
+    pub const fn reserved(&self) -> u32 {
+        let val = (self.0 >> 1usize) & 0x7fff_ffff;
+        val as u32
+    }
+    #[doc = "RESERVED"]
+    #[inline(always)]
+    pub fn set_reserved(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x7fff_ffff << 1usize)) | (((val as u32) & 0x7fff_ffff) << 1usize);
+    }
+}
+impl Default for RngDebugEnInput {
+    #[inline(always)]
+    fn default() -> RngDebugEnInput {
+        RngDebugEnInput(0)
+    }
+}
+#[doc = "Interrupt/status bit clear Register."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct RngIcr(pub u32);
+impl RngIcr {
+    #[doc = "Write 1'b1 - clear corresponding bit in RNG_ISR."]
+    #[inline(always)]
+    pub const fn ehr_valid(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Write 1'b1 - clear corresponding bit in RNG_ISR."]
+    #[inline(always)]
+    pub fn set_ehr_valid(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[doc = "Cannot be cleared by SW! Only RNG reset clears this bit."]
+    #[inline(always)]
+    pub const fn autocorr_err(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Cannot be cleared by SW! Only RNG reset clears this bit."]
+    #[inline(always)]
+    pub fn set_autocorr_err(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+    #[doc = "Write 1'b1 - clear corresponding bit in RNG_ISR."]
+    #[inline(always)]
+    pub const fn crngt_err(&self) -> bool {
+        let val = (self.0 >> 2usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Write 1'b1 - clear corresponding bit in RNG_ISR."]
+    #[inline(always)]
+    pub fn set_crngt_err(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+    }
+    #[doc = "Write 1'b1 - clear corresponding bit in RNG_ISR."]
+    #[inline(always)]
+    pub const fn vn_err(&self) -> bool {
+        let val = (self.0 >> 3usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Write 1'b1 - clear corresponding bit in RNG_ISR."]
+    #[inline(always)]
+    pub fn set_vn_err(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
+    }
+    #[doc = "RESERVED"]
+    #[inline(always)]
+    pub const fn reserved(&self) -> u32 {
+        let val = (self.0 >> 4usize) & 0x0fff_ffff;
+        val as u32
+    }
+    #[doc = "RESERVED"]
+    #[inline(always)]
+    pub fn set_reserved(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x0fff_ffff << 4usize)) | (((val as u32) & 0x0fff_ffff) << 4usize);
+    }
+}
+impl Default for RngIcr {
+    #[inline(always)]
+    fn default() -> RngIcr {
+        RngIcr(0)
+    }
+}
+#[doc = "Interrupt masking."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct RngImr(pub u32);
+impl RngImr {
+    #[doc = "1'b1-mask interrupt, no interrupt will be generated. See RNG_ISR for an explanation on this interrupt."]
+    #[inline(always)]
+    pub const fn ehr_valid_int_mask(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "1'b1-mask interrupt, no interrupt will be generated. See RNG_ISR for an explanation on this interrupt."]
+    #[inline(always)]
+    pub fn set_ehr_valid_int_mask(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[doc = "1'b1-mask interrupt, no interrupt will be generated. See RNG_ISR for an explanation on this interrupt."]
+    #[inline(always)]
+    pub const fn autocorr_err_int_mask(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[doc = "1'b1-mask interrupt, no interrupt will be generated. See RNG_ISR for an explanation on this interrupt."]
+    #[inline(always)]
+    pub fn set_autocorr_err_int_mask(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+    #[doc = "1'b1-mask interrupt, no interrupt will be generated. See RNG_ISR for an explanation on this interrupt."]
+    #[inline(always)]
+    pub const fn crngt_err_int_mask(&self) -> bool {
+        let val = (self.0 >> 2usize) & 0x01;
+        val != 0
+    }
+    #[doc = "1'b1-mask interrupt, no interrupt will be generated. See RNG_ISR for an explanation on this interrupt."]
+    #[inline(always)]
+    pub fn set_crngt_err_int_mask(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+    }
+    #[doc = "1'b1-mask interrupt, no interrupt will be generated. See RNG_ISR for an explanation on this interrupt."]
+    #[inline(always)]
+    pub const fn vn_err_int_mask(&self) -> bool {
+        let val = (self.0 >> 3usize) & 0x01;
+        val != 0
+    }
+    #[doc = "1'b1-mask interrupt, no interrupt will be generated. See RNG_ISR for an explanation on this interrupt."]
+    #[inline(always)]
+    pub fn set_vn_err_int_mask(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
+    }
+    #[doc = "RESERVED"]
+    #[inline(always)]
+    pub const fn reserved(&self) -> u32 {
+        let val = (self.0 >> 4usize) & 0x0fff_ffff;
+        val as u32
+    }
+    #[doc = "RESERVED"]
+    #[inline(always)]
+    pub fn set_reserved(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x0fff_ffff << 4usize)) | (((val as u32) & 0x0fff_ffff) << 4usize);
+    }
+}
+impl Default for RngImr {
+    #[inline(always)]
+    fn default() -> RngImr {
+        RngImr(0)
+    }
+}
+#[doc = "RNG status register. If corresponding RNG_IMR bit is unmasked, an interrupt will be generated."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct RngIsr(pub u32);
+impl RngIsr {
+    #[doc = "1'b1 indicates that 192 bits have been collected in the RNG, and are ready to be read."]
+    #[inline(always)]
+    pub const fn ehr_valid(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "1'b1 indicates that 192 bits have been collected in the RNG, and are ready to be read."]
+    #[inline(always)]
+    pub fn set_ehr_valid(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[doc = "1'b1 indicates Autocorrelation test failed four times in a row. When set, RNG cease from functioning until next reset."]
+    #[inline(always)]
+    pub const fn autocorr_err(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[doc = "1'b1 indicates Autocorrelation test failed four times in a row. When set, RNG cease from functioning until next reset."]
+    #[inline(always)]
+    pub fn set_autocorr_err(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+    #[doc = "1'b1 indicates CRNGT in the RNG test failed. Failure occurs when two consecutive blocks of 16 collected bits are equal."]
+    #[inline(always)]
+    pub const fn crngt_err(&self) -> bool {
+        let val = (self.0 >> 2usize) & 0x01;
+        val != 0
+    }
+    #[doc = "1'b1 indicates CRNGT in the RNG test failed. Failure occurs when two consecutive blocks of 16 collected bits are equal."]
+    #[inline(always)]
+    pub fn set_crngt_err(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+    }
+    #[doc = "1'b1 indicates Von Neuman error. Error in von Neuman occurs if 32 consecutive collected bits are identical, ZERO or ONE."]
+    #[inline(always)]
+    pub const fn vn_err(&self) -> bool {
+        let val = (self.0 >> 3usize) & 0x01;
+        val != 0
+    }
+    #[doc = "1'b1 indicates Von Neuman error. Error in von Neuman occurs if 32 consecutive collected bits are identical, ZERO or ONE."]
+    #[inline(always)]
+    pub fn set_vn_err(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
+    }
+    #[doc = "RESERVED"]
+    #[inline(always)]
+    pub const fn reserved(&self) -> u32 {
+        let val = (self.0 >> 4usize) & 0x0fff_ffff;
+        val as u32
+    }
+    #[doc = "RESERVED"]
+    #[inline(always)]
+    pub fn set_reserved(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x0fff_ffff << 4usize)) | (((val as u32) & 0x0fff_ffff) << 4usize);
+    }
+}
+impl Default for RngIsr {
+    #[inline(always)]
+    fn default() -> RngIsr {
+        RngIsr(0)
+    }
+}
+#[doc = "Displays the version settings of the TRNG."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct RngVersion(pub u32);
+impl RngVersion {
+    #[doc = "* 1'b1 - 192-bit EHR. *1'b0 - 128-bit EHR"]
+    #[inline(always)]
+    pub const fn ehr_width_192(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "* 1'b1 - 192-bit EHR. *1'b0 - 128-bit EHR"]
+    #[inline(always)]
+    pub fn set_ehr_width_192(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[doc = "* 1'b1 - Exists. *1'b0 - Does not exist"]
+    #[inline(always)]
+    pub const fn crngt_exists(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[doc = "* 1'b1 - Exists. *1'b0 - Does not exist"]
+    #[inline(always)]
+    pub fn set_crngt_exists(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+    #[doc = "* 1'b1 - Exists. *1'b0 - Does not exist"]
+    #[inline(always)]
+    pub const fn autocorr_exists(&self) -> bool {
+        let val = (self.0 >> 2usize) & 0x01;
+        val != 0
+    }
+    #[doc = "* 1'b1 - Exists. *1'b0 - Does not exist"]
+    #[inline(always)]
+    pub fn set_autocorr_exists(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+    }
+    #[doc = "* 1'b1 - Exists. *1'b0 - Does not exist"]
+    #[inline(always)]
+    pub const fn trng_tests_bypass_en(&self) -> bool {
+        let val = (self.0 >> 3usize) & 0x01;
+        val != 0
+    }
+    #[doc = "* 1'b1 - Exists. *1'b0 - Does not exist"]
+    #[inline(always)]
+    pub fn set_trng_tests_bypass_en(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
+    }
+    #[doc = "* 1'b1 - Exists. *1'b0 - Does not exist"]
+    #[inline(always)]
+    pub const fn prng_exists(&self) -> bool {
+        let val = (self.0 >> 4usize) & 0x01;
+        val != 0
+    }
+    #[doc = "* 1'b1 - Exists. *1'b0 - Does not exist"]
+    #[inline(always)]
+    pub fn set_prng_exists(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
+    }
+    #[doc = "* 1'b1 - Exists. *1'b0 - Does not exist"]
+    #[inline(always)]
+    pub const fn kat_exists(&self) -> bool {
+        let val = (self.0 >> 5usize) & 0x01;
+        val != 0
+    }
+    #[doc = "* 1'b1 - Exists. *1'b0 - Does not exist"]
+    #[inline(always)]
+    pub fn set_kat_exists(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
+    }
+    #[doc = "* 1'b1 - Exists. *1'b0 - Does not exist"]
+    #[inline(always)]
+    pub const fn reseeding_exists(&self) -> bool {
+        let val = (self.0 >> 6usize) & 0x01;
+        val != 0
+    }
+    #[doc = "* 1'b1 - Exists. *1'b0 - Does not exist"]
+    #[inline(always)]
+    pub fn set_reseeding_exists(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
+    }
+    #[doc = "* 1'b1 - 5 SBOX AES. *1'b0 - 20 SBOX AES"]
+    #[inline(always)]
+    pub const fn rng_use_5_sboxes(&self) -> bool {
+        let val = (self.0 >> 7usize) & 0x01;
+        val != 0
+    }
+    #[doc = "* 1'b1 - 5 SBOX AES. *1'b0 - 20 SBOX AES"]
+    #[inline(always)]
+    pub fn set_rng_use_5_sboxes(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
+    }
+    #[doc = "RESERVED"]
+    #[inline(always)]
+    pub const fn reserved(&self) -> u32 {
+        let val = (self.0 >> 8usize) & 0x00ff_ffff;
+        val as u32
+    }
+    #[doc = "RESERVED"]
+    #[inline(always)]
+    pub fn set_reserved(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x00ff_ffff << 8usize)) | (((val as u32) & 0x00ff_ffff) << 8usize);
+    }
+}
+impl Default for RngVersion {
+    #[inline(always)]
+    fn default() -> RngVersion {
+        RngVersion(0)
+    }
+}
+#[doc = "Reset the counter of collected bits in the RNG."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct RstBitsCounter(pub u32);
+impl RstBitsCounter {
+    #[doc = "Writing any value to this address will reset the bits counter and RNG valid registers. RND_SORCE_ENABLE register must be unset in order for the reset to take place."]
+    #[inline(always)]
+    pub const fn rst_bits_counter(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Writing any value to this address will reset the bits counter and RNG valid registers. RND_SORCE_ENABLE register must be unset in order for the reset to take place."]
+    #[inline(always)]
+    pub fn set_rst_bits_counter(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[doc = "RESERVED"]
+    #[inline(always)]
+    pub const fn reserved(&self) -> u32 {
+        let val = (self.0 >> 1usize) & 0x7fff_ffff;
+        val as u32
+    }
+    #[doc = "RESERVED"]
+    #[inline(always)]
+    pub fn set_reserved(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x7fff_ffff << 1usize)) | (((val as u32) & 0x7fff_ffff) << 1usize);
+    }
+}
+impl Default for RstBitsCounter {
+    #[inline(always)]
+    fn default() -> RstBitsCounter {
+        RstBitsCounter(0)
+    }
+}
+#[doc = "RNG Busy indication."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct TrngBusy(pub u32);
+impl TrngBusy {
+    #[doc = "Reflects rng_busy status."]
+    #[inline(always)]
+    pub const fn trng_busy(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Reflects rng_busy status."]
+    #[inline(always)]
+    pub fn set_trng_busy(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[doc = "RESERVED"]
+    #[inline(always)]
+    pub const fn reserved(&self) -> u32 {
+        let val = (self.0 >> 1usize) & 0x7fff_ffff;
+        val as u32
+    }
+    #[doc = "RESERVED"]
+    #[inline(always)]
+    pub fn set_reserved(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x7fff_ffff << 1usize)) | (((val as u32) & 0x7fff_ffff) << 1usize);
+    }
+}
+impl Default for TrngBusy {
+    #[inline(always)]
+    fn default() -> TrngBusy {
+        TrngBusy(0)
+    }
+}
+#[doc = "Selecting the inverter-chain length."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct TrngConfig(pub u32);
+impl TrngConfig {
+    #[doc = "Selects the number of inverters (out of four possible selections) in the ring oscillator (the entropy source)."]
+    #[inline(always)]
+    pub const fn rnd_src_sel(&self) -> u8 {
+        let val = (self.0 >> 0usize) & 0x03;
+        val as u8
+    }
+    #[doc = "Selects the number of inverters (out of four possible selections) in the ring oscillator (the entropy source)."]
+    #[inline(always)]
+    pub fn set_rnd_src_sel(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x03 << 0usize)) | (((val as u32) & 0x03) << 0usize);
+    }
+    #[doc = "RESERVED"]
+    #[inline(always)]
+    pub const fn reserved(&self) -> u32 {
+        let val = (self.0 >> 2usize) & 0x3fff_ffff;
+        val as u32
+    }
+    #[doc = "RESERVED"]
+    #[inline(always)]
+    pub fn set_reserved(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x3fff_ffff << 2usize)) | (((val as u32) & 0x3fff_ffff) << 2usize);
+    }
+}
+impl Default for TrngConfig {
+    #[inline(always)]
+    fn default() -> TrngConfig {
+        TrngConfig(0)
+    }
+}
+#[doc = "Debug register."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct TrngDebugControl(pub u32);
+impl TrngDebugControl {
+    #[doc = "N/A"]
+    #[inline(always)]
+    pub const fn reserved(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "N/A"]
+    #[inline(always)]
+    pub fn set_reserved(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[doc = "When set, the Von-Neuman balancer is bypassed (including the 32 consecutive bits test)."]
+    #[inline(always)]
+    pub const fn vnc_bypass(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[doc = "When set, the Von-Neuman balancer is bypassed (including the 32 consecutive bits test)."]
+    #[inline(always)]
+    pub fn set_vnc_bypass(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+    #[doc = "When set, the CRNGT test in the RNG is bypassed."]
+    #[inline(always)]
+    pub const fn trng_crngt_bypass(&self) -> bool {
+        let val = (self.0 >> 2usize) & 0x01;
+        val != 0
+    }
+    #[doc = "When set, the CRNGT test in the RNG is bypassed."]
+    #[inline(always)]
+    pub fn set_trng_crngt_bypass(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+    }
+    #[doc = "When set, the autocorrelation test in the TRNG module is bypassed."]
+    #[inline(always)]
+    pub const fn auto_correlate_bypass(&self) -> bool {
+        let val = (self.0 >> 3usize) & 0x01;
+        val != 0
+    }
+    #[doc = "When set, the autocorrelation test in the TRNG module is bypassed."]
+    #[inline(always)]
+    pub fn set_auto_correlate_bypass(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
+    }
+}
+impl Default for TrngDebugControl {
+    #[inline(always)]
+    fn default() -> TrngDebugControl {
+        TrngDebugControl(0)
+    }
+}
+#[doc = "Generate internal SW reset within the RNG block."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct TrngSwReset(pub u32);
+impl TrngSwReset {
+    #[doc = "Writing 1'b1 to this register causes an internal RNG reset."]
+    #[inline(always)]
+    pub const fn trng_sw_reset(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Writing 1'b1 to this register causes an internal RNG reset."]
+    #[inline(always)]
+    pub fn set_trng_sw_reset(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[doc = "RESERVED"]
+    #[inline(always)]
+    pub const fn reserved(&self) -> u32 {
+        let val = (self.0 >> 1usize) & 0x7fff_ffff;
+        val as u32
+    }
+    #[doc = "RESERVED"]
+    #[inline(always)]
+    pub fn set_reserved(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x7fff_ffff << 1usize)) | (((val as u32) & 0x7fff_ffff) << 1usize);
+    }
+}
+impl Default for TrngSwReset {
+    #[inline(always)]
+    fn default() -> TrngSwReset {
+        TrngSwReset(0)
+    }
+}
+#[doc = "192 bit collection indication."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct TrngValid(pub u32);
+impl TrngValid {
+    #[doc = "1'b1 indicates that collection of bits in the RNG is completed, and data can be read from EHR_DATA register."]
+    #[inline(always)]
+    pub const fn ehr_valid(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "1'b1 indicates that collection of bits in the RNG is completed, and data can be read from EHR_DATA register."]
+    #[inline(always)]
+    pub fn set_ehr_valid(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[doc = "RESERVED"]
+    #[inline(always)]
+    pub const fn reserved(&self) -> u32 {
+        let val = (self.0 >> 1usize) & 0x7fff_ffff;
+        val as u32
+    }
+    #[doc = "RESERVED"]
+    #[inline(always)]
+    pub fn set_reserved(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x7fff_ffff << 1usize)) | (((val as u32) & 0x7fff_ffff) << 1usize);
+    }
+}
+impl Default for TrngValid {
+    #[inline(always)]
+    fn default() -> TrngValid {
+        TrngValid(0)
+    }
+}
diff --git a/src/rp2350/uart.rs b/src/rp2350/uart.rs
new file mode 100644
index 00000000..078cce38
--- /dev/null
+++ b/src/rp2350/uart.rs
@@ -0,0 +1,127 @@
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Uart {
+    ptr: *mut u8,
+}
+unsafe impl Send for Uart {}
+unsafe impl Sync for Uart {}
+impl Uart {
+    #[inline(always)]
+    pub const unsafe fn from_ptr(ptr: *mut ()) -> Self {
+        Self { ptr: ptr as _ }
+    }
+    #[inline(always)]
+    pub const fn as_ptr(&self) -> *mut () {
+        self.ptr as _
+    }
+    #[doc = "Data Register, UARTDR"]
+    #[inline(always)]
+    pub const fn uartdr(self) -> crate::common::Reg<regs::Uartdr, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(0usize) as _) }
+    }
+    #[doc = "Receive Status Register/Error Clear Register, UARTRSR/UARTECR"]
+    #[inline(always)]
+    pub const fn uartrsr(self) -> crate::common::Reg<regs::Uartrsr, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(4usize) as _) }
+    }
+    #[doc = "Flag Register, UARTFR"]
+    #[inline(always)]
+    pub const fn uartfr(self) -> crate::common::Reg<regs::Uartfr, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(24usize) as _) }
+    }
+    #[doc = "IrDA Low-Power Counter Register, UARTILPR"]
+    #[inline(always)]
+    pub const fn uartilpr(self) -> crate::common::Reg<regs::Uartilpr, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(32usize) as _) }
+    }
+    #[doc = "Integer Baud Rate Register, UARTIBRD"]
+    #[inline(always)]
+    pub const fn uartibrd(self) -> crate::common::Reg<regs::Uartibrd, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(36usize) as _) }
+    }
+    #[doc = "Fractional Baud Rate Register, UARTFBRD"]
+    #[inline(always)]
+    pub const fn uartfbrd(self) -> crate::common::Reg<regs::Uartfbrd, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(40usize) as _) }
+    }
+    #[doc = "Line Control Register, UARTLCR_H"]
+    #[inline(always)]
+    pub const fn uartlcr_h(self) -> crate::common::Reg<regs::UartlcrH, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(44usize) as _) }
+    }
+    #[doc = "Control Register, UARTCR"]
+    #[inline(always)]
+    pub const fn uartcr(self) -> crate::common::Reg<regs::Uartcr, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(48usize) as _) }
+    }
+    #[doc = "Interrupt FIFO Level Select Register, UARTIFLS"]
+    #[inline(always)]
+    pub const fn uartifls(self) -> crate::common::Reg<regs::Uartifls, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(52usize) as _) }
+    }
+    #[doc = "Interrupt Mask Set/Clear Register, UARTIMSC"]
+    #[inline(always)]
+    pub const fn uartimsc(self) -> crate::common::Reg<regs::Uartimsc, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(56usize) as _) }
+    }
+    #[doc = "Raw Interrupt Status Register, UARTRIS"]
+    #[inline(always)]
+    pub const fn uartris(self) -> crate::common::Reg<regs::Uartris, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(60usize) as _) }
+    }
+    #[doc = "Masked Interrupt Status Register, UARTMIS"]
+    #[inline(always)]
+    pub const fn uartmis(self) -> crate::common::Reg<regs::Uartmis, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(64usize) as _) }
+    }
+    #[doc = "Interrupt Clear Register, UARTICR"]
+    #[inline(always)]
+    pub const fn uarticr(self) -> crate::common::Reg<regs::Uarticr, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(68usize) as _) }
+    }
+    #[doc = "DMA Control Register, UARTDMACR"]
+    #[inline(always)]
+    pub const fn uartdmacr(self) -> crate::common::Reg<regs::Uartdmacr, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(72usize) as _) }
+    }
+    #[doc = "UARTPeriphID0 Register"]
+    #[inline(always)]
+    pub const fn uartperiphid0(self) -> crate::common::Reg<regs::Uartperiphid0, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(4064usize) as _) }
+    }
+    #[doc = "UARTPeriphID1 Register"]
+    #[inline(always)]
+    pub const fn uartperiphid1(self) -> crate::common::Reg<regs::Uartperiphid1, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(4068usize) as _) }
+    }
+    #[doc = "UARTPeriphID2 Register"]
+    #[inline(always)]
+    pub const fn uartperiphid2(self) -> crate::common::Reg<regs::Uartperiphid2, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(4072usize) as _) }
+    }
+    #[doc = "UARTPeriphID3 Register"]
+    #[inline(always)]
+    pub const fn uartperiphid3(self) -> crate::common::Reg<regs::Uartperiphid3, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(4076usize) as _) }
+    }
+    #[doc = "UARTPCellID0 Register"]
+    #[inline(always)]
+    pub const fn uartpcellid0(self) -> crate::common::Reg<regs::Uartpcellid0, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(4080usize) as _) }
+    }
+    #[doc = "UARTPCellID1 Register"]
+    #[inline(always)]
+    pub const fn uartpcellid1(self) -> crate::common::Reg<regs::Uartpcellid1, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(4084usize) as _) }
+    }
+    #[doc = "UARTPCellID2 Register"]
+    #[inline(always)]
+    pub const fn uartpcellid2(self) -> crate::common::Reg<regs::Uartpcellid2, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(4088usize) as _) }
+    }
+    #[doc = "UARTPCellID3 Register"]
+    #[inline(always)]
+    pub const fn uartpcellid3(self) -> crate::common::Reg<regs::Uartpcellid3, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(4092usize) as _) }
+    }
+}
+pub mod regs;
diff --git a/src/rp2350/uart/regs.rs b/src/rp2350/uart/regs.rs
new file mode 100644
index 00000000..048d8929
--- /dev/null
+++ b/src/rp2350/uart/regs.rs
@@ -0,0 +1,1353 @@
+#[doc = "Control Register, UARTCR"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Uartcr(pub u32);
+impl Uartcr {
+    #[doc = "UART enable: 0 = UART is disabled. If the UART is disabled in the middle of transmission or reception, it completes the current character before stopping. 1 = the UART is enabled. Data transmission and reception occurs for either UART signals or SIR signals depending on the setting of the SIREN bit."]
+    #[inline(always)]
+    pub const fn uarten(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "UART enable: 0 = UART is disabled. If the UART is disabled in the middle of transmission or reception, it completes the current character before stopping. 1 = the UART is enabled. Data transmission and reception occurs for either UART signals or SIR signals depending on the setting of the SIREN bit."]
+    #[inline(always)]
+    pub fn set_uarten(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[doc = "SIR enable: 0 = IrDA SIR ENDEC is disabled. nSIROUT remains LOW (no light pulse generated), and signal transitions on SIRIN have no effect. 1 = IrDA SIR ENDEC is enabled. Data is transmitted and received on nSIROUT and SIRIN. UARTTXD remains HIGH, in the marking state. Signal transitions on UARTRXD or modem status inputs have no effect. This bit has no effect if the UARTEN bit disables the UART."]
+    #[inline(always)]
+    pub const fn siren(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[doc = "SIR enable: 0 = IrDA SIR ENDEC is disabled. nSIROUT remains LOW (no light pulse generated), and signal transitions on SIRIN have no effect. 1 = IrDA SIR ENDEC is enabled. Data is transmitted and received on nSIROUT and SIRIN. UARTTXD remains HIGH, in the marking state. Signal transitions on UARTRXD or modem status inputs have no effect. This bit has no effect if the UARTEN bit disables the UART."]
+    #[inline(always)]
+    pub fn set_siren(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+    #[doc = "SIR low-power IrDA mode. This bit selects the IrDA encoding mode. If this bit is cleared to 0, low-level bits are transmitted as an active high pulse with a width of 3 / 16th of the bit period. If this bit is set to 1, low-level bits are transmitted with a pulse width that is 3 times the period of the IrLPBaud16 input signal, regardless of the selected bit rate. Setting this bit uses less power, but might reduce transmission distances."]
+    #[inline(always)]
+    pub const fn sirlp(&self) -> bool {
+        let val = (self.0 >> 2usize) & 0x01;
+        val != 0
+    }
+    #[doc = "SIR low-power IrDA mode. This bit selects the IrDA encoding mode. If this bit is cleared to 0, low-level bits are transmitted as an active high pulse with a width of 3 / 16th of the bit period. If this bit is set to 1, low-level bits are transmitted with a pulse width that is 3 times the period of the IrLPBaud16 input signal, regardless of the selected bit rate. Setting this bit uses less power, but might reduce transmission distances."]
+    #[inline(always)]
+    pub fn set_sirlp(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+    }
+    #[doc = "Loopback enable. If this bit is set to 1 and the SIREN bit is set to 1 and the SIRTEST bit in the Test Control Register, UARTTCR is set to 1, then the nSIROUT path is inverted, and fed through to the SIRIN path. The SIRTEST bit in the test register must be set to 1 to override the normal half-duplex SIR operation. This must be the requirement for accessing the test registers during normal operation, and SIRTEST must be cleared to 0 when loopback testing is finished. This feature reduces the amount of external coupling required during system test. If this bit is set to 1, and the SIRTEST bit is set to 0, the UARTTXD path is fed through to the UARTRXD path. In either SIR mode or UART mode, when this bit is set, the modem outputs are also fed through to the modem inputs. This bit is cleared to 0 on reset, to disable loopback."]
+    #[inline(always)]
+    pub const fn lbe(&self) -> bool {
+        let val = (self.0 >> 7usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Loopback enable. If this bit is set to 1 and the SIREN bit is set to 1 and the SIRTEST bit in the Test Control Register, UARTTCR is set to 1, then the nSIROUT path is inverted, and fed through to the SIRIN path. The SIRTEST bit in the test register must be set to 1 to override the normal half-duplex SIR operation. This must be the requirement for accessing the test registers during normal operation, and SIRTEST must be cleared to 0 when loopback testing is finished. This feature reduces the amount of external coupling required during system test. If this bit is set to 1, and the SIRTEST bit is set to 0, the UARTTXD path is fed through to the UARTRXD path. In either SIR mode or UART mode, when this bit is set, the modem outputs are also fed through to the modem inputs. This bit is cleared to 0 on reset, to disable loopback."]
+    #[inline(always)]
+    pub fn set_lbe(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
+    }
+    #[doc = "Transmit enable. If this bit is set to 1, the transmit section of the UART is enabled. Data transmission occurs for either UART signals, or SIR signals depending on the setting of the SIREN bit. When the UART is disabled in the middle of transmission, it completes the current character before stopping."]
+    #[inline(always)]
+    pub const fn txe(&self) -> bool {
+        let val = (self.0 >> 8usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Transmit enable. If this bit is set to 1, the transmit section of the UART is enabled. Data transmission occurs for either UART signals, or SIR signals depending on the setting of the SIREN bit. When the UART is disabled in the middle of transmission, it completes the current character before stopping."]
+    #[inline(always)]
+    pub fn set_txe(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
+    }
+    #[doc = "Receive enable. If this bit is set to 1, the receive section of the UART is enabled. Data reception occurs for either UART signals or SIR signals depending on the setting of the SIREN bit. When the UART is disabled in the middle of reception, it completes the current character before stopping."]
+    #[inline(always)]
+    pub const fn rxe(&self) -> bool {
+        let val = (self.0 >> 9usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Receive enable. If this bit is set to 1, the receive section of the UART is enabled. Data reception occurs for either UART signals or SIR signals depending on the setting of the SIREN bit. When the UART is disabled in the middle of reception, it completes the current character before stopping."]
+    #[inline(always)]
+    pub fn set_rxe(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
+    }
+    #[doc = "Data transmit ready. This bit is the complement of the UART data transmit ready, nUARTDTR, modem status output. That is, when the bit is programmed to a 1 then nUARTDTR is LOW."]
+    #[inline(always)]
+    pub const fn dtr(&self) -> bool {
+        let val = (self.0 >> 10usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Data transmit ready. This bit is the complement of the UART data transmit ready, nUARTDTR, modem status output. That is, when the bit is programmed to a 1 then nUARTDTR is LOW."]
+    #[inline(always)]
+    pub fn set_dtr(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize);
+    }
+    #[doc = "Request to send. This bit is the complement of the UART request to send, nUARTRTS, modem status output. That is, when the bit is programmed to a 1 then nUARTRTS is LOW."]
+    #[inline(always)]
+    pub const fn rts(&self) -> bool {
+        let val = (self.0 >> 11usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Request to send. This bit is the complement of the UART request to send, nUARTRTS, modem status output. That is, when the bit is programmed to a 1 then nUARTRTS is LOW."]
+    #[inline(always)]
+    pub fn set_rts(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
+    }
+    #[doc = "This bit is the complement of the UART Out1 (nUARTOut1) modem status output. That is, when the bit is programmed to a 1 the output is 0. For DTE this can be used as Data Carrier Detect (DCD)."]
+    #[inline(always)]
+    pub const fn out1(&self) -> bool {
+        let val = (self.0 >> 12usize) & 0x01;
+        val != 0
+    }
+    #[doc = "This bit is the complement of the UART Out1 (nUARTOut1) modem status output. That is, when the bit is programmed to a 1 the output is 0. For DTE this can be used as Data Carrier Detect (DCD)."]
+    #[inline(always)]
+    pub fn set_out1(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
+    }
+    #[doc = "This bit is the complement of the UART Out2 (nUARTOut2) modem status output. That is, when the bit is programmed to a 1, the output is 0. For DTE this can be used as Ring Indicator (RI)."]
+    #[inline(always)]
+    pub const fn out2(&self) -> bool {
+        let val = (self.0 >> 13usize) & 0x01;
+        val != 0
+    }
+    #[doc = "This bit is the complement of the UART Out2 (nUARTOut2) modem status output. That is, when the bit is programmed to a 1, the output is 0. For DTE this can be used as Ring Indicator (RI)."]
+    #[inline(always)]
+    pub fn set_out2(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize);
+    }
+    #[doc = "RTS hardware flow control enable. If this bit is set to 1, RTS hardware flow control is enabled. Data is only requested when there is space in the receive FIFO for it to be received."]
+    #[inline(always)]
+    pub const fn rtsen(&self) -> bool {
+        let val = (self.0 >> 14usize) & 0x01;
+        val != 0
+    }
+    #[doc = "RTS hardware flow control enable. If this bit is set to 1, RTS hardware flow control is enabled. Data is only requested when there is space in the receive FIFO for it to be received."]
+    #[inline(always)]
+    pub fn set_rtsen(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize);
+    }
+    #[doc = "CTS hardware flow control enable. If this bit is set to 1, CTS hardware flow control is enabled. Data is only transmitted when the nUARTCTS signal is asserted."]
+    #[inline(always)]
+    pub const fn ctsen(&self) -> bool {
+        let val = (self.0 >> 15usize) & 0x01;
+        val != 0
+    }
+    #[doc = "CTS hardware flow control enable. If this bit is set to 1, CTS hardware flow control is enabled. Data is only transmitted when the nUARTCTS signal is asserted."]
+    #[inline(always)]
+    pub fn set_ctsen(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize);
+    }
+}
+impl Default for Uartcr {
+    #[inline(always)]
+    fn default() -> Uartcr {
+        Uartcr(0)
+    }
+}
+#[doc = "DMA Control Register, UARTDMACR"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Uartdmacr(pub u32);
+impl Uartdmacr {
+    #[doc = "Receive DMA enable. If this bit is set to 1, DMA for the receive FIFO is enabled."]
+    #[inline(always)]
+    pub const fn rxdmae(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Receive DMA enable. If this bit is set to 1, DMA for the receive FIFO is enabled."]
+    #[inline(always)]
+    pub fn set_rxdmae(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[doc = "Transmit DMA enable. If this bit is set to 1, DMA for the transmit FIFO is enabled."]
+    #[inline(always)]
+    pub const fn txdmae(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Transmit DMA enable. If this bit is set to 1, DMA for the transmit FIFO is enabled."]
+    #[inline(always)]
+    pub fn set_txdmae(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+    #[doc = "DMA on error. If this bit is set to 1, the DMA receive request outputs, UARTRXDMASREQ or UARTRXDMABREQ, are disabled when the UART error interrupt is asserted."]
+    #[inline(always)]
+    pub const fn dmaonerr(&self) -> bool {
+        let val = (self.0 >> 2usize) & 0x01;
+        val != 0
+    }
+    #[doc = "DMA on error. If this bit is set to 1, the DMA receive request outputs, UARTRXDMASREQ or UARTRXDMABREQ, are disabled when the UART error interrupt is asserted."]
+    #[inline(always)]
+    pub fn set_dmaonerr(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+    }
+}
+impl Default for Uartdmacr {
+    #[inline(always)]
+    fn default() -> Uartdmacr {
+        Uartdmacr(0)
+    }
+}
+#[doc = "Data Register, UARTDR"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Uartdr(pub u32);
+impl Uartdr {
+    #[doc = "Receive (read) data character. Transmit (write) data character."]
+    #[inline(always)]
+    pub const fn data(&self) -> u8 {
+        let val = (self.0 >> 0usize) & 0xff;
+        val as u8
+    }
+    #[doc = "Receive (read) data character. Transmit (write) data character."]
+    #[inline(always)]
+    pub fn set_data(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize);
+    }
+    #[doc = "Framing error. When set to 1, it indicates that the received character did not have a valid stop bit (a valid stop bit is 1). In FIFO mode, this error is associated with the character at the top of the FIFO."]
+    #[inline(always)]
+    pub const fn fe(&self) -> bool {
+        let val = (self.0 >> 8usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Framing error. When set to 1, it indicates that the received character did not have a valid stop bit (a valid stop bit is 1). In FIFO mode, this error is associated with the character at the top of the FIFO."]
+    #[inline(always)]
+    pub fn set_fe(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
+    }
+    #[doc = "Parity error. When set to 1, it indicates that the parity of the received data character does not match the parity that the EPS and SPS bits in the Line Control Register, UARTLCR_H. In FIFO mode, this error is associated with the character at the top of the FIFO."]
+    #[inline(always)]
+    pub const fn pe(&self) -> bool {
+        let val = (self.0 >> 9usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Parity error. When set to 1, it indicates that the parity of the received data character does not match the parity that the EPS and SPS bits in the Line Control Register, UARTLCR_H. In FIFO mode, this error is associated with the character at the top of the FIFO."]
+    #[inline(always)]
+    pub fn set_pe(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
+    }
+    #[doc = "Break error. This bit is set to 1 if a break condition was detected, indicating that the received data input was held LOW for longer than a full-word transmission time (defined as start, data, parity and stop bits). In FIFO mode, this error is associated with the character at the top of the FIFO. When a break occurs, only one 0 character is loaded into the FIFO. The next character is only enabled after the receive data input goes to a 1 (marking state), and the next valid start bit is received."]
+    #[inline(always)]
+    pub const fn be(&self) -> bool {
+        let val = (self.0 >> 10usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Break error. This bit is set to 1 if a break condition was detected, indicating that the received data input was held LOW for longer than a full-word transmission time (defined as start, data, parity and stop bits). In FIFO mode, this error is associated with the character at the top of the FIFO. When a break occurs, only one 0 character is loaded into the FIFO. The next character is only enabled after the receive data input goes to a 1 (marking state), and the next valid start bit is received."]
+    #[inline(always)]
+    pub fn set_be(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize);
+    }
+    #[doc = "Overrun error. This bit is set to 1 if data is received and the receive FIFO is already full. This is cleared to 0 once there is an empty space in the FIFO and a new character can be written to it."]
+    #[inline(always)]
+    pub const fn oe(&self) -> bool {
+        let val = (self.0 >> 11usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Overrun error. This bit is set to 1 if data is received and the receive FIFO is already full. This is cleared to 0 once there is an empty space in the FIFO and a new character can be written to it."]
+    #[inline(always)]
+    pub fn set_oe(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
+    }
+}
+impl Default for Uartdr {
+    #[inline(always)]
+    fn default() -> Uartdr {
+        Uartdr(0)
+    }
+}
+#[doc = "Fractional Baud Rate Register, UARTFBRD"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Uartfbrd(pub u32);
+impl Uartfbrd {
+    #[doc = "The fractional baud rate divisor. These bits are cleared to 0 on reset."]
+    #[inline(always)]
+    pub const fn baud_divfrac(&self) -> u8 {
+        let val = (self.0 >> 0usize) & 0x3f;
+        val as u8
+    }
+    #[doc = "The fractional baud rate divisor. These bits are cleared to 0 on reset."]
+    #[inline(always)]
+    pub fn set_baud_divfrac(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x3f << 0usize)) | (((val as u32) & 0x3f) << 0usize);
+    }
+}
+impl Default for Uartfbrd {
+    #[inline(always)]
+    fn default() -> Uartfbrd {
+        Uartfbrd(0)
+    }
+}
+#[doc = "Flag Register, UARTFR"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Uartfr(pub u32);
+impl Uartfr {
+    #[doc = "Clear to send. This bit is the complement of the UART clear to send, nUARTCTS, modem status input. That is, the bit is 1 when nUARTCTS is LOW."]
+    #[inline(always)]
+    pub const fn cts(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Clear to send. This bit is the complement of the UART clear to send, nUARTCTS, modem status input. That is, the bit is 1 when nUARTCTS is LOW."]
+    #[inline(always)]
+    pub fn set_cts(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[doc = "Data set ready. This bit is the complement of the UART data set ready, nUARTDSR, modem status input. That is, the bit is 1 when nUARTDSR is LOW."]
+    #[inline(always)]
+    pub const fn dsr(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Data set ready. This bit is the complement of the UART data set ready, nUARTDSR, modem status input. That is, the bit is 1 when nUARTDSR is LOW."]
+    #[inline(always)]
+    pub fn set_dsr(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+    #[doc = "Data carrier detect. This bit is the complement of the UART data carrier detect, nUARTDCD, modem status input. That is, the bit is 1 when nUARTDCD is LOW."]
+    #[inline(always)]
+    pub const fn dcd(&self) -> bool {
+        let val = (self.0 >> 2usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Data carrier detect. This bit is the complement of the UART data carrier detect, nUARTDCD, modem status input. That is, the bit is 1 when nUARTDCD is LOW."]
+    #[inline(always)]
+    pub fn set_dcd(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+    }
+    #[doc = "UART busy. If this bit is set to 1, the UART is busy transmitting data. This bit remains set until the complete byte, including all the stop bits, has been sent from the shift register. This bit is set as soon as the transmit FIFO becomes non-empty, regardless of whether the UART is enabled or not."]
+    #[inline(always)]
+    pub const fn busy(&self) -> bool {
+        let val = (self.0 >> 3usize) & 0x01;
+        val != 0
+    }
+    #[doc = "UART busy. If this bit is set to 1, the UART is busy transmitting data. This bit remains set until the complete byte, including all the stop bits, has been sent from the shift register. This bit is set as soon as the transmit FIFO becomes non-empty, regardless of whether the UART is enabled or not."]
+    #[inline(always)]
+    pub fn set_busy(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
+    }
+    #[doc = "Receive FIFO empty. The meaning of this bit depends on the state of the FEN bit in the UARTLCR_H Register. If the FIFO is disabled, this bit is set when the receive holding register is empty. If the FIFO is enabled, the RXFE bit is set when the receive FIFO is empty."]
+    #[inline(always)]
+    pub const fn rxfe(&self) -> bool {
+        let val = (self.0 >> 4usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Receive FIFO empty. The meaning of this bit depends on the state of the FEN bit in the UARTLCR_H Register. If the FIFO is disabled, this bit is set when the receive holding register is empty. If the FIFO is enabled, the RXFE bit is set when the receive FIFO is empty."]
+    #[inline(always)]
+    pub fn set_rxfe(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
+    }
+    #[doc = "Transmit FIFO full. The meaning of this bit depends on the state of the FEN bit in the UARTLCR_H Register. If the FIFO is disabled, this bit is set when the transmit holding register is full. If the FIFO is enabled, the TXFF bit is set when the transmit FIFO is full."]
+    #[inline(always)]
+    pub const fn txff(&self) -> bool {
+        let val = (self.0 >> 5usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Transmit FIFO full. The meaning of this bit depends on the state of the FEN bit in the UARTLCR_H Register. If the FIFO is disabled, this bit is set when the transmit holding register is full. If the FIFO is enabled, the TXFF bit is set when the transmit FIFO is full."]
+    #[inline(always)]
+    pub fn set_txff(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
+    }
+    #[doc = "Receive FIFO full. The meaning of this bit depends on the state of the FEN bit in the UARTLCR_H Register. If the FIFO is disabled, this bit is set when the receive holding register is full. If the FIFO is enabled, the RXFF bit is set when the receive FIFO is full."]
+    #[inline(always)]
+    pub const fn rxff(&self) -> bool {
+        let val = (self.0 >> 6usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Receive FIFO full. The meaning of this bit depends on the state of the FEN bit in the UARTLCR_H Register. If the FIFO is disabled, this bit is set when the receive holding register is full. If the FIFO is enabled, the RXFF bit is set when the receive FIFO is full."]
+    #[inline(always)]
+    pub fn set_rxff(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
+    }
+    #[doc = "Transmit FIFO empty. The meaning of this bit depends on the state of the FEN bit in the Line Control Register, UARTLCR_H. If the FIFO is disabled, this bit is set when the transmit holding register is empty. If the FIFO is enabled, the TXFE bit is set when the transmit FIFO is empty. This bit does not indicate if there is data in the transmit shift register."]
+    #[inline(always)]
+    pub const fn txfe(&self) -> bool {
+        let val = (self.0 >> 7usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Transmit FIFO empty. The meaning of this bit depends on the state of the FEN bit in the Line Control Register, UARTLCR_H. If the FIFO is disabled, this bit is set when the transmit holding register is empty. If the FIFO is enabled, the TXFE bit is set when the transmit FIFO is empty. This bit does not indicate if there is data in the transmit shift register."]
+    #[inline(always)]
+    pub fn set_txfe(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
+    }
+    #[doc = "Ring indicator. This bit is the complement of the UART ring indicator, nUARTRI, modem status input. That is, the bit is 1 when nUARTRI is LOW."]
+    #[inline(always)]
+    pub const fn ri(&self) -> bool {
+        let val = (self.0 >> 8usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Ring indicator. This bit is the complement of the UART ring indicator, nUARTRI, modem status input. That is, the bit is 1 when nUARTRI is LOW."]
+    #[inline(always)]
+    pub fn set_ri(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
+    }
+}
+impl Default for Uartfr {
+    #[inline(always)]
+    fn default() -> Uartfr {
+        Uartfr(0)
+    }
+}
+#[doc = "Integer Baud Rate Register, UARTIBRD"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Uartibrd(pub u32);
+impl Uartibrd {
+    #[doc = "The integer baud rate divisor. These bits are cleared to 0 on reset."]
+    #[inline(always)]
+    pub const fn baud_divint(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0xffff;
+        val as u16
+    }
+    #[doc = "The integer baud rate divisor. These bits are cleared to 0 on reset."]
+    #[inline(always)]
+    pub fn set_baud_divint(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+    }
+}
+impl Default for Uartibrd {
+    #[inline(always)]
+    fn default() -> Uartibrd {
+        Uartibrd(0)
+    }
+}
+#[doc = "Interrupt Clear Register, UARTICR"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Uarticr(pub u32);
+impl Uarticr {
+    #[doc = "nUARTRI modem interrupt clear. Clears the UARTRIINTR interrupt."]
+    #[inline(always)]
+    pub const fn rimic(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "nUARTRI modem interrupt clear. Clears the UARTRIINTR interrupt."]
+    #[inline(always)]
+    pub fn set_rimic(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[doc = "nUARTCTS modem interrupt clear. Clears the UARTCTSINTR interrupt."]
+    #[inline(always)]
+    pub const fn ctsmic(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[doc = "nUARTCTS modem interrupt clear. Clears the UARTCTSINTR interrupt."]
+    #[inline(always)]
+    pub fn set_ctsmic(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+    #[doc = "nUARTDCD modem interrupt clear. Clears the UARTDCDINTR interrupt."]
+    #[inline(always)]
+    pub const fn dcdmic(&self) -> bool {
+        let val = (self.0 >> 2usize) & 0x01;
+        val != 0
+    }
+    #[doc = "nUARTDCD modem interrupt clear. Clears the UARTDCDINTR interrupt."]
+    #[inline(always)]
+    pub fn set_dcdmic(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+    }
+    #[doc = "nUARTDSR modem interrupt clear. Clears the UARTDSRINTR interrupt."]
+    #[inline(always)]
+    pub const fn dsrmic(&self) -> bool {
+        let val = (self.0 >> 3usize) & 0x01;
+        val != 0
+    }
+    #[doc = "nUARTDSR modem interrupt clear. Clears the UARTDSRINTR interrupt."]
+    #[inline(always)]
+    pub fn set_dsrmic(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
+    }
+    #[doc = "Receive interrupt clear. Clears the UARTRXINTR interrupt."]
+    #[inline(always)]
+    pub const fn rxic(&self) -> bool {
+        let val = (self.0 >> 4usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Receive interrupt clear. Clears the UARTRXINTR interrupt."]
+    #[inline(always)]
+    pub fn set_rxic(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
+    }
+    #[doc = "Transmit interrupt clear. Clears the UARTTXINTR interrupt."]
+    #[inline(always)]
+    pub const fn txic(&self) -> bool {
+        let val = (self.0 >> 5usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Transmit interrupt clear. Clears the UARTTXINTR interrupt."]
+    #[inline(always)]
+    pub fn set_txic(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
+    }
+    #[doc = "Receive timeout interrupt clear. Clears the UARTRTINTR interrupt."]
+    #[inline(always)]
+    pub const fn rtic(&self) -> bool {
+        let val = (self.0 >> 6usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Receive timeout interrupt clear. Clears the UARTRTINTR interrupt."]
+    #[inline(always)]
+    pub fn set_rtic(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
+    }
+    #[doc = "Framing error interrupt clear. Clears the UARTFEINTR interrupt."]
+    #[inline(always)]
+    pub const fn feic(&self) -> bool {
+        let val = (self.0 >> 7usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Framing error interrupt clear. Clears the UARTFEINTR interrupt."]
+    #[inline(always)]
+    pub fn set_feic(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
+    }
+    #[doc = "Parity error interrupt clear. Clears the UARTPEINTR interrupt."]
+    #[inline(always)]
+    pub const fn peic(&self) -> bool {
+        let val = (self.0 >> 8usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Parity error interrupt clear. Clears the UARTPEINTR interrupt."]
+    #[inline(always)]
+    pub fn set_peic(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
+    }
+    #[doc = "Break error interrupt clear. Clears the UARTBEINTR interrupt."]
+    #[inline(always)]
+    pub const fn beic(&self) -> bool {
+        let val = (self.0 >> 9usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Break error interrupt clear. Clears the UARTBEINTR interrupt."]
+    #[inline(always)]
+    pub fn set_beic(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
+    }
+    #[doc = "Overrun error interrupt clear. Clears the UARTOEINTR interrupt."]
+    #[inline(always)]
+    pub const fn oeic(&self) -> bool {
+        let val = (self.0 >> 10usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Overrun error interrupt clear. Clears the UARTOEINTR interrupt."]
+    #[inline(always)]
+    pub fn set_oeic(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize);
+    }
+}
+impl Default for Uarticr {
+    #[inline(always)]
+    fn default() -> Uarticr {
+        Uarticr(0)
+    }
+}
+#[doc = "Interrupt FIFO Level Select Register, UARTIFLS"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Uartifls(pub u32);
+impl Uartifls {
+    #[doc = "Transmit interrupt FIFO level select. The trigger points for the transmit interrupt are as follows: b000 = Transmit FIFO becomes <= 1 / 8 full b001 = Transmit FIFO becomes <= 1 / 4 full b010 = Transmit FIFO becomes <= 1 / 2 full b011 = Transmit FIFO becomes <= 3 / 4 full b100 = Transmit FIFO becomes <= 7 / 8 full b101-b111 = reserved."]
+    #[inline(always)]
+    pub const fn txiflsel(&self) -> u8 {
+        let val = (self.0 >> 0usize) & 0x07;
+        val as u8
+    }
+    #[doc = "Transmit interrupt FIFO level select. The trigger points for the transmit interrupt are as follows: b000 = Transmit FIFO becomes <= 1 / 8 full b001 = Transmit FIFO becomes <= 1 / 4 full b010 = Transmit FIFO becomes <= 1 / 2 full b011 = Transmit FIFO becomes <= 3 / 4 full b100 = Transmit FIFO becomes <= 7 / 8 full b101-b111 = reserved."]
+    #[inline(always)]
+    pub fn set_txiflsel(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x07 << 0usize)) | (((val as u32) & 0x07) << 0usize);
+    }
+    #[doc = "Receive interrupt FIFO level select. The trigger points for the receive interrupt are as follows: b000 = Receive FIFO becomes >= 1 / 8 full b001 = Receive FIFO becomes >= 1 / 4 full b010 = Receive FIFO becomes >= 1 / 2 full b011 = Receive FIFO becomes >= 3 / 4 full b100 = Receive FIFO becomes >= 7 / 8 full b101-b111 = reserved."]
+    #[inline(always)]
+    pub const fn rxiflsel(&self) -> u8 {
+        let val = (self.0 >> 3usize) & 0x07;
+        val as u8
+    }
+    #[doc = "Receive interrupt FIFO level select. The trigger points for the receive interrupt are as follows: b000 = Receive FIFO becomes >= 1 / 8 full b001 = Receive FIFO becomes >= 1 / 4 full b010 = Receive FIFO becomes >= 1 / 2 full b011 = Receive FIFO becomes >= 3 / 4 full b100 = Receive FIFO becomes >= 7 / 8 full b101-b111 = reserved."]
+    #[inline(always)]
+    pub fn set_rxiflsel(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x07 << 3usize)) | (((val as u32) & 0x07) << 3usize);
+    }
+}
+impl Default for Uartifls {
+    #[inline(always)]
+    fn default() -> Uartifls {
+        Uartifls(0)
+    }
+}
+#[doc = "IrDA Low-Power Counter Register, UARTILPR"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Uartilpr(pub u32);
+impl Uartilpr {
+    #[doc = "8-bit low-power divisor value. These bits are cleared to 0 at reset."]
+    #[inline(always)]
+    pub const fn ilpdvsr(&self) -> u8 {
+        let val = (self.0 >> 0usize) & 0xff;
+        val as u8
+    }
+    #[doc = "8-bit low-power divisor value. These bits are cleared to 0 at reset."]
+    #[inline(always)]
+    pub fn set_ilpdvsr(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize);
+    }
+}
+impl Default for Uartilpr {
+    #[inline(always)]
+    fn default() -> Uartilpr {
+        Uartilpr(0)
+    }
+}
+#[doc = "Interrupt Mask Set/Clear Register, UARTIMSC"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Uartimsc(pub u32);
+impl Uartimsc {
+    #[doc = "nUARTRI modem interrupt mask. A read returns the current mask for the UARTRIINTR interrupt. On a write of 1, the mask of the UARTRIINTR interrupt is set. A write of 0 clears the mask."]
+    #[inline(always)]
+    pub const fn rimim(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "nUARTRI modem interrupt mask. A read returns the current mask for the UARTRIINTR interrupt. On a write of 1, the mask of the UARTRIINTR interrupt is set. A write of 0 clears the mask."]
+    #[inline(always)]
+    pub fn set_rimim(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[doc = "nUARTCTS modem interrupt mask. A read returns the current mask for the UARTCTSINTR interrupt. On a write of 1, the mask of the UARTCTSINTR interrupt is set. A write of 0 clears the mask."]
+    #[inline(always)]
+    pub const fn ctsmim(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[doc = "nUARTCTS modem interrupt mask. A read returns the current mask for the UARTCTSINTR interrupt. On a write of 1, the mask of the UARTCTSINTR interrupt is set. A write of 0 clears the mask."]
+    #[inline(always)]
+    pub fn set_ctsmim(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+    #[doc = "nUARTDCD modem interrupt mask. A read returns the current mask for the UARTDCDINTR interrupt. On a write of 1, the mask of the UARTDCDINTR interrupt is set. A write of 0 clears the mask."]
+    #[inline(always)]
+    pub const fn dcdmim(&self) -> bool {
+        let val = (self.0 >> 2usize) & 0x01;
+        val != 0
+    }
+    #[doc = "nUARTDCD modem interrupt mask. A read returns the current mask for the UARTDCDINTR interrupt. On a write of 1, the mask of the UARTDCDINTR interrupt is set. A write of 0 clears the mask."]
+    #[inline(always)]
+    pub fn set_dcdmim(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+    }
+    #[doc = "nUARTDSR modem interrupt mask. A read returns the current mask for the UARTDSRINTR interrupt. On a write of 1, the mask of the UARTDSRINTR interrupt is set. A write of 0 clears the mask."]
+    #[inline(always)]
+    pub const fn dsrmim(&self) -> bool {
+        let val = (self.0 >> 3usize) & 0x01;
+        val != 0
+    }
+    #[doc = "nUARTDSR modem interrupt mask. A read returns the current mask for the UARTDSRINTR interrupt. On a write of 1, the mask of the UARTDSRINTR interrupt is set. A write of 0 clears the mask."]
+    #[inline(always)]
+    pub fn set_dsrmim(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
+    }
+    #[doc = "Receive interrupt mask. A read returns the current mask for the UARTRXINTR interrupt. On a write of 1, the mask of the UARTRXINTR interrupt is set. A write of 0 clears the mask."]
+    #[inline(always)]
+    pub const fn rxim(&self) -> bool {
+        let val = (self.0 >> 4usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Receive interrupt mask. A read returns the current mask for the UARTRXINTR interrupt. On a write of 1, the mask of the UARTRXINTR interrupt is set. A write of 0 clears the mask."]
+    #[inline(always)]
+    pub fn set_rxim(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
+    }
+    #[doc = "Transmit interrupt mask. A read returns the current mask for the UARTTXINTR interrupt. On a write of 1, the mask of the UARTTXINTR interrupt is set. A write of 0 clears the mask."]
+    #[inline(always)]
+    pub const fn txim(&self) -> bool {
+        let val = (self.0 >> 5usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Transmit interrupt mask. A read returns the current mask for the UARTTXINTR interrupt. On a write of 1, the mask of the UARTTXINTR interrupt is set. A write of 0 clears the mask."]
+    #[inline(always)]
+    pub fn set_txim(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
+    }
+    #[doc = "Receive timeout interrupt mask. A read returns the current mask for the UARTRTINTR interrupt. On a write of 1, the mask of the UARTRTINTR interrupt is set. A write of 0 clears the mask."]
+    #[inline(always)]
+    pub const fn rtim(&self) -> bool {
+        let val = (self.0 >> 6usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Receive timeout interrupt mask. A read returns the current mask for the UARTRTINTR interrupt. On a write of 1, the mask of the UARTRTINTR interrupt is set. A write of 0 clears the mask."]
+    #[inline(always)]
+    pub fn set_rtim(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
+    }
+    #[doc = "Framing error interrupt mask. A read returns the current mask for the UARTFEINTR interrupt. On a write of 1, the mask of the UARTFEINTR interrupt is set. A write of 0 clears the mask."]
+    #[inline(always)]
+    pub const fn feim(&self) -> bool {
+        let val = (self.0 >> 7usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Framing error interrupt mask. A read returns the current mask for the UARTFEINTR interrupt. On a write of 1, the mask of the UARTFEINTR interrupt is set. A write of 0 clears the mask."]
+    #[inline(always)]
+    pub fn set_feim(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
+    }
+    #[doc = "Parity error interrupt mask. A read returns the current mask for the UARTPEINTR interrupt. On a write of 1, the mask of the UARTPEINTR interrupt is set. A write of 0 clears the mask."]
+    #[inline(always)]
+    pub const fn peim(&self) -> bool {
+        let val = (self.0 >> 8usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Parity error interrupt mask. A read returns the current mask for the UARTPEINTR interrupt. On a write of 1, the mask of the UARTPEINTR interrupt is set. A write of 0 clears the mask."]
+    #[inline(always)]
+    pub fn set_peim(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
+    }
+    #[doc = "Break error interrupt mask. A read returns the current mask for the UARTBEINTR interrupt. On a write of 1, the mask of the UARTBEINTR interrupt is set. A write of 0 clears the mask."]
+    #[inline(always)]
+    pub const fn beim(&self) -> bool {
+        let val = (self.0 >> 9usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Break error interrupt mask. A read returns the current mask for the UARTBEINTR interrupt. On a write of 1, the mask of the UARTBEINTR interrupt is set. A write of 0 clears the mask."]
+    #[inline(always)]
+    pub fn set_beim(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
+    }
+    #[doc = "Overrun error interrupt mask. A read returns the current mask for the UARTOEINTR interrupt. On a write of 1, the mask of the UARTOEINTR interrupt is set. A write of 0 clears the mask."]
+    #[inline(always)]
+    pub const fn oeim(&self) -> bool {
+        let val = (self.0 >> 10usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Overrun error interrupt mask. A read returns the current mask for the UARTOEINTR interrupt. On a write of 1, the mask of the UARTOEINTR interrupt is set. A write of 0 clears the mask."]
+    #[inline(always)]
+    pub fn set_oeim(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize);
+    }
+}
+impl Default for Uartimsc {
+    #[inline(always)]
+    fn default() -> Uartimsc {
+        Uartimsc(0)
+    }
+}
+#[doc = "Line Control Register, UARTLCR_H"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct UartlcrH(pub u32);
+impl UartlcrH {
+    #[doc = "Send break. If this bit is set to 1, a low-level is continually output on the UARTTXD output, after completing transmission of the current character. For the proper execution of the break command, the software must set this bit for at least two complete frames. For normal use, this bit must be cleared to 0."]
+    #[inline(always)]
+    pub const fn brk(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Send break. If this bit is set to 1, a low-level is continually output on the UARTTXD output, after completing transmission of the current character. For the proper execution of the break command, the software must set this bit for at least two complete frames. For normal use, this bit must be cleared to 0."]
+    #[inline(always)]
+    pub fn set_brk(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[doc = "Parity enable: 0 = parity is disabled and no parity bit added to the data frame 1 = parity checking and generation is enabled."]
+    #[inline(always)]
+    pub const fn pen(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Parity enable: 0 = parity is disabled and no parity bit added to the data frame 1 = parity checking and generation is enabled."]
+    #[inline(always)]
+    pub fn set_pen(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+    #[doc = "Even parity select. Controls the type of parity the UART uses during transmission and reception: 0 = odd parity. The UART generates or checks for an odd number of 1s in the data and parity bits. 1 = even parity. The UART generates or checks for an even number of 1s in the data and parity bits. This bit has no effect when the PEN bit disables parity checking and generation."]
+    #[inline(always)]
+    pub const fn eps(&self) -> bool {
+        let val = (self.0 >> 2usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Even parity select. Controls the type of parity the UART uses during transmission and reception: 0 = odd parity. The UART generates or checks for an odd number of 1s in the data and parity bits. 1 = even parity. The UART generates or checks for an even number of 1s in the data and parity bits. This bit has no effect when the PEN bit disables parity checking and generation."]
+    #[inline(always)]
+    pub fn set_eps(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+    }
+    #[doc = "Two stop bits select. If this bit is set to 1, two stop bits are transmitted at the end of the frame. The receive logic does not check for two stop bits being received."]
+    #[inline(always)]
+    pub const fn stp2(&self) -> bool {
+        let val = (self.0 >> 3usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Two stop bits select. If this bit is set to 1, two stop bits are transmitted at the end of the frame. The receive logic does not check for two stop bits being received."]
+    #[inline(always)]
+    pub fn set_stp2(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
+    }
+    #[doc = "Enable FIFOs: 0 = FIFOs are disabled (character mode) that is, the FIFOs become 1-byte-deep holding registers 1 = transmit and receive FIFO buffers are enabled (FIFO mode)."]
+    #[inline(always)]
+    pub const fn fen(&self) -> bool {
+        let val = (self.0 >> 4usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Enable FIFOs: 0 = FIFOs are disabled (character mode) that is, the FIFOs become 1-byte-deep holding registers 1 = transmit and receive FIFO buffers are enabled (FIFO mode)."]
+    #[inline(always)]
+    pub fn set_fen(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
+    }
+    #[doc = "Word length. These bits indicate the number of data bits transmitted or received in a frame as follows: b11 = 8 bits b10 = 7 bits b01 = 6 bits b00 = 5 bits."]
+    #[inline(always)]
+    pub const fn wlen(&self) -> u8 {
+        let val = (self.0 >> 5usize) & 0x03;
+        val as u8
+    }
+    #[doc = "Word length. These bits indicate the number of data bits transmitted or received in a frame as follows: b11 = 8 bits b10 = 7 bits b01 = 6 bits b00 = 5 bits."]
+    #[inline(always)]
+    pub fn set_wlen(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x03 << 5usize)) | (((val as u32) & 0x03) << 5usize);
+    }
+    #[doc = "Stick parity select. 0 = stick parity is disabled 1 = either: * if the EPS bit is 0 then the parity bit is transmitted and checked as a 1 * if the EPS bit is 1 then the parity bit is transmitted and checked as a 0. This bit has no effect when the PEN bit disables parity checking and generation."]
+    #[inline(always)]
+    pub const fn sps(&self) -> bool {
+        let val = (self.0 >> 7usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Stick parity select. 0 = stick parity is disabled 1 = either: * if the EPS bit is 0 then the parity bit is transmitted and checked as a 1 * if the EPS bit is 1 then the parity bit is transmitted and checked as a 0. This bit has no effect when the PEN bit disables parity checking and generation."]
+    #[inline(always)]
+    pub fn set_sps(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
+    }
+}
+impl Default for UartlcrH {
+    #[inline(always)]
+    fn default() -> UartlcrH {
+        UartlcrH(0)
+    }
+}
+#[doc = "Masked Interrupt Status Register, UARTMIS"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Uartmis(pub u32);
+impl Uartmis {
+    #[doc = "nUARTRI modem masked interrupt status. Returns the masked interrupt state of the UARTRIINTR interrupt."]
+    #[inline(always)]
+    pub const fn rimmis(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "nUARTRI modem masked interrupt status. Returns the masked interrupt state of the UARTRIINTR interrupt."]
+    #[inline(always)]
+    pub fn set_rimmis(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[doc = "nUARTCTS modem masked interrupt status. Returns the masked interrupt state of the UARTCTSINTR interrupt."]
+    #[inline(always)]
+    pub const fn ctsmmis(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[doc = "nUARTCTS modem masked interrupt status. Returns the masked interrupt state of the UARTCTSINTR interrupt."]
+    #[inline(always)]
+    pub fn set_ctsmmis(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+    #[doc = "nUARTDCD modem masked interrupt status. Returns the masked interrupt state of the UARTDCDINTR interrupt."]
+    #[inline(always)]
+    pub const fn dcdmmis(&self) -> bool {
+        let val = (self.0 >> 2usize) & 0x01;
+        val != 0
+    }
+    #[doc = "nUARTDCD modem masked interrupt status. Returns the masked interrupt state of the UARTDCDINTR interrupt."]
+    #[inline(always)]
+    pub fn set_dcdmmis(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+    }
+    #[doc = "nUARTDSR modem masked interrupt status. Returns the masked interrupt state of the UARTDSRINTR interrupt."]
+    #[inline(always)]
+    pub const fn dsrmmis(&self) -> bool {
+        let val = (self.0 >> 3usize) & 0x01;
+        val != 0
+    }
+    #[doc = "nUARTDSR modem masked interrupt status. Returns the masked interrupt state of the UARTDSRINTR interrupt."]
+    #[inline(always)]
+    pub fn set_dsrmmis(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
+    }
+    #[doc = "Receive masked interrupt status. Returns the masked interrupt state of the UARTRXINTR interrupt."]
+    #[inline(always)]
+    pub const fn rxmis(&self) -> bool {
+        let val = (self.0 >> 4usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Receive masked interrupt status. Returns the masked interrupt state of the UARTRXINTR interrupt."]
+    #[inline(always)]
+    pub fn set_rxmis(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
+    }
+    #[doc = "Transmit masked interrupt status. Returns the masked interrupt state of the UARTTXINTR interrupt."]
+    #[inline(always)]
+    pub const fn txmis(&self) -> bool {
+        let val = (self.0 >> 5usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Transmit masked interrupt status. Returns the masked interrupt state of the UARTTXINTR interrupt."]
+    #[inline(always)]
+    pub fn set_txmis(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
+    }
+    #[doc = "Receive timeout masked interrupt status. Returns the masked interrupt state of the UARTRTINTR interrupt."]
+    #[inline(always)]
+    pub const fn rtmis(&self) -> bool {
+        let val = (self.0 >> 6usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Receive timeout masked interrupt status. Returns the masked interrupt state of the UARTRTINTR interrupt."]
+    #[inline(always)]
+    pub fn set_rtmis(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
+    }
+    #[doc = "Framing error masked interrupt status. Returns the masked interrupt state of the UARTFEINTR interrupt."]
+    #[inline(always)]
+    pub const fn femis(&self) -> bool {
+        let val = (self.0 >> 7usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Framing error masked interrupt status. Returns the masked interrupt state of the UARTFEINTR interrupt."]
+    #[inline(always)]
+    pub fn set_femis(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
+    }
+    #[doc = "Parity error masked interrupt status. Returns the masked interrupt state of the UARTPEINTR interrupt."]
+    #[inline(always)]
+    pub const fn pemis(&self) -> bool {
+        let val = (self.0 >> 8usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Parity error masked interrupt status. Returns the masked interrupt state of the UARTPEINTR interrupt."]
+    #[inline(always)]
+    pub fn set_pemis(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
+    }
+    #[doc = "Break error masked interrupt status. Returns the masked interrupt state of the UARTBEINTR interrupt."]
+    #[inline(always)]
+    pub const fn bemis(&self) -> bool {
+        let val = (self.0 >> 9usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Break error masked interrupt status. Returns the masked interrupt state of the UARTBEINTR interrupt."]
+    #[inline(always)]
+    pub fn set_bemis(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
+    }
+    #[doc = "Overrun error masked interrupt status. Returns the masked interrupt state of the UARTOEINTR interrupt."]
+    #[inline(always)]
+    pub const fn oemis(&self) -> bool {
+        let val = (self.0 >> 10usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Overrun error masked interrupt status. Returns the masked interrupt state of the UARTOEINTR interrupt."]
+    #[inline(always)]
+    pub fn set_oemis(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize);
+    }
+}
+impl Default for Uartmis {
+    #[inline(always)]
+    fn default() -> Uartmis {
+        Uartmis(0)
+    }
+}
+#[doc = "UARTPCellID0 Register"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Uartpcellid0(pub u32);
+impl Uartpcellid0 {
+    #[doc = "These bits read back as 0x0D"]
+    #[inline(always)]
+    pub const fn uartpcellid0(&self) -> u8 {
+        let val = (self.0 >> 0usize) & 0xff;
+        val as u8
+    }
+    #[doc = "These bits read back as 0x0D"]
+    #[inline(always)]
+    pub fn set_uartpcellid0(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize);
+    }
+}
+impl Default for Uartpcellid0 {
+    #[inline(always)]
+    fn default() -> Uartpcellid0 {
+        Uartpcellid0(0)
+    }
+}
+#[doc = "UARTPCellID1 Register"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Uartpcellid1(pub u32);
+impl Uartpcellid1 {
+    #[doc = "These bits read back as 0xF0"]
+    #[inline(always)]
+    pub const fn uartpcellid1(&self) -> u8 {
+        let val = (self.0 >> 0usize) & 0xff;
+        val as u8
+    }
+    #[doc = "These bits read back as 0xF0"]
+    #[inline(always)]
+    pub fn set_uartpcellid1(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize);
+    }
+}
+impl Default for Uartpcellid1 {
+    #[inline(always)]
+    fn default() -> Uartpcellid1 {
+        Uartpcellid1(0)
+    }
+}
+#[doc = "UARTPCellID2 Register"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Uartpcellid2(pub u32);
+impl Uartpcellid2 {
+    #[doc = "These bits read back as 0x05"]
+    #[inline(always)]
+    pub const fn uartpcellid2(&self) -> u8 {
+        let val = (self.0 >> 0usize) & 0xff;
+        val as u8
+    }
+    #[doc = "These bits read back as 0x05"]
+    #[inline(always)]
+    pub fn set_uartpcellid2(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize);
+    }
+}
+impl Default for Uartpcellid2 {
+    #[inline(always)]
+    fn default() -> Uartpcellid2 {
+        Uartpcellid2(0)
+    }
+}
+#[doc = "UARTPCellID3 Register"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Uartpcellid3(pub u32);
+impl Uartpcellid3 {
+    #[doc = "These bits read back as 0xB1"]
+    #[inline(always)]
+    pub const fn uartpcellid3(&self) -> u8 {
+        let val = (self.0 >> 0usize) & 0xff;
+        val as u8
+    }
+    #[doc = "These bits read back as 0xB1"]
+    #[inline(always)]
+    pub fn set_uartpcellid3(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize);
+    }
+}
+impl Default for Uartpcellid3 {
+    #[inline(always)]
+    fn default() -> Uartpcellid3 {
+        Uartpcellid3(0)
+    }
+}
+#[doc = "UARTPeriphID0 Register"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Uartperiphid0(pub u32);
+impl Uartperiphid0 {
+    #[doc = "These bits read back as 0x11"]
+    #[inline(always)]
+    pub const fn partnumber0(&self) -> u8 {
+        let val = (self.0 >> 0usize) & 0xff;
+        val as u8
+    }
+    #[doc = "These bits read back as 0x11"]
+    #[inline(always)]
+    pub fn set_partnumber0(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize);
+    }
+}
+impl Default for Uartperiphid0 {
+    #[inline(always)]
+    fn default() -> Uartperiphid0 {
+        Uartperiphid0(0)
+    }
+}
+#[doc = "UARTPeriphID1 Register"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Uartperiphid1(pub u32);
+impl Uartperiphid1 {
+    #[doc = "These bits read back as 0x0"]
+    #[inline(always)]
+    pub const fn partnumber1(&self) -> u8 {
+        let val = (self.0 >> 0usize) & 0x0f;
+        val as u8
+    }
+    #[doc = "These bits read back as 0x0"]
+    #[inline(always)]
+    pub fn set_partnumber1(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize);
+    }
+    #[doc = "These bits read back as 0x1"]
+    #[inline(always)]
+    pub const fn designer0(&self) -> u8 {
+        let val = (self.0 >> 4usize) & 0x0f;
+        val as u8
+    }
+    #[doc = "These bits read back as 0x1"]
+    #[inline(always)]
+    pub fn set_designer0(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x0f << 4usize)) | (((val as u32) & 0x0f) << 4usize);
+    }
+}
+impl Default for Uartperiphid1 {
+    #[inline(always)]
+    fn default() -> Uartperiphid1 {
+        Uartperiphid1(0)
+    }
+}
+#[doc = "UARTPeriphID2 Register"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Uartperiphid2(pub u32);
+impl Uartperiphid2 {
+    #[doc = "These bits read back as 0x4"]
+    #[inline(always)]
+    pub const fn designer1(&self) -> u8 {
+        let val = (self.0 >> 0usize) & 0x0f;
+        val as u8
+    }
+    #[doc = "These bits read back as 0x4"]
+    #[inline(always)]
+    pub fn set_designer1(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize);
+    }
+    #[doc = "This field depends on the revision of the UART: r1p0 0x0 r1p1 0x1 r1p3 0x2 r1p4 0x2 r1p5 0x3"]
+    #[inline(always)]
+    pub const fn revision(&self) -> u8 {
+        let val = (self.0 >> 4usize) & 0x0f;
+        val as u8
+    }
+    #[doc = "This field depends on the revision of the UART: r1p0 0x0 r1p1 0x1 r1p3 0x2 r1p4 0x2 r1p5 0x3"]
+    #[inline(always)]
+    pub fn set_revision(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x0f << 4usize)) | (((val as u32) & 0x0f) << 4usize);
+    }
+}
+impl Default for Uartperiphid2 {
+    #[inline(always)]
+    fn default() -> Uartperiphid2 {
+        Uartperiphid2(0)
+    }
+}
+#[doc = "UARTPeriphID3 Register"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Uartperiphid3(pub u32);
+impl Uartperiphid3 {
+    #[doc = "These bits read back as 0x00"]
+    #[inline(always)]
+    pub const fn configuration(&self) -> u8 {
+        let val = (self.0 >> 0usize) & 0xff;
+        val as u8
+    }
+    #[doc = "These bits read back as 0x00"]
+    #[inline(always)]
+    pub fn set_configuration(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize);
+    }
+}
+impl Default for Uartperiphid3 {
+    #[inline(always)]
+    fn default() -> Uartperiphid3 {
+        Uartperiphid3(0)
+    }
+}
+#[doc = "Raw Interrupt Status Register, UARTRIS"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Uartris(pub u32);
+impl Uartris {
+    #[doc = "nUARTRI modem interrupt status. Returns the raw interrupt state of the UARTRIINTR interrupt."]
+    #[inline(always)]
+    pub const fn rirmis(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "nUARTRI modem interrupt status. Returns the raw interrupt state of the UARTRIINTR interrupt."]
+    #[inline(always)]
+    pub fn set_rirmis(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[doc = "nUARTCTS modem interrupt status. Returns the raw interrupt state of the UARTCTSINTR interrupt."]
+    #[inline(always)]
+    pub const fn ctsrmis(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[doc = "nUARTCTS modem interrupt status. Returns the raw interrupt state of the UARTCTSINTR interrupt."]
+    #[inline(always)]
+    pub fn set_ctsrmis(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+    #[doc = "nUARTDCD modem interrupt status. Returns the raw interrupt state of the UARTDCDINTR interrupt."]
+    #[inline(always)]
+    pub const fn dcdrmis(&self) -> bool {
+        let val = (self.0 >> 2usize) & 0x01;
+        val != 0
+    }
+    #[doc = "nUARTDCD modem interrupt status. Returns the raw interrupt state of the UARTDCDINTR interrupt."]
+    #[inline(always)]
+    pub fn set_dcdrmis(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+    }
+    #[doc = "nUARTDSR modem interrupt status. Returns the raw interrupt state of the UARTDSRINTR interrupt."]
+    #[inline(always)]
+    pub const fn dsrrmis(&self) -> bool {
+        let val = (self.0 >> 3usize) & 0x01;
+        val != 0
+    }
+    #[doc = "nUARTDSR modem interrupt status. Returns the raw interrupt state of the UARTDSRINTR interrupt."]
+    #[inline(always)]
+    pub fn set_dsrrmis(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
+    }
+    #[doc = "Receive interrupt status. Returns the raw interrupt state of the UARTRXINTR interrupt."]
+    #[inline(always)]
+    pub const fn rxris(&self) -> bool {
+        let val = (self.0 >> 4usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Receive interrupt status. Returns the raw interrupt state of the UARTRXINTR interrupt."]
+    #[inline(always)]
+    pub fn set_rxris(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
+    }
+    #[doc = "Transmit interrupt status. Returns the raw interrupt state of the UARTTXINTR interrupt."]
+    #[inline(always)]
+    pub const fn txris(&self) -> bool {
+        let val = (self.0 >> 5usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Transmit interrupt status. Returns the raw interrupt state of the UARTTXINTR interrupt."]
+    #[inline(always)]
+    pub fn set_txris(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
+    }
+    #[doc = "Receive timeout interrupt status. Returns the raw interrupt state of the UARTRTINTR interrupt. a"]
+    #[inline(always)]
+    pub const fn rtris(&self) -> bool {
+        let val = (self.0 >> 6usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Receive timeout interrupt status. Returns the raw interrupt state of the UARTRTINTR interrupt. a"]
+    #[inline(always)]
+    pub fn set_rtris(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
+    }
+    #[doc = "Framing error interrupt status. Returns the raw interrupt state of the UARTFEINTR interrupt."]
+    #[inline(always)]
+    pub const fn feris(&self) -> bool {
+        let val = (self.0 >> 7usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Framing error interrupt status. Returns the raw interrupt state of the UARTFEINTR interrupt."]
+    #[inline(always)]
+    pub fn set_feris(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
+    }
+    #[doc = "Parity error interrupt status. Returns the raw interrupt state of the UARTPEINTR interrupt."]
+    #[inline(always)]
+    pub const fn peris(&self) -> bool {
+        let val = (self.0 >> 8usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Parity error interrupt status. Returns the raw interrupt state of the UARTPEINTR interrupt."]
+    #[inline(always)]
+    pub fn set_peris(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
+    }
+    #[doc = "Break error interrupt status. Returns the raw interrupt state of the UARTBEINTR interrupt."]
+    #[inline(always)]
+    pub const fn beris(&self) -> bool {
+        let val = (self.0 >> 9usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Break error interrupt status. Returns the raw interrupt state of the UARTBEINTR interrupt."]
+    #[inline(always)]
+    pub fn set_beris(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
+    }
+    #[doc = "Overrun error interrupt status. Returns the raw interrupt state of the UARTOEINTR interrupt."]
+    #[inline(always)]
+    pub const fn oeris(&self) -> bool {
+        let val = (self.0 >> 10usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Overrun error interrupt status. Returns the raw interrupt state of the UARTOEINTR interrupt."]
+    #[inline(always)]
+    pub fn set_oeris(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize);
+    }
+}
+impl Default for Uartris {
+    #[inline(always)]
+    fn default() -> Uartris {
+        Uartris(0)
+    }
+}
+#[doc = "Receive Status Register/Error Clear Register, UARTRSR/UARTECR"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Uartrsr(pub u32);
+impl Uartrsr {
+    #[doc = "Framing error. When set to 1, it indicates that the received character did not have a valid stop bit (a valid stop bit is 1). This bit is cleared to 0 by a write to UARTECR. In FIFO mode, this error is associated with the character at the top of the FIFO."]
+    #[inline(always)]
+    pub const fn fe(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Framing error. When set to 1, it indicates that the received character did not have a valid stop bit (a valid stop bit is 1). This bit is cleared to 0 by a write to UARTECR. In FIFO mode, this error is associated with the character at the top of the FIFO."]
+    #[inline(always)]
+    pub fn set_fe(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[doc = "Parity error. When set to 1, it indicates that the parity of the received data character does not match the parity that the EPS and SPS bits in the Line Control Register, UARTLCR_H. This bit is cleared to 0 by a write to UARTECR. In FIFO mode, this error is associated with the character at the top of the FIFO."]
+    #[inline(always)]
+    pub const fn pe(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Parity error. When set to 1, it indicates that the parity of the received data character does not match the parity that the EPS and SPS bits in the Line Control Register, UARTLCR_H. This bit is cleared to 0 by a write to UARTECR. In FIFO mode, this error is associated with the character at the top of the FIFO."]
+    #[inline(always)]
+    pub fn set_pe(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+    #[doc = "Break error. This bit is set to 1 if a break condition was detected, indicating that the received data input was held LOW for longer than a full-word transmission time (defined as start, data, parity, and stop bits). This bit is cleared to 0 after a write to UARTECR. In FIFO mode, this error is associated with the character at the top of the FIFO. When a break occurs, only one 0 character is loaded into the FIFO. The next character is only enabled after the receive data input goes to a 1 (marking state) and the next valid start bit is received."]
+    #[inline(always)]
+    pub const fn be(&self) -> bool {
+        let val = (self.0 >> 2usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Break error. This bit is set to 1 if a break condition was detected, indicating that the received data input was held LOW for longer than a full-word transmission time (defined as start, data, parity, and stop bits). This bit is cleared to 0 after a write to UARTECR. In FIFO mode, this error is associated with the character at the top of the FIFO. When a break occurs, only one 0 character is loaded into the FIFO. The next character is only enabled after the receive data input goes to a 1 (marking state) and the next valid start bit is received."]
+    #[inline(always)]
+    pub fn set_be(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+    }
+    #[doc = "Overrun error. This bit is set to 1 if data is received and the FIFO is already full. This bit is cleared to 0 by a write to UARTECR. The FIFO contents remain valid because no more data is written when the FIFO is full, only the contents of the shift register are overwritten. The CPU must now read the data, to empty the FIFO."]
+    #[inline(always)]
+    pub const fn oe(&self) -> bool {
+        let val = (self.0 >> 3usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Overrun error. This bit is set to 1 if data is received and the FIFO is already full. This bit is cleared to 0 by a write to UARTECR. The FIFO contents remain valid because no more data is written when the FIFO is full, only the contents of the shift register are overwritten. The CPU must now read the data, to empty the FIFO."]
+    #[inline(always)]
+    pub fn set_oe(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
+    }
+}
+impl Default for Uartrsr {
+    #[inline(always)]
+    fn default() -> Uartrsr {
+        Uartrsr(0)
+    }
+}
diff --git a/src/rp2350/usb.rs b/src/rp2350/usb.rs
new file mode 100644
index 00000000..388e7a5f
--- /dev/null
+++ b/src/rp2350/usb.rs
@@ -0,0 +1,190 @@
+#[doc = "USB FS/LS controller device registers"]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Usb {
+    ptr: *mut u8,
+}
+unsafe impl Send for Usb {}
+unsafe impl Sync for Usb {}
+impl Usb {
+    #[inline(always)]
+    pub const unsafe fn from_ptr(ptr: *mut ()) -> Self {
+        Self { ptr: ptr as _ }
+    }
+    #[inline(always)]
+    pub const fn as_ptr(&self) -> *mut () {
+        self.ptr as _
+    }
+    #[doc = "Device address and endpoint control"]
+    #[inline(always)]
+    pub const fn addr_endp(self) -> crate::common::Reg<regs::AddrEndp, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(0usize) as _) }
+    }
+    #[doc = "Interrupt endpoint 1. Only valid for HOST mode."]
+    #[inline(always)]
+    pub const fn addr_endp_x(
+        self,
+        n: usize,
+    ) -> crate::common::Reg<regs::AddrEndpX, crate::common::RW> {
+        assert!(n < 15usize);
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(4usize + n * 4usize) as _) }
+    }
+    #[doc = "Main control register"]
+    #[inline(always)]
+    pub const fn main_ctrl(self) -> crate::common::Reg<regs::MainCtrl, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(64usize) as _) }
+    }
+    #[doc = "Set the SOF (Start of Frame) frame number in the host controller. The SOF packet is sent every 1ms and the host will increment the frame number by 1 each time."]
+    #[inline(always)]
+    pub const fn sof_wr(self) -> crate::common::Reg<regs::SofWr, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(68usize) as _) }
+    }
+    #[doc = "Read the last SOF (Start of Frame) frame number seen. In device mode the last SOF received from the host. In host mode the last SOF sent by the host."]
+    #[inline(always)]
+    pub const fn sof_rd(self) -> crate::common::Reg<regs::SofRd, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(72usize) as _) }
+    }
+    #[doc = "SIE control register"]
+    #[inline(always)]
+    pub const fn sie_ctrl(self) -> crate::common::Reg<regs::SieCtrl, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(76usize) as _) }
+    }
+    #[doc = "SIE status register"]
+    #[inline(always)]
+    pub const fn sie_status(self) -> crate::common::Reg<regs::SieStatus, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(80usize) as _) }
+    }
+    #[doc = "interrupt endpoint control register"]
+    #[inline(always)]
+    pub const fn int_ep_ctrl(self) -> crate::common::Reg<regs::IntEpCtrl, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(84usize) as _) }
+    }
+    #[doc = "Buffer status register. A bit set here indicates that a buffer has completed on the endpoint (if the buffer interrupt is enabled). It is possible for 2 buffers to be completed, so clearing the buffer status bit may instantly re set it on the next clock cycle."]
+    #[inline(always)]
+    pub const fn buff_status(self) -> crate::common::Reg<regs::BuffStatus, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(88usize) as _) }
+    }
+    #[doc = "Which of the double buffers should be handled. Only valid if using an interrupt per buffer (i.e. not per 2 buffers). Not valid for host interrupt endpoint polling because they are only single buffered."]
+    #[inline(always)]
+    pub const fn buff_cpu_should_handle(
+        self,
+    ) -> crate::common::Reg<regs::BuffCpuShouldHandle, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(92usize) as _) }
+    }
+    #[doc = "Device only: Can be set to ignore the buffer control register for this endpoint in case you would like to revoke a buffer. A NAK will be sent for every access to the endpoint until this bit is cleared. A corresponding bit in `EP_ABORT_DONE` is set when it is safe to modify the buffer control register."]
+    #[inline(always)]
+    pub const fn ep_abort(self) -> crate::common::Reg<regs::EpAbort, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(96usize) as _) }
+    }
+    #[doc = "Device only: Used in conjunction with `EP_ABORT`. Set once an endpoint is idle so the programmer knows it is safe to modify the buffer control register."]
+    #[inline(always)]
+    pub const fn ep_abort_done(self) -> crate::common::Reg<regs::EpAbortDone, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(100usize) as _) }
+    }
+    #[doc = "Device: this bit must be set in conjunction with the `STALL` bit in the buffer control register to send a STALL on EP0. The device controller clears these bits when a SETUP packet is received because the USB spec requires that a STALL condition is cleared when a SETUP packet is received."]
+    #[inline(always)]
+    pub const fn ep_stall_arm(self) -> crate::common::Reg<regs::EpStallArm, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(104usize) as _) }
+    }
+    #[doc = "Used by the host controller. Sets the wait time in microseconds before trying again if the device replies with a NAK."]
+    #[inline(always)]
+    pub const fn nak_poll(self) -> crate::common::Reg<regs::NakPoll, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(108usize) as _) }
+    }
+    #[doc = "Device: bits are set when the `IRQ_ON_NAK` or `IRQ_ON_STALL` bits are set. For EP0 this comes from `SIE_CTRL`. For all other endpoints it comes from the endpoint control register."]
+    #[inline(always)]
+    pub const fn ep_status_stall_nak(
+        self,
+    ) -> crate::common::Reg<regs::EpStatusStallNak, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(112usize) as _) }
+    }
+    #[doc = "Where to connect the USB controller. Should be to_phy by default."]
+    #[inline(always)]
+    pub const fn usb_muxing(self) -> crate::common::Reg<regs::UsbMuxing, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(116usize) as _) }
+    }
+    #[doc = "Overrides for the power signals in the event that the VBUS signals are not hooked up to GPIO. Set the value of the override and then the override enable to switch over to the override value."]
+    #[inline(always)]
+    pub const fn usb_pwr(self) -> crate::common::Reg<regs::UsbPwr, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(120usize) as _) }
+    }
+    #[doc = "This register allows for direct control of the USB phy. Use in conjunction with usbphy_direct_override register to enable each override bit."]
+    #[inline(always)]
+    pub const fn usbphy_direct(self) -> crate::common::Reg<regs::UsbphyDirect, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(124usize) as _) }
+    }
+    #[doc = "Override enable for each control in usbphy_direct"]
+    #[inline(always)]
+    pub const fn usbphy_direct_override(
+        self,
+    ) -> crate::common::Reg<regs::UsbphyDirectOverride, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(128usize) as _) }
+    }
+    #[doc = "Used to adjust trim values of USB phy pull down resistors."]
+    #[inline(always)]
+    pub const fn usbphy_trim(self) -> crate::common::Reg<regs::UsbphyTrim, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(132usize) as _) }
+    }
+    #[doc = "Used for debug only."]
+    #[inline(always)]
+    pub const fn linestate_tuning(
+        self,
+    ) -> crate::common::Reg<regs::LinestateTuning, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(136usize) as _) }
+    }
+    #[doc = "Raw Interrupts"]
+    #[inline(always)]
+    pub const fn intr(self) -> crate::common::Reg<regs::Int, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(140usize) as _) }
+    }
+    #[doc = "Interrupt Enable"]
+    #[inline(always)]
+    pub const fn inte(self) -> crate::common::Reg<regs::Int, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(144usize) as _) }
+    }
+    #[doc = "Interrupt Force"]
+    #[inline(always)]
+    pub const fn intf(self) -> crate::common::Reg<regs::Int, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(148usize) as _) }
+    }
+    #[doc = "Interrupt status after masking & forcing"]
+    #[inline(always)]
+    pub const fn ints(self) -> crate::common::Reg<regs::Int, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(152usize) as _) }
+    }
+    #[doc = "Device only. Raw value of free-running PHY clock counter @48MHz. Used to calculate time between SOF events."]
+    #[inline(always)]
+    pub const fn sof_timestamp_raw(
+        self,
+    ) -> crate::common::Reg<regs::SofTimestampRaw, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(256usize) as _) }
+    }
+    #[doc = "Device only. Value of free-running PHY clock counter @48MHz when last SOF event occurred."]
+    #[inline(always)]
+    pub const fn sof_timestamp_last(
+        self,
+    ) -> crate::common::Reg<regs::SofTimestampLast, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(260usize) as _) }
+    }
+    #[inline(always)]
+    pub const fn sm_state(self) -> crate::common::Reg<regs::SmState, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(264usize) as _) }
+    }
+    #[doc = "TX error count for each endpoint. Write to each field to reset the counter to 0."]
+    #[inline(always)]
+    pub const fn ep_tx_error(self) -> crate::common::Reg<regs::EpTxError, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(268usize) as _) }
+    }
+    #[doc = "RX error count for each endpoint. Write to each field to reset the counter to 0."]
+    #[inline(always)]
+    pub const fn ep_rx_error(self) -> crate::common::Reg<regs::EpRxError, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(272usize) as _) }
+    }
+    #[doc = "Watchdog that forces the device state machine to idle and raises an interrupt if the device stays in a state that isn't idle for the configured limit. The counter is reset on every state transition. Set limit while enable is low and then set the enable."]
+    #[inline(always)]
+    pub const fn dev_sm_watchdog(
+        self,
+    ) -> crate::common::Reg<regs::DevSmWatchdog, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(276usize) as _) }
+    }
+}
+pub mod regs;
diff --git a/src/rp2350/usb/regs.rs b/src/rp2350/usb/regs.rs
new file mode 100644
index 00000000..590e2c74
--- /dev/null
+++ b/src/rp2350/usb/regs.rs
@@ -0,0 +1,2610 @@
+#[doc = "Device address and endpoint control"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct AddrEndp(pub u32);
+impl AddrEndp {
+    #[doc = "In device mode, the address that the device should respond to. Set in response to a SET_ADDR setup packet from the host. In host mode set to the address of the device to communicate with."]
+    #[inline(always)]
+    pub const fn address(&self) -> u8 {
+        let val = (self.0 >> 0usize) & 0x7f;
+        val as u8
+    }
+    #[doc = "In device mode, the address that the device should respond to. Set in response to a SET_ADDR setup packet from the host. In host mode set to the address of the device to communicate with."]
+    #[inline(always)]
+    pub fn set_address(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x7f << 0usize)) | (((val as u32) & 0x7f) << 0usize);
+    }
+    #[doc = "Device endpoint to send data to. Only valid for HOST mode."]
+    #[inline(always)]
+    pub const fn endpoint(&self) -> u8 {
+        let val = (self.0 >> 16usize) & 0x0f;
+        val as u8
+    }
+    #[doc = "Device endpoint to send data to. Only valid for HOST mode."]
+    #[inline(always)]
+    pub fn set_endpoint(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x0f << 16usize)) | (((val as u32) & 0x0f) << 16usize);
+    }
+}
+impl Default for AddrEndp {
+    #[inline(always)]
+    fn default() -> AddrEndp {
+        AddrEndp(0)
+    }
+}
+#[doc = "Interrupt endpoint 4. Only valid for HOST mode."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct AddrEndpX(pub u32);
+impl AddrEndpX {
+    #[doc = "Device address"]
+    #[inline(always)]
+    pub const fn address(&self) -> u8 {
+        let val = (self.0 >> 0usize) & 0x7f;
+        val as u8
+    }
+    #[doc = "Device address"]
+    #[inline(always)]
+    pub fn set_address(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x7f << 0usize)) | (((val as u32) & 0x7f) << 0usize);
+    }
+    #[doc = "Endpoint number of the interrupt endpoint"]
+    #[inline(always)]
+    pub const fn endpoint(&self) -> u8 {
+        let val = (self.0 >> 16usize) & 0x0f;
+        val as u8
+    }
+    #[doc = "Endpoint number of the interrupt endpoint"]
+    #[inline(always)]
+    pub fn set_endpoint(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x0f << 16usize)) | (((val as u32) & 0x0f) << 16usize);
+    }
+    #[doc = "Direction of the interrupt endpoint. In=0, Out=1"]
+    #[inline(always)]
+    pub const fn intep_dir(&self) -> bool {
+        let val = (self.0 >> 25usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Direction of the interrupt endpoint. In=0, Out=1"]
+    #[inline(always)]
+    pub fn set_intep_dir(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 25usize)) | (((val as u32) & 0x01) << 25usize);
+    }
+    #[doc = "Interrupt EP requires preamble (is a low speed device on a full speed hub)"]
+    #[inline(always)]
+    pub const fn intep_preamble(&self) -> bool {
+        let val = (self.0 >> 26usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Interrupt EP requires preamble (is a low speed device on a full speed hub)"]
+    #[inline(always)]
+    pub fn set_intep_preamble(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 26usize)) | (((val as u32) & 0x01) << 26usize);
+    }
+}
+impl Default for AddrEndpX {
+    #[inline(always)]
+    fn default() -> AddrEndpX {
+        AddrEndpX(0)
+    }
+}
+#[doc = "Which of the double buffers should be handled. Only valid if using an interrupt per buffer (i.e. not per 2 buffers). Not valid for host interrupt endpoint polling because they are only single buffered."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct BuffCpuShouldHandle(pub u32);
+impl BuffCpuShouldHandle {
+    #[inline(always)]
+    pub const fn ep_in(&self, n: usize) -> bool {
+        assert!(n < 16usize);
+        let offs = 0usize + n * 2usize;
+        let val = (self.0 >> offs) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_ep_in(&mut self, n: usize, val: bool) {
+        assert!(n < 16usize);
+        let offs = 0usize + n * 2usize;
+        self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
+    }
+    #[inline(always)]
+    pub const fn ep_out(&self, n: usize) -> bool {
+        assert!(n < 16usize);
+        let offs = 1usize + n * 2usize;
+        let val = (self.0 >> offs) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_ep_out(&mut self, n: usize, val: bool) {
+        assert!(n < 16usize);
+        let offs = 1usize + n * 2usize;
+        self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
+    }
+}
+impl Default for BuffCpuShouldHandle {
+    #[inline(always)]
+    fn default() -> BuffCpuShouldHandle {
+        BuffCpuShouldHandle(0)
+    }
+}
+#[doc = "Buffer status register. A bit set here indicates that a buffer has completed on the endpoint (if the buffer interrupt is enabled). It is possible for 2 buffers to be completed, so clearing the buffer status bit may instantly re set it on the next clock cycle."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct BuffStatus(pub u32);
+impl BuffStatus {
+    #[inline(always)]
+    pub const fn ep_in(&self, n: usize) -> bool {
+        assert!(n < 16usize);
+        let offs = 0usize + n * 2usize;
+        let val = (self.0 >> offs) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_ep_in(&mut self, n: usize, val: bool) {
+        assert!(n < 16usize);
+        let offs = 0usize + n * 2usize;
+        self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
+    }
+    #[inline(always)]
+    pub const fn ep_out(&self, n: usize) -> bool {
+        assert!(n < 16usize);
+        let offs = 1usize + n * 2usize;
+        let val = (self.0 >> offs) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_ep_out(&mut self, n: usize, val: bool) {
+        assert!(n < 16usize);
+        let offs = 1usize + n * 2usize;
+        self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
+    }
+}
+impl Default for BuffStatus {
+    #[inline(always)]
+    fn default() -> BuffStatus {
+        BuffStatus(0)
+    }
+}
+#[doc = "Watchdog that forces the device state machine to idle and raises an interrupt if the device stays in a state that isn't idle for the configured limit. The counter is reset on every state transition. Set limit while enable is low and then set the enable."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct DevSmWatchdog(pub u32);
+impl DevSmWatchdog {
+    #[inline(always)]
+    pub const fn limit(&self) -> u32 {
+        let val = (self.0 >> 0usize) & 0x0003_ffff;
+        val as u32
+    }
+    #[inline(always)]
+    pub fn set_limit(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x0003_ffff << 0usize)) | (((val as u32) & 0x0003_ffff) << 0usize);
+    }
+    #[inline(always)]
+    pub const fn enable(&self) -> bool {
+        let val = (self.0 >> 18usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_enable(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize);
+    }
+    #[doc = "Set to 1 to forcibly reset the device state machine on watchdog expiry"]
+    #[inline(always)]
+    pub const fn reset(&self) -> bool {
+        let val = (self.0 >> 19usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Set to 1 to forcibly reset the device state machine on watchdog expiry"]
+    #[inline(always)]
+    pub fn set_reset(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize);
+    }
+    #[inline(always)]
+    pub const fn fired(&self) -> bool {
+        let val = (self.0 >> 20usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_fired(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize);
+    }
+}
+impl Default for DevSmWatchdog {
+    #[inline(always)]
+    fn default() -> DevSmWatchdog {
+        DevSmWatchdog(0)
+    }
+}
+#[doc = "Device only: Can be set to ignore the buffer control register for this endpoint in case you would like to revoke a buffer. A NAK will be sent for every access to the endpoint until this bit is cleared. A corresponding bit in `EP_ABORT_DONE` is set when it is safe to modify the buffer control register."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct EpAbort(pub u32);
+impl EpAbort {
+    #[inline(always)]
+    pub const fn ep_in(&self, n: usize) -> bool {
+        assert!(n < 16usize);
+        let offs = 0usize + n * 2usize;
+        let val = (self.0 >> offs) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_ep_in(&mut self, n: usize, val: bool) {
+        assert!(n < 16usize);
+        let offs = 0usize + n * 2usize;
+        self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
+    }
+    #[inline(always)]
+    pub const fn ep_out(&self, n: usize) -> bool {
+        assert!(n < 16usize);
+        let offs = 1usize + n * 2usize;
+        let val = (self.0 >> offs) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_ep_out(&mut self, n: usize, val: bool) {
+        assert!(n < 16usize);
+        let offs = 1usize + n * 2usize;
+        self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
+    }
+}
+impl Default for EpAbort {
+    #[inline(always)]
+    fn default() -> EpAbort {
+        EpAbort(0)
+    }
+}
+#[doc = "Device only: Used in conjunction with `EP_ABORT`. Set once an endpoint is idle so the programmer knows it is safe to modify the buffer control register."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct EpAbortDone(pub u32);
+impl EpAbortDone {
+    #[inline(always)]
+    pub const fn ep_in(&self, n: usize) -> bool {
+        assert!(n < 16usize);
+        let offs = 0usize + n * 2usize;
+        let val = (self.0 >> offs) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_ep_in(&mut self, n: usize, val: bool) {
+        assert!(n < 16usize);
+        let offs = 0usize + n * 2usize;
+        self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
+    }
+    #[inline(always)]
+    pub const fn ep_out(&self, n: usize) -> bool {
+        assert!(n < 16usize);
+        let offs = 1usize + n * 2usize;
+        let val = (self.0 >> offs) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_ep_out(&mut self, n: usize, val: bool) {
+        assert!(n < 16usize);
+        let offs = 1usize + n * 2usize;
+        self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
+    }
+}
+impl Default for EpAbortDone {
+    #[inline(always)]
+    fn default() -> EpAbortDone {
+        EpAbortDone(0)
+    }
+}
+#[doc = "RX error count for each endpoint. Write to each field to reset the counter to 0."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct EpRxError(pub u32);
+impl EpRxError {
+    #[inline(always)]
+    pub const fn ep0_transaction(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_ep0_transaction(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[inline(always)]
+    pub const fn ep0_seq(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_ep0_seq(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+    #[inline(always)]
+    pub const fn ep1_transaction(&self) -> bool {
+        let val = (self.0 >> 2usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_ep1_transaction(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+    }
+    #[inline(always)]
+    pub const fn ep1_seq(&self) -> bool {
+        let val = (self.0 >> 3usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_ep1_seq(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
+    }
+    #[inline(always)]
+    pub const fn ep2_transaction(&self) -> bool {
+        let val = (self.0 >> 4usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_ep2_transaction(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
+    }
+    #[inline(always)]
+    pub const fn ep2_seq(&self) -> bool {
+        let val = (self.0 >> 5usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_ep2_seq(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
+    }
+    #[inline(always)]
+    pub const fn ep3_transaction(&self) -> bool {
+        let val = (self.0 >> 6usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_ep3_transaction(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
+    }
+    #[inline(always)]
+    pub const fn ep3_seq(&self) -> bool {
+        let val = (self.0 >> 7usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_ep3_seq(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
+    }
+    #[inline(always)]
+    pub const fn ep4_transaction(&self) -> bool {
+        let val = (self.0 >> 8usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_ep4_transaction(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
+    }
+    #[inline(always)]
+    pub const fn ep4_seq(&self) -> bool {
+        let val = (self.0 >> 9usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_ep4_seq(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
+    }
+    #[inline(always)]
+    pub const fn ep5_transaction(&self) -> bool {
+        let val = (self.0 >> 10usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_ep5_transaction(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize);
+    }
+    #[inline(always)]
+    pub const fn ep5_seq(&self) -> bool {
+        let val = (self.0 >> 11usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_ep5_seq(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
+    }
+    #[inline(always)]
+    pub const fn ep6_transaction(&self) -> bool {
+        let val = (self.0 >> 12usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_ep6_transaction(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
+    }
+    #[inline(always)]
+    pub const fn ep6_seq(&self) -> bool {
+        let val = (self.0 >> 13usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_ep6_seq(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize);
+    }
+    #[inline(always)]
+    pub const fn ep7_transaction(&self) -> bool {
+        let val = (self.0 >> 14usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_ep7_transaction(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize);
+    }
+    #[inline(always)]
+    pub const fn ep7_seq(&self) -> bool {
+        let val = (self.0 >> 15usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_ep7_seq(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize);
+    }
+    #[inline(always)]
+    pub const fn ep8_transaction(&self) -> bool {
+        let val = (self.0 >> 16usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_ep8_transaction(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
+    }
+    #[inline(always)]
+    pub const fn ep8_seq(&self) -> bool {
+        let val = (self.0 >> 17usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_ep8_seq(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
+    }
+    #[inline(always)]
+    pub const fn ep9_transaction(&self) -> bool {
+        let val = (self.0 >> 18usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_ep9_transaction(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize);
+    }
+    #[inline(always)]
+    pub const fn ep9_seq(&self) -> bool {
+        let val = (self.0 >> 19usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_ep9_seq(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize);
+    }
+    #[inline(always)]
+    pub const fn ep10_transaction(&self) -> bool {
+        let val = (self.0 >> 20usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_ep10_transaction(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize);
+    }
+    #[inline(always)]
+    pub const fn ep10_seq(&self) -> bool {
+        let val = (self.0 >> 21usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_ep10_seq(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 21usize)) | (((val as u32) & 0x01) << 21usize);
+    }
+    #[inline(always)]
+    pub const fn ep11_transaction(&self) -> bool {
+        let val = (self.0 >> 22usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_ep11_transaction(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 22usize)) | (((val as u32) & 0x01) << 22usize);
+    }
+    #[inline(always)]
+    pub const fn ep11_seq(&self) -> bool {
+        let val = (self.0 >> 23usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_ep11_seq(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 23usize)) | (((val as u32) & 0x01) << 23usize);
+    }
+    #[inline(always)]
+    pub const fn ep12_transaction(&self) -> bool {
+        let val = (self.0 >> 24usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_ep12_transaction(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 24usize)) | (((val as u32) & 0x01) << 24usize);
+    }
+    #[inline(always)]
+    pub const fn ep12_seq(&self) -> bool {
+        let val = (self.0 >> 25usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_ep12_seq(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 25usize)) | (((val as u32) & 0x01) << 25usize);
+    }
+    #[inline(always)]
+    pub const fn ep13_transaction(&self) -> bool {
+        let val = (self.0 >> 26usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_ep13_transaction(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 26usize)) | (((val as u32) & 0x01) << 26usize);
+    }
+    #[inline(always)]
+    pub const fn ep13_seq(&self) -> bool {
+        let val = (self.0 >> 27usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_ep13_seq(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 27usize)) | (((val as u32) & 0x01) << 27usize);
+    }
+    #[inline(always)]
+    pub const fn ep14_transaction(&self) -> bool {
+        let val = (self.0 >> 28usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_ep14_transaction(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 28usize)) | (((val as u32) & 0x01) << 28usize);
+    }
+    #[inline(always)]
+    pub const fn ep14_seq(&self) -> bool {
+        let val = (self.0 >> 29usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_ep14_seq(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 29usize)) | (((val as u32) & 0x01) << 29usize);
+    }
+    #[inline(always)]
+    pub const fn ep15_transaction(&self) -> bool {
+        let val = (self.0 >> 30usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_ep15_transaction(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 30usize)) | (((val as u32) & 0x01) << 30usize);
+    }
+    #[inline(always)]
+    pub const fn ep15_seq(&self) -> bool {
+        let val = (self.0 >> 31usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_ep15_seq(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 31usize)) | (((val as u32) & 0x01) << 31usize);
+    }
+}
+impl Default for EpRxError {
+    #[inline(always)]
+    fn default() -> EpRxError {
+        EpRxError(0)
+    }
+}
+#[doc = "Device: this bit must be set in conjunction with the `STALL` bit in the buffer control register to send a STALL on EP0. The device controller clears these bits when a SETUP packet is received because the USB spec requires that a STALL condition is cleared when a SETUP packet is received."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct EpStallArm(pub u32);
+impl EpStallArm {
+    #[inline(always)]
+    pub const fn ep0_in(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_ep0_in(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[inline(always)]
+    pub const fn ep0_out(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_ep0_out(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+}
+impl Default for EpStallArm {
+    #[inline(always)]
+    fn default() -> EpStallArm {
+        EpStallArm(0)
+    }
+}
+#[doc = "Device: bits are set when the `IRQ_ON_NAK` or `IRQ_ON_STALL` bits are set. For EP0 this comes from `SIE_CTRL`. For all other endpoints it comes from the endpoint control register."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct EpStatusStallNak(pub u32);
+impl EpStatusStallNak {
+    #[inline(always)]
+    pub const fn ep_in(&self, n: usize) -> bool {
+        assert!(n < 16usize);
+        let offs = 0usize + n * 2usize;
+        let val = (self.0 >> offs) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_ep_in(&mut self, n: usize, val: bool) {
+        assert!(n < 16usize);
+        let offs = 0usize + n * 2usize;
+        self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
+    }
+    #[inline(always)]
+    pub const fn ep_out(&self, n: usize) -> bool {
+        assert!(n < 16usize);
+        let offs = 1usize + n * 2usize;
+        let val = (self.0 >> offs) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_ep_out(&mut self, n: usize, val: bool) {
+        assert!(n < 16usize);
+        let offs = 1usize + n * 2usize;
+        self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
+    }
+}
+impl Default for EpStatusStallNak {
+    #[inline(always)]
+    fn default() -> EpStatusStallNak {
+        EpStatusStallNak(0)
+    }
+}
+#[doc = "TX error count for each endpoint. Write to each field to reset the counter to 0."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct EpTxError(pub u32);
+impl EpTxError {
+    #[inline(always)]
+    pub const fn ep0(&self) -> u8 {
+        let val = (self.0 >> 0usize) & 0x03;
+        val as u8
+    }
+    #[inline(always)]
+    pub fn set_ep0(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x03 << 0usize)) | (((val as u32) & 0x03) << 0usize);
+    }
+    #[inline(always)]
+    pub const fn ep1(&self) -> u8 {
+        let val = (self.0 >> 2usize) & 0x03;
+        val as u8
+    }
+    #[inline(always)]
+    pub fn set_ep1(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x03 << 2usize)) | (((val as u32) & 0x03) << 2usize);
+    }
+    #[inline(always)]
+    pub const fn ep2(&self) -> u8 {
+        let val = (self.0 >> 4usize) & 0x03;
+        val as u8
+    }
+    #[inline(always)]
+    pub fn set_ep2(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x03 << 4usize)) | (((val as u32) & 0x03) << 4usize);
+    }
+    #[inline(always)]
+    pub const fn ep3(&self) -> u8 {
+        let val = (self.0 >> 6usize) & 0x03;
+        val as u8
+    }
+    #[inline(always)]
+    pub fn set_ep3(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x03 << 6usize)) | (((val as u32) & 0x03) << 6usize);
+    }
+    #[inline(always)]
+    pub const fn ep4(&self) -> u8 {
+        let val = (self.0 >> 8usize) & 0x03;
+        val as u8
+    }
+    #[inline(always)]
+    pub fn set_ep4(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x03 << 8usize)) | (((val as u32) & 0x03) << 8usize);
+    }
+    #[inline(always)]
+    pub const fn ep5(&self) -> u8 {
+        let val = (self.0 >> 10usize) & 0x03;
+        val as u8
+    }
+    #[inline(always)]
+    pub fn set_ep5(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x03 << 10usize)) | (((val as u32) & 0x03) << 10usize);
+    }
+    #[inline(always)]
+    pub const fn ep6(&self) -> u8 {
+        let val = (self.0 >> 12usize) & 0x03;
+        val as u8
+    }
+    #[inline(always)]
+    pub fn set_ep6(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x03 << 12usize)) | (((val as u32) & 0x03) << 12usize);
+    }
+    #[inline(always)]
+    pub const fn ep7(&self) -> u8 {
+        let val = (self.0 >> 14usize) & 0x03;
+        val as u8
+    }
+    #[inline(always)]
+    pub fn set_ep7(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x03 << 14usize)) | (((val as u32) & 0x03) << 14usize);
+    }
+    #[inline(always)]
+    pub const fn ep8(&self) -> u8 {
+        let val = (self.0 >> 16usize) & 0x03;
+        val as u8
+    }
+    #[inline(always)]
+    pub fn set_ep8(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x03 << 16usize)) | (((val as u32) & 0x03) << 16usize);
+    }
+    #[inline(always)]
+    pub const fn ep9(&self) -> u8 {
+        let val = (self.0 >> 18usize) & 0x03;
+        val as u8
+    }
+    #[inline(always)]
+    pub fn set_ep9(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x03 << 18usize)) | (((val as u32) & 0x03) << 18usize);
+    }
+    #[inline(always)]
+    pub const fn ep10(&self) -> u8 {
+        let val = (self.0 >> 20usize) & 0x03;
+        val as u8
+    }
+    #[inline(always)]
+    pub fn set_ep10(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x03 << 20usize)) | (((val as u32) & 0x03) << 20usize);
+    }
+    #[inline(always)]
+    pub const fn ep11(&self) -> u8 {
+        let val = (self.0 >> 22usize) & 0x03;
+        val as u8
+    }
+    #[inline(always)]
+    pub fn set_ep11(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x03 << 22usize)) | (((val as u32) & 0x03) << 22usize);
+    }
+    #[inline(always)]
+    pub const fn ep12(&self) -> u8 {
+        let val = (self.0 >> 24usize) & 0x03;
+        val as u8
+    }
+    #[inline(always)]
+    pub fn set_ep12(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x03 << 24usize)) | (((val as u32) & 0x03) << 24usize);
+    }
+    #[inline(always)]
+    pub const fn ep13(&self) -> u8 {
+        let val = (self.0 >> 26usize) & 0x03;
+        val as u8
+    }
+    #[inline(always)]
+    pub fn set_ep13(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x03 << 26usize)) | (((val as u32) & 0x03) << 26usize);
+    }
+    #[inline(always)]
+    pub const fn ep14(&self) -> u8 {
+        let val = (self.0 >> 28usize) & 0x03;
+        val as u8
+    }
+    #[inline(always)]
+    pub fn set_ep14(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x03 << 28usize)) | (((val as u32) & 0x03) << 28usize);
+    }
+    #[inline(always)]
+    pub const fn ep15(&self) -> u8 {
+        let val = (self.0 >> 30usize) & 0x03;
+        val as u8
+    }
+    #[inline(always)]
+    pub fn set_ep15(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x03 << 30usize)) | (((val as u32) & 0x03) << 30usize);
+    }
+}
+impl Default for EpTxError {
+    #[inline(always)]
+    fn default() -> EpTxError {
+        EpTxError(0)
+    }
+}
+#[doc = "Raw Interrupts"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Int(pub u32);
+impl Int {
+    #[doc = "Host: raised when a device is connected or disconnected (i.e. when SIE_STATUS.SPEED changes). Cleared by writing to SIE_STATUS.SPEED"]
+    #[inline(always)]
+    pub const fn host_conn_dis(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Host: raised when a device is connected or disconnected (i.e. when SIE_STATUS.SPEED changes). Cleared by writing to SIE_STATUS.SPEED"]
+    #[inline(always)]
+    pub fn set_host_conn_dis(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[doc = "Host: raised when a device wakes up the host. Cleared by writing to SIE_STATUS.RESUME"]
+    #[inline(always)]
+    pub const fn host_resume(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Host: raised when a device wakes up the host. Cleared by writing to SIE_STATUS.RESUME"]
+    #[inline(always)]
+    pub fn set_host_resume(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+    #[doc = "Host: raised every time the host sends a SOF (Start of Frame). Cleared by reading SOF_RD"]
+    #[inline(always)]
+    pub const fn host_sof(&self) -> bool {
+        let val = (self.0 >> 2usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Host: raised every time the host sends a SOF (Start of Frame). Cleared by reading SOF_RD"]
+    #[inline(always)]
+    pub fn set_host_sof(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+    }
+    #[doc = "Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by writing to this bit."]
+    #[inline(always)]
+    pub const fn trans_complete(&self) -> bool {
+        let val = (self.0 >> 3usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by writing to this bit."]
+    #[inline(always)]
+    pub fn set_trans_complete(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
+    }
+    #[doc = "Raised when any bit in BUFF_STATUS is set. Clear by clearing all bits in BUFF_STATUS."]
+    #[inline(always)]
+    pub const fn buff_status(&self) -> bool {
+        let val = (self.0 >> 4usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Raised when any bit in BUFF_STATUS is set. Clear by clearing all bits in BUFF_STATUS."]
+    #[inline(always)]
+    pub fn set_buff_status(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
+    }
+    #[doc = "Source: SIE_STATUS.DATA_SEQ_ERROR"]
+    #[inline(always)]
+    pub const fn error_data_seq(&self) -> bool {
+        let val = (self.0 >> 5usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Source: SIE_STATUS.DATA_SEQ_ERROR"]
+    #[inline(always)]
+    pub fn set_error_data_seq(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
+    }
+    #[doc = "Source: SIE_STATUS.RX_TIMEOUT"]
+    #[inline(always)]
+    pub const fn error_rx_timeout(&self) -> bool {
+        let val = (self.0 >> 6usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Source: SIE_STATUS.RX_TIMEOUT"]
+    #[inline(always)]
+    pub fn set_error_rx_timeout(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
+    }
+    #[doc = "Source: SIE_STATUS.RX_OVERFLOW"]
+    #[inline(always)]
+    pub const fn error_rx_overflow(&self) -> bool {
+        let val = (self.0 >> 7usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Source: SIE_STATUS.RX_OVERFLOW"]
+    #[inline(always)]
+    pub fn set_error_rx_overflow(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
+    }
+    #[doc = "Source: SIE_STATUS.BIT_STUFF_ERROR"]
+    #[inline(always)]
+    pub const fn error_bit_stuff(&self) -> bool {
+        let val = (self.0 >> 8usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Source: SIE_STATUS.BIT_STUFF_ERROR"]
+    #[inline(always)]
+    pub fn set_error_bit_stuff(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
+    }
+    #[doc = "Source: SIE_STATUS.CRC_ERROR"]
+    #[inline(always)]
+    pub const fn error_crc(&self) -> bool {
+        let val = (self.0 >> 9usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Source: SIE_STATUS.CRC_ERROR"]
+    #[inline(always)]
+    pub fn set_error_crc(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
+    }
+    #[doc = "Source: SIE_STATUS.STALL_REC"]
+    #[inline(always)]
+    pub const fn stall(&self) -> bool {
+        let val = (self.0 >> 10usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Source: SIE_STATUS.STALL_REC"]
+    #[inline(always)]
+    pub fn set_stall(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize);
+    }
+    #[doc = "Source: SIE_STATUS.VBUS_DETECTED"]
+    #[inline(always)]
+    pub const fn vbus_detect(&self) -> bool {
+        let val = (self.0 >> 11usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Source: SIE_STATUS.VBUS_DETECTED"]
+    #[inline(always)]
+    pub fn set_vbus_detect(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
+    }
+    #[doc = "Source: SIE_STATUS.BUS_RESET"]
+    #[inline(always)]
+    pub const fn bus_reset(&self) -> bool {
+        let val = (self.0 >> 12usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Source: SIE_STATUS.BUS_RESET"]
+    #[inline(always)]
+    pub fn set_bus_reset(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
+    }
+    #[doc = "Set when the device connection state changes. Cleared by writing to SIE_STATUS.CONNECTED"]
+    #[inline(always)]
+    pub const fn dev_conn_dis(&self) -> bool {
+        let val = (self.0 >> 13usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Set when the device connection state changes. Cleared by writing to SIE_STATUS.CONNECTED"]
+    #[inline(always)]
+    pub fn set_dev_conn_dis(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize);
+    }
+    #[doc = "Set when the device suspend state changes. Cleared by writing to SIE_STATUS.SUSPENDED"]
+    #[inline(always)]
+    pub const fn dev_suspend(&self) -> bool {
+        let val = (self.0 >> 14usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Set when the device suspend state changes. Cleared by writing to SIE_STATUS.SUSPENDED"]
+    #[inline(always)]
+    pub fn set_dev_suspend(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize);
+    }
+    #[doc = "Set when the device receives a resume from the host. Cleared by writing to SIE_STATUS.RESUME"]
+    #[inline(always)]
+    pub const fn dev_resume_from_host(&self) -> bool {
+        let val = (self.0 >> 15usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Set when the device receives a resume from the host. Cleared by writing to SIE_STATUS.RESUME"]
+    #[inline(always)]
+    pub fn set_dev_resume_from_host(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize);
+    }
+    #[doc = "Device. Source: SIE_STATUS.SETUP_REC"]
+    #[inline(always)]
+    pub const fn setup_req(&self) -> bool {
+        let val = (self.0 >> 16usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Device. Source: SIE_STATUS.SETUP_REC"]
+    #[inline(always)]
+    pub fn set_setup_req(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
+    }
+    #[doc = "Set every time the device receives a SOF (Start of Frame) packet. Cleared by reading SOF_RD"]
+    #[inline(always)]
+    pub const fn dev_sof(&self) -> bool {
+        let val = (self.0 >> 17usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Set every time the device receives a SOF (Start of Frame) packet. Cleared by reading SOF_RD"]
+    #[inline(always)]
+    pub fn set_dev_sof(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
+    }
+    #[doc = "Raised when any bit in ABORT_DONE is set. Clear by clearing all bits in ABORT_DONE."]
+    #[inline(always)]
+    pub const fn abort_done(&self) -> bool {
+        let val = (self.0 >> 18usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Raised when any bit in ABORT_DONE is set. Clear by clearing all bits in ABORT_DONE."]
+    #[inline(always)]
+    pub fn set_abort_done(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize);
+    }
+    #[doc = "Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by clearing all bits in EP_STATUS_STALL_NAK."]
+    #[inline(always)]
+    pub const fn ep_stall_nak(&self) -> bool {
+        let val = (self.0 >> 19usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by clearing all bits in EP_STATUS_STALL_NAK."]
+    #[inline(always)]
+    pub fn set_ep_stall_nak(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize);
+    }
+    #[doc = "Source: SIE_STATUS.RX_SHORT_PACKET"]
+    #[inline(always)]
+    pub const fn rx_short_packet(&self) -> bool {
+        let val = (self.0 >> 20usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Source: SIE_STATUS.RX_SHORT_PACKET"]
+    #[inline(always)]
+    pub fn set_rx_short_packet(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize);
+    }
+    #[doc = "Source: SIE_STATUS.ENDPOINT_ERROR"]
+    #[inline(always)]
+    pub const fn endpoint_error(&self) -> bool {
+        let val = (self.0 >> 21usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Source: SIE_STATUS.ENDPOINT_ERROR"]
+    #[inline(always)]
+    pub fn set_endpoint_error(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 21usize)) | (((val as u32) & 0x01) << 21usize);
+    }
+    #[doc = "Source: DEV_SM_WATCHDOG.FIRED"]
+    #[inline(always)]
+    pub const fn dev_sm_watchdog_fired(&self) -> bool {
+        let val = (self.0 >> 22usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Source: DEV_SM_WATCHDOG.FIRED"]
+    #[inline(always)]
+    pub fn set_dev_sm_watchdog_fired(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 22usize)) | (((val as u32) & 0x01) << 22usize);
+    }
+    #[doc = "Source: NAK_POLL.EPX_STOPPED_ON_NAK"]
+    #[inline(always)]
+    pub const fn epx_stopped_on_nak(&self) -> bool {
+        let val = (self.0 >> 23usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Source: NAK_POLL.EPX_STOPPED_ON_NAK"]
+    #[inline(always)]
+    pub fn set_epx_stopped_on_nak(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 23usize)) | (((val as u32) & 0x01) << 23usize);
+    }
+}
+impl Default for Int {
+    #[inline(always)]
+    fn default() -> Int {
+        Int(0)
+    }
+}
+#[doc = "interrupt endpoint control register"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct IntEpCtrl(pub u32);
+impl IntEpCtrl {
+    #[doc = "Host: Enable interrupt endpoint 1 -> 15"]
+    #[inline(always)]
+    pub const fn int_ep_active(&self) -> u16 {
+        let val = (self.0 >> 1usize) & 0x7fff;
+        val as u16
+    }
+    #[doc = "Host: Enable interrupt endpoint 1 -> 15"]
+    #[inline(always)]
+    pub fn set_int_ep_active(&mut self, val: u16) {
+        self.0 = (self.0 & !(0x7fff << 1usize)) | (((val as u32) & 0x7fff) << 1usize);
+    }
+}
+impl Default for IntEpCtrl {
+    #[inline(always)]
+    fn default() -> IntEpCtrl {
+        IntEpCtrl(0)
+    }
+}
+#[doc = "Used for debug only."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct LinestateTuning(pub u32);
+impl LinestateTuning {
+    #[doc = "Device - register the received data to account for hub bit dribble before EOP. Only affects certain hubs."]
+    #[inline(always)]
+    pub const fn rcv_delay(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Device - register the received data to account for hub bit dribble before EOP. Only affects certain hubs."]
+    #[inline(always)]
+    pub fn set_rcv_delay(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[doc = "Device/Host - add an extra 1-bit debounce of linestate sampling."]
+    #[inline(always)]
+    pub const fn linestate_delay(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Device/Host - add an extra 1-bit debounce of linestate sampling."]
+    #[inline(always)]
+    pub fn set_linestate_delay(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+    #[doc = "Host - increase inter-packet and turnaround timeouts to accommodate worst-case hub delays."]
+    #[inline(always)]
+    pub const fn multi_hub_fix(&self) -> bool {
+        let val = (self.0 >> 2usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Host - increase inter-packet and turnaround timeouts to accommodate worst-case hub delays."]
+    #[inline(always)]
+    pub fn set_multi_hub_fix(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+    }
+    #[doc = "Device - the controller FSM performs two reads of the buffer status memory address to avoid sampling metastable data. An enabled buffer is only used if both reads match."]
+    #[inline(always)]
+    pub const fn dev_buff_control_double_read_fix(&self) -> bool {
+        let val = (self.0 >> 3usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Device - the controller FSM performs two reads of the buffer status memory address to avoid sampling metastable data. An enabled buffer is only used if both reads match."]
+    #[inline(always)]
+    pub fn set_dev_buff_control_double_read_fix(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
+    }
+    #[doc = "RX - when a bitstuff error is signalled by rx_dasm, unconditionally terminate RX decode to avoid a hang during certain packet phases."]
+    #[inline(always)]
+    pub const fn sie_rx_bitstuff_fix(&self) -> bool {
+        let val = (self.0 >> 4usize) & 0x01;
+        val != 0
+    }
+    #[doc = "RX - when a bitstuff error is signalled by rx_dasm, unconditionally terminate RX decode to avoid a hang during certain packet phases."]
+    #[inline(always)]
+    pub fn set_sie_rx_bitstuff_fix(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
+    }
+    #[doc = "RX - when recovering from line chatter or bitstuff errors, treat SE0 as the end of chatter as well as 8 consecutive idle bits."]
+    #[inline(always)]
+    pub const fn sie_rx_chatter_se0_fix(&self) -> bool {
+        let val = (self.0 >> 5usize) & 0x01;
+        val != 0
+    }
+    #[doc = "RX - when recovering from line chatter or bitstuff errors, treat SE0 as the end of chatter as well as 8 consecutive idle bits."]
+    #[inline(always)]
+    pub fn set_sie_rx_chatter_se0_fix(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
+    }
+    #[doc = "Device - suppress repeated errors until the device FSM is next in the process of decoding an inbound packet."]
+    #[inline(always)]
+    pub const fn dev_rx_err_quiesce(&self) -> bool {
+        let val = (self.0 >> 6usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Device - suppress repeated errors until the device FSM is next in the process of decoding an inbound packet."]
+    #[inline(always)]
+    pub fn set_dev_rx_err_quiesce(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
+    }
+    #[doc = "Device - exit suspend on any non-idle signalling, not qualified with a 1ms timer"]
+    #[inline(always)]
+    pub const fn dev_ls_wake_fix(&self) -> bool {
+        let val = (self.0 >> 7usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Device - exit suspend on any non-idle signalling, not qualified with a 1ms timer"]
+    #[inline(always)]
+    pub fn set_dev_ls_wake_fix(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
+    }
+    #[inline(always)]
+    pub const fn spare_fix(&self) -> u8 {
+        let val = (self.0 >> 8usize) & 0x0f;
+        val as u8
+    }
+    #[inline(always)]
+    pub fn set_spare_fix(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x0f << 8usize)) | (((val as u32) & 0x0f) << 8usize);
+    }
+}
+impl Default for LinestateTuning {
+    #[inline(always)]
+    fn default() -> LinestateTuning {
+        LinestateTuning(0)
+    }
+}
+#[doc = "Main control register"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct MainCtrl(pub u32);
+impl MainCtrl {
+    #[doc = "Enable controller"]
+    #[inline(always)]
+    pub const fn controller_en(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Enable controller"]
+    #[inline(always)]
+    pub fn set_controller_en(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[doc = "Device mode = 0, Host mode = 1"]
+    #[inline(always)]
+    pub const fn host_ndevice(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Device mode = 0, Host mode = 1"]
+    #[inline(always)]
+    pub fn set_host_ndevice(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+    #[doc = "Isolates USB phy after controller power-up Remove isolation once software has configured the controller Not isolated = 0, Isolated = 1"]
+    #[inline(always)]
+    pub const fn phy_iso(&self) -> bool {
+        let val = (self.0 >> 2usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Isolates USB phy after controller power-up Remove isolation once software has configured the controller Not isolated = 0, Isolated = 1"]
+    #[inline(always)]
+    pub fn set_phy_iso(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+    }
+    #[doc = "Reduced timings for simulation"]
+    #[inline(always)]
+    pub const fn sim_timing(&self) -> bool {
+        let val = (self.0 >> 31usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Reduced timings for simulation"]
+    #[inline(always)]
+    pub fn set_sim_timing(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 31usize)) | (((val as u32) & 0x01) << 31usize);
+    }
+}
+impl Default for MainCtrl {
+    #[inline(always)]
+    fn default() -> MainCtrl {
+        MainCtrl(0)
+    }
+}
+#[doc = "Used by the host controller. Sets the wait time in microseconds before trying again if the device replies with a NAK."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct NakPoll(pub u32);
+impl NakPoll {
+    #[doc = "NAK polling interval for a low speed device"]
+    #[inline(always)]
+    pub const fn delay_ls(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0x03ff;
+        val as u16
+    }
+    #[doc = "NAK polling interval for a low speed device"]
+    #[inline(always)]
+    pub fn set_delay_ls(&mut self, val: u16) {
+        self.0 = (self.0 & !(0x03ff << 0usize)) | (((val as u32) & 0x03ff) << 0usize);
+    }
+    #[doc = "Bits 5:0 of nak_retry_count"]
+    #[inline(always)]
+    pub const fn retry_count_lo(&self) -> u8 {
+        let val = (self.0 >> 10usize) & 0x3f;
+        val as u8
+    }
+    #[doc = "Bits 5:0 of nak_retry_count"]
+    #[inline(always)]
+    pub fn set_retry_count_lo(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x3f << 10usize)) | (((val as u32) & 0x3f) << 10usize);
+    }
+    #[doc = "NAK polling interval for a full speed device"]
+    #[inline(always)]
+    pub const fn delay_fs(&self) -> u16 {
+        let val = (self.0 >> 16usize) & 0x03ff;
+        val as u16
+    }
+    #[doc = "NAK polling interval for a full speed device"]
+    #[inline(always)]
+    pub fn set_delay_fs(&mut self, val: u16) {
+        self.0 = (self.0 & !(0x03ff << 16usize)) | (((val as u32) & 0x03ff) << 16usize);
+    }
+    #[doc = "Stop polling epx when a nak is received"]
+    #[inline(always)]
+    pub const fn stop_epx_on_nak(&self) -> bool {
+        let val = (self.0 >> 26usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Stop polling epx when a nak is received"]
+    #[inline(always)]
+    pub fn set_stop_epx_on_nak(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 26usize)) | (((val as u32) & 0x01) << 26usize);
+    }
+    #[doc = "EPX polling has stopped because a nak was received"]
+    #[inline(always)]
+    pub const fn epx_stopped_on_nak(&self) -> bool {
+        let val = (self.0 >> 27usize) & 0x01;
+        val != 0
+    }
+    #[doc = "EPX polling has stopped because a nak was received"]
+    #[inline(always)]
+    pub fn set_epx_stopped_on_nak(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 27usize)) | (((val as u32) & 0x01) << 27usize);
+    }
+    #[doc = "Bits 9:6 of nak_retry count"]
+    #[inline(always)]
+    pub const fn retry_count_hi(&self) -> u8 {
+        let val = (self.0 >> 28usize) & 0x0f;
+        val as u8
+    }
+    #[doc = "Bits 9:6 of nak_retry count"]
+    #[inline(always)]
+    pub fn set_retry_count_hi(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x0f << 28usize)) | (((val as u32) & 0x0f) << 28usize);
+    }
+}
+impl Default for NakPoll {
+    #[inline(always)]
+    fn default() -> NakPoll {
+        NakPoll(0)
+    }
+}
+#[doc = "SIE control register"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct SieCtrl(pub u32);
+impl SieCtrl {
+    #[doc = "Host: Start transaction"]
+    #[inline(always)]
+    pub const fn start_trans(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Host: Start transaction"]
+    #[inline(always)]
+    pub fn set_start_trans(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[doc = "Host: Send Setup packet"]
+    #[inline(always)]
+    pub const fn send_setup(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Host: Send Setup packet"]
+    #[inline(always)]
+    pub fn set_send_setup(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+    #[doc = "Host: Send transaction (OUT from host)"]
+    #[inline(always)]
+    pub const fn send_data(&self) -> bool {
+        let val = (self.0 >> 2usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Host: Send transaction (OUT from host)"]
+    #[inline(always)]
+    pub fn set_send_data(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+    }
+    #[doc = "Host: Receive transaction (IN to host)"]
+    #[inline(always)]
+    pub const fn receive_data(&self) -> bool {
+        let val = (self.0 >> 3usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Host: Receive transaction (IN to host)"]
+    #[inline(always)]
+    pub fn set_receive_data(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
+    }
+    #[doc = "Host: Stop transaction"]
+    #[inline(always)]
+    pub const fn stop_trans(&self) -> bool {
+        let val = (self.0 >> 4usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Host: Stop transaction"]
+    #[inline(always)]
+    pub fn set_stop_trans(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
+    }
+    #[doc = "Host: Preable enable for LS device on FS hub"]
+    #[inline(always)]
+    pub const fn preamble_en(&self) -> bool {
+        let val = (self.0 >> 6usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Host: Preable enable for LS device on FS hub"]
+    #[inline(always)]
+    pub fn set_preamble_en(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
+    }
+    #[doc = "Host: Delay packet(s) until after SOF"]
+    #[inline(always)]
+    pub const fn sof_sync(&self) -> bool {
+        let val = (self.0 >> 8usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Host: Delay packet(s) until after SOF"]
+    #[inline(always)]
+    pub fn set_sof_sync(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
+    }
+    #[doc = "Host: Enable SOF generation (for full speed bus)"]
+    #[inline(always)]
+    pub const fn sof_en(&self) -> bool {
+        let val = (self.0 >> 9usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Host: Enable SOF generation (for full speed bus)"]
+    #[inline(always)]
+    pub fn set_sof_en(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
+    }
+    #[doc = "Host: Enable keep alive packet (for low speed bus)"]
+    #[inline(always)]
+    pub const fn keep_alive_en(&self) -> bool {
+        let val = (self.0 >> 10usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Host: Enable keep alive packet (for low speed bus)"]
+    #[inline(always)]
+    pub fn set_keep_alive_en(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize);
+    }
+    #[doc = "Host: Enable VBUS"]
+    #[inline(always)]
+    pub const fn vbus_en(&self) -> bool {
+        let val = (self.0 >> 11usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Host: Enable VBUS"]
+    #[inline(always)]
+    pub fn set_vbus_en(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
+    }
+    #[doc = "Device: Remote wakeup. Device can initiate its own resume after suspend."]
+    #[inline(always)]
+    pub const fn resume(&self) -> bool {
+        let val = (self.0 >> 12usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Device: Remote wakeup. Device can initiate its own resume after suspend."]
+    #[inline(always)]
+    pub fn set_resume(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
+    }
+    #[doc = "Host: Reset bus"]
+    #[inline(always)]
+    pub const fn reset_bus(&self) -> bool {
+        let val = (self.0 >> 13usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Host: Reset bus"]
+    #[inline(always)]
+    pub fn set_reset_bus(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize);
+    }
+    #[doc = "Host: Enable pull down resistors"]
+    #[inline(always)]
+    pub const fn pulldown_en(&self) -> bool {
+        let val = (self.0 >> 15usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Host: Enable pull down resistors"]
+    #[inline(always)]
+    pub fn set_pulldown_en(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize);
+    }
+    #[doc = "Device: Enable pull up resistor"]
+    #[inline(always)]
+    pub const fn pullup_en(&self) -> bool {
+        let val = (self.0 >> 16usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Device: Enable pull up resistor"]
+    #[inline(always)]
+    pub fn set_pullup_en(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
+    }
+    #[doc = "Device: Pull-up strength (0=1K2, 1=2k3)"]
+    #[inline(always)]
+    pub const fn rpu_opt(&self) -> bool {
+        let val = (self.0 >> 17usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Device: Pull-up strength (0=1K2, 1=2k3)"]
+    #[inline(always)]
+    pub fn set_rpu_opt(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
+    }
+    #[doc = "Power down bus transceiver"]
+    #[inline(always)]
+    pub const fn transceiver_pd(&self) -> bool {
+        let val = (self.0 >> 18usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Power down bus transceiver"]
+    #[inline(always)]
+    pub fn set_transceiver_pd(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize);
+    }
+    #[doc = "Device: Stop EP0 on a short packet."]
+    #[inline(always)]
+    pub const fn ep0_stop_on_short_packet(&self) -> bool {
+        let val = (self.0 >> 19usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Device: Stop EP0 on a short packet."]
+    #[inline(always)]
+    pub fn set_ep0_stop_on_short_packet(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize);
+    }
+    #[doc = "Direct control of DM"]
+    #[inline(always)]
+    pub const fn direct_dm(&self) -> bool {
+        let val = (self.0 >> 24usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Direct control of DM"]
+    #[inline(always)]
+    pub fn set_direct_dm(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 24usize)) | (((val as u32) & 0x01) << 24usize);
+    }
+    #[doc = "Direct control of DP"]
+    #[inline(always)]
+    pub const fn direct_dp(&self) -> bool {
+        let val = (self.0 >> 25usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Direct control of DP"]
+    #[inline(always)]
+    pub fn set_direct_dp(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 25usize)) | (((val as u32) & 0x01) << 25usize);
+    }
+    #[doc = "Direct bus drive enable"]
+    #[inline(always)]
+    pub const fn direct_en(&self) -> bool {
+        let val = (self.0 >> 26usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Direct bus drive enable"]
+    #[inline(always)]
+    pub fn set_direct_en(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 26usize)) | (((val as u32) & 0x01) << 26usize);
+    }
+    #[doc = "Device: Set bit in EP_STATUS_STALL_NAK when EP0 sends a NAK"]
+    #[inline(always)]
+    pub const fn ep0_int_nak(&self) -> bool {
+        let val = (self.0 >> 27usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Device: Set bit in EP_STATUS_STALL_NAK when EP0 sends a NAK"]
+    #[inline(always)]
+    pub fn set_ep0_int_nak(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 27usize)) | (((val as u32) & 0x01) << 27usize);
+    }
+    #[doc = "Device: Set bit in BUFF_STATUS for every 2 buffers completed on EP0"]
+    #[inline(always)]
+    pub const fn ep0_int_2buf(&self) -> bool {
+        let val = (self.0 >> 28usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Device: Set bit in BUFF_STATUS for every 2 buffers completed on EP0"]
+    #[inline(always)]
+    pub fn set_ep0_int_2buf(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 28usize)) | (((val as u32) & 0x01) << 28usize);
+    }
+    #[doc = "Device: Set bit in BUFF_STATUS for every buffer completed on EP0"]
+    #[inline(always)]
+    pub const fn ep0_int_1buf(&self) -> bool {
+        let val = (self.0 >> 29usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Device: Set bit in BUFF_STATUS for every buffer completed on EP0"]
+    #[inline(always)]
+    pub fn set_ep0_int_1buf(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 29usize)) | (((val as u32) & 0x01) << 29usize);
+    }
+    #[doc = "Device: EP0 single buffered = 0, double buffered = 1"]
+    #[inline(always)]
+    pub const fn ep0_double_buf(&self) -> bool {
+        let val = (self.0 >> 30usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Device: EP0 single buffered = 0, double buffered = 1"]
+    #[inline(always)]
+    pub fn set_ep0_double_buf(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 30usize)) | (((val as u32) & 0x01) << 30usize);
+    }
+    #[doc = "Device: Set bit in EP_STATUS_STALL_NAK when EP0 sends a STALL"]
+    #[inline(always)]
+    pub const fn ep0_int_stall(&self) -> bool {
+        let val = (self.0 >> 31usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Device: Set bit in EP_STATUS_STALL_NAK when EP0 sends a STALL"]
+    #[inline(always)]
+    pub fn set_ep0_int_stall(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 31usize)) | (((val as u32) & 0x01) << 31usize);
+    }
+}
+impl Default for SieCtrl {
+    #[inline(always)]
+    fn default() -> SieCtrl {
+        SieCtrl(0)
+    }
+}
+#[doc = "SIE status register"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct SieStatus(pub u32);
+impl SieStatus {
+    #[doc = "Device: VBUS Detected"]
+    #[inline(always)]
+    pub const fn vbus_detected(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Device: VBUS Detected"]
+    #[inline(always)]
+    pub fn set_vbus_detected(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[doc = "USB bus line state"]
+    #[inline(always)]
+    pub const fn line_state(&self) -> u8 {
+        let val = (self.0 >> 2usize) & 0x03;
+        val as u8
+    }
+    #[doc = "USB bus line state"]
+    #[inline(always)]
+    pub fn set_line_state(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x03 << 2usize)) | (((val as u32) & 0x03) << 2usize);
+    }
+    #[doc = "Bus in suspended state. Valid for device. Device will go into suspend if neither Keep Alive / SOF frames are enabled."]
+    #[inline(always)]
+    pub const fn suspended(&self) -> bool {
+        let val = (self.0 >> 4usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Bus in suspended state. Valid for device. Device will go into suspend if neither Keep Alive / SOF frames are enabled."]
+    #[inline(always)]
+    pub fn set_suspended(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
+    }
+    #[doc = "Host: device speed. Disconnected = 00, LS = 01, FS = 10"]
+    #[inline(always)]
+    pub const fn speed(&self) -> u8 {
+        let val = (self.0 >> 8usize) & 0x03;
+        val as u8
+    }
+    #[doc = "Host: device speed. Disconnected = 00, LS = 01, FS = 10"]
+    #[inline(always)]
+    pub fn set_speed(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x03 << 8usize)) | (((val as u32) & 0x03) << 8usize);
+    }
+    #[doc = "VBUS over current detected"]
+    #[inline(always)]
+    pub const fn vbus_over_curr(&self) -> bool {
+        let val = (self.0 >> 10usize) & 0x01;
+        val != 0
+    }
+    #[doc = "VBUS over current detected"]
+    #[inline(always)]
+    pub fn set_vbus_over_curr(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize);
+    }
+    #[doc = "Host: Device has initiated a remote resume. Device: host has initiated a resume."]
+    #[inline(always)]
+    pub const fn resume(&self) -> bool {
+        let val = (self.0 >> 11usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Host: Device has initiated a remote resume. Device: host has initiated a resume."]
+    #[inline(always)]
+    pub fn set_resume(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
+    }
+    #[doc = "Device or Host has received a short packet. This is when the data received is less than configured in the buffer control register. Device: If using double buffered mode on device the buffer select will not be toggled after writing status back to the buffer control register. This is to prevent any further transactions on that endpoint until the user has reset the buffer control registers. Host: the current transfer will be stopped early."]
+    #[inline(always)]
+    pub const fn rx_short_packet(&self) -> bool {
+        let val = (self.0 >> 12usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Device or Host has received a short packet. This is when the data received is less than configured in the buffer control register. Device: If using double buffered mode on device the buffer select will not be toggled after writing status back to the buffer control register. This is to prevent any further transactions on that endpoint until the user has reset the buffer control registers. Host: the current transfer will be stopped early."]
+    #[inline(always)]
+    pub fn set_rx_short_packet(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
+    }
+    #[doc = "Device: connected"]
+    #[inline(always)]
+    pub const fn connected(&self) -> bool {
+        let val = (self.0 >> 16usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Device: connected"]
+    #[inline(always)]
+    pub fn set_connected(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
+    }
+    #[doc = "Device: Setup packet received"]
+    #[inline(always)]
+    pub const fn setup_rec(&self) -> bool {
+        let val = (self.0 >> 17usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Device: Setup packet received"]
+    #[inline(always)]
+    pub fn set_setup_rec(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
+    }
+    #[doc = "Transaction complete. Raised by device if: * An IN or OUT packet is sent with the `LAST_BUFF` bit set in the buffer control register Raised by host if: * A setup packet is sent when no data in or data out transaction follows * An IN packet is received and the `LAST_BUFF` bit is set in the buffer control register * An IN packet is received with zero length * An OUT packet is sent and the `LAST_BUFF` bit is set"]
+    #[inline(always)]
+    pub const fn trans_complete(&self) -> bool {
+        let val = (self.0 >> 18usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Transaction complete. Raised by device if: * An IN or OUT packet is sent with the `LAST_BUFF` bit set in the buffer control register Raised by host if: * A setup packet is sent when no data in or data out transaction follows * An IN packet is received and the `LAST_BUFF` bit is set in the buffer control register * An IN packet is received with zero length * An OUT packet is sent and the `LAST_BUFF` bit is set"]
+    #[inline(always)]
+    pub fn set_trans_complete(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize);
+    }
+    #[doc = "Device: bus reset received"]
+    #[inline(always)]
+    pub const fn bus_reset(&self) -> bool {
+        let val = (self.0 >> 19usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Device: bus reset received"]
+    #[inline(always)]
+    pub fn set_bus_reset(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize);
+    }
+    #[doc = "An endpoint has encountered an error. Read the ep_rx_error and ep_tx_error registers to find out which endpoint had an error."]
+    #[inline(always)]
+    pub const fn endpoint_error(&self) -> bool {
+        let val = (self.0 >> 23usize) & 0x01;
+        val != 0
+    }
+    #[doc = "An endpoint has encountered an error. Read the ep_rx_error and ep_tx_error registers to find out which endpoint had an error."]
+    #[inline(always)]
+    pub fn set_endpoint_error(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 23usize)) | (((val as u32) & 0x01) << 23usize);
+    }
+    #[doc = "CRC Error. Raised by the Serial RX engine."]
+    #[inline(always)]
+    pub const fn crc_error(&self) -> bool {
+        let val = (self.0 >> 24usize) & 0x01;
+        val != 0
+    }
+    #[doc = "CRC Error. Raised by the Serial RX engine."]
+    #[inline(always)]
+    pub fn set_crc_error(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 24usize)) | (((val as u32) & 0x01) << 24usize);
+    }
+    #[doc = "Bit Stuff Error. Raised by the Serial RX engine."]
+    #[inline(always)]
+    pub const fn bit_stuff_error(&self) -> bool {
+        let val = (self.0 >> 25usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Bit Stuff Error. Raised by the Serial RX engine."]
+    #[inline(always)]
+    pub fn set_bit_stuff_error(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 25usize)) | (((val as u32) & 0x01) << 25usize);
+    }
+    #[doc = "RX overflow is raised by the Serial RX engine if the incoming data is too fast."]
+    #[inline(always)]
+    pub const fn rx_overflow(&self) -> bool {
+        let val = (self.0 >> 26usize) & 0x01;
+        val != 0
+    }
+    #[doc = "RX overflow is raised by the Serial RX engine if the incoming data is too fast."]
+    #[inline(always)]
+    pub fn set_rx_overflow(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 26usize)) | (((val as u32) & 0x01) << 26usize);
+    }
+    #[doc = "RX timeout is raised by both the host and device if an ACK is not received in the maximum time specified by the USB spec."]
+    #[inline(always)]
+    pub const fn rx_timeout(&self) -> bool {
+        let val = (self.0 >> 27usize) & 0x01;
+        val != 0
+    }
+    #[doc = "RX timeout is raised by both the host and device if an ACK is not received in the maximum time specified by the USB spec."]
+    #[inline(always)]
+    pub fn set_rx_timeout(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 27usize)) | (((val as u32) & 0x01) << 27usize);
+    }
+    #[doc = "Host: NAK received"]
+    #[inline(always)]
+    pub const fn nak_rec(&self) -> bool {
+        let val = (self.0 >> 28usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Host: NAK received"]
+    #[inline(always)]
+    pub fn set_nak_rec(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 28usize)) | (((val as u32) & 0x01) << 28usize);
+    }
+    #[doc = "Host: STALL received"]
+    #[inline(always)]
+    pub const fn stall_rec(&self) -> bool {
+        let val = (self.0 >> 29usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Host: STALL received"]
+    #[inline(always)]
+    pub fn set_stall_rec(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 29usize)) | (((val as u32) & 0x01) << 29usize);
+    }
+    #[doc = "ACK received. Raised by both host and device."]
+    #[inline(always)]
+    pub const fn ack_rec(&self) -> bool {
+        let val = (self.0 >> 30usize) & 0x01;
+        val != 0
+    }
+    #[doc = "ACK received. Raised by both host and device."]
+    #[inline(always)]
+    pub fn set_ack_rec(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 30usize)) | (((val as u32) & 0x01) << 30usize);
+    }
+    #[doc = "Data Sequence Error. The device can raise a sequence error in the following conditions: * A SETUP packet is received followed by a DATA1 packet (data phase should always be DATA0) * An OUT packet is received from the host but doesn't match the data pid in the buffer control register read from DPSRAM The host can raise a data sequence error in the following conditions: * An IN packet from the device has the wrong data PID"]
+    #[inline(always)]
+    pub const fn data_seq_error(&self) -> bool {
+        let val = (self.0 >> 31usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Data Sequence Error. The device can raise a sequence error in the following conditions: * A SETUP packet is received followed by a DATA1 packet (data phase should always be DATA0) * An OUT packet is received from the host but doesn't match the data pid in the buffer control register read from DPSRAM The host can raise a data sequence error in the following conditions: * An IN packet from the device has the wrong data PID"]
+    #[inline(always)]
+    pub fn set_data_seq_error(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 31usize)) | (((val as u32) & 0x01) << 31usize);
+    }
+}
+impl Default for SieStatus {
+    #[inline(always)]
+    fn default() -> SieStatus {
+        SieStatus(0)
+    }
+}
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct SmState(pub u32);
+impl SmState {
+    #[inline(always)]
+    pub const fn state(&self) -> u8 {
+        let val = (self.0 >> 0usize) & 0x1f;
+        val as u8
+    }
+    #[inline(always)]
+    pub fn set_state(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x1f << 0usize)) | (((val as u32) & 0x1f) << 0usize);
+    }
+    #[inline(always)]
+    pub const fn bc_state(&self) -> u8 {
+        let val = (self.0 >> 5usize) & 0x07;
+        val as u8
+    }
+    #[inline(always)]
+    pub fn set_bc_state(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x07 << 5usize)) | (((val as u32) & 0x07) << 5usize);
+    }
+    #[inline(always)]
+    pub const fn rx_dasm(&self) -> u8 {
+        let val = (self.0 >> 8usize) & 0x0f;
+        val as u8
+    }
+    #[inline(always)]
+    pub fn set_rx_dasm(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x0f << 8usize)) | (((val as u32) & 0x0f) << 8usize);
+    }
+}
+impl Default for SmState {
+    #[inline(always)]
+    fn default() -> SmState {
+        SmState(0)
+    }
+}
+#[doc = "Read the last SOF (Start of Frame) frame number seen. In device mode the last SOF received from the host. In host mode the last SOF sent by the host."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct SofRd(pub u32);
+impl SofRd {
+    #[inline(always)]
+    pub const fn count(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0x07ff;
+        val as u16
+    }
+    #[inline(always)]
+    pub fn set_count(&mut self, val: u16) {
+        self.0 = (self.0 & !(0x07ff << 0usize)) | (((val as u32) & 0x07ff) << 0usize);
+    }
+}
+impl Default for SofRd {
+    #[inline(always)]
+    fn default() -> SofRd {
+        SofRd(0)
+    }
+}
+#[doc = "Device only. Value of free-running PHY clock counter @48MHz when last SOF event occurred."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct SofTimestampLast(pub u32);
+impl SofTimestampLast {
+    #[inline(always)]
+    pub const fn sof_timestamp_last(&self) -> u32 {
+        let val = (self.0 >> 0usize) & 0x001f_ffff;
+        val as u32
+    }
+    #[inline(always)]
+    pub fn set_sof_timestamp_last(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x001f_ffff << 0usize)) | (((val as u32) & 0x001f_ffff) << 0usize);
+    }
+}
+impl Default for SofTimestampLast {
+    #[inline(always)]
+    fn default() -> SofTimestampLast {
+        SofTimestampLast(0)
+    }
+}
+#[doc = "Device only. Raw value of free-running PHY clock counter @48MHz. Used to calculate time between SOF events."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct SofTimestampRaw(pub u32);
+impl SofTimestampRaw {
+    #[inline(always)]
+    pub const fn sof_timestamp_raw(&self) -> u32 {
+        let val = (self.0 >> 0usize) & 0x001f_ffff;
+        val as u32
+    }
+    #[inline(always)]
+    pub fn set_sof_timestamp_raw(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x001f_ffff << 0usize)) | (((val as u32) & 0x001f_ffff) << 0usize);
+    }
+}
+impl Default for SofTimestampRaw {
+    #[inline(always)]
+    fn default() -> SofTimestampRaw {
+        SofTimestampRaw(0)
+    }
+}
+#[doc = "Set the SOF (Start of Frame) frame number in the host controller. The SOF packet is sent every 1ms and the host will increment the frame number by 1 each time."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct SofWr(pub u32);
+impl SofWr {
+    #[inline(always)]
+    pub const fn count(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0x07ff;
+        val as u16
+    }
+    #[inline(always)]
+    pub fn set_count(&mut self, val: u16) {
+        self.0 = (self.0 & !(0x07ff << 0usize)) | (((val as u32) & 0x07ff) << 0usize);
+    }
+}
+impl Default for SofWr {
+    #[inline(always)]
+    fn default() -> SofWr {
+        SofWr(0)
+    }
+}
+#[doc = "Where to connect the USB controller. Should be to_phy by default."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct UsbMuxing(pub u32);
+impl UsbMuxing {
+    #[inline(always)]
+    pub const fn to_phy(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_to_phy(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[inline(always)]
+    pub const fn to_extphy(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_to_extphy(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+    #[inline(always)]
+    pub const fn to_digital_pad(&self) -> bool {
+        let val = (self.0 >> 2usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_to_digital_pad(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+    }
+    #[inline(always)]
+    pub const fn softcon(&self) -> bool {
+        let val = (self.0 >> 3usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_softcon(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
+    }
+    #[doc = "Use the usb DP and DM pins as GPIO pins instead of connecting them to the USB controller."]
+    #[inline(always)]
+    pub const fn usbphy_as_gpio(&self) -> bool {
+        let val = (self.0 >> 4usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Use the usb DP and DM pins as GPIO pins instead of connecting them to the USB controller."]
+    #[inline(always)]
+    pub fn set_usbphy_as_gpio(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
+    }
+    #[doc = "Swap the USB PHY DP and DM pins and all related controls and flip receive differential data. Can be used to switch USB DP/DP on the PCB. This is done at a low level so overrides all other controls."]
+    #[inline(always)]
+    pub const fn swap_dpdm(&self) -> bool {
+        let val = (self.0 >> 31usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Swap the USB PHY DP and DM pins and all related controls and flip receive differential data. Can be used to switch USB DP/DP on the PCB. This is done at a low level so overrides all other controls."]
+    #[inline(always)]
+    pub fn set_swap_dpdm(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 31usize)) | (((val as u32) & 0x01) << 31usize);
+    }
+}
+impl Default for UsbMuxing {
+    #[inline(always)]
+    fn default() -> UsbMuxing {
+        UsbMuxing(0)
+    }
+}
+#[doc = "Overrides for the power signals in the event that the VBUS signals are not hooked up to GPIO. Set the value of the override and then the override enable to switch over to the override value."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct UsbPwr(pub u32);
+impl UsbPwr {
+    #[inline(always)]
+    pub const fn vbus_en(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_vbus_en(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[inline(always)]
+    pub const fn vbus_en_override_en(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_vbus_en_override_en(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+    #[inline(always)]
+    pub const fn vbus_detect(&self) -> bool {
+        let val = (self.0 >> 2usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_vbus_detect(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+    }
+    #[inline(always)]
+    pub const fn vbus_detect_override_en(&self) -> bool {
+        let val = (self.0 >> 3usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_vbus_detect_override_en(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
+    }
+    #[inline(always)]
+    pub const fn overcurr_detect(&self) -> bool {
+        let val = (self.0 >> 4usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_overcurr_detect(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
+    }
+    #[inline(always)]
+    pub const fn overcurr_detect_en(&self) -> bool {
+        let val = (self.0 >> 5usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_overcurr_detect_en(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
+    }
+}
+impl Default for UsbPwr {
+    #[inline(always)]
+    fn default() -> UsbPwr {
+        UsbPwr(0)
+    }
+}
+#[doc = "This register allows for direct control of the USB phy. Use in conjunction with usbphy_direct_override register to enable each override bit."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct UsbphyDirect(pub u32);
+impl UsbphyDirect {
+    #[doc = "Enable the second DP pull up resistor. 0 - Pull = Rpu2; 1 - Pull = Rpu1 + Rpu2"]
+    #[inline(always)]
+    pub const fn dp_pullup_hisel(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Enable the second DP pull up resistor. 0 - Pull = Rpu2; 1 - Pull = Rpu1 + Rpu2"]
+    #[inline(always)]
+    pub fn set_dp_pullup_hisel(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[doc = "DP pull up enable"]
+    #[inline(always)]
+    pub const fn dp_pullup_en(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[doc = "DP pull up enable"]
+    #[inline(always)]
+    pub fn set_dp_pullup_en(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+    #[doc = "DP pull down enable"]
+    #[inline(always)]
+    pub const fn dp_pulldn_en(&self) -> bool {
+        let val = (self.0 >> 2usize) & 0x01;
+        val != 0
+    }
+    #[doc = "DP pull down enable"]
+    #[inline(always)]
+    pub fn set_dp_pulldn_en(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+    }
+    #[doc = "Enable the second DM pull up resistor. 0 - Pull = Rpu2; 1 - Pull = Rpu1 + Rpu2"]
+    #[inline(always)]
+    pub const fn dm_pullup_hisel(&self) -> bool {
+        let val = (self.0 >> 4usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Enable the second DM pull up resistor. 0 - Pull = Rpu2; 1 - Pull = Rpu1 + Rpu2"]
+    #[inline(always)]
+    pub fn set_dm_pullup_hisel(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
+    }
+    #[doc = "DM pull up enable"]
+    #[inline(always)]
+    pub const fn dm_pullup_en(&self) -> bool {
+        let val = (self.0 >> 5usize) & 0x01;
+        val != 0
+    }
+    #[doc = "DM pull up enable"]
+    #[inline(always)]
+    pub fn set_dm_pullup_en(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
+    }
+    #[doc = "DM pull down enable"]
+    #[inline(always)]
+    pub const fn dm_pulldn_en(&self) -> bool {
+        let val = (self.0 >> 6usize) & 0x01;
+        val != 0
+    }
+    #[doc = "DM pull down enable"]
+    #[inline(always)]
+    pub fn set_dm_pulldn_en(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
+    }
+    #[doc = "Output enable. If TX_DIFFMODE=1, OE for DPP/DPM diff pair. 0 - DPP/DPM in Hi-Z state; 1 - DPP/DPM driving If TX_DIFFMODE=0, OE for DPP only. 0 - DPP in Hi-Z state; 1 - DPP driving"]
+    #[inline(always)]
+    pub const fn tx_dp_oe(&self) -> bool {
+        let val = (self.0 >> 8usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Output enable. If TX_DIFFMODE=1, OE for DPP/DPM diff pair. 0 - DPP/DPM in Hi-Z state; 1 - DPP/DPM driving If TX_DIFFMODE=0, OE for DPP only. 0 - DPP in Hi-Z state; 1 - DPP driving"]
+    #[inline(always)]
+    pub fn set_tx_dp_oe(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
+    }
+    #[doc = "Output enable. If TX_DIFFMODE=1, Ignored. If TX_DIFFMODE=0, OE for DPM only. 0 - DPM in Hi-Z state; 1 - DPM driving"]
+    #[inline(always)]
+    pub const fn tx_dm_oe(&self) -> bool {
+        let val = (self.0 >> 9usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Output enable. If TX_DIFFMODE=1, Ignored. If TX_DIFFMODE=0, OE for DPM only. 0 - DPM in Hi-Z state; 1 - DPM driving"]
+    #[inline(always)]
+    pub fn set_tx_dm_oe(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
+    }
+    #[doc = "Output data. If TX_DIFFMODE=1, Drives DPP/DPM diff pair. TX_DP_OE=1 to enable drive. DPP=TX_DP, DPM=~TX_DP If TX_DIFFMODE=0, Drives DPP only. TX_DP_OE=1 to enable drive. DPP=TX_DP"]
+    #[inline(always)]
+    pub const fn tx_dp(&self) -> bool {
+        let val = (self.0 >> 10usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Output data. If TX_DIFFMODE=1, Drives DPP/DPM diff pair. TX_DP_OE=1 to enable drive. DPP=TX_DP, DPM=~TX_DP If TX_DIFFMODE=0, Drives DPP only. TX_DP_OE=1 to enable drive. DPP=TX_DP"]
+    #[inline(always)]
+    pub fn set_tx_dp(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize);
+    }
+    #[doc = "Output data. TX_DIFFMODE=1, Ignored TX_DIFFMODE=0, Drives DPM only. TX_DM_OE=1 to enable drive. DPM=TX_DM"]
+    #[inline(always)]
+    pub const fn tx_dm(&self) -> bool {
+        let val = (self.0 >> 11usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Output data. TX_DIFFMODE=1, Ignored TX_DIFFMODE=0, Drives DPM only. TX_DM_OE=1 to enable drive. DPM=TX_DM"]
+    #[inline(always)]
+    pub fn set_tx_dm(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
+    }
+    #[doc = "RX power down override (if override enable is set). 1 = powered down."]
+    #[inline(always)]
+    pub const fn rx_pd(&self) -> bool {
+        let val = (self.0 >> 12usize) & 0x01;
+        val != 0
+    }
+    #[doc = "RX power down override (if override enable is set). 1 = powered down."]
+    #[inline(always)]
+    pub fn set_rx_pd(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
+    }
+    #[doc = "TX power down override (if override enable is set). 1 = powered down."]
+    #[inline(always)]
+    pub const fn tx_pd(&self) -> bool {
+        let val = (self.0 >> 13usize) & 0x01;
+        val != 0
+    }
+    #[doc = "TX power down override (if override enable is set). 1 = powered down."]
+    #[inline(always)]
+    pub fn set_tx_pd(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize);
+    }
+    #[doc = "TX_FSSLEW=0: Low speed slew rate TX_FSSLEW=1: Full speed slew rate"]
+    #[inline(always)]
+    pub const fn tx_fsslew(&self) -> bool {
+        let val = (self.0 >> 14usize) & 0x01;
+        val != 0
+    }
+    #[doc = "TX_FSSLEW=0: Low speed slew rate TX_FSSLEW=1: Full speed slew rate"]
+    #[inline(always)]
+    pub fn set_tx_fsslew(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize);
+    }
+    #[doc = "TX_DIFFMODE=0: Single ended mode TX_DIFFMODE=1: Differential drive mode (TX_DM, TX_DM_OE ignored)"]
+    #[inline(always)]
+    pub const fn tx_diffmode(&self) -> bool {
+        let val = (self.0 >> 15usize) & 0x01;
+        val != 0
+    }
+    #[doc = "TX_DIFFMODE=0: Single ended mode TX_DIFFMODE=1: Differential drive mode (TX_DM, TX_DM_OE ignored)"]
+    #[inline(always)]
+    pub fn set_tx_diffmode(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize);
+    }
+    #[doc = "Differential RX"]
+    #[inline(always)]
+    pub const fn rx_dd(&self) -> bool {
+        let val = (self.0 >> 16usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Differential RX"]
+    #[inline(always)]
+    pub fn set_rx_dd(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
+    }
+    #[doc = "DPP pin state"]
+    #[inline(always)]
+    pub const fn rx_dp(&self) -> bool {
+        let val = (self.0 >> 17usize) & 0x01;
+        val != 0
+    }
+    #[doc = "DPP pin state"]
+    #[inline(always)]
+    pub fn set_rx_dp(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
+    }
+    #[doc = "DPM pin state"]
+    #[inline(always)]
+    pub const fn rx_dm(&self) -> bool {
+        let val = (self.0 >> 18usize) & 0x01;
+        val != 0
+    }
+    #[doc = "DPM pin state"]
+    #[inline(always)]
+    pub fn set_rx_dm(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize);
+    }
+    #[doc = "DP overcurrent"]
+    #[inline(always)]
+    pub const fn dp_ovcn(&self) -> bool {
+        let val = (self.0 >> 19usize) & 0x01;
+        val != 0
+    }
+    #[doc = "DP overcurrent"]
+    #[inline(always)]
+    pub fn set_dp_ovcn(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize);
+    }
+    #[doc = "DM overcurrent"]
+    #[inline(always)]
+    pub const fn dm_ovcn(&self) -> bool {
+        let val = (self.0 >> 20usize) & 0x01;
+        val != 0
+    }
+    #[doc = "DM overcurrent"]
+    #[inline(always)]
+    pub fn set_dm_ovcn(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize);
+    }
+    #[doc = "DP over voltage"]
+    #[inline(always)]
+    pub const fn dp_ovv(&self) -> bool {
+        let val = (self.0 >> 21usize) & 0x01;
+        val != 0
+    }
+    #[doc = "DP over voltage"]
+    #[inline(always)]
+    pub fn set_dp_ovv(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 21usize)) | (((val as u32) & 0x01) << 21usize);
+    }
+    #[doc = "DM over voltage"]
+    #[inline(always)]
+    pub const fn dm_ovv(&self) -> bool {
+        let val = (self.0 >> 22usize) & 0x01;
+        val != 0
+    }
+    #[doc = "DM over voltage"]
+    #[inline(always)]
+    pub fn set_dm_ovv(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 22usize)) | (((val as u32) & 0x01) << 22usize);
+    }
+    #[doc = "Override rx_dd value into controller"]
+    #[inline(always)]
+    pub const fn rx_dd_override(&self) -> bool {
+        let val = (self.0 >> 23usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Override rx_dd value into controller"]
+    #[inline(always)]
+    pub fn set_rx_dd_override(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 23usize)) | (((val as u32) & 0x01) << 23usize);
+    }
+    #[doc = "Override rx_dp value into controller"]
+    #[inline(always)]
+    pub const fn rx_dp_override(&self) -> bool {
+        let val = (self.0 >> 24usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Override rx_dp value into controller"]
+    #[inline(always)]
+    pub fn set_rx_dp_override(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 24usize)) | (((val as u32) & 0x01) << 24usize);
+    }
+    #[doc = "Override rx_dm value into controller"]
+    #[inline(always)]
+    pub const fn rx_dm_override(&self) -> bool {
+        let val = (self.0 >> 25usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Override rx_dm value into controller"]
+    #[inline(always)]
+    pub fn set_rx_dm_override(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 25usize)) | (((val as u32) & 0x01) << 25usize);
+    }
+}
+impl Default for UsbphyDirect {
+    #[inline(always)]
+    fn default() -> UsbphyDirect {
+        UsbphyDirect(0)
+    }
+}
+#[doc = "Override enable for each control in usbphy_direct"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct UsbphyDirectOverride(pub u32);
+impl UsbphyDirectOverride {
+    #[inline(always)]
+    pub const fn dp_pullup_hisel_override_en(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_dp_pullup_hisel_override_en(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[inline(always)]
+    pub const fn dm_pullup_hisel_override_en(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_dm_pullup_hisel_override_en(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+    #[inline(always)]
+    pub const fn dp_pullup_en_override_en(&self) -> bool {
+        let val = (self.0 >> 2usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_dp_pullup_en_override_en(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+    }
+    #[inline(always)]
+    pub const fn dp_pulldn_en_override_en(&self) -> bool {
+        let val = (self.0 >> 3usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_dp_pulldn_en_override_en(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
+    }
+    #[inline(always)]
+    pub const fn dm_pulldn_en_override_en(&self) -> bool {
+        let val = (self.0 >> 4usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_dm_pulldn_en_override_en(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
+    }
+    #[inline(always)]
+    pub const fn tx_dp_oe_override_en(&self) -> bool {
+        let val = (self.0 >> 5usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_tx_dp_oe_override_en(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
+    }
+    #[inline(always)]
+    pub const fn tx_dm_oe_override_en(&self) -> bool {
+        let val = (self.0 >> 6usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_tx_dm_oe_override_en(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
+    }
+    #[inline(always)]
+    pub const fn tx_dp_override_en(&self) -> bool {
+        let val = (self.0 >> 7usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_tx_dp_override_en(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
+    }
+    #[inline(always)]
+    pub const fn tx_dm_override_en(&self) -> bool {
+        let val = (self.0 >> 8usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_tx_dm_override_en(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
+    }
+    #[inline(always)]
+    pub const fn rx_pd_override_en(&self) -> bool {
+        let val = (self.0 >> 9usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_rx_pd_override_en(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
+    }
+    #[inline(always)]
+    pub const fn tx_pd_override_en(&self) -> bool {
+        let val = (self.0 >> 10usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_tx_pd_override_en(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize);
+    }
+    #[inline(always)]
+    pub const fn tx_fsslew_override_en(&self) -> bool {
+        let val = (self.0 >> 11usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_tx_fsslew_override_en(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
+    }
+    #[inline(always)]
+    pub const fn dm_pullup_override_en(&self) -> bool {
+        let val = (self.0 >> 12usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_dm_pullup_override_en(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
+    }
+    #[inline(always)]
+    pub const fn tx_diffmode_override_en(&self) -> bool {
+        let val = (self.0 >> 15usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_tx_diffmode_override_en(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize);
+    }
+    #[inline(always)]
+    pub const fn rx_dd_override_en(&self) -> bool {
+        let val = (self.0 >> 16usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_rx_dd_override_en(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
+    }
+    #[inline(always)]
+    pub const fn rx_dp_override_en(&self) -> bool {
+        let val = (self.0 >> 17usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_rx_dp_override_en(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
+    }
+    #[inline(always)]
+    pub const fn rx_dm_override_en(&self) -> bool {
+        let val = (self.0 >> 18usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_rx_dm_override_en(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize);
+    }
+}
+impl Default for UsbphyDirectOverride {
+    #[inline(always)]
+    fn default() -> UsbphyDirectOverride {
+        UsbphyDirectOverride(0)
+    }
+}
+#[doc = "Used to adjust trim values of USB phy pull down resistors."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct UsbphyTrim(pub u32);
+impl UsbphyTrim {
+    #[doc = "Value to drive to USB PHY DP pulldown resistor trim control Experimental data suggests that the reset value will work, but this register allows adjustment if required"]
+    #[inline(always)]
+    pub const fn dp_pulldn_trim(&self) -> u8 {
+        let val = (self.0 >> 0usize) & 0x1f;
+        val as u8
+    }
+    #[doc = "Value to drive to USB PHY DP pulldown resistor trim control Experimental data suggests that the reset value will work, but this register allows adjustment if required"]
+    #[inline(always)]
+    pub fn set_dp_pulldn_trim(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x1f << 0usize)) | (((val as u32) & 0x1f) << 0usize);
+    }
+    #[doc = "Value to drive to USB PHY DM pulldown resistor trim control Experimental data suggests that the reset value will work, but this register allows adjustment if required"]
+    #[inline(always)]
+    pub const fn dm_pulldn_trim(&self) -> u8 {
+        let val = (self.0 >> 8usize) & 0x1f;
+        val as u8
+    }
+    #[doc = "Value to drive to USB PHY DM pulldown resistor trim control Experimental data suggests that the reset value will work, but this register allows adjustment if required"]
+    #[inline(always)]
+    pub fn set_dm_pulldn_trim(&mut self, val: u8) {
+        self.0 = (self.0 & !(0x1f << 8usize)) | (((val as u32) & 0x1f) << 8usize);
+    }
+}
+impl Default for UsbphyTrim {
+    #[inline(always)]
+    fn default() -> UsbphyTrim {
+        UsbphyTrim(0)
+    }
+}
diff --git a/src/rp2350/usb_dpram.rs b/src/rp2350/usb_dpram.rs
new file mode 100644
index 00000000..ec3eec2a
--- /dev/null
+++ b/src/rp2350/usb_dpram.rs
@@ -0,0 +1,67 @@
+#[doc = "DPRAM layout for USB device."]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct UsbDpram {
+    ptr: *mut u8,
+}
+unsafe impl Send for UsbDpram {}
+unsafe impl Sync for UsbDpram {}
+impl UsbDpram {
+    #[inline(always)]
+    pub const unsafe fn from_ptr(ptr: *mut ()) -> Self {
+        Self { ptr: ptr as _ }
+    }
+    #[inline(always)]
+    pub const fn as_ptr(&self) -> *mut () {
+        self.ptr as _
+    }
+    #[doc = "Bytes 0-3 of the SETUP packet from the host."]
+    #[inline(always)]
+    pub const fn setup_packet_low(
+        self,
+    ) -> crate::common::Reg<regs::SetupPacketLow, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(0usize) as _) }
+    }
+    #[doc = "Bytes 4-7 of the setup packet from the host."]
+    #[inline(always)]
+    pub const fn setup_packet_high(
+        self,
+    ) -> crate::common::Reg<regs::SetupPacketHigh, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(4usize) as _) }
+    }
+    #[inline(always)]
+    pub const fn ep_in_control(
+        self,
+        n: usize,
+    ) -> crate::common::Reg<regs::EpControl, crate::common::RW> {
+        assert!(n < 15usize);
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(8usize + n * 8usize) as _) }
+    }
+    #[inline(always)]
+    pub const fn ep_out_control(
+        self,
+        n: usize,
+    ) -> crate::common::Reg<regs::EpControl, crate::common::RW> {
+        assert!(n < 15usize);
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(12usize + n * 8usize) as _) }
+    }
+    #[doc = "Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode."]
+    #[inline(always)]
+    pub const fn ep_in_buffer_control(
+        self,
+        n: usize,
+    ) -> crate::common::Reg<regs::EpBufferControl, crate::common::RW> {
+        assert!(n < 16usize);
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(128usize + n * 8usize) as _) }
+    }
+    #[doc = "Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode."]
+    #[inline(always)]
+    pub const fn ep_out_buffer_control(
+        self,
+        n: usize,
+    ) -> crate::common::Reg<regs::EpBufferControl, crate::common::RW> {
+        assert!(n < 16usize);
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(132usize + n * 8usize) as _) }
+    }
+}
+pub mod regs;
+pub mod vals;
diff --git a/src/rp2350/usb_dpram/regs.rs b/src/rp2350/usb_dpram/regs.rs
new file mode 100644
index 00000000..f249c875
--- /dev/null
+++ b/src/rp2350/usb_dpram/regs.rs
@@ -0,0 +1,291 @@
+#[doc = "Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct EpBufferControl(pub u32);
+impl EpBufferControl {
+    #[doc = "The length of the data in buffer 1."]
+    #[inline(always)]
+    pub const fn length(&self, n: usize) -> u16 {
+        assert!(n < 2usize);
+        let offs = 0usize + n * 16usize;
+        let val = (self.0 >> offs) & 0x03ff;
+        val as u16
+    }
+    #[doc = "The length of the data in buffer 1."]
+    #[inline(always)]
+    pub fn set_length(&mut self, n: usize, val: u16) {
+        assert!(n < 2usize);
+        let offs = 0usize + n * 16usize;
+        self.0 = (self.0 & !(0x03ff << offs)) | (((val as u32) & 0x03ff) << offs);
+    }
+    #[doc = "Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back."]
+    #[inline(always)]
+    pub const fn available(&self, n: usize) -> bool {
+        assert!(n < 2usize);
+        let offs = 10usize + n * 16usize;
+        let val = (self.0 >> offs) & 0x01;
+        val != 0
+    }
+    #[doc = "Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back."]
+    #[inline(always)]
+    pub fn set_available(&mut self, n: usize, val: bool) {
+        assert!(n < 2usize);
+        let offs = 10usize + n * 16usize;
+        self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
+    }
+    #[doc = "Reply with a stall (valid for both buffers)."]
+    #[inline(always)]
+    pub const fn stall(&self) -> bool {
+        let val = (self.0 >> 11usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Reply with a stall (valid for both buffers)."]
+    #[inline(always)]
+    pub fn set_stall(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
+    }
+    #[doc = "Reset the buffer selector to buffer 0."]
+    #[inline(always)]
+    pub const fn reset(&self) -> bool {
+        let val = (self.0 >> 12usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Reset the buffer selector to buffer 0."]
+    #[inline(always)]
+    pub fn set_reset(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
+    }
+    #[doc = "The data pid of buffer 0."]
+    #[inline(always)]
+    pub const fn pid(&self, n: usize) -> bool {
+        assert!(n < 2usize);
+        let offs = 13usize + n * 16usize;
+        let val = (self.0 >> offs) & 0x01;
+        val != 0
+    }
+    #[doc = "The data pid of buffer 0."]
+    #[inline(always)]
+    pub fn set_pid(&mut self, n: usize, val: bool) {
+        assert!(n < 2usize);
+        let offs = 13usize + n * 16usize;
+        self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
+    }
+    #[doc = "Buffer 0 is the last buffer of the transfer."]
+    #[inline(always)]
+    pub const fn last(&self, n: usize) -> bool {
+        assert!(n < 2usize);
+        let offs = 14usize + n * 16usize;
+        let val = (self.0 >> offs) & 0x01;
+        val != 0
+    }
+    #[doc = "Buffer 0 is the last buffer of the transfer."]
+    #[inline(always)]
+    pub fn set_last(&mut self, n: usize, val: bool) {
+        assert!(n < 2usize);
+        let offs = 14usize + n * 16usize;
+        self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
+    }
+    #[doc = "Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data."]
+    #[inline(always)]
+    pub const fn full(&self, n: usize) -> bool {
+        assert!(n < 2usize);
+        let offs = 15usize + n * 16usize;
+        let val = (self.0 >> offs) & 0x01;
+        val != 0
+    }
+    #[doc = "Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data."]
+    #[inline(always)]
+    pub fn set_full(&mut self, n: usize, val: bool) {
+        assert!(n < 2usize);
+        let offs = 15usize + n * 16usize;
+        self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
+    }
+    #[doc = "The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. For a non Isochronous endpoint the offset is always 64 bytes."]
+    #[inline(always)]
+    pub const fn double_buffer_iso_offset(
+        &self,
+    ) -> super::vals::EpBufferControlDoubleBufferIsoOffset {
+        let val = (self.0 >> 27usize) & 0x03;
+        super::vals::EpBufferControlDoubleBufferIsoOffset::from_bits(val as u8)
+    }
+    #[doc = "The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. For a non Isochronous endpoint the offset is always 64 bytes."]
+    #[inline(always)]
+    pub fn set_double_buffer_iso_offset(
+        &mut self,
+        val: super::vals::EpBufferControlDoubleBufferIsoOffset,
+    ) {
+        self.0 = (self.0 & !(0x03 << 27usize)) | (((val.to_bits() as u32) & 0x03) << 27usize);
+    }
+}
+impl Default for EpBufferControl {
+    #[inline(always)]
+    fn default() -> EpBufferControl {
+        EpBufferControl(0)
+    }
+}
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct EpControl(pub u32);
+impl EpControl {
+    #[doc = "64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM."]
+    #[inline(always)]
+    pub const fn buffer_address(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0xffff;
+        val as u16
+    }
+    #[doc = "64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM."]
+    #[inline(always)]
+    pub fn set_buffer_address(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+    }
+    #[doc = "Trigger an interrupt if a NAK is sent. Intended for debug only."]
+    #[inline(always)]
+    pub const fn interrupt_on_nak(&self) -> bool {
+        let val = (self.0 >> 16usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Trigger an interrupt if a NAK is sent. Intended for debug only."]
+    #[inline(always)]
+    pub fn set_interrupt_on_nak(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
+    }
+    #[doc = "Trigger an interrupt if a STALL is sent. Intended for debug only."]
+    #[inline(always)]
+    pub const fn interrupt_on_stall(&self) -> bool {
+        let val = (self.0 >> 17usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Trigger an interrupt if a STALL is sent. Intended for debug only."]
+    #[inline(always)]
+    pub fn set_interrupt_on_stall(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
+    }
+    #[inline(always)]
+    pub const fn endpoint_type(&self) -> super::vals::EpControlEndpointType {
+        let val = (self.0 >> 26usize) & 0x03;
+        super::vals::EpControlEndpointType::from_bits(val as u8)
+    }
+    #[inline(always)]
+    pub fn set_endpoint_type(&mut self, val: super::vals::EpControlEndpointType) {
+        self.0 = (self.0 & !(0x03 << 26usize)) | (((val.to_bits() as u32) & 0x03) << 26usize);
+    }
+    #[doc = "Trigger an interrupt each time both buffers are done. Only valid in double buffered mode."]
+    #[inline(always)]
+    pub const fn interrupt_per_double_buff(&self) -> bool {
+        let val = (self.0 >> 28usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Trigger an interrupt each time both buffers are done. Only valid in double buffered mode."]
+    #[inline(always)]
+    pub fn set_interrupt_per_double_buff(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 28usize)) | (((val as u32) & 0x01) << 28usize);
+    }
+    #[doc = "Trigger an interrupt each time a buffer is done."]
+    #[inline(always)]
+    pub const fn interrupt_per_buff(&self) -> bool {
+        let val = (self.0 >> 29usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Trigger an interrupt each time a buffer is done."]
+    #[inline(always)]
+    pub fn set_interrupt_per_buff(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 29usize)) | (((val as u32) & 0x01) << 29usize);
+    }
+    #[doc = "This endpoint is double buffered."]
+    #[inline(always)]
+    pub const fn double_buffered(&self) -> bool {
+        let val = (self.0 >> 30usize) & 0x01;
+        val != 0
+    }
+    #[doc = "This endpoint is double buffered."]
+    #[inline(always)]
+    pub fn set_double_buffered(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 30usize)) | (((val as u32) & 0x01) << 30usize);
+    }
+    #[doc = "Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set."]
+    #[inline(always)]
+    pub const fn enable(&self) -> bool {
+        let val = (self.0 >> 31usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set."]
+    #[inline(always)]
+    pub fn set_enable(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 31usize)) | (((val as u32) & 0x01) << 31usize);
+    }
+}
+impl Default for EpControl {
+    #[inline(always)]
+    fn default() -> EpControl {
+        EpControl(0)
+    }
+}
+#[doc = "Bytes 4-7 of the setup packet from the host."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct SetupPacketHigh(pub u32);
+impl SetupPacketHigh {
+    #[inline(always)]
+    pub const fn windex(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0xffff;
+        val as u16
+    }
+    #[inline(always)]
+    pub fn set_windex(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+    }
+    #[inline(always)]
+    pub const fn wlength(&self) -> u16 {
+        let val = (self.0 >> 16usize) & 0xffff;
+        val as u16
+    }
+    #[inline(always)]
+    pub fn set_wlength(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 16usize)) | (((val as u32) & 0xffff) << 16usize);
+    }
+}
+impl Default for SetupPacketHigh {
+    #[inline(always)]
+    fn default() -> SetupPacketHigh {
+        SetupPacketHigh(0)
+    }
+}
+#[doc = "Bytes 0-3 of the SETUP packet from the host."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct SetupPacketLow(pub u32);
+impl SetupPacketLow {
+    #[inline(always)]
+    pub const fn bmrequesttype(&self) -> u8 {
+        let val = (self.0 >> 0usize) & 0xff;
+        val as u8
+    }
+    #[inline(always)]
+    pub fn set_bmrequesttype(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize);
+    }
+    #[inline(always)]
+    pub const fn brequest(&self) -> u8 {
+        let val = (self.0 >> 8usize) & 0xff;
+        val as u8
+    }
+    #[inline(always)]
+    pub fn set_brequest(&mut self, val: u8) {
+        self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize);
+    }
+    #[inline(always)]
+    pub const fn wvalue(&self) -> u16 {
+        let val = (self.0 >> 16usize) & 0xffff;
+        val as u16
+    }
+    #[inline(always)]
+    pub fn set_wvalue(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 16usize)) | (((val as u32) & 0xffff) << 16usize);
+    }
+}
+impl Default for SetupPacketLow {
+    #[inline(always)]
+    fn default() -> SetupPacketLow {
+        SetupPacketLow(0)
+    }
+}
diff --git a/src/rp2350/usb_dpram/vals.rs b/src/rp2350/usb_dpram/vals.rs
new file mode 100644
index 00000000..d0e39228
--- /dev/null
+++ b/src/rp2350/usb_dpram/vals.rs
@@ -0,0 +1,60 @@
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum EpBufferControlDoubleBufferIsoOffset {
+    _128 = 0,
+    _256 = 0x01,
+    _512 = 0x02,
+    _1024 = 0x03,
+}
+impl EpBufferControlDoubleBufferIsoOffset {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> EpBufferControlDoubleBufferIsoOffset {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for EpBufferControlDoubleBufferIsoOffset {
+    #[inline(always)]
+    fn from(val: u8) -> EpBufferControlDoubleBufferIsoOffset {
+        EpBufferControlDoubleBufferIsoOffset::from_bits(val)
+    }
+}
+impl From<EpBufferControlDoubleBufferIsoOffset> for u8 {
+    #[inline(always)]
+    fn from(val: EpBufferControlDoubleBufferIsoOffset) -> u8 {
+        EpBufferControlDoubleBufferIsoOffset::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum EpControlEndpointType {
+    CONTROL = 0,
+    ISOCHRONOUS = 0x01,
+    BULK = 0x02,
+    INTERRUPT = 0x03,
+}
+impl EpControlEndpointType {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> EpControlEndpointType {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for EpControlEndpointType {
+    #[inline(always)]
+    fn from(val: u8) -> EpControlEndpointType {
+        EpControlEndpointType::from_bits(val)
+    }
+}
+impl From<EpControlEndpointType> for u8 {
+    #[inline(always)]
+    fn from(val: EpControlEndpointType) -> u8 {
+        EpControlEndpointType::to_bits(val)
+    }
+}
diff --git a/src/rp2350/watchdog.rs b/src/rp2350/watchdog.rs
new file mode 100644
index 00000000..4c60649e
--- /dev/null
+++ b/src/rp2350/watchdog.rs
@@ -0,0 +1,72 @@
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Watchdog {
+    ptr: *mut u8,
+}
+unsafe impl Send for Watchdog {}
+unsafe impl Sync for Watchdog {}
+impl Watchdog {
+    #[inline(always)]
+    pub const unsafe fn from_ptr(ptr: *mut ()) -> Self {
+        Self { ptr: ptr as _ }
+    }
+    #[inline(always)]
+    pub const fn as_ptr(&self) -> *mut () {
+        self.ptr as _
+    }
+    #[doc = "Watchdog control The rst_wdsel register determines which subsystems are reset when the watchdog is triggered. The watchdog can be triggered in software."]
+    #[inline(always)]
+    pub const fn ctrl(self) -> crate::common::Reg<regs::Ctrl, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(0usize) as _) }
+    }
+    #[doc = "Load the watchdog timer. The maximum setting is 0xffffff which corresponds to approximately 16 seconds."]
+    #[inline(always)]
+    pub const fn load(self) -> crate::common::Reg<regs::Load, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(4usize) as _) }
+    }
+    #[doc = "Logs the reason for the last reset. Both bits are zero for the case of a hardware reset. Additionally, as of RP2350, a debugger warm reset of either core (SYSRESETREQ or hartreset) will also clear the watchdog reason register, so that software loaded under the debugger following a watchdog timeout will not continue to see the timeout condition."]
+    #[inline(always)]
+    pub const fn reason(self) -> crate::common::Reg<regs::Reason, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(8usize) as _) }
+    }
+    #[doc = "Scratch register. Information persists through soft reset of the chip."]
+    #[inline(always)]
+    pub const fn scratch0(self) -> crate::common::Reg<u32, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(12usize) as _) }
+    }
+    #[doc = "Scratch register. Information persists through soft reset of the chip."]
+    #[inline(always)]
+    pub const fn scratch1(self) -> crate::common::Reg<u32, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(16usize) as _) }
+    }
+    #[doc = "Scratch register. Information persists through soft reset of the chip."]
+    #[inline(always)]
+    pub const fn scratch2(self) -> crate::common::Reg<u32, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(20usize) as _) }
+    }
+    #[doc = "Scratch register. Information persists through soft reset of the chip."]
+    #[inline(always)]
+    pub const fn scratch3(self) -> crate::common::Reg<u32, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(24usize) as _) }
+    }
+    #[doc = "Scratch register. Information persists through soft reset of the chip."]
+    #[inline(always)]
+    pub const fn scratch4(self) -> crate::common::Reg<u32, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(28usize) as _) }
+    }
+    #[doc = "Scratch register. Information persists through soft reset of the chip."]
+    #[inline(always)]
+    pub const fn scratch5(self) -> crate::common::Reg<u32, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(32usize) as _) }
+    }
+    #[doc = "Scratch register. Information persists through soft reset of the chip."]
+    #[inline(always)]
+    pub const fn scratch6(self) -> crate::common::Reg<u32, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(36usize) as _) }
+    }
+    #[doc = "Scratch register. Information persists through soft reset of the chip."]
+    #[inline(always)]
+    pub const fn scratch7(self) -> crate::common::Reg<u32, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(40usize) as _) }
+    }
+}
+pub mod regs;
diff --git a/src/rp2350/watchdog/regs.rs b/src/rp2350/watchdog/regs.rs
new file mode 100644
index 00000000..31eab793
--- /dev/null
+++ b/src/rp2350/watchdog/regs.rs
@@ -0,0 +1,129 @@
+#[doc = "Watchdog control The rst_wdsel register determines which subsystems are reset when the watchdog is triggered. The watchdog can be triggered in software."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Ctrl(pub u32);
+impl Ctrl {
+    #[doc = "Indicates the time in usec before a watchdog reset will be triggered"]
+    #[inline(always)]
+    pub const fn time(&self) -> u32 {
+        let val = (self.0 >> 0usize) & 0x00ff_ffff;
+        val as u32
+    }
+    #[doc = "Indicates the time in usec before a watchdog reset will be triggered"]
+    #[inline(always)]
+    pub fn set_time(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize);
+    }
+    #[doc = "Pause the watchdog timer when JTAG is accessing the bus fabric"]
+    #[inline(always)]
+    pub const fn pause_jtag(&self) -> bool {
+        let val = (self.0 >> 24usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Pause the watchdog timer when JTAG is accessing the bus fabric"]
+    #[inline(always)]
+    pub fn set_pause_jtag(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 24usize)) | (((val as u32) & 0x01) << 24usize);
+    }
+    #[doc = "Pause the watchdog timer when processor 0 is in debug mode"]
+    #[inline(always)]
+    pub const fn pause_dbg0(&self) -> bool {
+        let val = (self.0 >> 25usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Pause the watchdog timer when processor 0 is in debug mode"]
+    #[inline(always)]
+    pub fn set_pause_dbg0(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 25usize)) | (((val as u32) & 0x01) << 25usize);
+    }
+    #[doc = "Pause the watchdog timer when processor 1 is in debug mode"]
+    #[inline(always)]
+    pub const fn pause_dbg1(&self) -> bool {
+        let val = (self.0 >> 26usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Pause the watchdog timer when processor 1 is in debug mode"]
+    #[inline(always)]
+    pub fn set_pause_dbg1(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 26usize)) | (((val as u32) & 0x01) << 26usize);
+    }
+    #[doc = "When not enabled the watchdog timer is paused"]
+    #[inline(always)]
+    pub const fn enable(&self) -> bool {
+        let val = (self.0 >> 30usize) & 0x01;
+        val != 0
+    }
+    #[doc = "When not enabled the watchdog timer is paused"]
+    #[inline(always)]
+    pub fn set_enable(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 30usize)) | (((val as u32) & 0x01) << 30usize);
+    }
+    #[doc = "Trigger a watchdog reset"]
+    #[inline(always)]
+    pub const fn trigger(&self) -> bool {
+        let val = (self.0 >> 31usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Trigger a watchdog reset"]
+    #[inline(always)]
+    pub fn set_trigger(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 31usize)) | (((val as u32) & 0x01) << 31usize);
+    }
+}
+impl Default for Ctrl {
+    #[inline(always)]
+    fn default() -> Ctrl {
+        Ctrl(0)
+    }
+}
+#[doc = "Load the watchdog timer. The maximum setting is 0xffffff which corresponds to approximately 16 seconds."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Load(pub u32);
+impl Load {
+    #[inline(always)]
+    pub const fn load(&self) -> u32 {
+        let val = (self.0 >> 0usize) & 0x00ff_ffff;
+        val as u32
+    }
+    #[inline(always)]
+    pub fn set_load(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize);
+    }
+}
+impl Default for Load {
+    #[inline(always)]
+    fn default() -> Load {
+        Load(0)
+    }
+}
+#[doc = "Logs the reason for the last reset. Both bits are zero for the case of a hardware reset. Additionally, as of RP2350, a debugger warm reset of either core (SYSRESETREQ or hartreset) will also clear the watchdog reason register, so that software loaded under the debugger following a watchdog timeout will not continue to see the timeout condition."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Reason(pub u32);
+impl Reason {
+    #[inline(always)]
+    pub const fn timer(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_timer(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[inline(always)]
+    pub const fn force(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[inline(always)]
+    pub fn set_force(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+}
+impl Default for Reason {
+    #[inline(always)]
+    fn default() -> Reason {
+        Reason(0)
+    }
+}
diff --git a/src/rp2350/xip_aux.rs b/src/rp2350/xip_aux.rs
new file mode 100644
index 00000000..e81beae5
--- /dev/null
+++ b/src/rp2350/xip_aux.rs
@@ -0,0 +1,34 @@
+#[doc = "Auxiliary DMA access to XIP FIFOs, via fast AHB bus access"]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct XipAux {
+    ptr: *mut u8,
+}
+unsafe impl Send for XipAux {}
+unsafe impl Sync for XipAux {}
+impl XipAux {
+    #[inline(always)]
+    pub const unsafe fn from_ptr(ptr: *mut ()) -> Self {
+        Self { ptr: ptr as _ }
+    }
+    #[inline(always)]
+    pub const fn as_ptr(&self) -> *mut () {
+        self.ptr as _
+    }
+    #[doc = "Read the XIP stream FIFO (fast bus access to XIP_CTRL_STREAM_FIFO)"]
+    #[inline(always)]
+    pub const fn stream(self) -> crate::common::Reg<u32, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(0usize) as _) }
+    }
+    #[doc = "Write to the QMI direct-mode TX FIFO (fast bus access to QMI_DIRECT_TX)"]
+    #[inline(always)]
+    pub const fn qmi_direct_tx(self) -> crate::common::Reg<regs::QmiDirectTx, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(4usize) as _) }
+    }
+    #[doc = "Read from the QMI direct-mode RX FIFO (fast bus access to QMI_DIRECT_RX)"]
+    #[inline(always)]
+    pub const fn qmi_direct_rx(self) -> crate::common::Reg<regs::QmiDirectRx, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(8usize) as _) }
+    }
+}
+pub mod regs;
+pub mod vals;
diff --git a/src/rp2350/xip_aux/regs.rs b/src/rp2350/xip_aux/regs.rs
new file mode 100644
index 00000000..f0dc0f1d
--- /dev/null
+++ b/src/rp2350/xip_aux/regs.rs
@@ -0,0 +1,90 @@
+#[doc = "Read from the QMI direct-mode RX FIFO (fast bus access to QMI_DIRECT_RX)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct QmiDirectRx(pub u32);
+impl QmiDirectRx {
+    #[doc = "With each byte clocked out on the serial interface, one byte will simultaneously be clocked in, and will appear in this FIFO. The serial interface will stall when this FIFO is full, to avoid dropping data. When 16-bit data is pushed into the TX FIFO, the corresponding RX FIFO push will also contain 16 bits of data. The least-significant byte is the first one received."]
+    #[inline(always)]
+    pub const fn qmi_direct_rx(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0xffff;
+        val as u16
+    }
+    #[doc = "With each byte clocked out on the serial interface, one byte will simultaneously be clocked in, and will appear in this FIFO. The serial interface will stall when this FIFO is full, to avoid dropping data. When 16-bit data is pushed into the TX FIFO, the corresponding RX FIFO push will also contain 16 bits of data. The least-significant byte is the first one received."]
+    #[inline(always)]
+    pub fn set_qmi_direct_rx(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+    }
+}
+impl Default for QmiDirectRx {
+    #[inline(always)]
+    fn default() -> QmiDirectRx {
+        QmiDirectRx(0)
+    }
+}
+#[doc = "Write to the QMI direct-mode TX FIFO (fast bus access to QMI_DIRECT_TX)"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct QmiDirectTx(pub u32);
+impl QmiDirectTx {
+    #[doc = "Data pushed here will be clocked out falling edges of SCK (or before the very first rising edge of SCK, if this is the first pulse). For each byte clocked out, the interface will simultaneously sample one byte, on rising edges of SCK, and push this to the DIRECT_RX FIFO. For 16-bit data, the least-significant byte is transmitted first."]
+    #[inline(always)]
+    pub const fn data(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0xffff;
+        val as u16
+    }
+    #[doc = "Data pushed here will be clocked out falling edges of SCK (or before the very first rising edge of SCK, if this is the first pulse). For each byte clocked out, the interface will simultaneously sample one byte, on rising edges of SCK, and push this to the DIRECT_RX FIFO. For 16-bit data, the least-significant byte is transmitted first."]
+    #[inline(always)]
+    pub fn set_data(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+    }
+    #[doc = "Configure whether this FIFO record is transferred with single/dual/quad interface width (0/1/2). Different widths can be mixed freely."]
+    #[inline(always)]
+    pub const fn iwidth(&self) -> super::vals::Iwidth {
+        let val = (self.0 >> 16usize) & 0x03;
+        super::vals::Iwidth::from_bits(val as u8)
+    }
+    #[doc = "Configure whether this FIFO record is transferred with single/dual/quad interface width (0/1/2). Different widths can be mixed freely."]
+    #[inline(always)]
+    pub fn set_iwidth(&mut self, val: super::vals::Iwidth) {
+        self.0 = (self.0 & !(0x03 << 16usize)) | (((val.to_bits() as u32) & 0x03) << 16usize);
+    }
+    #[doc = "Data width. If 0, hardware will transmit the 8 LSBs of the DIRECT_TX DATA field, and return an 8-bit value in the 8 LSBs of DIRECT_RX. If 1, the full 16-bit width is used. 8-bit and 16-bit transfers can be mixed freely."]
+    #[inline(always)]
+    pub const fn dwidth(&self) -> bool {
+        let val = (self.0 >> 18usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Data width. If 0, hardware will transmit the 8 LSBs of the DIRECT_TX DATA field, and return an 8-bit value in the 8 LSBs of DIRECT_RX. If 1, the full 16-bit width is used. 8-bit and 16-bit transfers can be mixed freely."]
+    #[inline(always)]
+    pub fn set_dwidth(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize);
+    }
+    #[doc = "Output enable (active-high). For single width (SPI), this field is ignored, and SD0 is always set to output, with SD1 always set to input. For dual and quad width (DSPI/QSPI), this sets whether the relevant SDx pads are set to output whilst transferring this FIFO record. In this case the command/address should have OE set, and the data transfer should have OE set or clear depending on the direction of the transfer."]
+    #[inline(always)]
+    pub const fn oe(&self) -> bool {
+        let val = (self.0 >> 19usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Output enable (active-high). For single width (SPI), this field is ignored, and SD0 is always set to output, with SD1 always set to input. For dual and quad width (DSPI/QSPI), this sets whether the relevant SDx pads are set to output whilst transferring this FIFO record. In this case the command/address should have OE set, and the data transfer should have OE set or clear depending on the direction of the transfer."]
+    #[inline(always)]
+    pub fn set_oe(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize);
+    }
+    #[doc = "Inhibit the RX FIFO push that would correspond to this TX FIFO entry. Useful to avoid garbage appearing in the RX FIFO when pushing the command at the beginning of a SPI transfer."]
+    #[inline(always)]
+    pub const fn nopush(&self) -> bool {
+        let val = (self.0 >> 20usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Inhibit the RX FIFO push that would correspond to this TX FIFO entry. Useful to avoid garbage appearing in the RX FIFO when pushing the command at the beginning of a SPI transfer."]
+    #[inline(always)]
+    pub fn set_nopush(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize);
+    }
+}
+impl Default for QmiDirectTx {
+    #[inline(always)]
+    fn default() -> QmiDirectTx {
+        QmiDirectTx(0)
+    }
+}
diff --git a/src/rp2350/xip_aux/vals.rs b/src/rp2350/xip_aux/vals.rs
new file mode 100644
index 00000000..d49136f2
--- /dev/null
+++ b/src/rp2350/xip_aux/vals.rs
@@ -0,0 +1,33 @@
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Iwidth {
+    #[doc = "Single width"]
+    S = 0,
+    #[doc = "Dual width"]
+    D = 0x01,
+    #[doc = "Quad width"]
+    Q = 0x02,
+    _RESERVED_3 = 0x03,
+}
+impl Iwidth {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Iwidth {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Iwidth {
+    #[inline(always)]
+    fn from(val: u8) -> Iwidth {
+        Iwidth::from_bits(val)
+    }
+}
+impl From<Iwidth> for u8 {
+    #[inline(always)]
+    fn from(val: Iwidth) -> u8 {
+        Iwidth::to_bits(val)
+    }
+}
diff --git a/src/rp2350/xip_ctrl.rs b/src/rp2350/xip_ctrl.rs
new file mode 100644
index 00000000..bce3a5b3
--- /dev/null
+++ b/src/rp2350/xip_ctrl.rs
@@ -0,0 +1,52 @@
+#[doc = "QSPI flash execute-in-place block"]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct XipCtrl {
+    ptr: *mut u8,
+}
+unsafe impl Send for XipCtrl {}
+unsafe impl Sync for XipCtrl {}
+impl XipCtrl {
+    #[inline(always)]
+    pub const unsafe fn from_ptr(ptr: *mut ()) -> Self {
+        Self { ptr: ptr as _ }
+    }
+    #[inline(always)]
+    pub const fn as_ptr(&self) -> *mut () {
+        self.ptr as _
+    }
+    #[doc = "Cache control register. Read-only from a Non-secure context."]
+    #[inline(always)]
+    pub const fn ctrl(self) -> crate::common::Reg<regs::Ctrl, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(0usize) as _) }
+    }
+    #[inline(always)]
+    pub const fn stat(self) -> crate::common::Reg<regs::Stat, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(8usize) as _) }
+    }
+    #[doc = "Cache Hit counter"]
+    #[inline(always)]
+    pub const fn ctr_hit(self) -> crate::common::Reg<u32, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(12usize) as _) }
+    }
+    #[doc = "Cache Access counter"]
+    #[inline(always)]
+    pub const fn ctr_acc(self) -> crate::common::Reg<u32, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(16usize) as _) }
+    }
+    #[doc = "FIFO stream address"]
+    #[inline(always)]
+    pub const fn stream_addr(self) -> crate::common::Reg<regs::StreamAddr, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(20usize) as _) }
+    }
+    #[doc = "FIFO stream control"]
+    #[inline(always)]
+    pub const fn stream_ctr(self) -> crate::common::Reg<regs::StreamCtr, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(24usize) as _) }
+    }
+    #[doc = "FIFO stream data"]
+    #[inline(always)]
+    pub const fn stream_fifo(self) -> crate::common::Reg<u32, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(28usize) as _) }
+    }
+}
+pub mod regs;
diff --git a/src/rp2350/xip_ctrl/regs.rs b/src/rp2350/xip_ctrl/regs.rs
new file mode 100644
index 00000000..07f0c822
--- /dev/null
+++ b/src/rp2350/xip_ctrl/regs.rs
@@ -0,0 +1,212 @@
+#[doc = "Cache control register. Read-only from a Non-secure context."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Ctrl(pub u32);
+impl Ctrl {
+    #[doc = "When 1, enable the cache for Secure accesses. When enabled, Secure XIP accesses to the cached (addr\\[26\\] == 0) window will query the cache, and QSPI accesses are performed only if the requested data is not present. When disabled, Secure access ignore the cache contents, and always access the QSPI interface. Accesses to the uncached (addr\\[26\\] == 1) window will never query the cache, irrespective of this bit. There is no cache-as-SRAM address window. Cache lines are allocated for SRAM-like use by individually pinning them, and keeping the cache enabled."]
+    #[inline(always)]
+    pub const fn en_secure(&self) -> bool {
+        let val = (self.0 >> 0usize) & 0x01;
+        val != 0
+    }
+    #[doc = "When 1, enable the cache for Secure accesses. When enabled, Secure XIP accesses to the cached (addr\\[26\\] == 0) window will query the cache, and QSPI accesses are performed only if the requested data is not present. When disabled, Secure access ignore the cache contents, and always access the QSPI interface. Accesses to the uncached (addr\\[26\\] == 1) window will never query the cache, irrespective of this bit. There is no cache-as-SRAM address window. Cache lines are allocated for SRAM-like use by individually pinning them, and keeping the cache enabled."]
+    #[inline(always)]
+    pub fn set_en_secure(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+    }
+    #[doc = "When 1, enable the cache for Non-secure accesses. When enabled, Non-secure XIP accesses to the cached (addr\\[26\\] == 0) window will query the cache, and QSPI accesses are performed only if the requested data is not present. When disabled, Secure access ignore the cache contents, and always access the QSPI interface. Accesses to the uncached (addr\\[26\\] == 1) window will never query the cache, irrespective of this bit."]
+    #[inline(always)]
+    pub const fn en_nonsecure(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[doc = "When 1, enable the cache for Non-secure accesses. When enabled, Non-secure XIP accesses to the cached (addr\\[26\\] == 0) window will query the cache, and QSPI accesses are performed only if the requested data is not present. When disabled, Secure access ignore the cache contents, and always access the QSPI interface. Accesses to the uncached (addr\\[26\\] == 1) window will never query the cache, irrespective of this bit."]
+    #[inline(always)]
+    pub fn set_en_nonsecure(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+    #[doc = "When 1, the cache memories are powered down. They retain state, but can not be accessed. This reduces static power dissipation. Writing 1 to this bit forces CTRL_EN_SECURE and CTRL_EN_NONSECURE to 0, i.e. the cache cannot be enabled when powered down."]
+    #[inline(always)]
+    pub const fn power_down(&self) -> bool {
+        let val = (self.0 >> 3usize) & 0x01;
+        val != 0
+    }
+    #[doc = "When 1, the cache memories are powered down. They retain state, but can not be accessed. This reduces static power dissipation. Writing 1 to this bit forces CTRL_EN_SECURE and CTRL_EN_NONSECURE to 0, i.e. the cache cannot be enabled when powered down."]
+    #[inline(always)]
+    pub fn set_power_down(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
+    }
+    #[doc = "When 1, Secure accesses to the uncached window (addr\\[27:26\\] == 1) will generate a bus error. This may reduce the number of SAU/MPU/PMP regions required to protect flash contents. Note this does not disable access to the uncached, untranslated window -- see NO_UNTRANSLATED_SEC."]
+    #[inline(always)]
+    pub const fn no_uncached_sec(&self) -> bool {
+        let val = (self.0 >> 4usize) & 0x01;
+        val != 0
+    }
+    #[doc = "When 1, Secure accesses to the uncached window (addr\\[27:26\\] == 1) will generate a bus error. This may reduce the number of SAU/MPU/PMP regions required to protect flash contents. Note this does not disable access to the uncached, untranslated window -- see NO_UNTRANSLATED_SEC."]
+    #[inline(always)]
+    pub fn set_no_uncached_sec(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
+    }
+    #[doc = "When 1, Non-secure accesses to the uncached window (addr\\[27:26\\] == 1) will generate a bus error. This may reduce the number of SAU/MPU/PMP regions required to protect flash contents. Note this does not disable access to the uncached, untranslated window -- see NO_UNTRANSLATED_SEC."]
+    #[inline(always)]
+    pub const fn no_uncached_nonsec(&self) -> bool {
+        let val = (self.0 >> 5usize) & 0x01;
+        val != 0
+    }
+    #[doc = "When 1, Non-secure accesses to the uncached window (addr\\[27:26\\] == 1) will generate a bus error. This may reduce the number of SAU/MPU/PMP regions required to protect flash contents. Note this does not disable access to the uncached, untranslated window -- see NO_UNTRANSLATED_SEC."]
+    #[inline(always)]
+    pub fn set_no_uncached_nonsec(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
+    }
+    #[doc = "When 1, Secure accesses to the uncached, untranslated window (addr\\[27:26\\] == 3) will generate a bus error."]
+    #[inline(always)]
+    pub const fn no_untranslated_sec(&self) -> bool {
+        let val = (self.0 >> 6usize) & 0x01;
+        val != 0
+    }
+    #[doc = "When 1, Secure accesses to the uncached, untranslated window (addr\\[27:26\\] == 3) will generate a bus error."]
+    #[inline(always)]
+    pub fn set_no_untranslated_sec(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
+    }
+    #[doc = "When 1, Non-secure accesses to the uncached, untranslated window (addr\\[27:26\\] == 3) will generate a bus error."]
+    #[inline(always)]
+    pub const fn no_untranslated_nonsec(&self) -> bool {
+        let val = (self.0 >> 7usize) & 0x01;
+        val != 0
+    }
+    #[doc = "When 1, Non-secure accesses to the uncached, untranslated window (addr\\[27:26\\] == 3) will generate a bus error."]
+    #[inline(always)]
+    pub fn set_no_untranslated_nonsec(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
+    }
+    #[doc = "When 0, Non-secure accesses to the cache maintenance address window (addr\\[27\\] == 1, addr\\[26\\] == 0) will generate a bus error. When 1, Non-secure accesses can perform cache maintenance operations by writing to the cache maintenance address window. Cache maintenance operations may be used to corrupt Secure data by invalidating cache lines inappropriately, or map Secure content into a Non-secure region by pinning cache lines. Therefore this bit should generally be set to 0, unless Secure code is not using the cache. Care should also be taken to clear the cache data memory and tag memory before granting maintenance operations to Non-secure code."]
+    #[inline(always)]
+    pub const fn maint_nonsec(&self) -> bool {
+        let val = (self.0 >> 8usize) & 0x01;
+        val != 0
+    }
+    #[doc = "When 0, Non-secure accesses to the cache maintenance address window (addr\\[27\\] == 1, addr\\[26\\] == 0) will generate a bus error. When 1, Non-secure accesses can perform cache maintenance operations by writing to the cache maintenance address window. Cache maintenance operations may be used to corrupt Secure data by invalidating cache lines inappropriately, or map Secure content into a Non-secure region by pinning cache lines. Therefore this bit should generally be set to 0, unless Secure code is not using the cache. Care should also be taken to clear the cache data memory and tag memory before granting maintenance operations to Non-secure code."]
+    #[inline(always)]
+    pub fn set_maint_nonsec(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
+    }
+    #[doc = "When 1, route all cached+Secure accesses to way 0 of the cache, and route all cached+Non-secure accesses to way 1 of the cache. This partitions the cache into two half-sized direct-mapped regions, such that Non-secure code can not observe cache line state changes caused by Secure execution. A full cache flush is required when changing the value of SPLIT_WAYS. The flush should be performed whilst SPLIT_WAYS is 0, so that both cache ways are accessible for invalidation."]
+    #[inline(always)]
+    pub const fn split_ways(&self) -> bool {
+        let val = (self.0 >> 9usize) & 0x01;
+        val != 0
+    }
+    #[doc = "When 1, route all cached+Secure accesses to way 0 of the cache, and route all cached+Non-secure accesses to way 1 of the cache. This partitions the cache into two half-sized direct-mapped regions, such that Non-secure code can not observe cache line state changes caused by Secure execution. A full cache flush is required when changing the value of SPLIT_WAYS. The flush should be performed whilst SPLIT_WAYS is 0, so that both cache ways are accessible for invalidation."]
+    #[inline(always)]
+    pub fn set_split_ways(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
+    }
+    #[doc = "If 1, enable writes to XIP memory window 0 (addresses 0x10000000 through 0x10ffffff, and their uncached mirrors). If 0, this region is read-only. XIP memory is *read-only by default*. This bit must be set to enable writes if a RAM device is attached on QSPI chip select 0. The default read-only behaviour avoids two issues with writing to a read-only QSPI device (e.g. flash). First, a write will initially appear to succeed due to caching, but the data will eventually be lost when the written line is evicted, causing unpredictable behaviour. Second, when a written line is evicted, it will cause a write command to be issued to the flash, which can break the flash out of its continuous read mode. After this point, flash reads will return garbage. This is a security concern, as it allows Non-secure software to break Secure flash reads if it has permission to write to any flash address. Note the read-only behaviour is implemented by downgrading writes to reads, so writes will still cause allocation of an address, but have no other effect."]
+    #[inline(always)]
+    pub const fn writable_m0(&self) -> bool {
+        let val = (self.0 >> 10usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, enable writes to XIP memory window 0 (addresses 0x10000000 through 0x10ffffff, and their uncached mirrors). If 0, this region is read-only. XIP memory is *read-only by default*. This bit must be set to enable writes if a RAM device is attached on QSPI chip select 0. The default read-only behaviour avoids two issues with writing to a read-only QSPI device (e.g. flash). First, a write will initially appear to succeed due to caching, but the data will eventually be lost when the written line is evicted, causing unpredictable behaviour. Second, when a written line is evicted, it will cause a write command to be issued to the flash, which can break the flash out of its continuous read mode. After this point, flash reads will return garbage. This is a security concern, as it allows Non-secure software to break Secure flash reads if it has permission to write to any flash address. Note the read-only behaviour is implemented by downgrading writes to reads, so writes will still cause allocation of an address, but have no other effect."]
+    #[inline(always)]
+    pub fn set_writable_m0(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize);
+    }
+    #[doc = "If 1, enable writes to XIP memory window 1 (addresses 0x11000000 through 0x11ffffff, and their uncached mirrors). If 0, this region is read-only. XIP memory is *read-only by default*. This bit must be set to enable writes if a RAM device is attached on QSPI chip select 1. The default read-only behaviour avoids two issues with writing to a read-only QSPI device (e.g. flash). First, a write will initially appear to succeed due to caching, but the data will eventually be lost when the written line is evicted, causing unpredictable behaviour. Second, when a written line is evicted, it will cause a write command to be issued to the flash, which can break the flash out of its continuous read mode. After this point, flash reads will return garbage. This is a security concern, as it allows Non-secure software to break Secure flash reads if it has permission to write to any flash address. Note the read-only behaviour is implemented by downgrading writes to reads, so writes will still cause allocation of an address, but have no other effect."]
+    #[inline(always)]
+    pub const fn writable_m1(&self) -> bool {
+        let val = (self.0 >> 11usize) & 0x01;
+        val != 0
+    }
+    #[doc = "If 1, enable writes to XIP memory window 1 (addresses 0x11000000 through 0x11ffffff, and their uncached mirrors). If 0, this region is read-only. XIP memory is *read-only by default*. This bit must be set to enable writes if a RAM device is attached on QSPI chip select 1. The default read-only behaviour avoids two issues with writing to a read-only QSPI device (e.g. flash). First, a write will initially appear to succeed due to caching, but the data will eventually be lost when the written line is evicted, causing unpredictable behaviour. Second, when a written line is evicted, it will cause a write command to be issued to the flash, which can break the flash out of its continuous read mode. After this point, flash reads will return garbage. This is a security concern, as it allows Non-secure software to break Secure flash reads if it has permission to write to any flash address. Note the read-only behaviour is implemented by downgrading writes to reads, so writes will still cause allocation of an address, but have no other effect."]
+    #[inline(always)]
+    pub fn set_writable_m1(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
+    }
+}
+impl Default for Ctrl {
+    #[inline(always)]
+    fn default() -> Ctrl {
+        Ctrl(0)
+    }
+}
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Stat(pub u32);
+impl Stat {
+    #[doc = "When 1, indicates the XIP streaming FIFO is completely empty."]
+    #[inline(always)]
+    pub const fn fifo_empty(&self) -> bool {
+        let val = (self.0 >> 1usize) & 0x01;
+        val != 0
+    }
+    #[doc = "When 1, indicates the XIP streaming FIFO is completely empty."]
+    #[inline(always)]
+    pub fn set_fifo_empty(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+    }
+    #[doc = "When 1, indicates the XIP streaming FIFO is completely full. The streaming FIFO is 2 entries deep, so the full and empty flag allow its level to be ascertained."]
+    #[inline(always)]
+    pub const fn fifo_full(&self) -> bool {
+        let val = (self.0 >> 2usize) & 0x01;
+        val != 0
+    }
+    #[doc = "When 1, indicates the XIP streaming FIFO is completely full. The streaming FIFO is 2 entries deep, so the full and empty flag allow its level to be ascertained."]
+    #[inline(always)]
+    pub fn set_fifo_full(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+    }
+}
+impl Default for Stat {
+    #[inline(always)]
+    fn default() -> Stat {
+        Stat(0)
+    }
+}
+#[doc = "FIFO stream address"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct StreamAddr(pub u32);
+impl StreamAddr {
+    #[doc = "The address of the next word to be streamed from flash to the streaming FIFO. Increments automatically after each flash access. Write the initial access address here before starting a streaming read."]
+    #[inline(always)]
+    pub const fn stream_addr(&self) -> u32 {
+        let val = (self.0 >> 2usize) & 0x3fff_ffff;
+        val as u32
+    }
+    #[doc = "The address of the next word to be streamed from flash to the streaming FIFO. Increments automatically after each flash access. Write the initial access address here before starting a streaming read."]
+    #[inline(always)]
+    pub fn set_stream_addr(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x3fff_ffff << 2usize)) | (((val as u32) & 0x3fff_ffff) << 2usize);
+    }
+}
+impl Default for StreamAddr {
+    #[inline(always)]
+    fn default() -> StreamAddr {
+        StreamAddr(0)
+    }
+}
+#[doc = "FIFO stream control"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct StreamCtr(pub u32);
+impl StreamCtr {
+    #[doc = "Write a nonzero value to start a streaming read. This will then progress in the background, using flash idle cycles to transfer a linear data block from flash to the streaming FIFO. Decrements automatically (1 at a time) as the stream progresses, and halts on reaching 0. Write 0 to halt an in-progress stream, and discard any in-flight read, so that a new stream can immediately be started (after draining the FIFO and reinitialising STREAM_ADDR)"]
+    #[inline(always)]
+    pub const fn stream_ctr(&self) -> u32 {
+        let val = (self.0 >> 0usize) & 0x003f_ffff;
+        val as u32
+    }
+    #[doc = "Write a nonzero value to start a streaming read. This will then progress in the background, using flash idle cycles to transfer a linear data block from flash to the streaming FIFO. Decrements automatically (1 at a time) as the stream progresses, and halts on reaching 0. Write 0 to halt an in-progress stream, and discard any in-flight read, so that a new stream can immediately be started (after draining the FIFO and reinitialising STREAM_ADDR)"]
+    #[inline(always)]
+    pub fn set_stream_ctr(&mut self, val: u32) {
+        self.0 = (self.0 & !(0x003f_ffff << 0usize)) | (((val as u32) & 0x003f_ffff) << 0usize);
+    }
+}
+impl Default for StreamCtr {
+    #[inline(always)]
+    fn default() -> StreamCtr {
+        StreamCtr(0)
+    }
+}
diff --git a/src/rp2350/xosc.rs b/src/rp2350/xosc.rs
new file mode 100644
index 00000000..95054801
--- /dev/null
+++ b/src/rp2350/xosc.rs
@@ -0,0 +1,44 @@
+#[doc = "Controls the crystal oscillator"]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Xosc {
+    ptr: *mut u8,
+}
+unsafe impl Send for Xosc {}
+unsafe impl Sync for Xosc {}
+impl Xosc {
+    #[inline(always)]
+    pub const unsafe fn from_ptr(ptr: *mut ()) -> Self {
+        Self { ptr: ptr as _ }
+    }
+    #[inline(always)]
+    pub const fn as_ptr(&self) -> *mut () {
+        self.ptr as _
+    }
+    #[doc = "Crystal Oscillator Control"]
+    #[inline(always)]
+    pub const fn ctrl(self) -> crate::common::Reg<regs::Ctrl, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(0usize) as _) }
+    }
+    #[doc = "Crystal Oscillator Status"]
+    #[inline(always)]
+    pub const fn status(self) -> crate::common::Reg<regs::Status, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(4usize) as _) }
+    }
+    #[doc = "Crystal Oscillator pause control"]
+    #[inline(always)]
+    pub const fn dormant(self) -> crate::common::Reg<regs::Dormant, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(8usize) as _) }
+    }
+    #[doc = "Controls the startup delay"]
+    #[inline(always)]
+    pub const fn startup(self) -> crate::common::Reg<regs::Startup, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(12usize) as _) }
+    }
+    #[doc = "A down counter running at the xosc frequency which counts to zero and stops. Can be used for short software pauses when setting up time sensitive hardware. To start the counter, write a non-zero value. Reads will return 1 while the count is running and 0 when it has finished. Minimum count value is 4. Count values <4 will be treated as count value =4. Note that synchronisation to the register clock domain costs 2 register clock cycles and the counter cannot compensate for that."]
+    #[inline(always)]
+    pub const fn count(self) -> crate::common::Reg<regs::Count, crate::common::RW> {
+        unsafe { crate::common::Reg::from_ptr(self.ptr.add(16usize) as _) }
+    }
+}
+pub mod regs;
+pub mod vals;
diff --git a/src/rp2350/xosc/regs.rs b/src/rp2350/xosc/regs.rs
new file mode 100644
index 00000000..8d2cd482
--- /dev/null
+++ b/src/rp2350/xosc/regs.rs
@@ -0,0 +1,169 @@
+#[doc = "A down counter running at the xosc frequency which counts to zero and stops. Can be used for short software pauses when setting up time sensitive hardware. To start the counter, write a non-zero value. Reads will return 1 while the count is running and 0 when it has finished. Minimum count value is 4. Count values <4 will be treated as count value =4. Note that synchronisation to the register clock domain costs 2 register clock cycles and the counter cannot compensate for that."]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Count(pub u32);
+impl Count {
+    #[inline(always)]
+    pub const fn count(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0xffff;
+        val as u16
+    }
+    #[inline(always)]
+    pub fn set_count(&mut self, val: u16) {
+        self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+    }
+}
+impl Default for Count {
+    #[inline(always)]
+    fn default() -> Count {
+        Count(0)
+    }
+}
+#[doc = "Crystal Oscillator Control"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Ctrl(pub u32);
+impl Ctrl {
+    #[doc = "The 12-bit code is intended to give some protection against accidental writes. An invalid setting will retain the previous value. The actual value being used can be read from STATUS_FREQ_RANGE"]
+    #[inline(always)]
+    pub const fn freq_range(&self) -> super::vals::CtrlFreqRange {
+        let val = (self.0 >> 0usize) & 0x0fff;
+        super::vals::CtrlFreqRange::from_bits(val as u16)
+    }
+    #[doc = "The 12-bit code is intended to give some protection against accidental writes. An invalid setting will retain the previous value. The actual value being used can be read from STATUS_FREQ_RANGE"]
+    #[inline(always)]
+    pub fn set_freq_range(&mut self, val: super::vals::CtrlFreqRange) {
+        self.0 = (self.0 & !(0x0fff << 0usize)) | (((val.to_bits() as u32) & 0x0fff) << 0usize);
+    }
+    #[doc = "On power-up this field is initialised to DISABLE and the chip runs from the ROSC. If the chip has subsequently been programmed to run from the XOSC then setting this field to DISABLE may lock-up the chip. If this is a concern then run the clk_ref from the ROSC and enable the clk_sys RESUS feature. The 12-bit code is intended to give some protection against accidental writes. An invalid setting will retain the previous value. The actual value being used can be read from STATUS_ENABLED"]
+    #[inline(always)]
+    pub const fn enable(&self) -> super::vals::Enable {
+        let val = (self.0 >> 12usize) & 0x0fff;
+        super::vals::Enable::from_bits(val as u16)
+    }
+    #[doc = "On power-up this field is initialised to DISABLE and the chip runs from the ROSC. If the chip has subsequently been programmed to run from the XOSC then setting this field to DISABLE may lock-up the chip. If this is a concern then run the clk_ref from the ROSC and enable the clk_sys RESUS feature. The 12-bit code is intended to give some protection against accidental writes. An invalid setting will retain the previous value. The actual value being used can be read from STATUS_ENABLED"]
+    #[inline(always)]
+    pub fn set_enable(&mut self, val: super::vals::Enable) {
+        self.0 = (self.0 & !(0x0fff << 12usize)) | (((val.to_bits() as u32) & 0x0fff) << 12usize);
+    }
+}
+impl Default for Ctrl {
+    #[inline(always)]
+    fn default() -> Ctrl {
+        Ctrl(0)
+    }
+}
+#[doc = "Crystal Oscillator pause control"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Dormant(pub u32);
+impl Dormant {
+    #[doc = "This is used to save power by pausing the XOSC On power-up this field is initialised to WAKE An invalid write will also select WAKE Warning: stop the PLLs before selecting dormant mode Warning: setup the irq before selecting dormant mode"]
+    #[inline(always)]
+    pub const fn dormant(&self) -> super::vals::Dormant {
+        let val = (self.0 >> 0usize) & 0xffff_ffff;
+        super::vals::Dormant::from_bits(val as u32)
+    }
+    #[doc = "This is used to save power by pausing the XOSC On power-up this field is initialised to WAKE An invalid write will also select WAKE Warning: stop the PLLs before selecting dormant mode Warning: setup the irq before selecting dormant mode"]
+    #[inline(always)]
+    pub fn set_dormant(&mut self, val: super::vals::Dormant) {
+        self.0 = (self.0 & !(0xffff_ffff << 0usize))
+            | (((val.to_bits() as u32) & 0xffff_ffff) << 0usize);
+    }
+}
+impl Default for Dormant {
+    #[inline(always)]
+    fn default() -> Dormant {
+        Dormant(0)
+    }
+}
+#[doc = "Controls the startup delay"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Startup(pub u32);
+impl Startup {
+    #[doc = "in multiples of 256*xtal_period. The reset value of 0xc4 corresponds to approx 50 000 cycles."]
+    #[inline(always)]
+    pub const fn delay(&self) -> u16 {
+        let val = (self.0 >> 0usize) & 0x3fff;
+        val as u16
+    }
+    #[doc = "in multiples of 256*xtal_period. The reset value of 0xc4 corresponds to approx 50 000 cycles."]
+    #[inline(always)]
+    pub fn set_delay(&mut self, val: u16) {
+        self.0 = (self.0 & !(0x3fff << 0usize)) | (((val as u32) & 0x3fff) << 0usize);
+    }
+    #[doc = "Multiplies the startup_delay by 4, just in case. The reset value is controlled by a mask-programmable tiecell and is provided in case we are booting from XOSC and the default startup delay is insufficient. The reset value is 0x0."]
+    #[inline(always)]
+    pub const fn x4(&self) -> bool {
+        let val = (self.0 >> 20usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Multiplies the startup_delay by 4, just in case. The reset value is controlled by a mask-programmable tiecell and is provided in case we are booting from XOSC and the default startup delay is insufficient. The reset value is 0x0."]
+    #[inline(always)]
+    pub fn set_x4(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize);
+    }
+}
+impl Default for Startup {
+    #[inline(always)]
+    fn default() -> Startup {
+        Startup(0)
+    }
+}
+#[doc = "Crystal Oscillator Status"]
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq)]
+pub struct Status(pub u32);
+impl Status {
+    #[doc = "The current frequency range setting"]
+    #[inline(always)]
+    pub const fn freq_range(&self) -> super::vals::StatusFreqRange {
+        let val = (self.0 >> 0usize) & 0x03;
+        super::vals::StatusFreqRange::from_bits(val as u8)
+    }
+    #[doc = "The current frequency range setting"]
+    #[inline(always)]
+    pub fn set_freq_range(&mut self, val: super::vals::StatusFreqRange) {
+        self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize);
+    }
+    #[doc = "Oscillator is enabled but not necessarily running and stable, resets to 0"]
+    #[inline(always)]
+    pub const fn enabled(&self) -> bool {
+        let val = (self.0 >> 12usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Oscillator is enabled but not necessarily running and stable, resets to 0"]
+    #[inline(always)]
+    pub fn set_enabled(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
+    }
+    #[doc = "An invalid value has been written to CTRL_ENABLE or CTRL_FREQ_RANGE or DORMANT"]
+    #[inline(always)]
+    pub const fn badwrite(&self) -> bool {
+        let val = (self.0 >> 24usize) & 0x01;
+        val != 0
+    }
+    #[doc = "An invalid value has been written to CTRL_ENABLE or CTRL_FREQ_RANGE or DORMANT"]
+    #[inline(always)]
+    pub fn set_badwrite(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 24usize)) | (((val as u32) & 0x01) << 24usize);
+    }
+    #[doc = "Oscillator is running and stable"]
+    #[inline(always)]
+    pub const fn stable(&self) -> bool {
+        let val = (self.0 >> 31usize) & 0x01;
+        val != 0
+    }
+    #[doc = "Oscillator is running and stable"]
+    #[inline(always)]
+    pub fn set_stable(&mut self, val: bool) {
+        self.0 = (self.0 & !(0x01 << 31usize)) | (((val as u32) & 0x01) << 31usize);
+    }
+}
+impl Default for Status {
+    #[inline(always)]
+    fn default() -> Status {
+        Status(0)
+    }
+}
diff --git a/src/rp2350/xosc/vals.rs b/src/rp2350/xosc/vals.rs
new file mode 100644
index 00000000..06a57082
--- /dev/null
+++ b/src/rp2350/xosc/vals.rs
@@ -0,0 +1,113 @@
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub struct CtrlFreqRange(pub u16);
+impl CtrlFreqRange {
+    pub const _1_15MHZ: Self = Self(0x0aa0);
+    pub const _10_30MHZ: Self = Self(0x0aa1);
+    pub const _25_60MHZ: Self = Self(0x0aa2);
+    pub const _40_100MHZ: Self = Self(0x0aa3);
+}
+impl CtrlFreqRange {
+    pub const fn from_bits(val: u16) -> CtrlFreqRange {
+        Self(val & 0x0fff)
+    }
+    pub const fn to_bits(self) -> u16 {
+        self.0
+    }
+}
+impl From<u16> for CtrlFreqRange {
+    #[inline(always)]
+    fn from(val: u16) -> CtrlFreqRange {
+        CtrlFreqRange::from_bits(val)
+    }
+}
+impl From<CtrlFreqRange> for u16 {
+    #[inline(always)]
+    fn from(val: CtrlFreqRange) -> u16 {
+        CtrlFreqRange::to_bits(val)
+    }
+}
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub struct Dormant(pub u32);
+impl Dormant {
+    pub const DORMANT: Self = Self(0x636f_6d61);
+    pub const WAKE: Self = Self(0x7761_6b65);
+}
+impl Dormant {
+    pub const fn from_bits(val: u32) -> Dormant {
+        Self(val & 0xffff_ffff)
+    }
+    pub const fn to_bits(self) -> u32 {
+        self.0
+    }
+}
+impl From<u32> for Dormant {
+    #[inline(always)]
+    fn from(val: u32) -> Dormant {
+        Dormant::from_bits(val)
+    }
+}
+impl From<Dormant> for u32 {
+    #[inline(always)]
+    fn from(val: Dormant) -> u32 {
+        Dormant::to_bits(val)
+    }
+}
+#[repr(transparent)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub struct Enable(pub u16);
+impl Enable {
+    pub const DISABLE: Self = Self(0x0d1e);
+    pub const ENABLE: Self = Self(0x0fab);
+}
+impl Enable {
+    pub const fn from_bits(val: u16) -> Enable {
+        Self(val & 0x0fff)
+    }
+    pub const fn to_bits(self) -> u16 {
+        self.0
+    }
+}
+impl From<u16> for Enable {
+    #[inline(always)]
+    fn from(val: u16) -> Enable {
+        Enable::from_bits(val)
+    }
+}
+impl From<Enable> for u16 {
+    #[inline(always)]
+    fn from(val: Enable) -> u16 {
+        Enable::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum StatusFreqRange {
+    _1_15MHZ = 0,
+    _10_30MHZ = 0x01,
+    _25_60MHZ = 0x02,
+    _40_100MHZ = 0x03,
+}
+impl StatusFreqRange {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> StatusFreqRange {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for StatusFreqRange {
+    #[inline(always)]
+    fn from(val: u8) -> StatusFreqRange {
+        StatusFreqRange::from_bits(val)
+    }
+}
+impl From<StatusFreqRange> for u8 {
+    #[inline(always)]
+    fn from(val: StatusFreqRange) -> u8 {
+        StatusFreqRange::to_bits(val)
+    }
+}
diff --git a/svd/RP2040.svd b/svd/RP2040.svd
new file mode 100644
index 00000000..454f4890
--- /dev/null
+++ b/svd/RP2040.svd
@@ -0,0 +1,51055 @@
+<?xml version="1.0" encoding="utf-8"?>
+<!--
+Copyright (c) 2024 Raspberry Pi Ltd.
+
+SPDX-License-Identifier: BSD-3-Clause
+-->
+<device schemaVersion="1.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD.xsd">
+    <vendor>Raspberry Pi</vendor>
+    <name>RP2040</name>
+    <series>RP</series>
+    <version>0.1</version>
+    <description>
+        Dual-core Arm Cortex-M0+ processor, flexible clock running up to 133 MHz
+        264KB on-chip SRAM
+        2 x UART, 2 x SPI controllers, 2 x I2C controllers, 16 x PWM channels
+        1 x USB 1.1 controller and PHY, with host and device support
+        8 x Programmable I/O (PIO) state machines for custom peripheral support
+        Supported input power 1.8-5.5V DC
+        Operating temperature -20C to +85C
+        Drag-and-drop programming using mass storage over USB
+        Low-power sleep and dormant modes
+        Accurate on-chip clock
+        Temperature sensor
+        Accelerated integer and floating-point libraries on-chip
+    </description>
+    <width>32</width>
+    <size>32</size>
+    <resetMask>0xffffffff</resetMask>
+    <resetValue>0x00000000</resetValue>
+    <access>read-write</access>
+    <licenseText>
+        Copyright (c) 2024 Raspberry Pi Ltd.
+
+        SPDX-License-Identifier: BSD-3-Clause
+    </licenseText>
+    <cpu>
+        <name>CM0PLUS</name>
+        <revision>r0p1</revision>
+        <endian>little</endian>
+        <mpuPresent>true</mpuPresent>
+        <fpuPresent>false</fpuPresent>
+        <vtorPresent>1</vtorPresent>
+        <nvicPrioBits>2</nvicPrioBits>
+        <vendorSystickConfig>false</vendorSystickConfig>
+        <deviceNumInterrupts>26</deviceNumInterrupts>
+    </cpu>
+    <addressUnitBits>8</addressUnitBits>
+    <peripherals>
+    <peripheral>
+        <name>RESETS</name>
+        <baseAddress>0x4000c000</baseAddress>
+        <addressBlock>
+            <offset>0</offset>
+            <size>12</size>
+            <usage>registers</usage>
+        </addressBlock>
+        <registers>
+            <register>
+                <name>RESET</name>
+                <addressOffset>0x00000000</addressOffset>
+                <description>Reset control. If a bit is set it means the peripheral is in reset. 0 means the peripheral&#39;s reset is deasserted.</description>
+                <resetValue>0x01ffffff</resetValue>
+                <fields>
+                    <field>
+                        <name>USBCTRL</name>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>UART1</name>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>UART0</name>
+                        <bitRange>[22:22]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>TIMER</name>
+                        <bitRange>[21:21]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>TBMAN</name>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SYSINFO</name>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SYSCFG</name>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SPI1</name>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SPI0</name>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>RTC</name>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PWM</name>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PLL_USB</name>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PLL_SYS</name>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PIO1</name>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PIO0</name>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PADS_QSPI</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PADS_BANK0</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>JTAG</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>IO_QSPI</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>IO_BANK0</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>I2C1</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>I2C0</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DMA</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>BUSCTRL</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ADC</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>WDSEL</name>
+                <addressOffset>0x00000004</addressOffset>
+                <description>Watchdog select. If a bit is set then the watchdog will reset this peripheral when the watchdog fires.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>USBCTRL</name>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>UART1</name>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>UART0</name>
+                        <bitRange>[22:22]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>TIMER</name>
+                        <bitRange>[21:21]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>TBMAN</name>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SYSINFO</name>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SYSCFG</name>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SPI1</name>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SPI0</name>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>RTC</name>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PWM</name>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PLL_USB</name>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PLL_SYS</name>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PIO1</name>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PIO0</name>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PADS_QSPI</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PADS_BANK0</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>JTAG</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>IO_QSPI</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>IO_BANK0</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>I2C1</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>I2C0</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DMA</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>BUSCTRL</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ADC</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>RESET_DONE</name>
+                <addressOffset>0x00000008</addressOffset>
+                <description>Reset done. If a bit is set then a reset done signal has been returned by the peripheral. This indicates that the peripheral&#39;s registers are ready to be accessed.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>USBCTRL</name>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>UART1</name>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>UART0</name>
+                        <bitRange>[22:22]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>TIMER</name>
+                        <bitRange>[21:21]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>TBMAN</name>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SYSINFO</name>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SYSCFG</name>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SPI1</name>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SPI0</name>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>RTC</name>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>PWM</name>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>PLL_USB</name>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>PLL_SYS</name>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>PIO1</name>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>PIO0</name>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>PADS_QSPI</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>PADS_BANK0</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>JTAG</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>IO_QSPI</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>IO_BANK0</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>I2C1</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>I2C0</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>DMA</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>BUSCTRL</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>ADC</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+        </registers>
+    </peripheral>
+    <peripheral>
+        <name>PSM</name>
+        <baseAddress>0x40010000</baseAddress>
+        <addressBlock>
+            <offset>0</offset>
+            <size>16</size>
+            <usage>registers</usage>
+        </addressBlock>
+        <registers>
+            <register>
+                <name>FRCE_ON</name>
+                <addressOffset>0x00000000</addressOffset>
+                <description>Force block out of reset (i.e. power it on)</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>PROC1</name>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PROC0</name>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SIO</name>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>VREG_AND_CHIP_RESET</name>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>XIP</name>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SRAM5</name>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SRAM4</name>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SRAM3</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SRAM2</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SRAM1</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SRAM0</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ROM</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>BUSFABRIC</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>RESETS</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLOCKS</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>XOSC</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ROSC</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>FRCE_OFF</name>
+                <addressOffset>0x00000004</addressOffset>
+                <description>Force into reset (i.e. power it off)</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>PROC1</name>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PROC0</name>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SIO</name>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>VREG_AND_CHIP_RESET</name>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>XIP</name>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SRAM5</name>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SRAM4</name>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SRAM3</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SRAM2</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SRAM1</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SRAM0</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ROM</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>BUSFABRIC</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>RESETS</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLOCKS</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>XOSC</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ROSC</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>WDSEL</name>
+                <addressOffset>0x00000008</addressOffset>
+                <description>Set to 1 if this peripheral should be reset when the watchdog fires.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>PROC1</name>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PROC0</name>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SIO</name>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>VREG_AND_CHIP_RESET</name>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>XIP</name>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SRAM5</name>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SRAM4</name>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SRAM3</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SRAM2</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SRAM1</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SRAM0</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ROM</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>BUSFABRIC</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>RESETS</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLOCKS</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>XOSC</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ROSC</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>DONE</name>
+                <addressOffset>0x0000000c</addressOffset>
+                <description>Indicates the peripheral&#39;s registers are ready to access.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>PROC1</name>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>PROC0</name>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SIO</name>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>VREG_AND_CHIP_RESET</name>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>XIP</name>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SRAM5</name>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SRAM4</name>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SRAM3</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SRAM2</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SRAM1</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SRAM0</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>ROM</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>BUSFABRIC</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>RESETS</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CLOCKS</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>XOSC</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>ROSC</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+        </registers>
+    </peripheral>
+    <peripheral>
+        <name>CLOCKS</name>
+        <baseAddress>0x40008000</baseAddress>
+        <addressBlock>
+            <offset>0</offset>
+            <size>200</size>
+            <usage>registers</usage>
+        </addressBlock>
+        <interrupt>
+            <name>CLOCKS_IRQ</name>
+            <value>17</value>
+        </interrupt>
+        <registers>
+            <register>
+                <name>CLK_GPOUT0_CTRL</name>
+                <addressOffset>0x00000000</addressOffset>
+                <description>Clock control, can be changed on-the-fly (except for auxsrc)</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>NUDGE</name>
+                        <description>An edge on this signal shifts the phase of the output by 1 cycle of the input clock 
+                            This can be done at any time</description>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PHASE</name>
+                        <description>This delays the enable signal by up to 3 cycles of the input clock 
+                            This must be set before the clock is enabled to have any effect</description>
+                        <bitRange>[17:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DC50</name>
+                        <description>Enables duty cycle correction for odd divisors</description>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ENABLE</name>
+                        <description>Starts and stops the clock generator cleanly</description>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>KILL</name>
+                        <description>Asynchronously kills the clock generator</description>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>AUXSRC</name>
+                        <description>Selects the auxiliary clock source, will glitch when switching</description>
+                        <bitRange>[8:5]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>clksrc_pll_sys</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>clksrc_gpin0</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>clksrc_gpin1</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>clksrc_pll_usb</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>rosc_clksrc</name>
+                                <value>4</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>xosc_clksrc</name>
+                                <value>5</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>clk_sys</name>
+                                <value>6</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>clk_usb</name>
+                                <value>7</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>clk_adc</name>
+                                <value>8</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>clk_rtc</name>
+                                <value>9</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>clk_ref</name>
+                                <value>10</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CLK_GPOUT0_DIV</name>
+                <addressOffset>0x00000004</addressOffset>
+                <description>Clock divisor, can be changed on-the-fly</description>
+                <resetValue>0x00000100</resetValue>
+                <fields>
+                    <field>
+                        <name>INT</name>
+                        <description>Integer component of the divisor, 0 -&gt; divide by 2^16</description>
+                        <bitRange>[31:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>FRAC</name>
+                        <description>Fractional component of the divisor</description>
+                        <bitRange>[7:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CLK_GPOUT0_SELECTED</name>
+                <addressOffset>0x00000008</addressOffset>
+                <description>Indicates which SRC is currently selected by the glitchless mux (one-hot).</description>
+                <resetValue>0x00000001</resetValue>
+                <fields>
+                    <field>
+                        <name>CLK_GPOUT0_SELECTED</name>
+                        <description>This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1.</description>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CLK_GPOUT1_CTRL</name>
+                <addressOffset>0x0000000c</addressOffset>
+                <description>Clock control, can be changed on-the-fly (except for auxsrc)</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>NUDGE</name>
+                        <description>An edge on this signal shifts the phase of the output by 1 cycle of the input clock 
+                            This can be done at any time</description>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PHASE</name>
+                        <description>This delays the enable signal by up to 3 cycles of the input clock 
+                            This must be set before the clock is enabled to have any effect</description>
+                        <bitRange>[17:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DC50</name>
+                        <description>Enables duty cycle correction for odd divisors</description>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ENABLE</name>
+                        <description>Starts and stops the clock generator cleanly</description>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>KILL</name>
+                        <description>Asynchronously kills the clock generator</description>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>AUXSRC</name>
+                        <description>Selects the auxiliary clock source, will glitch when switching</description>
+                        <bitRange>[8:5]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>clksrc_pll_sys</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>clksrc_gpin0</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>clksrc_gpin1</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>clksrc_pll_usb</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>rosc_clksrc</name>
+                                <value>4</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>xosc_clksrc</name>
+                                <value>5</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>clk_sys</name>
+                                <value>6</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>clk_usb</name>
+                                <value>7</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>clk_adc</name>
+                                <value>8</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>clk_rtc</name>
+                                <value>9</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>clk_ref</name>
+                                <value>10</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CLK_GPOUT1_DIV</name>
+                <addressOffset>0x00000010</addressOffset>
+                <description>Clock divisor, can be changed on-the-fly</description>
+                <resetValue>0x00000100</resetValue>
+                <fields>
+                    <field>
+                        <name>INT</name>
+                        <description>Integer component of the divisor, 0 -&gt; divide by 2^16</description>
+                        <bitRange>[31:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>FRAC</name>
+                        <description>Fractional component of the divisor</description>
+                        <bitRange>[7:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CLK_GPOUT1_SELECTED</name>
+                <addressOffset>0x00000014</addressOffset>
+                <description>Indicates which SRC is currently selected by the glitchless mux (one-hot).</description>
+                <resetValue>0x00000001</resetValue>
+                <fields>
+                    <field>
+                        <name>CLK_GPOUT1_SELECTED</name>
+                        <description>This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1.</description>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CLK_GPOUT2_CTRL</name>
+                <addressOffset>0x00000018</addressOffset>
+                <description>Clock control, can be changed on-the-fly (except for auxsrc)</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>NUDGE</name>
+                        <description>An edge on this signal shifts the phase of the output by 1 cycle of the input clock 
+                            This can be done at any time</description>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PHASE</name>
+                        <description>This delays the enable signal by up to 3 cycles of the input clock 
+                            This must be set before the clock is enabled to have any effect</description>
+                        <bitRange>[17:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DC50</name>
+                        <description>Enables duty cycle correction for odd divisors</description>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ENABLE</name>
+                        <description>Starts and stops the clock generator cleanly</description>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>KILL</name>
+                        <description>Asynchronously kills the clock generator</description>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>AUXSRC</name>
+                        <description>Selects the auxiliary clock source, will glitch when switching</description>
+                        <bitRange>[8:5]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>clksrc_pll_sys</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>clksrc_gpin0</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>clksrc_gpin1</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>clksrc_pll_usb</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>rosc_clksrc_ph</name>
+                                <value>4</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>xosc_clksrc</name>
+                                <value>5</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>clk_sys</name>
+                                <value>6</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>clk_usb</name>
+                                <value>7</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>clk_adc</name>
+                                <value>8</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>clk_rtc</name>
+                                <value>9</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>clk_ref</name>
+                                <value>10</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CLK_GPOUT2_DIV</name>
+                <addressOffset>0x0000001c</addressOffset>
+                <description>Clock divisor, can be changed on-the-fly</description>
+                <resetValue>0x00000100</resetValue>
+                <fields>
+                    <field>
+                        <name>INT</name>
+                        <description>Integer component of the divisor, 0 -&gt; divide by 2^16</description>
+                        <bitRange>[31:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>FRAC</name>
+                        <description>Fractional component of the divisor</description>
+                        <bitRange>[7:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CLK_GPOUT2_SELECTED</name>
+                <addressOffset>0x00000020</addressOffset>
+                <description>Indicates which SRC is currently selected by the glitchless mux (one-hot).</description>
+                <resetValue>0x00000001</resetValue>
+                <fields>
+                    <field>
+                        <name>CLK_GPOUT2_SELECTED</name>
+                        <description>This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1.</description>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CLK_GPOUT3_CTRL</name>
+                <addressOffset>0x00000024</addressOffset>
+                <description>Clock control, can be changed on-the-fly (except for auxsrc)</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>NUDGE</name>
+                        <description>An edge on this signal shifts the phase of the output by 1 cycle of the input clock 
+                            This can be done at any time</description>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PHASE</name>
+                        <description>This delays the enable signal by up to 3 cycles of the input clock 
+                            This must be set before the clock is enabled to have any effect</description>
+                        <bitRange>[17:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DC50</name>
+                        <description>Enables duty cycle correction for odd divisors</description>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ENABLE</name>
+                        <description>Starts and stops the clock generator cleanly</description>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>KILL</name>
+                        <description>Asynchronously kills the clock generator</description>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>AUXSRC</name>
+                        <description>Selects the auxiliary clock source, will glitch when switching</description>
+                        <bitRange>[8:5]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>clksrc_pll_sys</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>clksrc_gpin0</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>clksrc_gpin1</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>clksrc_pll_usb</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>rosc_clksrc_ph</name>
+                                <value>4</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>xosc_clksrc</name>
+                                <value>5</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>clk_sys</name>
+                                <value>6</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>clk_usb</name>
+                                <value>7</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>clk_adc</name>
+                                <value>8</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>clk_rtc</name>
+                                <value>9</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>clk_ref</name>
+                                <value>10</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CLK_GPOUT3_DIV</name>
+                <addressOffset>0x00000028</addressOffset>
+                <description>Clock divisor, can be changed on-the-fly</description>
+                <resetValue>0x00000100</resetValue>
+                <fields>
+                    <field>
+                        <name>INT</name>
+                        <description>Integer component of the divisor, 0 -&gt; divide by 2^16</description>
+                        <bitRange>[31:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>FRAC</name>
+                        <description>Fractional component of the divisor</description>
+                        <bitRange>[7:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CLK_GPOUT3_SELECTED</name>
+                <addressOffset>0x0000002c</addressOffset>
+                <description>Indicates which SRC is currently selected by the glitchless mux (one-hot).</description>
+                <resetValue>0x00000001</resetValue>
+                <fields>
+                    <field>
+                        <name>CLK_GPOUT3_SELECTED</name>
+                        <description>This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1.</description>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CLK_REF_CTRL</name>
+                <addressOffset>0x00000030</addressOffset>
+                <description>Clock control, can be changed on-the-fly (except for auxsrc)</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>AUXSRC</name>
+                        <description>Selects the auxiliary clock source, will glitch when switching</description>
+                        <bitRange>[6:5]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>clksrc_pll_usb</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>clksrc_gpin0</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>clksrc_gpin1</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>SRC</name>
+                        <description>Selects the clock source glitchlessly, can be changed on-the-fly</description>
+                        <bitRange>[1:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>rosc_clksrc_ph</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>clksrc_clk_ref_aux</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>xosc_clksrc</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CLK_REF_DIV</name>
+                <addressOffset>0x00000034</addressOffset>
+                <description>Clock divisor, can be changed on-the-fly</description>
+                <resetValue>0x00000100</resetValue>
+                <fields>
+                    <field>
+                        <name>INT</name>
+                        <description>Integer component of the divisor, 0 -&gt; divide by 2^16</description>
+                        <bitRange>[9:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CLK_REF_SELECTED</name>
+                <addressOffset>0x00000038</addressOffset>
+                <description>Indicates which SRC is currently selected by the glitchless mux (one-hot).</description>
+                <resetValue>0x00000001</resetValue>
+                <fields>
+                    <field>
+                        <name>CLK_REF_SELECTED</name>
+                        <description>The glitchless multiplexer does not switch instantaneously (to avoid glitches), so software should poll this register to wait for the switch to complete. This register contains one decoded bit for each of the clock sources enumerated in the CTRL SRC field. At most one of these bits will be set at any time, indicating that clock is currently present at the output of the glitchless mux. Whilst switching is in progress, this register may briefly show all-0s.</description>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CLK_SYS_CTRL</name>
+                <addressOffset>0x0000003c</addressOffset>
+                <description>Clock control, can be changed on-the-fly (except for auxsrc)</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>AUXSRC</name>
+                        <description>Selects the auxiliary clock source, will glitch when switching</description>
+                        <bitRange>[7:5]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>clksrc_pll_sys</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>clksrc_pll_usb</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>rosc_clksrc</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>xosc_clksrc</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>clksrc_gpin0</name>
+                                <value>4</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>clksrc_gpin1</name>
+                                <value>5</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>SRC</name>
+                        <description>Selects the clock source glitchlessly, can be changed on-the-fly</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>clk_ref</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>clksrc_clk_sys_aux</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CLK_SYS_DIV</name>
+                <addressOffset>0x00000040</addressOffset>
+                <description>Clock divisor, can be changed on-the-fly</description>
+                <resetValue>0x00000100</resetValue>
+                <fields>
+                    <field>
+                        <name>INT</name>
+                        <description>Integer component of the divisor, 0 -&gt; divide by 2^16</description>
+                        <bitRange>[31:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>FRAC</name>
+                        <description>Fractional component of the divisor</description>
+                        <bitRange>[7:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CLK_SYS_SELECTED</name>
+                <addressOffset>0x00000044</addressOffset>
+                <description>Indicates which SRC is currently selected by the glitchless mux (one-hot).</description>
+                <resetValue>0x00000001</resetValue>
+                <fields>
+                    <field>
+                        <name>CLK_SYS_SELECTED</name>
+                        <description>The glitchless multiplexer does not switch instantaneously (to avoid glitches), so software should poll this register to wait for the switch to complete. This register contains one decoded bit for each of the clock sources enumerated in the CTRL SRC field. At most one of these bits will be set at any time, indicating that clock is currently present at the output of the glitchless mux. Whilst switching is in progress, this register may briefly show all-0s.</description>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CLK_PERI_CTRL</name>
+                <addressOffset>0x00000048</addressOffset>
+                <description>Clock control, can be changed on-the-fly (except for auxsrc)</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>ENABLE</name>
+                        <description>Starts and stops the clock generator cleanly</description>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>KILL</name>
+                        <description>Asynchronously kills the clock generator</description>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>AUXSRC</name>
+                        <description>Selects the auxiliary clock source, will glitch when switching</description>
+                        <bitRange>[7:5]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>clk_sys</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>clksrc_pll_sys</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>clksrc_pll_usb</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>rosc_clksrc_ph</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>xosc_clksrc</name>
+                                <value>4</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>clksrc_gpin0</name>
+                                <value>5</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>clksrc_gpin1</name>
+                                <value>6</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CLK_PERI_DIV</name>
+                <addressOffset>0x0000004c</addressOffset>
+                <description>Clock divisor, can be changed on-the-fly</description>
+                <resetValue>0x00000100</resetValue>
+                <fields>
+                    <field>
+                        <name>INT</name>
+                        <description>Integer component of the divisor, 0 -&gt; divide by 2^16</description>
+                        <bitRange>[31:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>FRAC</name>
+                        <description>Fractional component of the divisor</description>
+                        <bitRange>[7:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CLK_PERI_SELECTED</name>
+                <addressOffset>0x00000050</addressOffset>
+                <description>Indicates which SRC is currently selected by the glitchless mux (one-hot).</description>
+                <resetValue>0x00000001</resetValue>
+                <fields>
+                    <field>
+                        <name>CLK_PERI_SELECTED</name>
+                        <description>This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1.</description>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CLK_USB_CTRL</name>
+                <addressOffset>0x00000054</addressOffset>
+                <description>Clock control, can be changed on-the-fly (except for auxsrc)</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>NUDGE</name>
+                        <description>An edge on this signal shifts the phase of the output by 1 cycle of the input clock 
+                            This can be done at any time</description>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PHASE</name>
+                        <description>This delays the enable signal by up to 3 cycles of the input clock 
+                            This must be set before the clock is enabled to have any effect</description>
+                        <bitRange>[17:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ENABLE</name>
+                        <description>Starts and stops the clock generator cleanly</description>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>KILL</name>
+                        <description>Asynchronously kills the clock generator</description>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>AUXSRC</name>
+                        <description>Selects the auxiliary clock source, will glitch when switching</description>
+                        <bitRange>[7:5]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>clksrc_pll_usb</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>clksrc_pll_sys</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>rosc_clksrc_ph</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>xosc_clksrc</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>clksrc_gpin0</name>
+                                <value>4</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>clksrc_gpin1</name>
+                                <value>5</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CLK_USB_DIV</name>
+                <addressOffset>0x00000058</addressOffset>
+                <description>Clock divisor, can be changed on-the-fly</description>
+                <resetValue>0x00000100</resetValue>
+                <fields>
+                    <field>
+                        <name>INT</name>
+                        <description>Integer component of the divisor, 0 -&gt; divide by 2^16</description>
+                        <bitRange>[9:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CLK_USB_SELECTED</name>
+                <addressOffset>0x0000005c</addressOffset>
+                <description>Indicates which SRC is currently selected by the glitchless mux (one-hot).</description>
+                <resetValue>0x00000001</resetValue>
+                <fields>
+                    <field>
+                        <name>CLK_USB_SELECTED</name>
+                        <description>This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1.</description>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CLK_ADC_CTRL</name>
+                <addressOffset>0x00000060</addressOffset>
+                <description>Clock control, can be changed on-the-fly (except for auxsrc)</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>NUDGE</name>
+                        <description>An edge on this signal shifts the phase of the output by 1 cycle of the input clock 
+                            This can be done at any time</description>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PHASE</name>
+                        <description>This delays the enable signal by up to 3 cycles of the input clock 
+                            This must be set before the clock is enabled to have any effect</description>
+                        <bitRange>[17:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ENABLE</name>
+                        <description>Starts and stops the clock generator cleanly</description>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>KILL</name>
+                        <description>Asynchronously kills the clock generator</description>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>AUXSRC</name>
+                        <description>Selects the auxiliary clock source, will glitch when switching</description>
+                        <bitRange>[7:5]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>clksrc_pll_usb</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>clksrc_pll_sys</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>rosc_clksrc_ph</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>xosc_clksrc</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>clksrc_gpin0</name>
+                                <value>4</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>clksrc_gpin1</name>
+                                <value>5</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CLK_ADC_DIV</name>
+                <addressOffset>0x00000064</addressOffset>
+                <description>Clock divisor, can be changed on-the-fly</description>
+                <resetValue>0x00000100</resetValue>
+                <fields>
+                    <field>
+                        <name>INT</name>
+                        <description>Integer component of the divisor, 0 -&gt; divide by 2^16</description>
+                        <bitRange>[9:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CLK_ADC_SELECTED</name>
+                <addressOffset>0x00000068</addressOffset>
+                <description>Indicates which SRC is currently selected by the glitchless mux (one-hot).</description>
+                <resetValue>0x00000001</resetValue>
+                <fields>
+                    <field>
+                        <name>CLK_ADC_SELECTED</name>
+                        <description>This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1.</description>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CLK_RTC_CTRL</name>
+                <addressOffset>0x0000006c</addressOffset>
+                <description>Clock control, can be changed on-the-fly (except for auxsrc)</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>NUDGE</name>
+                        <description>An edge on this signal shifts the phase of the output by 1 cycle of the input clock 
+                            This can be done at any time</description>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PHASE</name>
+                        <description>This delays the enable signal by up to 3 cycles of the input clock 
+                            This must be set before the clock is enabled to have any effect</description>
+                        <bitRange>[17:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ENABLE</name>
+                        <description>Starts and stops the clock generator cleanly</description>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>KILL</name>
+                        <description>Asynchronously kills the clock generator</description>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>AUXSRC</name>
+                        <description>Selects the auxiliary clock source, will glitch when switching</description>
+                        <bitRange>[7:5]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>clksrc_pll_usb</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>clksrc_pll_sys</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>rosc_clksrc_ph</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>xosc_clksrc</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>clksrc_gpin0</name>
+                                <value>4</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>clksrc_gpin1</name>
+                                <value>5</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CLK_RTC_DIV</name>
+                <addressOffset>0x00000070</addressOffset>
+                <description>Clock divisor, can be changed on-the-fly</description>
+                <resetValue>0x00000100</resetValue>
+                <fields>
+                    <field>
+                        <name>INT</name>
+                        <description>Integer component of the divisor, 0 -&gt; divide by 2^16</description>
+                        <bitRange>[31:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>FRAC</name>
+                        <description>Fractional component of the divisor</description>
+                        <bitRange>[7:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CLK_RTC_SELECTED</name>
+                <addressOffset>0x00000074</addressOffset>
+                <description>Indicates which SRC is currently selected by the glitchless mux (one-hot).</description>
+                <resetValue>0x00000001</resetValue>
+                <fields>
+                    <field>
+                        <name>CLK_RTC_SELECTED</name>
+                        <description>This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1.</description>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CLK_SYS_RESUS_CTRL</name>
+                <addressOffset>0x00000078</addressOffset>
+                <resetValue>0x000000ff</resetValue>
+                <fields>
+                    <field>
+                        <name>CLEAR</name>
+                        <description>For clearing the resus after the fault that triggered it has been corrected</description>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>FRCE</name>
+                        <description>Force a resus, for test purposes only</description>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ENABLE</name>
+                        <description>Enable resus</description>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>TIMEOUT</name>
+                        <description>This is expressed as a number of clk_ref cycles 
+                            and must be &gt;= 2x clk_ref_freq/min_clk_tst_freq</description>
+                        <bitRange>[7:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CLK_SYS_RESUS_STATUS</name>
+                <addressOffset>0x0000007c</addressOffset>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>RESUSSED</name>
+                        <description>Clock has been resuscitated, correct the error then send ctrl_clear=1</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>FC0_REF_KHZ</name>
+                <addressOffset>0x00000080</addressOffset>
+                <description>Reference clock frequency in kHz</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>FC0_REF_KHZ</name>
+                        <bitRange>[19:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>FC0_MIN_KHZ</name>
+                <addressOffset>0x00000084</addressOffset>
+                <description>Minimum pass frequency in kHz. This is optional. Set to 0 if you are not using the pass/fail flags</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>FC0_MIN_KHZ</name>
+                        <bitRange>[24:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>FC0_MAX_KHZ</name>
+                <addressOffset>0x00000088</addressOffset>
+                <description>Maximum pass frequency in kHz. This is optional. Set to 0x1ffffff if you are not using the pass/fail flags</description>
+                <resetValue>0x01ffffff</resetValue>
+                <fields>
+                    <field>
+                        <name>FC0_MAX_KHZ</name>
+                        <bitRange>[24:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>FC0_DELAY</name>
+                <addressOffset>0x0000008c</addressOffset>
+                <description>Delays the start of frequency counting to allow the mux to settle 
+                    Delay is measured in multiples of the reference clock period</description>
+                <resetValue>0x00000001</resetValue>
+                <fields>
+                    <field>
+                        <name>FC0_DELAY</name>
+                        <bitRange>[2:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>FC0_INTERVAL</name>
+                <addressOffset>0x00000090</addressOffset>
+                <description>The test interval is 0.98us * 2**interval, but let&#39;s call it 1us * 2**interval 
+                    The default gives a test interval of 250us</description>
+                <resetValue>0x00000008</resetValue>
+                <fields>
+                    <field>
+                        <name>FC0_INTERVAL</name>
+                        <bitRange>[3:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>FC0_SRC</name>
+                <addressOffset>0x00000094</addressOffset>
+                <description>Clock sent to frequency counter, set to 0 when not required 
+                    Writing to this register initiates the frequency count</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>FC0_SRC</name>
+                        <bitRange>[7:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NULL</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pll_sys_clksrc_primary</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pll_usb_clksrc_primary</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>rosc_clksrc</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>rosc_clksrc_ph</name>
+                                <value>4</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>xosc_clksrc</name>
+                                <value>5</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>clksrc_gpin0</name>
+                                <value>6</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>clksrc_gpin1</name>
+                                <value>7</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>clk_ref</name>
+                                <value>8</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>clk_sys</name>
+                                <value>9</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>clk_peri</name>
+                                <value>10</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>clk_usb</name>
+                                <value>11</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>clk_adc</name>
+                                <value>12</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>clk_rtc</name>
+                                <value>13</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>FC0_STATUS</name>
+                <addressOffset>0x00000098</addressOffset>
+                <description>Frequency counter status</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>DIED</name>
+                        <description>Test clock stopped during test</description>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>FAST</name>
+                        <description>Test clock faster than expected, only valid when status_done=1</description>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SLOW</name>
+                        <description>Test clock slower than expected, only valid when status_done=1</description>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>FAIL</name>
+                        <description>Test failed</description>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>WAITING</name>
+                        <description>Waiting for test clock to start</description>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>RUNNING</name>
+                        <description>Test running</description>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>DONE</name>
+                        <description>Test complete</description>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>PASS</name>
+                        <description>Test passed</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>FC0_RESULT</name>
+                <addressOffset>0x0000009c</addressOffset>
+                <description>Result of frequency measurement, only valid when status_done=1</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>KHZ</name>
+                        <bitRange>[29:5]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>FRAC</name>
+                        <bitRange>[4:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>WAKE_EN0</name>
+                <addressOffset>0x000000a0</addressOffset>
+                <description>enable clock in wake mode</description>
+                <resetValue>0xffffffff</resetValue>
+                <fields>
+                    <field>
+                        <name>CLK_SYS_SRAM3</name>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_SRAM2</name>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_SRAM1</name>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_SRAM0</name>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_SPI1</name>
+                        <bitRange>[27:27]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_PERI_SPI1</name>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_SPI0</name>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_PERI_SPI0</name>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_SIO</name>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_RTC</name>
+                        <bitRange>[22:22]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_RTC_RTC</name>
+                        <bitRange>[21:21]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_ROSC</name>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_ROM</name>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_RESETS</name>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_PWM</name>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_PSM</name>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_PLL_USB</name>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_PLL_SYS</name>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_PIO1</name>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_PIO0</name>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_PADS</name>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_VREG_AND_CHIP_RESET</name>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_JTAG</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_IO</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_I2C1</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_I2C0</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_DMA</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_BUSFABRIC</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_BUSCTRL</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_ADC</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_ADC_ADC</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_CLOCKS</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>WAKE_EN1</name>
+                <addressOffset>0x000000a4</addressOffset>
+                <description>enable clock in wake mode</description>
+                <resetValue>0x00007fff</resetValue>
+                <fields>
+                    <field>
+                        <name>CLK_SYS_XOSC</name>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_XIP</name>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_WATCHDOG</name>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_USB_USBCTRL</name>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_USBCTRL</name>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_UART1</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_PERI_UART1</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_UART0</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_PERI_UART0</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_TIMER</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_TBMAN</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_SYSINFO</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_SYSCFG</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_SRAM5</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_SRAM4</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SLEEP_EN0</name>
+                <addressOffset>0x000000a8</addressOffset>
+                <description>enable clock in sleep mode</description>
+                <resetValue>0xffffffff</resetValue>
+                <fields>
+                    <field>
+                        <name>CLK_SYS_SRAM3</name>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_SRAM2</name>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_SRAM1</name>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_SRAM0</name>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_SPI1</name>
+                        <bitRange>[27:27]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_PERI_SPI1</name>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_SPI0</name>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_PERI_SPI0</name>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_SIO</name>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_RTC</name>
+                        <bitRange>[22:22]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_RTC_RTC</name>
+                        <bitRange>[21:21]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_ROSC</name>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_ROM</name>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_RESETS</name>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_PWM</name>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_PSM</name>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_PLL_USB</name>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_PLL_SYS</name>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_PIO1</name>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_PIO0</name>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_PADS</name>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_VREG_AND_CHIP_RESET</name>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_JTAG</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_IO</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_I2C1</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_I2C0</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_DMA</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_BUSFABRIC</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_BUSCTRL</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_ADC</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_ADC_ADC</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_CLOCKS</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SLEEP_EN1</name>
+                <addressOffset>0x000000ac</addressOffset>
+                <description>enable clock in sleep mode</description>
+                <resetValue>0x00007fff</resetValue>
+                <fields>
+                    <field>
+                        <name>CLK_SYS_XOSC</name>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_XIP</name>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_WATCHDOG</name>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_USB_USBCTRL</name>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_USBCTRL</name>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_UART1</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_PERI_UART1</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_UART0</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_PERI_UART0</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_TIMER</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_TBMAN</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_SYSINFO</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_SYSCFG</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_SRAM5</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_SRAM4</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>ENABLED0</name>
+                <addressOffset>0x000000b0</addressOffset>
+                <description>indicates the state of the clock enable</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CLK_SYS_SRAM3</name>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_SRAM2</name>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_SRAM1</name>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_SRAM0</name>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_SPI1</name>
+                        <bitRange>[27:27]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CLK_PERI_SPI1</name>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_SPI0</name>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CLK_PERI_SPI0</name>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_SIO</name>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_RTC</name>
+                        <bitRange>[22:22]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CLK_RTC_RTC</name>
+                        <bitRange>[21:21]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_ROSC</name>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_ROM</name>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_RESETS</name>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_PWM</name>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_PSM</name>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_PLL_USB</name>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_PLL_SYS</name>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_PIO1</name>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_PIO0</name>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_PADS</name>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_VREG_AND_CHIP_RESET</name>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_JTAG</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_IO</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_I2C1</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_I2C0</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_DMA</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_BUSFABRIC</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_BUSCTRL</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_ADC</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CLK_ADC_ADC</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_CLOCKS</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>ENABLED1</name>
+                <addressOffset>0x000000b4</addressOffset>
+                <description>indicates the state of the clock enable</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CLK_SYS_XOSC</name>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_XIP</name>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_WATCHDOG</name>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CLK_USB_USBCTRL</name>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_USBCTRL</name>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_UART1</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CLK_PERI_UART1</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_UART0</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CLK_PERI_UART0</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_TIMER</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_TBMAN</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_SYSINFO</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_SYSCFG</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_SRAM5</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_SRAM4</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INTR</name>
+                <addressOffset>0x000000b8</addressOffset>
+                <description>Raw Interrupts</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CLK_SYS_RESUS</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INTE</name>
+                <addressOffset>0x000000bc</addressOffset>
+                <description>Interrupt Enable</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CLK_SYS_RESUS</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INTF</name>
+                <addressOffset>0x000000c0</addressOffset>
+                <description>Interrupt Force</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CLK_SYS_RESUS</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INTS</name>
+                <addressOffset>0x000000c4</addressOffset>
+                <description>Interrupt status after masking &amp; forcing</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CLK_SYS_RESUS</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+        </registers>
+    </peripheral>
+    <peripheral>
+        <name>PADS_BANK0</name>
+        <baseAddress>0x4001c000</baseAddress>
+        <addressBlock>
+            <offset>0</offset>
+            <size>132</size>
+            <usage>registers</usage>
+        </addressBlock>
+        <registers>
+            <register>
+                <name>VOLTAGE_SELECT</name>
+                <addressOffset>0x00000000</addressOffset>
+                <description>Voltage select. Per bank control</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>VOLTAGE_SELECT</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>3v3</name>
+                                <value>0</value>
+                                <description>Set voltage to 3.3V (DVDD &gt;= 2V5)</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>1v8</name>
+                                <value>1</value>
+                                <description>Set voltage to 1.8V (DVDD &lt;= 1V8)</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO0</name>
+                <addressOffset>0x00000004</addressOffset>
+                <description>Pad control register</description>
+                <resetValue>0x00000056</resetValue>
+                <fields>
+                    <field>
+                        <name>OD</name>
+                        <description>Output disable. Has priority over output enable from peripherals</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>IE</name>
+                        <description>Input enable</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DRIVE</name>
+                        <description>Drive strength.</description>
+                        <bitRange>[5:4]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>2mA</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>4mA</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>8mA</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>12mA</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>PUE</name>
+                        <description>Pull up enable</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PDE</name>
+                        <description>Pull down enable</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SCHMITT</name>
+                        <description>Enable schmitt trigger</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SLEWFAST</name>
+                        <description>Slew rate control. 1 = Fast, 0 = Slow</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO1</name>
+                <addressOffset>0x00000008</addressOffset>
+                <description>Pad control register</description>
+                <resetValue>0x00000056</resetValue>
+                <fields>
+                    <field>
+                        <name>OD</name>
+                        <description>Output disable. Has priority over output enable from peripherals</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>IE</name>
+                        <description>Input enable</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DRIVE</name>
+                        <description>Drive strength.</description>
+                        <bitRange>[5:4]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>2mA</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>4mA</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>8mA</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>12mA</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>PUE</name>
+                        <description>Pull up enable</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PDE</name>
+                        <description>Pull down enable</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SCHMITT</name>
+                        <description>Enable schmitt trigger</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SLEWFAST</name>
+                        <description>Slew rate control. 1 = Fast, 0 = Slow</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO2</name>
+                <addressOffset>0x0000000c</addressOffset>
+                <description>Pad control register</description>
+                <resetValue>0x00000056</resetValue>
+                <fields>
+                    <field>
+                        <name>OD</name>
+                        <description>Output disable. Has priority over output enable from peripherals</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>IE</name>
+                        <description>Input enable</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DRIVE</name>
+                        <description>Drive strength.</description>
+                        <bitRange>[5:4]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>2mA</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>4mA</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>8mA</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>12mA</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>PUE</name>
+                        <description>Pull up enable</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PDE</name>
+                        <description>Pull down enable</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SCHMITT</name>
+                        <description>Enable schmitt trigger</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SLEWFAST</name>
+                        <description>Slew rate control. 1 = Fast, 0 = Slow</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO3</name>
+                <addressOffset>0x00000010</addressOffset>
+                <description>Pad control register</description>
+                <resetValue>0x00000056</resetValue>
+                <fields>
+                    <field>
+                        <name>OD</name>
+                        <description>Output disable. Has priority over output enable from peripherals</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>IE</name>
+                        <description>Input enable</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DRIVE</name>
+                        <description>Drive strength.</description>
+                        <bitRange>[5:4]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>2mA</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>4mA</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>8mA</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>12mA</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>PUE</name>
+                        <description>Pull up enable</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PDE</name>
+                        <description>Pull down enable</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SCHMITT</name>
+                        <description>Enable schmitt trigger</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SLEWFAST</name>
+                        <description>Slew rate control. 1 = Fast, 0 = Slow</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO4</name>
+                <addressOffset>0x00000014</addressOffset>
+                <description>Pad control register</description>
+                <resetValue>0x00000056</resetValue>
+                <fields>
+                    <field>
+                        <name>OD</name>
+                        <description>Output disable. Has priority over output enable from peripherals</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>IE</name>
+                        <description>Input enable</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DRIVE</name>
+                        <description>Drive strength.</description>
+                        <bitRange>[5:4]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>2mA</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>4mA</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>8mA</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>12mA</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>PUE</name>
+                        <description>Pull up enable</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PDE</name>
+                        <description>Pull down enable</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SCHMITT</name>
+                        <description>Enable schmitt trigger</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SLEWFAST</name>
+                        <description>Slew rate control. 1 = Fast, 0 = Slow</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO5</name>
+                <addressOffset>0x00000018</addressOffset>
+                <description>Pad control register</description>
+                <resetValue>0x00000056</resetValue>
+                <fields>
+                    <field>
+                        <name>OD</name>
+                        <description>Output disable. Has priority over output enable from peripherals</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>IE</name>
+                        <description>Input enable</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DRIVE</name>
+                        <description>Drive strength.</description>
+                        <bitRange>[5:4]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>2mA</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>4mA</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>8mA</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>12mA</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>PUE</name>
+                        <description>Pull up enable</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PDE</name>
+                        <description>Pull down enable</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SCHMITT</name>
+                        <description>Enable schmitt trigger</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SLEWFAST</name>
+                        <description>Slew rate control. 1 = Fast, 0 = Slow</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO6</name>
+                <addressOffset>0x0000001c</addressOffset>
+                <description>Pad control register</description>
+                <resetValue>0x00000056</resetValue>
+                <fields>
+                    <field>
+                        <name>OD</name>
+                        <description>Output disable. Has priority over output enable from peripherals</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>IE</name>
+                        <description>Input enable</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DRIVE</name>
+                        <description>Drive strength.</description>
+                        <bitRange>[5:4]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>2mA</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>4mA</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>8mA</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>12mA</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>PUE</name>
+                        <description>Pull up enable</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PDE</name>
+                        <description>Pull down enable</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SCHMITT</name>
+                        <description>Enable schmitt trigger</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SLEWFAST</name>
+                        <description>Slew rate control. 1 = Fast, 0 = Slow</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO7</name>
+                <addressOffset>0x00000020</addressOffset>
+                <description>Pad control register</description>
+                <resetValue>0x00000056</resetValue>
+                <fields>
+                    <field>
+                        <name>OD</name>
+                        <description>Output disable. Has priority over output enable from peripherals</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>IE</name>
+                        <description>Input enable</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DRIVE</name>
+                        <description>Drive strength.</description>
+                        <bitRange>[5:4]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>2mA</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>4mA</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>8mA</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>12mA</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>PUE</name>
+                        <description>Pull up enable</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PDE</name>
+                        <description>Pull down enable</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SCHMITT</name>
+                        <description>Enable schmitt trigger</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SLEWFAST</name>
+                        <description>Slew rate control. 1 = Fast, 0 = Slow</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO8</name>
+                <addressOffset>0x00000024</addressOffset>
+                <description>Pad control register</description>
+                <resetValue>0x00000056</resetValue>
+                <fields>
+                    <field>
+                        <name>OD</name>
+                        <description>Output disable. Has priority over output enable from peripherals</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>IE</name>
+                        <description>Input enable</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DRIVE</name>
+                        <description>Drive strength.</description>
+                        <bitRange>[5:4]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>2mA</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>4mA</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>8mA</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>12mA</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>PUE</name>
+                        <description>Pull up enable</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PDE</name>
+                        <description>Pull down enable</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SCHMITT</name>
+                        <description>Enable schmitt trigger</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SLEWFAST</name>
+                        <description>Slew rate control. 1 = Fast, 0 = Slow</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO9</name>
+                <addressOffset>0x00000028</addressOffset>
+                <description>Pad control register</description>
+                <resetValue>0x00000056</resetValue>
+                <fields>
+                    <field>
+                        <name>OD</name>
+                        <description>Output disable. Has priority over output enable from peripherals</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>IE</name>
+                        <description>Input enable</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DRIVE</name>
+                        <description>Drive strength.</description>
+                        <bitRange>[5:4]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>2mA</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>4mA</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>8mA</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>12mA</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>PUE</name>
+                        <description>Pull up enable</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PDE</name>
+                        <description>Pull down enable</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SCHMITT</name>
+                        <description>Enable schmitt trigger</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SLEWFAST</name>
+                        <description>Slew rate control. 1 = Fast, 0 = Slow</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO10</name>
+                <addressOffset>0x0000002c</addressOffset>
+                <description>Pad control register</description>
+                <resetValue>0x00000056</resetValue>
+                <fields>
+                    <field>
+                        <name>OD</name>
+                        <description>Output disable. Has priority over output enable from peripherals</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>IE</name>
+                        <description>Input enable</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DRIVE</name>
+                        <description>Drive strength.</description>
+                        <bitRange>[5:4]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>2mA</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>4mA</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>8mA</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>12mA</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>PUE</name>
+                        <description>Pull up enable</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PDE</name>
+                        <description>Pull down enable</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SCHMITT</name>
+                        <description>Enable schmitt trigger</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SLEWFAST</name>
+                        <description>Slew rate control. 1 = Fast, 0 = Slow</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO11</name>
+                <addressOffset>0x00000030</addressOffset>
+                <description>Pad control register</description>
+                <resetValue>0x00000056</resetValue>
+                <fields>
+                    <field>
+                        <name>OD</name>
+                        <description>Output disable. Has priority over output enable from peripherals</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>IE</name>
+                        <description>Input enable</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DRIVE</name>
+                        <description>Drive strength.</description>
+                        <bitRange>[5:4]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>2mA</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>4mA</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>8mA</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>12mA</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>PUE</name>
+                        <description>Pull up enable</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PDE</name>
+                        <description>Pull down enable</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SCHMITT</name>
+                        <description>Enable schmitt trigger</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SLEWFAST</name>
+                        <description>Slew rate control. 1 = Fast, 0 = Slow</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO12</name>
+                <addressOffset>0x00000034</addressOffset>
+                <description>Pad control register</description>
+                <resetValue>0x00000056</resetValue>
+                <fields>
+                    <field>
+                        <name>OD</name>
+                        <description>Output disable. Has priority over output enable from peripherals</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>IE</name>
+                        <description>Input enable</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DRIVE</name>
+                        <description>Drive strength.</description>
+                        <bitRange>[5:4]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>2mA</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>4mA</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>8mA</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>12mA</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>PUE</name>
+                        <description>Pull up enable</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PDE</name>
+                        <description>Pull down enable</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SCHMITT</name>
+                        <description>Enable schmitt trigger</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SLEWFAST</name>
+                        <description>Slew rate control. 1 = Fast, 0 = Slow</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO13</name>
+                <addressOffset>0x00000038</addressOffset>
+                <description>Pad control register</description>
+                <resetValue>0x00000056</resetValue>
+                <fields>
+                    <field>
+                        <name>OD</name>
+                        <description>Output disable. Has priority over output enable from peripherals</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>IE</name>
+                        <description>Input enable</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DRIVE</name>
+                        <description>Drive strength.</description>
+                        <bitRange>[5:4]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>2mA</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>4mA</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>8mA</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>12mA</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>PUE</name>
+                        <description>Pull up enable</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PDE</name>
+                        <description>Pull down enable</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SCHMITT</name>
+                        <description>Enable schmitt trigger</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SLEWFAST</name>
+                        <description>Slew rate control. 1 = Fast, 0 = Slow</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO14</name>
+                <addressOffset>0x0000003c</addressOffset>
+                <description>Pad control register</description>
+                <resetValue>0x00000056</resetValue>
+                <fields>
+                    <field>
+                        <name>OD</name>
+                        <description>Output disable. Has priority over output enable from peripherals</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>IE</name>
+                        <description>Input enable</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DRIVE</name>
+                        <description>Drive strength.</description>
+                        <bitRange>[5:4]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>2mA</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>4mA</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>8mA</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>12mA</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>PUE</name>
+                        <description>Pull up enable</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PDE</name>
+                        <description>Pull down enable</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SCHMITT</name>
+                        <description>Enable schmitt trigger</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SLEWFAST</name>
+                        <description>Slew rate control. 1 = Fast, 0 = Slow</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO15</name>
+                <addressOffset>0x00000040</addressOffset>
+                <description>Pad control register</description>
+                <resetValue>0x00000056</resetValue>
+                <fields>
+                    <field>
+                        <name>OD</name>
+                        <description>Output disable. Has priority over output enable from peripherals</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>IE</name>
+                        <description>Input enable</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DRIVE</name>
+                        <description>Drive strength.</description>
+                        <bitRange>[5:4]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>2mA</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>4mA</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>8mA</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>12mA</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>PUE</name>
+                        <description>Pull up enable</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PDE</name>
+                        <description>Pull down enable</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SCHMITT</name>
+                        <description>Enable schmitt trigger</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SLEWFAST</name>
+                        <description>Slew rate control. 1 = Fast, 0 = Slow</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO16</name>
+                <addressOffset>0x00000044</addressOffset>
+                <description>Pad control register</description>
+                <resetValue>0x00000056</resetValue>
+                <fields>
+                    <field>
+                        <name>OD</name>
+                        <description>Output disable. Has priority over output enable from peripherals</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>IE</name>
+                        <description>Input enable</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DRIVE</name>
+                        <description>Drive strength.</description>
+                        <bitRange>[5:4]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>2mA</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>4mA</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>8mA</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>12mA</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>PUE</name>
+                        <description>Pull up enable</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PDE</name>
+                        <description>Pull down enable</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SCHMITT</name>
+                        <description>Enable schmitt trigger</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SLEWFAST</name>
+                        <description>Slew rate control. 1 = Fast, 0 = Slow</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO17</name>
+                <addressOffset>0x00000048</addressOffset>
+                <description>Pad control register</description>
+                <resetValue>0x00000056</resetValue>
+                <fields>
+                    <field>
+                        <name>OD</name>
+                        <description>Output disable. Has priority over output enable from peripherals</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>IE</name>
+                        <description>Input enable</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DRIVE</name>
+                        <description>Drive strength.</description>
+                        <bitRange>[5:4]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>2mA</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>4mA</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>8mA</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>12mA</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>PUE</name>
+                        <description>Pull up enable</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PDE</name>
+                        <description>Pull down enable</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SCHMITT</name>
+                        <description>Enable schmitt trigger</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SLEWFAST</name>
+                        <description>Slew rate control. 1 = Fast, 0 = Slow</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO18</name>
+                <addressOffset>0x0000004c</addressOffset>
+                <description>Pad control register</description>
+                <resetValue>0x00000056</resetValue>
+                <fields>
+                    <field>
+                        <name>OD</name>
+                        <description>Output disable. Has priority over output enable from peripherals</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>IE</name>
+                        <description>Input enable</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DRIVE</name>
+                        <description>Drive strength.</description>
+                        <bitRange>[5:4]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>2mA</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>4mA</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>8mA</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>12mA</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>PUE</name>
+                        <description>Pull up enable</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PDE</name>
+                        <description>Pull down enable</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SCHMITT</name>
+                        <description>Enable schmitt trigger</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SLEWFAST</name>
+                        <description>Slew rate control. 1 = Fast, 0 = Slow</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO19</name>
+                <addressOffset>0x00000050</addressOffset>
+                <description>Pad control register</description>
+                <resetValue>0x00000056</resetValue>
+                <fields>
+                    <field>
+                        <name>OD</name>
+                        <description>Output disable. Has priority over output enable from peripherals</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>IE</name>
+                        <description>Input enable</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DRIVE</name>
+                        <description>Drive strength.</description>
+                        <bitRange>[5:4]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>2mA</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>4mA</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>8mA</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>12mA</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>PUE</name>
+                        <description>Pull up enable</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PDE</name>
+                        <description>Pull down enable</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SCHMITT</name>
+                        <description>Enable schmitt trigger</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SLEWFAST</name>
+                        <description>Slew rate control. 1 = Fast, 0 = Slow</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO20</name>
+                <addressOffset>0x00000054</addressOffset>
+                <description>Pad control register</description>
+                <resetValue>0x00000056</resetValue>
+                <fields>
+                    <field>
+                        <name>OD</name>
+                        <description>Output disable. Has priority over output enable from peripherals</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>IE</name>
+                        <description>Input enable</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DRIVE</name>
+                        <description>Drive strength.</description>
+                        <bitRange>[5:4]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>2mA</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>4mA</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>8mA</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>12mA</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>PUE</name>
+                        <description>Pull up enable</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PDE</name>
+                        <description>Pull down enable</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SCHMITT</name>
+                        <description>Enable schmitt trigger</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SLEWFAST</name>
+                        <description>Slew rate control. 1 = Fast, 0 = Slow</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO21</name>
+                <addressOffset>0x00000058</addressOffset>
+                <description>Pad control register</description>
+                <resetValue>0x00000056</resetValue>
+                <fields>
+                    <field>
+                        <name>OD</name>
+                        <description>Output disable. Has priority over output enable from peripherals</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>IE</name>
+                        <description>Input enable</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DRIVE</name>
+                        <description>Drive strength.</description>
+                        <bitRange>[5:4]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>2mA</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>4mA</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>8mA</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>12mA</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>PUE</name>
+                        <description>Pull up enable</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PDE</name>
+                        <description>Pull down enable</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SCHMITT</name>
+                        <description>Enable schmitt trigger</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SLEWFAST</name>
+                        <description>Slew rate control. 1 = Fast, 0 = Slow</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO22</name>
+                <addressOffset>0x0000005c</addressOffset>
+                <description>Pad control register</description>
+                <resetValue>0x00000056</resetValue>
+                <fields>
+                    <field>
+                        <name>OD</name>
+                        <description>Output disable. Has priority over output enable from peripherals</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>IE</name>
+                        <description>Input enable</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DRIVE</name>
+                        <description>Drive strength.</description>
+                        <bitRange>[5:4]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>2mA</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>4mA</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>8mA</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>12mA</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>PUE</name>
+                        <description>Pull up enable</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PDE</name>
+                        <description>Pull down enable</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SCHMITT</name>
+                        <description>Enable schmitt trigger</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SLEWFAST</name>
+                        <description>Slew rate control. 1 = Fast, 0 = Slow</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO23</name>
+                <addressOffset>0x00000060</addressOffset>
+                <description>Pad control register</description>
+                <resetValue>0x00000056</resetValue>
+                <fields>
+                    <field>
+                        <name>OD</name>
+                        <description>Output disable. Has priority over output enable from peripherals</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>IE</name>
+                        <description>Input enable</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DRIVE</name>
+                        <description>Drive strength.</description>
+                        <bitRange>[5:4]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>2mA</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>4mA</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>8mA</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>12mA</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>PUE</name>
+                        <description>Pull up enable</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PDE</name>
+                        <description>Pull down enable</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SCHMITT</name>
+                        <description>Enable schmitt trigger</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SLEWFAST</name>
+                        <description>Slew rate control. 1 = Fast, 0 = Slow</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO24</name>
+                <addressOffset>0x00000064</addressOffset>
+                <description>Pad control register</description>
+                <resetValue>0x00000056</resetValue>
+                <fields>
+                    <field>
+                        <name>OD</name>
+                        <description>Output disable. Has priority over output enable from peripherals</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>IE</name>
+                        <description>Input enable</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DRIVE</name>
+                        <description>Drive strength.</description>
+                        <bitRange>[5:4]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>2mA</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>4mA</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>8mA</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>12mA</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>PUE</name>
+                        <description>Pull up enable</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PDE</name>
+                        <description>Pull down enable</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SCHMITT</name>
+                        <description>Enable schmitt trigger</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SLEWFAST</name>
+                        <description>Slew rate control. 1 = Fast, 0 = Slow</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO25</name>
+                <addressOffset>0x00000068</addressOffset>
+                <description>Pad control register</description>
+                <resetValue>0x00000056</resetValue>
+                <fields>
+                    <field>
+                        <name>OD</name>
+                        <description>Output disable. Has priority over output enable from peripherals</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>IE</name>
+                        <description>Input enable</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DRIVE</name>
+                        <description>Drive strength.</description>
+                        <bitRange>[5:4]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>2mA</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>4mA</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>8mA</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>12mA</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>PUE</name>
+                        <description>Pull up enable</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PDE</name>
+                        <description>Pull down enable</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SCHMITT</name>
+                        <description>Enable schmitt trigger</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SLEWFAST</name>
+                        <description>Slew rate control. 1 = Fast, 0 = Slow</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO26</name>
+                <addressOffset>0x0000006c</addressOffset>
+                <description>Pad control register</description>
+                <resetValue>0x00000056</resetValue>
+                <fields>
+                    <field>
+                        <name>OD</name>
+                        <description>Output disable. Has priority over output enable from peripherals</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>IE</name>
+                        <description>Input enable</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DRIVE</name>
+                        <description>Drive strength.</description>
+                        <bitRange>[5:4]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>2mA</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>4mA</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>8mA</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>12mA</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>PUE</name>
+                        <description>Pull up enable</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PDE</name>
+                        <description>Pull down enable</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SCHMITT</name>
+                        <description>Enable schmitt trigger</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SLEWFAST</name>
+                        <description>Slew rate control. 1 = Fast, 0 = Slow</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO27</name>
+                <addressOffset>0x00000070</addressOffset>
+                <description>Pad control register</description>
+                <resetValue>0x00000056</resetValue>
+                <fields>
+                    <field>
+                        <name>OD</name>
+                        <description>Output disable. Has priority over output enable from peripherals</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>IE</name>
+                        <description>Input enable</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DRIVE</name>
+                        <description>Drive strength.</description>
+                        <bitRange>[5:4]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>2mA</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>4mA</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>8mA</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>12mA</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>PUE</name>
+                        <description>Pull up enable</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PDE</name>
+                        <description>Pull down enable</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SCHMITT</name>
+                        <description>Enable schmitt trigger</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SLEWFAST</name>
+                        <description>Slew rate control. 1 = Fast, 0 = Slow</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO28</name>
+                <addressOffset>0x00000074</addressOffset>
+                <description>Pad control register</description>
+                <resetValue>0x00000056</resetValue>
+                <fields>
+                    <field>
+                        <name>OD</name>
+                        <description>Output disable. Has priority over output enable from peripherals</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>IE</name>
+                        <description>Input enable</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DRIVE</name>
+                        <description>Drive strength.</description>
+                        <bitRange>[5:4]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>2mA</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>4mA</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>8mA</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>12mA</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>PUE</name>
+                        <description>Pull up enable</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PDE</name>
+                        <description>Pull down enable</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SCHMITT</name>
+                        <description>Enable schmitt trigger</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SLEWFAST</name>
+                        <description>Slew rate control. 1 = Fast, 0 = Slow</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO29</name>
+                <addressOffset>0x00000078</addressOffset>
+                <description>Pad control register</description>
+                <resetValue>0x00000056</resetValue>
+                <fields>
+                    <field>
+                        <name>OD</name>
+                        <description>Output disable. Has priority over output enable from peripherals</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>IE</name>
+                        <description>Input enable</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DRIVE</name>
+                        <description>Drive strength.</description>
+                        <bitRange>[5:4]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>2mA</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>4mA</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>8mA</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>12mA</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>PUE</name>
+                        <description>Pull up enable</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PDE</name>
+                        <description>Pull down enable</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SCHMITT</name>
+                        <description>Enable schmitt trigger</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SLEWFAST</name>
+                        <description>Slew rate control. 1 = Fast, 0 = Slow</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SWCLK</name>
+                <addressOffset>0x0000007c</addressOffset>
+                <description>Pad control register</description>
+                <resetValue>0x000000da</resetValue>
+                <fields>
+                    <field>
+                        <name>OD</name>
+                        <description>Output disable. Has priority over output enable from peripherals</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>IE</name>
+                        <description>Input enable</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DRIVE</name>
+                        <description>Drive strength.</description>
+                        <bitRange>[5:4]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>2mA</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>4mA</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>8mA</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>12mA</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>PUE</name>
+                        <description>Pull up enable</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PDE</name>
+                        <description>Pull down enable</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SCHMITT</name>
+                        <description>Enable schmitt trigger</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SLEWFAST</name>
+                        <description>Slew rate control. 1 = Fast, 0 = Slow</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SWD</name>
+                <addressOffset>0x00000080</addressOffset>
+                <description>Pad control register</description>
+                <resetValue>0x0000005a</resetValue>
+                <fields>
+                    <field>
+                        <name>OD</name>
+                        <description>Output disable. Has priority over output enable from peripherals</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>IE</name>
+                        <description>Input enable</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DRIVE</name>
+                        <description>Drive strength.</description>
+                        <bitRange>[5:4]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>2mA</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>4mA</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>8mA</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>12mA</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>PUE</name>
+                        <description>Pull up enable</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PDE</name>
+                        <description>Pull down enable</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SCHMITT</name>
+                        <description>Enable schmitt trigger</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SLEWFAST</name>
+                        <description>Slew rate control. 1 = Fast, 0 = Slow</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+        </registers>
+    </peripheral>
+    <peripheral>
+        <name>PADS_QSPI</name>
+        <baseAddress>0x40020000</baseAddress>
+        <addressBlock>
+            <offset>0</offset>
+            <size>28</size>
+            <usage>registers</usage>
+        </addressBlock>
+        <registers>
+            <register>
+                <name>VOLTAGE_SELECT</name>
+                <addressOffset>0x00000000</addressOffset>
+                <description>Voltage select. Per bank control</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>VOLTAGE_SELECT</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>3v3</name>
+                                <value>0</value>
+                                <description>Set voltage to 3.3V (DVDD &gt;= 2V5)</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>1v8</name>
+                                <value>1</value>
+                                <description>Set voltage to 1.8V (DVDD &lt;= 1V8)</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO_QSPI_SCLK</name>
+                <addressOffset>0x00000004</addressOffset>
+                <description>Pad control register</description>
+                <resetValue>0x00000056</resetValue>
+                <fields>
+                    <field>
+                        <name>OD</name>
+                        <description>Output disable. Has priority over output enable from peripherals</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>IE</name>
+                        <description>Input enable</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DRIVE</name>
+                        <description>Drive strength.</description>
+                        <bitRange>[5:4]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>2mA</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>4mA</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>8mA</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>12mA</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>PUE</name>
+                        <description>Pull up enable</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PDE</name>
+                        <description>Pull down enable</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SCHMITT</name>
+                        <description>Enable schmitt trigger</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SLEWFAST</name>
+                        <description>Slew rate control. 1 = Fast, 0 = Slow</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO_QSPI_SD0</name>
+                <addressOffset>0x00000008</addressOffset>
+                <description>Pad control register</description>
+                <resetValue>0x00000052</resetValue>
+                <fields>
+                    <field>
+                        <name>OD</name>
+                        <description>Output disable. Has priority over output enable from peripherals</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>IE</name>
+                        <description>Input enable</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DRIVE</name>
+                        <description>Drive strength.</description>
+                        <bitRange>[5:4]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>2mA</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>4mA</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>8mA</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>12mA</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>PUE</name>
+                        <description>Pull up enable</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PDE</name>
+                        <description>Pull down enable</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SCHMITT</name>
+                        <description>Enable schmitt trigger</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SLEWFAST</name>
+                        <description>Slew rate control. 1 = Fast, 0 = Slow</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO_QSPI_SD1</name>
+                <addressOffset>0x0000000c</addressOffset>
+                <description>Pad control register</description>
+                <resetValue>0x00000052</resetValue>
+                <fields>
+                    <field>
+                        <name>OD</name>
+                        <description>Output disable. Has priority over output enable from peripherals</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>IE</name>
+                        <description>Input enable</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DRIVE</name>
+                        <description>Drive strength.</description>
+                        <bitRange>[5:4]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>2mA</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>4mA</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>8mA</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>12mA</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>PUE</name>
+                        <description>Pull up enable</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PDE</name>
+                        <description>Pull down enable</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SCHMITT</name>
+                        <description>Enable schmitt trigger</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SLEWFAST</name>
+                        <description>Slew rate control. 1 = Fast, 0 = Slow</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO_QSPI_SD2</name>
+                <addressOffset>0x00000010</addressOffset>
+                <description>Pad control register</description>
+                <resetValue>0x00000052</resetValue>
+                <fields>
+                    <field>
+                        <name>OD</name>
+                        <description>Output disable. Has priority over output enable from peripherals</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>IE</name>
+                        <description>Input enable</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DRIVE</name>
+                        <description>Drive strength.</description>
+                        <bitRange>[5:4]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>2mA</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>4mA</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>8mA</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>12mA</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>PUE</name>
+                        <description>Pull up enable</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PDE</name>
+                        <description>Pull down enable</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SCHMITT</name>
+                        <description>Enable schmitt trigger</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SLEWFAST</name>
+                        <description>Slew rate control. 1 = Fast, 0 = Slow</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO_QSPI_SD3</name>
+                <addressOffset>0x00000014</addressOffset>
+                <description>Pad control register</description>
+                <resetValue>0x00000052</resetValue>
+                <fields>
+                    <field>
+                        <name>OD</name>
+                        <description>Output disable. Has priority over output enable from peripherals</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>IE</name>
+                        <description>Input enable</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DRIVE</name>
+                        <description>Drive strength.</description>
+                        <bitRange>[5:4]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>2mA</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>4mA</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>8mA</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>12mA</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>PUE</name>
+                        <description>Pull up enable</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PDE</name>
+                        <description>Pull down enable</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SCHMITT</name>
+                        <description>Enable schmitt trigger</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SLEWFAST</name>
+                        <description>Slew rate control. 1 = Fast, 0 = Slow</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO_QSPI_SS</name>
+                <addressOffset>0x00000018</addressOffset>
+                <description>Pad control register</description>
+                <resetValue>0x0000005a</resetValue>
+                <fields>
+                    <field>
+                        <name>OD</name>
+                        <description>Output disable. Has priority over output enable from peripherals</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>IE</name>
+                        <description>Input enable</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DRIVE</name>
+                        <description>Drive strength.</description>
+                        <bitRange>[5:4]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>2mA</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>4mA</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>8mA</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>12mA</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>PUE</name>
+                        <description>Pull up enable</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PDE</name>
+                        <description>Pull down enable</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SCHMITT</name>
+                        <description>Enable schmitt trigger</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SLEWFAST</name>
+                        <description>Slew rate control. 1 = Fast, 0 = Slow</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+        </registers>
+    </peripheral>
+    <peripheral>
+        <name>IO_QSPI</name>
+        <baseAddress>0x40018000</baseAddress>
+        <addressBlock>
+            <offset>0</offset>
+            <size>88</size>
+            <usage>registers</usage>
+        </addressBlock>
+        <interrupt>
+            <name>IO_IRQ_QSPI</name>
+            <value>14</value>
+        </interrupt>
+        <registers>
+            <register>
+                <name>GPIO_QSPI_SCLK_STATUS</name>
+                <addressOffset>0x00000000</addressOffset>
+                <description>GPIO status</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>IRQTOPROC</name>
+                        <description>interrupt to processors, after override is applied</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>IRQFROMPAD</name>
+                        <description>interrupt from pad before override is applied</description>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>INTOPERI</name>
+                        <description>input signal to peripheral, after override is applied</description>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>INFROMPAD</name>
+                        <description>input signal from pad, before override is applied</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OETOPAD</name>
+                        <description>output enable to pad after register override is applied</description>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OEFROMPERI</name>
+                        <description>output enable from selected peripheral, before register override is applied</description>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OUTTOPAD</name>
+                        <description>output signal to pad after register override is applied</description>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OUTFROMPERI</name>
+                        <description>output signal from selected peripheral, before register override is applied</description>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO_QSPI_SCLK_CTRL</name>
+                <addressOffset>0x00000004</addressOffset>
+                <description>GPIO control including function select and overrides.</description>
+                <resetValue>0x0000001f</resetValue>
+                <fields>
+                    <field>
+                        <name>IRQOVER</name>
+                        <bitRange>[29:28]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>don&#39;t invert the interrupt</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>invert the interrupt</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive interrupt low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive interrupt high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>INOVER</name>
+                        <bitRange>[17:16]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>don&#39;t invert the peri input</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>invert the peri input</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive peri input low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive peri input high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>OEOVER</name>
+                        <bitRange>[13:12]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>drive output enable from peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>DISABLE</name>
+                                <value>2</value>
+                                <description>disable output</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ENABLE</name>
+                                <value>3</value>
+                                <description>enable output</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>OUTOVER</name>
+                        <bitRange>[9:8]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>drive output from peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>drive output from inverse of peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive output low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive output high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>FUNCSEL</name>
+                        <description>0-31 -&gt; selects pin function according to the gpio table 
+                            31 == NULL</description>
+                        <bitRange>[4:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>xip_sclk</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sio_30</name>
+                                <value>5</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>null</name>
+                                <value>31</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO_QSPI_SS_STATUS</name>
+                <addressOffset>0x00000008</addressOffset>
+                <description>GPIO status</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>IRQTOPROC</name>
+                        <description>interrupt to processors, after override is applied</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>IRQFROMPAD</name>
+                        <description>interrupt from pad before override is applied</description>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>INTOPERI</name>
+                        <description>input signal to peripheral, after override is applied</description>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>INFROMPAD</name>
+                        <description>input signal from pad, before override is applied</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OETOPAD</name>
+                        <description>output enable to pad after register override is applied</description>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OEFROMPERI</name>
+                        <description>output enable from selected peripheral, before register override is applied</description>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OUTTOPAD</name>
+                        <description>output signal to pad after register override is applied</description>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OUTFROMPERI</name>
+                        <description>output signal from selected peripheral, before register override is applied</description>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO_QSPI_SS_CTRL</name>
+                <addressOffset>0x0000000c</addressOffset>
+                <description>GPIO control including function select and overrides.</description>
+                <resetValue>0x0000001f</resetValue>
+                <fields>
+                    <field>
+                        <name>IRQOVER</name>
+                        <bitRange>[29:28]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>don&#39;t invert the interrupt</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>invert the interrupt</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive interrupt low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive interrupt high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>INOVER</name>
+                        <bitRange>[17:16]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>don&#39;t invert the peri input</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>invert the peri input</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive peri input low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive peri input high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>OEOVER</name>
+                        <bitRange>[13:12]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>drive output enable from peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>DISABLE</name>
+                                <value>2</value>
+                                <description>disable output</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ENABLE</name>
+                                <value>3</value>
+                                <description>enable output</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>OUTOVER</name>
+                        <bitRange>[9:8]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>drive output from peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>drive output from inverse of peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive output low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive output high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>FUNCSEL</name>
+                        <description>0-31 -&gt; selects pin function according to the gpio table 
+                            31 == NULL</description>
+                        <bitRange>[4:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>xip_ss_n</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sio_31</name>
+                                <value>5</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>null</name>
+                                <value>31</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO_QSPI_SD0_STATUS</name>
+                <addressOffset>0x00000010</addressOffset>
+                <description>GPIO status</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>IRQTOPROC</name>
+                        <description>interrupt to processors, after override is applied</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>IRQFROMPAD</name>
+                        <description>interrupt from pad before override is applied</description>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>INTOPERI</name>
+                        <description>input signal to peripheral, after override is applied</description>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>INFROMPAD</name>
+                        <description>input signal from pad, before override is applied</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OETOPAD</name>
+                        <description>output enable to pad after register override is applied</description>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OEFROMPERI</name>
+                        <description>output enable from selected peripheral, before register override is applied</description>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OUTTOPAD</name>
+                        <description>output signal to pad after register override is applied</description>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OUTFROMPERI</name>
+                        <description>output signal from selected peripheral, before register override is applied</description>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO_QSPI_SD0_CTRL</name>
+                <addressOffset>0x00000014</addressOffset>
+                <description>GPIO control including function select and overrides.</description>
+                <resetValue>0x0000001f</resetValue>
+                <fields>
+                    <field>
+                        <name>IRQOVER</name>
+                        <bitRange>[29:28]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>don&#39;t invert the interrupt</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>invert the interrupt</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive interrupt low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive interrupt high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>INOVER</name>
+                        <bitRange>[17:16]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>don&#39;t invert the peri input</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>invert the peri input</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive peri input low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive peri input high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>OEOVER</name>
+                        <bitRange>[13:12]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>drive output enable from peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>DISABLE</name>
+                                <value>2</value>
+                                <description>disable output</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ENABLE</name>
+                                <value>3</value>
+                                <description>enable output</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>OUTOVER</name>
+                        <bitRange>[9:8]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>drive output from peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>drive output from inverse of peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive output low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive output high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>FUNCSEL</name>
+                        <description>0-31 -&gt; selects pin function according to the gpio table 
+                            31 == NULL</description>
+                        <bitRange>[4:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>xip_sd0</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sio_32</name>
+                                <value>5</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>null</name>
+                                <value>31</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO_QSPI_SD1_STATUS</name>
+                <addressOffset>0x00000018</addressOffset>
+                <description>GPIO status</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>IRQTOPROC</name>
+                        <description>interrupt to processors, after override is applied</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>IRQFROMPAD</name>
+                        <description>interrupt from pad before override is applied</description>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>INTOPERI</name>
+                        <description>input signal to peripheral, after override is applied</description>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>INFROMPAD</name>
+                        <description>input signal from pad, before override is applied</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OETOPAD</name>
+                        <description>output enable to pad after register override is applied</description>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OEFROMPERI</name>
+                        <description>output enable from selected peripheral, before register override is applied</description>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OUTTOPAD</name>
+                        <description>output signal to pad after register override is applied</description>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OUTFROMPERI</name>
+                        <description>output signal from selected peripheral, before register override is applied</description>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO_QSPI_SD1_CTRL</name>
+                <addressOffset>0x0000001c</addressOffset>
+                <description>GPIO control including function select and overrides.</description>
+                <resetValue>0x0000001f</resetValue>
+                <fields>
+                    <field>
+                        <name>IRQOVER</name>
+                        <bitRange>[29:28]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>don&#39;t invert the interrupt</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>invert the interrupt</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive interrupt low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive interrupt high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>INOVER</name>
+                        <bitRange>[17:16]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>don&#39;t invert the peri input</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>invert the peri input</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive peri input low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive peri input high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>OEOVER</name>
+                        <bitRange>[13:12]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>drive output enable from peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>DISABLE</name>
+                                <value>2</value>
+                                <description>disable output</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ENABLE</name>
+                                <value>3</value>
+                                <description>enable output</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>OUTOVER</name>
+                        <bitRange>[9:8]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>drive output from peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>drive output from inverse of peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive output low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive output high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>FUNCSEL</name>
+                        <description>0-31 -&gt; selects pin function according to the gpio table 
+                            31 == NULL</description>
+                        <bitRange>[4:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>xip_sd1</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sio_33</name>
+                                <value>5</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>null</name>
+                                <value>31</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO_QSPI_SD2_STATUS</name>
+                <addressOffset>0x00000020</addressOffset>
+                <description>GPIO status</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>IRQTOPROC</name>
+                        <description>interrupt to processors, after override is applied</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>IRQFROMPAD</name>
+                        <description>interrupt from pad before override is applied</description>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>INTOPERI</name>
+                        <description>input signal to peripheral, after override is applied</description>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>INFROMPAD</name>
+                        <description>input signal from pad, before override is applied</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OETOPAD</name>
+                        <description>output enable to pad after register override is applied</description>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OEFROMPERI</name>
+                        <description>output enable from selected peripheral, before register override is applied</description>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OUTTOPAD</name>
+                        <description>output signal to pad after register override is applied</description>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OUTFROMPERI</name>
+                        <description>output signal from selected peripheral, before register override is applied</description>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO_QSPI_SD2_CTRL</name>
+                <addressOffset>0x00000024</addressOffset>
+                <description>GPIO control including function select and overrides.</description>
+                <resetValue>0x0000001f</resetValue>
+                <fields>
+                    <field>
+                        <name>IRQOVER</name>
+                        <bitRange>[29:28]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>don&#39;t invert the interrupt</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>invert the interrupt</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive interrupt low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive interrupt high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>INOVER</name>
+                        <bitRange>[17:16]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>don&#39;t invert the peri input</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>invert the peri input</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive peri input low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive peri input high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>OEOVER</name>
+                        <bitRange>[13:12]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>drive output enable from peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>DISABLE</name>
+                                <value>2</value>
+                                <description>disable output</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ENABLE</name>
+                                <value>3</value>
+                                <description>enable output</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>OUTOVER</name>
+                        <bitRange>[9:8]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>drive output from peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>drive output from inverse of peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive output low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive output high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>FUNCSEL</name>
+                        <description>0-31 -&gt; selects pin function according to the gpio table 
+                            31 == NULL</description>
+                        <bitRange>[4:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>xip_sd2</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sio_34</name>
+                                <value>5</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>null</name>
+                                <value>31</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO_QSPI_SD3_STATUS</name>
+                <addressOffset>0x00000028</addressOffset>
+                <description>GPIO status</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>IRQTOPROC</name>
+                        <description>interrupt to processors, after override is applied</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>IRQFROMPAD</name>
+                        <description>interrupt from pad before override is applied</description>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>INTOPERI</name>
+                        <description>input signal to peripheral, after override is applied</description>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>INFROMPAD</name>
+                        <description>input signal from pad, before override is applied</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OETOPAD</name>
+                        <description>output enable to pad after register override is applied</description>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OEFROMPERI</name>
+                        <description>output enable from selected peripheral, before register override is applied</description>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OUTTOPAD</name>
+                        <description>output signal to pad after register override is applied</description>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OUTFROMPERI</name>
+                        <description>output signal from selected peripheral, before register override is applied</description>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO_QSPI_SD3_CTRL</name>
+                <addressOffset>0x0000002c</addressOffset>
+                <description>GPIO control including function select and overrides.</description>
+                <resetValue>0x0000001f</resetValue>
+                <fields>
+                    <field>
+                        <name>IRQOVER</name>
+                        <bitRange>[29:28]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>don&#39;t invert the interrupt</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>invert the interrupt</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive interrupt low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive interrupt high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>INOVER</name>
+                        <bitRange>[17:16]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>don&#39;t invert the peri input</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>invert the peri input</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive peri input low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive peri input high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>OEOVER</name>
+                        <bitRange>[13:12]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>drive output enable from peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>DISABLE</name>
+                                <value>2</value>
+                                <description>disable output</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ENABLE</name>
+                                <value>3</value>
+                                <description>enable output</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>OUTOVER</name>
+                        <bitRange>[9:8]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>drive output from peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>drive output from inverse of peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive output low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive output high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>FUNCSEL</name>
+                        <description>0-31 -&gt; selects pin function according to the gpio table 
+                            31 == NULL</description>
+                        <bitRange>[4:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>xip_sd3</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sio_35</name>
+                                <value>5</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>null</name>
+                                <value>31</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INTR</name>
+                <addressOffset>0x00000030</addressOffset>
+                <description>Raw Interrupts</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>GPIO_QSPI_SD3_EDGE_HIGH</name>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD3_EDGE_LOW</name>
+                        <bitRange>[22:22]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD3_LEVEL_HIGH</name>
+                        <bitRange>[21:21]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD3_LEVEL_LOW</name>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD2_EDGE_HIGH</name>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD2_EDGE_LOW</name>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD2_LEVEL_HIGH</name>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD2_LEVEL_LOW</name>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD1_EDGE_HIGH</name>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD1_EDGE_LOW</name>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD1_LEVEL_HIGH</name>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD1_LEVEL_LOW</name>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD0_EDGE_HIGH</name>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD0_EDGE_LOW</name>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD0_LEVEL_HIGH</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD0_LEVEL_LOW</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SS_EDGE_HIGH</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SS_EDGE_LOW</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SS_LEVEL_HIGH</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SS_LEVEL_LOW</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SCLK_EDGE_HIGH</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SCLK_EDGE_LOW</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SCLK_LEVEL_HIGH</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SCLK_LEVEL_LOW</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PROC0_INTE</name>
+                <addressOffset>0x00000034</addressOffset>
+                <description>Interrupt Enable for proc0</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>GPIO_QSPI_SD3_EDGE_HIGH</name>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD3_EDGE_LOW</name>
+                        <bitRange>[22:22]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD3_LEVEL_HIGH</name>
+                        <bitRange>[21:21]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD3_LEVEL_LOW</name>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD2_EDGE_HIGH</name>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD2_EDGE_LOW</name>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD2_LEVEL_HIGH</name>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD2_LEVEL_LOW</name>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD1_EDGE_HIGH</name>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD1_EDGE_LOW</name>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD1_LEVEL_HIGH</name>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD1_LEVEL_LOW</name>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD0_EDGE_HIGH</name>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD0_EDGE_LOW</name>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD0_LEVEL_HIGH</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD0_LEVEL_LOW</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SS_EDGE_HIGH</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SS_EDGE_LOW</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SS_LEVEL_HIGH</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SS_LEVEL_LOW</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SCLK_EDGE_HIGH</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SCLK_EDGE_LOW</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SCLK_LEVEL_HIGH</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SCLK_LEVEL_LOW</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PROC0_INTF</name>
+                <addressOffset>0x00000038</addressOffset>
+                <description>Interrupt Force for proc0</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>GPIO_QSPI_SD3_EDGE_HIGH</name>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD3_EDGE_LOW</name>
+                        <bitRange>[22:22]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD3_LEVEL_HIGH</name>
+                        <bitRange>[21:21]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD3_LEVEL_LOW</name>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD2_EDGE_HIGH</name>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD2_EDGE_LOW</name>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD2_LEVEL_HIGH</name>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD2_LEVEL_LOW</name>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD1_EDGE_HIGH</name>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD1_EDGE_LOW</name>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD1_LEVEL_HIGH</name>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD1_LEVEL_LOW</name>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD0_EDGE_HIGH</name>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD0_EDGE_LOW</name>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD0_LEVEL_HIGH</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD0_LEVEL_LOW</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SS_EDGE_HIGH</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SS_EDGE_LOW</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SS_LEVEL_HIGH</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SS_LEVEL_LOW</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SCLK_EDGE_HIGH</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SCLK_EDGE_LOW</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SCLK_LEVEL_HIGH</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SCLK_LEVEL_LOW</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PROC0_INTS</name>
+                <addressOffset>0x0000003c</addressOffset>
+                <description>Interrupt status after masking &amp; forcing for proc0</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>GPIO_QSPI_SD3_EDGE_HIGH</name>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD3_EDGE_LOW</name>
+                        <bitRange>[22:22]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD3_LEVEL_HIGH</name>
+                        <bitRange>[21:21]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD3_LEVEL_LOW</name>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD2_EDGE_HIGH</name>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD2_EDGE_LOW</name>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD2_LEVEL_HIGH</name>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD2_LEVEL_LOW</name>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD1_EDGE_HIGH</name>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD1_EDGE_LOW</name>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD1_LEVEL_HIGH</name>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD1_LEVEL_LOW</name>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD0_EDGE_HIGH</name>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD0_EDGE_LOW</name>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD0_LEVEL_HIGH</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD0_LEVEL_LOW</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SS_EDGE_HIGH</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SS_EDGE_LOW</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SS_LEVEL_HIGH</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SS_LEVEL_LOW</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SCLK_EDGE_HIGH</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SCLK_EDGE_LOW</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SCLK_LEVEL_HIGH</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SCLK_LEVEL_LOW</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PROC1_INTE</name>
+                <addressOffset>0x00000040</addressOffset>
+                <description>Interrupt Enable for proc1</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>GPIO_QSPI_SD3_EDGE_HIGH</name>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD3_EDGE_LOW</name>
+                        <bitRange>[22:22]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD3_LEVEL_HIGH</name>
+                        <bitRange>[21:21]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD3_LEVEL_LOW</name>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD2_EDGE_HIGH</name>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD2_EDGE_LOW</name>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD2_LEVEL_HIGH</name>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD2_LEVEL_LOW</name>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD1_EDGE_HIGH</name>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD1_EDGE_LOW</name>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD1_LEVEL_HIGH</name>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD1_LEVEL_LOW</name>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD0_EDGE_HIGH</name>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD0_EDGE_LOW</name>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD0_LEVEL_HIGH</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD0_LEVEL_LOW</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SS_EDGE_HIGH</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SS_EDGE_LOW</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SS_LEVEL_HIGH</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SS_LEVEL_LOW</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SCLK_EDGE_HIGH</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SCLK_EDGE_LOW</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SCLK_LEVEL_HIGH</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SCLK_LEVEL_LOW</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PROC1_INTF</name>
+                <addressOffset>0x00000044</addressOffset>
+                <description>Interrupt Force for proc1</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>GPIO_QSPI_SD3_EDGE_HIGH</name>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD3_EDGE_LOW</name>
+                        <bitRange>[22:22]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD3_LEVEL_HIGH</name>
+                        <bitRange>[21:21]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD3_LEVEL_LOW</name>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD2_EDGE_HIGH</name>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD2_EDGE_LOW</name>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD2_LEVEL_HIGH</name>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD2_LEVEL_LOW</name>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD1_EDGE_HIGH</name>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD1_EDGE_LOW</name>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD1_LEVEL_HIGH</name>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD1_LEVEL_LOW</name>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD0_EDGE_HIGH</name>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD0_EDGE_LOW</name>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD0_LEVEL_HIGH</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD0_LEVEL_LOW</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SS_EDGE_HIGH</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SS_EDGE_LOW</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SS_LEVEL_HIGH</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SS_LEVEL_LOW</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SCLK_EDGE_HIGH</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SCLK_EDGE_LOW</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SCLK_LEVEL_HIGH</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SCLK_LEVEL_LOW</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PROC1_INTS</name>
+                <addressOffset>0x00000048</addressOffset>
+                <description>Interrupt status after masking &amp; forcing for proc1</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>GPIO_QSPI_SD3_EDGE_HIGH</name>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD3_EDGE_LOW</name>
+                        <bitRange>[22:22]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD3_LEVEL_HIGH</name>
+                        <bitRange>[21:21]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD3_LEVEL_LOW</name>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD2_EDGE_HIGH</name>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD2_EDGE_LOW</name>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD2_LEVEL_HIGH</name>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD2_LEVEL_LOW</name>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD1_EDGE_HIGH</name>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD1_EDGE_LOW</name>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD1_LEVEL_HIGH</name>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD1_LEVEL_LOW</name>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD0_EDGE_HIGH</name>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD0_EDGE_LOW</name>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD0_LEVEL_HIGH</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD0_LEVEL_LOW</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SS_EDGE_HIGH</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SS_EDGE_LOW</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SS_LEVEL_HIGH</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SS_LEVEL_LOW</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SCLK_EDGE_HIGH</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SCLK_EDGE_LOW</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SCLK_LEVEL_HIGH</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SCLK_LEVEL_LOW</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>DORMANT_WAKE_INTE</name>
+                <addressOffset>0x0000004c</addressOffset>
+                <description>Interrupt Enable for dormant_wake</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>GPIO_QSPI_SD3_EDGE_HIGH</name>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD3_EDGE_LOW</name>
+                        <bitRange>[22:22]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD3_LEVEL_HIGH</name>
+                        <bitRange>[21:21]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD3_LEVEL_LOW</name>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD2_EDGE_HIGH</name>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD2_EDGE_LOW</name>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD2_LEVEL_HIGH</name>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD2_LEVEL_LOW</name>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD1_EDGE_HIGH</name>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD1_EDGE_LOW</name>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD1_LEVEL_HIGH</name>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD1_LEVEL_LOW</name>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD0_EDGE_HIGH</name>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD0_EDGE_LOW</name>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD0_LEVEL_HIGH</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD0_LEVEL_LOW</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SS_EDGE_HIGH</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SS_EDGE_LOW</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SS_LEVEL_HIGH</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SS_LEVEL_LOW</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SCLK_EDGE_HIGH</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SCLK_EDGE_LOW</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SCLK_LEVEL_HIGH</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SCLK_LEVEL_LOW</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>DORMANT_WAKE_INTF</name>
+                <addressOffset>0x00000050</addressOffset>
+                <description>Interrupt Force for dormant_wake</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>GPIO_QSPI_SD3_EDGE_HIGH</name>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD3_EDGE_LOW</name>
+                        <bitRange>[22:22]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD3_LEVEL_HIGH</name>
+                        <bitRange>[21:21]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD3_LEVEL_LOW</name>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD2_EDGE_HIGH</name>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD2_EDGE_LOW</name>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD2_LEVEL_HIGH</name>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD2_LEVEL_LOW</name>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD1_EDGE_HIGH</name>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD1_EDGE_LOW</name>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD1_LEVEL_HIGH</name>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD1_LEVEL_LOW</name>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD0_EDGE_HIGH</name>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD0_EDGE_LOW</name>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD0_LEVEL_HIGH</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD0_LEVEL_LOW</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SS_EDGE_HIGH</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SS_EDGE_LOW</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SS_LEVEL_HIGH</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SS_LEVEL_LOW</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SCLK_EDGE_HIGH</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SCLK_EDGE_LOW</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SCLK_LEVEL_HIGH</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SCLK_LEVEL_LOW</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>DORMANT_WAKE_INTS</name>
+                <addressOffset>0x00000054</addressOffset>
+                <description>Interrupt status after masking &amp; forcing for dormant_wake</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>GPIO_QSPI_SD3_EDGE_HIGH</name>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD3_EDGE_LOW</name>
+                        <bitRange>[22:22]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD3_LEVEL_HIGH</name>
+                        <bitRange>[21:21]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD3_LEVEL_LOW</name>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD2_EDGE_HIGH</name>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD2_EDGE_LOW</name>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD2_LEVEL_HIGH</name>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD2_LEVEL_LOW</name>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD1_EDGE_HIGH</name>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD1_EDGE_LOW</name>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD1_LEVEL_HIGH</name>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD1_LEVEL_LOW</name>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD0_EDGE_HIGH</name>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD0_EDGE_LOW</name>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD0_LEVEL_HIGH</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD0_LEVEL_LOW</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SS_EDGE_HIGH</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SS_EDGE_LOW</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SS_LEVEL_HIGH</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SS_LEVEL_LOW</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SCLK_EDGE_HIGH</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SCLK_EDGE_LOW</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SCLK_LEVEL_HIGH</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SCLK_LEVEL_LOW</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+        </registers>
+    </peripheral>
+    <peripheral>
+        <name>IO_BANK0</name>
+        <baseAddress>0x40014000</baseAddress>
+        <addressBlock>
+            <offset>0</offset>
+            <size>400</size>
+            <usage>registers</usage>
+        </addressBlock>
+        <interrupt>
+            <name>IO_IRQ_BANK0</name>
+            <value>13</value>
+        </interrupt>
+        <registers>
+            <register>
+                <name>GPIO0_STATUS</name>
+                <addressOffset>0x00000000</addressOffset>
+                <description>GPIO status</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>IRQTOPROC</name>
+                        <description>interrupt to processors, after override is applied</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>IRQFROMPAD</name>
+                        <description>interrupt from pad before override is applied</description>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>INTOPERI</name>
+                        <description>input signal to peripheral, after override is applied</description>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>INFROMPAD</name>
+                        <description>input signal from pad, before override is applied</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OETOPAD</name>
+                        <description>output enable to pad after register override is applied</description>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OEFROMPERI</name>
+                        <description>output enable from selected peripheral, before register override is applied</description>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OUTTOPAD</name>
+                        <description>output signal to pad after register override is applied</description>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OUTFROMPERI</name>
+                        <description>output signal from selected peripheral, before register override is applied</description>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO0_CTRL</name>
+                <addressOffset>0x00000004</addressOffset>
+                <description>GPIO control including function select and overrides.</description>
+                <resetValue>0x0000001f</resetValue>
+                <fields>
+                    <field>
+                        <name>IRQOVER</name>
+                        <bitRange>[29:28]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>don&#39;t invert the interrupt</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>invert the interrupt</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive interrupt low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive interrupt high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>INOVER</name>
+                        <bitRange>[17:16]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>don&#39;t invert the peri input</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>invert the peri input</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive peri input low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive peri input high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>OEOVER</name>
+                        <bitRange>[13:12]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>drive output enable from peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>DISABLE</name>
+                                <value>2</value>
+                                <description>disable output</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ENABLE</name>
+                                <value>3</value>
+                                <description>enable output</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>OUTOVER</name>
+                        <bitRange>[9:8]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>drive output from peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>drive output from inverse of peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive output low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive output high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>FUNCSEL</name>
+                        <description>0-31 -&gt; selects pin function according to the gpio table 
+                            31 == NULL</description>
+                        <bitRange>[4:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>jtag_tck</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>spi0_rx</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>uart0_tx</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>i2c0_sda</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pwm_a_0</name>
+                                <value>4</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sio_0</name>
+                                <value>5</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio0_0</name>
+                                <value>6</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio1_0</name>
+                                <value>7</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>usb_muxing_overcurr_detect</name>
+                                <value>9</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>null</name>
+                                <value>31</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO1_STATUS</name>
+                <addressOffset>0x00000008</addressOffset>
+                <description>GPIO status</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>IRQTOPROC</name>
+                        <description>interrupt to processors, after override is applied</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>IRQFROMPAD</name>
+                        <description>interrupt from pad before override is applied</description>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>INTOPERI</name>
+                        <description>input signal to peripheral, after override is applied</description>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>INFROMPAD</name>
+                        <description>input signal from pad, before override is applied</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OETOPAD</name>
+                        <description>output enable to pad after register override is applied</description>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OEFROMPERI</name>
+                        <description>output enable from selected peripheral, before register override is applied</description>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OUTTOPAD</name>
+                        <description>output signal to pad after register override is applied</description>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OUTFROMPERI</name>
+                        <description>output signal from selected peripheral, before register override is applied</description>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO1_CTRL</name>
+                <addressOffset>0x0000000c</addressOffset>
+                <description>GPIO control including function select and overrides.</description>
+                <resetValue>0x0000001f</resetValue>
+                <fields>
+                    <field>
+                        <name>IRQOVER</name>
+                        <bitRange>[29:28]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>don&#39;t invert the interrupt</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>invert the interrupt</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive interrupt low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive interrupt high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>INOVER</name>
+                        <bitRange>[17:16]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>don&#39;t invert the peri input</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>invert the peri input</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive peri input low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive peri input high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>OEOVER</name>
+                        <bitRange>[13:12]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>drive output enable from peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>DISABLE</name>
+                                <value>2</value>
+                                <description>disable output</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ENABLE</name>
+                                <value>3</value>
+                                <description>enable output</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>OUTOVER</name>
+                        <bitRange>[9:8]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>drive output from peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>drive output from inverse of peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive output low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive output high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>FUNCSEL</name>
+                        <description>0-31 -&gt; selects pin function according to the gpio table 
+                            31 == NULL</description>
+                        <bitRange>[4:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>jtag_tms</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>spi0_ss_n</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>uart0_rx</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>i2c0_scl</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pwm_b_0</name>
+                                <value>4</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sio_1</name>
+                                <value>5</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio0_1</name>
+                                <value>6</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio1_1</name>
+                                <value>7</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>usb_muxing_vbus_detect</name>
+                                <value>9</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>null</name>
+                                <value>31</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO2_STATUS</name>
+                <addressOffset>0x00000010</addressOffset>
+                <description>GPIO status</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>IRQTOPROC</name>
+                        <description>interrupt to processors, after override is applied</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>IRQFROMPAD</name>
+                        <description>interrupt from pad before override is applied</description>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>INTOPERI</name>
+                        <description>input signal to peripheral, after override is applied</description>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>INFROMPAD</name>
+                        <description>input signal from pad, before override is applied</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OETOPAD</name>
+                        <description>output enable to pad after register override is applied</description>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OEFROMPERI</name>
+                        <description>output enable from selected peripheral, before register override is applied</description>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OUTTOPAD</name>
+                        <description>output signal to pad after register override is applied</description>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OUTFROMPERI</name>
+                        <description>output signal from selected peripheral, before register override is applied</description>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO2_CTRL</name>
+                <addressOffset>0x00000014</addressOffset>
+                <description>GPIO control including function select and overrides.</description>
+                <resetValue>0x0000001f</resetValue>
+                <fields>
+                    <field>
+                        <name>IRQOVER</name>
+                        <bitRange>[29:28]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>don&#39;t invert the interrupt</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>invert the interrupt</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive interrupt low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive interrupt high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>INOVER</name>
+                        <bitRange>[17:16]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>don&#39;t invert the peri input</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>invert the peri input</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive peri input low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive peri input high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>OEOVER</name>
+                        <bitRange>[13:12]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>drive output enable from peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>DISABLE</name>
+                                <value>2</value>
+                                <description>disable output</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ENABLE</name>
+                                <value>3</value>
+                                <description>enable output</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>OUTOVER</name>
+                        <bitRange>[9:8]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>drive output from peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>drive output from inverse of peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive output low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive output high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>FUNCSEL</name>
+                        <description>0-31 -&gt; selects pin function according to the gpio table 
+                            31 == NULL</description>
+                        <bitRange>[4:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>jtag_tdi</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>spi0_sclk</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>uart0_cts</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>i2c1_sda</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pwm_a_1</name>
+                                <value>4</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sio_2</name>
+                                <value>5</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio0_2</name>
+                                <value>6</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio1_2</name>
+                                <value>7</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>usb_muxing_vbus_en</name>
+                                <value>9</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>null</name>
+                                <value>31</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO3_STATUS</name>
+                <addressOffset>0x00000018</addressOffset>
+                <description>GPIO status</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>IRQTOPROC</name>
+                        <description>interrupt to processors, after override is applied</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>IRQFROMPAD</name>
+                        <description>interrupt from pad before override is applied</description>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>INTOPERI</name>
+                        <description>input signal to peripheral, after override is applied</description>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>INFROMPAD</name>
+                        <description>input signal from pad, before override is applied</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OETOPAD</name>
+                        <description>output enable to pad after register override is applied</description>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OEFROMPERI</name>
+                        <description>output enable from selected peripheral, before register override is applied</description>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OUTTOPAD</name>
+                        <description>output signal to pad after register override is applied</description>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OUTFROMPERI</name>
+                        <description>output signal from selected peripheral, before register override is applied</description>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO3_CTRL</name>
+                <addressOffset>0x0000001c</addressOffset>
+                <description>GPIO control including function select and overrides.</description>
+                <resetValue>0x0000001f</resetValue>
+                <fields>
+                    <field>
+                        <name>IRQOVER</name>
+                        <bitRange>[29:28]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>don&#39;t invert the interrupt</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>invert the interrupt</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive interrupt low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive interrupt high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>INOVER</name>
+                        <bitRange>[17:16]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>don&#39;t invert the peri input</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>invert the peri input</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive peri input low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive peri input high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>OEOVER</name>
+                        <bitRange>[13:12]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>drive output enable from peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>DISABLE</name>
+                                <value>2</value>
+                                <description>disable output</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ENABLE</name>
+                                <value>3</value>
+                                <description>enable output</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>OUTOVER</name>
+                        <bitRange>[9:8]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>drive output from peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>drive output from inverse of peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive output low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive output high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>FUNCSEL</name>
+                        <description>0-31 -&gt; selects pin function according to the gpio table 
+                            31 == NULL</description>
+                        <bitRange>[4:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>jtag_tdo</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>spi0_tx</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>uart0_rts</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>i2c1_scl</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pwm_b_1</name>
+                                <value>4</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sio_3</name>
+                                <value>5</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio0_3</name>
+                                <value>6</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio1_3</name>
+                                <value>7</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>usb_muxing_overcurr_detect</name>
+                                <value>9</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>null</name>
+                                <value>31</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO4_STATUS</name>
+                <addressOffset>0x00000020</addressOffset>
+                <description>GPIO status</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>IRQTOPROC</name>
+                        <description>interrupt to processors, after override is applied</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>IRQFROMPAD</name>
+                        <description>interrupt from pad before override is applied</description>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>INTOPERI</name>
+                        <description>input signal to peripheral, after override is applied</description>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>INFROMPAD</name>
+                        <description>input signal from pad, before override is applied</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OETOPAD</name>
+                        <description>output enable to pad after register override is applied</description>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OEFROMPERI</name>
+                        <description>output enable from selected peripheral, before register override is applied</description>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OUTTOPAD</name>
+                        <description>output signal to pad after register override is applied</description>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OUTFROMPERI</name>
+                        <description>output signal from selected peripheral, before register override is applied</description>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO4_CTRL</name>
+                <addressOffset>0x00000024</addressOffset>
+                <description>GPIO control including function select and overrides.</description>
+                <resetValue>0x0000001f</resetValue>
+                <fields>
+                    <field>
+                        <name>IRQOVER</name>
+                        <bitRange>[29:28]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>don&#39;t invert the interrupt</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>invert the interrupt</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive interrupt low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive interrupt high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>INOVER</name>
+                        <bitRange>[17:16]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>don&#39;t invert the peri input</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>invert the peri input</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive peri input low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive peri input high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>OEOVER</name>
+                        <bitRange>[13:12]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>drive output enable from peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>DISABLE</name>
+                                <value>2</value>
+                                <description>disable output</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ENABLE</name>
+                                <value>3</value>
+                                <description>enable output</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>OUTOVER</name>
+                        <bitRange>[9:8]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>drive output from peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>drive output from inverse of peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive output low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive output high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>FUNCSEL</name>
+                        <description>0-31 -&gt; selects pin function according to the gpio table 
+                            31 == NULL</description>
+                        <bitRange>[4:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>spi0_rx</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>uart1_tx</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>i2c0_sda</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pwm_a_2</name>
+                                <value>4</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sio_4</name>
+                                <value>5</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio0_4</name>
+                                <value>6</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio1_4</name>
+                                <value>7</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>usb_muxing_vbus_detect</name>
+                                <value>9</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>null</name>
+                                <value>31</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO5_STATUS</name>
+                <addressOffset>0x00000028</addressOffset>
+                <description>GPIO status</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>IRQTOPROC</name>
+                        <description>interrupt to processors, after override is applied</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>IRQFROMPAD</name>
+                        <description>interrupt from pad before override is applied</description>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>INTOPERI</name>
+                        <description>input signal to peripheral, after override is applied</description>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>INFROMPAD</name>
+                        <description>input signal from pad, before override is applied</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OETOPAD</name>
+                        <description>output enable to pad after register override is applied</description>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OEFROMPERI</name>
+                        <description>output enable from selected peripheral, before register override is applied</description>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OUTTOPAD</name>
+                        <description>output signal to pad after register override is applied</description>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OUTFROMPERI</name>
+                        <description>output signal from selected peripheral, before register override is applied</description>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO5_CTRL</name>
+                <addressOffset>0x0000002c</addressOffset>
+                <description>GPIO control including function select and overrides.</description>
+                <resetValue>0x0000001f</resetValue>
+                <fields>
+                    <field>
+                        <name>IRQOVER</name>
+                        <bitRange>[29:28]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>don&#39;t invert the interrupt</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>invert the interrupt</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive interrupt low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive interrupt high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>INOVER</name>
+                        <bitRange>[17:16]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>don&#39;t invert the peri input</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>invert the peri input</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive peri input low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive peri input high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>OEOVER</name>
+                        <bitRange>[13:12]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>drive output enable from peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>DISABLE</name>
+                                <value>2</value>
+                                <description>disable output</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ENABLE</name>
+                                <value>3</value>
+                                <description>enable output</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>OUTOVER</name>
+                        <bitRange>[9:8]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>drive output from peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>drive output from inverse of peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive output low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive output high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>FUNCSEL</name>
+                        <description>0-31 -&gt; selects pin function according to the gpio table 
+                            31 == NULL</description>
+                        <bitRange>[4:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>spi0_ss_n</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>uart1_rx</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>i2c0_scl</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pwm_b_2</name>
+                                <value>4</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sio_5</name>
+                                <value>5</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio0_5</name>
+                                <value>6</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio1_5</name>
+                                <value>7</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>usb_muxing_vbus_en</name>
+                                <value>9</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>null</name>
+                                <value>31</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO6_STATUS</name>
+                <addressOffset>0x00000030</addressOffset>
+                <description>GPIO status</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>IRQTOPROC</name>
+                        <description>interrupt to processors, after override is applied</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>IRQFROMPAD</name>
+                        <description>interrupt from pad before override is applied</description>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>INTOPERI</name>
+                        <description>input signal to peripheral, after override is applied</description>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>INFROMPAD</name>
+                        <description>input signal from pad, before override is applied</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OETOPAD</name>
+                        <description>output enable to pad after register override is applied</description>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OEFROMPERI</name>
+                        <description>output enable from selected peripheral, before register override is applied</description>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OUTTOPAD</name>
+                        <description>output signal to pad after register override is applied</description>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OUTFROMPERI</name>
+                        <description>output signal from selected peripheral, before register override is applied</description>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO6_CTRL</name>
+                <addressOffset>0x00000034</addressOffset>
+                <description>GPIO control including function select and overrides.</description>
+                <resetValue>0x0000001f</resetValue>
+                <fields>
+                    <field>
+                        <name>IRQOVER</name>
+                        <bitRange>[29:28]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>don&#39;t invert the interrupt</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>invert the interrupt</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive interrupt low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive interrupt high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>INOVER</name>
+                        <bitRange>[17:16]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>don&#39;t invert the peri input</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>invert the peri input</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive peri input low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive peri input high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>OEOVER</name>
+                        <bitRange>[13:12]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>drive output enable from peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>DISABLE</name>
+                                <value>2</value>
+                                <description>disable output</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ENABLE</name>
+                                <value>3</value>
+                                <description>enable output</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>OUTOVER</name>
+                        <bitRange>[9:8]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>drive output from peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>drive output from inverse of peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive output low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive output high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>FUNCSEL</name>
+                        <description>0-31 -&gt; selects pin function according to the gpio table 
+                            31 == NULL</description>
+                        <bitRange>[4:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>spi0_sclk</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>uart1_cts</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>i2c1_sda</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pwm_a_3</name>
+                                <value>4</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sio_6</name>
+                                <value>5</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio0_6</name>
+                                <value>6</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio1_6</name>
+                                <value>7</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>usb_muxing_extphy_softcon</name>
+                                <value>8</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>usb_muxing_overcurr_detect</name>
+                                <value>9</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>null</name>
+                                <value>31</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO7_STATUS</name>
+                <addressOffset>0x00000038</addressOffset>
+                <description>GPIO status</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>IRQTOPROC</name>
+                        <description>interrupt to processors, after override is applied</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>IRQFROMPAD</name>
+                        <description>interrupt from pad before override is applied</description>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>INTOPERI</name>
+                        <description>input signal to peripheral, after override is applied</description>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>INFROMPAD</name>
+                        <description>input signal from pad, before override is applied</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OETOPAD</name>
+                        <description>output enable to pad after register override is applied</description>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OEFROMPERI</name>
+                        <description>output enable from selected peripheral, before register override is applied</description>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OUTTOPAD</name>
+                        <description>output signal to pad after register override is applied</description>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OUTFROMPERI</name>
+                        <description>output signal from selected peripheral, before register override is applied</description>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO7_CTRL</name>
+                <addressOffset>0x0000003c</addressOffset>
+                <description>GPIO control including function select and overrides.</description>
+                <resetValue>0x0000001f</resetValue>
+                <fields>
+                    <field>
+                        <name>IRQOVER</name>
+                        <bitRange>[29:28]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>don&#39;t invert the interrupt</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>invert the interrupt</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive interrupt low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive interrupt high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>INOVER</name>
+                        <bitRange>[17:16]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>don&#39;t invert the peri input</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>invert the peri input</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive peri input low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive peri input high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>OEOVER</name>
+                        <bitRange>[13:12]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>drive output enable from peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>DISABLE</name>
+                                <value>2</value>
+                                <description>disable output</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ENABLE</name>
+                                <value>3</value>
+                                <description>enable output</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>OUTOVER</name>
+                        <bitRange>[9:8]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>drive output from peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>drive output from inverse of peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive output low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive output high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>FUNCSEL</name>
+                        <description>0-31 -&gt; selects pin function according to the gpio table 
+                            31 == NULL</description>
+                        <bitRange>[4:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>spi0_tx</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>uart1_rts</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>i2c1_scl</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pwm_b_3</name>
+                                <value>4</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sio_7</name>
+                                <value>5</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio0_7</name>
+                                <value>6</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio1_7</name>
+                                <value>7</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>usb_muxing_extphy_oe_n</name>
+                                <value>8</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>usb_muxing_vbus_detect</name>
+                                <value>9</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>null</name>
+                                <value>31</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO8_STATUS</name>
+                <addressOffset>0x00000040</addressOffset>
+                <description>GPIO status</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>IRQTOPROC</name>
+                        <description>interrupt to processors, after override is applied</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>IRQFROMPAD</name>
+                        <description>interrupt from pad before override is applied</description>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>INTOPERI</name>
+                        <description>input signal to peripheral, after override is applied</description>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>INFROMPAD</name>
+                        <description>input signal from pad, before override is applied</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OETOPAD</name>
+                        <description>output enable to pad after register override is applied</description>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OEFROMPERI</name>
+                        <description>output enable from selected peripheral, before register override is applied</description>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OUTTOPAD</name>
+                        <description>output signal to pad after register override is applied</description>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OUTFROMPERI</name>
+                        <description>output signal from selected peripheral, before register override is applied</description>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO8_CTRL</name>
+                <addressOffset>0x00000044</addressOffset>
+                <description>GPIO control including function select and overrides.</description>
+                <resetValue>0x0000001f</resetValue>
+                <fields>
+                    <field>
+                        <name>IRQOVER</name>
+                        <bitRange>[29:28]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>don&#39;t invert the interrupt</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>invert the interrupt</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive interrupt low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive interrupt high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>INOVER</name>
+                        <bitRange>[17:16]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>don&#39;t invert the peri input</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>invert the peri input</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive peri input low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive peri input high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>OEOVER</name>
+                        <bitRange>[13:12]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>drive output enable from peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>DISABLE</name>
+                                <value>2</value>
+                                <description>disable output</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ENABLE</name>
+                                <value>3</value>
+                                <description>enable output</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>OUTOVER</name>
+                        <bitRange>[9:8]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>drive output from peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>drive output from inverse of peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive output low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive output high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>FUNCSEL</name>
+                        <description>0-31 -&gt; selects pin function according to the gpio table 
+                            31 == NULL</description>
+                        <bitRange>[4:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>spi1_rx</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>uart1_tx</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>i2c0_sda</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pwm_a_4</name>
+                                <value>4</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sio_8</name>
+                                <value>5</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio0_8</name>
+                                <value>6</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio1_8</name>
+                                <value>7</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>usb_muxing_extphy_rcv</name>
+                                <value>8</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>usb_muxing_vbus_en</name>
+                                <value>9</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>null</name>
+                                <value>31</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO9_STATUS</name>
+                <addressOffset>0x00000048</addressOffset>
+                <description>GPIO status</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>IRQTOPROC</name>
+                        <description>interrupt to processors, after override is applied</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>IRQFROMPAD</name>
+                        <description>interrupt from pad before override is applied</description>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>INTOPERI</name>
+                        <description>input signal to peripheral, after override is applied</description>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>INFROMPAD</name>
+                        <description>input signal from pad, before override is applied</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OETOPAD</name>
+                        <description>output enable to pad after register override is applied</description>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OEFROMPERI</name>
+                        <description>output enable from selected peripheral, before register override is applied</description>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OUTTOPAD</name>
+                        <description>output signal to pad after register override is applied</description>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OUTFROMPERI</name>
+                        <description>output signal from selected peripheral, before register override is applied</description>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO9_CTRL</name>
+                <addressOffset>0x0000004c</addressOffset>
+                <description>GPIO control including function select and overrides.</description>
+                <resetValue>0x0000001f</resetValue>
+                <fields>
+                    <field>
+                        <name>IRQOVER</name>
+                        <bitRange>[29:28]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>don&#39;t invert the interrupt</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>invert the interrupt</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive interrupt low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive interrupt high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>INOVER</name>
+                        <bitRange>[17:16]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>don&#39;t invert the peri input</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>invert the peri input</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive peri input low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive peri input high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>OEOVER</name>
+                        <bitRange>[13:12]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>drive output enable from peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>DISABLE</name>
+                                <value>2</value>
+                                <description>disable output</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ENABLE</name>
+                                <value>3</value>
+                                <description>enable output</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>OUTOVER</name>
+                        <bitRange>[9:8]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>drive output from peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>drive output from inverse of peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive output low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive output high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>FUNCSEL</name>
+                        <description>0-31 -&gt; selects pin function according to the gpio table 
+                            31 == NULL</description>
+                        <bitRange>[4:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>spi1_ss_n</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>uart1_rx</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>i2c0_scl</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pwm_b_4</name>
+                                <value>4</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sio_9</name>
+                                <value>5</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio0_9</name>
+                                <value>6</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio1_9</name>
+                                <value>7</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>usb_muxing_extphy_vp</name>
+                                <value>8</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>usb_muxing_overcurr_detect</name>
+                                <value>9</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>null</name>
+                                <value>31</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO10_STATUS</name>
+                <addressOffset>0x00000050</addressOffset>
+                <description>GPIO status</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>IRQTOPROC</name>
+                        <description>interrupt to processors, after override is applied</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>IRQFROMPAD</name>
+                        <description>interrupt from pad before override is applied</description>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>INTOPERI</name>
+                        <description>input signal to peripheral, after override is applied</description>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>INFROMPAD</name>
+                        <description>input signal from pad, before override is applied</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OETOPAD</name>
+                        <description>output enable to pad after register override is applied</description>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OEFROMPERI</name>
+                        <description>output enable from selected peripheral, before register override is applied</description>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OUTTOPAD</name>
+                        <description>output signal to pad after register override is applied</description>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OUTFROMPERI</name>
+                        <description>output signal from selected peripheral, before register override is applied</description>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO10_CTRL</name>
+                <addressOffset>0x00000054</addressOffset>
+                <description>GPIO control including function select and overrides.</description>
+                <resetValue>0x0000001f</resetValue>
+                <fields>
+                    <field>
+                        <name>IRQOVER</name>
+                        <bitRange>[29:28]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>don&#39;t invert the interrupt</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>invert the interrupt</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive interrupt low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive interrupt high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>INOVER</name>
+                        <bitRange>[17:16]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>don&#39;t invert the peri input</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>invert the peri input</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive peri input low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive peri input high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>OEOVER</name>
+                        <bitRange>[13:12]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>drive output enable from peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>DISABLE</name>
+                                <value>2</value>
+                                <description>disable output</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ENABLE</name>
+                                <value>3</value>
+                                <description>enable output</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>OUTOVER</name>
+                        <bitRange>[9:8]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>drive output from peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>drive output from inverse of peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive output low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive output high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>FUNCSEL</name>
+                        <description>0-31 -&gt; selects pin function according to the gpio table 
+                            31 == NULL</description>
+                        <bitRange>[4:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>spi1_sclk</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>uart1_cts</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>i2c1_sda</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pwm_a_5</name>
+                                <value>4</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sio_10</name>
+                                <value>5</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio0_10</name>
+                                <value>6</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio1_10</name>
+                                <value>7</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>usb_muxing_extphy_vm</name>
+                                <value>8</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>usb_muxing_vbus_detect</name>
+                                <value>9</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>null</name>
+                                <value>31</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO11_STATUS</name>
+                <addressOffset>0x00000058</addressOffset>
+                <description>GPIO status</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>IRQTOPROC</name>
+                        <description>interrupt to processors, after override is applied</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>IRQFROMPAD</name>
+                        <description>interrupt from pad before override is applied</description>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>INTOPERI</name>
+                        <description>input signal to peripheral, after override is applied</description>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>INFROMPAD</name>
+                        <description>input signal from pad, before override is applied</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OETOPAD</name>
+                        <description>output enable to pad after register override is applied</description>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OEFROMPERI</name>
+                        <description>output enable from selected peripheral, before register override is applied</description>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OUTTOPAD</name>
+                        <description>output signal to pad after register override is applied</description>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OUTFROMPERI</name>
+                        <description>output signal from selected peripheral, before register override is applied</description>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO11_CTRL</name>
+                <addressOffset>0x0000005c</addressOffset>
+                <description>GPIO control including function select and overrides.</description>
+                <resetValue>0x0000001f</resetValue>
+                <fields>
+                    <field>
+                        <name>IRQOVER</name>
+                        <bitRange>[29:28]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>don&#39;t invert the interrupt</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>invert the interrupt</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive interrupt low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive interrupt high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>INOVER</name>
+                        <bitRange>[17:16]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>don&#39;t invert the peri input</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>invert the peri input</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive peri input low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive peri input high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>OEOVER</name>
+                        <bitRange>[13:12]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>drive output enable from peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>DISABLE</name>
+                                <value>2</value>
+                                <description>disable output</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ENABLE</name>
+                                <value>3</value>
+                                <description>enable output</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>OUTOVER</name>
+                        <bitRange>[9:8]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>drive output from peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>drive output from inverse of peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive output low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive output high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>FUNCSEL</name>
+                        <description>0-31 -&gt; selects pin function according to the gpio table 
+                            31 == NULL</description>
+                        <bitRange>[4:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>spi1_tx</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>uart1_rts</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>i2c1_scl</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pwm_b_5</name>
+                                <value>4</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sio_11</name>
+                                <value>5</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio0_11</name>
+                                <value>6</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio1_11</name>
+                                <value>7</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>usb_muxing_extphy_suspnd</name>
+                                <value>8</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>usb_muxing_vbus_en</name>
+                                <value>9</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>null</name>
+                                <value>31</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO12_STATUS</name>
+                <addressOffset>0x00000060</addressOffset>
+                <description>GPIO status</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>IRQTOPROC</name>
+                        <description>interrupt to processors, after override is applied</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>IRQFROMPAD</name>
+                        <description>interrupt from pad before override is applied</description>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>INTOPERI</name>
+                        <description>input signal to peripheral, after override is applied</description>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>INFROMPAD</name>
+                        <description>input signal from pad, before override is applied</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OETOPAD</name>
+                        <description>output enable to pad after register override is applied</description>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OEFROMPERI</name>
+                        <description>output enable from selected peripheral, before register override is applied</description>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OUTTOPAD</name>
+                        <description>output signal to pad after register override is applied</description>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OUTFROMPERI</name>
+                        <description>output signal from selected peripheral, before register override is applied</description>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO12_CTRL</name>
+                <addressOffset>0x00000064</addressOffset>
+                <description>GPIO control including function select and overrides.</description>
+                <resetValue>0x0000001f</resetValue>
+                <fields>
+                    <field>
+                        <name>IRQOVER</name>
+                        <bitRange>[29:28]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>don&#39;t invert the interrupt</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>invert the interrupt</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive interrupt low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive interrupt high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>INOVER</name>
+                        <bitRange>[17:16]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>don&#39;t invert the peri input</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>invert the peri input</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive peri input low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive peri input high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>OEOVER</name>
+                        <bitRange>[13:12]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>drive output enable from peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>DISABLE</name>
+                                <value>2</value>
+                                <description>disable output</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ENABLE</name>
+                                <value>3</value>
+                                <description>enable output</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>OUTOVER</name>
+                        <bitRange>[9:8]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>drive output from peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>drive output from inverse of peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive output low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive output high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>FUNCSEL</name>
+                        <description>0-31 -&gt; selects pin function according to the gpio table 
+                            31 == NULL</description>
+                        <bitRange>[4:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>spi1_rx</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>uart0_tx</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>i2c0_sda</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pwm_a_6</name>
+                                <value>4</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sio_12</name>
+                                <value>5</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio0_12</name>
+                                <value>6</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio1_12</name>
+                                <value>7</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>usb_muxing_extphy_speed</name>
+                                <value>8</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>usb_muxing_overcurr_detect</name>
+                                <value>9</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>null</name>
+                                <value>31</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO13_STATUS</name>
+                <addressOffset>0x00000068</addressOffset>
+                <description>GPIO status</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>IRQTOPROC</name>
+                        <description>interrupt to processors, after override is applied</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>IRQFROMPAD</name>
+                        <description>interrupt from pad before override is applied</description>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>INTOPERI</name>
+                        <description>input signal to peripheral, after override is applied</description>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>INFROMPAD</name>
+                        <description>input signal from pad, before override is applied</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OETOPAD</name>
+                        <description>output enable to pad after register override is applied</description>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OEFROMPERI</name>
+                        <description>output enable from selected peripheral, before register override is applied</description>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OUTTOPAD</name>
+                        <description>output signal to pad after register override is applied</description>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OUTFROMPERI</name>
+                        <description>output signal from selected peripheral, before register override is applied</description>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO13_CTRL</name>
+                <addressOffset>0x0000006c</addressOffset>
+                <description>GPIO control including function select and overrides.</description>
+                <resetValue>0x0000001f</resetValue>
+                <fields>
+                    <field>
+                        <name>IRQOVER</name>
+                        <bitRange>[29:28]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>don&#39;t invert the interrupt</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>invert the interrupt</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive interrupt low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive interrupt high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>INOVER</name>
+                        <bitRange>[17:16]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>don&#39;t invert the peri input</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>invert the peri input</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive peri input low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive peri input high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>OEOVER</name>
+                        <bitRange>[13:12]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>drive output enable from peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>DISABLE</name>
+                                <value>2</value>
+                                <description>disable output</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ENABLE</name>
+                                <value>3</value>
+                                <description>enable output</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>OUTOVER</name>
+                        <bitRange>[9:8]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>drive output from peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>drive output from inverse of peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive output low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive output high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>FUNCSEL</name>
+                        <description>0-31 -&gt; selects pin function according to the gpio table 
+                            31 == NULL</description>
+                        <bitRange>[4:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>spi1_ss_n</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>uart0_rx</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>i2c0_scl</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pwm_b_6</name>
+                                <value>4</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sio_13</name>
+                                <value>5</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio0_13</name>
+                                <value>6</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio1_13</name>
+                                <value>7</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>usb_muxing_extphy_vpo</name>
+                                <value>8</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>usb_muxing_vbus_detect</name>
+                                <value>9</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>null</name>
+                                <value>31</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO14_STATUS</name>
+                <addressOffset>0x00000070</addressOffset>
+                <description>GPIO status</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>IRQTOPROC</name>
+                        <description>interrupt to processors, after override is applied</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>IRQFROMPAD</name>
+                        <description>interrupt from pad before override is applied</description>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>INTOPERI</name>
+                        <description>input signal to peripheral, after override is applied</description>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>INFROMPAD</name>
+                        <description>input signal from pad, before override is applied</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OETOPAD</name>
+                        <description>output enable to pad after register override is applied</description>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OEFROMPERI</name>
+                        <description>output enable from selected peripheral, before register override is applied</description>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OUTTOPAD</name>
+                        <description>output signal to pad after register override is applied</description>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OUTFROMPERI</name>
+                        <description>output signal from selected peripheral, before register override is applied</description>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO14_CTRL</name>
+                <addressOffset>0x00000074</addressOffset>
+                <description>GPIO control including function select and overrides.</description>
+                <resetValue>0x0000001f</resetValue>
+                <fields>
+                    <field>
+                        <name>IRQOVER</name>
+                        <bitRange>[29:28]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>don&#39;t invert the interrupt</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>invert the interrupt</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive interrupt low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive interrupt high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>INOVER</name>
+                        <bitRange>[17:16]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>don&#39;t invert the peri input</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>invert the peri input</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive peri input low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive peri input high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>OEOVER</name>
+                        <bitRange>[13:12]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>drive output enable from peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>DISABLE</name>
+                                <value>2</value>
+                                <description>disable output</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ENABLE</name>
+                                <value>3</value>
+                                <description>enable output</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>OUTOVER</name>
+                        <bitRange>[9:8]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>drive output from peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>drive output from inverse of peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive output low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive output high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>FUNCSEL</name>
+                        <description>0-31 -&gt; selects pin function according to the gpio table 
+                            31 == NULL</description>
+                        <bitRange>[4:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>spi1_sclk</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>uart0_cts</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>i2c1_sda</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pwm_a_7</name>
+                                <value>4</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sio_14</name>
+                                <value>5</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio0_14</name>
+                                <value>6</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio1_14</name>
+                                <value>7</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>usb_muxing_extphy_vmo</name>
+                                <value>8</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>usb_muxing_vbus_en</name>
+                                <value>9</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>null</name>
+                                <value>31</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO15_STATUS</name>
+                <addressOffset>0x00000078</addressOffset>
+                <description>GPIO status</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>IRQTOPROC</name>
+                        <description>interrupt to processors, after override is applied</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>IRQFROMPAD</name>
+                        <description>interrupt from pad before override is applied</description>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>INTOPERI</name>
+                        <description>input signal to peripheral, after override is applied</description>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>INFROMPAD</name>
+                        <description>input signal from pad, before override is applied</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OETOPAD</name>
+                        <description>output enable to pad after register override is applied</description>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OEFROMPERI</name>
+                        <description>output enable from selected peripheral, before register override is applied</description>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OUTTOPAD</name>
+                        <description>output signal to pad after register override is applied</description>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OUTFROMPERI</name>
+                        <description>output signal from selected peripheral, before register override is applied</description>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO15_CTRL</name>
+                <addressOffset>0x0000007c</addressOffset>
+                <description>GPIO control including function select and overrides.</description>
+                <resetValue>0x0000001f</resetValue>
+                <fields>
+                    <field>
+                        <name>IRQOVER</name>
+                        <bitRange>[29:28]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>don&#39;t invert the interrupt</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>invert the interrupt</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive interrupt low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive interrupt high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>INOVER</name>
+                        <bitRange>[17:16]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>don&#39;t invert the peri input</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>invert the peri input</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive peri input low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive peri input high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>OEOVER</name>
+                        <bitRange>[13:12]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>drive output enable from peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>DISABLE</name>
+                                <value>2</value>
+                                <description>disable output</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ENABLE</name>
+                                <value>3</value>
+                                <description>enable output</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>OUTOVER</name>
+                        <bitRange>[9:8]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>drive output from peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>drive output from inverse of peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive output low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive output high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>FUNCSEL</name>
+                        <description>0-31 -&gt; selects pin function according to the gpio table 
+                            31 == NULL</description>
+                        <bitRange>[4:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>spi1_tx</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>uart0_rts</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>i2c1_scl</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pwm_b_7</name>
+                                <value>4</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sio_15</name>
+                                <value>5</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio0_15</name>
+                                <value>6</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio1_15</name>
+                                <value>7</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>usb_muxing_digital_dp</name>
+                                <value>8</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>usb_muxing_overcurr_detect</name>
+                                <value>9</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>null</name>
+                                <value>31</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO16_STATUS</name>
+                <addressOffset>0x00000080</addressOffset>
+                <description>GPIO status</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>IRQTOPROC</name>
+                        <description>interrupt to processors, after override is applied</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>IRQFROMPAD</name>
+                        <description>interrupt from pad before override is applied</description>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>INTOPERI</name>
+                        <description>input signal to peripheral, after override is applied</description>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>INFROMPAD</name>
+                        <description>input signal from pad, before override is applied</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OETOPAD</name>
+                        <description>output enable to pad after register override is applied</description>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OEFROMPERI</name>
+                        <description>output enable from selected peripheral, before register override is applied</description>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OUTTOPAD</name>
+                        <description>output signal to pad after register override is applied</description>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OUTFROMPERI</name>
+                        <description>output signal from selected peripheral, before register override is applied</description>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO16_CTRL</name>
+                <addressOffset>0x00000084</addressOffset>
+                <description>GPIO control including function select and overrides.</description>
+                <resetValue>0x0000001f</resetValue>
+                <fields>
+                    <field>
+                        <name>IRQOVER</name>
+                        <bitRange>[29:28]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>don&#39;t invert the interrupt</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>invert the interrupt</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive interrupt low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive interrupt high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>INOVER</name>
+                        <bitRange>[17:16]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>don&#39;t invert the peri input</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>invert the peri input</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive peri input low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive peri input high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>OEOVER</name>
+                        <bitRange>[13:12]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>drive output enable from peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>DISABLE</name>
+                                <value>2</value>
+                                <description>disable output</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ENABLE</name>
+                                <value>3</value>
+                                <description>enable output</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>OUTOVER</name>
+                        <bitRange>[9:8]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>drive output from peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>drive output from inverse of peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive output low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive output high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>FUNCSEL</name>
+                        <description>0-31 -&gt; selects pin function according to the gpio table 
+                            31 == NULL</description>
+                        <bitRange>[4:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>spi0_rx</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>uart0_tx</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>i2c0_sda</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pwm_a_0</name>
+                                <value>4</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sio_16</name>
+                                <value>5</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio0_16</name>
+                                <value>6</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio1_16</name>
+                                <value>7</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>usb_muxing_digital_dm</name>
+                                <value>8</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>usb_muxing_vbus_detect</name>
+                                <value>9</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>null</name>
+                                <value>31</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO17_STATUS</name>
+                <addressOffset>0x00000088</addressOffset>
+                <description>GPIO status</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>IRQTOPROC</name>
+                        <description>interrupt to processors, after override is applied</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>IRQFROMPAD</name>
+                        <description>interrupt from pad before override is applied</description>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>INTOPERI</name>
+                        <description>input signal to peripheral, after override is applied</description>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>INFROMPAD</name>
+                        <description>input signal from pad, before override is applied</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OETOPAD</name>
+                        <description>output enable to pad after register override is applied</description>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OEFROMPERI</name>
+                        <description>output enable from selected peripheral, before register override is applied</description>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OUTTOPAD</name>
+                        <description>output signal to pad after register override is applied</description>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OUTFROMPERI</name>
+                        <description>output signal from selected peripheral, before register override is applied</description>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO17_CTRL</name>
+                <addressOffset>0x0000008c</addressOffset>
+                <description>GPIO control including function select and overrides.</description>
+                <resetValue>0x0000001f</resetValue>
+                <fields>
+                    <field>
+                        <name>IRQOVER</name>
+                        <bitRange>[29:28]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>don&#39;t invert the interrupt</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>invert the interrupt</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive interrupt low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive interrupt high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>INOVER</name>
+                        <bitRange>[17:16]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>don&#39;t invert the peri input</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>invert the peri input</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive peri input low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive peri input high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>OEOVER</name>
+                        <bitRange>[13:12]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>drive output enable from peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>DISABLE</name>
+                                <value>2</value>
+                                <description>disable output</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ENABLE</name>
+                                <value>3</value>
+                                <description>enable output</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>OUTOVER</name>
+                        <bitRange>[9:8]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>drive output from peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>drive output from inverse of peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive output low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive output high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>FUNCSEL</name>
+                        <description>0-31 -&gt; selects pin function according to the gpio table 
+                            31 == NULL</description>
+                        <bitRange>[4:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>spi0_ss_n</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>uart0_rx</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>i2c0_scl</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pwm_b_0</name>
+                                <value>4</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sio_17</name>
+                                <value>5</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio0_17</name>
+                                <value>6</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio1_17</name>
+                                <value>7</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>usb_muxing_vbus_en</name>
+                                <value>9</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>null</name>
+                                <value>31</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO18_STATUS</name>
+                <addressOffset>0x00000090</addressOffset>
+                <description>GPIO status</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>IRQTOPROC</name>
+                        <description>interrupt to processors, after override is applied</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>IRQFROMPAD</name>
+                        <description>interrupt from pad before override is applied</description>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>INTOPERI</name>
+                        <description>input signal to peripheral, after override is applied</description>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>INFROMPAD</name>
+                        <description>input signal from pad, before override is applied</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OETOPAD</name>
+                        <description>output enable to pad after register override is applied</description>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OEFROMPERI</name>
+                        <description>output enable from selected peripheral, before register override is applied</description>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OUTTOPAD</name>
+                        <description>output signal to pad after register override is applied</description>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OUTFROMPERI</name>
+                        <description>output signal from selected peripheral, before register override is applied</description>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO18_CTRL</name>
+                <addressOffset>0x00000094</addressOffset>
+                <description>GPIO control including function select and overrides.</description>
+                <resetValue>0x0000001f</resetValue>
+                <fields>
+                    <field>
+                        <name>IRQOVER</name>
+                        <bitRange>[29:28]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>don&#39;t invert the interrupt</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>invert the interrupt</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive interrupt low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive interrupt high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>INOVER</name>
+                        <bitRange>[17:16]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>don&#39;t invert the peri input</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>invert the peri input</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive peri input low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive peri input high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>OEOVER</name>
+                        <bitRange>[13:12]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>drive output enable from peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>DISABLE</name>
+                                <value>2</value>
+                                <description>disable output</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ENABLE</name>
+                                <value>3</value>
+                                <description>enable output</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>OUTOVER</name>
+                        <bitRange>[9:8]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>drive output from peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>drive output from inverse of peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive output low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive output high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>FUNCSEL</name>
+                        <description>0-31 -&gt; selects pin function according to the gpio table 
+                            31 == NULL</description>
+                        <bitRange>[4:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>spi0_sclk</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>uart0_cts</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>i2c1_sda</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pwm_a_1</name>
+                                <value>4</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sio_18</name>
+                                <value>5</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio0_18</name>
+                                <value>6</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio1_18</name>
+                                <value>7</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>usb_muxing_overcurr_detect</name>
+                                <value>9</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>null</name>
+                                <value>31</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO19_STATUS</name>
+                <addressOffset>0x00000098</addressOffset>
+                <description>GPIO status</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>IRQTOPROC</name>
+                        <description>interrupt to processors, after override is applied</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>IRQFROMPAD</name>
+                        <description>interrupt from pad before override is applied</description>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>INTOPERI</name>
+                        <description>input signal to peripheral, after override is applied</description>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>INFROMPAD</name>
+                        <description>input signal from pad, before override is applied</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OETOPAD</name>
+                        <description>output enable to pad after register override is applied</description>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OEFROMPERI</name>
+                        <description>output enable from selected peripheral, before register override is applied</description>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OUTTOPAD</name>
+                        <description>output signal to pad after register override is applied</description>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OUTFROMPERI</name>
+                        <description>output signal from selected peripheral, before register override is applied</description>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO19_CTRL</name>
+                <addressOffset>0x0000009c</addressOffset>
+                <description>GPIO control including function select and overrides.</description>
+                <resetValue>0x0000001f</resetValue>
+                <fields>
+                    <field>
+                        <name>IRQOVER</name>
+                        <bitRange>[29:28]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>don&#39;t invert the interrupt</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>invert the interrupt</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive interrupt low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive interrupt high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>INOVER</name>
+                        <bitRange>[17:16]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>don&#39;t invert the peri input</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>invert the peri input</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive peri input low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive peri input high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>OEOVER</name>
+                        <bitRange>[13:12]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>drive output enable from peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>DISABLE</name>
+                                <value>2</value>
+                                <description>disable output</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ENABLE</name>
+                                <value>3</value>
+                                <description>enable output</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>OUTOVER</name>
+                        <bitRange>[9:8]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>drive output from peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>drive output from inverse of peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive output low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive output high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>FUNCSEL</name>
+                        <description>0-31 -&gt; selects pin function according to the gpio table 
+                            31 == NULL</description>
+                        <bitRange>[4:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>spi0_tx</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>uart0_rts</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>i2c1_scl</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pwm_b_1</name>
+                                <value>4</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sio_19</name>
+                                <value>5</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio0_19</name>
+                                <value>6</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio1_19</name>
+                                <value>7</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>usb_muxing_vbus_detect</name>
+                                <value>9</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>null</name>
+                                <value>31</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO20_STATUS</name>
+                <addressOffset>0x000000a0</addressOffset>
+                <description>GPIO status</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>IRQTOPROC</name>
+                        <description>interrupt to processors, after override is applied</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>IRQFROMPAD</name>
+                        <description>interrupt from pad before override is applied</description>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>INTOPERI</name>
+                        <description>input signal to peripheral, after override is applied</description>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>INFROMPAD</name>
+                        <description>input signal from pad, before override is applied</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OETOPAD</name>
+                        <description>output enable to pad after register override is applied</description>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OEFROMPERI</name>
+                        <description>output enable from selected peripheral, before register override is applied</description>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OUTTOPAD</name>
+                        <description>output signal to pad after register override is applied</description>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OUTFROMPERI</name>
+                        <description>output signal from selected peripheral, before register override is applied</description>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO20_CTRL</name>
+                <addressOffset>0x000000a4</addressOffset>
+                <description>GPIO control including function select and overrides.</description>
+                <resetValue>0x0000001f</resetValue>
+                <fields>
+                    <field>
+                        <name>IRQOVER</name>
+                        <bitRange>[29:28]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>don&#39;t invert the interrupt</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>invert the interrupt</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive interrupt low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive interrupt high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>INOVER</name>
+                        <bitRange>[17:16]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>don&#39;t invert the peri input</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>invert the peri input</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive peri input low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive peri input high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>OEOVER</name>
+                        <bitRange>[13:12]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>drive output enable from peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>DISABLE</name>
+                                <value>2</value>
+                                <description>disable output</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ENABLE</name>
+                                <value>3</value>
+                                <description>enable output</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>OUTOVER</name>
+                        <bitRange>[9:8]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>drive output from peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>drive output from inverse of peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive output low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive output high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>FUNCSEL</name>
+                        <description>0-31 -&gt; selects pin function according to the gpio table 
+                            31 == NULL</description>
+                        <bitRange>[4:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>spi0_rx</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>uart1_tx</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>i2c0_sda</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pwm_a_2</name>
+                                <value>4</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sio_20</name>
+                                <value>5</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio0_20</name>
+                                <value>6</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio1_20</name>
+                                <value>7</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>clocks_gpin_0</name>
+                                <value>8</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>usb_muxing_vbus_en</name>
+                                <value>9</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>null</name>
+                                <value>31</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO21_STATUS</name>
+                <addressOffset>0x000000a8</addressOffset>
+                <description>GPIO status</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>IRQTOPROC</name>
+                        <description>interrupt to processors, after override is applied</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>IRQFROMPAD</name>
+                        <description>interrupt from pad before override is applied</description>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>INTOPERI</name>
+                        <description>input signal to peripheral, after override is applied</description>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>INFROMPAD</name>
+                        <description>input signal from pad, before override is applied</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OETOPAD</name>
+                        <description>output enable to pad after register override is applied</description>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OEFROMPERI</name>
+                        <description>output enable from selected peripheral, before register override is applied</description>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OUTTOPAD</name>
+                        <description>output signal to pad after register override is applied</description>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OUTFROMPERI</name>
+                        <description>output signal from selected peripheral, before register override is applied</description>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO21_CTRL</name>
+                <addressOffset>0x000000ac</addressOffset>
+                <description>GPIO control including function select and overrides.</description>
+                <resetValue>0x0000001f</resetValue>
+                <fields>
+                    <field>
+                        <name>IRQOVER</name>
+                        <bitRange>[29:28]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>don&#39;t invert the interrupt</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>invert the interrupt</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive interrupt low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive interrupt high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>INOVER</name>
+                        <bitRange>[17:16]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>don&#39;t invert the peri input</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>invert the peri input</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive peri input low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive peri input high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>OEOVER</name>
+                        <bitRange>[13:12]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>drive output enable from peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>DISABLE</name>
+                                <value>2</value>
+                                <description>disable output</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ENABLE</name>
+                                <value>3</value>
+                                <description>enable output</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>OUTOVER</name>
+                        <bitRange>[9:8]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>drive output from peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>drive output from inverse of peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive output low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive output high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>FUNCSEL</name>
+                        <description>0-31 -&gt; selects pin function according to the gpio table 
+                            31 == NULL</description>
+                        <bitRange>[4:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>spi0_ss_n</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>uart1_rx</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>i2c0_scl</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pwm_b_2</name>
+                                <value>4</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sio_21</name>
+                                <value>5</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio0_21</name>
+                                <value>6</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio1_21</name>
+                                <value>7</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>clocks_gpout_0</name>
+                                <value>8</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>usb_muxing_overcurr_detect</name>
+                                <value>9</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>null</name>
+                                <value>31</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO22_STATUS</name>
+                <addressOffset>0x000000b0</addressOffset>
+                <description>GPIO status</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>IRQTOPROC</name>
+                        <description>interrupt to processors, after override is applied</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>IRQFROMPAD</name>
+                        <description>interrupt from pad before override is applied</description>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>INTOPERI</name>
+                        <description>input signal to peripheral, after override is applied</description>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>INFROMPAD</name>
+                        <description>input signal from pad, before override is applied</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OETOPAD</name>
+                        <description>output enable to pad after register override is applied</description>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OEFROMPERI</name>
+                        <description>output enable from selected peripheral, before register override is applied</description>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OUTTOPAD</name>
+                        <description>output signal to pad after register override is applied</description>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OUTFROMPERI</name>
+                        <description>output signal from selected peripheral, before register override is applied</description>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO22_CTRL</name>
+                <addressOffset>0x000000b4</addressOffset>
+                <description>GPIO control including function select and overrides.</description>
+                <resetValue>0x0000001f</resetValue>
+                <fields>
+                    <field>
+                        <name>IRQOVER</name>
+                        <bitRange>[29:28]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>don&#39;t invert the interrupt</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>invert the interrupt</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive interrupt low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive interrupt high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>INOVER</name>
+                        <bitRange>[17:16]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>don&#39;t invert the peri input</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>invert the peri input</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive peri input low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive peri input high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>OEOVER</name>
+                        <bitRange>[13:12]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>drive output enable from peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>DISABLE</name>
+                                <value>2</value>
+                                <description>disable output</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ENABLE</name>
+                                <value>3</value>
+                                <description>enable output</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>OUTOVER</name>
+                        <bitRange>[9:8]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>drive output from peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>drive output from inverse of peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive output low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive output high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>FUNCSEL</name>
+                        <description>0-31 -&gt; selects pin function according to the gpio table 
+                            31 == NULL</description>
+                        <bitRange>[4:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>spi0_sclk</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>uart1_cts</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>i2c1_sda</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pwm_a_3</name>
+                                <value>4</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sio_22</name>
+                                <value>5</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio0_22</name>
+                                <value>6</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio1_22</name>
+                                <value>7</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>clocks_gpin_1</name>
+                                <value>8</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>usb_muxing_vbus_detect</name>
+                                <value>9</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>null</name>
+                                <value>31</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO23_STATUS</name>
+                <addressOffset>0x000000b8</addressOffset>
+                <description>GPIO status</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>IRQTOPROC</name>
+                        <description>interrupt to processors, after override is applied</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>IRQFROMPAD</name>
+                        <description>interrupt from pad before override is applied</description>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>INTOPERI</name>
+                        <description>input signal to peripheral, after override is applied</description>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>INFROMPAD</name>
+                        <description>input signal from pad, before override is applied</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OETOPAD</name>
+                        <description>output enable to pad after register override is applied</description>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OEFROMPERI</name>
+                        <description>output enable from selected peripheral, before register override is applied</description>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OUTTOPAD</name>
+                        <description>output signal to pad after register override is applied</description>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OUTFROMPERI</name>
+                        <description>output signal from selected peripheral, before register override is applied</description>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO23_CTRL</name>
+                <addressOffset>0x000000bc</addressOffset>
+                <description>GPIO control including function select and overrides.</description>
+                <resetValue>0x0000001f</resetValue>
+                <fields>
+                    <field>
+                        <name>IRQOVER</name>
+                        <bitRange>[29:28]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>don&#39;t invert the interrupt</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>invert the interrupt</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive interrupt low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive interrupt high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>INOVER</name>
+                        <bitRange>[17:16]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>don&#39;t invert the peri input</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>invert the peri input</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive peri input low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive peri input high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>OEOVER</name>
+                        <bitRange>[13:12]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>drive output enable from peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>DISABLE</name>
+                                <value>2</value>
+                                <description>disable output</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ENABLE</name>
+                                <value>3</value>
+                                <description>enable output</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>OUTOVER</name>
+                        <bitRange>[9:8]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>drive output from peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>drive output from inverse of peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive output low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive output high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>FUNCSEL</name>
+                        <description>0-31 -&gt; selects pin function according to the gpio table 
+                            31 == NULL</description>
+                        <bitRange>[4:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>spi0_tx</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>uart1_rts</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>i2c1_scl</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pwm_b_3</name>
+                                <value>4</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sio_23</name>
+                                <value>5</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio0_23</name>
+                                <value>6</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio1_23</name>
+                                <value>7</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>clocks_gpout_1</name>
+                                <value>8</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>usb_muxing_vbus_en</name>
+                                <value>9</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>null</name>
+                                <value>31</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO24_STATUS</name>
+                <addressOffset>0x000000c0</addressOffset>
+                <description>GPIO status</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>IRQTOPROC</name>
+                        <description>interrupt to processors, after override is applied</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>IRQFROMPAD</name>
+                        <description>interrupt from pad before override is applied</description>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>INTOPERI</name>
+                        <description>input signal to peripheral, after override is applied</description>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>INFROMPAD</name>
+                        <description>input signal from pad, before override is applied</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OETOPAD</name>
+                        <description>output enable to pad after register override is applied</description>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OEFROMPERI</name>
+                        <description>output enable from selected peripheral, before register override is applied</description>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OUTTOPAD</name>
+                        <description>output signal to pad after register override is applied</description>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OUTFROMPERI</name>
+                        <description>output signal from selected peripheral, before register override is applied</description>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO24_CTRL</name>
+                <addressOffset>0x000000c4</addressOffset>
+                <description>GPIO control including function select and overrides.</description>
+                <resetValue>0x0000001f</resetValue>
+                <fields>
+                    <field>
+                        <name>IRQOVER</name>
+                        <bitRange>[29:28]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>don&#39;t invert the interrupt</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>invert the interrupt</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive interrupt low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive interrupt high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>INOVER</name>
+                        <bitRange>[17:16]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>don&#39;t invert the peri input</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>invert the peri input</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive peri input low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive peri input high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>OEOVER</name>
+                        <bitRange>[13:12]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>drive output enable from peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>DISABLE</name>
+                                <value>2</value>
+                                <description>disable output</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ENABLE</name>
+                                <value>3</value>
+                                <description>enable output</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>OUTOVER</name>
+                        <bitRange>[9:8]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>drive output from peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>drive output from inverse of peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive output low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive output high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>FUNCSEL</name>
+                        <description>0-31 -&gt; selects pin function according to the gpio table 
+                            31 == NULL</description>
+                        <bitRange>[4:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>spi1_rx</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>uart1_tx</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>i2c0_sda</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pwm_a_4</name>
+                                <value>4</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sio_24</name>
+                                <value>5</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio0_24</name>
+                                <value>6</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio1_24</name>
+                                <value>7</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>clocks_gpout_2</name>
+                                <value>8</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>usb_muxing_overcurr_detect</name>
+                                <value>9</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>null</name>
+                                <value>31</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO25_STATUS</name>
+                <addressOffset>0x000000c8</addressOffset>
+                <description>GPIO status</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>IRQTOPROC</name>
+                        <description>interrupt to processors, after override is applied</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>IRQFROMPAD</name>
+                        <description>interrupt from pad before override is applied</description>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>INTOPERI</name>
+                        <description>input signal to peripheral, after override is applied</description>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>INFROMPAD</name>
+                        <description>input signal from pad, before override is applied</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OETOPAD</name>
+                        <description>output enable to pad after register override is applied</description>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OEFROMPERI</name>
+                        <description>output enable from selected peripheral, before register override is applied</description>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OUTTOPAD</name>
+                        <description>output signal to pad after register override is applied</description>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OUTFROMPERI</name>
+                        <description>output signal from selected peripheral, before register override is applied</description>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO25_CTRL</name>
+                <addressOffset>0x000000cc</addressOffset>
+                <description>GPIO control including function select and overrides.</description>
+                <resetValue>0x0000001f</resetValue>
+                <fields>
+                    <field>
+                        <name>IRQOVER</name>
+                        <bitRange>[29:28]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>don&#39;t invert the interrupt</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>invert the interrupt</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive interrupt low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive interrupt high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>INOVER</name>
+                        <bitRange>[17:16]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>don&#39;t invert the peri input</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>invert the peri input</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive peri input low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive peri input high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>OEOVER</name>
+                        <bitRange>[13:12]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>drive output enable from peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>DISABLE</name>
+                                <value>2</value>
+                                <description>disable output</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ENABLE</name>
+                                <value>3</value>
+                                <description>enable output</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>OUTOVER</name>
+                        <bitRange>[9:8]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>drive output from peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>drive output from inverse of peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive output low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive output high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>FUNCSEL</name>
+                        <description>0-31 -&gt; selects pin function according to the gpio table 
+                            31 == NULL</description>
+                        <bitRange>[4:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>spi1_ss_n</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>uart1_rx</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>i2c0_scl</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pwm_b_4</name>
+                                <value>4</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sio_25</name>
+                                <value>5</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio0_25</name>
+                                <value>6</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio1_25</name>
+                                <value>7</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>clocks_gpout_3</name>
+                                <value>8</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>usb_muxing_vbus_detect</name>
+                                <value>9</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>null</name>
+                                <value>31</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO26_STATUS</name>
+                <addressOffset>0x000000d0</addressOffset>
+                <description>GPIO status</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>IRQTOPROC</name>
+                        <description>interrupt to processors, after override is applied</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>IRQFROMPAD</name>
+                        <description>interrupt from pad before override is applied</description>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>INTOPERI</name>
+                        <description>input signal to peripheral, after override is applied</description>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>INFROMPAD</name>
+                        <description>input signal from pad, before override is applied</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OETOPAD</name>
+                        <description>output enable to pad after register override is applied</description>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OEFROMPERI</name>
+                        <description>output enable from selected peripheral, before register override is applied</description>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OUTTOPAD</name>
+                        <description>output signal to pad after register override is applied</description>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OUTFROMPERI</name>
+                        <description>output signal from selected peripheral, before register override is applied</description>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO26_CTRL</name>
+                <addressOffset>0x000000d4</addressOffset>
+                <description>GPIO control including function select and overrides.</description>
+                <resetValue>0x0000001f</resetValue>
+                <fields>
+                    <field>
+                        <name>IRQOVER</name>
+                        <bitRange>[29:28]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>don&#39;t invert the interrupt</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>invert the interrupt</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive interrupt low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive interrupt high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>INOVER</name>
+                        <bitRange>[17:16]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>don&#39;t invert the peri input</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>invert the peri input</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive peri input low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive peri input high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>OEOVER</name>
+                        <bitRange>[13:12]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>drive output enable from peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>DISABLE</name>
+                                <value>2</value>
+                                <description>disable output</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ENABLE</name>
+                                <value>3</value>
+                                <description>enable output</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>OUTOVER</name>
+                        <bitRange>[9:8]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>drive output from peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>drive output from inverse of peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive output low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive output high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>FUNCSEL</name>
+                        <description>0-31 -&gt; selects pin function according to the gpio table 
+                            31 == NULL</description>
+                        <bitRange>[4:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>spi1_sclk</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>uart1_cts</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>i2c1_sda</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pwm_a_5</name>
+                                <value>4</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sio_26</name>
+                                <value>5</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio0_26</name>
+                                <value>6</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio1_26</name>
+                                <value>7</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>usb_muxing_vbus_en</name>
+                                <value>9</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>null</name>
+                                <value>31</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO27_STATUS</name>
+                <addressOffset>0x000000d8</addressOffset>
+                <description>GPIO status</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>IRQTOPROC</name>
+                        <description>interrupt to processors, after override is applied</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>IRQFROMPAD</name>
+                        <description>interrupt from pad before override is applied</description>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>INTOPERI</name>
+                        <description>input signal to peripheral, after override is applied</description>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>INFROMPAD</name>
+                        <description>input signal from pad, before override is applied</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OETOPAD</name>
+                        <description>output enable to pad after register override is applied</description>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OEFROMPERI</name>
+                        <description>output enable from selected peripheral, before register override is applied</description>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OUTTOPAD</name>
+                        <description>output signal to pad after register override is applied</description>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OUTFROMPERI</name>
+                        <description>output signal from selected peripheral, before register override is applied</description>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO27_CTRL</name>
+                <addressOffset>0x000000dc</addressOffset>
+                <description>GPIO control including function select and overrides.</description>
+                <resetValue>0x0000001f</resetValue>
+                <fields>
+                    <field>
+                        <name>IRQOVER</name>
+                        <bitRange>[29:28]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>don&#39;t invert the interrupt</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>invert the interrupt</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive interrupt low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive interrupt high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>INOVER</name>
+                        <bitRange>[17:16]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>don&#39;t invert the peri input</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>invert the peri input</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive peri input low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive peri input high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>OEOVER</name>
+                        <bitRange>[13:12]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>drive output enable from peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>DISABLE</name>
+                                <value>2</value>
+                                <description>disable output</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ENABLE</name>
+                                <value>3</value>
+                                <description>enable output</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>OUTOVER</name>
+                        <bitRange>[9:8]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>drive output from peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>drive output from inverse of peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive output low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive output high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>FUNCSEL</name>
+                        <description>0-31 -&gt; selects pin function according to the gpio table 
+                            31 == NULL</description>
+                        <bitRange>[4:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>spi1_tx</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>uart1_rts</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>i2c1_scl</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pwm_b_5</name>
+                                <value>4</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sio_27</name>
+                                <value>5</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio0_27</name>
+                                <value>6</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio1_27</name>
+                                <value>7</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>usb_muxing_overcurr_detect</name>
+                                <value>9</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>null</name>
+                                <value>31</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO28_STATUS</name>
+                <addressOffset>0x000000e0</addressOffset>
+                <description>GPIO status</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>IRQTOPROC</name>
+                        <description>interrupt to processors, after override is applied</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>IRQFROMPAD</name>
+                        <description>interrupt from pad before override is applied</description>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>INTOPERI</name>
+                        <description>input signal to peripheral, after override is applied</description>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>INFROMPAD</name>
+                        <description>input signal from pad, before override is applied</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OETOPAD</name>
+                        <description>output enable to pad after register override is applied</description>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OEFROMPERI</name>
+                        <description>output enable from selected peripheral, before register override is applied</description>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OUTTOPAD</name>
+                        <description>output signal to pad after register override is applied</description>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OUTFROMPERI</name>
+                        <description>output signal from selected peripheral, before register override is applied</description>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO28_CTRL</name>
+                <addressOffset>0x000000e4</addressOffset>
+                <description>GPIO control including function select and overrides.</description>
+                <resetValue>0x0000001f</resetValue>
+                <fields>
+                    <field>
+                        <name>IRQOVER</name>
+                        <bitRange>[29:28]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>don&#39;t invert the interrupt</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>invert the interrupt</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive interrupt low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive interrupt high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>INOVER</name>
+                        <bitRange>[17:16]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>don&#39;t invert the peri input</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>invert the peri input</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive peri input low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive peri input high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>OEOVER</name>
+                        <bitRange>[13:12]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>drive output enable from peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>DISABLE</name>
+                                <value>2</value>
+                                <description>disable output</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ENABLE</name>
+                                <value>3</value>
+                                <description>enable output</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>OUTOVER</name>
+                        <bitRange>[9:8]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>drive output from peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>drive output from inverse of peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive output low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive output high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>FUNCSEL</name>
+                        <description>0-31 -&gt; selects pin function according to the gpio table 
+                            31 == NULL</description>
+                        <bitRange>[4:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>spi1_rx</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>uart0_tx</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>i2c0_sda</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pwm_a_6</name>
+                                <value>4</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sio_28</name>
+                                <value>5</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio0_28</name>
+                                <value>6</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio1_28</name>
+                                <value>7</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>usb_muxing_vbus_detect</name>
+                                <value>9</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>null</name>
+                                <value>31</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO29_STATUS</name>
+                <addressOffset>0x000000e8</addressOffset>
+                <description>GPIO status</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>IRQTOPROC</name>
+                        <description>interrupt to processors, after override is applied</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>IRQFROMPAD</name>
+                        <description>interrupt from pad before override is applied</description>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>INTOPERI</name>
+                        <description>input signal to peripheral, after override is applied</description>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>INFROMPAD</name>
+                        <description>input signal from pad, before override is applied</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OETOPAD</name>
+                        <description>output enable to pad after register override is applied</description>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OEFROMPERI</name>
+                        <description>output enable from selected peripheral, before register override is applied</description>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OUTTOPAD</name>
+                        <description>output signal to pad after register override is applied</description>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OUTFROMPERI</name>
+                        <description>output signal from selected peripheral, before register override is applied</description>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO29_CTRL</name>
+                <addressOffset>0x000000ec</addressOffset>
+                <description>GPIO control including function select and overrides.</description>
+                <resetValue>0x0000001f</resetValue>
+                <fields>
+                    <field>
+                        <name>IRQOVER</name>
+                        <bitRange>[29:28]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>don&#39;t invert the interrupt</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>invert the interrupt</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive interrupt low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive interrupt high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>INOVER</name>
+                        <bitRange>[17:16]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>don&#39;t invert the peri input</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>invert the peri input</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive peri input low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive peri input high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>OEOVER</name>
+                        <bitRange>[13:12]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>drive output enable from peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>DISABLE</name>
+                                <value>2</value>
+                                <description>disable output</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ENABLE</name>
+                                <value>3</value>
+                                <description>enable output</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>OUTOVER</name>
+                        <bitRange>[9:8]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>drive output from peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>drive output from inverse of peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive output low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive output high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>FUNCSEL</name>
+                        <description>0-31 -&gt; selects pin function according to the gpio table 
+                            31 == NULL</description>
+                        <bitRange>[4:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>spi1_ss_n</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>uart0_rx</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>i2c0_scl</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pwm_b_6</name>
+                                <value>4</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sio_29</name>
+                                <value>5</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio0_29</name>
+                                <value>6</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio1_29</name>
+                                <value>7</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>usb_muxing_vbus_en</name>
+                                <value>9</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>null</name>
+                                <value>31</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INTR0</name>
+                <addressOffset>0x000000f0</addressOffset>
+                <description>Raw Interrupts</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>GPIO7_EDGE_HIGH</name>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>GPIO7_EDGE_LOW</name>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>GPIO7_LEVEL_HIGH</name>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO7_LEVEL_LOW</name>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO6_EDGE_HIGH</name>
+                        <bitRange>[27:27]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>GPIO6_EDGE_LOW</name>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>GPIO6_LEVEL_HIGH</name>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO6_LEVEL_LOW</name>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO5_EDGE_HIGH</name>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>GPIO5_EDGE_LOW</name>
+                        <bitRange>[22:22]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>GPIO5_LEVEL_HIGH</name>
+                        <bitRange>[21:21]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO5_LEVEL_LOW</name>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO4_EDGE_HIGH</name>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>GPIO4_EDGE_LOW</name>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>GPIO4_LEVEL_HIGH</name>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO4_LEVEL_LOW</name>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO3_EDGE_HIGH</name>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>GPIO3_EDGE_LOW</name>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>GPIO3_LEVEL_HIGH</name>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO3_LEVEL_LOW</name>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO2_EDGE_HIGH</name>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>GPIO2_EDGE_LOW</name>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>GPIO2_LEVEL_HIGH</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO2_LEVEL_LOW</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO1_EDGE_HIGH</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>GPIO1_EDGE_LOW</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>GPIO1_LEVEL_HIGH</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO1_LEVEL_LOW</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO0_EDGE_HIGH</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>GPIO0_EDGE_LOW</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>GPIO0_LEVEL_HIGH</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO0_LEVEL_LOW</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INTR1</name>
+                <addressOffset>0x000000f4</addressOffset>
+                <description>Raw Interrupts</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>GPIO15_EDGE_HIGH</name>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>GPIO15_EDGE_LOW</name>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>GPIO15_LEVEL_HIGH</name>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO15_LEVEL_LOW</name>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO14_EDGE_HIGH</name>
+                        <bitRange>[27:27]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>GPIO14_EDGE_LOW</name>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>GPIO14_LEVEL_HIGH</name>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO14_LEVEL_LOW</name>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO13_EDGE_HIGH</name>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>GPIO13_EDGE_LOW</name>
+                        <bitRange>[22:22]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>GPIO13_LEVEL_HIGH</name>
+                        <bitRange>[21:21]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO13_LEVEL_LOW</name>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO12_EDGE_HIGH</name>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>GPIO12_EDGE_LOW</name>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>GPIO12_LEVEL_HIGH</name>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO12_LEVEL_LOW</name>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO11_EDGE_HIGH</name>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>GPIO11_EDGE_LOW</name>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>GPIO11_LEVEL_HIGH</name>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO11_LEVEL_LOW</name>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO10_EDGE_HIGH</name>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>GPIO10_EDGE_LOW</name>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>GPIO10_LEVEL_HIGH</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO10_LEVEL_LOW</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO9_EDGE_HIGH</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>GPIO9_EDGE_LOW</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>GPIO9_LEVEL_HIGH</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO9_LEVEL_LOW</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO8_EDGE_HIGH</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>GPIO8_EDGE_LOW</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>GPIO8_LEVEL_HIGH</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO8_LEVEL_LOW</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INTR2</name>
+                <addressOffset>0x000000f8</addressOffset>
+                <description>Raw Interrupts</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>GPIO23_EDGE_HIGH</name>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>GPIO23_EDGE_LOW</name>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>GPIO23_LEVEL_HIGH</name>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO23_LEVEL_LOW</name>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO22_EDGE_HIGH</name>
+                        <bitRange>[27:27]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>GPIO22_EDGE_LOW</name>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>GPIO22_LEVEL_HIGH</name>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO22_LEVEL_LOW</name>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO21_EDGE_HIGH</name>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>GPIO21_EDGE_LOW</name>
+                        <bitRange>[22:22]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>GPIO21_LEVEL_HIGH</name>
+                        <bitRange>[21:21]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO21_LEVEL_LOW</name>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO20_EDGE_HIGH</name>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>GPIO20_EDGE_LOW</name>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>GPIO20_LEVEL_HIGH</name>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO20_LEVEL_LOW</name>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO19_EDGE_HIGH</name>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>GPIO19_EDGE_LOW</name>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>GPIO19_LEVEL_HIGH</name>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO19_LEVEL_LOW</name>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO18_EDGE_HIGH</name>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>GPIO18_EDGE_LOW</name>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>GPIO18_LEVEL_HIGH</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO18_LEVEL_LOW</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO17_EDGE_HIGH</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>GPIO17_EDGE_LOW</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>GPIO17_LEVEL_HIGH</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO17_LEVEL_LOW</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO16_EDGE_HIGH</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>GPIO16_EDGE_LOW</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>GPIO16_LEVEL_HIGH</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO16_LEVEL_LOW</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INTR3</name>
+                <addressOffset>0x000000fc</addressOffset>
+                <description>Raw Interrupts</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>GPIO29_EDGE_HIGH</name>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>GPIO29_EDGE_LOW</name>
+                        <bitRange>[22:22]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>GPIO29_LEVEL_HIGH</name>
+                        <bitRange>[21:21]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO29_LEVEL_LOW</name>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO28_EDGE_HIGH</name>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>GPIO28_EDGE_LOW</name>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>GPIO28_LEVEL_HIGH</name>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO28_LEVEL_LOW</name>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO27_EDGE_HIGH</name>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>GPIO27_EDGE_LOW</name>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>GPIO27_LEVEL_HIGH</name>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO27_LEVEL_LOW</name>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO26_EDGE_HIGH</name>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>GPIO26_EDGE_LOW</name>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>GPIO26_LEVEL_HIGH</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO26_LEVEL_LOW</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO25_EDGE_HIGH</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>GPIO25_EDGE_LOW</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>GPIO25_LEVEL_HIGH</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO25_LEVEL_LOW</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO24_EDGE_HIGH</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>GPIO24_EDGE_LOW</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>GPIO24_LEVEL_HIGH</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO24_LEVEL_LOW</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PROC0_INTE0</name>
+                <addressOffset>0x00000100</addressOffset>
+                <description>Interrupt Enable for proc0</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>GPIO7_EDGE_HIGH</name>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO7_EDGE_LOW</name>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO7_LEVEL_HIGH</name>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO7_LEVEL_LOW</name>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO6_EDGE_HIGH</name>
+                        <bitRange>[27:27]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO6_EDGE_LOW</name>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO6_LEVEL_HIGH</name>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO6_LEVEL_LOW</name>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO5_EDGE_HIGH</name>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO5_EDGE_LOW</name>
+                        <bitRange>[22:22]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO5_LEVEL_HIGH</name>
+                        <bitRange>[21:21]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO5_LEVEL_LOW</name>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO4_EDGE_HIGH</name>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO4_EDGE_LOW</name>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO4_LEVEL_HIGH</name>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO4_LEVEL_LOW</name>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO3_EDGE_HIGH</name>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO3_EDGE_LOW</name>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO3_LEVEL_HIGH</name>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO3_LEVEL_LOW</name>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO2_EDGE_HIGH</name>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO2_EDGE_LOW</name>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO2_LEVEL_HIGH</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO2_LEVEL_LOW</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO1_EDGE_HIGH</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO1_EDGE_LOW</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO1_LEVEL_HIGH</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO1_LEVEL_LOW</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO0_EDGE_HIGH</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO0_EDGE_LOW</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO0_LEVEL_HIGH</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO0_LEVEL_LOW</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PROC0_INTE1</name>
+                <addressOffset>0x00000104</addressOffset>
+                <description>Interrupt Enable for proc0</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>GPIO15_EDGE_HIGH</name>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO15_EDGE_LOW</name>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO15_LEVEL_HIGH</name>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO15_LEVEL_LOW</name>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO14_EDGE_HIGH</name>
+                        <bitRange>[27:27]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO14_EDGE_LOW</name>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO14_LEVEL_HIGH</name>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO14_LEVEL_LOW</name>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO13_EDGE_HIGH</name>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO13_EDGE_LOW</name>
+                        <bitRange>[22:22]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO13_LEVEL_HIGH</name>
+                        <bitRange>[21:21]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO13_LEVEL_LOW</name>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO12_EDGE_HIGH</name>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO12_EDGE_LOW</name>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO12_LEVEL_HIGH</name>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO12_LEVEL_LOW</name>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO11_EDGE_HIGH</name>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO11_EDGE_LOW</name>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO11_LEVEL_HIGH</name>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO11_LEVEL_LOW</name>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO10_EDGE_HIGH</name>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO10_EDGE_LOW</name>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO10_LEVEL_HIGH</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO10_LEVEL_LOW</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO9_EDGE_HIGH</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO9_EDGE_LOW</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO9_LEVEL_HIGH</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO9_LEVEL_LOW</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO8_EDGE_HIGH</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO8_EDGE_LOW</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO8_LEVEL_HIGH</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO8_LEVEL_LOW</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PROC0_INTE2</name>
+                <addressOffset>0x00000108</addressOffset>
+                <description>Interrupt Enable for proc0</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>GPIO23_EDGE_HIGH</name>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO23_EDGE_LOW</name>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO23_LEVEL_HIGH</name>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO23_LEVEL_LOW</name>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO22_EDGE_HIGH</name>
+                        <bitRange>[27:27]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO22_EDGE_LOW</name>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO22_LEVEL_HIGH</name>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO22_LEVEL_LOW</name>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO21_EDGE_HIGH</name>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO21_EDGE_LOW</name>
+                        <bitRange>[22:22]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO21_LEVEL_HIGH</name>
+                        <bitRange>[21:21]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO21_LEVEL_LOW</name>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO20_EDGE_HIGH</name>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO20_EDGE_LOW</name>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO20_LEVEL_HIGH</name>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO20_LEVEL_LOW</name>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO19_EDGE_HIGH</name>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO19_EDGE_LOW</name>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO19_LEVEL_HIGH</name>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO19_LEVEL_LOW</name>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO18_EDGE_HIGH</name>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO18_EDGE_LOW</name>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO18_LEVEL_HIGH</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO18_LEVEL_LOW</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO17_EDGE_HIGH</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO17_EDGE_LOW</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO17_LEVEL_HIGH</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO17_LEVEL_LOW</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO16_EDGE_HIGH</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO16_EDGE_LOW</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO16_LEVEL_HIGH</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO16_LEVEL_LOW</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PROC0_INTE3</name>
+                <addressOffset>0x0000010c</addressOffset>
+                <description>Interrupt Enable for proc0</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>GPIO29_EDGE_HIGH</name>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO29_EDGE_LOW</name>
+                        <bitRange>[22:22]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO29_LEVEL_HIGH</name>
+                        <bitRange>[21:21]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO29_LEVEL_LOW</name>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO28_EDGE_HIGH</name>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO28_EDGE_LOW</name>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO28_LEVEL_HIGH</name>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO28_LEVEL_LOW</name>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO27_EDGE_HIGH</name>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO27_EDGE_LOW</name>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO27_LEVEL_HIGH</name>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO27_LEVEL_LOW</name>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO26_EDGE_HIGH</name>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO26_EDGE_LOW</name>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO26_LEVEL_HIGH</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO26_LEVEL_LOW</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO25_EDGE_HIGH</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO25_EDGE_LOW</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO25_LEVEL_HIGH</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO25_LEVEL_LOW</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO24_EDGE_HIGH</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO24_EDGE_LOW</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO24_LEVEL_HIGH</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO24_LEVEL_LOW</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PROC0_INTF0</name>
+                <addressOffset>0x00000110</addressOffset>
+                <description>Interrupt Force for proc0</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>GPIO7_EDGE_HIGH</name>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO7_EDGE_LOW</name>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO7_LEVEL_HIGH</name>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO7_LEVEL_LOW</name>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO6_EDGE_HIGH</name>
+                        <bitRange>[27:27]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO6_EDGE_LOW</name>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO6_LEVEL_HIGH</name>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO6_LEVEL_LOW</name>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO5_EDGE_HIGH</name>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO5_EDGE_LOW</name>
+                        <bitRange>[22:22]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO5_LEVEL_HIGH</name>
+                        <bitRange>[21:21]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO5_LEVEL_LOW</name>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO4_EDGE_HIGH</name>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO4_EDGE_LOW</name>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO4_LEVEL_HIGH</name>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO4_LEVEL_LOW</name>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO3_EDGE_HIGH</name>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO3_EDGE_LOW</name>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO3_LEVEL_HIGH</name>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO3_LEVEL_LOW</name>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO2_EDGE_HIGH</name>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO2_EDGE_LOW</name>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO2_LEVEL_HIGH</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO2_LEVEL_LOW</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO1_EDGE_HIGH</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO1_EDGE_LOW</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO1_LEVEL_HIGH</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO1_LEVEL_LOW</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO0_EDGE_HIGH</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO0_EDGE_LOW</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO0_LEVEL_HIGH</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO0_LEVEL_LOW</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PROC0_INTF1</name>
+                <addressOffset>0x00000114</addressOffset>
+                <description>Interrupt Force for proc0</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>GPIO15_EDGE_HIGH</name>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO15_EDGE_LOW</name>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO15_LEVEL_HIGH</name>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO15_LEVEL_LOW</name>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO14_EDGE_HIGH</name>
+                        <bitRange>[27:27]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO14_EDGE_LOW</name>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO14_LEVEL_HIGH</name>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO14_LEVEL_LOW</name>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO13_EDGE_HIGH</name>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO13_EDGE_LOW</name>
+                        <bitRange>[22:22]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO13_LEVEL_HIGH</name>
+                        <bitRange>[21:21]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO13_LEVEL_LOW</name>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO12_EDGE_HIGH</name>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO12_EDGE_LOW</name>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO12_LEVEL_HIGH</name>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO12_LEVEL_LOW</name>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO11_EDGE_HIGH</name>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO11_EDGE_LOW</name>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO11_LEVEL_HIGH</name>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO11_LEVEL_LOW</name>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO10_EDGE_HIGH</name>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO10_EDGE_LOW</name>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO10_LEVEL_HIGH</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO10_LEVEL_LOW</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO9_EDGE_HIGH</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO9_EDGE_LOW</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO9_LEVEL_HIGH</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO9_LEVEL_LOW</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO8_EDGE_HIGH</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO8_EDGE_LOW</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO8_LEVEL_HIGH</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO8_LEVEL_LOW</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PROC0_INTF2</name>
+                <addressOffset>0x00000118</addressOffset>
+                <description>Interrupt Force for proc0</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>GPIO23_EDGE_HIGH</name>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO23_EDGE_LOW</name>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO23_LEVEL_HIGH</name>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO23_LEVEL_LOW</name>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO22_EDGE_HIGH</name>
+                        <bitRange>[27:27]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO22_EDGE_LOW</name>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO22_LEVEL_HIGH</name>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO22_LEVEL_LOW</name>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO21_EDGE_HIGH</name>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO21_EDGE_LOW</name>
+                        <bitRange>[22:22]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO21_LEVEL_HIGH</name>
+                        <bitRange>[21:21]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO21_LEVEL_LOW</name>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO20_EDGE_HIGH</name>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO20_EDGE_LOW</name>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO20_LEVEL_HIGH</name>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO20_LEVEL_LOW</name>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO19_EDGE_HIGH</name>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO19_EDGE_LOW</name>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO19_LEVEL_HIGH</name>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO19_LEVEL_LOW</name>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO18_EDGE_HIGH</name>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO18_EDGE_LOW</name>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO18_LEVEL_HIGH</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO18_LEVEL_LOW</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO17_EDGE_HIGH</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO17_EDGE_LOW</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO17_LEVEL_HIGH</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO17_LEVEL_LOW</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO16_EDGE_HIGH</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO16_EDGE_LOW</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO16_LEVEL_HIGH</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO16_LEVEL_LOW</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PROC0_INTF3</name>
+                <addressOffset>0x0000011c</addressOffset>
+                <description>Interrupt Force for proc0</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>GPIO29_EDGE_HIGH</name>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO29_EDGE_LOW</name>
+                        <bitRange>[22:22]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO29_LEVEL_HIGH</name>
+                        <bitRange>[21:21]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO29_LEVEL_LOW</name>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO28_EDGE_HIGH</name>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO28_EDGE_LOW</name>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO28_LEVEL_HIGH</name>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO28_LEVEL_LOW</name>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO27_EDGE_HIGH</name>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO27_EDGE_LOW</name>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO27_LEVEL_HIGH</name>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO27_LEVEL_LOW</name>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO26_EDGE_HIGH</name>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO26_EDGE_LOW</name>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO26_LEVEL_HIGH</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO26_LEVEL_LOW</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO25_EDGE_HIGH</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO25_EDGE_LOW</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO25_LEVEL_HIGH</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO25_LEVEL_LOW</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO24_EDGE_HIGH</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO24_EDGE_LOW</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO24_LEVEL_HIGH</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO24_LEVEL_LOW</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PROC0_INTS0</name>
+                <addressOffset>0x00000120</addressOffset>
+                <description>Interrupt status after masking &amp; forcing for proc0</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>GPIO7_EDGE_HIGH</name>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO7_EDGE_LOW</name>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO7_LEVEL_HIGH</name>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO7_LEVEL_LOW</name>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO6_EDGE_HIGH</name>
+                        <bitRange>[27:27]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO6_EDGE_LOW</name>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO6_LEVEL_HIGH</name>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO6_LEVEL_LOW</name>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO5_EDGE_HIGH</name>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO5_EDGE_LOW</name>
+                        <bitRange>[22:22]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO5_LEVEL_HIGH</name>
+                        <bitRange>[21:21]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO5_LEVEL_LOW</name>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO4_EDGE_HIGH</name>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO4_EDGE_LOW</name>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO4_LEVEL_HIGH</name>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO4_LEVEL_LOW</name>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO3_EDGE_HIGH</name>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO3_EDGE_LOW</name>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO3_LEVEL_HIGH</name>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO3_LEVEL_LOW</name>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO2_EDGE_HIGH</name>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO2_EDGE_LOW</name>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO2_LEVEL_HIGH</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO2_LEVEL_LOW</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO1_EDGE_HIGH</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO1_EDGE_LOW</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO1_LEVEL_HIGH</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO1_LEVEL_LOW</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO0_EDGE_HIGH</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO0_EDGE_LOW</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO0_LEVEL_HIGH</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO0_LEVEL_LOW</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PROC0_INTS1</name>
+                <addressOffset>0x00000124</addressOffset>
+                <description>Interrupt status after masking &amp; forcing for proc0</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>GPIO15_EDGE_HIGH</name>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO15_EDGE_LOW</name>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO15_LEVEL_HIGH</name>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO15_LEVEL_LOW</name>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO14_EDGE_HIGH</name>
+                        <bitRange>[27:27]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO14_EDGE_LOW</name>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO14_LEVEL_HIGH</name>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO14_LEVEL_LOW</name>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO13_EDGE_HIGH</name>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO13_EDGE_LOW</name>
+                        <bitRange>[22:22]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO13_LEVEL_HIGH</name>
+                        <bitRange>[21:21]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO13_LEVEL_LOW</name>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO12_EDGE_HIGH</name>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO12_EDGE_LOW</name>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO12_LEVEL_HIGH</name>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO12_LEVEL_LOW</name>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO11_EDGE_HIGH</name>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO11_EDGE_LOW</name>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO11_LEVEL_HIGH</name>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO11_LEVEL_LOW</name>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO10_EDGE_HIGH</name>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO10_EDGE_LOW</name>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO10_LEVEL_HIGH</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO10_LEVEL_LOW</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO9_EDGE_HIGH</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO9_EDGE_LOW</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO9_LEVEL_HIGH</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO9_LEVEL_LOW</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO8_EDGE_HIGH</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO8_EDGE_LOW</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO8_LEVEL_HIGH</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO8_LEVEL_LOW</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PROC0_INTS2</name>
+                <addressOffset>0x00000128</addressOffset>
+                <description>Interrupt status after masking &amp; forcing for proc0</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>GPIO23_EDGE_HIGH</name>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO23_EDGE_LOW</name>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO23_LEVEL_HIGH</name>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO23_LEVEL_LOW</name>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO22_EDGE_HIGH</name>
+                        <bitRange>[27:27]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO22_EDGE_LOW</name>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO22_LEVEL_HIGH</name>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO22_LEVEL_LOW</name>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO21_EDGE_HIGH</name>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO21_EDGE_LOW</name>
+                        <bitRange>[22:22]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO21_LEVEL_HIGH</name>
+                        <bitRange>[21:21]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO21_LEVEL_LOW</name>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO20_EDGE_HIGH</name>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO20_EDGE_LOW</name>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO20_LEVEL_HIGH</name>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO20_LEVEL_LOW</name>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO19_EDGE_HIGH</name>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO19_EDGE_LOW</name>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO19_LEVEL_HIGH</name>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO19_LEVEL_LOW</name>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO18_EDGE_HIGH</name>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO18_EDGE_LOW</name>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO18_LEVEL_HIGH</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO18_LEVEL_LOW</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO17_EDGE_HIGH</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO17_EDGE_LOW</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO17_LEVEL_HIGH</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO17_LEVEL_LOW</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO16_EDGE_HIGH</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO16_EDGE_LOW</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO16_LEVEL_HIGH</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO16_LEVEL_LOW</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PROC0_INTS3</name>
+                <addressOffset>0x0000012c</addressOffset>
+                <description>Interrupt status after masking &amp; forcing for proc0</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>GPIO29_EDGE_HIGH</name>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO29_EDGE_LOW</name>
+                        <bitRange>[22:22]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO29_LEVEL_HIGH</name>
+                        <bitRange>[21:21]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO29_LEVEL_LOW</name>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO28_EDGE_HIGH</name>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO28_EDGE_LOW</name>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO28_LEVEL_HIGH</name>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO28_LEVEL_LOW</name>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO27_EDGE_HIGH</name>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO27_EDGE_LOW</name>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO27_LEVEL_HIGH</name>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO27_LEVEL_LOW</name>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO26_EDGE_HIGH</name>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO26_EDGE_LOW</name>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO26_LEVEL_HIGH</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO26_LEVEL_LOW</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO25_EDGE_HIGH</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO25_EDGE_LOW</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO25_LEVEL_HIGH</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO25_LEVEL_LOW</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO24_EDGE_HIGH</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO24_EDGE_LOW</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO24_LEVEL_HIGH</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO24_LEVEL_LOW</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PROC1_INTE0</name>
+                <addressOffset>0x00000130</addressOffset>
+                <description>Interrupt Enable for proc1</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>GPIO7_EDGE_HIGH</name>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO7_EDGE_LOW</name>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO7_LEVEL_HIGH</name>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO7_LEVEL_LOW</name>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO6_EDGE_HIGH</name>
+                        <bitRange>[27:27]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO6_EDGE_LOW</name>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO6_LEVEL_HIGH</name>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO6_LEVEL_LOW</name>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO5_EDGE_HIGH</name>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO5_EDGE_LOW</name>
+                        <bitRange>[22:22]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO5_LEVEL_HIGH</name>
+                        <bitRange>[21:21]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO5_LEVEL_LOW</name>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO4_EDGE_HIGH</name>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO4_EDGE_LOW</name>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO4_LEVEL_HIGH</name>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO4_LEVEL_LOW</name>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO3_EDGE_HIGH</name>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO3_EDGE_LOW</name>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO3_LEVEL_HIGH</name>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO3_LEVEL_LOW</name>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO2_EDGE_HIGH</name>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO2_EDGE_LOW</name>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO2_LEVEL_HIGH</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO2_LEVEL_LOW</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO1_EDGE_HIGH</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO1_EDGE_LOW</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO1_LEVEL_HIGH</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO1_LEVEL_LOW</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO0_EDGE_HIGH</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO0_EDGE_LOW</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO0_LEVEL_HIGH</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO0_LEVEL_LOW</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PROC1_INTE1</name>
+                <addressOffset>0x00000134</addressOffset>
+                <description>Interrupt Enable for proc1</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>GPIO15_EDGE_HIGH</name>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO15_EDGE_LOW</name>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO15_LEVEL_HIGH</name>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO15_LEVEL_LOW</name>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO14_EDGE_HIGH</name>
+                        <bitRange>[27:27]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO14_EDGE_LOW</name>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO14_LEVEL_HIGH</name>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO14_LEVEL_LOW</name>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO13_EDGE_HIGH</name>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO13_EDGE_LOW</name>
+                        <bitRange>[22:22]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO13_LEVEL_HIGH</name>
+                        <bitRange>[21:21]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO13_LEVEL_LOW</name>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO12_EDGE_HIGH</name>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO12_EDGE_LOW</name>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO12_LEVEL_HIGH</name>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO12_LEVEL_LOW</name>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO11_EDGE_HIGH</name>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO11_EDGE_LOW</name>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO11_LEVEL_HIGH</name>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO11_LEVEL_LOW</name>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO10_EDGE_HIGH</name>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO10_EDGE_LOW</name>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO10_LEVEL_HIGH</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO10_LEVEL_LOW</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO9_EDGE_HIGH</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO9_EDGE_LOW</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO9_LEVEL_HIGH</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO9_LEVEL_LOW</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO8_EDGE_HIGH</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO8_EDGE_LOW</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO8_LEVEL_HIGH</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO8_LEVEL_LOW</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PROC1_INTE2</name>
+                <addressOffset>0x00000138</addressOffset>
+                <description>Interrupt Enable for proc1</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>GPIO23_EDGE_HIGH</name>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO23_EDGE_LOW</name>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO23_LEVEL_HIGH</name>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO23_LEVEL_LOW</name>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO22_EDGE_HIGH</name>
+                        <bitRange>[27:27]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO22_EDGE_LOW</name>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO22_LEVEL_HIGH</name>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO22_LEVEL_LOW</name>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO21_EDGE_HIGH</name>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO21_EDGE_LOW</name>
+                        <bitRange>[22:22]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO21_LEVEL_HIGH</name>
+                        <bitRange>[21:21]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO21_LEVEL_LOW</name>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO20_EDGE_HIGH</name>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO20_EDGE_LOW</name>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO20_LEVEL_HIGH</name>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO20_LEVEL_LOW</name>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO19_EDGE_HIGH</name>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO19_EDGE_LOW</name>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO19_LEVEL_HIGH</name>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO19_LEVEL_LOW</name>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO18_EDGE_HIGH</name>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO18_EDGE_LOW</name>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO18_LEVEL_HIGH</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO18_LEVEL_LOW</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO17_EDGE_HIGH</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO17_EDGE_LOW</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO17_LEVEL_HIGH</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO17_LEVEL_LOW</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO16_EDGE_HIGH</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO16_EDGE_LOW</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO16_LEVEL_HIGH</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO16_LEVEL_LOW</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PROC1_INTE3</name>
+                <addressOffset>0x0000013c</addressOffset>
+                <description>Interrupt Enable for proc1</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>GPIO29_EDGE_HIGH</name>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO29_EDGE_LOW</name>
+                        <bitRange>[22:22]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO29_LEVEL_HIGH</name>
+                        <bitRange>[21:21]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO29_LEVEL_LOW</name>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO28_EDGE_HIGH</name>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO28_EDGE_LOW</name>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO28_LEVEL_HIGH</name>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO28_LEVEL_LOW</name>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO27_EDGE_HIGH</name>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO27_EDGE_LOW</name>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO27_LEVEL_HIGH</name>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO27_LEVEL_LOW</name>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO26_EDGE_HIGH</name>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO26_EDGE_LOW</name>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO26_LEVEL_HIGH</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO26_LEVEL_LOW</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO25_EDGE_HIGH</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO25_EDGE_LOW</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO25_LEVEL_HIGH</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO25_LEVEL_LOW</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO24_EDGE_HIGH</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO24_EDGE_LOW</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO24_LEVEL_HIGH</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO24_LEVEL_LOW</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PROC1_INTF0</name>
+                <addressOffset>0x00000140</addressOffset>
+                <description>Interrupt Force for proc1</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>GPIO7_EDGE_HIGH</name>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO7_EDGE_LOW</name>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO7_LEVEL_HIGH</name>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO7_LEVEL_LOW</name>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO6_EDGE_HIGH</name>
+                        <bitRange>[27:27]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO6_EDGE_LOW</name>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO6_LEVEL_HIGH</name>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO6_LEVEL_LOW</name>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO5_EDGE_HIGH</name>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO5_EDGE_LOW</name>
+                        <bitRange>[22:22]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO5_LEVEL_HIGH</name>
+                        <bitRange>[21:21]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO5_LEVEL_LOW</name>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO4_EDGE_HIGH</name>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO4_EDGE_LOW</name>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO4_LEVEL_HIGH</name>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO4_LEVEL_LOW</name>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO3_EDGE_HIGH</name>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO3_EDGE_LOW</name>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO3_LEVEL_HIGH</name>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO3_LEVEL_LOW</name>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO2_EDGE_HIGH</name>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO2_EDGE_LOW</name>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO2_LEVEL_HIGH</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO2_LEVEL_LOW</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO1_EDGE_HIGH</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO1_EDGE_LOW</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO1_LEVEL_HIGH</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO1_LEVEL_LOW</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO0_EDGE_HIGH</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO0_EDGE_LOW</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO0_LEVEL_HIGH</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO0_LEVEL_LOW</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PROC1_INTF1</name>
+                <addressOffset>0x00000144</addressOffset>
+                <description>Interrupt Force for proc1</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>GPIO15_EDGE_HIGH</name>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO15_EDGE_LOW</name>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO15_LEVEL_HIGH</name>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO15_LEVEL_LOW</name>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO14_EDGE_HIGH</name>
+                        <bitRange>[27:27]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO14_EDGE_LOW</name>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO14_LEVEL_HIGH</name>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO14_LEVEL_LOW</name>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO13_EDGE_HIGH</name>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO13_EDGE_LOW</name>
+                        <bitRange>[22:22]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO13_LEVEL_HIGH</name>
+                        <bitRange>[21:21]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO13_LEVEL_LOW</name>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO12_EDGE_HIGH</name>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO12_EDGE_LOW</name>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO12_LEVEL_HIGH</name>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO12_LEVEL_LOW</name>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO11_EDGE_HIGH</name>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO11_EDGE_LOW</name>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO11_LEVEL_HIGH</name>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO11_LEVEL_LOW</name>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO10_EDGE_HIGH</name>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO10_EDGE_LOW</name>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO10_LEVEL_HIGH</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO10_LEVEL_LOW</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO9_EDGE_HIGH</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO9_EDGE_LOW</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO9_LEVEL_HIGH</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO9_LEVEL_LOW</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO8_EDGE_HIGH</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO8_EDGE_LOW</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO8_LEVEL_HIGH</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO8_LEVEL_LOW</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PROC1_INTF2</name>
+                <addressOffset>0x00000148</addressOffset>
+                <description>Interrupt Force for proc1</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>GPIO23_EDGE_HIGH</name>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO23_EDGE_LOW</name>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO23_LEVEL_HIGH</name>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO23_LEVEL_LOW</name>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO22_EDGE_HIGH</name>
+                        <bitRange>[27:27]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO22_EDGE_LOW</name>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO22_LEVEL_HIGH</name>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO22_LEVEL_LOW</name>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO21_EDGE_HIGH</name>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO21_EDGE_LOW</name>
+                        <bitRange>[22:22]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO21_LEVEL_HIGH</name>
+                        <bitRange>[21:21]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO21_LEVEL_LOW</name>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO20_EDGE_HIGH</name>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO20_EDGE_LOW</name>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO20_LEVEL_HIGH</name>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO20_LEVEL_LOW</name>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO19_EDGE_HIGH</name>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO19_EDGE_LOW</name>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO19_LEVEL_HIGH</name>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO19_LEVEL_LOW</name>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO18_EDGE_HIGH</name>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO18_EDGE_LOW</name>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO18_LEVEL_HIGH</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO18_LEVEL_LOW</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO17_EDGE_HIGH</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO17_EDGE_LOW</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO17_LEVEL_HIGH</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO17_LEVEL_LOW</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO16_EDGE_HIGH</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO16_EDGE_LOW</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO16_LEVEL_HIGH</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO16_LEVEL_LOW</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PROC1_INTF3</name>
+                <addressOffset>0x0000014c</addressOffset>
+                <description>Interrupt Force for proc1</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>GPIO29_EDGE_HIGH</name>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO29_EDGE_LOW</name>
+                        <bitRange>[22:22]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO29_LEVEL_HIGH</name>
+                        <bitRange>[21:21]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO29_LEVEL_LOW</name>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO28_EDGE_HIGH</name>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO28_EDGE_LOW</name>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO28_LEVEL_HIGH</name>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO28_LEVEL_LOW</name>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO27_EDGE_HIGH</name>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO27_EDGE_LOW</name>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO27_LEVEL_HIGH</name>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO27_LEVEL_LOW</name>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO26_EDGE_HIGH</name>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO26_EDGE_LOW</name>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO26_LEVEL_HIGH</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO26_LEVEL_LOW</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO25_EDGE_HIGH</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO25_EDGE_LOW</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO25_LEVEL_HIGH</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO25_LEVEL_LOW</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO24_EDGE_HIGH</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO24_EDGE_LOW</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO24_LEVEL_HIGH</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO24_LEVEL_LOW</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PROC1_INTS0</name>
+                <addressOffset>0x00000150</addressOffset>
+                <description>Interrupt status after masking &amp; forcing for proc1</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>GPIO7_EDGE_HIGH</name>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO7_EDGE_LOW</name>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO7_LEVEL_HIGH</name>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO7_LEVEL_LOW</name>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO6_EDGE_HIGH</name>
+                        <bitRange>[27:27]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO6_EDGE_LOW</name>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO6_LEVEL_HIGH</name>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO6_LEVEL_LOW</name>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO5_EDGE_HIGH</name>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO5_EDGE_LOW</name>
+                        <bitRange>[22:22]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO5_LEVEL_HIGH</name>
+                        <bitRange>[21:21]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO5_LEVEL_LOW</name>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO4_EDGE_HIGH</name>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO4_EDGE_LOW</name>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO4_LEVEL_HIGH</name>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO4_LEVEL_LOW</name>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO3_EDGE_HIGH</name>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO3_EDGE_LOW</name>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO3_LEVEL_HIGH</name>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO3_LEVEL_LOW</name>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO2_EDGE_HIGH</name>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO2_EDGE_LOW</name>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO2_LEVEL_HIGH</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO2_LEVEL_LOW</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO1_EDGE_HIGH</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO1_EDGE_LOW</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO1_LEVEL_HIGH</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO1_LEVEL_LOW</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO0_EDGE_HIGH</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO0_EDGE_LOW</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO0_LEVEL_HIGH</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO0_LEVEL_LOW</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PROC1_INTS1</name>
+                <addressOffset>0x00000154</addressOffset>
+                <description>Interrupt status after masking &amp; forcing for proc1</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>GPIO15_EDGE_HIGH</name>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO15_EDGE_LOW</name>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO15_LEVEL_HIGH</name>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO15_LEVEL_LOW</name>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO14_EDGE_HIGH</name>
+                        <bitRange>[27:27]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO14_EDGE_LOW</name>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO14_LEVEL_HIGH</name>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO14_LEVEL_LOW</name>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO13_EDGE_HIGH</name>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO13_EDGE_LOW</name>
+                        <bitRange>[22:22]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO13_LEVEL_HIGH</name>
+                        <bitRange>[21:21]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO13_LEVEL_LOW</name>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO12_EDGE_HIGH</name>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO12_EDGE_LOW</name>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO12_LEVEL_HIGH</name>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO12_LEVEL_LOW</name>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO11_EDGE_HIGH</name>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO11_EDGE_LOW</name>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO11_LEVEL_HIGH</name>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO11_LEVEL_LOW</name>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO10_EDGE_HIGH</name>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO10_EDGE_LOW</name>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO10_LEVEL_HIGH</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO10_LEVEL_LOW</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO9_EDGE_HIGH</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO9_EDGE_LOW</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO9_LEVEL_HIGH</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO9_LEVEL_LOW</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO8_EDGE_HIGH</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO8_EDGE_LOW</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO8_LEVEL_HIGH</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO8_LEVEL_LOW</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PROC1_INTS2</name>
+                <addressOffset>0x00000158</addressOffset>
+                <description>Interrupt status after masking &amp; forcing for proc1</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>GPIO23_EDGE_HIGH</name>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO23_EDGE_LOW</name>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO23_LEVEL_HIGH</name>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO23_LEVEL_LOW</name>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO22_EDGE_HIGH</name>
+                        <bitRange>[27:27]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO22_EDGE_LOW</name>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO22_LEVEL_HIGH</name>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO22_LEVEL_LOW</name>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO21_EDGE_HIGH</name>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO21_EDGE_LOW</name>
+                        <bitRange>[22:22]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO21_LEVEL_HIGH</name>
+                        <bitRange>[21:21]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO21_LEVEL_LOW</name>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO20_EDGE_HIGH</name>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO20_EDGE_LOW</name>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO20_LEVEL_HIGH</name>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO20_LEVEL_LOW</name>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO19_EDGE_HIGH</name>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO19_EDGE_LOW</name>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO19_LEVEL_HIGH</name>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO19_LEVEL_LOW</name>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO18_EDGE_HIGH</name>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO18_EDGE_LOW</name>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO18_LEVEL_HIGH</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO18_LEVEL_LOW</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO17_EDGE_HIGH</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO17_EDGE_LOW</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO17_LEVEL_HIGH</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO17_LEVEL_LOW</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO16_EDGE_HIGH</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO16_EDGE_LOW</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO16_LEVEL_HIGH</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO16_LEVEL_LOW</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PROC1_INTS3</name>
+                <addressOffset>0x0000015c</addressOffset>
+                <description>Interrupt status after masking &amp; forcing for proc1</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>GPIO29_EDGE_HIGH</name>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO29_EDGE_LOW</name>
+                        <bitRange>[22:22]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO29_LEVEL_HIGH</name>
+                        <bitRange>[21:21]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO29_LEVEL_LOW</name>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO28_EDGE_HIGH</name>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO28_EDGE_LOW</name>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO28_LEVEL_HIGH</name>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO28_LEVEL_LOW</name>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO27_EDGE_HIGH</name>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO27_EDGE_LOW</name>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO27_LEVEL_HIGH</name>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO27_LEVEL_LOW</name>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO26_EDGE_HIGH</name>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO26_EDGE_LOW</name>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO26_LEVEL_HIGH</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO26_LEVEL_LOW</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO25_EDGE_HIGH</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO25_EDGE_LOW</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO25_LEVEL_HIGH</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO25_LEVEL_LOW</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO24_EDGE_HIGH</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO24_EDGE_LOW</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO24_LEVEL_HIGH</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO24_LEVEL_LOW</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>DORMANT_WAKE_INTE0</name>
+                <addressOffset>0x00000160</addressOffset>
+                <description>Interrupt Enable for dormant_wake</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>GPIO7_EDGE_HIGH</name>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO7_EDGE_LOW</name>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO7_LEVEL_HIGH</name>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO7_LEVEL_LOW</name>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO6_EDGE_HIGH</name>
+                        <bitRange>[27:27]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO6_EDGE_LOW</name>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO6_LEVEL_HIGH</name>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO6_LEVEL_LOW</name>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO5_EDGE_HIGH</name>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO5_EDGE_LOW</name>
+                        <bitRange>[22:22]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO5_LEVEL_HIGH</name>
+                        <bitRange>[21:21]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO5_LEVEL_LOW</name>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO4_EDGE_HIGH</name>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO4_EDGE_LOW</name>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO4_LEVEL_HIGH</name>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO4_LEVEL_LOW</name>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO3_EDGE_HIGH</name>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO3_EDGE_LOW</name>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO3_LEVEL_HIGH</name>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO3_LEVEL_LOW</name>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO2_EDGE_HIGH</name>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO2_EDGE_LOW</name>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO2_LEVEL_HIGH</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO2_LEVEL_LOW</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO1_EDGE_HIGH</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO1_EDGE_LOW</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO1_LEVEL_HIGH</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO1_LEVEL_LOW</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO0_EDGE_HIGH</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO0_EDGE_LOW</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO0_LEVEL_HIGH</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO0_LEVEL_LOW</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>DORMANT_WAKE_INTE1</name>
+                <addressOffset>0x00000164</addressOffset>
+                <description>Interrupt Enable for dormant_wake</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>GPIO15_EDGE_HIGH</name>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO15_EDGE_LOW</name>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO15_LEVEL_HIGH</name>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO15_LEVEL_LOW</name>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO14_EDGE_HIGH</name>
+                        <bitRange>[27:27]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO14_EDGE_LOW</name>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO14_LEVEL_HIGH</name>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO14_LEVEL_LOW</name>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO13_EDGE_HIGH</name>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO13_EDGE_LOW</name>
+                        <bitRange>[22:22]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO13_LEVEL_HIGH</name>
+                        <bitRange>[21:21]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO13_LEVEL_LOW</name>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO12_EDGE_HIGH</name>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO12_EDGE_LOW</name>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO12_LEVEL_HIGH</name>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO12_LEVEL_LOW</name>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO11_EDGE_HIGH</name>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO11_EDGE_LOW</name>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO11_LEVEL_HIGH</name>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO11_LEVEL_LOW</name>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO10_EDGE_HIGH</name>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO10_EDGE_LOW</name>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO10_LEVEL_HIGH</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO10_LEVEL_LOW</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO9_EDGE_HIGH</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO9_EDGE_LOW</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO9_LEVEL_HIGH</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO9_LEVEL_LOW</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO8_EDGE_HIGH</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO8_EDGE_LOW</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO8_LEVEL_HIGH</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO8_LEVEL_LOW</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>DORMANT_WAKE_INTE2</name>
+                <addressOffset>0x00000168</addressOffset>
+                <description>Interrupt Enable for dormant_wake</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>GPIO23_EDGE_HIGH</name>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO23_EDGE_LOW</name>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO23_LEVEL_HIGH</name>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO23_LEVEL_LOW</name>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO22_EDGE_HIGH</name>
+                        <bitRange>[27:27]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO22_EDGE_LOW</name>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO22_LEVEL_HIGH</name>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO22_LEVEL_LOW</name>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO21_EDGE_HIGH</name>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO21_EDGE_LOW</name>
+                        <bitRange>[22:22]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO21_LEVEL_HIGH</name>
+                        <bitRange>[21:21]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO21_LEVEL_LOW</name>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO20_EDGE_HIGH</name>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO20_EDGE_LOW</name>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO20_LEVEL_HIGH</name>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO20_LEVEL_LOW</name>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO19_EDGE_HIGH</name>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO19_EDGE_LOW</name>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO19_LEVEL_HIGH</name>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO19_LEVEL_LOW</name>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO18_EDGE_HIGH</name>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO18_EDGE_LOW</name>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO18_LEVEL_HIGH</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO18_LEVEL_LOW</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO17_EDGE_HIGH</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO17_EDGE_LOW</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO17_LEVEL_HIGH</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO17_LEVEL_LOW</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO16_EDGE_HIGH</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO16_EDGE_LOW</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO16_LEVEL_HIGH</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO16_LEVEL_LOW</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>DORMANT_WAKE_INTE3</name>
+                <addressOffset>0x0000016c</addressOffset>
+                <description>Interrupt Enable for dormant_wake</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>GPIO29_EDGE_HIGH</name>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO29_EDGE_LOW</name>
+                        <bitRange>[22:22]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO29_LEVEL_HIGH</name>
+                        <bitRange>[21:21]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO29_LEVEL_LOW</name>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO28_EDGE_HIGH</name>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO28_EDGE_LOW</name>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO28_LEVEL_HIGH</name>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO28_LEVEL_LOW</name>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO27_EDGE_HIGH</name>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO27_EDGE_LOW</name>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO27_LEVEL_HIGH</name>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO27_LEVEL_LOW</name>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO26_EDGE_HIGH</name>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO26_EDGE_LOW</name>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO26_LEVEL_HIGH</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO26_LEVEL_LOW</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO25_EDGE_HIGH</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO25_EDGE_LOW</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO25_LEVEL_HIGH</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO25_LEVEL_LOW</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO24_EDGE_HIGH</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO24_EDGE_LOW</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO24_LEVEL_HIGH</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO24_LEVEL_LOW</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>DORMANT_WAKE_INTF0</name>
+                <addressOffset>0x00000170</addressOffset>
+                <description>Interrupt Force for dormant_wake</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>GPIO7_EDGE_HIGH</name>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO7_EDGE_LOW</name>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO7_LEVEL_HIGH</name>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO7_LEVEL_LOW</name>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO6_EDGE_HIGH</name>
+                        <bitRange>[27:27]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO6_EDGE_LOW</name>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO6_LEVEL_HIGH</name>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO6_LEVEL_LOW</name>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO5_EDGE_HIGH</name>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO5_EDGE_LOW</name>
+                        <bitRange>[22:22]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO5_LEVEL_HIGH</name>
+                        <bitRange>[21:21]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO5_LEVEL_LOW</name>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO4_EDGE_HIGH</name>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO4_EDGE_LOW</name>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO4_LEVEL_HIGH</name>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO4_LEVEL_LOW</name>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO3_EDGE_HIGH</name>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO3_EDGE_LOW</name>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO3_LEVEL_HIGH</name>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO3_LEVEL_LOW</name>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO2_EDGE_HIGH</name>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO2_EDGE_LOW</name>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO2_LEVEL_HIGH</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO2_LEVEL_LOW</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO1_EDGE_HIGH</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO1_EDGE_LOW</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO1_LEVEL_HIGH</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO1_LEVEL_LOW</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO0_EDGE_HIGH</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO0_EDGE_LOW</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO0_LEVEL_HIGH</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO0_LEVEL_LOW</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>DORMANT_WAKE_INTF1</name>
+                <addressOffset>0x00000174</addressOffset>
+                <description>Interrupt Force for dormant_wake</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>GPIO15_EDGE_HIGH</name>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO15_EDGE_LOW</name>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO15_LEVEL_HIGH</name>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO15_LEVEL_LOW</name>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO14_EDGE_HIGH</name>
+                        <bitRange>[27:27]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO14_EDGE_LOW</name>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO14_LEVEL_HIGH</name>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO14_LEVEL_LOW</name>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO13_EDGE_HIGH</name>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO13_EDGE_LOW</name>
+                        <bitRange>[22:22]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO13_LEVEL_HIGH</name>
+                        <bitRange>[21:21]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO13_LEVEL_LOW</name>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO12_EDGE_HIGH</name>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO12_EDGE_LOW</name>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO12_LEVEL_HIGH</name>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO12_LEVEL_LOW</name>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO11_EDGE_HIGH</name>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO11_EDGE_LOW</name>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO11_LEVEL_HIGH</name>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO11_LEVEL_LOW</name>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO10_EDGE_HIGH</name>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO10_EDGE_LOW</name>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO10_LEVEL_HIGH</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO10_LEVEL_LOW</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO9_EDGE_HIGH</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO9_EDGE_LOW</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO9_LEVEL_HIGH</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO9_LEVEL_LOW</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO8_EDGE_HIGH</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO8_EDGE_LOW</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO8_LEVEL_HIGH</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO8_LEVEL_LOW</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>DORMANT_WAKE_INTF2</name>
+                <addressOffset>0x00000178</addressOffset>
+                <description>Interrupt Force for dormant_wake</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>GPIO23_EDGE_HIGH</name>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO23_EDGE_LOW</name>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO23_LEVEL_HIGH</name>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO23_LEVEL_LOW</name>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO22_EDGE_HIGH</name>
+                        <bitRange>[27:27]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO22_EDGE_LOW</name>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO22_LEVEL_HIGH</name>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO22_LEVEL_LOW</name>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO21_EDGE_HIGH</name>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO21_EDGE_LOW</name>
+                        <bitRange>[22:22]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO21_LEVEL_HIGH</name>
+                        <bitRange>[21:21]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO21_LEVEL_LOW</name>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO20_EDGE_HIGH</name>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO20_EDGE_LOW</name>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO20_LEVEL_HIGH</name>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO20_LEVEL_LOW</name>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO19_EDGE_HIGH</name>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO19_EDGE_LOW</name>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO19_LEVEL_HIGH</name>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO19_LEVEL_LOW</name>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO18_EDGE_HIGH</name>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO18_EDGE_LOW</name>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO18_LEVEL_HIGH</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO18_LEVEL_LOW</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO17_EDGE_HIGH</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO17_EDGE_LOW</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO17_LEVEL_HIGH</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO17_LEVEL_LOW</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO16_EDGE_HIGH</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO16_EDGE_LOW</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO16_LEVEL_HIGH</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO16_LEVEL_LOW</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>DORMANT_WAKE_INTF3</name>
+                <addressOffset>0x0000017c</addressOffset>
+                <description>Interrupt Force for dormant_wake</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>GPIO29_EDGE_HIGH</name>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO29_EDGE_LOW</name>
+                        <bitRange>[22:22]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO29_LEVEL_HIGH</name>
+                        <bitRange>[21:21]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO29_LEVEL_LOW</name>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO28_EDGE_HIGH</name>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO28_EDGE_LOW</name>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO28_LEVEL_HIGH</name>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO28_LEVEL_LOW</name>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO27_EDGE_HIGH</name>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO27_EDGE_LOW</name>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO27_LEVEL_HIGH</name>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO27_LEVEL_LOW</name>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO26_EDGE_HIGH</name>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO26_EDGE_LOW</name>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO26_LEVEL_HIGH</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO26_LEVEL_LOW</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO25_EDGE_HIGH</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO25_EDGE_LOW</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO25_LEVEL_HIGH</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO25_LEVEL_LOW</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO24_EDGE_HIGH</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO24_EDGE_LOW</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO24_LEVEL_HIGH</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO24_LEVEL_LOW</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>DORMANT_WAKE_INTS0</name>
+                <addressOffset>0x00000180</addressOffset>
+                <description>Interrupt status after masking &amp; forcing for dormant_wake</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>GPIO7_EDGE_HIGH</name>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO7_EDGE_LOW</name>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO7_LEVEL_HIGH</name>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO7_LEVEL_LOW</name>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO6_EDGE_HIGH</name>
+                        <bitRange>[27:27]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO6_EDGE_LOW</name>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO6_LEVEL_HIGH</name>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO6_LEVEL_LOW</name>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO5_EDGE_HIGH</name>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO5_EDGE_LOW</name>
+                        <bitRange>[22:22]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO5_LEVEL_HIGH</name>
+                        <bitRange>[21:21]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO5_LEVEL_LOW</name>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO4_EDGE_HIGH</name>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO4_EDGE_LOW</name>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO4_LEVEL_HIGH</name>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO4_LEVEL_LOW</name>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO3_EDGE_HIGH</name>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO3_EDGE_LOW</name>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO3_LEVEL_HIGH</name>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO3_LEVEL_LOW</name>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO2_EDGE_HIGH</name>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO2_EDGE_LOW</name>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO2_LEVEL_HIGH</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO2_LEVEL_LOW</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO1_EDGE_HIGH</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO1_EDGE_LOW</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO1_LEVEL_HIGH</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO1_LEVEL_LOW</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO0_EDGE_HIGH</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO0_EDGE_LOW</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO0_LEVEL_HIGH</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO0_LEVEL_LOW</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>DORMANT_WAKE_INTS1</name>
+                <addressOffset>0x00000184</addressOffset>
+                <description>Interrupt status after masking &amp; forcing for dormant_wake</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>GPIO15_EDGE_HIGH</name>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO15_EDGE_LOW</name>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO15_LEVEL_HIGH</name>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO15_LEVEL_LOW</name>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO14_EDGE_HIGH</name>
+                        <bitRange>[27:27]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO14_EDGE_LOW</name>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO14_LEVEL_HIGH</name>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO14_LEVEL_LOW</name>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO13_EDGE_HIGH</name>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO13_EDGE_LOW</name>
+                        <bitRange>[22:22]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO13_LEVEL_HIGH</name>
+                        <bitRange>[21:21]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO13_LEVEL_LOW</name>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO12_EDGE_HIGH</name>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO12_EDGE_LOW</name>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO12_LEVEL_HIGH</name>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO12_LEVEL_LOW</name>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO11_EDGE_HIGH</name>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO11_EDGE_LOW</name>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO11_LEVEL_HIGH</name>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO11_LEVEL_LOW</name>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO10_EDGE_HIGH</name>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO10_EDGE_LOW</name>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO10_LEVEL_HIGH</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO10_LEVEL_LOW</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO9_EDGE_HIGH</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO9_EDGE_LOW</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO9_LEVEL_HIGH</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO9_LEVEL_LOW</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO8_EDGE_HIGH</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO8_EDGE_LOW</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO8_LEVEL_HIGH</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO8_LEVEL_LOW</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>DORMANT_WAKE_INTS2</name>
+                <addressOffset>0x00000188</addressOffset>
+                <description>Interrupt status after masking &amp; forcing for dormant_wake</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>GPIO23_EDGE_HIGH</name>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO23_EDGE_LOW</name>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO23_LEVEL_HIGH</name>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO23_LEVEL_LOW</name>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO22_EDGE_HIGH</name>
+                        <bitRange>[27:27]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO22_EDGE_LOW</name>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO22_LEVEL_HIGH</name>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO22_LEVEL_LOW</name>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO21_EDGE_HIGH</name>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO21_EDGE_LOW</name>
+                        <bitRange>[22:22]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO21_LEVEL_HIGH</name>
+                        <bitRange>[21:21]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO21_LEVEL_LOW</name>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO20_EDGE_HIGH</name>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO20_EDGE_LOW</name>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO20_LEVEL_HIGH</name>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO20_LEVEL_LOW</name>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO19_EDGE_HIGH</name>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO19_EDGE_LOW</name>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO19_LEVEL_HIGH</name>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO19_LEVEL_LOW</name>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO18_EDGE_HIGH</name>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO18_EDGE_LOW</name>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO18_LEVEL_HIGH</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO18_LEVEL_LOW</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO17_EDGE_HIGH</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO17_EDGE_LOW</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO17_LEVEL_HIGH</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO17_LEVEL_LOW</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO16_EDGE_HIGH</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO16_EDGE_LOW</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO16_LEVEL_HIGH</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO16_LEVEL_LOW</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>DORMANT_WAKE_INTS3</name>
+                <addressOffset>0x0000018c</addressOffset>
+                <description>Interrupt status after masking &amp; forcing for dormant_wake</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>GPIO29_EDGE_HIGH</name>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO29_EDGE_LOW</name>
+                        <bitRange>[22:22]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO29_LEVEL_HIGH</name>
+                        <bitRange>[21:21]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO29_LEVEL_LOW</name>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO28_EDGE_HIGH</name>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO28_EDGE_LOW</name>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO28_LEVEL_HIGH</name>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO28_LEVEL_LOW</name>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO27_EDGE_HIGH</name>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO27_EDGE_LOW</name>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO27_LEVEL_HIGH</name>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO27_LEVEL_LOW</name>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO26_EDGE_HIGH</name>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO26_EDGE_LOW</name>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO26_LEVEL_HIGH</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO26_LEVEL_LOW</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO25_EDGE_HIGH</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO25_EDGE_LOW</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO25_LEVEL_HIGH</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO25_LEVEL_LOW</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO24_EDGE_HIGH</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO24_EDGE_LOW</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO24_LEVEL_HIGH</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO24_LEVEL_LOW</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+        </registers>
+    </peripheral>
+    <peripheral>
+        <name>SYSINFO</name>
+        <baseAddress>0x40000000</baseAddress>
+        <addressBlock>
+            <offset>0</offset>
+            <size>20</size>
+            <usage>registers</usage>
+        </addressBlock>
+        <registers>
+            <register>
+                <name>CHIP_ID</name>
+                <addressOffset>0x00000000</addressOffset>
+                <description>JEDEC JEP-106 compliant chip identifier.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>REVISION</name>
+                        <bitRange>[31:28]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>PART</name>
+                        <bitRange>[27:12]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>MANUFACTURER</name>
+                        <bitRange>[11:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PLATFORM</name>
+                <addressOffset>0x00000004</addressOffset>
+                <description>Platform register. Allows software to know what environment it is running in.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>ASIC</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>FPGA</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GITREF_RP2040</name>
+                <addressOffset>0x00000010</addressOffset>
+                <description>Git hash of the chip source. Used to identify chip version.</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>GITREF_RP2040</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+        </registers>
+    </peripheral>
+    <peripheral>
+        <name>PPB</name>
+        <baseAddress>0xe0000000</baseAddress>
+        <addressBlock>
+            <offset>0</offset>
+            <size>60836</size>
+            <usage>registers</usage>
+        </addressBlock>
+        <registers>
+            <register>
+                <name>SYST_CSR</name>
+                <addressOffset>0x0000e010</addressOffset>
+                <description>Use the SysTick Control and Status Register to enable the SysTick features.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>COUNTFLAG</name>
+                        <description>Returns 1 if timer counted to 0 since last time this was read. Clears on read by application or debugger.</description>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CLKSOURCE</name>
+                        <description>SysTick clock source. Always reads as one if SYST_CALIB reports NOREF. 
+                            Selects the SysTick timer clock source: 
+                            0 = External reference clock. 
+                            1 = Processor clock.</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>TICKINT</name>
+                        <description>Enables SysTick exception request: 
+                            0 = Counting down to zero does not assert the SysTick exception request. 
+                            1 = Counting down to zero to asserts the SysTick exception request.</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ENABLE</name>
+                        <description>Enable SysTick counter: 
+                            0 = Counter disabled. 
+                            1 = Counter enabled.</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SYST_RVR</name>
+                <addressOffset>0x0000e014</addressOffset>
+                <description>Use the SysTick Reload Value Register to specify the start value to load into the current value register when the counter reaches 0. It can be any value between 0 and 0x00FFFFFF. A start value of 0 is possible, but has no effect because the SysTick interrupt and COUNTFLAG are activated when counting from 1 to 0. The reset value of this register is UNKNOWN. 
+                    To generate a multi-shot timer with a period of N processor clock cycles, use a RELOAD value of N-1. For example, if the SysTick interrupt is required every 100 clock pulses, set RELOAD to 99.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>RELOAD</name>
+                        <description>Value to load into the SysTick Current Value Register when the counter reaches 0.</description>
+                        <bitRange>[23:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SYST_CVR</name>
+                <addressOffset>0x0000e018</addressOffset>
+                <description>Use the SysTick Current Value Register to find the current value in the register. The reset value of this register is UNKNOWN.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CURRENT</name>
+                        <description>Reads return the current value of the SysTick counter. This register is write-clear. Writing to it with any value clears the register to 0. Clearing this register also clears the COUNTFLAG bit of the SysTick Control and Status Register.</description>
+                        <bitRange>[23:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SYST_CALIB</name>
+                <addressOffset>0x0000e01c</addressOffset>
+                <description>Use the SysTick Calibration Value Register to enable software to scale to any required speed using divide and multiply.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>NOREF</name>
+                        <description>If reads as 1, the Reference clock is not provided - the CLKSOURCE bit of the SysTick Control and Status register will be forced to 1 and cannot be cleared to 0.</description>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SKEW</name>
+                        <description>If reads as 1, the calibration value for 10ms is inexact (due to clock frequency).</description>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>TENMS</name>
+                        <description>An optional Reload value to be used for 10ms (100Hz) timing, subject to system clock skew errors. If the value reads as 0, the calibration value is not known.</description>
+                        <bitRange>[23:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>NVIC_ISER</name>
+                <addressOffset>0x0000e100</addressOffset>
+                <description>Use the Interrupt Set-Enable Register to enable interrupts and determine which interrupts are currently enabled. 
+                    If a pending interrupt is enabled, the NVIC activates the interrupt based on its priority. If an interrupt is not enabled, asserting its interrupt signal changes the interrupt state to pending, but the NVIC never activates the interrupt, regardless of its priority.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>SETENA</name>
+                        <description>Interrupt set-enable bits. 
+                            Write: 
+                            0 = No effect. 
+                            1 = Enable interrupt. 
+                            Read: 
+                            0 = Interrupt disabled. 
+                            1 = Interrupt enabled.</description>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>NVIC_ICER</name>
+                <addressOffset>0x0000e180</addressOffset>
+                <description>Use the Interrupt Clear-Enable Registers to disable interrupts and determine which interrupts are currently enabled.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CLRENA</name>
+                        <description>Interrupt clear-enable bits. 
+                            Write: 
+                            0 = No effect. 
+                            1 = Disable interrupt. 
+                            Read: 
+                            0 = Interrupt disabled. 
+                            1 = Interrupt enabled.</description>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>NVIC_ISPR</name>
+                <addressOffset>0x0000e200</addressOffset>
+                <description>The NVIC_ISPR forces interrupts into the pending state, and shows which interrupts are pending.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>SETPEND</name>
+                        <description>Interrupt set-pending bits. 
+                            Write: 
+                            0 = No effect. 
+                            1 = Changes interrupt state to pending. 
+                            Read: 
+                            0 = Interrupt is not pending. 
+                            1 = Interrupt is pending. 
+                            Note: Writing 1 to the NVIC_ISPR bit corresponding to: 
+                            An interrupt that is pending has no effect. 
+                            A disabled interrupt sets the state of that interrupt to pending.</description>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>NVIC_ICPR</name>
+                <addressOffset>0x0000e280</addressOffset>
+                <description>Use the Interrupt Clear-Pending Register to clear pending interrupts and determine which interrupts are currently pending.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CLRPEND</name>
+                        <description>Interrupt clear-pending bits. 
+                            Write: 
+                            0 = No effect. 
+                            1 = Removes pending state and interrupt. 
+                            Read: 
+                            0 = Interrupt is not pending. 
+                            1 = Interrupt is pending.</description>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>NVIC_IPR0</name>
+                <addressOffset>0x0000e400</addressOffset>
+                <description>Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest. 
+                    Note: Writing 1 to an NVIC_ICPR bit does not affect the active state of the corresponding interrupt. 
+                    These registers are only word-accessible</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>IP_3</name>
+                        <description>Priority of interrupt 3</description>
+                        <bitRange>[31:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>IP_2</name>
+                        <description>Priority of interrupt 2</description>
+                        <bitRange>[23:22]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>IP_1</name>
+                        <description>Priority of interrupt 1</description>
+                        <bitRange>[15:14]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>IP_0</name>
+                        <description>Priority of interrupt 0</description>
+                        <bitRange>[7:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>NVIC_IPR1</name>
+                <addressOffset>0x0000e404</addressOffset>
+                <description>Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>IP_7</name>
+                        <description>Priority of interrupt 7</description>
+                        <bitRange>[31:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>IP_6</name>
+                        <description>Priority of interrupt 6</description>
+                        <bitRange>[23:22]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>IP_5</name>
+                        <description>Priority of interrupt 5</description>
+                        <bitRange>[15:14]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>IP_4</name>
+                        <description>Priority of interrupt 4</description>
+                        <bitRange>[7:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>NVIC_IPR2</name>
+                <addressOffset>0x0000e408</addressOffset>
+                <description>Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>IP_11</name>
+                        <description>Priority of interrupt 11</description>
+                        <bitRange>[31:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>IP_10</name>
+                        <description>Priority of interrupt 10</description>
+                        <bitRange>[23:22]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>IP_9</name>
+                        <description>Priority of interrupt 9</description>
+                        <bitRange>[15:14]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>IP_8</name>
+                        <description>Priority of interrupt 8</description>
+                        <bitRange>[7:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>NVIC_IPR3</name>
+                <addressOffset>0x0000e40c</addressOffset>
+                <description>Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>IP_15</name>
+                        <description>Priority of interrupt 15</description>
+                        <bitRange>[31:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>IP_14</name>
+                        <description>Priority of interrupt 14</description>
+                        <bitRange>[23:22]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>IP_13</name>
+                        <description>Priority of interrupt 13</description>
+                        <bitRange>[15:14]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>IP_12</name>
+                        <description>Priority of interrupt 12</description>
+                        <bitRange>[7:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>NVIC_IPR4</name>
+                <addressOffset>0x0000e410</addressOffset>
+                <description>Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>IP_19</name>
+                        <description>Priority of interrupt 19</description>
+                        <bitRange>[31:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>IP_18</name>
+                        <description>Priority of interrupt 18</description>
+                        <bitRange>[23:22]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>IP_17</name>
+                        <description>Priority of interrupt 17</description>
+                        <bitRange>[15:14]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>IP_16</name>
+                        <description>Priority of interrupt 16</description>
+                        <bitRange>[7:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>NVIC_IPR5</name>
+                <addressOffset>0x0000e414</addressOffset>
+                <description>Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>IP_23</name>
+                        <description>Priority of interrupt 23</description>
+                        <bitRange>[31:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>IP_22</name>
+                        <description>Priority of interrupt 22</description>
+                        <bitRange>[23:22]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>IP_21</name>
+                        <description>Priority of interrupt 21</description>
+                        <bitRange>[15:14]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>IP_20</name>
+                        <description>Priority of interrupt 20</description>
+                        <bitRange>[7:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>NVIC_IPR6</name>
+                <addressOffset>0x0000e418</addressOffset>
+                <description>Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>IP_27</name>
+                        <description>Priority of interrupt 27</description>
+                        <bitRange>[31:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>IP_26</name>
+                        <description>Priority of interrupt 26</description>
+                        <bitRange>[23:22]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>IP_25</name>
+                        <description>Priority of interrupt 25</description>
+                        <bitRange>[15:14]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>IP_24</name>
+                        <description>Priority of interrupt 24</description>
+                        <bitRange>[7:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>NVIC_IPR7</name>
+                <addressOffset>0x0000e41c</addressOffset>
+                <description>Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>IP_31</name>
+                        <description>Priority of interrupt 31</description>
+                        <bitRange>[31:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>IP_30</name>
+                        <description>Priority of interrupt 30</description>
+                        <bitRange>[23:22]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>IP_29</name>
+                        <description>Priority of interrupt 29</description>
+                        <bitRange>[15:14]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>IP_28</name>
+                        <description>Priority of interrupt 28</description>
+                        <bitRange>[7:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CPUID</name>
+                <addressOffset>0x0000ed00</addressOffset>
+                <description>Read the CPU ID Base Register to determine: the ID number of the processor core, the version number of the processor core, the implementation details of the processor core.</description>
+                <resetValue>0x410cc601</resetValue>
+                <fields>
+                    <field>
+                        <name>IMPLEMENTER</name>
+                        <description>Implementor code: 0x41 = ARM</description>
+                        <bitRange>[31:24]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>VARIANT</name>
+                        <description>Major revision number n in the rnpm revision status: 
+                            0x0 = Revision 0.</description>
+                        <bitRange>[23:20]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>ARCHITECTURE</name>
+                        <description>Constant that defines the architecture of the processor: 
+                            0xC = ARMv6-M architecture.</description>
+                        <bitRange>[19:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>PARTNO</name>
+                        <description>Number of processor within family: 0xC60 = Cortex-M0+</description>
+                        <bitRange>[15:4]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>REVISION</name>
+                        <description>Minor revision number m in the rnpm revision status: 
+                            0x1 = Patch 1.</description>
+                        <bitRange>[3:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>ICSR</name>
+                <addressOffset>0x0000ed04</addressOffset>
+                <description>Use the Interrupt Control State Register to set a pending Non-Maskable Interrupt (NMI), set or clear a pending PendSV, set or clear a pending SysTick, check for pending exceptions, check the vector number of the highest priority pended exception, check the vector number of the active exception.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>NMIPENDSET</name>
+                        <description>Setting this bit will activate an NMI. Since NMI is the highest priority exception, it will activate as soon as it is registered. 
+                            NMI set-pending bit. 
+                            Write: 
+                            0 = No effect. 
+                            1 = Changes NMI exception state to pending. 
+                            Read: 
+                            0 = NMI exception is not pending. 
+                            1 = NMI exception is pending. 
+                            Because NMI is the highest-priority exception, normally the processor enters the NMI 
+                            exception handler as soon as it detects a write of 1 to this bit. Entering the handler then clears 
+                            this bit to 0. This means a read of this bit by the NMI exception handler returns 1 only if the 
+                            NMI signal is reasserted while the processor is executing that handler.</description>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PENDSVSET</name>
+                        <description>PendSV set-pending bit. 
+                            Write: 
+                            0 = No effect. 
+                            1 = Changes PendSV exception state to pending. 
+                            Read: 
+                            0 = PendSV exception is not pending. 
+                            1 = PendSV exception is pending. 
+                            Writing 1 to this bit is the only way to set the PendSV exception state to pending.</description>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PENDSVCLR</name>
+                        <description>PendSV clear-pending bit. 
+                            Write: 
+                            0 = No effect. 
+                            1 = Removes the pending state from the PendSV exception.</description>
+                        <bitRange>[27:27]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PENDSTSET</name>
+                        <description>SysTick exception set-pending bit. 
+                            Write: 
+                            0 = No effect. 
+                            1 = Changes SysTick exception state to pending. 
+                            Read: 
+                            0 = SysTick exception is not pending. 
+                            1 = SysTick exception is pending.</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PENDSTCLR</name>
+                        <description>SysTick exception clear-pending bit. 
+                            Write: 
+                            0 = No effect. 
+                            1 = Removes the pending state from the SysTick exception. 
+                            This bit is WO. On a register read its value is Unknown.</description>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ISRPREEMPT</name>
+                        <description>The system can only access this bit when the core is halted. It indicates that a pending interrupt is to be taken in the next running cycle. If C_MASKINTS is clear in the Debug Halting Control and Status Register, the interrupt is serviced.</description>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>ISRPENDING</name>
+                        <description>External interrupt pending flag</description>
+                        <bitRange>[22:22]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>VECTPENDING</name>
+                        <description>Indicates the exception number for the highest priority pending exception: 0 = no pending exceptions. Non zero = The pending state includes the effect of memory-mapped enable and mask registers. It does not include the PRIMASK special-purpose register qualifier.</description>
+                        <bitRange>[20:12]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>VECTACTIVE</name>
+                        <description>Active exception number field. Reset clears the VECTACTIVE field.</description>
+                        <bitRange>[8:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>VTOR</name>
+                <addressOffset>0x0000ed08</addressOffset>
+                <description>The VTOR holds the vector table offset address.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>TBLOFF</name>
+                        <description>Bits [31:8] of the indicate the vector table offset address.</description>
+                        <bitRange>[31:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>AIRCR</name>
+                <addressOffset>0x0000ed0c</addressOffset>
+                <description>Use the Application Interrupt and Reset Control Register to: determine data endianness, clear all active state information from debug halt mode, request a system reset.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>VECTKEY</name>
+                        <description>Register key: 
+                            Reads as Unknown 
+                            On writes, write 0x05FA to VECTKEY, otherwise the write is ignored.</description>
+                        <bitRange>[31:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ENDIANESS</name>
+                        <description>Data endianness implemented: 
+                            0 = Little-endian.</description>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SYSRESETREQ</name>
+                        <description>Writing 1 to this bit causes the SYSRESETREQ signal to the outer system to be asserted to request a reset. The intention is to force a large system reset of all major components except for debug. The C_HALT bit in the DHCSR is cleared as a result of the system reset requested. The debugger does not lose contact with the device.</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>VECTCLRACTIVE</name>
+                        <description>Clears all active state information for fixed and configurable exceptions. This bit: is self-clearing, can only be set by the DAP when the core is halted.  When set: clears all active exception status of the processor, forces a return to Thread mode, forces an IPSR of 0. A debugger must re-initialize the stack.</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SCR</name>
+                <addressOffset>0x0000ed10</addressOffset>
+                <description>System Control Register. Use the System Control Register for power-management functions: signal to the system when the processor can enter a low power state, control how the processor enters and exits low power states.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>SEVONPEND</name>
+                        <description>Send Event on Pending bit: 
+                            0 = Only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded. 
+                            1 = Enabled events and all interrupts, including disabled interrupts, can wakeup the processor. 
+                            When an event or interrupt becomes pending, the event signal wakes up the processor from WFE. If the 
+                            processor is not waiting for an event, the event is registered and affects the next WFE. 
+                            The processor also wakes up on execution of an SEV instruction or an external event.</description>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SLEEPDEEP</name>
+                        <description>Controls whether the processor uses sleep or deep sleep as its low power mode: 
+                            0 = Sleep. 
+                            1 = Deep sleep.</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SLEEPONEXIT</name>
+                        <description>Indicates sleep-on-exit when returning from Handler mode to Thread mode: 
+                            0 = Do not sleep when returning to Thread mode. 
+                            1 = Enter sleep, or deep sleep, on return from an ISR to Thread mode. 
+                            Setting this bit to 1 enables an interrupt driven application to avoid returning to an empty main application.</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CCR</name>
+                <addressOffset>0x0000ed14</addressOffset>
+                <description>The Configuration and Control Register permanently enables stack alignment and causes unaligned accesses to result in a Hard Fault.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>STKALIGN</name>
+                        <description>Always reads as one, indicates 8-byte stack alignment on exception entry. On exception entry, the processor uses bit[9] of the stacked PSR to indicate the stack alignment. On return from the exception it uses this stacked bit to restore the correct stack alignment.</description>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>UNALIGN_TRP</name>
+                        <description>Always reads as one, indicates that all unaligned accesses generate a HardFault.</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SHPR2</name>
+                <addressOffset>0x0000ed1c</addressOffset>
+                <description>System handlers are a special class of exception handler that can have their priority set to any of the priority levels. Use the System Handler Priority Register 2 to set the priority of SVCall.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>PRI_11</name>
+                        <description>Priority of system handler 11, SVCall</description>
+                        <bitRange>[31:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SHPR3</name>
+                <addressOffset>0x0000ed20</addressOffset>
+                <description>System handlers are a special class of exception handler that can have their priority set to any of the priority levels. Use the System Handler Priority Register 3 to set the priority of PendSV and SysTick.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>PRI_15</name>
+                        <description>Priority of system handler 15, SysTick</description>
+                        <bitRange>[31:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PRI_14</name>
+                        <description>Priority of system handler 14, PendSV</description>
+                        <bitRange>[23:22]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SHCSR</name>
+                <addressOffset>0x0000ed24</addressOffset>
+                <description>Use the System Handler Control and State Register to determine or clear the pending status of SVCall.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>SVCALLPENDED</name>
+                        <description>Reads as 1 if SVCall is Pending.  Write 1 to set pending SVCall, write 0 to clear pending SVCall.</description>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>MPU_TYPE</name>
+                <addressOffset>0x0000ed90</addressOffset>
+                <description>Read the MPU Type Register to determine if the processor implements an MPU, and how many regions the MPU supports.</description>
+                <resetValue>0x00000800</resetValue>
+                <fields>
+                    <field>
+                        <name>IREGION</name>
+                        <description>Instruction region. Reads as zero as ARMv6-M only supports a unified MPU.</description>
+                        <bitRange>[23:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>DREGION</name>
+                        <description>Number of regions supported by the MPU.</description>
+                        <bitRange>[15:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SEPARATE</name>
+                        <description>Indicates support for separate instruction and data address maps. Reads as 0 as ARMv6-M only supports a unified MPU.</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>MPU_CTRL</name>
+                <addressOffset>0x0000ed94</addressOffset>
+                <description>Use the MPU Control Register to enable and disable the MPU, and to control whether the default memory map is enabled as a background region for privileged accesses, and whether the MPU is enabled for HardFaults and NMIs.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>PRIVDEFENA</name>
+                        <description>Controls whether the default memory map is enabled as a background region for privileged accesses. This bit is ignored when ENABLE is clear. 
+                            0 = If the MPU is enabled, disables use of the default memory map. Any memory access to a location not 
+                            covered by any enabled region causes a fault. 
+                            1 = If the MPU is enabled, enables use of the default memory map as a background region for privileged software accesses. 
+                            When enabled, the background region acts as if it is region number -1. Any region that is defined and enabled has priority over this default map.</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>HFNMIENA</name>
+                        <description>Controls the use of the MPU for HardFaults and NMIs. Setting this bit when ENABLE is clear results in UNPREDICTABLE behaviour. 
+                            When the MPU is enabled: 
+                            0 = MPU is disabled during HardFault and NMI handlers, regardless of the value of the ENABLE bit. 
+                            1 = the MPU is enabled during HardFault and NMI handlers.</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ENABLE</name>
+                        <description>Enables the MPU. If the MPU is disabled, privileged and unprivileged accesses use the default memory map. 
+                            0 = MPU disabled. 
+                            1 = MPU enabled.</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>MPU_RNR</name>
+                <addressOffset>0x0000ed98</addressOffset>
+                <description>Use the MPU Region Number Register to select the region currently accessed by MPU_RBAR and MPU_RASR.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>REGION</name>
+                        <description>Indicates the MPU region referenced by the MPU_RBAR and MPU_RASR registers. 
+                            The MPU supports 8 memory regions, so the permitted values of this field are 0-7.</description>
+                        <bitRange>[3:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>MPU_RBAR</name>
+                <addressOffset>0x0000ed9c</addressOffset>
+                <description>Read the MPU Region Base Address Register to determine the base address of the region identified by MPU_RNR. Write to update the base address of said region or that of a specified region, with whose number MPU_RNR will also be updated.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>ADDR</name>
+                        <description>Base address of the region.</description>
+                        <bitRange>[31:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>VALID</name>
+                        <description>On writes, indicates whether the write must update the base address of the region identified by the REGION field, updating the MPU_RNR to indicate this new region. 
+                            Write: 
+                            0 = MPU_RNR not changed, and the processor: 
+                            Updates the base address for the region specified in the MPU_RNR. 
+                            Ignores the value of the REGION field. 
+                            1 = The processor: 
+                            Updates the value of the MPU_RNR to the value of the REGION field. 
+                            Updates the base address for the region specified in the REGION field. 
+                            Always reads as zero.</description>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>REGION</name>
+                        <description>On writes, specifies the number of the region whose base address to update provided VALID is set written as 1. On reads, returns bits [3:0] of MPU_RNR.</description>
+                        <bitRange>[3:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>MPU_RASR</name>
+                <addressOffset>0x0000eda0</addressOffset>
+                <description>Use the MPU Region Attribute and Size Register to define the size, access behaviour and memory type of the region identified by MPU_RNR, and enable that region.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>ATTRS</name>
+                        <description>The MPU Region Attribute field. Use to define the region attribute control. 
+                            28 = XN: Instruction access disable bit: 
+                            0 = Instruction fetches enabled. 
+                            1 = Instruction fetches disabled. 
+                            26:24 = AP: Access permission field 
+                            18 = S: Shareable bit 
+                            17 = C: Cacheable bit 
+                            16 = B: Bufferable bit</description>
+                        <bitRange>[31:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SRD</name>
+                        <description>Subregion Disable. For regions of 256 bytes or larger, each bit of this field controls whether one of the eight equal subregions is enabled.</description>
+                        <bitRange>[15:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SIZE</name>
+                        <description>Indicates the region size. Region size in bytes = 2^(SIZE+1). The minimum permitted value is 7 (b00111) = 256Bytes</description>
+                        <bitRange>[5:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ENABLE</name>
+                        <description>Enables the region.</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+        </registers>
+    </peripheral>
+    <peripheral>
+        <name>SSI</name>
+        <description>DW_apb_ssi has the following features: 
+            * APB interface – Allows for easy integration into a DesignWare Synthesizable Components for AMBA 2 implementation. 
+            * APB3 and APB4 protocol support. 
+            * Scalable APB data bus width – Supports APB data bus widths of 8, 16, and 32 bits. 
+            * Serial-master or serial-slave operation – Enables serial communication with serial-master or serial-slave peripheral devices. 
+            * Programmable Dual/Quad/Octal SPI support in Master Mode. 
+            * Dual Data Rate (DDR) and Read Data Strobe (RDS) Support - Enables the DW_apb_ssi master to perform operations with the device in DDR and RDS modes when working in Dual/Quad/Octal mode of operation. 
+            * Data Mask Support - Enables the DW_apb_ssi to selectively update the bytes in the device. This feature is applicable only in enhanced SPI modes. 
+            * eXecute-In-Place (XIP) support - Enables the DW_apb_ssi master to behave as a memory mapped I/O and fetches the data from the device based on the APB read request. This feature is applicable only in enhanced SPI modes. 
+            * DMA Controller Interface – Enables the DW_apb_ssi to interface to a DMA controller over the bus using a handshaking interface for transfer requests. 
+            * Independent masking of interrupts – Master collision, transmit FIFO overflow, transmit FIFO empty, receive FIFO full, receive FIFO underflow, and receive FIFO overflow interrupts can all be masked independently. 
+            * Multi-master contention detection – Informs the processor of multiple serial-master accesses on the serial bus. 
+            * Bypass of meta-stability flip-flops for synchronous clocks – When the APB clock (pclk) and the DW_apb_ssi serial clock (ssi_clk) are synchronous, meta-stable flip-flops are not used when transferring control signals across these clock domains. 
+            * Programmable delay on the sample time of the received serial data bit (rxd); enables programmable control of routing delays resulting in higher serial data-bit rates. 
+            * Programmable features: 
+            - Serial interface operation – Choice of Motorola SPI, Texas Instruments Synchronous Serial Protocol or National Semiconductor Microwire. 
+            - Clock bit-rate – Dynamic control of the serial bit rate of the data transfer; used in only serial-master mode of operation. 
+            - Data Item size (4 to 32 bits) – Item size of each data transfer under the control of the programmer. 
+            * Configured features: 
+            - FIFO depth – 16 words deep. The FIFO width is fixed at 32 bits. 
+            - 1 slave select output. 
+            - Hardware slave-select – Dedicated hardware slave-select line. 
+            - Combined interrupt line - one combined interrupt line from the DW_apb_ssi to the interrupt controller. 
+            - Interrupt polarity – active high interrupt lines. 
+            - Serial clock polarity – low serial-clock polarity directly after reset. 
+            - Serial clock phase – capture on first edge of serial-clock directly after reset.</description>
+        <baseAddress>0x18000000</baseAddress>
+        <addressBlock>
+            <offset>0</offset>
+            <size>252</size>
+            <usage>registers</usage>
+        </addressBlock>
+        <registers>
+            <register>
+                <name>CTRLR0</name>
+                <addressOffset>0x00000000</addressOffset>
+                <description>Control register 0</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>SSTE</name>
+                        <description>Slave select toggle enable</description>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SPI_FRF</name>
+                        <description>SPI frame format</description>
+                        <bitRange>[22:21]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>STD</name>
+                                <value>0</value>
+                                <description>Standard 1-bit SPI frame format; 1 bit per SCK, full-duplex</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>DUAL</name>
+                                <value>1</value>
+                                <description>Dual-SPI frame format; two bits per SCK, half-duplex</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>QUAD</name>
+                                <value>2</value>
+                                <description>Quad-SPI frame format; four bits per SCK, half-duplex</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>DFS_32</name>
+                        <description>Data frame size in 32b transfer mode 
+                            Value of n -&gt; n+1 clocks per frame.</description>
+                        <bitRange>[20:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CFS</name>
+                        <description>Control frame size 
+                            Value of n -&gt; n+1 clocks per frame.</description>
+                        <bitRange>[15:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SRL</name>
+                        <description>Shift register loop (test mode)</description>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SLV_OE</name>
+                        <description>Slave output enable</description>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>TMOD</name>
+                        <description>Transfer mode</description>
+                        <bitRange>[9:8]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>TX_AND_RX</name>
+                                <value>0</value>
+                                <description>Both transmit and receive</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TX_ONLY</name>
+                                <value>1</value>
+                                <description>Transmit only (not for FRF == 0, standard SPI mode)</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>RX_ONLY</name>
+                                <value>2</value>
+                                <description>Receive only (not for FRF == 0, standard SPI mode)</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>EEPROM_READ</name>
+                                <value>3</value>
+                                <description>EEPROM read mode (TX then RX; RX starts after control data TX&#39;d)</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>SCPOL</name>
+                        <description>Serial clock polarity</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SCPH</name>
+                        <description>Serial clock phase</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>FRF</name>
+                        <description>Frame format</description>
+                        <bitRange>[5:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DFS</name>
+                        <description>Data frame size</description>
+                        <bitRange>[3:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CTRLR1</name>
+                <addressOffset>0x00000004</addressOffset>
+                <description>Master Control register 1</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>NDF</name>
+                        <description>Number of data frames</description>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SSIENR</name>
+                <addressOffset>0x00000008</addressOffset>
+                <description>SSI Enable</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>SSI_EN</name>
+                        <description>SSI enable</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>MWCR</name>
+                <addressOffset>0x0000000c</addressOffset>
+                <description>Microwire Control</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>MHS</name>
+                        <description>Microwire handshaking</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>MDD</name>
+                        <description>Microwire control</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>MWMOD</name>
+                        <description>Microwire transfer mode</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SER</name>
+                <addressOffset>0x00000010</addressOffset>
+                <description>Slave enable</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>SER</name>
+                        <description>For each bit: 
+                            0 -&gt; slave not selected 
+                            1 -&gt; slave selected</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>BAUDR</name>
+                <addressOffset>0x00000014</addressOffset>
+                <description>Baud rate</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>SCKDV</name>
+                        <description>SSI clock divider</description>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>TXFTLR</name>
+                <addressOffset>0x00000018</addressOffset>
+                <description>TX FIFO threshold level</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>TFT</name>
+                        <description>Transmit FIFO threshold</description>
+                        <bitRange>[7:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>RXFTLR</name>
+                <addressOffset>0x0000001c</addressOffset>
+                <description>RX FIFO threshold level</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>RFT</name>
+                        <description>Receive FIFO threshold</description>
+                        <bitRange>[7:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>TXFLR</name>
+                <addressOffset>0x00000020</addressOffset>
+                <description>TX FIFO level</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>TFTFL</name>
+                        <description>Transmit FIFO level</description>
+                        <bitRange>[7:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>RXFLR</name>
+                <addressOffset>0x00000024</addressOffset>
+                <description>RX FIFO level</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>RXTFL</name>
+                        <description>Receive FIFO level</description>
+                        <bitRange>[7:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SR</name>
+                <addressOffset>0x00000028</addressOffset>
+                <description>Status register</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>DCOL</name>
+                        <description>Data collision error</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>TXE</name>
+                        <description>Transmission error</description>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>RFF</name>
+                        <description>Receive FIFO full</description>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>RFNE</name>
+                        <description>Receive FIFO not empty</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>TFE</name>
+                        <description>Transmit FIFO empty</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>TFNF</name>
+                        <description>Transmit FIFO not full</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>BUSY</name>
+                        <description>SSI busy flag</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>IMR</name>
+                <addressOffset>0x0000002c</addressOffset>
+                <description>Interrupt mask</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>MSTIM</name>
+                        <description>Multi-master contention interrupt mask</description>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>RXFIM</name>
+                        <description>Receive FIFO full interrupt mask</description>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>RXOIM</name>
+                        <description>Receive FIFO overflow interrupt mask</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>RXUIM</name>
+                        <description>Receive FIFO underflow interrupt mask</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>TXOIM</name>
+                        <description>Transmit FIFO overflow interrupt mask</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>TXEIM</name>
+                        <description>Transmit FIFO empty interrupt mask</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>ISR</name>
+                <addressOffset>0x00000030</addressOffset>
+                <description>Interrupt status</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>MSTIS</name>
+                        <description>Multi-master contention interrupt status</description>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>RXFIS</name>
+                        <description>Receive FIFO full interrupt status</description>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>RXOIS</name>
+                        <description>Receive FIFO overflow interrupt status</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>RXUIS</name>
+                        <description>Receive FIFO underflow interrupt status</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>TXOIS</name>
+                        <description>Transmit FIFO overflow interrupt status</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>TXEIS</name>
+                        <description>Transmit FIFO empty interrupt status</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>RISR</name>
+                <addressOffset>0x00000034</addressOffset>
+                <description>Raw interrupt status</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>MSTIR</name>
+                        <description>Multi-master contention raw interrupt status</description>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>RXFIR</name>
+                        <description>Receive FIFO full raw interrupt status</description>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>RXOIR</name>
+                        <description>Receive FIFO overflow raw interrupt status</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>RXUIR</name>
+                        <description>Receive FIFO underflow raw interrupt status</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>TXOIR</name>
+                        <description>Transmit FIFO overflow raw interrupt status</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>TXEIR</name>
+                        <description>Transmit FIFO empty raw interrupt status</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>TXOICR</name>
+                <addressOffset>0x00000038</addressOffset>
+                <description>TX FIFO overflow interrupt clear</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>TXOICR</name>
+                        <description>Clear-on-read transmit FIFO overflow interrupt</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>RXOICR</name>
+                <addressOffset>0x0000003c</addressOffset>
+                <description>RX FIFO overflow interrupt clear</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>RXOICR</name>
+                        <description>Clear-on-read receive FIFO overflow interrupt</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>RXUICR</name>
+                <addressOffset>0x00000040</addressOffset>
+                <description>RX FIFO underflow interrupt clear</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>RXUICR</name>
+                        <description>Clear-on-read receive FIFO underflow interrupt</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>MSTICR</name>
+                <addressOffset>0x00000044</addressOffset>
+                <description>Multi-master interrupt clear</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>MSTICR</name>
+                        <description>Clear-on-read multi-master contention interrupt</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>ICR</name>
+                <addressOffset>0x00000048</addressOffset>
+                <description>Interrupt clear</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>ICR</name>
+                        <description>Clear-on-read all active interrupts</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>DMACR</name>
+                <addressOffset>0x0000004c</addressOffset>
+                <description>DMA control</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>TDMAE</name>
+                        <description>Transmit DMA enable</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>RDMAE</name>
+                        <description>Receive DMA enable</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>DMATDLR</name>
+                <addressOffset>0x00000050</addressOffset>
+                <description>DMA TX data level</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>DMATDL</name>
+                        <description>Transmit data watermark level</description>
+                        <bitRange>[7:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>DMARDLR</name>
+                <addressOffset>0x00000054</addressOffset>
+                <description>DMA RX data level</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>DMARDL</name>
+                        <description>Receive data watermark level (DMARDLR+1)</description>
+                        <bitRange>[7:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>IDR</name>
+                <addressOffset>0x00000058</addressOffset>
+                <description>Identification register</description>
+                <resetValue>0x51535049</resetValue>
+                <fields>
+                    <field>
+                        <name>IDCODE</name>
+                        <description>Peripheral dentification code</description>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SSI_VERSION_ID</name>
+                <addressOffset>0x0000005c</addressOffset>
+                <description>Version ID</description>
+                <resetValue>0x3430312a</resetValue>
+                <fields>
+                    <field>
+                        <name>SSI_COMP_VERSION</name>
+                        <description>SNPS component version (format X.YY)</description>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>DR0</name>
+                <addressOffset>0x00000060</addressOffset>
+                <description>Data Register 0 (of 36)</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>DR</name>
+                        <description>First data register of 36</description>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>RX_SAMPLE_DLY</name>
+                <addressOffset>0x000000f0</addressOffset>
+                <description>RX sample delay</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>RSD</name>
+                        <description>RXD sample delay (in SCLK cycles)</description>
+                        <bitRange>[7:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SPI_CTRLR0</name>
+                <addressOffset>0x000000f4</addressOffset>
+                <description>SPI control</description>
+                <resetValue>0x03000000</resetValue>
+                <fields>
+                    <field>
+                        <name>XIP_CMD</name>
+                        <description>SPI Command to send in XIP mode (INST_L = 8-bit) or to append to Address (INST_L = 0-bit)</description>
+                        <bitRange>[31:24]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SPI_RXDS_EN</name>
+                        <description>Read data strobe enable</description>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INST_DDR_EN</name>
+                        <description>Instruction DDR transfer enable</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SPI_DDR_EN</name>
+                        <description>SPI DDR transfer enable</description>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>WAIT_CYCLES</name>
+                        <description>Wait cycles between control frame transmit and data reception (in SCLK cycles)</description>
+                        <bitRange>[15:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INST_L</name>
+                        <description>Instruction length (0/4/8/16b)</description>
+                        <bitRange>[9:8]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NONE</name>
+                                <value>0</value>
+                                <description>No instruction</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>4B</name>
+                                <value>1</value>
+                                <description>4-bit instruction</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>8B</name>
+                                <value>2</value>
+                                <description>8-bit instruction</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>16B</name>
+                                <value>3</value>
+                                <description>16-bit instruction</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>ADDR_L</name>
+                        <description>Address length (0b-60b in 4b increments)</description>
+                        <bitRange>[5:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>TRANS_TYPE</name>
+                        <description>Address and instruction transfer format</description>
+                        <bitRange>[1:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>1C1A</name>
+                                <value>0</value>
+                                <description>Command and address both in standard SPI frame format</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>1C2A</name>
+                                <value>1</value>
+                                <description>Command in standard SPI format, address in format specified by FRF</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>2C2A</name>
+                                <value>2</value>
+                                <description>Command and address both in format specified by FRF (e.g. Dual-SPI)</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>TXD_DRIVE_EDGE</name>
+                <addressOffset>0x000000f8</addressOffset>
+                <description>TX drive edge</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>TDE</name>
+                        <description>TXD drive edge</description>
+                        <bitRange>[7:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+        </registers>
+    </peripheral>
+    <peripheral>
+        <name>XIP_CTRL</name>
+        <description>QSPI flash execute-in-place block</description>
+        <baseAddress>0x14000000</baseAddress>
+        <addressBlock>
+            <offset>0</offset>
+            <size>32</size>
+            <usage>registers</usage>
+        </addressBlock>
+        <interrupt>
+            <name>XIP_IRQ</name>
+            <value>6</value>
+        </interrupt>
+        <registers>
+            <register>
+                <name>CTRL</name>
+                <addressOffset>0x00000000</addressOffset>
+                <description>Cache control</description>
+                <resetValue>0x00000003</resetValue>
+                <fields>
+                    <field>
+                        <name>POWER_DOWN</name>
+                        <description>When 1, the cache memories are powered down. They retain state, 
+                            but can not be accessed. This reduces static power dissipation. 
+                            Writing 1 to this bit forces CTRL_EN to 0, i.e. the cache cannot 
+                            be enabled when powered down. 
+                            Cache-as-SRAM accesses will produce a bus error response when 
+                            the cache is powered down.</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ERR_BADWRITE</name>
+                        <description>When 1, writes to any alias other than 0x0 (caching, allocating) 
+                            will produce a bus fault. When 0, these writes are silently ignored. 
+                            In either case, writes to the 0x0 alias will deallocate on tag match, 
+                            as usual.</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>EN</name>
+                        <description>When 1, enable the cache. When the cache is disabled, all XIP accesses 
+                            will go straight to the flash, without querying the cache. When enabled, 
+                            cacheable XIP accesses will query the cache, and the flash will 
+                            not be accessed if the tag matches and the valid bit is set.
+
+                            If the cache is enabled, cache-as-SRAM accesses have no effect on the 
+                            cache data RAM, and will produce a bus error response.</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>FLUSH</name>
+                <addressOffset>0x00000004</addressOffset>
+                <description>Cache Flush control</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>FLUSH</name>
+                        <description>Write 1 to flush the cache. This clears the tag memory, but 
+                            the data memory retains its contents. (This means cache-as-SRAM 
+                            contents is not affected by flush or reset.) 
+                            Reading will hold the bus (stall the processor) until the flush 
+                            completes. Alternatively STAT can be polled until completion.</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>STAT</name>
+                <addressOffset>0x00000008</addressOffset>
+                <description>Cache Status</description>
+                <resetValue>0x00000002</resetValue>
+                <fields>
+                    <field>
+                        <name>FIFO_FULL</name>
+                        <description>When 1, indicates the XIP streaming FIFO is completely full. 
+                            The streaming FIFO is 2 entries deep, so the full and empty 
+                            flag allow its level to be ascertained.</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>FIFO_EMPTY</name>
+                        <description>When 1, indicates the XIP streaming FIFO is completely empty.</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>FLUSH_READY</name>
+                        <description>Reads as 0 while a cache flush is in progress, and 1 otherwise. 
+                            The cache is flushed whenever the XIP block is reset, and also 
+                            when requested via the FLUSH register.</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CTR_HIT</name>
+                <addressOffset>0x0000000c</addressOffset>
+                <description>Cache Hit counter</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CTR_HIT</name>
+                        <description>A 32 bit saturating counter that increments upon each cache hit, 
+                            i.e. when an XIP access is serviced directly from cached data. 
+                            Write any value to clear.</description>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CTR_ACC</name>
+                <addressOffset>0x00000010</addressOffset>
+                <description>Cache Access counter</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CTR_ACC</name>
+                        <description>A 32 bit saturating counter that increments upon each XIP access, 
+                            whether the cache is hit or not. This includes noncacheable accesses. 
+                            Write any value to clear.</description>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>STREAM_ADDR</name>
+                <addressOffset>0x00000014</addressOffset>
+                <description>FIFO stream address</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>STREAM_ADDR</name>
+                        <description>The address of the next word to be streamed from flash to the streaming FIFO. 
+                            Increments automatically after each flash access. 
+                            Write the initial access address here before starting a streaming read.</description>
+                        <bitRange>[31:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>STREAM_CTR</name>
+                <addressOffset>0x00000018</addressOffset>
+                <description>FIFO stream control</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>STREAM_CTR</name>
+                        <description>Write a nonzero value to start a streaming read. This will then 
+                            progress in the background, using flash idle cycles to transfer 
+                            a linear data block from flash to the streaming FIFO. 
+                            Decrements automatically (1 at a time) as the stream 
+                            progresses, and halts on reaching 0. 
+                            Write 0 to halt an in-progress stream, and discard any in-flight 
+                            read, so that a new stream can immediately be started (after 
+                            draining the FIFO and reinitialising STREAM_ADDR)</description>
+                        <bitRange>[21:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>STREAM_FIFO</name>
+                <addressOffset>0x0000001c</addressOffset>
+                <description>FIFO stream data</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>STREAM_FIFO</name>
+                        <description>Streamed data is buffered here, for retrieval by the system DMA. 
+                            This FIFO can also be accessed via the XIP_AUX slave, to avoid exposing 
+                            the DMA to bus stalls caused by other XIP traffic.</description>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-only</access>
+                        <readAction>modify</readAction>
+                    </field>
+                </fields>
+            </register>
+        </registers>
+    </peripheral>
+    <peripheral>
+        <name>SYSCFG</name>
+        <description>Register block for various chip control signals</description>
+        <baseAddress>0x40004000</baseAddress>
+        <addressBlock>
+            <offset>0</offset>
+            <size>28</size>
+            <usage>registers</usage>
+        </addressBlock>
+        <registers>
+            <register>
+                <name>PROC0_NMI_MASK</name>
+                <addressOffset>0x00000000</addressOffset>
+                <description>Processor core 0 NMI source mask</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>PROC0_NMI_MASK</name>
+                        <description>Set a bit high to enable NMI from that IRQ</description>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PROC1_NMI_MASK</name>
+                <addressOffset>0x00000004</addressOffset>
+                <description>Processor core 1 NMI source mask</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>PROC1_NMI_MASK</name>
+                        <description>Set a bit high to enable NMI from that IRQ</description>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PROC_CONFIG</name>
+                <addressOffset>0x00000008</addressOffset>
+                <description>Configuration for processors</description>
+                <resetValue>0x10000000</resetValue>
+                <fields>
+                    <field>
+                        <name>PROC1_DAP_INSTID</name>
+                        <description>Configure proc1 DAP instance ID. 
+                            Recommend that this is NOT changed until you require debug access in multi-chip environment 
+                            WARNING: do not set to 15 as this is reserved for RescueDP</description>
+                        <bitRange>[31:28]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PROC0_DAP_INSTID</name>
+                        <description>Configure proc0 DAP instance ID. 
+                            Recommend that this is NOT changed until you require debug access in multi-chip environment 
+                            WARNING: do not set to 15 as this is reserved for RescueDP</description>
+                        <bitRange>[27:24]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PROC1_HALTED</name>
+                        <description>Indication that proc1 has halted</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>PROC0_HALTED</name>
+                        <description>Indication that proc0 has halted</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PROC_IN_SYNC_BYPASS</name>
+                <addressOffset>0x0000000c</addressOffset>
+                <description>For each bit, if 1, bypass the input synchronizer between that GPIO 
+                    and the GPIO input register in the SIO. The input synchronizers should 
+                    generally be unbypassed, to avoid injecting metastabilities into processors. 
+                    If you&#39;re feeling brave, you can bypass to save two cycles of input 
+                    latency. This register applies to GPIO 0...29.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>PROC_IN_SYNC_BYPASS</name>
+                        <bitRange>[29:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PROC_IN_SYNC_BYPASS_HI</name>
+                <addressOffset>0x00000010</addressOffset>
+                <description>For each bit, if 1, bypass the input synchronizer between that GPIO 
+                    and the GPIO input register in the SIO. The input synchronizers should 
+                    generally be unbypassed, to avoid injecting metastabilities into processors. 
+                    If you&#39;re feeling brave, you can bypass to save two cycles of input 
+                    latency. This register applies to GPIO 30...35 (the QSPI IOs).</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>PROC_IN_SYNC_BYPASS_HI</name>
+                        <bitRange>[5:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>DBGFORCE</name>
+                <addressOffset>0x00000014</addressOffset>
+                <description>Directly control the SWD debug port of either processor</description>
+                <resetValue>0x00000066</resetValue>
+                <fields>
+                    <field>
+                        <name>PROC1_ATTACH</name>
+                        <description>Attach processor 1 debug port to syscfg controls, and disconnect it from external SWD pads.</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PROC1_SWCLK</name>
+                        <description>Directly drive processor 1 SWCLK, if PROC1_ATTACH is set</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PROC1_SWDI</name>
+                        <description>Directly drive processor 1 SWDIO input, if PROC1_ATTACH is set</description>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PROC1_SWDO</name>
+                        <description>Observe the value of processor 1 SWDIO output.</description>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>PROC0_ATTACH</name>
+                        <description>Attach processor 0 debug port to syscfg controls, and disconnect it from external SWD pads.</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PROC0_SWCLK</name>
+                        <description>Directly drive processor 0 SWCLK, if PROC0_ATTACH is set</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PROC0_SWDI</name>
+                        <description>Directly drive processor 0 SWDIO input, if PROC0_ATTACH is set</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PROC0_SWDO</name>
+                        <description>Observe the value of processor 0 SWDIO output.</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>MEMPOWERDOWN</name>
+                <addressOffset>0x00000018</addressOffset>
+                <description>Control power downs to memories. Set high to power down memories. 
+                    Use with extreme caution</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>ROM</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>USB</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SRAM5</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SRAM4</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SRAM3</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SRAM2</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SRAM1</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SRAM0</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+        </registers>
+    </peripheral>
+    <peripheral>
+        <name>XOSC</name>
+        <description>Controls the crystal oscillator</description>
+        <baseAddress>0x40024000</baseAddress>
+        <addressBlock>
+            <offset>0</offset>
+            <size>32</size>
+            <usage>registers</usage>
+        </addressBlock>
+        <registers>
+            <register>
+                <name>CTRL</name>
+                <addressOffset>0x00000000</addressOffset>
+                <description>Crystal Oscillator Control</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>ENABLE</name>
+                        <description>On power-up this field is initialised to DISABLE and the chip runs from the ROSC. 
+                            If the chip has subsequently been programmed to run from the XOSC then DISABLE may lock-up the chip. If this is a concern then run the clk_ref from the ROSC and enable the clk_sys RESUS feature. 
+                            The 12-bit code is intended to give some protection against accidental writes. An invalid setting will enable the oscillator.</description>
+                        <bitRange>[23:12]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>DISABLE</name>
+                                <value>3358</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ENABLE</name>
+                                <value>4011</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>FREQ_RANGE</name>
+                        <description>Frequency range. An invalid setting will retain the previous value. The actual value being used can be read from STATUS_FREQ_RANGE. This resets to 0xAA0 and cannot be changed.</description>
+                        <bitRange>[11:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>1_15MHZ</name>
+                                <value>2720</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>RESERVED_1</name>
+                                <value>2721</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>RESERVED_2</name>
+                                <value>2722</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>RESERVED_3</name>
+                                <value>2723</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>STATUS</name>
+                <addressOffset>0x00000004</addressOffset>
+                <description>Crystal Oscillator Status</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>STABLE</name>
+                        <description>Oscillator is running and stable</description>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>BADWRITE</name>
+                        <description>An invalid value has been written to CTRL_ENABLE or CTRL_FREQ_RANGE or DORMANT</description>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>ENABLED</name>
+                        <description>Oscillator is enabled but not necessarily running and stable, resets to 0</description>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>FREQ_RANGE</name>
+                        <description>The current frequency range setting, always reads 0</description>
+                        <bitRange>[1:0]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>1_15MHZ</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>RESERVED_1</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>RESERVED_2</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>RESERVED_3</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>DORMANT</name>
+                <addressOffset>0x00000008</addressOffset>
+                <description>Crystal Oscillator pause control</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>DORMANT</name>
+                        <description>This is used to save power by pausing the XOSC 
+                            On power-up this field is initialised to WAKE 
+                            An invalid write will also select WAKE 
+                            Warning: stop the PLLs before selecting dormant mode 
+                            Warning: setup the irq before selecting dormant mode</description>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>dormant</name>
+                                <value>1668246881</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>WAKE</name>
+                                <value>2002873189</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>STARTUP</name>
+                <addressOffset>0x0000000c</addressOffset>
+                <description>Controls the startup delay</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>X4</name>
+                        <description>Multiplies the startup_delay by 4. This is of little value to the user given that the delay can be programmed directly.</description>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DELAY</name>
+                        <description>in multiples of 256*xtal_period. The reset value of 0xc4 corresponds to approx 50 000 cycles.</description>
+                        <bitRange>[13:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>COUNT</name>
+                <addressOffset>0x0000001c</addressOffset>
+                <description>A down counter running at the xosc frequency which counts to zero and stops. 
+                    To start the counter write a non-zero value. 
+                    Can be used for short software pauses when setting up time sensitive hardware.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>COUNT</name>
+                        <bitRange>[7:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+        </registers>
+    </peripheral>
+    <peripheral>
+        <name>PLL_SYS</name>
+        <baseAddress>0x40028000</baseAddress>
+        <addressBlock>
+            <offset>0</offset>
+            <size>16</size>
+            <usage>registers</usage>
+        </addressBlock>
+        <registers>
+            <register>
+                <name>CS</name>
+                <addressOffset>0x00000000</addressOffset>
+                <description>Control and Status 
+                    GENERAL CONSTRAINTS: 
+                    Reference clock frequency min=5MHz, max=800MHz 
+                    Feedback divider min=16, max=320 
+                    VCO frequency min=750MHz, max=1600MHz</description>
+                <resetValue>0x00000001</resetValue>
+                <fields>
+                    <field>
+                        <name>LOCK</name>
+                        <description>PLL is locked</description>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>BYPASS</name>
+                        <description>Passes the reference clock to the output instead of the divided VCO. The VCO continues to run so the user can switch between the reference clock and the divided VCO but the output will glitch when doing so.</description>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>REFDIV</name>
+                        <description>Divides the PLL input reference clock. 
+                            Behaviour is undefined for div=0. 
+                            PLL output will be unpredictable during refdiv changes, wait for lock=1 before using it.</description>
+                        <bitRange>[5:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PWR</name>
+                <addressOffset>0x00000004</addressOffset>
+                <description>Controls the PLL power modes.</description>
+                <resetValue>0x0000002d</resetValue>
+                <fields>
+                    <field>
+                        <name>VCOPD</name>
+                        <description>PLL VCO powerdown 
+                            To save power set high when PLL output not required or bypass=1.</description>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>POSTDIVPD</name>
+                        <description>PLL post divider powerdown 
+                            To save power set high when PLL output not required or bypass=1.</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DSMPD</name>
+                        <description>PLL DSM powerdown 
+                            Nothing is achieved by setting this low.</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PD</name>
+                        <description>PLL powerdown 
+                            To save power set high when PLL output not required.</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>FBDIV_INT</name>
+                <addressOffset>0x00000008</addressOffset>
+                <description>Feedback divisor 
+                    (note: this PLL does not support fractional division)</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>FBDIV_INT</name>
+                        <description>see ctrl reg description for constraints</description>
+                        <bitRange>[11:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PRIM</name>
+                <addressOffset>0x0000000c</addressOffset>
+                <description>Controls the PLL post dividers for the primary output 
+                    (note: this PLL does not have a secondary output) 
+                    the primary output is driven from VCO divided by postdiv1*postdiv2</description>
+                <resetValue>0x00077000</resetValue>
+                <fields>
+                    <field>
+                        <name>POSTDIV1</name>
+                        <description>divide by 1-7</description>
+                        <bitRange>[18:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>POSTDIV2</name>
+                        <description>divide by 1-7</description>
+                        <bitRange>[14:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+        </registers>
+    </peripheral>
+    <peripheral derivedFrom="PLL_SYS">
+        <name>PLL_USB</name>
+        <baseAddress>0x4002c000</baseAddress>
+    </peripheral>
+    <peripheral>
+        <name>UART0</name>
+        <baseAddress>0x40034000</baseAddress>
+        <addressBlock>
+            <offset>0</offset>
+            <size>4096</size>
+            <usage>registers</usage>
+        </addressBlock>
+        <interrupt>
+            <name>UART0_IRQ</name>
+            <value>20</value>
+        </interrupt>
+        <registers>
+            <register>
+                <name>UARTDR</name>
+                <addressOffset>0x00000000</addressOffset>
+                <description>Data Register, UARTDR</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>OE</name>
+                        <description>Overrun error. This bit is set to 1 if data is received and the receive FIFO is already full. This is cleared to 0 once there is an empty space in the FIFO and a new character can be written to it.</description>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>BE</name>
+                        <description>Break error. This bit is set to 1 if a break condition was detected, indicating that the received data input was held LOW for longer than a full-word transmission time (defined as start, data, parity and stop bits). In FIFO mode, this error is associated with the character at the top of the FIFO. When a break occurs, only one 0 character is loaded into the FIFO. The next character is only enabled after the receive data input goes to a 1 (marking state), and the next valid start bit is received.</description>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>PE</name>
+                        <description>Parity error. When set to 1, it indicates that the parity of the received data character does not match the parity that the EPS and SPS bits in the Line Control Register, UARTLCR_H. In FIFO mode, this error is associated with the character at the top of the FIFO.</description>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>FE</name>
+                        <description>Framing error. When set to 1, it indicates that the received character did not have a valid stop bit (a valid stop bit is 1). In FIFO mode, this error is associated with the character at the top of the FIFO.</description>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>DATA</name>
+                        <description>Receive (read) data character. Transmit (write) data character.</description>
+                        <bitRange>[7:0]</bitRange>
+                        <access>read-write</access>
+                        <readAction>modify</readAction>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>UARTRSR</name>
+                <addressOffset>0x00000004</addressOffset>
+                <description>Receive Status Register/Error Clear Register, UARTRSR/UARTECR</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>OE</name>
+                        <description>Overrun error. This bit is set to 1 if data is received and the FIFO is already full. This bit is cleared to 0 by a write to UARTECR. The FIFO contents remain valid because no more data is written when the FIFO is full, only the contents of the shift register are overwritten. The CPU must now read the data, to empty the FIFO.</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>BE</name>
+                        <description>Break error. This bit is set to 1 if a break condition was detected, indicating that the received data input was held LOW for longer than a full-word transmission time (defined as start, data, parity, and stop bits). This bit is cleared to 0 after a write to UARTECR. In FIFO mode, this error is associated with the character at the top of the FIFO. When a break occurs, only one 0 character is loaded into the FIFO. The next character is only enabled after the receive data input goes to a 1 (marking state) and the next valid start bit is received.</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>PE</name>
+                        <description>Parity error. When set to 1, it indicates that the parity of the received data character does not match the parity that the EPS and SPS bits in the Line Control Register, UARTLCR_H. This bit is cleared to 0 by a write to UARTECR. In FIFO mode, this error is associated with the character at the top of the FIFO.</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>FE</name>
+                        <description>Framing error. When set to 1, it indicates that the received character did not have a valid stop bit (a valid stop bit is 1). This bit is cleared to 0 by a write to UARTECR. In FIFO mode, this error is associated with the character at the top of the FIFO.</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>UARTFR</name>
+                <addressOffset>0x00000018</addressOffset>
+                <description>Flag Register, UARTFR</description>
+                <resetValue>0x00000090</resetValue>
+                <fields>
+                    <field>
+                        <name>RI</name>
+                        <description>Ring indicator. This bit is the complement of the UART ring indicator, nUARTRI, modem status input. That is, the bit is 1 when nUARTRI is LOW.</description>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>TXFE</name>
+                        <description>Transmit FIFO empty. The meaning of this bit depends on the state of the FEN bit in the Line Control Register, UARTLCR_H. If the FIFO is disabled, this bit is set when the transmit holding register is empty. If the FIFO is enabled, the TXFE bit is set when the transmit FIFO is empty. This bit does not indicate if there is data in the transmit shift register.</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>RXFF</name>
+                        <description>Receive FIFO full. The meaning of this bit depends on the state of the FEN bit in the UARTLCR_H Register. If the FIFO is disabled, this bit is set when the receive holding register is full. If the FIFO is enabled, the RXFF bit is set when the receive FIFO is full.</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>TXFF</name>
+                        <description>Transmit FIFO full. The meaning of this bit depends on the state of the FEN bit in the UARTLCR_H Register. If the FIFO is disabled, this bit is set when the transmit holding register is full. If the FIFO is enabled, the TXFF bit is set when the transmit FIFO is full.</description>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>RXFE</name>
+                        <description>Receive FIFO empty. The meaning of this bit depends on the state of the FEN bit in the UARTLCR_H Register. If the FIFO is disabled, this bit is set when the receive holding register is empty. If the FIFO is enabled, the RXFE bit is set when the receive FIFO is empty.</description>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>BUSY</name>
+                        <description>UART busy. If this bit is set to 1, the UART is busy transmitting data. This bit remains set until the complete byte, including all the stop bits, has been sent from the shift register. This bit is set as soon as the transmit FIFO becomes non-empty, regardless of whether the UART is enabled or not.</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>DCD</name>
+                        <description>Data carrier detect. This bit is the complement of the UART data carrier detect, nUARTDCD, modem status input. That is, the bit is 1 when nUARTDCD is LOW.</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>DSR</name>
+                        <description>Data set ready. This bit is the complement of the UART data set ready, nUARTDSR, modem status input. That is, the bit is 1 when nUARTDSR is LOW.</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CTS</name>
+                        <description>Clear to send. This bit is the complement of the UART clear to send, nUARTCTS, modem status input. That is, the bit is 1 when nUARTCTS is LOW.</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>UARTILPR</name>
+                <addressOffset>0x00000020</addressOffset>
+                <description>IrDA Low-Power Counter Register, UARTILPR</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>ILPDVSR</name>
+                        <description>8-bit low-power divisor value. These bits are cleared to 0 at reset.</description>
+                        <bitRange>[7:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>UARTIBRD</name>
+                <addressOffset>0x00000024</addressOffset>
+                <description>Integer Baud Rate Register, UARTIBRD</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>BAUD_DIVINT</name>
+                        <description>The integer baud rate divisor. These bits are cleared to 0 on reset.</description>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>UARTFBRD</name>
+                <addressOffset>0x00000028</addressOffset>
+                <description>Fractional Baud Rate Register, UARTFBRD</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>BAUD_DIVFRAC</name>
+                        <description>The fractional baud rate divisor. These bits are cleared to 0 on reset.</description>
+                        <bitRange>[5:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>UARTLCR_H</name>
+                <addressOffset>0x0000002c</addressOffset>
+                <description>Line Control Register, UARTLCR_H</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>SPS</name>
+                        <description>Stick parity select. 0 = stick parity is disabled 1 = either: * if the EPS bit is 0 then the parity bit is transmitted and checked as a 1 * if the EPS bit is 1 then the parity bit is transmitted and checked as a 0. This bit has no effect when the PEN bit disables parity checking and generation.</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>WLEN</name>
+                        <description>Word length. These bits indicate the number of data bits transmitted or received in a frame as follows: b11 = 8 bits b10 = 7 bits b01 = 6 bits b00 = 5 bits.</description>
+                        <bitRange>[6:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>FEN</name>
+                        <description>Enable FIFOs: 0 = FIFOs are disabled (character mode) that is, the FIFOs become 1-byte-deep holding registers 1 = transmit and receive FIFO buffers are enabled (FIFO mode).</description>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>STP2</name>
+                        <description>Two stop bits select. If this bit is set to 1, two stop bits are transmitted at the end of the frame. The receive logic does not check for two stop bits being received.</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>EPS</name>
+                        <description>Even parity select. Controls the type of parity the UART uses during transmission and reception: 0 = odd parity. The UART generates or checks for an odd number of 1s in the data and parity bits. 1 = even parity. The UART generates or checks for an even number of 1s in the data and parity bits. This bit has no effect when the PEN bit disables parity checking and generation.</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PEN</name>
+                        <description>Parity enable: 0 = parity is disabled and no parity bit added to the data frame 1 = parity checking and generation is enabled.</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>BRK</name>
+                        <description>Send break. If this bit is set to 1, a low-level is continually output on the UARTTXD output, after completing transmission of the current character. For the proper execution of the break command, the software must set this bit for at least two complete frames. For normal use, this bit must be cleared to 0.</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>UARTCR</name>
+                <addressOffset>0x00000030</addressOffset>
+                <description>Control Register, UARTCR</description>
+                <resetValue>0x00000300</resetValue>
+                <fields>
+                    <field>
+                        <name>CTSEN</name>
+                        <description>CTS hardware flow control enable. If this bit is set to 1, CTS hardware flow control is enabled. Data is only transmitted when the nUARTCTS signal is asserted.</description>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>RTSEN</name>
+                        <description>RTS hardware flow control enable. If this bit is set to 1, RTS hardware flow control is enabled. Data is only requested when there is space in the receive FIFO for it to be received.</description>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>OUT2</name>
+                        <description>This bit is the complement of the UART Out2 (nUARTOut2) modem status output. That is, when the bit is programmed to a 1, the output is 0. For DTE this can be used as Ring Indicator (RI).</description>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>OUT1</name>
+                        <description>This bit is the complement of the UART Out1 (nUARTOut1) modem status output. That is, when the bit is programmed to a 1 the output is 0. For DTE this can be used as Data Carrier Detect (DCD).</description>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>RTS</name>
+                        <description>Request to send. This bit is the complement of the UART request to send, nUARTRTS, modem status output. That is, when the bit is programmed to a 1 then nUARTRTS is LOW.</description>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DTR</name>
+                        <description>Data transmit ready. This bit is the complement of the UART data transmit ready, nUARTDTR, modem status output. That is, when the bit is programmed to a 1 then nUARTDTR is LOW.</description>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>RXE</name>
+                        <description>Receive enable. If this bit is set to 1, the receive section of the UART is enabled. Data reception occurs for either UART signals or SIR signals depending on the setting of the SIREN bit. When the UART is disabled in the middle of reception, it completes the current character before stopping.</description>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>TXE</name>
+                        <description>Transmit enable. If this bit is set to 1, the transmit section of the UART is enabled. Data transmission occurs for either UART signals, or SIR signals depending on the setting of the SIREN bit. When the UART is disabled in the middle of transmission, it completes the current character before stopping.</description>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LBE</name>
+                        <description>Loopback enable. If this bit is set to 1 and the SIREN bit is set to 1 and the SIRTEST bit in the Test Control Register, UARTTCR is set to 1, then the nSIROUT path is inverted, and fed through to the SIRIN path. The SIRTEST bit in the test register must be set to 1 to override the normal half-duplex SIR operation. This must be the requirement for accessing the test registers during normal operation, and SIRTEST must be cleared to 0 when loopback testing is finished. This feature reduces the amount of external coupling required during system test. If this bit is set to 1, and the SIRTEST bit is set to 0, the UARTTXD path is fed through to the UARTRXD path. In either SIR mode or UART mode, when this bit is set, the modem outputs are also fed through to the modem inputs. This bit is cleared to 0 on reset, to disable loopback.</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SIRLP</name>
+                        <description>SIR low-power IrDA mode. This bit selects the IrDA encoding mode. If this bit is cleared to 0, low-level bits are transmitted as an active high pulse with a width of 3 / 16th of the bit period. If this bit is set to 1, low-level bits are transmitted with a pulse width that is 3 times the period of the IrLPBaud16 input signal, regardless of the selected bit rate. Setting this bit uses less power, but might reduce transmission distances.</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SIREN</name>
+                        <description>SIR enable: 0 = IrDA SIR ENDEC is disabled. nSIROUT remains LOW (no light pulse generated), and signal transitions on SIRIN have no effect. 1 = IrDA SIR ENDEC is enabled. Data is transmitted and received on nSIROUT and SIRIN. UARTTXD remains HIGH, in the marking state. Signal transitions on UARTRXD or modem status inputs have no effect. This bit has no effect if the UARTEN bit disables the UART.</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>UARTEN</name>
+                        <description>UART enable: 0 = UART is disabled. If the UART is disabled in the middle of transmission or reception, it completes the current character before stopping. 1 = the UART is enabled. Data transmission and reception occurs for either UART signals or SIR signals depending on the setting of the SIREN bit.</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>UARTIFLS</name>
+                <addressOffset>0x00000034</addressOffset>
+                <description>Interrupt FIFO Level Select Register, UARTIFLS</description>
+                <resetValue>0x00000012</resetValue>
+                <fields>
+                    <field>
+                        <name>RXIFLSEL</name>
+                        <description>Receive interrupt FIFO level select. The trigger points for the receive interrupt are as follows: b000 = Receive FIFO becomes &gt;= 1 / 8 full b001 = Receive FIFO becomes &gt;= 1 / 4 full b010 = Receive FIFO becomes &gt;= 1 / 2 full b011 = Receive FIFO becomes &gt;= 3 / 4 full b100 = Receive FIFO becomes &gt;= 7 / 8 full b101-b111 = reserved.</description>
+                        <bitRange>[5:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>TXIFLSEL</name>
+                        <description>Transmit interrupt FIFO level select. The trigger points for the transmit interrupt are as follows: b000 = Transmit FIFO becomes &lt;= 1 / 8 full b001 = Transmit FIFO becomes &lt;= 1 / 4 full b010 = Transmit FIFO becomes &lt;= 1 / 2 full b011 = Transmit FIFO becomes &lt;= 3 / 4 full b100 = Transmit FIFO becomes &lt;= 7 / 8 full b101-b111 = reserved.</description>
+                        <bitRange>[2:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>UARTIMSC</name>
+                <addressOffset>0x00000038</addressOffset>
+                <description>Interrupt Mask Set/Clear Register, UARTIMSC</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>OEIM</name>
+                        <description>Overrun error interrupt mask. A read returns the current mask for the UARTOEINTR interrupt. On a write of 1, the mask of the UARTOEINTR interrupt is set. A write of 0 clears the mask.</description>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>BEIM</name>
+                        <description>Break error interrupt mask. A read returns the current mask for the UARTBEINTR interrupt. On a write of 1, the mask of the UARTBEINTR interrupt is set. A write of 0 clears the mask.</description>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PEIM</name>
+                        <description>Parity error interrupt mask. A read returns the current mask for the UARTPEINTR interrupt. On a write of 1, the mask of the UARTPEINTR interrupt is set. A write of 0 clears the mask.</description>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>FEIM</name>
+                        <description>Framing error interrupt mask. A read returns the current mask for the UARTFEINTR interrupt. On a write of 1, the mask of the UARTFEINTR interrupt is set. A write of 0 clears the mask.</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>RTIM</name>
+                        <description>Receive timeout interrupt mask. A read returns the current mask for the UARTRTINTR interrupt. On a write of 1, the mask of the UARTRTINTR interrupt is set. A write of 0 clears the mask.</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>TXIM</name>
+                        <description>Transmit interrupt mask. A read returns the current mask for the UARTTXINTR interrupt. On a write of 1, the mask of the UARTTXINTR interrupt is set. A write of 0 clears the mask.</description>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>RXIM</name>
+                        <description>Receive interrupt mask. A read returns the current mask for the UARTRXINTR interrupt. On a write of 1, the mask of the UARTRXINTR interrupt is set. A write of 0 clears the mask.</description>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DSRMIM</name>
+                        <description>nUARTDSR modem interrupt mask. A read returns the current mask for the UARTDSRINTR interrupt. On a write of 1, the mask of the UARTDSRINTR interrupt is set. A write of 0 clears the mask.</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DCDMIM</name>
+                        <description>nUARTDCD modem interrupt mask. A read returns the current mask for the UARTDCDINTR interrupt. On a write of 1, the mask of the UARTDCDINTR interrupt is set. A write of 0 clears the mask.</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CTSMIM</name>
+                        <description>nUARTCTS modem interrupt mask. A read returns the current mask for the UARTCTSINTR interrupt. On a write of 1, the mask of the UARTCTSINTR interrupt is set. A write of 0 clears the mask.</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>RIMIM</name>
+                        <description>nUARTRI modem interrupt mask. A read returns the current mask for the UARTRIINTR interrupt. On a write of 1, the mask of the UARTRIINTR interrupt is set. A write of 0 clears the mask.</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>UARTRIS</name>
+                <addressOffset>0x0000003c</addressOffset>
+                <description>Raw Interrupt Status Register, UARTRIS</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>OERIS</name>
+                        <description>Overrun error interrupt status. Returns the raw interrupt state of the UARTOEINTR interrupt.</description>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>BERIS</name>
+                        <description>Break error interrupt status. Returns the raw interrupt state of the UARTBEINTR interrupt.</description>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>PERIS</name>
+                        <description>Parity error interrupt status. Returns the raw interrupt state of the UARTPEINTR interrupt.</description>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>FERIS</name>
+                        <description>Framing error interrupt status. Returns the raw interrupt state of the UARTFEINTR interrupt.</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>RTRIS</name>
+                        <description>Receive timeout interrupt status. Returns the raw interrupt state of the UARTRTINTR interrupt. a</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>TXRIS</name>
+                        <description>Transmit interrupt status. Returns the raw interrupt state of the UARTTXINTR interrupt.</description>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>RXRIS</name>
+                        <description>Receive interrupt status. Returns the raw interrupt state of the UARTRXINTR interrupt.</description>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>DSRRMIS</name>
+                        <description>nUARTDSR modem interrupt status. Returns the raw interrupt state of the UARTDSRINTR interrupt.</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>DCDRMIS</name>
+                        <description>nUARTDCD modem interrupt status. Returns the raw interrupt state of the UARTDCDINTR interrupt.</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CTSRMIS</name>
+                        <description>nUARTCTS modem interrupt status. Returns the raw interrupt state of the UARTCTSINTR interrupt.</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>RIRMIS</name>
+                        <description>nUARTRI modem interrupt status. Returns the raw interrupt state of the UARTRIINTR interrupt.</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>UARTMIS</name>
+                <addressOffset>0x00000040</addressOffset>
+                <description>Masked Interrupt Status Register, UARTMIS</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>OEMIS</name>
+                        <description>Overrun error masked interrupt status. Returns the masked interrupt state of the UARTOEINTR interrupt.</description>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>BEMIS</name>
+                        <description>Break error masked interrupt status. Returns the masked interrupt state of the UARTBEINTR interrupt.</description>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>PEMIS</name>
+                        <description>Parity error masked interrupt status. Returns the masked interrupt state of the UARTPEINTR interrupt.</description>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>FEMIS</name>
+                        <description>Framing error masked interrupt status. Returns the masked interrupt state of the UARTFEINTR interrupt.</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>RTMIS</name>
+                        <description>Receive timeout masked interrupt status. Returns the masked interrupt state of the UARTRTINTR interrupt.</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>TXMIS</name>
+                        <description>Transmit masked interrupt status. Returns the masked interrupt state of the UARTTXINTR interrupt.</description>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>RXMIS</name>
+                        <description>Receive masked interrupt status. Returns the masked interrupt state of the UARTRXINTR interrupt.</description>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>DSRMMIS</name>
+                        <description>nUARTDSR modem masked interrupt status. Returns the masked interrupt state of the UARTDSRINTR interrupt.</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>DCDMMIS</name>
+                        <description>nUARTDCD modem masked interrupt status. Returns the masked interrupt state of the UARTDCDINTR interrupt.</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CTSMMIS</name>
+                        <description>nUARTCTS modem masked interrupt status. Returns the masked interrupt state of the UARTCTSINTR interrupt.</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>RIMMIS</name>
+                        <description>nUARTRI modem masked interrupt status. Returns the masked interrupt state of the UARTRIINTR interrupt.</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>UARTICR</name>
+                <addressOffset>0x00000044</addressOffset>
+                <description>Interrupt Clear Register, UARTICR</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>OEIC</name>
+                        <description>Overrun error interrupt clear. Clears the UARTOEINTR interrupt.</description>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>BEIC</name>
+                        <description>Break error interrupt clear. Clears the UARTBEINTR interrupt.</description>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>PEIC</name>
+                        <description>Parity error interrupt clear. Clears the UARTPEINTR interrupt.</description>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>FEIC</name>
+                        <description>Framing error interrupt clear. Clears the UARTFEINTR interrupt.</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>RTIC</name>
+                        <description>Receive timeout interrupt clear. Clears the UARTRTINTR interrupt.</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>TXIC</name>
+                        <description>Transmit interrupt clear. Clears the UARTTXINTR interrupt.</description>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>RXIC</name>
+                        <description>Receive interrupt clear. Clears the UARTRXINTR interrupt.</description>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>DSRMIC</name>
+                        <description>nUARTDSR modem interrupt clear. Clears the UARTDSRINTR interrupt.</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>DCDMIC</name>
+                        <description>nUARTDCD modem interrupt clear. Clears the UARTDCDINTR interrupt.</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>CTSMIC</name>
+                        <description>nUARTCTS modem interrupt clear. Clears the UARTCTSINTR interrupt.</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>RIMIC</name>
+                        <description>nUARTRI modem interrupt clear. Clears the UARTRIINTR interrupt.</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>UARTDMACR</name>
+                <addressOffset>0x00000048</addressOffset>
+                <description>DMA Control Register, UARTDMACR</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>DMAONERR</name>
+                        <description>DMA on error. If this bit is set to 1, the DMA receive request outputs, UARTRXDMASREQ or UARTRXDMABREQ, are disabled when the UART error interrupt is asserted.</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>TXDMAE</name>
+                        <description>Transmit DMA enable. If this bit is set to 1, DMA for the transmit FIFO is enabled.</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>RXDMAE</name>
+                        <description>Receive DMA enable. If this bit is set to 1, DMA for the receive FIFO is enabled.</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>UARTPERIPHID0</name>
+                <addressOffset>0x00000fe0</addressOffset>
+                <description>UARTPeriphID0 Register</description>
+                <resetValue>0x00000011</resetValue>
+                <fields>
+                    <field>
+                        <name>PARTNUMBER0</name>
+                        <description>These bits read back as 0x11</description>
+                        <bitRange>[7:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>UARTPERIPHID1</name>
+                <addressOffset>0x00000fe4</addressOffset>
+                <description>UARTPeriphID1 Register</description>
+                <resetValue>0x00000010</resetValue>
+                <fields>
+                    <field>
+                        <name>DESIGNER0</name>
+                        <description>These bits read back as 0x1</description>
+                        <bitRange>[7:4]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>PARTNUMBER1</name>
+                        <description>These bits read back as 0x0</description>
+                        <bitRange>[3:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>UARTPERIPHID2</name>
+                <addressOffset>0x00000fe8</addressOffset>
+                <description>UARTPeriphID2 Register</description>
+                <resetValue>0x00000034</resetValue>
+                <fields>
+                    <field>
+                        <name>REVISION</name>
+                        <description>This field depends on the revision of the UART: r1p0 0x0 r1p1 0x1 r1p3 0x2 r1p4 0x2 r1p5 0x3</description>
+                        <bitRange>[7:4]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>DESIGNER1</name>
+                        <description>These bits read back as 0x4</description>
+                        <bitRange>[3:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>UARTPERIPHID3</name>
+                <addressOffset>0x00000fec</addressOffset>
+                <description>UARTPeriphID3 Register</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CONFIGURATION</name>
+                        <description>These bits read back as 0x00</description>
+                        <bitRange>[7:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>UARTPCELLID0</name>
+                <addressOffset>0x00000ff0</addressOffset>
+                <description>UARTPCellID0 Register</description>
+                <resetValue>0x0000000d</resetValue>
+                <fields>
+                    <field>
+                        <name>UARTPCELLID0</name>
+                        <description>These bits read back as 0x0D</description>
+                        <bitRange>[7:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>UARTPCELLID1</name>
+                <addressOffset>0x00000ff4</addressOffset>
+                <description>UARTPCellID1 Register</description>
+                <resetValue>0x000000f0</resetValue>
+                <fields>
+                    <field>
+                        <name>UARTPCELLID1</name>
+                        <description>These bits read back as 0xF0</description>
+                        <bitRange>[7:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>UARTPCELLID2</name>
+                <addressOffset>0x00000ff8</addressOffset>
+                <description>UARTPCellID2 Register</description>
+                <resetValue>0x00000005</resetValue>
+                <fields>
+                    <field>
+                        <name>UARTPCELLID2</name>
+                        <description>These bits read back as 0x05</description>
+                        <bitRange>[7:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>UARTPCELLID3</name>
+                <addressOffset>0x00000ffc</addressOffset>
+                <description>UARTPCellID3 Register</description>
+                <resetValue>0x000000b1</resetValue>
+                <fields>
+                    <field>
+                        <name>UARTPCELLID3</name>
+                        <description>These bits read back as 0xB1</description>
+                        <bitRange>[7:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+        </registers>
+    </peripheral>
+    <peripheral derivedFrom="UART0">
+        <name>UART1</name>
+        <baseAddress>0x40038000</baseAddress>
+        <interrupt>
+        <name>UART1_IRQ</name>
+        <value>21</value>
+    </interrupt>
+    </peripheral>
+    <peripheral>
+        <name>ROSC</name>
+        <baseAddress>0x40060000</baseAddress>
+        <addressBlock>
+            <offset>0</offset>
+            <size>36</size>
+            <usage>registers</usage>
+        </addressBlock>
+        <registers>
+            <register>
+                <name>CTRL</name>
+                <addressOffset>0x00000000</addressOffset>
+                <description>Ring Oscillator control</description>
+                <resetValue>0x00000aa0</resetValue>
+                <fields>
+                    <field>
+                        <name>ENABLE</name>
+                        <description>On power-up this field is initialised to ENABLE 
+                            The system clock must be switched to another source before setting this field to DISABLE otherwise the chip will lock up 
+                            The 12-bit code is intended to give some protection against accidental writes. An invalid setting will enable the oscillator.</description>
+                        <bitRange>[23:12]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>DISABLE</name>
+                                <value>3358</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ENABLE</name>
+                                <value>4011</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>FREQ_RANGE</name>
+                        <description>Controls the number of delay stages in the ROSC ring 
+                            LOW uses stages 0 to 7 
+                            MEDIUM uses stages 2 to 7 
+                            HIGH uses stages 4 to 7 
+                            TOOHIGH uses stages 6 to 7 and should not be used because its frequency exceeds design specifications 
+                            The clock output will not glitch when changing the range up one step at a time 
+                            The clock output will glitch when changing the range down 
+                            Note: the values here are gray coded which is why HIGH comes before TOOHIGH</description>
+                        <bitRange>[11:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>4004</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>MEDIUM</name>
+                                <value>4005</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>4007</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TOOHIGH</name>
+                                <value>4006</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>FREQA</name>
+                <addressOffset>0x00000004</addressOffset>
+                <description>The FREQA &amp; FREQB registers control the frequency by controlling the drive strength of each stage 
+                    The drive strength has 4 levels determined by the number of bits set 
+                    Increasing the number of bits set increases the drive strength and increases the oscillation frequency 
+                    0 bits set is the default drive strength 
+                    1 bit set doubles the drive strength 
+                    2 bits set triples drive strength 
+                    3 bits set quadruples drive strength</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>PASSWD</name>
+                        <description>Set to 0x9696 to apply the settings 
+                            Any other value in this field will set all drive strengths to 0</description>
+                        <bitRange>[31:16]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>PASS</name>
+                                <value>38550</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>DS3</name>
+                        <description>Stage 3 drive strength</description>
+                        <bitRange>[14:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DS2</name>
+                        <description>Stage 2 drive strength</description>
+                        <bitRange>[10:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DS1</name>
+                        <description>Stage 1 drive strength</description>
+                        <bitRange>[6:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DS0</name>
+                        <description>Stage 0 drive strength</description>
+                        <bitRange>[2:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>FREQB</name>
+                <addressOffset>0x00000008</addressOffset>
+                <description>For a detailed description see freqa register</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>PASSWD</name>
+                        <description>Set to 0x9696 to apply the settings 
+                            Any other value in this field will set all drive strengths to 0</description>
+                        <bitRange>[31:16]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>PASS</name>
+                                <value>38550</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>DS7</name>
+                        <description>Stage 7 drive strength</description>
+                        <bitRange>[14:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DS6</name>
+                        <description>Stage 6 drive strength</description>
+                        <bitRange>[10:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DS5</name>
+                        <description>Stage 5 drive strength</description>
+                        <bitRange>[6:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DS4</name>
+                        <description>Stage 4 drive strength</description>
+                        <bitRange>[2:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>DORMANT</name>
+                <addressOffset>0x0000000c</addressOffset>
+                <description>Ring Oscillator pause control</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>DORMANT</name>
+                        <description>This is used to save power by pausing the ROSC 
+                            On power-up this field is initialised to WAKE 
+                            An invalid write will also select WAKE 
+                            Warning: setup the irq before selecting dormant mode</description>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>dormant</name>
+                                <value>1668246881</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>WAKE</name>
+                                <value>2002873189</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>DIV</name>
+                <addressOffset>0x00000010</addressOffset>
+                <description>Controls the output divider</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>DIV</name>
+                        <description>set to 0xaa0 + div where 
+                            div = 0 divides by 32 
+                            div = 1-31 divides by div 
+                            any other value sets div=31 
+                            this register resets to div=16</description>
+                        <bitRange>[11:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>PASS</name>
+                                <value>2720</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PHASE</name>
+                <addressOffset>0x00000014</addressOffset>
+                <description>Controls the phase shifted output</description>
+                <resetValue>0x00000008</resetValue>
+                <fields>
+                    <field>
+                        <name>PASSWD</name>
+                        <description>set to 0xaa 
+                            any other value enables the output with shift=0</description>
+                        <bitRange>[11:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ENABLE</name>
+                        <description>enable the phase-shifted output 
+                            this can be changed on-the-fly</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>FLIP</name>
+                        <description>invert the phase-shifted output 
+                            this is ignored when div=1</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SHIFT</name>
+                        <description>phase shift the phase-shifted output by SHIFT input clocks 
+                            this can be changed on-the-fly 
+                            must be set to 0 before setting div=1</description>
+                        <bitRange>[1:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>STATUS</name>
+                <addressOffset>0x00000018</addressOffset>
+                <description>Ring Oscillator Status</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>STABLE</name>
+                        <description>Oscillator is running and stable</description>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>BADWRITE</name>
+                        <description>An invalid value has been written to CTRL_ENABLE or CTRL_FREQ_RANGE or FREQA or FREQB or DIV or PHASE or DORMANT</description>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>DIV_RUNNING</name>
+                        <description>post-divider is running 
+                            this resets to 0 but transitions to 1 during chip startup</description>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>ENABLED</name>
+                        <description>Oscillator is enabled but not necessarily running and stable 
+                            this resets to 0 but transitions to 1 during chip startup</description>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>RANDOMBIT</name>
+                <addressOffset>0x0000001c</addressOffset>
+                <description>This just reads the state of the oscillator output so randomness is compromised if the ring oscillator is stopped or run at a harmonic of the bus frequency</description>
+                <resetValue>0x00000001</resetValue>
+                <fields>
+                    <field>
+                        <name>RANDOMBIT</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>COUNT</name>
+                <addressOffset>0x00000020</addressOffset>
+                <description>A down counter running at the ROSC frequency which counts to zero and stops. 
+                    To start the counter write a non-zero value. 
+                    Can be used for short software pauses when setting up time sensitive hardware.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>COUNT</name>
+                        <bitRange>[7:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+        </registers>
+    </peripheral>
+    <peripheral>
+        <name>WATCHDOG</name>
+        <baseAddress>0x40058000</baseAddress>
+        <addressBlock>
+            <offset>0</offset>
+            <size>48</size>
+            <usage>registers</usage>
+        </addressBlock>
+        <registers>
+            <register>
+                <name>CTRL</name>
+                <addressOffset>0x00000000</addressOffset>
+                <description>Watchdog control 
+                    The rst_wdsel register determines which subsystems are reset when the watchdog is triggered. 
+                    The watchdog can be triggered in software.</description>
+                <resetValue>0x07000000</resetValue>
+                <fields>
+                    <field>
+                        <name>TRIGGER</name>
+                        <description>Trigger a watchdog reset</description>
+                        <bitRange>[31:31]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>ENABLE</name>
+                        <description>When not enabled the watchdog timer is paused</description>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PAUSE_DBG1</name>
+                        <description>Pause the watchdog timer when processor 1 is in debug mode</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PAUSE_DBG0</name>
+                        <description>Pause the watchdog timer when processor 0 is in debug mode</description>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PAUSE_JTAG</name>
+                        <description>Pause the watchdog timer when JTAG is accessing the bus fabric</description>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>TIME</name>
+                        <description>Indicates the number of ticks / 2 (see errata RP2040-E1) before a watchdog reset will be triggered</description>
+                        <bitRange>[23:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>LOAD</name>
+                <addressOffset>0x00000004</addressOffset>
+                <description>Load the watchdog timer. The maximum setting is 0xffffff which corresponds to 0xffffff / 2 ticks before triggering a watchdog reset (see errata RP2040-E1).</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>LOAD</name>
+                        <bitRange>[23:0]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>REASON</name>
+                <addressOffset>0x00000008</addressOffset>
+                <description>Logs the reason for the last reset. Both bits are zero for the case of a hardware reset.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>FORCE</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>TIMER</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SCRATCH0</name>
+                <addressOffset>0x0000000c</addressOffset>
+                <description>Scratch register. Information persists through soft reset of the chip.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>SCRATCH0</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SCRATCH1</name>
+                <addressOffset>0x00000010</addressOffset>
+                <description>Scratch register. Information persists through soft reset of the chip.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>SCRATCH1</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SCRATCH2</name>
+                <addressOffset>0x00000014</addressOffset>
+                <description>Scratch register. Information persists through soft reset of the chip.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>SCRATCH2</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SCRATCH3</name>
+                <addressOffset>0x00000018</addressOffset>
+                <description>Scratch register. Information persists through soft reset of the chip.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>SCRATCH3</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SCRATCH4</name>
+                <addressOffset>0x0000001c</addressOffset>
+                <description>Scratch register. Information persists through soft reset of the chip.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>SCRATCH4</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SCRATCH5</name>
+                <addressOffset>0x00000020</addressOffset>
+                <description>Scratch register. Information persists through soft reset of the chip.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>SCRATCH5</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SCRATCH6</name>
+                <addressOffset>0x00000024</addressOffset>
+                <description>Scratch register. Information persists through soft reset of the chip.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>SCRATCH6</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SCRATCH7</name>
+                <addressOffset>0x00000028</addressOffset>
+                <description>Scratch register. Information persists through soft reset of the chip.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>SCRATCH7</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>TICK</name>
+                <addressOffset>0x0000002c</addressOffset>
+                <description>Controls the tick generator</description>
+                <resetValue>0x00000200</resetValue>
+                <fields>
+                    <field>
+                        <name>COUNT</name>
+                        <description>Count down timer: the remaining number clk_tick cycles before the next tick is generated.</description>
+                        <bitRange>[19:11]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>RUNNING</name>
+                        <description>Is the tick generator running?</description>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>ENABLE</name>
+                        <description>start / stop tick generation</description>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CYCLES</name>
+                        <description>Total number of clk_tick cycles before the next tick.</description>
+                        <bitRange>[8:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+        </registers>
+    </peripheral>
+    <peripheral>
+        <name>DMA</name>
+        <description>DMA with separate read and write masters</description>
+        <baseAddress>0x50000000</baseAddress>
+        <addressBlock>
+            <offset>0</offset>
+            <size>2760</size>
+            <usage>registers</usage>
+        </addressBlock>
+        <interrupt>
+            <name>DMA_IRQ_0</name>
+            <value>11</value>
+        </interrupt>
+        <interrupt>
+            <name>DMA_IRQ_1</name>
+            <value>12</value>
+        </interrupt>
+        <registers>
+            <register>
+                <name>CH0_READ_ADDR</name>
+                <addressOffset>0x00000000</addressOffset>
+                <description>DMA Channel 0 Read Address pointer</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CH0_READ_ADDR</name>
+                        <description>This register updates automatically each time a read completes. The current value is the next address to be read by this channel.</description>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH0_WRITE_ADDR</name>
+                <addressOffset>0x00000004</addressOffset>
+                <description>DMA Channel 0 Write Address pointer</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CH0_WRITE_ADDR</name>
+                        <description>This register updates automatically each time a write completes. The current value is the next address to be written by this channel.</description>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH0_TRANS_COUNT</name>
+                <addressOffset>0x00000008</addressOffset>
+                <description>DMA Channel 0 Transfer Count</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CH0_TRANS_COUNT</name>
+                        <description>Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).
+
+                            When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.
+
+                            Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.
+
+                            The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD.</description>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH0_CTRL_TRIG</name>
+                <addressOffset>0x0000000c</addressOffset>
+                <description>DMA Channel 0 Control and Status</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>AHB_ERROR</name>
+                        <description>Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag.</description>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>READ_ERROR</name>
+                        <description>If 1, the channel received a read bus error. Write one to clear. 
+                            READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)</description>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>WRITE_ERROR</name>
+                        <description>If 1, the channel received a write bus error. Write one to clear. 
+                            WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)</description>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>BUSY</name>
+                        <description>This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.
+
+                            To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT.</description>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SNIFF_EN</name>
+                        <description>If 1, this channel&#39;s data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.
+
+                            This allows checksum to be enabled or disabled on a per-control- block basis.</description>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>BSWAP</name>
+                        <description>Apply byte-swap transformation to DMA data. 
+                            For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.</description>
+                        <bitRange>[22:22]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>IRQ_QUIET</name>
+                        <description>In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.
+
+                            This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.</description>
+                        <bitRange>[21:21]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>TREQ_SEL</name>
+                        <description>Select a Transfer Request signal. 
+                            The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). 
+                            0x0 to 0x3a -&gt; select DREQ n as TREQ</description>
+                        <bitRange>[20:15]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>PIO0_TX0</name>
+                                <value>0</value>
+                                <description>Select PIO0&#39;s TX FIFO 0 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO0_TX1</name>
+                                <value>1</value>
+                                <description>Select PIO0&#39;s TX FIFO 1 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO0_TX2</name>
+                                <value>2</value>
+                                <description>Select PIO0&#39;s TX FIFO 2 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO0_TX3</name>
+                                <value>3</value>
+                                <description>Select PIO0&#39;s TX FIFO 3 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO0_RX0</name>
+                                <value>4</value>
+                                <description>Select PIO0&#39;s RX FIFO 0 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO0_RX1</name>
+                                <value>5</value>
+                                <description>Select PIO0&#39;s RX FIFO 1 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO0_RX2</name>
+                                <value>6</value>
+                                <description>Select PIO0&#39;s RX FIFO 2 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO0_RX3</name>
+                                <value>7</value>
+                                <description>Select PIO0&#39;s RX FIFO 3 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_TX0</name>
+                                <value>8</value>
+                                <description>Select PIO1&#39;s TX FIFO 0 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_TX1</name>
+                                <value>9</value>
+                                <description>Select PIO1&#39;s TX FIFO 1 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_TX2</name>
+                                <value>10</value>
+                                <description>Select PIO1&#39;s TX FIFO 2 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_TX3</name>
+                                <value>11</value>
+                                <description>Select PIO1&#39;s TX FIFO 3 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_RX0</name>
+                                <value>12</value>
+                                <description>Select PIO1&#39;s RX FIFO 0 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_RX1</name>
+                                <value>13</value>
+                                <description>Select PIO1&#39;s RX FIFO 1 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_RX2</name>
+                                <value>14</value>
+                                <description>Select PIO1&#39;s RX FIFO 2 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_RX3</name>
+                                <value>15</value>
+                                <description>Select PIO1&#39;s RX FIFO 3 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SPI0_TX</name>
+                                <value>16</value>
+                                <description>Select SPI0&#39;s TX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SPI0_RX</name>
+                                <value>17</value>
+                                <description>Select SPI0&#39;s RX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SPI1_TX</name>
+                                <value>18</value>
+                                <description>Select SPI1&#39;s TX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SPI1_RX</name>
+                                <value>19</value>
+                                <description>Select SPI1&#39;s RX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UART0_TX</name>
+                                <value>20</value>
+                                <description>Select UART0&#39;s TX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UART0_RX</name>
+                                <value>21</value>
+                                <description>Select UART0&#39;s RX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UART1_TX</name>
+                                <value>22</value>
+                                <description>Select UART1&#39;s TX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UART1_RX</name>
+                                <value>23</value>
+                                <description>Select UART1&#39;s RX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP0</name>
+                                <value>24</value>
+                                <description>Select PWM Counter 0&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP1</name>
+                                <value>25</value>
+                                <description>Select PWM Counter 1&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP2</name>
+                                <value>26</value>
+                                <description>Select PWM Counter 2&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP3</name>
+                                <value>27</value>
+                                <description>Select PWM Counter 3&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP4</name>
+                                <value>28</value>
+                                <description>Select PWM Counter 4&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP5</name>
+                                <value>29</value>
+                                <description>Select PWM Counter 5&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP6</name>
+                                <value>30</value>
+                                <description>Select PWM Counter 6&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP7</name>
+                                <value>31</value>
+                                <description>Select PWM Counter 7&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>I2C0_TX</name>
+                                <value>32</value>
+                                <description>Select I2C0&#39;s TX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>I2C0_RX</name>
+                                <value>33</value>
+                                <description>Select I2C0&#39;s RX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>I2C1_TX</name>
+                                <value>34</value>
+                                <description>Select I2C1&#39;s TX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>I2C1_RX</name>
+                                <value>35</value>
+                                <description>Select I2C1&#39;s RX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC</name>
+                                <value>36</value>
+                                <description>Select the ADC as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>XIP_STREAM</name>
+                                <value>37</value>
+                                <description>Select the XIP Streaming FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>XIP_SSITX</name>
+                                <value>38</value>
+                                <description>Select the XIP SSI TX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>XIP_SSIRX</name>
+                                <value>39</value>
+                                <description>Select the XIP SSI RX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TIMER0</name>
+                                <value>59</value>
+                                <description>Select Timer 0 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TIMER1</name>
+                                <value>60</value>
+                                <description>Select Timer 1 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TIMER2</name>
+                                <value>61</value>
+                                <description>Select Timer 2 as TREQ (Optional)</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TIMER3</name>
+                                <value>62</value>
+                                <description>Select Timer 3 as TREQ (Optional)</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PERMANENT</name>
+                                <value>63</value>
+                                <description>Permanent request, for unpaced transfers.</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>CHAIN_TO</name>
+                        <description>When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.</description>
+                        <bitRange>[14:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>RING_SEL</name>
+                        <description>Select whether RING_SIZE applies to read or write addresses. 
+                            If 0, read addresses are wrapped on a (1 &lt;&lt; RING_SIZE) boundary. If 1, write addresses are wrapped.</description>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>RING_SIZE</name>
+                        <description>Size of address wrap region. If 0, don&#39;t wrap. For values n &gt; 0, only the lower n bits of the address will change. This wraps the address on a (1 &lt;&lt; n) byte boundary, facilitating access to naturally-aligned ring buffers.
+
+                            Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.</description>
+                        <bitRange>[9:6]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>RING_NONE</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>INCR_WRITE</name>
+                        <description>If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.
+
+                            Generally this should be disabled for memory-to-peripheral transfers.</description>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INCR_READ</name>
+                        <description>If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.
+
+                            Generally this should be disabled for peripheral-to-memory transfers.</description>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DATA_SIZE</name>
+                        <description>Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.</description>
+                        <bitRange>[3:2]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>SIZE_BYTE</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SIZE_HALFWORD</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SIZE_WORD</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>HIGH_PRIORITY</name>
+                        <description>HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.
+
+                            This only affects the order in which the DMA schedules channels. The DMA&#39;s bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>EN</name>
+                        <description>DMA Channel Enable. 
+                            When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH0_AL1_CTRL</name>
+                <addressOffset>0x00000010</addressOffset>
+                <description>Alias for channel 0 CTRL register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH0_AL1_CTRL</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH0_AL1_READ_ADDR</name>
+                <addressOffset>0x00000014</addressOffset>
+                <description>Alias for channel 0 READ_ADDR register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH0_AL1_READ_ADDR</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH0_AL1_WRITE_ADDR</name>
+                <addressOffset>0x00000018</addressOffset>
+                <description>Alias for channel 0 WRITE_ADDR register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH0_AL1_WRITE_ADDR</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH0_AL1_TRANS_COUNT_TRIG</name>
+                <addressOffset>0x0000001c</addressOffset>
+                <description>Alias for channel 0 TRANS_COUNT register 
+                    This is a trigger register (0xc). Writing a nonzero value will 
+                    reload the channel counter and start the channel.</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH0_AL1_TRANS_COUNT_TRIG</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH0_AL2_CTRL</name>
+                <addressOffset>0x00000020</addressOffset>
+                <description>Alias for channel 0 CTRL register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH0_AL2_CTRL</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH0_AL2_TRANS_COUNT</name>
+                <addressOffset>0x00000024</addressOffset>
+                <description>Alias for channel 0 TRANS_COUNT register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH0_AL2_TRANS_COUNT</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH0_AL2_READ_ADDR</name>
+                <addressOffset>0x00000028</addressOffset>
+                <description>Alias for channel 0 READ_ADDR register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH0_AL2_READ_ADDR</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH0_AL2_WRITE_ADDR_TRIG</name>
+                <addressOffset>0x0000002c</addressOffset>
+                <description>Alias for channel 0 WRITE_ADDR register 
+                    This is a trigger register (0xc). Writing a nonzero value will 
+                    reload the channel counter and start the channel.</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH0_AL2_WRITE_ADDR_TRIG</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH0_AL3_CTRL</name>
+                <addressOffset>0x00000030</addressOffset>
+                <description>Alias for channel 0 CTRL register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH0_AL3_CTRL</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH0_AL3_WRITE_ADDR</name>
+                <addressOffset>0x00000034</addressOffset>
+                <description>Alias for channel 0 WRITE_ADDR register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH0_AL3_WRITE_ADDR</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH0_AL3_TRANS_COUNT</name>
+                <addressOffset>0x00000038</addressOffset>
+                <description>Alias for channel 0 TRANS_COUNT register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH0_AL3_TRANS_COUNT</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH0_AL3_READ_ADDR_TRIG</name>
+                <addressOffset>0x0000003c</addressOffset>
+                <description>Alias for channel 0 READ_ADDR register 
+                    This is a trigger register (0xc). Writing a nonzero value will 
+                    reload the channel counter and start the channel.</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH0_AL3_READ_ADDR_TRIG</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH1_READ_ADDR</name>
+                <addressOffset>0x00000040</addressOffset>
+                <description>DMA Channel 1 Read Address pointer</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CH1_READ_ADDR</name>
+                        <description>This register updates automatically each time a read completes. The current value is the next address to be read by this channel.</description>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH1_WRITE_ADDR</name>
+                <addressOffset>0x00000044</addressOffset>
+                <description>DMA Channel 1 Write Address pointer</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CH1_WRITE_ADDR</name>
+                        <description>This register updates automatically each time a write completes. The current value is the next address to be written by this channel.</description>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH1_TRANS_COUNT</name>
+                <addressOffset>0x00000048</addressOffset>
+                <description>DMA Channel 1 Transfer Count</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CH1_TRANS_COUNT</name>
+                        <description>Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).
+
+                            When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.
+
+                            Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.
+
+                            The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD.</description>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH1_CTRL_TRIG</name>
+                <addressOffset>0x0000004c</addressOffset>
+                <description>DMA Channel 1 Control and Status</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>AHB_ERROR</name>
+                        <description>Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag.</description>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>READ_ERROR</name>
+                        <description>If 1, the channel received a read bus error. Write one to clear. 
+                            READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)</description>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>WRITE_ERROR</name>
+                        <description>If 1, the channel received a write bus error. Write one to clear. 
+                            WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)</description>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>BUSY</name>
+                        <description>This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.
+
+                            To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT.</description>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SNIFF_EN</name>
+                        <description>If 1, this channel&#39;s data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.
+
+                            This allows checksum to be enabled or disabled on a per-control- block basis.</description>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>BSWAP</name>
+                        <description>Apply byte-swap transformation to DMA data. 
+                            For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.</description>
+                        <bitRange>[22:22]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>IRQ_QUIET</name>
+                        <description>In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.
+
+                            This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.</description>
+                        <bitRange>[21:21]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>TREQ_SEL</name>
+                        <description>Select a Transfer Request signal. 
+                            The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). 
+                            0x0 to 0x3a -&gt; select DREQ n as TREQ</description>
+                        <bitRange>[20:15]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>PIO0_TX0</name>
+                                <value>0</value>
+                                <description>Select PIO0&#39;s TX FIFO 0 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO0_TX1</name>
+                                <value>1</value>
+                                <description>Select PIO0&#39;s TX FIFO 1 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO0_TX2</name>
+                                <value>2</value>
+                                <description>Select PIO0&#39;s TX FIFO 2 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO0_TX3</name>
+                                <value>3</value>
+                                <description>Select PIO0&#39;s TX FIFO 3 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO0_RX0</name>
+                                <value>4</value>
+                                <description>Select PIO0&#39;s RX FIFO 0 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO0_RX1</name>
+                                <value>5</value>
+                                <description>Select PIO0&#39;s RX FIFO 1 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO0_RX2</name>
+                                <value>6</value>
+                                <description>Select PIO0&#39;s RX FIFO 2 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO0_RX3</name>
+                                <value>7</value>
+                                <description>Select PIO0&#39;s RX FIFO 3 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_TX0</name>
+                                <value>8</value>
+                                <description>Select PIO1&#39;s TX FIFO 0 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_TX1</name>
+                                <value>9</value>
+                                <description>Select PIO1&#39;s TX FIFO 1 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_TX2</name>
+                                <value>10</value>
+                                <description>Select PIO1&#39;s TX FIFO 2 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_TX3</name>
+                                <value>11</value>
+                                <description>Select PIO1&#39;s TX FIFO 3 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_RX0</name>
+                                <value>12</value>
+                                <description>Select PIO1&#39;s RX FIFO 0 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_RX1</name>
+                                <value>13</value>
+                                <description>Select PIO1&#39;s RX FIFO 1 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_RX2</name>
+                                <value>14</value>
+                                <description>Select PIO1&#39;s RX FIFO 2 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_RX3</name>
+                                <value>15</value>
+                                <description>Select PIO1&#39;s RX FIFO 3 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SPI0_TX</name>
+                                <value>16</value>
+                                <description>Select SPI0&#39;s TX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SPI0_RX</name>
+                                <value>17</value>
+                                <description>Select SPI0&#39;s RX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SPI1_TX</name>
+                                <value>18</value>
+                                <description>Select SPI1&#39;s TX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SPI1_RX</name>
+                                <value>19</value>
+                                <description>Select SPI1&#39;s RX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UART0_TX</name>
+                                <value>20</value>
+                                <description>Select UART0&#39;s TX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UART0_RX</name>
+                                <value>21</value>
+                                <description>Select UART0&#39;s RX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UART1_TX</name>
+                                <value>22</value>
+                                <description>Select UART1&#39;s TX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UART1_RX</name>
+                                <value>23</value>
+                                <description>Select UART1&#39;s RX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP0</name>
+                                <value>24</value>
+                                <description>Select PWM Counter 0&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP1</name>
+                                <value>25</value>
+                                <description>Select PWM Counter 1&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP2</name>
+                                <value>26</value>
+                                <description>Select PWM Counter 2&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP3</name>
+                                <value>27</value>
+                                <description>Select PWM Counter 3&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP4</name>
+                                <value>28</value>
+                                <description>Select PWM Counter 4&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP5</name>
+                                <value>29</value>
+                                <description>Select PWM Counter 5&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP6</name>
+                                <value>30</value>
+                                <description>Select PWM Counter 6&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP7</name>
+                                <value>31</value>
+                                <description>Select PWM Counter 7&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>I2C0_TX</name>
+                                <value>32</value>
+                                <description>Select I2C0&#39;s TX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>I2C0_RX</name>
+                                <value>33</value>
+                                <description>Select I2C0&#39;s RX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>I2C1_TX</name>
+                                <value>34</value>
+                                <description>Select I2C1&#39;s TX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>I2C1_RX</name>
+                                <value>35</value>
+                                <description>Select I2C1&#39;s RX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC</name>
+                                <value>36</value>
+                                <description>Select the ADC as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>XIP_STREAM</name>
+                                <value>37</value>
+                                <description>Select the XIP Streaming FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>XIP_SSITX</name>
+                                <value>38</value>
+                                <description>Select the XIP SSI TX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>XIP_SSIRX</name>
+                                <value>39</value>
+                                <description>Select the XIP SSI RX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TIMER0</name>
+                                <value>59</value>
+                                <description>Select Timer 0 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TIMER1</name>
+                                <value>60</value>
+                                <description>Select Timer 1 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TIMER2</name>
+                                <value>61</value>
+                                <description>Select Timer 2 as TREQ (Optional)</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TIMER3</name>
+                                <value>62</value>
+                                <description>Select Timer 3 as TREQ (Optional)</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PERMANENT</name>
+                                <value>63</value>
+                                <description>Permanent request, for unpaced transfers.</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>CHAIN_TO</name>
+                        <description>When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.</description>
+                        <bitRange>[14:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>RING_SEL</name>
+                        <description>Select whether RING_SIZE applies to read or write addresses. 
+                            If 0, read addresses are wrapped on a (1 &lt;&lt; RING_SIZE) boundary. If 1, write addresses are wrapped.</description>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>RING_SIZE</name>
+                        <description>Size of address wrap region. If 0, don&#39;t wrap. For values n &gt; 0, only the lower n bits of the address will change. This wraps the address on a (1 &lt;&lt; n) byte boundary, facilitating access to naturally-aligned ring buffers.
+
+                            Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.</description>
+                        <bitRange>[9:6]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>RING_NONE</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>INCR_WRITE</name>
+                        <description>If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.
+
+                            Generally this should be disabled for memory-to-peripheral transfers.</description>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INCR_READ</name>
+                        <description>If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.
+
+                            Generally this should be disabled for peripheral-to-memory transfers.</description>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DATA_SIZE</name>
+                        <description>Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.</description>
+                        <bitRange>[3:2]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>SIZE_BYTE</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SIZE_HALFWORD</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SIZE_WORD</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>HIGH_PRIORITY</name>
+                        <description>HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.
+
+                            This only affects the order in which the DMA schedules channels. The DMA&#39;s bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>EN</name>
+                        <description>DMA Channel Enable. 
+                            When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH1_AL1_CTRL</name>
+                <addressOffset>0x00000050</addressOffset>
+                <description>Alias for channel 1 CTRL register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH1_AL1_CTRL</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH1_AL1_READ_ADDR</name>
+                <addressOffset>0x00000054</addressOffset>
+                <description>Alias for channel 1 READ_ADDR register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH1_AL1_READ_ADDR</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH1_AL1_WRITE_ADDR</name>
+                <addressOffset>0x00000058</addressOffset>
+                <description>Alias for channel 1 WRITE_ADDR register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH1_AL1_WRITE_ADDR</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH1_AL1_TRANS_COUNT_TRIG</name>
+                <addressOffset>0x0000005c</addressOffset>
+                <description>Alias for channel 1 TRANS_COUNT register 
+                    This is a trigger register (0xc). Writing a nonzero value will 
+                    reload the channel counter and start the channel.</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH1_AL1_TRANS_COUNT_TRIG</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH1_AL2_CTRL</name>
+                <addressOffset>0x00000060</addressOffset>
+                <description>Alias for channel 1 CTRL register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH1_AL2_CTRL</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH1_AL2_TRANS_COUNT</name>
+                <addressOffset>0x00000064</addressOffset>
+                <description>Alias for channel 1 TRANS_COUNT register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH1_AL2_TRANS_COUNT</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH1_AL2_READ_ADDR</name>
+                <addressOffset>0x00000068</addressOffset>
+                <description>Alias for channel 1 READ_ADDR register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH1_AL2_READ_ADDR</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH1_AL2_WRITE_ADDR_TRIG</name>
+                <addressOffset>0x0000006c</addressOffset>
+                <description>Alias for channel 1 WRITE_ADDR register 
+                    This is a trigger register (0xc). Writing a nonzero value will 
+                    reload the channel counter and start the channel.</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH1_AL2_WRITE_ADDR_TRIG</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH1_AL3_CTRL</name>
+                <addressOffset>0x00000070</addressOffset>
+                <description>Alias for channel 1 CTRL register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH1_AL3_CTRL</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH1_AL3_WRITE_ADDR</name>
+                <addressOffset>0x00000074</addressOffset>
+                <description>Alias for channel 1 WRITE_ADDR register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH1_AL3_WRITE_ADDR</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH1_AL3_TRANS_COUNT</name>
+                <addressOffset>0x00000078</addressOffset>
+                <description>Alias for channel 1 TRANS_COUNT register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH1_AL3_TRANS_COUNT</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH1_AL3_READ_ADDR_TRIG</name>
+                <addressOffset>0x0000007c</addressOffset>
+                <description>Alias for channel 1 READ_ADDR register 
+                    This is a trigger register (0xc). Writing a nonzero value will 
+                    reload the channel counter and start the channel.</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH1_AL3_READ_ADDR_TRIG</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH2_READ_ADDR</name>
+                <addressOffset>0x00000080</addressOffset>
+                <description>DMA Channel 2 Read Address pointer</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CH2_READ_ADDR</name>
+                        <description>This register updates automatically each time a read completes. The current value is the next address to be read by this channel.</description>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH2_WRITE_ADDR</name>
+                <addressOffset>0x00000084</addressOffset>
+                <description>DMA Channel 2 Write Address pointer</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CH2_WRITE_ADDR</name>
+                        <description>This register updates automatically each time a write completes. The current value is the next address to be written by this channel.</description>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH2_TRANS_COUNT</name>
+                <addressOffset>0x00000088</addressOffset>
+                <description>DMA Channel 2 Transfer Count</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CH2_TRANS_COUNT</name>
+                        <description>Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).
+
+                            When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.
+
+                            Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.
+
+                            The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD.</description>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH2_CTRL_TRIG</name>
+                <addressOffset>0x0000008c</addressOffset>
+                <description>DMA Channel 2 Control and Status</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>AHB_ERROR</name>
+                        <description>Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag.</description>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>READ_ERROR</name>
+                        <description>If 1, the channel received a read bus error. Write one to clear. 
+                            READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)</description>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>WRITE_ERROR</name>
+                        <description>If 1, the channel received a write bus error. Write one to clear. 
+                            WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)</description>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>BUSY</name>
+                        <description>This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.
+
+                            To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT.</description>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SNIFF_EN</name>
+                        <description>If 1, this channel&#39;s data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.
+
+                            This allows checksum to be enabled or disabled on a per-control- block basis.</description>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>BSWAP</name>
+                        <description>Apply byte-swap transformation to DMA data. 
+                            For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.</description>
+                        <bitRange>[22:22]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>IRQ_QUIET</name>
+                        <description>In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.
+
+                            This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.</description>
+                        <bitRange>[21:21]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>TREQ_SEL</name>
+                        <description>Select a Transfer Request signal. 
+                            The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). 
+                            0x0 to 0x3a -&gt; select DREQ n as TREQ</description>
+                        <bitRange>[20:15]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>PIO0_TX0</name>
+                                <value>0</value>
+                                <description>Select PIO0&#39;s TX FIFO 0 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO0_TX1</name>
+                                <value>1</value>
+                                <description>Select PIO0&#39;s TX FIFO 1 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO0_TX2</name>
+                                <value>2</value>
+                                <description>Select PIO0&#39;s TX FIFO 2 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO0_TX3</name>
+                                <value>3</value>
+                                <description>Select PIO0&#39;s TX FIFO 3 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO0_RX0</name>
+                                <value>4</value>
+                                <description>Select PIO0&#39;s RX FIFO 0 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO0_RX1</name>
+                                <value>5</value>
+                                <description>Select PIO0&#39;s RX FIFO 1 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO0_RX2</name>
+                                <value>6</value>
+                                <description>Select PIO0&#39;s RX FIFO 2 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO0_RX3</name>
+                                <value>7</value>
+                                <description>Select PIO0&#39;s RX FIFO 3 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_TX0</name>
+                                <value>8</value>
+                                <description>Select PIO1&#39;s TX FIFO 0 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_TX1</name>
+                                <value>9</value>
+                                <description>Select PIO1&#39;s TX FIFO 1 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_TX2</name>
+                                <value>10</value>
+                                <description>Select PIO1&#39;s TX FIFO 2 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_TX3</name>
+                                <value>11</value>
+                                <description>Select PIO1&#39;s TX FIFO 3 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_RX0</name>
+                                <value>12</value>
+                                <description>Select PIO1&#39;s RX FIFO 0 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_RX1</name>
+                                <value>13</value>
+                                <description>Select PIO1&#39;s RX FIFO 1 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_RX2</name>
+                                <value>14</value>
+                                <description>Select PIO1&#39;s RX FIFO 2 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_RX3</name>
+                                <value>15</value>
+                                <description>Select PIO1&#39;s RX FIFO 3 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SPI0_TX</name>
+                                <value>16</value>
+                                <description>Select SPI0&#39;s TX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SPI0_RX</name>
+                                <value>17</value>
+                                <description>Select SPI0&#39;s RX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SPI1_TX</name>
+                                <value>18</value>
+                                <description>Select SPI1&#39;s TX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SPI1_RX</name>
+                                <value>19</value>
+                                <description>Select SPI1&#39;s RX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UART0_TX</name>
+                                <value>20</value>
+                                <description>Select UART0&#39;s TX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UART0_RX</name>
+                                <value>21</value>
+                                <description>Select UART0&#39;s RX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UART1_TX</name>
+                                <value>22</value>
+                                <description>Select UART1&#39;s TX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UART1_RX</name>
+                                <value>23</value>
+                                <description>Select UART1&#39;s RX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP0</name>
+                                <value>24</value>
+                                <description>Select PWM Counter 0&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP1</name>
+                                <value>25</value>
+                                <description>Select PWM Counter 1&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP2</name>
+                                <value>26</value>
+                                <description>Select PWM Counter 2&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP3</name>
+                                <value>27</value>
+                                <description>Select PWM Counter 3&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP4</name>
+                                <value>28</value>
+                                <description>Select PWM Counter 4&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP5</name>
+                                <value>29</value>
+                                <description>Select PWM Counter 5&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP6</name>
+                                <value>30</value>
+                                <description>Select PWM Counter 6&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP7</name>
+                                <value>31</value>
+                                <description>Select PWM Counter 7&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>I2C0_TX</name>
+                                <value>32</value>
+                                <description>Select I2C0&#39;s TX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>I2C0_RX</name>
+                                <value>33</value>
+                                <description>Select I2C0&#39;s RX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>I2C1_TX</name>
+                                <value>34</value>
+                                <description>Select I2C1&#39;s TX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>I2C1_RX</name>
+                                <value>35</value>
+                                <description>Select I2C1&#39;s RX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC</name>
+                                <value>36</value>
+                                <description>Select the ADC as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>XIP_STREAM</name>
+                                <value>37</value>
+                                <description>Select the XIP Streaming FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>XIP_SSITX</name>
+                                <value>38</value>
+                                <description>Select the XIP SSI TX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>XIP_SSIRX</name>
+                                <value>39</value>
+                                <description>Select the XIP SSI RX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TIMER0</name>
+                                <value>59</value>
+                                <description>Select Timer 0 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TIMER1</name>
+                                <value>60</value>
+                                <description>Select Timer 1 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TIMER2</name>
+                                <value>61</value>
+                                <description>Select Timer 2 as TREQ (Optional)</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TIMER3</name>
+                                <value>62</value>
+                                <description>Select Timer 3 as TREQ (Optional)</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PERMANENT</name>
+                                <value>63</value>
+                                <description>Permanent request, for unpaced transfers.</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>CHAIN_TO</name>
+                        <description>When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.</description>
+                        <bitRange>[14:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>RING_SEL</name>
+                        <description>Select whether RING_SIZE applies to read or write addresses. 
+                            If 0, read addresses are wrapped on a (1 &lt;&lt; RING_SIZE) boundary. If 1, write addresses are wrapped.</description>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>RING_SIZE</name>
+                        <description>Size of address wrap region. If 0, don&#39;t wrap. For values n &gt; 0, only the lower n bits of the address will change. This wraps the address on a (1 &lt;&lt; n) byte boundary, facilitating access to naturally-aligned ring buffers.
+
+                            Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.</description>
+                        <bitRange>[9:6]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>RING_NONE</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>INCR_WRITE</name>
+                        <description>If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.
+
+                            Generally this should be disabled for memory-to-peripheral transfers.</description>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INCR_READ</name>
+                        <description>If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.
+
+                            Generally this should be disabled for peripheral-to-memory transfers.</description>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DATA_SIZE</name>
+                        <description>Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.</description>
+                        <bitRange>[3:2]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>SIZE_BYTE</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SIZE_HALFWORD</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SIZE_WORD</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>HIGH_PRIORITY</name>
+                        <description>HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.
+
+                            This only affects the order in which the DMA schedules channels. The DMA&#39;s bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>EN</name>
+                        <description>DMA Channel Enable. 
+                            When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH2_AL1_CTRL</name>
+                <addressOffset>0x00000090</addressOffset>
+                <description>Alias for channel 2 CTRL register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH2_AL1_CTRL</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH2_AL1_READ_ADDR</name>
+                <addressOffset>0x00000094</addressOffset>
+                <description>Alias for channel 2 READ_ADDR register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH2_AL1_READ_ADDR</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH2_AL1_WRITE_ADDR</name>
+                <addressOffset>0x00000098</addressOffset>
+                <description>Alias for channel 2 WRITE_ADDR register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH2_AL1_WRITE_ADDR</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH2_AL1_TRANS_COUNT_TRIG</name>
+                <addressOffset>0x0000009c</addressOffset>
+                <description>Alias for channel 2 TRANS_COUNT register 
+                    This is a trigger register (0xc). Writing a nonzero value will 
+                    reload the channel counter and start the channel.</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH2_AL1_TRANS_COUNT_TRIG</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH2_AL2_CTRL</name>
+                <addressOffset>0x000000a0</addressOffset>
+                <description>Alias for channel 2 CTRL register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH2_AL2_CTRL</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH2_AL2_TRANS_COUNT</name>
+                <addressOffset>0x000000a4</addressOffset>
+                <description>Alias for channel 2 TRANS_COUNT register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH2_AL2_TRANS_COUNT</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH2_AL2_READ_ADDR</name>
+                <addressOffset>0x000000a8</addressOffset>
+                <description>Alias for channel 2 READ_ADDR register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH2_AL2_READ_ADDR</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH2_AL2_WRITE_ADDR_TRIG</name>
+                <addressOffset>0x000000ac</addressOffset>
+                <description>Alias for channel 2 WRITE_ADDR register 
+                    This is a trigger register (0xc). Writing a nonzero value will 
+                    reload the channel counter and start the channel.</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH2_AL2_WRITE_ADDR_TRIG</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH2_AL3_CTRL</name>
+                <addressOffset>0x000000b0</addressOffset>
+                <description>Alias for channel 2 CTRL register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH2_AL3_CTRL</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH2_AL3_WRITE_ADDR</name>
+                <addressOffset>0x000000b4</addressOffset>
+                <description>Alias for channel 2 WRITE_ADDR register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH2_AL3_WRITE_ADDR</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH2_AL3_TRANS_COUNT</name>
+                <addressOffset>0x000000b8</addressOffset>
+                <description>Alias for channel 2 TRANS_COUNT register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH2_AL3_TRANS_COUNT</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH2_AL3_READ_ADDR_TRIG</name>
+                <addressOffset>0x000000bc</addressOffset>
+                <description>Alias for channel 2 READ_ADDR register 
+                    This is a trigger register (0xc). Writing a nonzero value will 
+                    reload the channel counter and start the channel.</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH2_AL3_READ_ADDR_TRIG</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH3_READ_ADDR</name>
+                <addressOffset>0x000000c0</addressOffset>
+                <description>DMA Channel 3 Read Address pointer</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CH3_READ_ADDR</name>
+                        <description>This register updates automatically each time a read completes. The current value is the next address to be read by this channel.</description>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH3_WRITE_ADDR</name>
+                <addressOffset>0x000000c4</addressOffset>
+                <description>DMA Channel 3 Write Address pointer</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CH3_WRITE_ADDR</name>
+                        <description>This register updates automatically each time a write completes. The current value is the next address to be written by this channel.</description>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH3_TRANS_COUNT</name>
+                <addressOffset>0x000000c8</addressOffset>
+                <description>DMA Channel 3 Transfer Count</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CH3_TRANS_COUNT</name>
+                        <description>Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).
+
+                            When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.
+
+                            Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.
+
+                            The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD.</description>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH3_CTRL_TRIG</name>
+                <addressOffset>0x000000cc</addressOffset>
+                <description>DMA Channel 3 Control and Status</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>AHB_ERROR</name>
+                        <description>Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag.</description>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>READ_ERROR</name>
+                        <description>If 1, the channel received a read bus error. Write one to clear. 
+                            READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)</description>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>WRITE_ERROR</name>
+                        <description>If 1, the channel received a write bus error. Write one to clear. 
+                            WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)</description>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>BUSY</name>
+                        <description>This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.
+
+                            To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT.</description>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SNIFF_EN</name>
+                        <description>If 1, this channel&#39;s data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.
+
+                            This allows checksum to be enabled or disabled on a per-control- block basis.</description>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>BSWAP</name>
+                        <description>Apply byte-swap transformation to DMA data. 
+                            For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.</description>
+                        <bitRange>[22:22]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>IRQ_QUIET</name>
+                        <description>In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.
+
+                            This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.</description>
+                        <bitRange>[21:21]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>TREQ_SEL</name>
+                        <description>Select a Transfer Request signal. 
+                            The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). 
+                            0x0 to 0x3a -&gt; select DREQ n as TREQ</description>
+                        <bitRange>[20:15]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>PIO0_TX0</name>
+                                <value>0</value>
+                                <description>Select PIO0&#39;s TX FIFO 0 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO0_TX1</name>
+                                <value>1</value>
+                                <description>Select PIO0&#39;s TX FIFO 1 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO0_TX2</name>
+                                <value>2</value>
+                                <description>Select PIO0&#39;s TX FIFO 2 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO0_TX3</name>
+                                <value>3</value>
+                                <description>Select PIO0&#39;s TX FIFO 3 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO0_RX0</name>
+                                <value>4</value>
+                                <description>Select PIO0&#39;s RX FIFO 0 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO0_RX1</name>
+                                <value>5</value>
+                                <description>Select PIO0&#39;s RX FIFO 1 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO0_RX2</name>
+                                <value>6</value>
+                                <description>Select PIO0&#39;s RX FIFO 2 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO0_RX3</name>
+                                <value>7</value>
+                                <description>Select PIO0&#39;s RX FIFO 3 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_TX0</name>
+                                <value>8</value>
+                                <description>Select PIO1&#39;s TX FIFO 0 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_TX1</name>
+                                <value>9</value>
+                                <description>Select PIO1&#39;s TX FIFO 1 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_TX2</name>
+                                <value>10</value>
+                                <description>Select PIO1&#39;s TX FIFO 2 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_TX3</name>
+                                <value>11</value>
+                                <description>Select PIO1&#39;s TX FIFO 3 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_RX0</name>
+                                <value>12</value>
+                                <description>Select PIO1&#39;s RX FIFO 0 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_RX1</name>
+                                <value>13</value>
+                                <description>Select PIO1&#39;s RX FIFO 1 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_RX2</name>
+                                <value>14</value>
+                                <description>Select PIO1&#39;s RX FIFO 2 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_RX3</name>
+                                <value>15</value>
+                                <description>Select PIO1&#39;s RX FIFO 3 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SPI0_TX</name>
+                                <value>16</value>
+                                <description>Select SPI0&#39;s TX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SPI0_RX</name>
+                                <value>17</value>
+                                <description>Select SPI0&#39;s RX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SPI1_TX</name>
+                                <value>18</value>
+                                <description>Select SPI1&#39;s TX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SPI1_RX</name>
+                                <value>19</value>
+                                <description>Select SPI1&#39;s RX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UART0_TX</name>
+                                <value>20</value>
+                                <description>Select UART0&#39;s TX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UART0_RX</name>
+                                <value>21</value>
+                                <description>Select UART0&#39;s RX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UART1_TX</name>
+                                <value>22</value>
+                                <description>Select UART1&#39;s TX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UART1_RX</name>
+                                <value>23</value>
+                                <description>Select UART1&#39;s RX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP0</name>
+                                <value>24</value>
+                                <description>Select PWM Counter 0&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP1</name>
+                                <value>25</value>
+                                <description>Select PWM Counter 1&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP2</name>
+                                <value>26</value>
+                                <description>Select PWM Counter 2&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP3</name>
+                                <value>27</value>
+                                <description>Select PWM Counter 3&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP4</name>
+                                <value>28</value>
+                                <description>Select PWM Counter 4&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP5</name>
+                                <value>29</value>
+                                <description>Select PWM Counter 5&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP6</name>
+                                <value>30</value>
+                                <description>Select PWM Counter 6&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP7</name>
+                                <value>31</value>
+                                <description>Select PWM Counter 7&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>I2C0_TX</name>
+                                <value>32</value>
+                                <description>Select I2C0&#39;s TX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>I2C0_RX</name>
+                                <value>33</value>
+                                <description>Select I2C0&#39;s RX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>I2C1_TX</name>
+                                <value>34</value>
+                                <description>Select I2C1&#39;s TX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>I2C1_RX</name>
+                                <value>35</value>
+                                <description>Select I2C1&#39;s RX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC</name>
+                                <value>36</value>
+                                <description>Select the ADC as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>XIP_STREAM</name>
+                                <value>37</value>
+                                <description>Select the XIP Streaming FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>XIP_SSITX</name>
+                                <value>38</value>
+                                <description>Select the XIP SSI TX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>XIP_SSIRX</name>
+                                <value>39</value>
+                                <description>Select the XIP SSI RX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TIMER0</name>
+                                <value>59</value>
+                                <description>Select Timer 0 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TIMER1</name>
+                                <value>60</value>
+                                <description>Select Timer 1 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TIMER2</name>
+                                <value>61</value>
+                                <description>Select Timer 2 as TREQ (Optional)</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TIMER3</name>
+                                <value>62</value>
+                                <description>Select Timer 3 as TREQ (Optional)</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PERMANENT</name>
+                                <value>63</value>
+                                <description>Permanent request, for unpaced transfers.</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>CHAIN_TO</name>
+                        <description>When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.</description>
+                        <bitRange>[14:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>RING_SEL</name>
+                        <description>Select whether RING_SIZE applies to read or write addresses. 
+                            If 0, read addresses are wrapped on a (1 &lt;&lt; RING_SIZE) boundary. If 1, write addresses are wrapped.</description>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>RING_SIZE</name>
+                        <description>Size of address wrap region. If 0, don&#39;t wrap. For values n &gt; 0, only the lower n bits of the address will change. This wraps the address on a (1 &lt;&lt; n) byte boundary, facilitating access to naturally-aligned ring buffers.
+
+                            Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.</description>
+                        <bitRange>[9:6]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>RING_NONE</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>INCR_WRITE</name>
+                        <description>If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.
+
+                            Generally this should be disabled for memory-to-peripheral transfers.</description>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INCR_READ</name>
+                        <description>If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.
+
+                            Generally this should be disabled for peripheral-to-memory transfers.</description>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DATA_SIZE</name>
+                        <description>Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.</description>
+                        <bitRange>[3:2]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>SIZE_BYTE</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SIZE_HALFWORD</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SIZE_WORD</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>HIGH_PRIORITY</name>
+                        <description>HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.
+
+                            This only affects the order in which the DMA schedules channels. The DMA&#39;s bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>EN</name>
+                        <description>DMA Channel Enable. 
+                            When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH3_AL1_CTRL</name>
+                <addressOffset>0x000000d0</addressOffset>
+                <description>Alias for channel 3 CTRL register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH3_AL1_CTRL</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH3_AL1_READ_ADDR</name>
+                <addressOffset>0x000000d4</addressOffset>
+                <description>Alias for channel 3 READ_ADDR register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH3_AL1_READ_ADDR</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH3_AL1_WRITE_ADDR</name>
+                <addressOffset>0x000000d8</addressOffset>
+                <description>Alias for channel 3 WRITE_ADDR register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH3_AL1_WRITE_ADDR</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH3_AL1_TRANS_COUNT_TRIG</name>
+                <addressOffset>0x000000dc</addressOffset>
+                <description>Alias for channel 3 TRANS_COUNT register 
+                    This is a trigger register (0xc). Writing a nonzero value will 
+                    reload the channel counter and start the channel.</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH3_AL1_TRANS_COUNT_TRIG</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH3_AL2_CTRL</name>
+                <addressOffset>0x000000e0</addressOffset>
+                <description>Alias for channel 3 CTRL register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH3_AL2_CTRL</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH3_AL2_TRANS_COUNT</name>
+                <addressOffset>0x000000e4</addressOffset>
+                <description>Alias for channel 3 TRANS_COUNT register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH3_AL2_TRANS_COUNT</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH3_AL2_READ_ADDR</name>
+                <addressOffset>0x000000e8</addressOffset>
+                <description>Alias for channel 3 READ_ADDR register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH3_AL2_READ_ADDR</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH3_AL2_WRITE_ADDR_TRIG</name>
+                <addressOffset>0x000000ec</addressOffset>
+                <description>Alias for channel 3 WRITE_ADDR register 
+                    This is a trigger register (0xc). Writing a nonzero value will 
+                    reload the channel counter and start the channel.</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH3_AL2_WRITE_ADDR_TRIG</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH3_AL3_CTRL</name>
+                <addressOffset>0x000000f0</addressOffset>
+                <description>Alias for channel 3 CTRL register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH3_AL3_CTRL</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH3_AL3_WRITE_ADDR</name>
+                <addressOffset>0x000000f4</addressOffset>
+                <description>Alias for channel 3 WRITE_ADDR register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH3_AL3_WRITE_ADDR</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH3_AL3_TRANS_COUNT</name>
+                <addressOffset>0x000000f8</addressOffset>
+                <description>Alias for channel 3 TRANS_COUNT register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH3_AL3_TRANS_COUNT</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH3_AL3_READ_ADDR_TRIG</name>
+                <addressOffset>0x000000fc</addressOffset>
+                <description>Alias for channel 3 READ_ADDR register 
+                    This is a trigger register (0xc). Writing a nonzero value will 
+                    reload the channel counter and start the channel.</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH3_AL3_READ_ADDR_TRIG</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH4_READ_ADDR</name>
+                <addressOffset>0x00000100</addressOffset>
+                <description>DMA Channel 4 Read Address pointer</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CH4_READ_ADDR</name>
+                        <description>This register updates automatically each time a read completes. The current value is the next address to be read by this channel.</description>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH4_WRITE_ADDR</name>
+                <addressOffset>0x00000104</addressOffset>
+                <description>DMA Channel 4 Write Address pointer</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CH4_WRITE_ADDR</name>
+                        <description>This register updates automatically each time a write completes. The current value is the next address to be written by this channel.</description>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH4_TRANS_COUNT</name>
+                <addressOffset>0x00000108</addressOffset>
+                <description>DMA Channel 4 Transfer Count</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CH4_TRANS_COUNT</name>
+                        <description>Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).
+
+                            When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.
+
+                            Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.
+
+                            The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD.</description>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH4_CTRL_TRIG</name>
+                <addressOffset>0x0000010c</addressOffset>
+                <description>DMA Channel 4 Control and Status</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>AHB_ERROR</name>
+                        <description>Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag.</description>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>READ_ERROR</name>
+                        <description>If 1, the channel received a read bus error. Write one to clear. 
+                            READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)</description>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>WRITE_ERROR</name>
+                        <description>If 1, the channel received a write bus error. Write one to clear. 
+                            WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)</description>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>BUSY</name>
+                        <description>This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.
+
+                            To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT.</description>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SNIFF_EN</name>
+                        <description>If 1, this channel&#39;s data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.
+
+                            This allows checksum to be enabled or disabled on a per-control- block basis.</description>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>BSWAP</name>
+                        <description>Apply byte-swap transformation to DMA data. 
+                            For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.</description>
+                        <bitRange>[22:22]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>IRQ_QUIET</name>
+                        <description>In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.
+
+                            This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.</description>
+                        <bitRange>[21:21]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>TREQ_SEL</name>
+                        <description>Select a Transfer Request signal. 
+                            The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). 
+                            0x0 to 0x3a -&gt; select DREQ n as TREQ</description>
+                        <bitRange>[20:15]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>PIO0_TX0</name>
+                                <value>0</value>
+                                <description>Select PIO0&#39;s TX FIFO 0 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO0_TX1</name>
+                                <value>1</value>
+                                <description>Select PIO0&#39;s TX FIFO 1 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO0_TX2</name>
+                                <value>2</value>
+                                <description>Select PIO0&#39;s TX FIFO 2 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO0_TX3</name>
+                                <value>3</value>
+                                <description>Select PIO0&#39;s TX FIFO 3 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO0_RX0</name>
+                                <value>4</value>
+                                <description>Select PIO0&#39;s RX FIFO 0 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO0_RX1</name>
+                                <value>5</value>
+                                <description>Select PIO0&#39;s RX FIFO 1 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO0_RX2</name>
+                                <value>6</value>
+                                <description>Select PIO0&#39;s RX FIFO 2 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO0_RX3</name>
+                                <value>7</value>
+                                <description>Select PIO0&#39;s RX FIFO 3 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_TX0</name>
+                                <value>8</value>
+                                <description>Select PIO1&#39;s TX FIFO 0 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_TX1</name>
+                                <value>9</value>
+                                <description>Select PIO1&#39;s TX FIFO 1 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_TX2</name>
+                                <value>10</value>
+                                <description>Select PIO1&#39;s TX FIFO 2 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_TX3</name>
+                                <value>11</value>
+                                <description>Select PIO1&#39;s TX FIFO 3 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_RX0</name>
+                                <value>12</value>
+                                <description>Select PIO1&#39;s RX FIFO 0 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_RX1</name>
+                                <value>13</value>
+                                <description>Select PIO1&#39;s RX FIFO 1 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_RX2</name>
+                                <value>14</value>
+                                <description>Select PIO1&#39;s RX FIFO 2 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_RX3</name>
+                                <value>15</value>
+                                <description>Select PIO1&#39;s RX FIFO 3 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SPI0_TX</name>
+                                <value>16</value>
+                                <description>Select SPI0&#39;s TX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SPI0_RX</name>
+                                <value>17</value>
+                                <description>Select SPI0&#39;s RX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SPI1_TX</name>
+                                <value>18</value>
+                                <description>Select SPI1&#39;s TX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SPI1_RX</name>
+                                <value>19</value>
+                                <description>Select SPI1&#39;s RX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UART0_TX</name>
+                                <value>20</value>
+                                <description>Select UART0&#39;s TX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UART0_RX</name>
+                                <value>21</value>
+                                <description>Select UART0&#39;s RX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UART1_TX</name>
+                                <value>22</value>
+                                <description>Select UART1&#39;s TX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UART1_RX</name>
+                                <value>23</value>
+                                <description>Select UART1&#39;s RX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP0</name>
+                                <value>24</value>
+                                <description>Select PWM Counter 0&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP1</name>
+                                <value>25</value>
+                                <description>Select PWM Counter 1&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP2</name>
+                                <value>26</value>
+                                <description>Select PWM Counter 2&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP3</name>
+                                <value>27</value>
+                                <description>Select PWM Counter 3&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP4</name>
+                                <value>28</value>
+                                <description>Select PWM Counter 4&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP5</name>
+                                <value>29</value>
+                                <description>Select PWM Counter 5&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP6</name>
+                                <value>30</value>
+                                <description>Select PWM Counter 6&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP7</name>
+                                <value>31</value>
+                                <description>Select PWM Counter 7&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>I2C0_TX</name>
+                                <value>32</value>
+                                <description>Select I2C0&#39;s TX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>I2C0_RX</name>
+                                <value>33</value>
+                                <description>Select I2C0&#39;s RX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>I2C1_TX</name>
+                                <value>34</value>
+                                <description>Select I2C1&#39;s TX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>I2C1_RX</name>
+                                <value>35</value>
+                                <description>Select I2C1&#39;s RX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC</name>
+                                <value>36</value>
+                                <description>Select the ADC as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>XIP_STREAM</name>
+                                <value>37</value>
+                                <description>Select the XIP Streaming FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>XIP_SSITX</name>
+                                <value>38</value>
+                                <description>Select the XIP SSI TX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>XIP_SSIRX</name>
+                                <value>39</value>
+                                <description>Select the XIP SSI RX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TIMER0</name>
+                                <value>59</value>
+                                <description>Select Timer 0 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TIMER1</name>
+                                <value>60</value>
+                                <description>Select Timer 1 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TIMER2</name>
+                                <value>61</value>
+                                <description>Select Timer 2 as TREQ (Optional)</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TIMER3</name>
+                                <value>62</value>
+                                <description>Select Timer 3 as TREQ (Optional)</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PERMANENT</name>
+                                <value>63</value>
+                                <description>Permanent request, for unpaced transfers.</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>CHAIN_TO</name>
+                        <description>When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.</description>
+                        <bitRange>[14:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>RING_SEL</name>
+                        <description>Select whether RING_SIZE applies to read or write addresses. 
+                            If 0, read addresses are wrapped on a (1 &lt;&lt; RING_SIZE) boundary. If 1, write addresses are wrapped.</description>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>RING_SIZE</name>
+                        <description>Size of address wrap region. If 0, don&#39;t wrap. For values n &gt; 0, only the lower n bits of the address will change. This wraps the address on a (1 &lt;&lt; n) byte boundary, facilitating access to naturally-aligned ring buffers.
+
+                            Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.</description>
+                        <bitRange>[9:6]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>RING_NONE</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>INCR_WRITE</name>
+                        <description>If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.
+
+                            Generally this should be disabled for memory-to-peripheral transfers.</description>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INCR_READ</name>
+                        <description>If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.
+
+                            Generally this should be disabled for peripheral-to-memory transfers.</description>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DATA_SIZE</name>
+                        <description>Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.</description>
+                        <bitRange>[3:2]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>SIZE_BYTE</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SIZE_HALFWORD</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SIZE_WORD</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>HIGH_PRIORITY</name>
+                        <description>HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.
+
+                            This only affects the order in which the DMA schedules channels. The DMA&#39;s bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>EN</name>
+                        <description>DMA Channel Enable. 
+                            When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH4_AL1_CTRL</name>
+                <addressOffset>0x00000110</addressOffset>
+                <description>Alias for channel 4 CTRL register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH4_AL1_CTRL</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH4_AL1_READ_ADDR</name>
+                <addressOffset>0x00000114</addressOffset>
+                <description>Alias for channel 4 READ_ADDR register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH4_AL1_READ_ADDR</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH4_AL1_WRITE_ADDR</name>
+                <addressOffset>0x00000118</addressOffset>
+                <description>Alias for channel 4 WRITE_ADDR register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH4_AL1_WRITE_ADDR</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH4_AL1_TRANS_COUNT_TRIG</name>
+                <addressOffset>0x0000011c</addressOffset>
+                <description>Alias for channel 4 TRANS_COUNT register 
+                    This is a trigger register (0xc). Writing a nonzero value will 
+                    reload the channel counter and start the channel.</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH4_AL1_TRANS_COUNT_TRIG</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH4_AL2_CTRL</name>
+                <addressOffset>0x00000120</addressOffset>
+                <description>Alias for channel 4 CTRL register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH4_AL2_CTRL</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH4_AL2_TRANS_COUNT</name>
+                <addressOffset>0x00000124</addressOffset>
+                <description>Alias for channel 4 TRANS_COUNT register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH4_AL2_TRANS_COUNT</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH4_AL2_READ_ADDR</name>
+                <addressOffset>0x00000128</addressOffset>
+                <description>Alias for channel 4 READ_ADDR register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH4_AL2_READ_ADDR</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH4_AL2_WRITE_ADDR_TRIG</name>
+                <addressOffset>0x0000012c</addressOffset>
+                <description>Alias for channel 4 WRITE_ADDR register 
+                    This is a trigger register (0xc). Writing a nonzero value will 
+                    reload the channel counter and start the channel.</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH4_AL2_WRITE_ADDR_TRIG</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH4_AL3_CTRL</name>
+                <addressOffset>0x00000130</addressOffset>
+                <description>Alias for channel 4 CTRL register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH4_AL3_CTRL</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH4_AL3_WRITE_ADDR</name>
+                <addressOffset>0x00000134</addressOffset>
+                <description>Alias for channel 4 WRITE_ADDR register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH4_AL3_WRITE_ADDR</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH4_AL3_TRANS_COUNT</name>
+                <addressOffset>0x00000138</addressOffset>
+                <description>Alias for channel 4 TRANS_COUNT register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH4_AL3_TRANS_COUNT</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH4_AL3_READ_ADDR_TRIG</name>
+                <addressOffset>0x0000013c</addressOffset>
+                <description>Alias for channel 4 READ_ADDR register 
+                    This is a trigger register (0xc). Writing a nonzero value will 
+                    reload the channel counter and start the channel.</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH4_AL3_READ_ADDR_TRIG</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH5_READ_ADDR</name>
+                <addressOffset>0x00000140</addressOffset>
+                <description>DMA Channel 5 Read Address pointer</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CH5_READ_ADDR</name>
+                        <description>This register updates automatically each time a read completes. The current value is the next address to be read by this channel.</description>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH5_WRITE_ADDR</name>
+                <addressOffset>0x00000144</addressOffset>
+                <description>DMA Channel 5 Write Address pointer</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CH5_WRITE_ADDR</name>
+                        <description>This register updates automatically each time a write completes. The current value is the next address to be written by this channel.</description>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH5_TRANS_COUNT</name>
+                <addressOffset>0x00000148</addressOffset>
+                <description>DMA Channel 5 Transfer Count</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CH5_TRANS_COUNT</name>
+                        <description>Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).
+
+                            When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.
+
+                            Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.
+
+                            The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD.</description>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH5_CTRL_TRIG</name>
+                <addressOffset>0x0000014c</addressOffset>
+                <description>DMA Channel 5 Control and Status</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>AHB_ERROR</name>
+                        <description>Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag.</description>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>READ_ERROR</name>
+                        <description>If 1, the channel received a read bus error. Write one to clear. 
+                            READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)</description>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>WRITE_ERROR</name>
+                        <description>If 1, the channel received a write bus error. Write one to clear. 
+                            WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)</description>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>BUSY</name>
+                        <description>This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.
+
+                            To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT.</description>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SNIFF_EN</name>
+                        <description>If 1, this channel&#39;s data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.
+
+                            This allows checksum to be enabled or disabled on a per-control- block basis.</description>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>BSWAP</name>
+                        <description>Apply byte-swap transformation to DMA data. 
+                            For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.</description>
+                        <bitRange>[22:22]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>IRQ_QUIET</name>
+                        <description>In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.
+
+                            This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.</description>
+                        <bitRange>[21:21]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>TREQ_SEL</name>
+                        <description>Select a Transfer Request signal. 
+                            The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). 
+                            0x0 to 0x3a -&gt; select DREQ n as TREQ</description>
+                        <bitRange>[20:15]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>PIO0_TX0</name>
+                                <value>0</value>
+                                <description>Select PIO0&#39;s TX FIFO 0 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO0_TX1</name>
+                                <value>1</value>
+                                <description>Select PIO0&#39;s TX FIFO 1 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO0_TX2</name>
+                                <value>2</value>
+                                <description>Select PIO0&#39;s TX FIFO 2 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO0_TX3</name>
+                                <value>3</value>
+                                <description>Select PIO0&#39;s TX FIFO 3 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO0_RX0</name>
+                                <value>4</value>
+                                <description>Select PIO0&#39;s RX FIFO 0 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO0_RX1</name>
+                                <value>5</value>
+                                <description>Select PIO0&#39;s RX FIFO 1 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO0_RX2</name>
+                                <value>6</value>
+                                <description>Select PIO0&#39;s RX FIFO 2 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO0_RX3</name>
+                                <value>7</value>
+                                <description>Select PIO0&#39;s RX FIFO 3 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_TX0</name>
+                                <value>8</value>
+                                <description>Select PIO1&#39;s TX FIFO 0 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_TX1</name>
+                                <value>9</value>
+                                <description>Select PIO1&#39;s TX FIFO 1 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_TX2</name>
+                                <value>10</value>
+                                <description>Select PIO1&#39;s TX FIFO 2 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_TX3</name>
+                                <value>11</value>
+                                <description>Select PIO1&#39;s TX FIFO 3 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_RX0</name>
+                                <value>12</value>
+                                <description>Select PIO1&#39;s RX FIFO 0 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_RX1</name>
+                                <value>13</value>
+                                <description>Select PIO1&#39;s RX FIFO 1 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_RX2</name>
+                                <value>14</value>
+                                <description>Select PIO1&#39;s RX FIFO 2 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_RX3</name>
+                                <value>15</value>
+                                <description>Select PIO1&#39;s RX FIFO 3 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SPI0_TX</name>
+                                <value>16</value>
+                                <description>Select SPI0&#39;s TX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SPI0_RX</name>
+                                <value>17</value>
+                                <description>Select SPI0&#39;s RX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SPI1_TX</name>
+                                <value>18</value>
+                                <description>Select SPI1&#39;s TX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SPI1_RX</name>
+                                <value>19</value>
+                                <description>Select SPI1&#39;s RX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UART0_TX</name>
+                                <value>20</value>
+                                <description>Select UART0&#39;s TX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UART0_RX</name>
+                                <value>21</value>
+                                <description>Select UART0&#39;s RX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UART1_TX</name>
+                                <value>22</value>
+                                <description>Select UART1&#39;s TX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UART1_RX</name>
+                                <value>23</value>
+                                <description>Select UART1&#39;s RX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP0</name>
+                                <value>24</value>
+                                <description>Select PWM Counter 0&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP1</name>
+                                <value>25</value>
+                                <description>Select PWM Counter 1&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP2</name>
+                                <value>26</value>
+                                <description>Select PWM Counter 2&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP3</name>
+                                <value>27</value>
+                                <description>Select PWM Counter 3&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP4</name>
+                                <value>28</value>
+                                <description>Select PWM Counter 4&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP5</name>
+                                <value>29</value>
+                                <description>Select PWM Counter 5&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP6</name>
+                                <value>30</value>
+                                <description>Select PWM Counter 6&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP7</name>
+                                <value>31</value>
+                                <description>Select PWM Counter 7&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>I2C0_TX</name>
+                                <value>32</value>
+                                <description>Select I2C0&#39;s TX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>I2C0_RX</name>
+                                <value>33</value>
+                                <description>Select I2C0&#39;s RX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>I2C1_TX</name>
+                                <value>34</value>
+                                <description>Select I2C1&#39;s TX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>I2C1_RX</name>
+                                <value>35</value>
+                                <description>Select I2C1&#39;s RX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC</name>
+                                <value>36</value>
+                                <description>Select the ADC as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>XIP_STREAM</name>
+                                <value>37</value>
+                                <description>Select the XIP Streaming FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>XIP_SSITX</name>
+                                <value>38</value>
+                                <description>Select the XIP SSI TX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>XIP_SSIRX</name>
+                                <value>39</value>
+                                <description>Select the XIP SSI RX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TIMER0</name>
+                                <value>59</value>
+                                <description>Select Timer 0 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TIMER1</name>
+                                <value>60</value>
+                                <description>Select Timer 1 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TIMER2</name>
+                                <value>61</value>
+                                <description>Select Timer 2 as TREQ (Optional)</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TIMER3</name>
+                                <value>62</value>
+                                <description>Select Timer 3 as TREQ (Optional)</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PERMANENT</name>
+                                <value>63</value>
+                                <description>Permanent request, for unpaced transfers.</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>CHAIN_TO</name>
+                        <description>When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.</description>
+                        <bitRange>[14:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>RING_SEL</name>
+                        <description>Select whether RING_SIZE applies to read or write addresses. 
+                            If 0, read addresses are wrapped on a (1 &lt;&lt; RING_SIZE) boundary. If 1, write addresses are wrapped.</description>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>RING_SIZE</name>
+                        <description>Size of address wrap region. If 0, don&#39;t wrap. For values n &gt; 0, only the lower n bits of the address will change. This wraps the address on a (1 &lt;&lt; n) byte boundary, facilitating access to naturally-aligned ring buffers.
+
+                            Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.</description>
+                        <bitRange>[9:6]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>RING_NONE</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>INCR_WRITE</name>
+                        <description>If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.
+
+                            Generally this should be disabled for memory-to-peripheral transfers.</description>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INCR_READ</name>
+                        <description>If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.
+
+                            Generally this should be disabled for peripheral-to-memory transfers.</description>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DATA_SIZE</name>
+                        <description>Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.</description>
+                        <bitRange>[3:2]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>SIZE_BYTE</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SIZE_HALFWORD</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SIZE_WORD</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>HIGH_PRIORITY</name>
+                        <description>HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.
+
+                            This only affects the order in which the DMA schedules channels. The DMA&#39;s bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>EN</name>
+                        <description>DMA Channel Enable. 
+                            When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH5_AL1_CTRL</name>
+                <addressOffset>0x00000150</addressOffset>
+                <description>Alias for channel 5 CTRL register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH5_AL1_CTRL</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH5_AL1_READ_ADDR</name>
+                <addressOffset>0x00000154</addressOffset>
+                <description>Alias for channel 5 READ_ADDR register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH5_AL1_READ_ADDR</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH5_AL1_WRITE_ADDR</name>
+                <addressOffset>0x00000158</addressOffset>
+                <description>Alias for channel 5 WRITE_ADDR register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH5_AL1_WRITE_ADDR</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH5_AL1_TRANS_COUNT_TRIG</name>
+                <addressOffset>0x0000015c</addressOffset>
+                <description>Alias for channel 5 TRANS_COUNT register 
+                    This is a trigger register (0xc). Writing a nonzero value will 
+                    reload the channel counter and start the channel.</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH5_AL1_TRANS_COUNT_TRIG</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH5_AL2_CTRL</name>
+                <addressOffset>0x00000160</addressOffset>
+                <description>Alias for channel 5 CTRL register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH5_AL2_CTRL</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH5_AL2_TRANS_COUNT</name>
+                <addressOffset>0x00000164</addressOffset>
+                <description>Alias for channel 5 TRANS_COUNT register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH5_AL2_TRANS_COUNT</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH5_AL2_READ_ADDR</name>
+                <addressOffset>0x00000168</addressOffset>
+                <description>Alias for channel 5 READ_ADDR register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH5_AL2_READ_ADDR</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH5_AL2_WRITE_ADDR_TRIG</name>
+                <addressOffset>0x0000016c</addressOffset>
+                <description>Alias for channel 5 WRITE_ADDR register 
+                    This is a trigger register (0xc). Writing a nonzero value will 
+                    reload the channel counter and start the channel.</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH5_AL2_WRITE_ADDR_TRIG</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH5_AL3_CTRL</name>
+                <addressOffset>0x00000170</addressOffset>
+                <description>Alias for channel 5 CTRL register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH5_AL3_CTRL</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH5_AL3_WRITE_ADDR</name>
+                <addressOffset>0x00000174</addressOffset>
+                <description>Alias for channel 5 WRITE_ADDR register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH5_AL3_WRITE_ADDR</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH5_AL3_TRANS_COUNT</name>
+                <addressOffset>0x00000178</addressOffset>
+                <description>Alias for channel 5 TRANS_COUNT register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH5_AL3_TRANS_COUNT</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH5_AL3_READ_ADDR_TRIG</name>
+                <addressOffset>0x0000017c</addressOffset>
+                <description>Alias for channel 5 READ_ADDR register 
+                    This is a trigger register (0xc). Writing a nonzero value will 
+                    reload the channel counter and start the channel.</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH5_AL3_READ_ADDR_TRIG</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH6_READ_ADDR</name>
+                <addressOffset>0x00000180</addressOffset>
+                <description>DMA Channel 6 Read Address pointer</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CH6_READ_ADDR</name>
+                        <description>This register updates automatically each time a read completes. The current value is the next address to be read by this channel.</description>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH6_WRITE_ADDR</name>
+                <addressOffset>0x00000184</addressOffset>
+                <description>DMA Channel 6 Write Address pointer</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CH6_WRITE_ADDR</name>
+                        <description>This register updates automatically each time a write completes. The current value is the next address to be written by this channel.</description>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH6_TRANS_COUNT</name>
+                <addressOffset>0x00000188</addressOffset>
+                <description>DMA Channel 6 Transfer Count</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CH6_TRANS_COUNT</name>
+                        <description>Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).
+
+                            When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.
+
+                            Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.
+
+                            The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD.</description>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH6_CTRL_TRIG</name>
+                <addressOffset>0x0000018c</addressOffset>
+                <description>DMA Channel 6 Control and Status</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>AHB_ERROR</name>
+                        <description>Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag.</description>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>READ_ERROR</name>
+                        <description>If 1, the channel received a read bus error. Write one to clear. 
+                            READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)</description>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>WRITE_ERROR</name>
+                        <description>If 1, the channel received a write bus error. Write one to clear. 
+                            WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)</description>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>BUSY</name>
+                        <description>This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.
+
+                            To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT.</description>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SNIFF_EN</name>
+                        <description>If 1, this channel&#39;s data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.
+
+                            This allows checksum to be enabled or disabled on a per-control- block basis.</description>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>BSWAP</name>
+                        <description>Apply byte-swap transformation to DMA data. 
+                            For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.</description>
+                        <bitRange>[22:22]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>IRQ_QUIET</name>
+                        <description>In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.
+
+                            This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.</description>
+                        <bitRange>[21:21]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>TREQ_SEL</name>
+                        <description>Select a Transfer Request signal. 
+                            The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). 
+                            0x0 to 0x3a -&gt; select DREQ n as TREQ</description>
+                        <bitRange>[20:15]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>PIO0_TX0</name>
+                                <value>0</value>
+                                <description>Select PIO0&#39;s TX FIFO 0 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO0_TX1</name>
+                                <value>1</value>
+                                <description>Select PIO0&#39;s TX FIFO 1 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO0_TX2</name>
+                                <value>2</value>
+                                <description>Select PIO0&#39;s TX FIFO 2 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO0_TX3</name>
+                                <value>3</value>
+                                <description>Select PIO0&#39;s TX FIFO 3 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO0_RX0</name>
+                                <value>4</value>
+                                <description>Select PIO0&#39;s RX FIFO 0 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO0_RX1</name>
+                                <value>5</value>
+                                <description>Select PIO0&#39;s RX FIFO 1 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO0_RX2</name>
+                                <value>6</value>
+                                <description>Select PIO0&#39;s RX FIFO 2 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO0_RX3</name>
+                                <value>7</value>
+                                <description>Select PIO0&#39;s RX FIFO 3 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_TX0</name>
+                                <value>8</value>
+                                <description>Select PIO1&#39;s TX FIFO 0 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_TX1</name>
+                                <value>9</value>
+                                <description>Select PIO1&#39;s TX FIFO 1 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_TX2</name>
+                                <value>10</value>
+                                <description>Select PIO1&#39;s TX FIFO 2 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_TX3</name>
+                                <value>11</value>
+                                <description>Select PIO1&#39;s TX FIFO 3 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_RX0</name>
+                                <value>12</value>
+                                <description>Select PIO1&#39;s RX FIFO 0 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_RX1</name>
+                                <value>13</value>
+                                <description>Select PIO1&#39;s RX FIFO 1 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_RX2</name>
+                                <value>14</value>
+                                <description>Select PIO1&#39;s RX FIFO 2 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_RX3</name>
+                                <value>15</value>
+                                <description>Select PIO1&#39;s RX FIFO 3 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SPI0_TX</name>
+                                <value>16</value>
+                                <description>Select SPI0&#39;s TX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SPI0_RX</name>
+                                <value>17</value>
+                                <description>Select SPI0&#39;s RX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SPI1_TX</name>
+                                <value>18</value>
+                                <description>Select SPI1&#39;s TX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SPI1_RX</name>
+                                <value>19</value>
+                                <description>Select SPI1&#39;s RX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UART0_TX</name>
+                                <value>20</value>
+                                <description>Select UART0&#39;s TX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UART0_RX</name>
+                                <value>21</value>
+                                <description>Select UART0&#39;s RX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UART1_TX</name>
+                                <value>22</value>
+                                <description>Select UART1&#39;s TX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UART1_RX</name>
+                                <value>23</value>
+                                <description>Select UART1&#39;s RX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP0</name>
+                                <value>24</value>
+                                <description>Select PWM Counter 0&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP1</name>
+                                <value>25</value>
+                                <description>Select PWM Counter 1&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP2</name>
+                                <value>26</value>
+                                <description>Select PWM Counter 2&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP3</name>
+                                <value>27</value>
+                                <description>Select PWM Counter 3&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP4</name>
+                                <value>28</value>
+                                <description>Select PWM Counter 4&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP5</name>
+                                <value>29</value>
+                                <description>Select PWM Counter 5&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP6</name>
+                                <value>30</value>
+                                <description>Select PWM Counter 6&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP7</name>
+                                <value>31</value>
+                                <description>Select PWM Counter 7&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>I2C0_TX</name>
+                                <value>32</value>
+                                <description>Select I2C0&#39;s TX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>I2C0_RX</name>
+                                <value>33</value>
+                                <description>Select I2C0&#39;s RX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>I2C1_TX</name>
+                                <value>34</value>
+                                <description>Select I2C1&#39;s TX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>I2C1_RX</name>
+                                <value>35</value>
+                                <description>Select I2C1&#39;s RX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC</name>
+                                <value>36</value>
+                                <description>Select the ADC as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>XIP_STREAM</name>
+                                <value>37</value>
+                                <description>Select the XIP Streaming FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>XIP_SSITX</name>
+                                <value>38</value>
+                                <description>Select the XIP SSI TX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>XIP_SSIRX</name>
+                                <value>39</value>
+                                <description>Select the XIP SSI RX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TIMER0</name>
+                                <value>59</value>
+                                <description>Select Timer 0 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TIMER1</name>
+                                <value>60</value>
+                                <description>Select Timer 1 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TIMER2</name>
+                                <value>61</value>
+                                <description>Select Timer 2 as TREQ (Optional)</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TIMER3</name>
+                                <value>62</value>
+                                <description>Select Timer 3 as TREQ (Optional)</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PERMANENT</name>
+                                <value>63</value>
+                                <description>Permanent request, for unpaced transfers.</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>CHAIN_TO</name>
+                        <description>When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.</description>
+                        <bitRange>[14:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>RING_SEL</name>
+                        <description>Select whether RING_SIZE applies to read or write addresses. 
+                            If 0, read addresses are wrapped on a (1 &lt;&lt; RING_SIZE) boundary. If 1, write addresses are wrapped.</description>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>RING_SIZE</name>
+                        <description>Size of address wrap region. If 0, don&#39;t wrap. For values n &gt; 0, only the lower n bits of the address will change. This wraps the address on a (1 &lt;&lt; n) byte boundary, facilitating access to naturally-aligned ring buffers.
+
+                            Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.</description>
+                        <bitRange>[9:6]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>RING_NONE</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>INCR_WRITE</name>
+                        <description>If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.
+
+                            Generally this should be disabled for memory-to-peripheral transfers.</description>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INCR_READ</name>
+                        <description>If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.
+
+                            Generally this should be disabled for peripheral-to-memory transfers.</description>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DATA_SIZE</name>
+                        <description>Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.</description>
+                        <bitRange>[3:2]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>SIZE_BYTE</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SIZE_HALFWORD</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SIZE_WORD</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>HIGH_PRIORITY</name>
+                        <description>HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.
+
+                            This only affects the order in which the DMA schedules channels. The DMA&#39;s bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>EN</name>
+                        <description>DMA Channel Enable. 
+                            When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH6_AL1_CTRL</name>
+                <addressOffset>0x00000190</addressOffset>
+                <description>Alias for channel 6 CTRL register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH6_AL1_CTRL</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH6_AL1_READ_ADDR</name>
+                <addressOffset>0x00000194</addressOffset>
+                <description>Alias for channel 6 READ_ADDR register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH6_AL1_READ_ADDR</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH6_AL1_WRITE_ADDR</name>
+                <addressOffset>0x00000198</addressOffset>
+                <description>Alias for channel 6 WRITE_ADDR register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH6_AL1_WRITE_ADDR</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH6_AL1_TRANS_COUNT_TRIG</name>
+                <addressOffset>0x0000019c</addressOffset>
+                <description>Alias for channel 6 TRANS_COUNT register 
+                    This is a trigger register (0xc). Writing a nonzero value will 
+                    reload the channel counter and start the channel.</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH6_AL1_TRANS_COUNT_TRIG</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH6_AL2_CTRL</name>
+                <addressOffset>0x000001a0</addressOffset>
+                <description>Alias for channel 6 CTRL register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH6_AL2_CTRL</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH6_AL2_TRANS_COUNT</name>
+                <addressOffset>0x000001a4</addressOffset>
+                <description>Alias for channel 6 TRANS_COUNT register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH6_AL2_TRANS_COUNT</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH6_AL2_READ_ADDR</name>
+                <addressOffset>0x000001a8</addressOffset>
+                <description>Alias for channel 6 READ_ADDR register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH6_AL2_READ_ADDR</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH6_AL2_WRITE_ADDR_TRIG</name>
+                <addressOffset>0x000001ac</addressOffset>
+                <description>Alias for channel 6 WRITE_ADDR register 
+                    This is a trigger register (0xc). Writing a nonzero value will 
+                    reload the channel counter and start the channel.</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH6_AL2_WRITE_ADDR_TRIG</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH6_AL3_CTRL</name>
+                <addressOffset>0x000001b0</addressOffset>
+                <description>Alias for channel 6 CTRL register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH6_AL3_CTRL</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH6_AL3_WRITE_ADDR</name>
+                <addressOffset>0x000001b4</addressOffset>
+                <description>Alias for channel 6 WRITE_ADDR register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH6_AL3_WRITE_ADDR</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH6_AL3_TRANS_COUNT</name>
+                <addressOffset>0x000001b8</addressOffset>
+                <description>Alias for channel 6 TRANS_COUNT register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH6_AL3_TRANS_COUNT</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH6_AL3_READ_ADDR_TRIG</name>
+                <addressOffset>0x000001bc</addressOffset>
+                <description>Alias for channel 6 READ_ADDR register 
+                    This is a trigger register (0xc). Writing a nonzero value will 
+                    reload the channel counter and start the channel.</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH6_AL3_READ_ADDR_TRIG</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH7_READ_ADDR</name>
+                <addressOffset>0x000001c0</addressOffset>
+                <description>DMA Channel 7 Read Address pointer</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CH7_READ_ADDR</name>
+                        <description>This register updates automatically each time a read completes. The current value is the next address to be read by this channel.</description>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH7_WRITE_ADDR</name>
+                <addressOffset>0x000001c4</addressOffset>
+                <description>DMA Channel 7 Write Address pointer</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CH7_WRITE_ADDR</name>
+                        <description>This register updates automatically each time a write completes. The current value is the next address to be written by this channel.</description>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH7_TRANS_COUNT</name>
+                <addressOffset>0x000001c8</addressOffset>
+                <description>DMA Channel 7 Transfer Count</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CH7_TRANS_COUNT</name>
+                        <description>Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).
+
+                            When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.
+
+                            Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.
+
+                            The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD.</description>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH7_CTRL_TRIG</name>
+                <addressOffset>0x000001cc</addressOffset>
+                <description>DMA Channel 7 Control and Status</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>AHB_ERROR</name>
+                        <description>Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag.</description>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>READ_ERROR</name>
+                        <description>If 1, the channel received a read bus error. Write one to clear. 
+                            READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)</description>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>WRITE_ERROR</name>
+                        <description>If 1, the channel received a write bus error. Write one to clear. 
+                            WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)</description>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>BUSY</name>
+                        <description>This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.
+
+                            To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT.</description>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SNIFF_EN</name>
+                        <description>If 1, this channel&#39;s data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.
+
+                            This allows checksum to be enabled or disabled on a per-control- block basis.</description>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>BSWAP</name>
+                        <description>Apply byte-swap transformation to DMA data. 
+                            For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.</description>
+                        <bitRange>[22:22]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>IRQ_QUIET</name>
+                        <description>In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.
+
+                            This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.</description>
+                        <bitRange>[21:21]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>TREQ_SEL</name>
+                        <description>Select a Transfer Request signal. 
+                            The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). 
+                            0x0 to 0x3a -&gt; select DREQ n as TREQ</description>
+                        <bitRange>[20:15]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>PIO0_TX0</name>
+                                <value>0</value>
+                                <description>Select PIO0&#39;s TX FIFO 0 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO0_TX1</name>
+                                <value>1</value>
+                                <description>Select PIO0&#39;s TX FIFO 1 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO0_TX2</name>
+                                <value>2</value>
+                                <description>Select PIO0&#39;s TX FIFO 2 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO0_TX3</name>
+                                <value>3</value>
+                                <description>Select PIO0&#39;s TX FIFO 3 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO0_RX0</name>
+                                <value>4</value>
+                                <description>Select PIO0&#39;s RX FIFO 0 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO0_RX1</name>
+                                <value>5</value>
+                                <description>Select PIO0&#39;s RX FIFO 1 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO0_RX2</name>
+                                <value>6</value>
+                                <description>Select PIO0&#39;s RX FIFO 2 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO0_RX3</name>
+                                <value>7</value>
+                                <description>Select PIO0&#39;s RX FIFO 3 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_TX0</name>
+                                <value>8</value>
+                                <description>Select PIO1&#39;s TX FIFO 0 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_TX1</name>
+                                <value>9</value>
+                                <description>Select PIO1&#39;s TX FIFO 1 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_TX2</name>
+                                <value>10</value>
+                                <description>Select PIO1&#39;s TX FIFO 2 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_TX3</name>
+                                <value>11</value>
+                                <description>Select PIO1&#39;s TX FIFO 3 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_RX0</name>
+                                <value>12</value>
+                                <description>Select PIO1&#39;s RX FIFO 0 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_RX1</name>
+                                <value>13</value>
+                                <description>Select PIO1&#39;s RX FIFO 1 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_RX2</name>
+                                <value>14</value>
+                                <description>Select PIO1&#39;s RX FIFO 2 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_RX3</name>
+                                <value>15</value>
+                                <description>Select PIO1&#39;s RX FIFO 3 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SPI0_TX</name>
+                                <value>16</value>
+                                <description>Select SPI0&#39;s TX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SPI0_RX</name>
+                                <value>17</value>
+                                <description>Select SPI0&#39;s RX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SPI1_TX</name>
+                                <value>18</value>
+                                <description>Select SPI1&#39;s TX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SPI1_RX</name>
+                                <value>19</value>
+                                <description>Select SPI1&#39;s RX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UART0_TX</name>
+                                <value>20</value>
+                                <description>Select UART0&#39;s TX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UART0_RX</name>
+                                <value>21</value>
+                                <description>Select UART0&#39;s RX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UART1_TX</name>
+                                <value>22</value>
+                                <description>Select UART1&#39;s TX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UART1_RX</name>
+                                <value>23</value>
+                                <description>Select UART1&#39;s RX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP0</name>
+                                <value>24</value>
+                                <description>Select PWM Counter 0&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP1</name>
+                                <value>25</value>
+                                <description>Select PWM Counter 1&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP2</name>
+                                <value>26</value>
+                                <description>Select PWM Counter 2&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP3</name>
+                                <value>27</value>
+                                <description>Select PWM Counter 3&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP4</name>
+                                <value>28</value>
+                                <description>Select PWM Counter 4&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP5</name>
+                                <value>29</value>
+                                <description>Select PWM Counter 5&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP6</name>
+                                <value>30</value>
+                                <description>Select PWM Counter 6&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP7</name>
+                                <value>31</value>
+                                <description>Select PWM Counter 7&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>I2C0_TX</name>
+                                <value>32</value>
+                                <description>Select I2C0&#39;s TX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>I2C0_RX</name>
+                                <value>33</value>
+                                <description>Select I2C0&#39;s RX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>I2C1_TX</name>
+                                <value>34</value>
+                                <description>Select I2C1&#39;s TX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>I2C1_RX</name>
+                                <value>35</value>
+                                <description>Select I2C1&#39;s RX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC</name>
+                                <value>36</value>
+                                <description>Select the ADC as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>XIP_STREAM</name>
+                                <value>37</value>
+                                <description>Select the XIP Streaming FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>XIP_SSITX</name>
+                                <value>38</value>
+                                <description>Select the XIP SSI TX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>XIP_SSIRX</name>
+                                <value>39</value>
+                                <description>Select the XIP SSI RX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TIMER0</name>
+                                <value>59</value>
+                                <description>Select Timer 0 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TIMER1</name>
+                                <value>60</value>
+                                <description>Select Timer 1 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TIMER2</name>
+                                <value>61</value>
+                                <description>Select Timer 2 as TREQ (Optional)</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TIMER3</name>
+                                <value>62</value>
+                                <description>Select Timer 3 as TREQ (Optional)</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PERMANENT</name>
+                                <value>63</value>
+                                <description>Permanent request, for unpaced transfers.</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>CHAIN_TO</name>
+                        <description>When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.</description>
+                        <bitRange>[14:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>RING_SEL</name>
+                        <description>Select whether RING_SIZE applies to read or write addresses. 
+                            If 0, read addresses are wrapped on a (1 &lt;&lt; RING_SIZE) boundary. If 1, write addresses are wrapped.</description>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>RING_SIZE</name>
+                        <description>Size of address wrap region. If 0, don&#39;t wrap. For values n &gt; 0, only the lower n bits of the address will change. This wraps the address on a (1 &lt;&lt; n) byte boundary, facilitating access to naturally-aligned ring buffers.
+
+                            Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.</description>
+                        <bitRange>[9:6]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>RING_NONE</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>INCR_WRITE</name>
+                        <description>If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.
+
+                            Generally this should be disabled for memory-to-peripheral transfers.</description>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INCR_READ</name>
+                        <description>If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.
+
+                            Generally this should be disabled for peripheral-to-memory transfers.</description>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DATA_SIZE</name>
+                        <description>Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.</description>
+                        <bitRange>[3:2]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>SIZE_BYTE</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SIZE_HALFWORD</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SIZE_WORD</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>HIGH_PRIORITY</name>
+                        <description>HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.
+
+                            This only affects the order in which the DMA schedules channels. The DMA&#39;s bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>EN</name>
+                        <description>DMA Channel Enable. 
+                            When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH7_AL1_CTRL</name>
+                <addressOffset>0x000001d0</addressOffset>
+                <description>Alias for channel 7 CTRL register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH7_AL1_CTRL</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH7_AL1_READ_ADDR</name>
+                <addressOffset>0x000001d4</addressOffset>
+                <description>Alias for channel 7 READ_ADDR register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH7_AL1_READ_ADDR</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH7_AL1_WRITE_ADDR</name>
+                <addressOffset>0x000001d8</addressOffset>
+                <description>Alias for channel 7 WRITE_ADDR register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH7_AL1_WRITE_ADDR</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH7_AL1_TRANS_COUNT_TRIG</name>
+                <addressOffset>0x000001dc</addressOffset>
+                <description>Alias for channel 7 TRANS_COUNT register 
+                    This is a trigger register (0xc). Writing a nonzero value will 
+                    reload the channel counter and start the channel.</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH7_AL1_TRANS_COUNT_TRIG</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH7_AL2_CTRL</name>
+                <addressOffset>0x000001e0</addressOffset>
+                <description>Alias for channel 7 CTRL register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH7_AL2_CTRL</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH7_AL2_TRANS_COUNT</name>
+                <addressOffset>0x000001e4</addressOffset>
+                <description>Alias for channel 7 TRANS_COUNT register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH7_AL2_TRANS_COUNT</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH7_AL2_READ_ADDR</name>
+                <addressOffset>0x000001e8</addressOffset>
+                <description>Alias for channel 7 READ_ADDR register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH7_AL2_READ_ADDR</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH7_AL2_WRITE_ADDR_TRIG</name>
+                <addressOffset>0x000001ec</addressOffset>
+                <description>Alias for channel 7 WRITE_ADDR register 
+                    This is a trigger register (0xc). Writing a nonzero value will 
+                    reload the channel counter and start the channel.</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH7_AL2_WRITE_ADDR_TRIG</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH7_AL3_CTRL</name>
+                <addressOffset>0x000001f0</addressOffset>
+                <description>Alias for channel 7 CTRL register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH7_AL3_CTRL</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH7_AL3_WRITE_ADDR</name>
+                <addressOffset>0x000001f4</addressOffset>
+                <description>Alias for channel 7 WRITE_ADDR register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH7_AL3_WRITE_ADDR</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH7_AL3_TRANS_COUNT</name>
+                <addressOffset>0x000001f8</addressOffset>
+                <description>Alias for channel 7 TRANS_COUNT register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH7_AL3_TRANS_COUNT</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH7_AL3_READ_ADDR_TRIG</name>
+                <addressOffset>0x000001fc</addressOffset>
+                <description>Alias for channel 7 READ_ADDR register 
+                    This is a trigger register (0xc). Writing a nonzero value will 
+                    reload the channel counter and start the channel.</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH7_AL3_READ_ADDR_TRIG</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH8_READ_ADDR</name>
+                <addressOffset>0x00000200</addressOffset>
+                <description>DMA Channel 8 Read Address pointer</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CH8_READ_ADDR</name>
+                        <description>This register updates automatically each time a read completes. The current value is the next address to be read by this channel.</description>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH8_WRITE_ADDR</name>
+                <addressOffset>0x00000204</addressOffset>
+                <description>DMA Channel 8 Write Address pointer</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CH8_WRITE_ADDR</name>
+                        <description>This register updates automatically each time a write completes. The current value is the next address to be written by this channel.</description>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH8_TRANS_COUNT</name>
+                <addressOffset>0x00000208</addressOffset>
+                <description>DMA Channel 8 Transfer Count</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CH8_TRANS_COUNT</name>
+                        <description>Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).
+
+                            When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.
+
+                            Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.
+
+                            The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD.</description>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH8_CTRL_TRIG</name>
+                <addressOffset>0x0000020c</addressOffset>
+                <description>DMA Channel 8 Control and Status</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>AHB_ERROR</name>
+                        <description>Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag.</description>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>READ_ERROR</name>
+                        <description>If 1, the channel received a read bus error. Write one to clear. 
+                            READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)</description>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>WRITE_ERROR</name>
+                        <description>If 1, the channel received a write bus error. Write one to clear. 
+                            WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)</description>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>BUSY</name>
+                        <description>This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.
+
+                            To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT.</description>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SNIFF_EN</name>
+                        <description>If 1, this channel&#39;s data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.
+
+                            This allows checksum to be enabled or disabled on a per-control- block basis.</description>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>BSWAP</name>
+                        <description>Apply byte-swap transformation to DMA data. 
+                            For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.</description>
+                        <bitRange>[22:22]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>IRQ_QUIET</name>
+                        <description>In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.
+
+                            This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.</description>
+                        <bitRange>[21:21]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>TREQ_SEL</name>
+                        <description>Select a Transfer Request signal. 
+                            The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). 
+                            0x0 to 0x3a -&gt; select DREQ n as TREQ</description>
+                        <bitRange>[20:15]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>PIO0_TX0</name>
+                                <value>0</value>
+                                <description>Select PIO0&#39;s TX FIFO 0 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO0_TX1</name>
+                                <value>1</value>
+                                <description>Select PIO0&#39;s TX FIFO 1 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO0_TX2</name>
+                                <value>2</value>
+                                <description>Select PIO0&#39;s TX FIFO 2 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO0_TX3</name>
+                                <value>3</value>
+                                <description>Select PIO0&#39;s TX FIFO 3 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO0_RX0</name>
+                                <value>4</value>
+                                <description>Select PIO0&#39;s RX FIFO 0 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO0_RX1</name>
+                                <value>5</value>
+                                <description>Select PIO0&#39;s RX FIFO 1 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO0_RX2</name>
+                                <value>6</value>
+                                <description>Select PIO0&#39;s RX FIFO 2 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO0_RX3</name>
+                                <value>7</value>
+                                <description>Select PIO0&#39;s RX FIFO 3 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_TX0</name>
+                                <value>8</value>
+                                <description>Select PIO1&#39;s TX FIFO 0 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_TX1</name>
+                                <value>9</value>
+                                <description>Select PIO1&#39;s TX FIFO 1 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_TX2</name>
+                                <value>10</value>
+                                <description>Select PIO1&#39;s TX FIFO 2 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_TX3</name>
+                                <value>11</value>
+                                <description>Select PIO1&#39;s TX FIFO 3 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_RX0</name>
+                                <value>12</value>
+                                <description>Select PIO1&#39;s RX FIFO 0 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_RX1</name>
+                                <value>13</value>
+                                <description>Select PIO1&#39;s RX FIFO 1 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_RX2</name>
+                                <value>14</value>
+                                <description>Select PIO1&#39;s RX FIFO 2 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_RX3</name>
+                                <value>15</value>
+                                <description>Select PIO1&#39;s RX FIFO 3 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SPI0_TX</name>
+                                <value>16</value>
+                                <description>Select SPI0&#39;s TX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SPI0_RX</name>
+                                <value>17</value>
+                                <description>Select SPI0&#39;s RX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SPI1_TX</name>
+                                <value>18</value>
+                                <description>Select SPI1&#39;s TX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SPI1_RX</name>
+                                <value>19</value>
+                                <description>Select SPI1&#39;s RX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UART0_TX</name>
+                                <value>20</value>
+                                <description>Select UART0&#39;s TX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UART0_RX</name>
+                                <value>21</value>
+                                <description>Select UART0&#39;s RX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UART1_TX</name>
+                                <value>22</value>
+                                <description>Select UART1&#39;s TX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UART1_RX</name>
+                                <value>23</value>
+                                <description>Select UART1&#39;s RX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP0</name>
+                                <value>24</value>
+                                <description>Select PWM Counter 0&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP1</name>
+                                <value>25</value>
+                                <description>Select PWM Counter 1&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP2</name>
+                                <value>26</value>
+                                <description>Select PWM Counter 2&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP3</name>
+                                <value>27</value>
+                                <description>Select PWM Counter 3&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP4</name>
+                                <value>28</value>
+                                <description>Select PWM Counter 4&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP5</name>
+                                <value>29</value>
+                                <description>Select PWM Counter 5&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP6</name>
+                                <value>30</value>
+                                <description>Select PWM Counter 6&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP7</name>
+                                <value>31</value>
+                                <description>Select PWM Counter 7&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>I2C0_TX</name>
+                                <value>32</value>
+                                <description>Select I2C0&#39;s TX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>I2C0_RX</name>
+                                <value>33</value>
+                                <description>Select I2C0&#39;s RX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>I2C1_TX</name>
+                                <value>34</value>
+                                <description>Select I2C1&#39;s TX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>I2C1_RX</name>
+                                <value>35</value>
+                                <description>Select I2C1&#39;s RX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC</name>
+                                <value>36</value>
+                                <description>Select the ADC as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>XIP_STREAM</name>
+                                <value>37</value>
+                                <description>Select the XIP Streaming FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>XIP_SSITX</name>
+                                <value>38</value>
+                                <description>Select the XIP SSI TX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>XIP_SSIRX</name>
+                                <value>39</value>
+                                <description>Select the XIP SSI RX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TIMER0</name>
+                                <value>59</value>
+                                <description>Select Timer 0 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TIMER1</name>
+                                <value>60</value>
+                                <description>Select Timer 1 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TIMER2</name>
+                                <value>61</value>
+                                <description>Select Timer 2 as TREQ (Optional)</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TIMER3</name>
+                                <value>62</value>
+                                <description>Select Timer 3 as TREQ (Optional)</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PERMANENT</name>
+                                <value>63</value>
+                                <description>Permanent request, for unpaced transfers.</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>CHAIN_TO</name>
+                        <description>When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.</description>
+                        <bitRange>[14:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>RING_SEL</name>
+                        <description>Select whether RING_SIZE applies to read or write addresses. 
+                            If 0, read addresses are wrapped on a (1 &lt;&lt; RING_SIZE) boundary. If 1, write addresses are wrapped.</description>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>RING_SIZE</name>
+                        <description>Size of address wrap region. If 0, don&#39;t wrap. For values n &gt; 0, only the lower n bits of the address will change. This wraps the address on a (1 &lt;&lt; n) byte boundary, facilitating access to naturally-aligned ring buffers.
+
+                            Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.</description>
+                        <bitRange>[9:6]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>RING_NONE</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>INCR_WRITE</name>
+                        <description>If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.
+
+                            Generally this should be disabled for memory-to-peripheral transfers.</description>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INCR_READ</name>
+                        <description>If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.
+
+                            Generally this should be disabled for peripheral-to-memory transfers.</description>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DATA_SIZE</name>
+                        <description>Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.</description>
+                        <bitRange>[3:2]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>SIZE_BYTE</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SIZE_HALFWORD</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SIZE_WORD</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>HIGH_PRIORITY</name>
+                        <description>HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.
+
+                            This only affects the order in which the DMA schedules channels. The DMA&#39;s bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>EN</name>
+                        <description>DMA Channel Enable. 
+                            When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH8_AL1_CTRL</name>
+                <addressOffset>0x00000210</addressOffset>
+                <description>Alias for channel 8 CTRL register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH8_AL1_CTRL</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH8_AL1_READ_ADDR</name>
+                <addressOffset>0x00000214</addressOffset>
+                <description>Alias for channel 8 READ_ADDR register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH8_AL1_READ_ADDR</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH8_AL1_WRITE_ADDR</name>
+                <addressOffset>0x00000218</addressOffset>
+                <description>Alias for channel 8 WRITE_ADDR register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH8_AL1_WRITE_ADDR</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH8_AL1_TRANS_COUNT_TRIG</name>
+                <addressOffset>0x0000021c</addressOffset>
+                <description>Alias for channel 8 TRANS_COUNT register 
+                    This is a trigger register (0xc). Writing a nonzero value will 
+                    reload the channel counter and start the channel.</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH8_AL1_TRANS_COUNT_TRIG</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH8_AL2_CTRL</name>
+                <addressOffset>0x00000220</addressOffset>
+                <description>Alias for channel 8 CTRL register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH8_AL2_CTRL</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH8_AL2_TRANS_COUNT</name>
+                <addressOffset>0x00000224</addressOffset>
+                <description>Alias for channel 8 TRANS_COUNT register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH8_AL2_TRANS_COUNT</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH8_AL2_READ_ADDR</name>
+                <addressOffset>0x00000228</addressOffset>
+                <description>Alias for channel 8 READ_ADDR register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH8_AL2_READ_ADDR</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH8_AL2_WRITE_ADDR_TRIG</name>
+                <addressOffset>0x0000022c</addressOffset>
+                <description>Alias for channel 8 WRITE_ADDR register 
+                    This is a trigger register (0xc). Writing a nonzero value will 
+                    reload the channel counter and start the channel.</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH8_AL2_WRITE_ADDR_TRIG</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH8_AL3_CTRL</name>
+                <addressOffset>0x00000230</addressOffset>
+                <description>Alias for channel 8 CTRL register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH8_AL3_CTRL</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH8_AL3_WRITE_ADDR</name>
+                <addressOffset>0x00000234</addressOffset>
+                <description>Alias for channel 8 WRITE_ADDR register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH8_AL3_WRITE_ADDR</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH8_AL3_TRANS_COUNT</name>
+                <addressOffset>0x00000238</addressOffset>
+                <description>Alias for channel 8 TRANS_COUNT register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH8_AL3_TRANS_COUNT</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH8_AL3_READ_ADDR_TRIG</name>
+                <addressOffset>0x0000023c</addressOffset>
+                <description>Alias for channel 8 READ_ADDR register 
+                    This is a trigger register (0xc). Writing a nonzero value will 
+                    reload the channel counter and start the channel.</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH8_AL3_READ_ADDR_TRIG</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH9_READ_ADDR</name>
+                <addressOffset>0x00000240</addressOffset>
+                <description>DMA Channel 9 Read Address pointer</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CH9_READ_ADDR</name>
+                        <description>This register updates automatically each time a read completes. The current value is the next address to be read by this channel.</description>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH9_WRITE_ADDR</name>
+                <addressOffset>0x00000244</addressOffset>
+                <description>DMA Channel 9 Write Address pointer</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CH9_WRITE_ADDR</name>
+                        <description>This register updates automatically each time a write completes. The current value is the next address to be written by this channel.</description>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH9_TRANS_COUNT</name>
+                <addressOffset>0x00000248</addressOffset>
+                <description>DMA Channel 9 Transfer Count</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CH9_TRANS_COUNT</name>
+                        <description>Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).
+
+                            When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.
+
+                            Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.
+
+                            The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD.</description>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH9_CTRL_TRIG</name>
+                <addressOffset>0x0000024c</addressOffset>
+                <description>DMA Channel 9 Control and Status</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>AHB_ERROR</name>
+                        <description>Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag.</description>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>READ_ERROR</name>
+                        <description>If 1, the channel received a read bus error. Write one to clear. 
+                            READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)</description>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>WRITE_ERROR</name>
+                        <description>If 1, the channel received a write bus error. Write one to clear. 
+                            WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)</description>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>BUSY</name>
+                        <description>This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.
+
+                            To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT.</description>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SNIFF_EN</name>
+                        <description>If 1, this channel&#39;s data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.
+
+                            This allows checksum to be enabled or disabled on a per-control- block basis.</description>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>BSWAP</name>
+                        <description>Apply byte-swap transformation to DMA data. 
+                            For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.</description>
+                        <bitRange>[22:22]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>IRQ_QUIET</name>
+                        <description>In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.
+
+                            This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.</description>
+                        <bitRange>[21:21]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>TREQ_SEL</name>
+                        <description>Select a Transfer Request signal. 
+                            The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). 
+                            0x0 to 0x3a -&gt; select DREQ n as TREQ</description>
+                        <bitRange>[20:15]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>PIO0_TX0</name>
+                                <value>0</value>
+                                <description>Select PIO0&#39;s TX FIFO 0 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO0_TX1</name>
+                                <value>1</value>
+                                <description>Select PIO0&#39;s TX FIFO 1 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO0_TX2</name>
+                                <value>2</value>
+                                <description>Select PIO0&#39;s TX FIFO 2 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO0_TX3</name>
+                                <value>3</value>
+                                <description>Select PIO0&#39;s TX FIFO 3 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO0_RX0</name>
+                                <value>4</value>
+                                <description>Select PIO0&#39;s RX FIFO 0 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO0_RX1</name>
+                                <value>5</value>
+                                <description>Select PIO0&#39;s RX FIFO 1 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO0_RX2</name>
+                                <value>6</value>
+                                <description>Select PIO0&#39;s RX FIFO 2 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO0_RX3</name>
+                                <value>7</value>
+                                <description>Select PIO0&#39;s RX FIFO 3 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_TX0</name>
+                                <value>8</value>
+                                <description>Select PIO1&#39;s TX FIFO 0 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_TX1</name>
+                                <value>9</value>
+                                <description>Select PIO1&#39;s TX FIFO 1 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_TX2</name>
+                                <value>10</value>
+                                <description>Select PIO1&#39;s TX FIFO 2 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_TX3</name>
+                                <value>11</value>
+                                <description>Select PIO1&#39;s TX FIFO 3 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_RX0</name>
+                                <value>12</value>
+                                <description>Select PIO1&#39;s RX FIFO 0 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_RX1</name>
+                                <value>13</value>
+                                <description>Select PIO1&#39;s RX FIFO 1 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_RX2</name>
+                                <value>14</value>
+                                <description>Select PIO1&#39;s RX FIFO 2 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_RX3</name>
+                                <value>15</value>
+                                <description>Select PIO1&#39;s RX FIFO 3 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SPI0_TX</name>
+                                <value>16</value>
+                                <description>Select SPI0&#39;s TX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SPI0_RX</name>
+                                <value>17</value>
+                                <description>Select SPI0&#39;s RX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SPI1_TX</name>
+                                <value>18</value>
+                                <description>Select SPI1&#39;s TX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SPI1_RX</name>
+                                <value>19</value>
+                                <description>Select SPI1&#39;s RX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UART0_TX</name>
+                                <value>20</value>
+                                <description>Select UART0&#39;s TX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UART0_RX</name>
+                                <value>21</value>
+                                <description>Select UART0&#39;s RX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UART1_TX</name>
+                                <value>22</value>
+                                <description>Select UART1&#39;s TX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UART1_RX</name>
+                                <value>23</value>
+                                <description>Select UART1&#39;s RX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP0</name>
+                                <value>24</value>
+                                <description>Select PWM Counter 0&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP1</name>
+                                <value>25</value>
+                                <description>Select PWM Counter 1&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP2</name>
+                                <value>26</value>
+                                <description>Select PWM Counter 2&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP3</name>
+                                <value>27</value>
+                                <description>Select PWM Counter 3&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP4</name>
+                                <value>28</value>
+                                <description>Select PWM Counter 4&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP5</name>
+                                <value>29</value>
+                                <description>Select PWM Counter 5&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP6</name>
+                                <value>30</value>
+                                <description>Select PWM Counter 6&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP7</name>
+                                <value>31</value>
+                                <description>Select PWM Counter 7&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>I2C0_TX</name>
+                                <value>32</value>
+                                <description>Select I2C0&#39;s TX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>I2C0_RX</name>
+                                <value>33</value>
+                                <description>Select I2C0&#39;s RX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>I2C1_TX</name>
+                                <value>34</value>
+                                <description>Select I2C1&#39;s TX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>I2C1_RX</name>
+                                <value>35</value>
+                                <description>Select I2C1&#39;s RX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC</name>
+                                <value>36</value>
+                                <description>Select the ADC as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>XIP_STREAM</name>
+                                <value>37</value>
+                                <description>Select the XIP Streaming FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>XIP_SSITX</name>
+                                <value>38</value>
+                                <description>Select the XIP SSI TX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>XIP_SSIRX</name>
+                                <value>39</value>
+                                <description>Select the XIP SSI RX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TIMER0</name>
+                                <value>59</value>
+                                <description>Select Timer 0 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TIMER1</name>
+                                <value>60</value>
+                                <description>Select Timer 1 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TIMER2</name>
+                                <value>61</value>
+                                <description>Select Timer 2 as TREQ (Optional)</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TIMER3</name>
+                                <value>62</value>
+                                <description>Select Timer 3 as TREQ (Optional)</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PERMANENT</name>
+                                <value>63</value>
+                                <description>Permanent request, for unpaced transfers.</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>CHAIN_TO</name>
+                        <description>When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.</description>
+                        <bitRange>[14:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>RING_SEL</name>
+                        <description>Select whether RING_SIZE applies to read or write addresses. 
+                            If 0, read addresses are wrapped on a (1 &lt;&lt; RING_SIZE) boundary. If 1, write addresses are wrapped.</description>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>RING_SIZE</name>
+                        <description>Size of address wrap region. If 0, don&#39;t wrap. For values n &gt; 0, only the lower n bits of the address will change. This wraps the address on a (1 &lt;&lt; n) byte boundary, facilitating access to naturally-aligned ring buffers.
+
+                            Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.</description>
+                        <bitRange>[9:6]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>RING_NONE</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>INCR_WRITE</name>
+                        <description>If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.
+
+                            Generally this should be disabled for memory-to-peripheral transfers.</description>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INCR_READ</name>
+                        <description>If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.
+
+                            Generally this should be disabled for peripheral-to-memory transfers.</description>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DATA_SIZE</name>
+                        <description>Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.</description>
+                        <bitRange>[3:2]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>SIZE_BYTE</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SIZE_HALFWORD</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SIZE_WORD</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>HIGH_PRIORITY</name>
+                        <description>HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.
+
+                            This only affects the order in which the DMA schedules channels. The DMA&#39;s bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>EN</name>
+                        <description>DMA Channel Enable. 
+                            When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH9_AL1_CTRL</name>
+                <addressOffset>0x00000250</addressOffset>
+                <description>Alias for channel 9 CTRL register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH9_AL1_CTRL</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH9_AL1_READ_ADDR</name>
+                <addressOffset>0x00000254</addressOffset>
+                <description>Alias for channel 9 READ_ADDR register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH9_AL1_READ_ADDR</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH9_AL1_WRITE_ADDR</name>
+                <addressOffset>0x00000258</addressOffset>
+                <description>Alias for channel 9 WRITE_ADDR register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH9_AL1_WRITE_ADDR</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH9_AL1_TRANS_COUNT_TRIG</name>
+                <addressOffset>0x0000025c</addressOffset>
+                <description>Alias for channel 9 TRANS_COUNT register 
+                    This is a trigger register (0xc). Writing a nonzero value will 
+                    reload the channel counter and start the channel.</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH9_AL1_TRANS_COUNT_TRIG</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH9_AL2_CTRL</name>
+                <addressOffset>0x00000260</addressOffset>
+                <description>Alias for channel 9 CTRL register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH9_AL2_CTRL</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH9_AL2_TRANS_COUNT</name>
+                <addressOffset>0x00000264</addressOffset>
+                <description>Alias for channel 9 TRANS_COUNT register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH9_AL2_TRANS_COUNT</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH9_AL2_READ_ADDR</name>
+                <addressOffset>0x00000268</addressOffset>
+                <description>Alias for channel 9 READ_ADDR register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH9_AL2_READ_ADDR</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH9_AL2_WRITE_ADDR_TRIG</name>
+                <addressOffset>0x0000026c</addressOffset>
+                <description>Alias for channel 9 WRITE_ADDR register 
+                    This is a trigger register (0xc). Writing a nonzero value will 
+                    reload the channel counter and start the channel.</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH9_AL2_WRITE_ADDR_TRIG</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH9_AL3_CTRL</name>
+                <addressOffset>0x00000270</addressOffset>
+                <description>Alias for channel 9 CTRL register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH9_AL3_CTRL</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH9_AL3_WRITE_ADDR</name>
+                <addressOffset>0x00000274</addressOffset>
+                <description>Alias for channel 9 WRITE_ADDR register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH9_AL3_WRITE_ADDR</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH9_AL3_TRANS_COUNT</name>
+                <addressOffset>0x00000278</addressOffset>
+                <description>Alias for channel 9 TRANS_COUNT register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH9_AL3_TRANS_COUNT</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH9_AL3_READ_ADDR_TRIG</name>
+                <addressOffset>0x0000027c</addressOffset>
+                <description>Alias for channel 9 READ_ADDR register 
+                    This is a trigger register (0xc). Writing a nonzero value will 
+                    reload the channel counter and start the channel.</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH9_AL3_READ_ADDR_TRIG</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH10_READ_ADDR</name>
+                <addressOffset>0x00000280</addressOffset>
+                <description>DMA Channel 10 Read Address pointer</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CH10_READ_ADDR</name>
+                        <description>This register updates automatically each time a read completes. The current value is the next address to be read by this channel.</description>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH10_WRITE_ADDR</name>
+                <addressOffset>0x00000284</addressOffset>
+                <description>DMA Channel 10 Write Address pointer</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CH10_WRITE_ADDR</name>
+                        <description>This register updates automatically each time a write completes. The current value is the next address to be written by this channel.</description>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH10_TRANS_COUNT</name>
+                <addressOffset>0x00000288</addressOffset>
+                <description>DMA Channel 10 Transfer Count</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CH10_TRANS_COUNT</name>
+                        <description>Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).
+
+                            When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.
+
+                            Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.
+
+                            The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD.</description>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH10_CTRL_TRIG</name>
+                <addressOffset>0x0000028c</addressOffset>
+                <description>DMA Channel 10 Control and Status</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>AHB_ERROR</name>
+                        <description>Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag.</description>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>READ_ERROR</name>
+                        <description>If 1, the channel received a read bus error. Write one to clear. 
+                            READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)</description>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>WRITE_ERROR</name>
+                        <description>If 1, the channel received a write bus error. Write one to clear. 
+                            WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)</description>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>BUSY</name>
+                        <description>This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.
+
+                            To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT.</description>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SNIFF_EN</name>
+                        <description>If 1, this channel&#39;s data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.
+
+                            This allows checksum to be enabled or disabled on a per-control- block basis.</description>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>BSWAP</name>
+                        <description>Apply byte-swap transformation to DMA data. 
+                            For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.</description>
+                        <bitRange>[22:22]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>IRQ_QUIET</name>
+                        <description>In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.
+
+                            This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.</description>
+                        <bitRange>[21:21]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>TREQ_SEL</name>
+                        <description>Select a Transfer Request signal. 
+                            The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). 
+                            0x0 to 0x3a -&gt; select DREQ n as TREQ</description>
+                        <bitRange>[20:15]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>PIO0_TX0</name>
+                                <value>0</value>
+                                <description>Select PIO0&#39;s TX FIFO 0 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO0_TX1</name>
+                                <value>1</value>
+                                <description>Select PIO0&#39;s TX FIFO 1 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO0_TX2</name>
+                                <value>2</value>
+                                <description>Select PIO0&#39;s TX FIFO 2 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO0_TX3</name>
+                                <value>3</value>
+                                <description>Select PIO0&#39;s TX FIFO 3 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO0_RX0</name>
+                                <value>4</value>
+                                <description>Select PIO0&#39;s RX FIFO 0 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO0_RX1</name>
+                                <value>5</value>
+                                <description>Select PIO0&#39;s RX FIFO 1 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO0_RX2</name>
+                                <value>6</value>
+                                <description>Select PIO0&#39;s RX FIFO 2 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO0_RX3</name>
+                                <value>7</value>
+                                <description>Select PIO0&#39;s RX FIFO 3 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_TX0</name>
+                                <value>8</value>
+                                <description>Select PIO1&#39;s TX FIFO 0 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_TX1</name>
+                                <value>9</value>
+                                <description>Select PIO1&#39;s TX FIFO 1 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_TX2</name>
+                                <value>10</value>
+                                <description>Select PIO1&#39;s TX FIFO 2 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_TX3</name>
+                                <value>11</value>
+                                <description>Select PIO1&#39;s TX FIFO 3 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_RX0</name>
+                                <value>12</value>
+                                <description>Select PIO1&#39;s RX FIFO 0 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_RX1</name>
+                                <value>13</value>
+                                <description>Select PIO1&#39;s RX FIFO 1 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_RX2</name>
+                                <value>14</value>
+                                <description>Select PIO1&#39;s RX FIFO 2 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_RX3</name>
+                                <value>15</value>
+                                <description>Select PIO1&#39;s RX FIFO 3 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SPI0_TX</name>
+                                <value>16</value>
+                                <description>Select SPI0&#39;s TX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SPI0_RX</name>
+                                <value>17</value>
+                                <description>Select SPI0&#39;s RX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SPI1_TX</name>
+                                <value>18</value>
+                                <description>Select SPI1&#39;s TX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SPI1_RX</name>
+                                <value>19</value>
+                                <description>Select SPI1&#39;s RX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UART0_TX</name>
+                                <value>20</value>
+                                <description>Select UART0&#39;s TX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UART0_RX</name>
+                                <value>21</value>
+                                <description>Select UART0&#39;s RX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UART1_TX</name>
+                                <value>22</value>
+                                <description>Select UART1&#39;s TX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UART1_RX</name>
+                                <value>23</value>
+                                <description>Select UART1&#39;s RX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP0</name>
+                                <value>24</value>
+                                <description>Select PWM Counter 0&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP1</name>
+                                <value>25</value>
+                                <description>Select PWM Counter 1&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP2</name>
+                                <value>26</value>
+                                <description>Select PWM Counter 2&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP3</name>
+                                <value>27</value>
+                                <description>Select PWM Counter 3&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP4</name>
+                                <value>28</value>
+                                <description>Select PWM Counter 4&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP5</name>
+                                <value>29</value>
+                                <description>Select PWM Counter 5&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP6</name>
+                                <value>30</value>
+                                <description>Select PWM Counter 6&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP7</name>
+                                <value>31</value>
+                                <description>Select PWM Counter 7&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>I2C0_TX</name>
+                                <value>32</value>
+                                <description>Select I2C0&#39;s TX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>I2C0_RX</name>
+                                <value>33</value>
+                                <description>Select I2C0&#39;s RX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>I2C1_TX</name>
+                                <value>34</value>
+                                <description>Select I2C1&#39;s TX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>I2C1_RX</name>
+                                <value>35</value>
+                                <description>Select I2C1&#39;s RX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC</name>
+                                <value>36</value>
+                                <description>Select the ADC as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>XIP_STREAM</name>
+                                <value>37</value>
+                                <description>Select the XIP Streaming FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>XIP_SSITX</name>
+                                <value>38</value>
+                                <description>Select the XIP SSI TX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>XIP_SSIRX</name>
+                                <value>39</value>
+                                <description>Select the XIP SSI RX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TIMER0</name>
+                                <value>59</value>
+                                <description>Select Timer 0 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TIMER1</name>
+                                <value>60</value>
+                                <description>Select Timer 1 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TIMER2</name>
+                                <value>61</value>
+                                <description>Select Timer 2 as TREQ (Optional)</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TIMER3</name>
+                                <value>62</value>
+                                <description>Select Timer 3 as TREQ (Optional)</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PERMANENT</name>
+                                <value>63</value>
+                                <description>Permanent request, for unpaced transfers.</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>CHAIN_TO</name>
+                        <description>When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.</description>
+                        <bitRange>[14:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>RING_SEL</name>
+                        <description>Select whether RING_SIZE applies to read or write addresses. 
+                            If 0, read addresses are wrapped on a (1 &lt;&lt; RING_SIZE) boundary. If 1, write addresses are wrapped.</description>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>RING_SIZE</name>
+                        <description>Size of address wrap region. If 0, don&#39;t wrap. For values n &gt; 0, only the lower n bits of the address will change. This wraps the address on a (1 &lt;&lt; n) byte boundary, facilitating access to naturally-aligned ring buffers.
+
+                            Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.</description>
+                        <bitRange>[9:6]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>RING_NONE</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>INCR_WRITE</name>
+                        <description>If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.
+
+                            Generally this should be disabled for memory-to-peripheral transfers.</description>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INCR_READ</name>
+                        <description>If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.
+
+                            Generally this should be disabled for peripheral-to-memory transfers.</description>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DATA_SIZE</name>
+                        <description>Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.</description>
+                        <bitRange>[3:2]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>SIZE_BYTE</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SIZE_HALFWORD</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SIZE_WORD</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>HIGH_PRIORITY</name>
+                        <description>HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.
+
+                            This only affects the order in which the DMA schedules channels. The DMA&#39;s bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>EN</name>
+                        <description>DMA Channel Enable. 
+                            When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH10_AL1_CTRL</name>
+                <addressOffset>0x00000290</addressOffset>
+                <description>Alias for channel 10 CTRL register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH10_AL1_CTRL</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH10_AL1_READ_ADDR</name>
+                <addressOffset>0x00000294</addressOffset>
+                <description>Alias for channel 10 READ_ADDR register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH10_AL1_READ_ADDR</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH10_AL1_WRITE_ADDR</name>
+                <addressOffset>0x00000298</addressOffset>
+                <description>Alias for channel 10 WRITE_ADDR register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH10_AL1_WRITE_ADDR</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH10_AL1_TRANS_COUNT_TRIG</name>
+                <addressOffset>0x0000029c</addressOffset>
+                <description>Alias for channel 10 TRANS_COUNT register 
+                    This is a trigger register (0xc). Writing a nonzero value will 
+                    reload the channel counter and start the channel.</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH10_AL1_TRANS_COUNT_TRIG</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH10_AL2_CTRL</name>
+                <addressOffset>0x000002a0</addressOffset>
+                <description>Alias for channel 10 CTRL register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH10_AL2_CTRL</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH10_AL2_TRANS_COUNT</name>
+                <addressOffset>0x000002a4</addressOffset>
+                <description>Alias for channel 10 TRANS_COUNT register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH10_AL2_TRANS_COUNT</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH10_AL2_READ_ADDR</name>
+                <addressOffset>0x000002a8</addressOffset>
+                <description>Alias for channel 10 READ_ADDR register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH10_AL2_READ_ADDR</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH10_AL2_WRITE_ADDR_TRIG</name>
+                <addressOffset>0x000002ac</addressOffset>
+                <description>Alias for channel 10 WRITE_ADDR register 
+                    This is a trigger register (0xc). Writing a nonzero value will 
+                    reload the channel counter and start the channel.</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH10_AL2_WRITE_ADDR_TRIG</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH10_AL3_CTRL</name>
+                <addressOffset>0x000002b0</addressOffset>
+                <description>Alias for channel 10 CTRL register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH10_AL3_CTRL</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH10_AL3_WRITE_ADDR</name>
+                <addressOffset>0x000002b4</addressOffset>
+                <description>Alias for channel 10 WRITE_ADDR register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH10_AL3_WRITE_ADDR</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH10_AL3_TRANS_COUNT</name>
+                <addressOffset>0x000002b8</addressOffset>
+                <description>Alias for channel 10 TRANS_COUNT register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH10_AL3_TRANS_COUNT</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH10_AL3_READ_ADDR_TRIG</name>
+                <addressOffset>0x000002bc</addressOffset>
+                <description>Alias for channel 10 READ_ADDR register 
+                    This is a trigger register (0xc). Writing a nonzero value will 
+                    reload the channel counter and start the channel.</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH10_AL3_READ_ADDR_TRIG</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH11_READ_ADDR</name>
+                <addressOffset>0x000002c0</addressOffset>
+                <description>DMA Channel 11 Read Address pointer</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CH11_READ_ADDR</name>
+                        <description>This register updates automatically each time a read completes. The current value is the next address to be read by this channel.</description>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH11_WRITE_ADDR</name>
+                <addressOffset>0x000002c4</addressOffset>
+                <description>DMA Channel 11 Write Address pointer</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CH11_WRITE_ADDR</name>
+                        <description>This register updates automatically each time a write completes. The current value is the next address to be written by this channel.</description>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH11_TRANS_COUNT</name>
+                <addressOffset>0x000002c8</addressOffset>
+                <description>DMA Channel 11 Transfer Count</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CH11_TRANS_COUNT</name>
+                        <description>Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).
+
+                            When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.
+
+                            Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.
+
+                            The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD.</description>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH11_CTRL_TRIG</name>
+                <addressOffset>0x000002cc</addressOffset>
+                <description>DMA Channel 11 Control and Status</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>AHB_ERROR</name>
+                        <description>Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag.</description>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>READ_ERROR</name>
+                        <description>If 1, the channel received a read bus error. Write one to clear. 
+                            READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)</description>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>WRITE_ERROR</name>
+                        <description>If 1, the channel received a write bus error. Write one to clear. 
+                            WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)</description>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>BUSY</name>
+                        <description>This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.
+
+                            To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT.</description>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SNIFF_EN</name>
+                        <description>If 1, this channel&#39;s data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.
+
+                            This allows checksum to be enabled or disabled on a per-control- block basis.</description>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>BSWAP</name>
+                        <description>Apply byte-swap transformation to DMA data. 
+                            For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.</description>
+                        <bitRange>[22:22]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>IRQ_QUIET</name>
+                        <description>In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.
+
+                            This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.</description>
+                        <bitRange>[21:21]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>TREQ_SEL</name>
+                        <description>Select a Transfer Request signal. 
+                            The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). 
+                            0x0 to 0x3a -&gt; select DREQ n as TREQ</description>
+                        <bitRange>[20:15]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>PIO0_TX0</name>
+                                <value>0</value>
+                                <description>Select PIO0&#39;s TX FIFO 0 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO0_TX1</name>
+                                <value>1</value>
+                                <description>Select PIO0&#39;s TX FIFO 1 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO0_TX2</name>
+                                <value>2</value>
+                                <description>Select PIO0&#39;s TX FIFO 2 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO0_TX3</name>
+                                <value>3</value>
+                                <description>Select PIO0&#39;s TX FIFO 3 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO0_RX0</name>
+                                <value>4</value>
+                                <description>Select PIO0&#39;s RX FIFO 0 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO0_RX1</name>
+                                <value>5</value>
+                                <description>Select PIO0&#39;s RX FIFO 1 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO0_RX2</name>
+                                <value>6</value>
+                                <description>Select PIO0&#39;s RX FIFO 2 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO0_RX3</name>
+                                <value>7</value>
+                                <description>Select PIO0&#39;s RX FIFO 3 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_TX0</name>
+                                <value>8</value>
+                                <description>Select PIO1&#39;s TX FIFO 0 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_TX1</name>
+                                <value>9</value>
+                                <description>Select PIO1&#39;s TX FIFO 1 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_TX2</name>
+                                <value>10</value>
+                                <description>Select PIO1&#39;s TX FIFO 2 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_TX3</name>
+                                <value>11</value>
+                                <description>Select PIO1&#39;s TX FIFO 3 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_RX0</name>
+                                <value>12</value>
+                                <description>Select PIO1&#39;s RX FIFO 0 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_RX1</name>
+                                <value>13</value>
+                                <description>Select PIO1&#39;s RX FIFO 1 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_RX2</name>
+                                <value>14</value>
+                                <description>Select PIO1&#39;s RX FIFO 2 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_RX3</name>
+                                <value>15</value>
+                                <description>Select PIO1&#39;s RX FIFO 3 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SPI0_TX</name>
+                                <value>16</value>
+                                <description>Select SPI0&#39;s TX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SPI0_RX</name>
+                                <value>17</value>
+                                <description>Select SPI0&#39;s RX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SPI1_TX</name>
+                                <value>18</value>
+                                <description>Select SPI1&#39;s TX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SPI1_RX</name>
+                                <value>19</value>
+                                <description>Select SPI1&#39;s RX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UART0_TX</name>
+                                <value>20</value>
+                                <description>Select UART0&#39;s TX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UART0_RX</name>
+                                <value>21</value>
+                                <description>Select UART0&#39;s RX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UART1_TX</name>
+                                <value>22</value>
+                                <description>Select UART1&#39;s TX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UART1_RX</name>
+                                <value>23</value>
+                                <description>Select UART1&#39;s RX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP0</name>
+                                <value>24</value>
+                                <description>Select PWM Counter 0&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP1</name>
+                                <value>25</value>
+                                <description>Select PWM Counter 1&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP2</name>
+                                <value>26</value>
+                                <description>Select PWM Counter 2&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP3</name>
+                                <value>27</value>
+                                <description>Select PWM Counter 3&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP4</name>
+                                <value>28</value>
+                                <description>Select PWM Counter 4&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP5</name>
+                                <value>29</value>
+                                <description>Select PWM Counter 5&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP6</name>
+                                <value>30</value>
+                                <description>Select PWM Counter 6&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP7</name>
+                                <value>31</value>
+                                <description>Select PWM Counter 7&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>I2C0_TX</name>
+                                <value>32</value>
+                                <description>Select I2C0&#39;s TX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>I2C0_RX</name>
+                                <value>33</value>
+                                <description>Select I2C0&#39;s RX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>I2C1_TX</name>
+                                <value>34</value>
+                                <description>Select I2C1&#39;s TX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>I2C1_RX</name>
+                                <value>35</value>
+                                <description>Select I2C1&#39;s RX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC</name>
+                                <value>36</value>
+                                <description>Select the ADC as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>XIP_STREAM</name>
+                                <value>37</value>
+                                <description>Select the XIP Streaming FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>XIP_SSITX</name>
+                                <value>38</value>
+                                <description>Select the XIP SSI TX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>XIP_SSIRX</name>
+                                <value>39</value>
+                                <description>Select the XIP SSI RX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TIMER0</name>
+                                <value>59</value>
+                                <description>Select Timer 0 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TIMER1</name>
+                                <value>60</value>
+                                <description>Select Timer 1 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TIMER2</name>
+                                <value>61</value>
+                                <description>Select Timer 2 as TREQ (Optional)</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TIMER3</name>
+                                <value>62</value>
+                                <description>Select Timer 3 as TREQ (Optional)</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PERMANENT</name>
+                                <value>63</value>
+                                <description>Permanent request, for unpaced transfers.</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>CHAIN_TO</name>
+                        <description>When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.</description>
+                        <bitRange>[14:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>RING_SEL</name>
+                        <description>Select whether RING_SIZE applies to read or write addresses. 
+                            If 0, read addresses are wrapped on a (1 &lt;&lt; RING_SIZE) boundary. If 1, write addresses are wrapped.</description>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>RING_SIZE</name>
+                        <description>Size of address wrap region. If 0, don&#39;t wrap. For values n &gt; 0, only the lower n bits of the address will change. This wraps the address on a (1 &lt;&lt; n) byte boundary, facilitating access to naturally-aligned ring buffers.
+
+                            Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.</description>
+                        <bitRange>[9:6]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>RING_NONE</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>INCR_WRITE</name>
+                        <description>If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.
+
+                            Generally this should be disabled for memory-to-peripheral transfers.</description>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INCR_READ</name>
+                        <description>If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.
+
+                            Generally this should be disabled for peripheral-to-memory transfers.</description>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DATA_SIZE</name>
+                        <description>Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.</description>
+                        <bitRange>[3:2]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>SIZE_BYTE</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SIZE_HALFWORD</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SIZE_WORD</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>HIGH_PRIORITY</name>
+                        <description>HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.
+
+                            This only affects the order in which the DMA schedules channels. The DMA&#39;s bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>EN</name>
+                        <description>DMA Channel Enable. 
+                            When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH11_AL1_CTRL</name>
+                <addressOffset>0x000002d0</addressOffset>
+                <description>Alias for channel 11 CTRL register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH11_AL1_CTRL</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH11_AL1_READ_ADDR</name>
+                <addressOffset>0x000002d4</addressOffset>
+                <description>Alias for channel 11 READ_ADDR register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH11_AL1_READ_ADDR</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH11_AL1_WRITE_ADDR</name>
+                <addressOffset>0x000002d8</addressOffset>
+                <description>Alias for channel 11 WRITE_ADDR register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH11_AL1_WRITE_ADDR</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH11_AL1_TRANS_COUNT_TRIG</name>
+                <addressOffset>0x000002dc</addressOffset>
+                <description>Alias for channel 11 TRANS_COUNT register 
+                    This is a trigger register (0xc). Writing a nonzero value will 
+                    reload the channel counter and start the channel.</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH11_AL1_TRANS_COUNT_TRIG</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH11_AL2_CTRL</name>
+                <addressOffset>0x000002e0</addressOffset>
+                <description>Alias for channel 11 CTRL register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH11_AL2_CTRL</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH11_AL2_TRANS_COUNT</name>
+                <addressOffset>0x000002e4</addressOffset>
+                <description>Alias for channel 11 TRANS_COUNT register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH11_AL2_TRANS_COUNT</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH11_AL2_READ_ADDR</name>
+                <addressOffset>0x000002e8</addressOffset>
+                <description>Alias for channel 11 READ_ADDR register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH11_AL2_READ_ADDR</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH11_AL2_WRITE_ADDR_TRIG</name>
+                <addressOffset>0x000002ec</addressOffset>
+                <description>Alias for channel 11 WRITE_ADDR register 
+                    This is a trigger register (0xc). Writing a nonzero value will 
+                    reload the channel counter and start the channel.</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH11_AL2_WRITE_ADDR_TRIG</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH11_AL3_CTRL</name>
+                <addressOffset>0x000002f0</addressOffset>
+                <description>Alias for channel 11 CTRL register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH11_AL3_CTRL</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH11_AL3_WRITE_ADDR</name>
+                <addressOffset>0x000002f4</addressOffset>
+                <description>Alias for channel 11 WRITE_ADDR register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH11_AL3_WRITE_ADDR</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH11_AL3_TRANS_COUNT</name>
+                <addressOffset>0x000002f8</addressOffset>
+                <description>Alias for channel 11 TRANS_COUNT register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH11_AL3_TRANS_COUNT</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH11_AL3_READ_ADDR_TRIG</name>
+                <addressOffset>0x000002fc</addressOffset>
+                <description>Alias for channel 11 READ_ADDR register 
+                    This is a trigger register (0xc). Writing a nonzero value will 
+                    reload the channel counter and start the channel.</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH11_AL3_READ_ADDR_TRIG</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INTR</name>
+                <addressOffset>0x00000400</addressOffset>
+                <description>Interrupt Status (raw)</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>INTR</name>
+                        <description>Raw interrupt status for DMA Channels 0..15. Bit n corresponds to channel n. Ignores any masking or forcing. Channel interrupts can be cleared by writing a bit mask to INTR, INTS0 or INTS1.
+
+                            Channel interrupts can be routed to either of two system-level IRQs based on INTE0 and INTE1.
+
+                            This can be used vector different channel interrupts to different ISRs: this might be done to allow NVIC IRQ preemption for more time-critical channels, or to spread IRQ load across different cores.
+
+                            It is also valid to ignore this behaviour and just use INTE0/INTS0/IRQ 0.</description>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INTE0</name>
+                <addressOffset>0x00000404</addressOffset>
+                <description>Interrupt Enables for IRQ 0</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>INTE0</name>
+                        <description>Set bit n to pass interrupts from channel n to DMA IRQ 0.</description>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INTF0</name>
+                <addressOffset>0x00000408</addressOffset>
+                <description>Force Interrupts</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>INTF0</name>
+                        <description>Write 1s to force the corresponding bits in INTE0. The interrupt remains asserted until INTF0 is cleared.</description>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INTS0</name>
+                <addressOffset>0x0000040c</addressOffset>
+                <description>Interrupt Status for IRQ 0</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>INTS0</name>
+                        <description>Indicates active channel interrupt requests which are currently causing IRQ 0 to be asserted. 
+                            Channel interrupts can be cleared by writing a bit mask here.</description>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INTR1</name>
+                <addressOffset>0x00000410</addressOffset>
+                <description>Interrupt Status (raw)</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>INTR1</name>
+                        <description>Raw interrupt status for DMA Channels 0..15. Bit n corresponds to channel n. Ignores any masking or forcing. Channel interrupts can be cleared by writing a bit mask to INTR, INTS0 or INTS1.
+
+                            Channel interrupts can be routed to either of two system-level IRQs based on INTE0 and INTE1.
+
+                            This can be used vector different channel interrupts to different ISRs: this might be done to allow NVIC IRQ preemption for more time-critical channels, or to spread IRQ load across different cores.
+
+                            It is also valid to ignore this behaviour and just use INTE0/INTS0/IRQ 0.</description>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INTE1</name>
+                <addressOffset>0x00000414</addressOffset>
+                <description>Interrupt Enables for IRQ 1</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>INTE1</name>
+                        <description>Set bit n to pass interrupts from channel n to DMA IRQ 1.</description>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INTF1</name>
+                <addressOffset>0x00000418</addressOffset>
+                <description>Force Interrupts for IRQ 1</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>INTF1</name>
+                        <description>Write 1s to force the corresponding bits in INTE0. The interrupt remains asserted until INTF0 is cleared.</description>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INTS1</name>
+                <addressOffset>0x0000041c</addressOffset>
+                <description>Interrupt Status (masked) for IRQ 1</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>INTS1</name>
+                        <description>Indicates active channel interrupt requests which are currently causing IRQ 1 to be asserted. 
+                            Channel interrupts can be cleared by writing a bit mask here.</description>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>TIMER0</name>
+                <addressOffset>0x00000420</addressOffset>
+                <description>Pacing (X/Y) Fractional Timer 
+                    The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>X</name>
+                        <description>Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer.</description>
+                        <bitRange>[31:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>Y</name>
+                        <description>Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer.</description>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>TIMER1</name>
+                <addressOffset>0x00000424</addressOffset>
+                <description>Pacing (X/Y) Fractional Timer 
+                    The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>X</name>
+                        <description>Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer.</description>
+                        <bitRange>[31:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>Y</name>
+                        <description>Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer.</description>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>TIMER2</name>
+                <addressOffset>0x00000428</addressOffset>
+                <description>Pacing (X/Y) Fractional Timer 
+                    The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>X</name>
+                        <description>Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer.</description>
+                        <bitRange>[31:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>Y</name>
+                        <description>Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer.</description>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>TIMER3</name>
+                <addressOffset>0x0000042c</addressOffset>
+                <description>Pacing (X/Y) Fractional Timer 
+                    The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>X</name>
+                        <description>Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer.</description>
+                        <bitRange>[31:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>Y</name>
+                        <description>Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer.</description>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>MULTI_CHAN_TRIGGER</name>
+                <addressOffset>0x00000430</addressOffset>
+                <description>Trigger one or more channels simultaneously</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>MULTI_CHAN_TRIGGER</name>
+                        <description>Each bit in this register corresponds to a DMA channel. Writing a 1 to the relevant bit is the same as writing to that channel&#39;s trigger register; the channel will start if it is currently enabled and not already busy.</description>
+                        <bitRange>[15:0]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SNIFF_CTRL</name>
+                <addressOffset>0x00000434</addressOffset>
+                <description>Sniffer Control</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>OUT_INV</name>
+                        <description>If set, the result appears inverted (bitwise complement) when read. This does not affect the way the checksum is calculated; the result is transformed on-the-fly between the result register and the bus.</description>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>OUT_REV</name>
+                        <description>If set, the result appears bit-reversed when read. This does not affect the way the checksum is calculated; the result is transformed on-the-fly between the result register and the bus.</description>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>BSWAP</name>
+                        <description>Locally perform a byte reverse on the sniffed data, before feeding into checksum.
+
+                            Note that the sniff hardware is downstream of the DMA channel byteswap performed in the read master: if channel CTRL_BSWAP and SNIFF_CTRL_BSWAP are both enabled, their effects cancel from the sniffer&#39;s point of view.</description>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CALC</name>
+                        <bitRange>[8:5]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>CRC32</name>
+                                <value>0</value>
+                                <description>Calculate a CRC-32 (IEEE802.3 polynomial)</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CRC32R</name>
+                                <value>1</value>
+                                <description>Calculate a CRC-32 (IEEE802.3 polynomial) with bit reversed data</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CRC16</name>
+                                <value>2</value>
+                                <description>Calculate a CRC-16-CCITT</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CRC16R</name>
+                                <value>3</value>
+                                <description>Calculate a CRC-16-CCITT with bit reversed data</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>EVEN</name>
+                                <value>14</value>
+                                <description>XOR reduction over all data. == 1 if the total 1 population count is odd.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SUM</name>
+                                <value>15</value>
+                                <description>Calculate a simple 32-bit checksum (addition with a 32 bit accumulator)</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>DMACH</name>
+                        <description>DMA channel for Sniffer to observe</description>
+                        <bitRange>[4:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>EN</name>
+                        <description>Enable sniffer</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SNIFF_DATA</name>
+                <addressOffset>0x00000438</addressOffset>
+                <description>Data accumulator for sniff hardware</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>SNIFF_DATA</name>
+                        <description>Write an initial seed value here before starting a DMA transfer on the channel indicated by SNIFF_CTRL_DMACH. The hardware will update this register each time it observes a read from the indicated channel. Once the channel completes, the final result can be read from this register.</description>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>FIFO_LEVELS</name>
+                <addressOffset>0x00000440</addressOffset>
+                <description>Debug RAF, WAF, TDF levels</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>RAF_LVL</name>
+                        <description>Current Read-Address-FIFO fill level</description>
+                        <bitRange>[23:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>WAF_LVL</name>
+                        <description>Current Write-Address-FIFO fill level</description>
+                        <bitRange>[15:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>TDF_LVL</name>
+                        <description>Current Transfer-Data-FIFO fill level</description>
+                        <bitRange>[7:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CHAN_ABORT</name>
+                <addressOffset>0x00000444</addressOffset>
+                <description>Abort an in-progress transfer sequence on one or more channels</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CHAN_ABORT</name>
+                        <description>Each bit corresponds to a channel. Writing a 1 aborts whatever transfer sequence is in progress on that channel. The bit will remain high until any in-flight transfers have been flushed through the address and data FIFOs.
+
+                            After writing, this register must be polled until it returns all-zero. Until this point, it is unsafe to restart the channel.</description>
+                        <bitRange>[15:0]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>N_CHANNELS</name>
+                <addressOffset>0x00000448</addressOffset>
+                <description>The number of channels this DMA instance is equipped with. This DMA supports up to 16 hardware channels, but can be configured with as few as one, to minimise silicon area.</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>N_CHANNELS</name>
+                        <bitRange>[4:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH0_DBG_CTDREQ</name>
+                <addressOffset>0x00000800</addressOffset>
+                <description>Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CH0_DBG_CTDREQ</name>
+                        <bitRange>[5:0]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH0_DBG_TCR</name>
+                <addressOffset>0x00000804</addressOffset>
+                <description>Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CH0_DBG_TCR</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH1_DBG_CTDREQ</name>
+                <addressOffset>0x00000840</addressOffset>
+                <description>Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CH1_DBG_CTDREQ</name>
+                        <bitRange>[5:0]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH1_DBG_TCR</name>
+                <addressOffset>0x00000844</addressOffset>
+                <description>Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CH1_DBG_TCR</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH2_DBG_CTDREQ</name>
+                <addressOffset>0x00000880</addressOffset>
+                <description>Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CH2_DBG_CTDREQ</name>
+                        <bitRange>[5:0]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH2_DBG_TCR</name>
+                <addressOffset>0x00000884</addressOffset>
+                <description>Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CH2_DBG_TCR</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH3_DBG_CTDREQ</name>
+                <addressOffset>0x000008c0</addressOffset>
+                <description>Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CH3_DBG_CTDREQ</name>
+                        <bitRange>[5:0]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH3_DBG_TCR</name>
+                <addressOffset>0x000008c4</addressOffset>
+                <description>Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CH3_DBG_TCR</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH4_DBG_CTDREQ</name>
+                <addressOffset>0x00000900</addressOffset>
+                <description>Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CH4_DBG_CTDREQ</name>
+                        <bitRange>[5:0]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH4_DBG_TCR</name>
+                <addressOffset>0x00000904</addressOffset>
+                <description>Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CH4_DBG_TCR</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH5_DBG_CTDREQ</name>
+                <addressOffset>0x00000940</addressOffset>
+                <description>Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CH5_DBG_CTDREQ</name>
+                        <bitRange>[5:0]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH5_DBG_TCR</name>
+                <addressOffset>0x00000944</addressOffset>
+                <description>Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CH5_DBG_TCR</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH6_DBG_CTDREQ</name>
+                <addressOffset>0x00000980</addressOffset>
+                <description>Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CH6_DBG_CTDREQ</name>
+                        <bitRange>[5:0]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH6_DBG_TCR</name>
+                <addressOffset>0x00000984</addressOffset>
+                <description>Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CH6_DBG_TCR</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH7_DBG_CTDREQ</name>
+                <addressOffset>0x000009c0</addressOffset>
+                <description>Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CH7_DBG_CTDREQ</name>
+                        <bitRange>[5:0]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH7_DBG_TCR</name>
+                <addressOffset>0x000009c4</addressOffset>
+                <description>Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CH7_DBG_TCR</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH8_DBG_CTDREQ</name>
+                <addressOffset>0x00000a00</addressOffset>
+                <description>Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CH8_DBG_CTDREQ</name>
+                        <bitRange>[5:0]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH8_DBG_TCR</name>
+                <addressOffset>0x00000a04</addressOffset>
+                <description>Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CH8_DBG_TCR</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH9_DBG_CTDREQ</name>
+                <addressOffset>0x00000a40</addressOffset>
+                <description>Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CH9_DBG_CTDREQ</name>
+                        <bitRange>[5:0]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH9_DBG_TCR</name>
+                <addressOffset>0x00000a44</addressOffset>
+                <description>Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CH9_DBG_TCR</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH10_DBG_CTDREQ</name>
+                <addressOffset>0x00000a80</addressOffset>
+                <description>Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CH10_DBG_CTDREQ</name>
+                        <bitRange>[5:0]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH10_DBG_TCR</name>
+                <addressOffset>0x00000a84</addressOffset>
+                <description>Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CH10_DBG_TCR</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH11_DBG_CTDREQ</name>
+                <addressOffset>0x00000ac0</addressOffset>
+                <description>Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CH11_DBG_CTDREQ</name>
+                        <bitRange>[5:0]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH11_DBG_TCR</name>
+                <addressOffset>0x00000ac4</addressOffset>
+                <description>Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CH11_DBG_TCR</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+        </registers>
+    </peripheral>
+    <peripheral>
+        <name>TIMER</name>
+        <description>Controls time and alarms 
+            time is a 64 bit value indicating the time in usec since power-on 
+            timeh is the top 32 bits of time &amp; timel is the bottom 32 bits 
+            to change time write to timelw before timehw 
+            to read time read from timelr before timehr 
+            An alarm is set by setting alarm_enable and writing to the corresponding alarm register 
+            When an alarm is pending, the corresponding alarm_running signal will be high 
+            An alarm can be cancelled before it has finished by clearing the alarm_enable 
+            When an alarm fires, the corresponding alarm_irq is set and alarm_running is cleared 
+            To clear the interrupt write a 1 to the corresponding alarm_irq</description>
+        <baseAddress>0x40054000</baseAddress>
+        <addressBlock>
+            <offset>0</offset>
+            <size>68</size>
+            <usage>registers</usage>
+        </addressBlock>
+        <interrupt>
+            <name>TIMER_IRQ_0</name>
+            <value>0</value>
+        </interrupt>
+        <interrupt>
+            <name>TIMER_IRQ_1</name>
+            <value>1</value>
+        </interrupt>
+        <interrupt>
+            <name>TIMER_IRQ_2</name>
+            <value>2</value>
+        </interrupt>
+        <interrupt>
+            <name>TIMER_IRQ_3</name>
+            <value>3</value>
+        </interrupt>
+        <registers>
+            <register>
+                <name>TIMEHW</name>
+                <addressOffset>0x00000000</addressOffset>
+                <description>Write to bits 63:32 of time 
+                    always write timelw before timehw</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>TIMEHW</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>TIMELW</name>
+                <addressOffset>0x00000004</addressOffset>
+                <description>Write to bits 31:0 of time 
+                    writes do not get copied to time until timehw is written</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>TIMELW</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>TIMEHR</name>
+                <addressOffset>0x00000008</addressOffset>
+                <description>Read from bits 63:32 of time 
+                    always read timelr before timehr</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>TIMEHR</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>TIMELR</name>
+                <addressOffset>0x0000000c</addressOffset>
+                <description>Read from bits 31:0 of time</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>TIMELR</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-only</access>
+                        <readAction>modify</readAction>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>ALARM0</name>
+                <addressOffset>0x00000010</addressOffset>
+                <description>Arm alarm 0, and configure the time it will fire. 
+                    Once armed, the alarm fires when TIMER_ALARM0 == TIMELR. 
+                    The alarm will disarm itself once it fires, and can 
+                    be disarmed early using the ARMED status register.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>ALARM0</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>ALARM1</name>
+                <addressOffset>0x00000014</addressOffset>
+                <description>Arm alarm 1, and configure the time it will fire. 
+                    Once armed, the alarm fires when TIMER_ALARM1 == TIMELR. 
+                    The alarm will disarm itself once it fires, and can 
+                    be disarmed early using the ARMED status register.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>ALARM1</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>ALARM2</name>
+                <addressOffset>0x00000018</addressOffset>
+                <description>Arm alarm 2, and configure the time it will fire. 
+                    Once armed, the alarm fires when TIMER_ALARM2 == TIMELR. 
+                    The alarm will disarm itself once it fires, and can 
+                    be disarmed early using the ARMED status register.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>ALARM2</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>ALARM3</name>
+                <addressOffset>0x0000001c</addressOffset>
+                <description>Arm alarm 3, and configure the time it will fire. 
+                    Once armed, the alarm fires when TIMER_ALARM3 == TIMELR. 
+                    The alarm will disarm itself once it fires, and can 
+                    be disarmed early using the ARMED status register.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>ALARM3</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>ARMED</name>
+                <addressOffset>0x00000020</addressOffset>
+                <description>Indicates the armed/disarmed status of each alarm. 
+                    A write to the corresponding ALARMx register arms the alarm. 
+                    Alarms automatically disarm upon firing, but writing ones here 
+                    will disarm immediately without waiting to fire.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>ARMED</name>
+                        <bitRange>[3:0]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>TIMERAWH</name>
+                <addressOffset>0x00000024</addressOffset>
+                <description>Raw read from bits 63:32 of time (no side effects)</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>TIMERAWH</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>TIMERAWL</name>
+                <addressOffset>0x00000028</addressOffset>
+                <description>Raw read from bits 31:0 of time (no side effects)</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>TIMERAWL</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>DBGPAUSE</name>
+                <addressOffset>0x0000002c</addressOffset>
+                <description>Set bits high to enable pause when the corresponding debug ports are active</description>
+                <resetValue>0x00000007</resetValue>
+                <fields>
+                    <field>
+                        <name>DBG1</name>
+                        <description>Pause when processor 1 is in debug mode</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DBG0</name>
+                        <description>Pause when processor 0 is in debug mode</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PAUSE</name>
+                <addressOffset>0x00000030</addressOffset>
+                <description>Set high to pause the timer</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>PAUSE</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INTR</name>
+                <addressOffset>0x00000034</addressOffset>
+                <description>Raw Interrupts</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>ALARM_3</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>ALARM_2</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>ALARM_1</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>ALARM_0</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INTE</name>
+                <addressOffset>0x00000038</addressOffset>
+                <description>Interrupt Enable</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>ALARM_3</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ALARM_2</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ALARM_1</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ALARM_0</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INTF</name>
+                <addressOffset>0x0000003c</addressOffset>
+                <description>Interrupt Force</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>ALARM_3</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ALARM_2</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ALARM_1</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ALARM_0</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INTS</name>
+                <addressOffset>0x00000040</addressOffset>
+                <description>Interrupt status after masking &amp; forcing</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>ALARM_3</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>ALARM_2</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>ALARM_1</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>ALARM_0</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+        </registers>
+    </peripheral>
+    <peripheral>
+        <name>PWM</name>
+        <description>Simple PWM</description>
+        <baseAddress>0x40050000</baseAddress>
+        <addressBlock>
+            <offset>0</offset>
+            <size>180</size>
+            <usage>registers</usage>
+        </addressBlock>
+        <interrupt>
+            <name>PWM_IRQ_WRAP</name>
+            <value>4</value>
+        </interrupt>
+        <registers>
+            <register>
+                <name>CH0_CSR</name>
+                <addressOffset>0x00000000</addressOffset>
+                <description>Control and status register</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>PH_ADV</name>
+                        <description>Advance the phase of the counter by 1 count, while it is running. 
+                            Self-clearing. Write a 1, and poll until low. Counter must be running 
+                            at less than full speed (div_int + div_frac / 16 &gt; 1)</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>PH_RET</name>
+                        <description>Retard the phase of the counter by 1 count, while it is running. 
+                            Self-clearing. Write a 1, and poll until low. Counter must be running.</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>DIVMODE</name>
+                        <bitRange>[5:4]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>div</name>
+                                <value>0</value>
+                                <description>Free-running counting at rate dictated by fractional divider</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>level</name>
+                                <value>1</value>
+                                <description>Fractional divider operation is gated by the PWM B pin.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>rise</name>
+                                <value>2</value>
+                                <description>Counter advances with each rising edge of the PWM B pin.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>fall</name>
+                                <value>3</value>
+                                <description>Counter advances with each falling edge of the PWM B pin.</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>B_INV</name>
+                        <description>Invert output B</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>A_INV</name>
+                        <description>Invert output A</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PH_CORRECT</name>
+                        <description>1: Enable phase-correct modulation. 0: Trailing-edge</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>EN</name>
+                        <description>Enable the PWM channel.</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH0_DIV</name>
+                <addressOffset>0x00000004</addressOffset>
+                <description>INT and FRAC form a fixed-point fractional number. 
+                    Counting rate is system clock frequency divided by this number. 
+                    Fractional division uses simple 1st-order sigma-delta.</description>
+                <resetValue>0x00000010</resetValue>
+                <fields>
+                    <field>
+                        <name>INT</name>
+                        <bitRange>[11:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>FRAC</name>
+                        <bitRange>[3:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH0_CTR</name>
+                <addressOffset>0x00000008</addressOffset>
+                <description>Direct access to the PWM counter</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CH0_CTR</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH0_CC</name>
+                <addressOffset>0x0000000c</addressOffset>
+                <description>Counter compare values</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>B</name>
+                        <bitRange>[31:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>A</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH0_TOP</name>
+                <addressOffset>0x00000010</addressOffset>
+                <description>Counter wrap value</description>
+                <resetValue>0x0000ffff</resetValue>
+                <fields>
+                    <field>
+                        <name>CH0_TOP</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH1_CSR</name>
+                <addressOffset>0x00000014</addressOffset>
+                <description>Control and status register</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>PH_ADV</name>
+                        <description>Advance the phase of the counter by 1 count, while it is running. 
+                            Self-clearing. Write a 1, and poll until low. Counter must be running 
+                            at less than full speed (div_int + div_frac / 16 &gt; 1)</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>PH_RET</name>
+                        <description>Retard the phase of the counter by 1 count, while it is running. 
+                            Self-clearing. Write a 1, and poll until low. Counter must be running.</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>DIVMODE</name>
+                        <bitRange>[5:4]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>div</name>
+                                <value>0</value>
+                                <description>Free-running counting at rate dictated by fractional divider</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>level</name>
+                                <value>1</value>
+                                <description>Fractional divider operation is gated by the PWM B pin.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>rise</name>
+                                <value>2</value>
+                                <description>Counter advances with each rising edge of the PWM B pin.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>fall</name>
+                                <value>3</value>
+                                <description>Counter advances with each falling edge of the PWM B pin.</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>B_INV</name>
+                        <description>Invert output B</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>A_INV</name>
+                        <description>Invert output A</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PH_CORRECT</name>
+                        <description>1: Enable phase-correct modulation. 0: Trailing-edge</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>EN</name>
+                        <description>Enable the PWM channel.</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH1_DIV</name>
+                <addressOffset>0x00000018</addressOffset>
+                <description>INT and FRAC form a fixed-point fractional number. 
+                    Counting rate is system clock frequency divided by this number. 
+                    Fractional division uses simple 1st-order sigma-delta.</description>
+                <resetValue>0x00000010</resetValue>
+                <fields>
+                    <field>
+                        <name>INT</name>
+                        <bitRange>[11:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>FRAC</name>
+                        <bitRange>[3:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH1_CTR</name>
+                <addressOffset>0x0000001c</addressOffset>
+                <description>Direct access to the PWM counter</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CH1_CTR</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH1_CC</name>
+                <addressOffset>0x00000020</addressOffset>
+                <description>Counter compare values</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>B</name>
+                        <bitRange>[31:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>A</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH1_TOP</name>
+                <addressOffset>0x00000024</addressOffset>
+                <description>Counter wrap value</description>
+                <resetValue>0x0000ffff</resetValue>
+                <fields>
+                    <field>
+                        <name>CH1_TOP</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH2_CSR</name>
+                <addressOffset>0x00000028</addressOffset>
+                <description>Control and status register</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>PH_ADV</name>
+                        <description>Advance the phase of the counter by 1 count, while it is running. 
+                            Self-clearing. Write a 1, and poll until low. Counter must be running 
+                            at less than full speed (div_int + div_frac / 16 &gt; 1)</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>PH_RET</name>
+                        <description>Retard the phase of the counter by 1 count, while it is running. 
+                            Self-clearing. Write a 1, and poll until low. Counter must be running.</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>DIVMODE</name>
+                        <bitRange>[5:4]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>div</name>
+                                <value>0</value>
+                                <description>Free-running counting at rate dictated by fractional divider</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>level</name>
+                                <value>1</value>
+                                <description>Fractional divider operation is gated by the PWM B pin.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>rise</name>
+                                <value>2</value>
+                                <description>Counter advances with each rising edge of the PWM B pin.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>fall</name>
+                                <value>3</value>
+                                <description>Counter advances with each falling edge of the PWM B pin.</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>B_INV</name>
+                        <description>Invert output B</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>A_INV</name>
+                        <description>Invert output A</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PH_CORRECT</name>
+                        <description>1: Enable phase-correct modulation. 0: Trailing-edge</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>EN</name>
+                        <description>Enable the PWM channel.</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH2_DIV</name>
+                <addressOffset>0x0000002c</addressOffset>
+                <description>INT and FRAC form a fixed-point fractional number. 
+                    Counting rate is system clock frequency divided by this number. 
+                    Fractional division uses simple 1st-order sigma-delta.</description>
+                <resetValue>0x00000010</resetValue>
+                <fields>
+                    <field>
+                        <name>INT</name>
+                        <bitRange>[11:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>FRAC</name>
+                        <bitRange>[3:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH2_CTR</name>
+                <addressOffset>0x00000030</addressOffset>
+                <description>Direct access to the PWM counter</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CH2_CTR</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH2_CC</name>
+                <addressOffset>0x00000034</addressOffset>
+                <description>Counter compare values</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>B</name>
+                        <bitRange>[31:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>A</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH2_TOP</name>
+                <addressOffset>0x00000038</addressOffset>
+                <description>Counter wrap value</description>
+                <resetValue>0x0000ffff</resetValue>
+                <fields>
+                    <field>
+                        <name>CH2_TOP</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH3_CSR</name>
+                <addressOffset>0x0000003c</addressOffset>
+                <description>Control and status register</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>PH_ADV</name>
+                        <description>Advance the phase of the counter by 1 count, while it is running. 
+                            Self-clearing. Write a 1, and poll until low. Counter must be running 
+                            at less than full speed (div_int + div_frac / 16 &gt; 1)</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>PH_RET</name>
+                        <description>Retard the phase of the counter by 1 count, while it is running. 
+                            Self-clearing. Write a 1, and poll until low. Counter must be running.</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>DIVMODE</name>
+                        <bitRange>[5:4]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>div</name>
+                                <value>0</value>
+                                <description>Free-running counting at rate dictated by fractional divider</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>level</name>
+                                <value>1</value>
+                                <description>Fractional divider operation is gated by the PWM B pin.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>rise</name>
+                                <value>2</value>
+                                <description>Counter advances with each rising edge of the PWM B pin.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>fall</name>
+                                <value>3</value>
+                                <description>Counter advances with each falling edge of the PWM B pin.</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>B_INV</name>
+                        <description>Invert output B</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>A_INV</name>
+                        <description>Invert output A</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PH_CORRECT</name>
+                        <description>1: Enable phase-correct modulation. 0: Trailing-edge</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>EN</name>
+                        <description>Enable the PWM channel.</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH3_DIV</name>
+                <addressOffset>0x00000040</addressOffset>
+                <description>INT and FRAC form a fixed-point fractional number. 
+                    Counting rate is system clock frequency divided by this number. 
+                    Fractional division uses simple 1st-order sigma-delta.</description>
+                <resetValue>0x00000010</resetValue>
+                <fields>
+                    <field>
+                        <name>INT</name>
+                        <bitRange>[11:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>FRAC</name>
+                        <bitRange>[3:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH3_CTR</name>
+                <addressOffset>0x00000044</addressOffset>
+                <description>Direct access to the PWM counter</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CH3_CTR</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH3_CC</name>
+                <addressOffset>0x00000048</addressOffset>
+                <description>Counter compare values</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>B</name>
+                        <bitRange>[31:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>A</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH3_TOP</name>
+                <addressOffset>0x0000004c</addressOffset>
+                <description>Counter wrap value</description>
+                <resetValue>0x0000ffff</resetValue>
+                <fields>
+                    <field>
+                        <name>CH3_TOP</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH4_CSR</name>
+                <addressOffset>0x00000050</addressOffset>
+                <description>Control and status register</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>PH_ADV</name>
+                        <description>Advance the phase of the counter by 1 count, while it is running. 
+                            Self-clearing. Write a 1, and poll until low. Counter must be running 
+                            at less than full speed (div_int + div_frac / 16 &gt; 1)</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>PH_RET</name>
+                        <description>Retard the phase of the counter by 1 count, while it is running. 
+                            Self-clearing. Write a 1, and poll until low. Counter must be running.</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>DIVMODE</name>
+                        <bitRange>[5:4]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>div</name>
+                                <value>0</value>
+                                <description>Free-running counting at rate dictated by fractional divider</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>level</name>
+                                <value>1</value>
+                                <description>Fractional divider operation is gated by the PWM B pin.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>rise</name>
+                                <value>2</value>
+                                <description>Counter advances with each rising edge of the PWM B pin.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>fall</name>
+                                <value>3</value>
+                                <description>Counter advances with each falling edge of the PWM B pin.</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>B_INV</name>
+                        <description>Invert output B</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>A_INV</name>
+                        <description>Invert output A</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PH_CORRECT</name>
+                        <description>1: Enable phase-correct modulation. 0: Trailing-edge</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>EN</name>
+                        <description>Enable the PWM channel.</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH4_DIV</name>
+                <addressOffset>0x00000054</addressOffset>
+                <description>INT and FRAC form a fixed-point fractional number. 
+                    Counting rate is system clock frequency divided by this number. 
+                    Fractional division uses simple 1st-order sigma-delta.</description>
+                <resetValue>0x00000010</resetValue>
+                <fields>
+                    <field>
+                        <name>INT</name>
+                        <bitRange>[11:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>FRAC</name>
+                        <bitRange>[3:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH4_CTR</name>
+                <addressOffset>0x00000058</addressOffset>
+                <description>Direct access to the PWM counter</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CH4_CTR</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH4_CC</name>
+                <addressOffset>0x0000005c</addressOffset>
+                <description>Counter compare values</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>B</name>
+                        <bitRange>[31:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>A</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH4_TOP</name>
+                <addressOffset>0x00000060</addressOffset>
+                <description>Counter wrap value</description>
+                <resetValue>0x0000ffff</resetValue>
+                <fields>
+                    <field>
+                        <name>CH4_TOP</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH5_CSR</name>
+                <addressOffset>0x00000064</addressOffset>
+                <description>Control and status register</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>PH_ADV</name>
+                        <description>Advance the phase of the counter by 1 count, while it is running. 
+                            Self-clearing. Write a 1, and poll until low. Counter must be running 
+                            at less than full speed (div_int + div_frac / 16 &gt; 1)</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>PH_RET</name>
+                        <description>Retard the phase of the counter by 1 count, while it is running. 
+                            Self-clearing. Write a 1, and poll until low. Counter must be running.</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>DIVMODE</name>
+                        <bitRange>[5:4]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>div</name>
+                                <value>0</value>
+                                <description>Free-running counting at rate dictated by fractional divider</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>level</name>
+                                <value>1</value>
+                                <description>Fractional divider operation is gated by the PWM B pin.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>rise</name>
+                                <value>2</value>
+                                <description>Counter advances with each rising edge of the PWM B pin.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>fall</name>
+                                <value>3</value>
+                                <description>Counter advances with each falling edge of the PWM B pin.</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>B_INV</name>
+                        <description>Invert output B</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>A_INV</name>
+                        <description>Invert output A</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PH_CORRECT</name>
+                        <description>1: Enable phase-correct modulation. 0: Trailing-edge</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>EN</name>
+                        <description>Enable the PWM channel.</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH5_DIV</name>
+                <addressOffset>0x00000068</addressOffset>
+                <description>INT and FRAC form a fixed-point fractional number. 
+                    Counting rate is system clock frequency divided by this number. 
+                    Fractional division uses simple 1st-order sigma-delta.</description>
+                <resetValue>0x00000010</resetValue>
+                <fields>
+                    <field>
+                        <name>INT</name>
+                        <bitRange>[11:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>FRAC</name>
+                        <bitRange>[3:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH5_CTR</name>
+                <addressOffset>0x0000006c</addressOffset>
+                <description>Direct access to the PWM counter</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CH5_CTR</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH5_CC</name>
+                <addressOffset>0x00000070</addressOffset>
+                <description>Counter compare values</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>B</name>
+                        <bitRange>[31:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>A</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH5_TOP</name>
+                <addressOffset>0x00000074</addressOffset>
+                <description>Counter wrap value</description>
+                <resetValue>0x0000ffff</resetValue>
+                <fields>
+                    <field>
+                        <name>CH5_TOP</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH6_CSR</name>
+                <addressOffset>0x00000078</addressOffset>
+                <description>Control and status register</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>PH_ADV</name>
+                        <description>Advance the phase of the counter by 1 count, while it is running. 
+                            Self-clearing. Write a 1, and poll until low. Counter must be running 
+                            at less than full speed (div_int + div_frac / 16 &gt; 1)</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>PH_RET</name>
+                        <description>Retard the phase of the counter by 1 count, while it is running. 
+                            Self-clearing. Write a 1, and poll until low. Counter must be running.</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>DIVMODE</name>
+                        <bitRange>[5:4]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>div</name>
+                                <value>0</value>
+                                <description>Free-running counting at rate dictated by fractional divider</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>level</name>
+                                <value>1</value>
+                                <description>Fractional divider operation is gated by the PWM B pin.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>rise</name>
+                                <value>2</value>
+                                <description>Counter advances with each rising edge of the PWM B pin.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>fall</name>
+                                <value>3</value>
+                                <description>Counter advances with each falling edge of the PWM B pin.</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>B_INV</name>
+                        <description>Invert output B</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>A_INV</name>
+                        <description>Invert output A</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PH_CORRECT</name>
+                        <description>1: Enable phase-correct modulation. 0: Trailing-edge</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>EN</name>
+                        <description>Enable the PWM channel.</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH6_DIV</name>
+                <addressOffset>0x0000007c</addressOffset>
+                <description>INT and FRAC form a fixed-point fractional number. 
+                    Counting rate is system clock frequency divided by this number. 
+                    Fractional division uses simple 1st-order sigma-delta.</description>
+                <resetValue>0x00000010</resetValue>
+                <fields>
+                    <field>
+                        <name>INT</name>
+                        <bitRange>[11:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>FRAC</name>
+                        <bitRange>[3:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH6_CTR</name>
+                <addressOffset>0x00000080</addressOffset>
+                <description>Direct access to the PWM counter</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CH6_CTR</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH6_CC</name>
+                <addressOffset>0x00000084</addressOffset>
+                <description>Counter compare values</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>B</name>
+                        <bitRange>[31:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>A</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH6_TOP</name>
+                <addressOffset>0x00000088</addressOffset>
+                <description>Counter wrap value</description>
+                <resetValue>0x0000ffff</resetValue>
+                <fields>
+                    <field>
+                        <name>CH6_TOP</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH7_CSR</name>
+                <addressOffset>0x0000008c</addressOffset>
+                <description>Control and status register</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>PH_ADV</name>
+                        <description>Advance the phase of the counter by 1 count, while it is running. 
+                            Self-clearing. Write a 1, and poll until low. Counter must be running 
+                            at less than full speed (div_int + div_frac / 16 &gt; 1)</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>PH_RET</name>
+                        <description>Retard the phase of the counter by 1 count, while it is running. 
+                            Self-clearing. Write a 1, and poll until low. Counter must be running.</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>DIVMODE</name>
+                        <bitRange>[5:4]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>div</name>
+                                <value>0</value>
+                                <description>Free-running counting at rate dictated by fractional divider</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>level</name>
+                                <value>1</value>
+                                <description>Fractional divider operation is gated by the PWM B pin.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>rise</name>
+                                <value>2</value>
+                                <description>Counter advances with each rising edge of the PWM B pin.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>fall</name>
+                                <value>3</value>
+                                <description>Counter advances with each falling edge of the PWM B pin.</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>B_INV</name>
+                        <description>Invert output B</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>A_INV</name>
+                        <description>Invert output A</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PH_CORRECT</name>
+                        <description>1: Enable phase-correct modulation. 0: Trailing-edge</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>EN</name>
+                        <description>Enable the PWM channel.</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH7_DIV</name>
+                <addressOffset>0x00000090</addressOffset>
+                <description>INT and FRAC form a fixed-point fractional number. 
+                    Counting rate is system clock frequency divided by this number. 
+                    Fractional division uses simple 1st-order sigma-delta.</description>
+                <resetValue>0x00000010</resetValue>
+                <fields>
+                    <field>
+                        <name>INT</name>
+                        <bitRange>[11:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>FRAC</name>
+                        <bitRange>[3:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH7_CTR</name>
+                <addressOffset>0x00000094</addressOffset>
+                <description>Direct access to the PWM counter</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CH7_CTR</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH7_CC</name>
+                <addressOffset>0x00000098</addressOffset>
+                <description>Counter compare values</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>B</name>
+                        <bitRange>[31:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>A</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH7_TOP</name>
+                <addressOffset>0x0000009c</addressOffset>
+                <description>Counter wrap value</description>
+                <resetValue>0x0000ffff</resetValue>
+                <fields>
+                    <field>
+                        <name>CH7_TOP</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>EN</name>
+                <addressOffset>0x000000a0</addressOffset>
+                <description>This register aliases the CSR_EN bits for all channels. 
+                    Writing to this register allows multiple channels to be enabled 
+                    or disabled simultaneously, so they can run in perfect sync. 
+                    For each channel, there is only one physical EN register bit, 
+                    which can be accessed through here or CHx_CSR.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CH7</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CH6</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CH5</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CH4</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CH3</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CH2</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CH1</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CH0</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INTR</name>
+                <addressOffset>0x000000a4</addressOffset>
+                <description>Raw Interrupts</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CH7</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>CH6</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>CH5</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>CH4</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>CH3</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>CH2</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>CH1</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>CH0</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INTE</name>
+                <addressOffset>0x000000a8</addressOffset>
+                <description>Interrupt Enable</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CH7</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CH6</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CH5</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CH4</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CH3</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CH2</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CH1</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CH0</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INTF</name>
+                <addressOffset>0x000000ac</addressOffset>
+                <description>Interrupt Force</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CH7</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CH6</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CH5</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CH4</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CH3</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CH2</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CH1</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CH0</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INTS</name>
+                <addressOffset>0x000000b0</addressOffset>
+                <description>Interrupt status after masking &amp; forcing</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CH7</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CH6</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CH5</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CH4</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CH3</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CH2</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CH1</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CH0</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+        </registers>
+    </peripheral>
+    <peripheral>
+        <name>ADC</name>
+        <description>Control and data interface to SAR ADC</description>
+        <baseAddress>0x4004c000</baseAddress>
+        <addressBlock>
+            <offset>0</offset>
+            <size>36</size>
+            <usage>registers</usage>
+        </addressBlock>
+        <interrupt>
+            <name>ADC_IRQ_FIFO</name>
+            <value>22</value>
+        </interrupt>
+        <registers>
+            <register>
+                <name>CS</name>
+                <addressOffset>0x00000000</addressOffset>
+                <description>ADC Control and Status</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>RROBIN</name>
+                        <description>Round-robin sampling. 1 bit per channel. Set all bits to 0 to disable. 
+                            Otherwise, the ADC will cycle through each enabled channel in a round-robin fashion. 
+                            The first channel to be sampled will be the one currently indicated by AINSEL. 
+                            AINSEL will be updated after each conversion with the newly-selected channel.</description>
+                        <bitRange>[20:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>AINSEL</name>
+                        <description>Select analog mux input. Updated automatically in round-robin mode.</description>
+                        <bitRange>[14:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ERR_STICKY</name>
+                        <description>Some past ADC conversion encountered an error. Write 1 to clear.</description>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>ERR</name>
+                        <description>The most recent ADC conversion encountered an error; result is undefined or noisy.</description>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>READY</name>
+                        <description>1 if the ADC is ready to start a new conversion. Implies any previous conversion has completed. 
+                            0 whilst conversion in progress.</description>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>START_MANY</name>
+                        <description>Continuously perform conversions whilst this bit is 1. A new conversion will start immediately after the previous finishes.</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>START_ONCE</name>
+                        <description>Start a single conversion. Self-clearing. Ignored if start_many is asserted.</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>TS_EN</name>
+                        <description>Power on temperature sensor. 1 - enabled. 0 - disabled.</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>EN</name>
+                        <description>Power on ADC and enable its clock. 
+                            1 - enabled. 0 - disabled.</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>RESULT</name>
+                <addressOffset>0x00000004</addressOffset>
+                <description>Result of most recent ADC conversion</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>RESULT</name>
+                        <bitRange>[11:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>FCS</name>
+                <addressOffset>0x00000008</addressOffset>
+                <description>FIFO control and status</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>THRESH</name>
+                        <description>DREQ/IRQ asserted when level &gt;= threshold</description>
+                        <bitRange>[27:24]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LEVEL</name>
+                        <description>The number of conversion results currently waiting in the FIFO</description>
+                        <bitRange>[19:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OVER</name>
+                        <description>1 if the FIFO has been overflowed. Write 1 to clear.</description>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>UNDER</name>
+                        <description>1 if the FIFO has been underflowed. Write 1 to clear.</description>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>FULL</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>EMPTY</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>DREQ_EN</name>
+                        <description>If 1: assert DMA requests when FIFO contains data</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ERR</name>
+                        <description>If 1: conversion error bit appears in the FIFO alongside the result</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SHIFT</name>
+                        <description>If 1: FIFO results are right-shifted to be one byte in size. Enables DMA to byte buffers.</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>EN</name>
+                        <description>If 1: write result to the FIFO after each conversion.</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>FIFO</name>
+                <addressOffset>0x0000000c</addressOffset>
+                <description>Conversion result FIFO</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>ERR</name>
+                        <description>1 if this particular sample experienced a conversion error. Remains in the same location if the sample is shifted.</description>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-only</access>
+                        <readAction>modify</readAction>
+                    </field>
+                    <field>
+                        <name>VAL</name>
+                        <bitRange>[11:0]</bitRange>
+                        <access>read-only</access>
+                        <readAction>modify</readAction>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>DIV</name>
+                <addressOffset>0x00000010</addressOffset>
+                <description>Clock divider. If non-zero, CS_START_MANY will start conversions 
+                    at regular intervals rather than back-to-back. 
+                    The divider is reset when either of these fields are written. 
+                    Total period is 1 + INT + FRAC / 256</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>INT</name>
+                        <description>Integer part of clock divisor.</description>
+                        <bitRange>[23:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>FRAC</name>
+                        <description>Fractional part of clock divisor. First-order delta-sigma.</description>
+                        <bitRange>[7:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INTR</name>
+                <addressOffset>0x00000014</addressOffset>
+                <description>Raw Interrupts</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>FIFO</name>
+                        <description>Triggered when the sample FIFO reaches a certain level. 
+                            This level can be programmed via the FCS_THRESH field.</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INTE</name>
+                <addressOffset>0x00000018</addressOffset>
+                <description>Interrupt Enable</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>FIFO</name>
+                        <description>Triggered when the sample FIFO reaches a certain level. 
+                            This level can be programmed via the FCS_THRESH field.</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INTF</name>
+                <addressOffset>0x0000001c</addressOffset>
+                <description>Interrupt Force</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>FIFO</name>
+                        <description>Triggered when the sample FIFO reaches a certain level. 
+                            This level can be programmed via the FCS_THRESH field.</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INTS</name>
+                <addressOffset>0x00000020</addressOffset>
+                <description>Interrupt status after masking &amp; forcing</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>FIFO</name>
+                        <description>Triggered when the sample FIFO reaches a certain level. 
+                            This level can be programmed via the FCS_THRESH field.</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+        </registers>
+    </peripheral>
+    <peripheral>
+        <name>I2C0</name>
+        <description>DW_apb_i2c address block
+
+            List of configuration constants for the Synopsys I2C hardware (you may see references to these in I2C register header; these are *fixed* values, set at hardware design time):
+
+            IC_ULTRA_FAST_MODE ................ 0x0 
+            IC_UFM_TBUF_CNT_DEFAULT ........... 0x8 
+            IC_UFM_SCL_LOW_COUNT .............. 0x0008 
+            IC_UFM_SCL_HIGH_COUNT ............. 0x0006 
+            IC_TX_TL .......................... 0x0 
+            IC_TX_CMD_BLOCK ................... 0x1 
+            IC_HAS_DMA ........................ 0x1 
+            IC_HAS_ASYNC_FIFO ................. 0x0 
+            IC_SMBUS_ARP ...................... 0x0 
+            IC_FIRST_DATA_BYTE_STATUS ......... 0x1 
+            IC_INTR_IO ........................ 0x1 
+            IC_MASTER_MODE .................... 0x1 
+            IC_DEFAULT_ACK_GENERAL_CALL ....... 0x1 
+            IC_INTR_POL ....................... 0x1 
+            IC_OPTIONAL_SAR ................... 0x0 
+            IC_DEFAULT_TAR_SLAVE_ADDR ......... 0x055 
+            IC_DEFAULT_SLAVE_ADDR ............. 0x055 
+            IC_DEFAULT_HS_SPKLEN .............. 0x1 
+            IC_FS_SCL_HIGH_COUNT .............. 0x0006 
+            IC_HS_SCL_LOW_COUNT ............... 0x0008 
+            IC_DEVICE_ID_VALUE ................ 0x0 
+            IC_10BITADDR_MASTER ............... 0x0 
+            IC_CLK_FREQ_OPTIMIZATION .......... 0x0 
+            IC_DEFAULT_FS_SPKLEN .............. 0x7 
+            IC_ADD_ENCODED_PARAMS ............. 0x0 
+            IC_DEFAULT_SDA_HOLD ............... 0x000001 
+            IC_DEFAULT_SDA_SETUP .............. 0x64 
+            IC_AVOID_RX_FIFO_FLUSH_ON_TX_ABRT . 0x0 
+            IC_CLOCK_PERIOD ................... 100 
+            IC_EMPTYFIFO_HOLD_MASTER_EN ....... 1 
+            IC_RESTART_EN ..................... 0x1 
+            IC_TX_CMD_BLOCK_DEFAULT ........... 0x0 
+            IC_BUS_CLEAR_FEATURE .............. 0x0 
+            IC_CAP_LOADING .................... 100 
+            IC_FS_SCL_LOW_COUNT ............... 0x000d 
+            APB_DATA_WIDTH .................... 32 
+            IC_SDA_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff 
+            IC_SLV_DATA_NACK_ONLY ............. 0x1 
+            IC_10BITADDR_SLAVE ................ 0x0 
+            IC_CLK_TYPE ....................... 0x0 
+            IC_SMBUS_UDID_MSB ................. 0x0 
+            IC_SMBUS_SUSPEND_ALERT ............ 0x0 
+            IC_HS_SCL_HIGH_COUNT .............. 0x0006 
+            IC_SLV_RESTART_DET_EN ............. 0x1 
+            IC_SMBUS .......................... 0x0 
+            IC_OPTIONAL_SAR_DEFAULT ........... 0x0 
+            IC_PERSISTANT_SLV_ADDR_DEFAULT .... 0x0 
+            IC_USE_COUNTS ..................... 0x0 
+            IC_RX_BUFFER_DEPTH ................ 16 
+            IC_SCL_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff 
+            IC_RX_FULL_HLD_BUS_EN ............. 0x1 
+            IC_SLAVE_DISABLE .................. 0x1 
+            IC_RX_TL .......................... 0x0 
+            IC_DEVICE_ID ...................... 0x0 
+            IC_HC_COUNT_VALUES ................ 0x0 
+            I2C_DYNAMIC_TAR_UPDATE ............ 0 
+            IC_SMBUS_CLK_LOW_MEXT_DEFAULT ..... 0xffffffff 
+            IC_SMBUS_CLK_LOW_SEXT_DEFAULT ..... 0xffffffff 
+            IC_HS_MASTER_CODE ................. 0x1 
+            IC_SMBUS_RST_IDLE_CNT_DEFAULT ..... 0xffff 
+            IC_SMBUS_UDID_LSB_DEFAULT ......... 0xffffffff 
+            IC_SS_SCL_HIGH_COUNT .............. 0x0028 
+            IC_SS_SCL_LOW_COUNT ............... 0x002f 
+            IC_MAX_SPEED_MODE ................. 0x2 
+            IC_STAT_FOR_CLK_STRETCH ........... 0x0 
+            IC_STOP_DET_IF_MASTER_ACTIVE ...... 0x0 
+            IC_DEFAULT_UFM_SPKLEN ............. 0x1 
+            IC_TX_BUFFER_DEPTH ................ 16</description>
+        <baseAddress>0x40044000</baseAddress>
+        <addressBlock>
+            <offset>0</offset>
+            <size>256</size>
+            <usage>registers</usage>
+        </addressBlock>
+        <interrupt>
+            <name>I2C0_IRQ</name>
+            <value>23</value>
+        </interrupt>
+        <registers>
+            <register>
+                <name>IC_CON</name>
+                <addressOffset>0x00000000</addressOffset>
+                <description>I2C Control Register. This register can be written only when the DW_apb_i2c is disabled, which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect.
+
+                    Read/Write Access: - bit 10 is read only. - bit 11 is read only - bit 16 is read only - bit 17 is read only - bits 18 and 19 are read only.</description>
+                <resetValue>0x00000065</resetValue>
+                <fields>
+                    <field>
+                        <name>STOP_DET_IF_MASTER_ACTIVE</name>
+                        <description>Master issues the STOP_DET interrupt irrespective of whether master is active or not</description>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>RX_FIFO_FULL_HLD_CTRL</name>
+                        <description>This bit controls whether DW_apb_i2c should hold the bus when the Rx FIFO is physically full to its RX_BUFFER_DEPTH, as described in the IC_RX_FULL_HLD_BUS_EN parameter.
+
+                            Reset value: 0x0.</description>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>DISABLED</name>
+                                <value>0</value>
+                                <description>Overflow when RX_FIFO is full</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ENABLED</name>
+                                <value>1</value>
+                                <description>Hold bus when RX_FIFO is full</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>TX_EMPTY_CTRL</name>
+                        <description>This bit controls the generation of the TX_EMPTY interrupt, as described in the IC_RAW_INTR_STAT register.
+
+                            Reset value: 0x0.</description>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>DISABLED</name>
+                                <value>0</value>
+                                <description>Default behaviour of TX_EMPTY interrupt</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ENABLED</name>
+                                <value>1</value>
+                                <description>Controlled generation of TX_EMPTY interrupt</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>STOP_DET_IFADDRESSED</name>
+                        <description>In slave mode: - 1&#39;b1:  issues the STOP_DET interrupt only when it is addressed. - 1&#39;b0:  issues the STOP_DET irrespective of whether it&#39;s addressed or not. Reset value: 0x0
+
+                            NOTE: During a general call address, this slave does not issue the STOP_DET interrupt if STOP_DET_IF_ADDRESSED = 1&#39;b1, even if the slave responds to the general call address by generating ACK. The STOP_DET interrupt is generated only when the transmitted address matches the slave address (SAR).</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>DISABLED</name>
+                                <value>0</value>
+                                <description>slave issues STOP_DET intr always</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ENABLED</name>
+                                <value>1</value>
+                                <description>slave issues STOP_DET intr only if addressed</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>IC_SLAVE_DISABLE</name>
+                        <description>This bit controls whether I2C has its slave disabled, which means once the presetn signal is applied, then this bit is set and the slave is disabled.
+
+                            If this bit is set (slave is disabled), DW_apb_i2c functions only as a master and does not perform any action that requires a slave.
+
+                            NOTE: Software should ensure that if this bit is written with 0, then bit 0 should also be written with a 0.</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>SLAVE_ENABLED</name>
+                                <value>0</value>
+                                <description>Slave mode is enabled</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SLAVE_DISABLED</name>
+                                <value>1</value>
+                                <description>Slave mode is disabled</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>IC_RESTART_EN</name>
+                        <description>Determines whether RESTART conditions may be sent when acting as a master. Some older slaves do not support handling RESTART conditions; however, RESTART conditions are used in several DW_apb_i2c operations. When RESTART is disabled, the master is prohibited from performing the following functions: - Sending a START BYTE - Performing any high-speed mode operation - High-speed mode operation - Performing direction changes in combined format mode - Performing a read operation with a 10-bit address By replacing RESTART condition followed by a STOP and a subsequent START condition, split operations are broken down into multiple DW_apb_i2c transfers. If the above operations are performed, it will result in setting bit 6 (TX_ABRT) of the IC_RAW_INTR_STAT register.
+
+                            Reset value: ENABLED</description>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>DISABLED</name>
+                                <value>0</value>
+                                <description>Master restart disabled</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ENABLED</name>
+                                <value>1</value>
+                                <description>Master restart enabled</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>IC_10BITADDR_MASTER</name>
+                        <description>Controls whether the DW_apb_i2c starts its transfers in 7- or 10-bit addressing mode when acting as a master. - 0: 7-bit addressing - 1: 10-bit addressing</description>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>ADDR_7BITS</name>
+                                <value>0</value>
+                                <description>Master 7Bit addressing mode</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADDR_10BITS</name>
+                                <value>1</value>
+                                <description>Master 10Bit addressing mode</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>IC_10BITADDR_SLAVE</name>
+                        <description>When acting as a slave, this bit controls whether the DW_apb_i2c responds to 7- or 10-bit addresses. - 0: 7-bit addressing. The DW_apb_i2c ignores transactions that involve 10-bit addressing; for 7-bit addressing, only the lower 7 bits of the IC_SAR register are compared. - 1: 10-bit addressing. The DW_apb_i2c responds to only 10-bit addressing transfers that match the full 10 bits of the IC_SAR register.</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>ADDR_7BITS</name>
+                                <value>0</value>
+                                <description>Slave 7Bit addressing</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADDR_10BITS</name>
+                                <value>1</value>
+                                <description>Slave 10Bit addressing</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>SPEED</name>
+                        <description>These bits control at which speed the DW_apb_i2c operates; its setting is relevant only if one is operating the DW_apb_i2c in master mode. Hardware protects against illegal values being programmed by software. These bits must be programmed appropriately for slave mode also, as it is used to capture correct value of spike filter as per the speed mode.
+
+                            This register should be programmed only with a value in the range of 1 to IC_MAX_SPEED_MODE; otherwise, hardware updates this register with the value of IC_MAX_SPEED_MODE.
+
+                            1: standard mode (100 kbit/s)
+
+                            2: fast mode (&lt;=400 kbit/s) or fast mode plus (&lt;=1000Kbit/s)
+
+                            3: high speed mode (3.4 Mbit/s)
+
+                            Note: This field is not applicable when IC_ULTRA_FAST_MODE=1</description>
+                        <bitRange>[2:1]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>STANDARD</name>
+                                <value>1</value>
+                                <description>Standard Speed mode of operation</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>FAST</name>
+                                <value>2</value>
+                                <description>Fast or Fast Plus mode of operation</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>High Speed mode of operation</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>MASTER_MODE</name>
+                        <description>This bit controls whether the DW_apb_i2c master is enabled.
+
+                            NOTE: Software should ensure that if this bit is written with &#39;1&#39; then bit 6 should also be written with a &#39;1&#39;.</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>DISABLED</name>
+                                <value>0</value>
+                                <description>Master mode is disabled</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ENABLED</name>
+                                <value>1</value>
+                                <description>Master mode is enabled</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>IC_TAR</name>
+                <addressOffset>0x00000004</addressOffset>
+                <description>I2C Target Address Register
+
+                    This register is 12 bits wide, and bits 31:12 are reserved. This register can be written to only when IC_ENABLE[0] is set to 0.
+
+                    Note: If the software or application is aware that the DW_apb_i2c is not using the TAR address for the pending commands in the Tx FIFO, then it is possible to update the TAR address even while the Tx FIFO has entries (IC_STATUS[2]= 0). - It is not necessary to perform any write to this register if DW_apb_i2c is enabled as an I2C slave only.</description>
+                <resetValue>0x00000055</resetValue>
+                <fields>
+                    <field>
+                        <name>SPECIAL</name>
+                        <description>This bit indicates whether software performs a Device-ID or General Call or START BYTE command. - 0: ignore bit 10 GC_OR_START and use IC_TAR normally - 1: perform special I2C command as specified in Device_ID or GC_OR_START bit Reset value: 0x0</description>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>DISABLED</name>
+                                <value>0</value>
+                                <description>Disables programming of GENERAL_CALL or START_BYTE transmission</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ENABLED</name>
+                                <value>1</value>
+                                <description>Enables programming of GENERAL_CALL or START_BYTE transmission</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>GC_OR_START</name>
+                        <description>If bit 11 (SPECIAL) is set to 1 and bit 13(Device-ID) is set to 0, then this bit indicates whether a General Call or START byte command is to be performed by the DW_apb_i2c. - 0: General Call Address - after issuing a General Call, only writes may be performed. Attempting to issue a read command results in setting bit 6 (TX_ABRT) of the IC_RAW_INTR_STAT register. The DW_apb_i2c remains in General Call mode until the SPECIAL bit value (bit 11) is cleared. - 1: START BYTE Reset value: 0x0</description>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>GENERAL_CALL</name>
+                                <value>0</value>
+                                <description>GENERAL_CALL byte transmission</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>START_BYTE</name>
+                                <value>1</value>
+                                <description>START byte transmission</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>IC_TAR</name>
+                        <description>This is the target address for any master transaction. When transmitting a General Call, these bits are ignored. To generate a START BYTE, the CPU needs to write only once into these bits.
+
+                            If the IC_TAR and IC_SAR are the same, loopback exists but the FIFOs are shared between master and slave, so full loopback is not feasible. Only one direction loopback mode is supported (simplex), not duplex. A master cannot transmit to itself; it can transmit to only a slave.</description>
+                        <bitRange>[9:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>IC_SAR</name>
+                <addressOffset>0x00000008</addressOffset>
+                <description>I2C Slave Address Register</description>
+                <resetValue>0x00000055</resetValue>
+                <fields>
+                    <field>
+                        <name>IC_SAR</name>
+                        <description>The IC_SAR holds the slave address when the I2C is operating as a slave. For 7-bit addressing, only IC_SAR[6:0] is used.
+
+                            This register can be written only when the I2C interface is disabled, which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect.
+
+                            Note: The default values cannot be any of the reserved address locations: that is, 0x00 to 0x07, or 0x78 to 0x7f. The correct operation of the device is not guaranteed if you program the IC_SAR or IC_TAR to a reserved value. Refer to &lt;&lt;table_I2C_firstbyte_bit_defs&gt;&gt; for a complete list of these reserved values.</description>
+                        <bitRange>[9:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>IC_DATA_CMD</name>
+                <addressOffset>0x00000010</addressOffset>
+                <description>I2C Rx/Tx Data Buffer and Command Register; this is the register the CPU writes to when filling the TX FIFO and the CPU reads from when retrieving bytes from RX FIFO.
+
+                    The size of the register changes as follows:
+
+                    Write: - 11 bits when IC_EMPTYFIFO_HOLD_MASTER_EN=1 - 9 bits when IC_EMPTYFIFO_HOLD_MASTER_EN=0 Read: - 12 bits when IC_FIRST_DATA_BYTE_STATUS = 1 - 8 bits when IC_FIRST_DATA_BYTE_STATUS = 0 Note: In order for the DW_apb_i2c to continue acknowledging reads, a read command should be written for every byte that is to be received; otherwise the DW_apb_i2c will stop acknowledging.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>FIRST_DATA_BYTE</name>
+                        <description>Indicates the first data byte received after the address phase for receive transfer in Master receiver or Slave receiver mode.
+
+                            Reset value : 0x0
+
+                            NOTE:  In case of APB_DATA_WIDTH=8,
+
+                            1. The user has to perform two APB Reads to IC_DATA_CMD in order to get status on 11 bit.
+
+                            2. In order to read the 11 bit, the user has to perform the first data byte read [7:0] (offset 0x10) and then perform the second read [15:8] (offset 0x11) in order to know the status of 11 bit (whether the data received in previous read is a first data byte or not).
+
+                            3. The 11th bit is an optional read field, user can ignore 2nd byte read [15:8] (offset 0x11) if not interested in FIRST_DATA_BYTE status.</description>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>INACTIVE</name>
+                                <value>0</value>
+                                <description>Sequential data byte received</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ACTIVE</name>
+                                <value>1</value>
+                                <description>Non sequential data byte received</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>RESTART</name>
+                        <description>This bit controls whether a RESTART is issued before the byte is sent or received.
+
+                            1 - If IC_RESTART_EN is 1, a RESTART is issued before the data is sent/received (according to the value of CMD), regardless of whether or not the transfer direction is changing from the previous command; if IC_RESTART_EN is 0, a STOP followed by a START is issued instead.
+
+                            0 - If IC_RESTART_EN is 1, a RESTART is issued only if the transfer direction is changing from the previous command; if IC_RESTART_EN is 0, a STOP followed by a START is issued instead.
+
+                            Reset value: 0x0</description>
+                        <bitRange>[10:10]</bitRange>
+                        <access>write-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>DISABLE</name>
+                                <value>0</value>
+                                <description>Don&#39;t Issue RESTART before this command</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ENABLE</name>
+                                <value>1</value>
+                                <description>Issue RESTART before this command</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>STOP</name>
+                        <description>This bit controls whether a STOP is issued after the byte is sent or received.
+
+                            - 1 - STOP is issued after this byte, regardless of whether or not the Tx FIFO is empty. If the Tx FIFO is not empty, the master immediately tries to start a new transfer by issuing a START and arbitrating for the bus. - 0 - STOP is not issued after this byte, regardless of whether or not the Tx FIFO is empty. If the Tx FIFO is not empty, the master continues the current transfer by sending/receiving data bytes according to the value of the CMD bit. If the Tx FIFO is empty, the master holds the SCL line low and stalls the bus until a new command is available in the Tx FIFO. Reset value: 0x0</description>
+                        <bitRange>[9:9]</bitRange>
+                        <access>write-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>DISABLE</name>
+                                <value>0</value>
+                                <description>Don&#39;t Issue STOP after this command</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ENABLE</name>
+                                <value>1</value>
+                                <description>Issue STOP after this command</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>CMD</name>
+                        <description>This bit controls whether a read or a write is performed. This bit does not control the direction when the DW_apb_i2con acts as a slave. It controls only the direction when it acts as a master.
+
+                            When a command is entered in the TX FIFO, this bit distinguishes the write and read commands. In slave-receiver mode, this bit is a &#39;don&#39;t care&#39; because writes to this register are not required. In slave-transmitter mode, a &#39;0&#39; indicates that the data in IC_DATA_CMD is to be transmitted.
+
+                            When programming this bit, you should remember the following: attempting to perform a read operation after a General Call command has been sent results in a TX_ABRT interrupt (bit 6 of the IC_RAW_INTR_STAT register), unless bit 11 (SPECIAL) in the IC_TAR register has been cleared. If a &#39;1&#39; is written to this bit after receiving a RD_REQ interrupt, then a TX_ABRT interrupt occurs.
+
+                            Reset value: 0x0</description>
+                        <bitRange>[8:8]</bitRange>
+                        <access>write-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>WRITE</name>
+                                <value>0</value>
+                                <description>Master Write Command</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>READ</name>
+                                <value>1</value>
+                                <description>Master Read Command</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>DAT</name>
+                        <description>This register contains the data to be transmitted or received on the I2C bus. If you are writing to this register and want to perform a read, bits 7:0 (DAT) are ignored by the DW_apb_i2c. However, when you read this register, these bits return the value of data received on the DW_apb_i2c interface.
+
+                            Reset value: 0x0</description>
+                        <bitRange>[7:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>IC_SS_SCL_HCNT</name>
+                <addressOffset>0x00000014</addressOffset>
+                <description>Standard Speed I2C Clock SCL High Count Register</description>
+                <resetValue>0x00000028</resetValue>
+                <fields>
+                    <field>
+                        <name>IC_SS_SCL_HCNT</name>
+                        <description>This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock high-period count for standard speed. For more information, refer to &#39;IC_CLK Frequency Configuration&#39;.
+
+                            This register can be written only when the I2C interface is disabled which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect.
+
+                            The minimum valid value is 6; hardware prevents values less than this being written, and if attempted results in 6 being set. For designs with APB_DATA_WIDTH = 8, the order of programming is important to ensure the correct operation of the DW_apb_i2c. The lower byte must be programmed first. Then the upper byte is programmed.
+
+                            NOTE: This register must not be programmed to a value higher than 65525, because DW_apb_i2c uses a 16-bit counter to flag an I2C bus idle condition when this counter reaches a value of IC_SS_SCL_HCNT + 10.</description>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>IC_SS_SCL_LCNT</name>
+                <addressOffset>0x00000018</addressOffset>
+                <description>Standard Speed I2C Clock SCL Low Count Register</description>
+                <resetValue>0x0000002f</resetValue>
+                <fields>
+                    <field>
+                        <name>IC_SS_SCL_LCNT</name>
+                        <description>This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock low period count for standard speed. For more information, refer to &#39;IC_CLK Frequency Configuration&#39;
+
+                            This register can be written only when the I2C interface is disabled which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect.
+
+                            The minimum valid value is 8; hardware prevents values less than this being written, and if attempted, results in 8 being set. For designs with APB_DATA_WIDTH = 8, the order of programming is important to ensure the correct operation of DW_apb_i2c. The lower byte must be programmed first, and then the upper byte is programmed.</description>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>IC_FS_SCL_HCNT</name>
+                <addressOffset>0x0000001c</addressOffset>
+                <description>Fast Mode or Fast Mode Plus I2C Clock SCL High Count Register</description>
+                <resetValue>0x00000006</resetValue>
+                <fields>
+                    <field>
+                        <name>IC_FS_SCL_HCNT</name>
+                        <description>This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock high-period count for fast mode or fast mode plus. It is used in high-speed mode to send the Master Code and START BYTE or General CALL. For more information, refer to &#39;IC_CLK Frequency Configuration&#39;.
+
+                            This register goes away and becomes read-only returning 0s if IC_MAX_SPEED_MODE = standard. This register can be written only when the I2C interface is disabled, which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect.
+
+                            The minimum valid value is 6; hardware prevents values less than this being written, and if attempted results in 6 being set. For designs with APB_DATA_WIDTH == 8 the order of programming is important to ensure the correct operation of the DW_apb_i2c. The lower byte must be programmed first. Then the upper byte is programmed.</description>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>IC_FS_SCL_LCNT</name>
+                <addressOffset>0x00000020</addressOffset>
+                <description>Fast Mode or Fast Mode Plus I2C Clock SCL Low Count Register</description>
+                <resetValue>0x0000000d</resetValue>
+                <fields>
+                    <field>
+                        <name>IC_FS_SCL_LCNT</name>
+                        <description>This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock low period count for fast speed. It is used in high-speed mode to send the Master Code and START BYTE or General CALL. For more information, refer to &#39;IC_CLK Frequency Configuration&#39;.
+
+                            This register goes away and becomes read-only returning 0s if IC_MAX_SPEED_MODE = standard.
+
+                            This register can be written only when the I2C interface is disabled, which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect.
+
+                            The minimum valid value is 8; hardware prevents values less than this being written, and if attempted results in 8 being set. For designs with APB_DATA_WIDTH = 8 the order of programming is important to ensure the correct operation of the DW_apb_i2c. The lower byte must be programmed first. Then the upper byte is programmed. If the value is less than 8 then the count value gets changed to 8.</description>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>IC_INTR_STAT</name>
+                <addressOffset>0x0000002c</addressOffset>
+                <description>I2C Interrupt Status Register
+
+                    Each bit in this register has a corresponding mask bit in the IC_INTR_MASK register. These bits are cleared by reading the matching interrupt clear register. The unmasked raw versions of these bits are available in the IC_RAW_INTR_STAT register.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>R_RESTART_DET</name>
+                        <description>See IC_RAW_INTR_STAT for a detailed description of R_RESTART_DET bit.
+
+                            Reset value: 0x0</description>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>INACTIVE</name>
+                                <value>0</value>
+                                <description>R_RESTART_DET interrupt is inactive</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ACTIVE</name>
+                                <value>1</value>
+                                <description>R_RESTART_DET interrupt is active</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>R_GEN_CALL</name>
+                        <description>See IC_RAW_INTR_STAT for a detailed description of R_GEN_CALL bit.
+
+                            Reset value: 0x0</description>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>INACTIVE</name>
+                                <value>0</value>
+                                <description>R_GEN_CALL interrupt is inactive</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ACTIVE</name>
+                                <value>1</value>
+                                <description>R_GEN_CALL interrupt is active</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>R_START_DET</name>
+                        <description>See IC_RAW_INTR_STAT for a detailed description of R_START_DET bit.
+
+                            Reset value: 0x0</description>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>INACTIVE</name>
+                                <value>0</value>
+                                <description>R_START_DET interrupt is inactive</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ACTIVE</name>
+                                <value>1</value>
+                                <description>R_START_DET interrupt is active</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>R_STOP_DET</name>
+                        <description>See IC_RAW_INTR_STAT for a detailed description of R_STOP_DET bit.
+
+                            Reset value: 0x0</description>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>INACTIVE</name>
+                                <value>0</value>
+                                <description>R_STOP_DET interrupt is inactive</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ACTIVE</name>
+                                <value>1</value>
+                                <description>R_STOP_DET interrupt is active</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>R_ACTIVITY</name>
+                        <description>See IC_RAW_INTR_STAT for a detailed description of R_ACTIVITY bit.
+
+                            Reset value: 0x0</description>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>INACTIVE</name>
+                                <value>0</value>
+                                <description>R_ACTIVITY interrupt is inactive</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ACTIVE</name>
+                                <value>1</value>
+                                <description>R_ACTIVITY interrupt is active</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>R_RX_DONE</name>
+                        <description>See IC_RAW_INTR_STAT for a detailed description of R_RX_DONE bit.
+
+                            Reset value: 0x0</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>INACTIVE</name>
+                                <value>0</value>
+                                <description>R_RX_DONE interrupt is inactive</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ACTIVE</name>
+                                <value>1</value>
+                                <description>R_RX_DONE interrupt is active</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>R_TX_ABRT</name>
+                        <description>See IC_RAW_INTR_STAT for a detailed description of R_TX_ABRT bit.
+
+                            Reset value: 0x0</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>INACTIVE</name>
+                                <value>0</value>
+                                <description>R_TX_ABRT interrupt is inactive</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ACTIVE</name>
+                                <value>1</value>
+                                <description>R_TX_ABRT interrupt is active</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>R_RD_REQ</name>
+                        <description>See IC_RAW_INTR_STAT for a detailed description of R_RD_REQ bit.
+
+                            Reset value: 0x0</description>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>INACTIVE</name>
+                                <value>0</value>
+                                <description>R_RD_REQ interrupt is inactive</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ACTIVE</name>
+                                <value>1</value>
+                                <description>R_RD_REQ interrupt is active</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>R_TX_EMPTY</name>
+                        <description>See IC_RAW_INTR_STAT for a detailed description of R_TX_EMPTY bit.
+
+                            Reset value: 0x0</description>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>INACTIVE</name>
+                                <value>0</value>
+                                <description>R_TX_EMPTY interrupt is inactive</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ACTIVE</name>
+                                <value>1</value>
+                                <description>R_TX_EMPTY interrupt is active</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>R_TX_OVER</name>
+                        <description>See IC_RAW_INTR_STAT for a detailed description of R_TX_OVER bit.
+
+                            Reset value: 0x0</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>INACTIVE</name>
+                                <value>0</value>
+                                <description>R_TX_OVER interrupt is inactive</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ACTIVE</name>
+                                <value>1</value>
+                                <description>R_TX_OVER interrupt is active</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>R_RX_FULL</name>
+                        <description>See IC_RAW_INTR_STAT for a detailed description of R_RX_FULL bit.
+
+                            Reset value: 0x0</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>INACTIVE</name>
+                                <value>0</value>
+                                <description>R_RX_FULL interrupt is inactive</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ACTIVE</name>
+                                <value>1</value>
+                                <description>R_RX_FULL interrupt is active</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>R_RX_OVER</name>
+                        <description>See IC_RAW_INTR_STAT for a detailed description of R_RX_OVER bit.
+
+                            Reset value: 0x0</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>INACTIVE</name>
+                                <value>0</value>
+                                <description>R_RX_OVER interrupt is inactive</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ACTIVE</name>
+                                <value>1</value>
+                                <description>R_RX_OVER interrupt is active</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>R_RX_UNDER</name>
+                        <description>See IC_RAW_INTR_STAT for a detailed description of R_RX_UNDER bit.
+
+                            Reset value: 0x0</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>INACTIVE</name>
+                                <value>0</value>
+                                <description>RX_UNDER interrupt is inactive</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ACTIVE</name>
+                                <value>1</value>
+                                <description>RX_UNDER interrupt is active</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>IC_INTR_MASK</name>
+                <addressOffset>0x00000030</addressOffset>
+                <description>I2C Interrupt Mask Register.
+
+                    These bits mask their corresponding interrupt status bits. This register is active low; a value of 0 masks the interrupt, whereas a value of 1 unmasks the interrupt.</description>
+                <resetValue>0x000008ff</resetValue>
+                <fields>
+                    <field>
+                        <name>M_RESTART_DET</name>
+                        <description>This bit masks the R_RESTART_DET interrupt in IC_INTR_STAT register.
+
+                            Reset value: 0x0</description>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>ENABLED</name>
+                                <value>0</value>
+                                <description>RESTART_DET interrupt is masked</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>DISABLED</name>
+                                <value>1</value>
+                                <description>RESTART_DET interrupt is unmasked</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>M_GEN_CALL</name>
+                        <description>This bit masks the R_GEN_CALL interrupt in IC_INTR_STAT register.
+
+                            Reset value: 0x1</description>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>ENABLED</name>
+                                <value>0</value>
+                                <description>GEN_CALL interrupt is masked</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>DISABLED</name>
+                                <value>1</value>
+                                <description>GEN_CALL interrupt is unmasked</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>M_START_DET</name>
+                        <description>This bit masks the R_START_DET interrupt in IC_INTR_STAT register.
+
+                            Reset value: 0x0</description>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>ENABLED</name>
+                                <value>0</value>
+                                <description>START_DET interrupt is masked</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>DISABLED</name>
+                                <value>1</value>
+                                <description>START_DET interrupt is unmasked</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>M_STOP_DET</name>
+                        <description>This bit masks the R_STOP_DET interrupt in IC_INTR_STAT register.
+
+                            Reset value: 0x0</description>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>ENABLED</name>
+                                <value>0</value>
+                                <description>STOP_DET interrupt is masked</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>DISABLED</name>
+                                <value>1</value>
+                                <description>STOP_DET interrupt is unmasked</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>M_ACTIVITY</name>
+                        <description>This bit masks the R_ACTIVITY interrupt in IC_INTR_STAT register.
+
+                            Reset value: 0x0</description>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>ENABLED</name>
+                                <value>0</value>
+                                <description>ACTIVITY interrupt is masked</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>DISABLED</name>
+                                <value>1</value>
+                                <description>ACTIVITY interrupt is unmasked</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>M_RX_DONE</name>
+                        <description>This bit masks the R_RX_DONE interrupt in IC_INTR_STAT register.
+
+                            Reset value: 0x1</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>ENABLED</name>
+                                <value>0</value>
+                                <description>RX_DONE interrupt is masked</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>DISABLED</name>
+                                <value>1</value>
+                                <description>RX_DONE interrupt is unmasked</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>M_TX_ABRT</name>
+                        <description>This bit masks the R_TX_ABRT interrupt in IC_INTR_STAT register.
+
+                            Reset value: 0x1</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>ENABLED</name>
+                                <value>0</value>
+                                <description>TX_ABORT interrupt is masked</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>DISABLED</name>
+                                <value>1</value>
+                                <description>TX_ABORT interrupt is unmasked</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>M_RD_REQ</name>
+                        <description>This bit masks the R_RD_REQ interrupt in IC_INTR_STAT register.
+
+                            Reset value: 0x1</description>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>ENABLED</name>
+                                <value>0</value>
+                                <description>RD_REQ interrupt is masked</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>DISABLED</name>
+                                <value>1</value>
+                                <description>RD_REQ interrupt is unmasked</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>M_TX_EMPTY</name>
+                        <description>This bit masks the R_TX_EMPTY interrupt in IC_INTR_STAT register.
+
+                            Reset value: 0x1</description>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>ENABLED</name>
+                                <value>0</value>
+                                <description>TX_EMPTY interrupt is masked</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>DISABLED</name>
+                                <value>1</value>
+                                <description>TX_EMPTY interrupt is unmasked</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>M_TX_OVER</name>
+                        <description>This bit masks the R_TX_OVER interrupt in IC_INTR_STAT register.
+
+                            Reset value: 0x1</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>ENABLED</name>
+                                <value>0</value>
+                                <description>TX_OVER interrupt is masked</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>DISABLED</name>
+                                <value>1</value>
+                                <description>TX_OVER interrupt is unmasked</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>M_RX_FULL</name>
+                        <description>This bit masks the R_RX_FULL interrupt in IC_INTR_STAT register.
+
+                            Reset value: 0x1</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>ENABLED</name>
+                                <value>0</value>
+                                <description>RX_FULL interrupt is masked</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>DISABLED</name>
+                                <value>1</value>
+                                <description>RX_FULL interrupt is unmasked</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>M_RX_OVER</name>
+                        <description>This bit masks the R_RX_OVER interrupt in IC_INTR_STAT register.
+
+                            Reset value: 0x1</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>ENABLED</name>
+                                <value>0</value>
+                                <description>RX_OVER interrupt is masked</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>DISABLED</name>
+                                <value>1</value>
+                                <description>RX_OVER interrupt is unmasked</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>M_RX_UNDER</name>
+                        <description>This bit masks the R_RX_UNDER interrupt in IC_INTR_STAT register.
+
+                            Reset value: 0x1</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>ENABLED</name>
+                                <value>0</value>
+                                <description>RX_UNDER interrupt is masked</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>DISABLED</name>
+                                <value>1</value>
+                                <description>RX_UNDER interrupt is unmasked</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>IC_RAW_INTR_STAT</name>
+                <addressOffset>0x00000034</addressOffset>
+                <description>I2C Raw Interrupt Status Register
+
+                    Unlike the IC_INTR_STAT register, these bits are not masked so they always show the true status of the DW_apb_i2c.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>RESTART_DET</name>
+                        <description>Indicates whether a RESTART condition has occurred on the I2C interface when DW_apb_i2c is operating in Slave mode and the slave is being addressed. Enabled only when IC_SLV_RESTART_DET_EN=1.
+
+                            Note: However, in high-speed mode or during a START BYTE transfer, the RESTART comes before the address field as per the I2C protocol. In this case, the slave is not the addressed slave when the RESTART is issued, therefore DW_apb_i2c does not generate the RESTART_DET interrupt.
+
+                            Reset value: 0x0</description>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>INACTIVE</name>
+                                <value>0</value>
+                                <description>RESTART_DET interrupt is inactive</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ACTIVE</name>
+                                <value>1</value>
+                                <description>RESTART_DET interrupt is active</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>GEN_CALL</name>
+                        <description>Set only when a General Call address is received and it is acknowledged. It stays set until it is cleared either by disabling DW_apb_i2c or when the CPU reads bit 0 of the IC_CLR_GEN_CALL register. DW_apb_i2c stores the received data in the Rx buffer.
+
+                            Reset value: 0x0</description>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>INACTIVE</name>
+                                <value>0</value>
+                                <description>GEN_CALL interrupt is inactive</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ACTIVE</name>
+                                <value>1</value>
+                                <description>GEN_CALL interrupt is active</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>START_DET</name>
+                        <description>Indicates whether a START or RESTART condition has occurred on the I2C interface regardless of whether DW_apb_i2c is operating in slave or master mode.
+
+                            Reset value: 0x0</description>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>INACTIVE</name>
+                                <value>0</value>
+                                <description>START_DET interrupt is inactive</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ACTIVE</name>
+                                <value>1</value>
+                                <description>START_DET interrupt is active</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>STOP_DET</name>
+                        <description>Indicates whether a STOP condition has occurred on the I2C interface regardless of whether DW_apb_i2c is operating in slave or master mode.
+
+                            In Slave Mode: - If IC_CON[7]=1&#39;b1  (STOP_DET_IFADDRESSED), the STOP_DET interrupt will be issued only if slave is addressed. Note: During a general call address, this slave does not issue a STOP_DET interrupt if STOP_DET_IF_ADDRESSED=1&#39;b1, even if the slave responds to the general call address by generating ACK. The STOP_DET interrupt is generated only when the transmitted address matches the slave address (SAR). - If IC_CON[7]=1&#39;b0 (STOP_DET_IFADDRESSED), the STOP_DET interrupt is issued irrespective of whether it is being addressed. In Master Mode: - If IC_CON[10]=1&#39;b1  (STOP_DET_IF_MASTER_ACTIVE),the STOP_DET interrupt will be issued only if Master is active. - If IC_CON[10]=1&#39;b0  (STOP_DET_IFADDRESSED),the STOP_DET interrupt will be issued irrespective of whether master is active or not. Reset value: 0x0</description>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>INACTIVE</name>
+                                <value>0</value>
+                                <description>STOP_DET interrupt is inactive</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ACTIVE</name>
+                                <value>1</value>
+                                <description>STOP_DET interrupt is active</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>ACTIVITY</name>
+                        <description>This bit captures DW_apb_i2c activity and stays set until it is cleared. There are four ways to clear it: - Disabling the DW_apb_i2c - Reading the IC_CLR_ACTIVITY register - Reading the IC_CLR_INTR register - System reset Once this bit is set, it stays set unless one of the four methods is used to clear it. Even if the DW_apb_i2c module is idle, this bit remains set until cleared, indicating that there was activity on the bus.
+
+                            Reset value: 0x0</description>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>INACTIVE</name>
+                                <value>0</value>
+                                <description>RAW_INTR_ACTIVITY interrupt is inactive</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ACTIVE</name>
+                                <value>1</value>
+                                <description>RAW_INTR_ACTIVITY interrupt is active</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>RX_DONE</name>
+                        <description>When the DW_apb_i2c is acting as a slave-transmitter, this bit is set to 1 if the master does not acknowledge a transmitted byte. This occurs on the last byte of the transmission, indicating that the transmission is done.
+
+                            Reset value: 0x0</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>INACTIVE</name>
+                                <value>0</value>
+                                <description>RX_DONE interrupt is inactive</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ACTIVE</name>
+                                <value>1</value>
+                                <description>RX_DONE interrupt is active</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>TX_ABRT</name>
+                        <description>This bit indicates if DW_apb_i2c, as an I2C transmitter, is unable to complete the intended actions on the contents of the transmit FIFO. This situation can occur both as an I2C master or an I2C slave, and is referred to as a &#39;transmit abort&#39;. When this bit is set to 1, the IC_TX_ABRT_SOURCE register indicates the reason why the transmit abort takes places.
+
+                            Note:  The DW_apb_i2c flushes/resets/empties the TX_FIFO and RX_FIFO whenever there is a transmit abort caused by any of the events tracked by the IC_TX_ABRT_SOURCE register. The FIFOs remains in this flushed state until the register IC_CLR_TX_ABRT is read. Once this read is performed, the Tx FIFO is then ready to accept more data bytes from the APB interface.
+
+                            Reset value: 0x0</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>INACTIVE</name>
+                                <value>0</value>
+                                <description>TX_ABRT interrupt is inactive</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ACTIVE</name>
+                                <value>1</value>
+                                <description>TX_ABRT interrupt is active</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>RD_REQ</name>
+                        <description>This bit is set to 1 when DW_apb_i2c is acting as a slave and another I2C master is attempting to read data from DW_apb_i2c. The DW_apb_i2c holds the I2C bus in a wait state (SCL=0) until this interrupt is serviced, which means that the slave has been addressed by a remote master that is asking for data to be transferred. The processor must respond to this interrupt and then write the requested data to the IC_DATA_CMD register. This bit is set to 0 just after the processor reads the IC_CLR_RD_REQ register.
+
+                            Reset value: 0x0</description>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>INACTIVE</name>
+                                <value>0</value>
+                                <description>RD_REQ interrupt is inactive</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ACTIVE</name>
+                                <value>1</value>
+                                <description>RD_REQ interrupt is active</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>TX_EMPTY</name>
+                        <description>The behavior of the TX_EMPTY interrupt status differs based on the TX_EMPTY_CTRL selection in the IC_CON register. - When TX_EMPTY_CTRL = 0: This bit is set to 1 when the transmit buffer is at or below the threshold value set in the IC_TX_TL register. - When TX_EMPTY_CTRL = 1: This bit is set to 1 when the transmit buffer is at or below the threshold value set in the IC_TX_TL register and the transmission of the address/data from the internal shift register for the most recently popped command is completed. It is automatically cleared by hardware when the buffer level goes above the threshold. When IC_ENABLE[0] is set to 0, the TX FIFO is flushed and held in reset. There the TX FIFO looks like it has no data within it, so this bit is set to 1, provided there is activity in the master or slave state machines. When there is no longer any activity, then with ic_en=0, this bit is set to 0.
+
+                            Reset value: 0x0.</description>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>INACTIVE</name>
+                                <value>0</value>
+                                <description>TX_EMPTY interrupt is inactive</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ACTIVE</name>
+                                <value>1</value>
+                                <description>TX_EMPTY interrupt is active</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>TX_OVER</name>
+                        <description>Set during transmit if the transmit buffer is filled to IC_TX_BUFFER_DEPTH and the processor attempts to issue another I2C command by writing to the IC_DATA_CMD register. When the module is disabled, this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared.
+
+                            Reset value: 0x0</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>INACTIVE</name>
+                                <value>0</value>
+                                <description>TX_OVER interrupt is inactive</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ACTIVE</name>
+                                <value>1</value>
+                                <description>TX_OVER interrupt is active</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>RX_FULL</name>
+                        <description>Set when the receive buffer reaches or goes above the RX_TL threshold in the IC_RX_TL register. It is automatically cleared by hardware when buffer level goes below the threshold. If the module is disabled (IC_ENABLE[0]=0), the RX FIFO is flushed and held in reset; therefore the RX FIFO is not full. So this bit is cleared once the IC_ENABLE bit 0 is programmed with a 0, regardless of the activity that continues.
+
+                            Reset value: 0x0</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>INACTIVE</name>
+                                <value>0</value>
+                                <description>RX_FULL interrupt is inactive</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ACTIVE</name>
+                                <value>1</value>
+                                <description>RX_FULL interrupt is active</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>RX_OVER</name>
+                        <description>Set if the receive buffer is completely filled to IC_RX_BUFFER_DEPTH and an additional byte is received from an external I2C device. The DW_apb_i2c acknowledges this, but any data bytes received after the FIFO is full are lost. If the module is disabled (IC_ENABLE[0]=0), this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared.
+
+                            Note:  If bit 9 of the IC_CON register (RX_FIFO_FULL_HLD_CTRL) is programmed to HIGH, then the RX_OVER interrupt never occurs, because the Rx FIFO never overflows.
+
+                            Reset value: 0x0</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>INACTIVE</name>
+                                <value>0</value>
+                                <description>RX_OVER interrupt is inactive</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ACTIVE</name>
+                                <value>1</value>
+                                <description>RX_OVER interrupt is active</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>RX_UNDER</name>
+                        <description>Set if the processor attempts to read the receive buffer when it is empty by reading from the IC_DATA_CMD register. If the module is disabled (IC_ENABLE[0]=0), this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared.
+
+                            Reset value: 0x0</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>INACTIVE</name>
+                                <value>0</value>
+                                <description>RX_UNDER interrupt is inactive</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ACTIVE</name>
+                                <value>1</value>
+                                <description>RX_UNDER interrupt is active</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>IC_RX_TL</name>
+                <addressOffset>0x00000038</addressOffset>
+                <description>I2C Receive FIFO Threshold Register</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>RX_TL</name>
+                        <description>Receive FIFO Threshold Level.
+
+                            Controls the level of entries (or above) that triggers the RX_FULL interrupt (bit 2 in IC_RAW_INTR_STAT register). The valid range is 0-255, with the additional restriction that hardware does not allow this value to be set to a value larger than the depth of the buffer. If an attempt is made to do that, the actual value set will be the maximum depth of the buffer. A value of 0 sets the threshold for 1 entry, and a value of 255 sets the threshold for 256 entries.</description>
+                        <bitRange>[7:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>IC_TX_TL</name>
+                <addressOffset>0x0000003c</addressOffset>
+                <description>I2C Transmit FIFO Threshold Register</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>TX_TL</name>
+                        <description>Transmit FIFO Threshold Level.
+
+                            Controls the level of entries (or below) that trigger the TX_EMPTY interrupt (bit 4 in IC_RAW_INTR_STAT register). The valid range is 0-255, with the additional restriction that it may not be set to value larger than the depth of the buffer. If an attempt is made to do that, the actual value set will be the maximum depth of the buffer. A value of 0 sets the threshold for 0 entries, and a value of 255 sets the threshold for 255 entries.</description>
+                        <bitRange>[7:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>IC_CLR_INTR</name>
+                <addressOffset>0x00000040</addressOffset>
+                <description>Clear Combined and Individual Interrupt Register</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CLR_INTR</name>
+                        <description>Read this register to clear the combined interrupt, all individual interrupts, and the IC_TX_ABRT_SOURCE register. This bit does not clear hardware clearable interrupts but software clearable interrupts. Refer to Bit 9 of the IC_TX_ABRT_SOURCE register for an exception to clearing IC_TX_ABRT_SOURCE.
+
+                            Reset value: 0x0</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>IC_CLR_RX_UNDER</name>
+                <addressOffset>0x00000044</addressOffset>
+                <description>Clear RX_UNDER Interrupt Register</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CLR_RX_UNDER</name>
+                        <description>Read this register to clear the RX_UNDER interrupt (bit 0) of the IC_RAW_INTR_STAT register.
+
+                            Reset value: 0x0</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>IC_CLR_RX_OVER</name>
+                <addressOffset>0x00000048</addressOffset>
+                <description>Clear RX_OVER Interrupt Register</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CLR_RX_OVER</name>
+                        <description>Read this register to clear the RX_OVER interrupt (bit 1) of the IC_RAW_INTR_STAT register.
+
+                            Reset value: 0x0</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>IC_CLR_TX_OVER</name>
+                <addressOffset>0x0000004c</addressOffset>
+                <description>Clear TX_OVER Interrupt Register</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CLR_TX_OVER</name>
+                        <description>Read this register to clear the TX_OVER interrupt (bit 3) of the IC_RAW_INTR_STAT register.
+
+                            Reset value: 0x0</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>IC_CLR_RD_REQ</name>
+                <addressOffset>0x00000050</addressOffset>
+                <description>Clear RD_REQ Interrupt Register</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CLR_RD_REQ</name>
+                        <description>Read this register to clear the RD_REQ interrupt (bit 5) of the IC_RAW_INTR_STAT register.
+
+                            Reset value: 0x0</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>IC_CLR_TX_ABRT</name>
+                <addressOffset>0x00000054</addressOffset>
+                <description>Clear TX_ABRT Interrupt Register</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CLR_TX_ABRT</name>
+                        <description>Read this register to clear the TX_ABRT interrupt (bit 6) of the IC_RAW_INTR_STAT register, and the IC_TX_ABRT_SOURCE register. This also releases the TX FIFO from the flushed/reset state, allowing more writes to the TX FIFO. Refer to Bit 9 of the IC_TX_ABRT_SOURCE register for an exception to clearing IC_TX_ABRT_SOURCE.
+
+                            Reset value: 0x0</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>IC_CLR_RX_DONE</name>
+                <addressOffset>0x00000058</addressOffset>
+                <description>Clear RX_DONE Interrupt Register</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CLR_RX_DONE</name>
+                        <description>Read this register to clear the RX_DONE interrupt (bit 7) of the IC_RAW_INTR_STAT register.
+
+                            Reset value: 0x0</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>IC_CLR_ACTIVITY</name>
+                <addressOffset>0x0000005c</addressOffset>
+                <description>Clear ACTIVITY Interrupt Register</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CLR_ACTIVITY</name>
+                        <description>Reading this register clears the ACTIVITY interrupt if the I2C is not active anymore. If the I2C module is still active on the bus, the ACTIVITY interrupt bit continues to be set. It is automatically cleared by hardware if the module is disabled and if there is no further activity on the bus. The value read from this register to get status of the ACTIVITY interrupt (bit 8) of the IC_RAW_INTR_STAT register.
+
+                            Reset value: 0x0</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>IC_CLR_STOP_DET</name>
+                <addressOffset>0x00000060</addressOffset>
+                <description>Clear STOP_DET Interrupt Register</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CLR_STOP_DET</name>
+                        <description>Read this register to clear the STOP_DET interrupt (bit 9) of the IC_RAW_INTR_STAT register.
+
+                            Reset value: 0x0</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>IC_CLR_START_DET</name>
+                <addressOffset>0x00000064</addressOffset>
+                <description>Clear START_DET Interrupt Register</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CLR_START_DET</name>
+                        <description>Read this register to clear the START_DET interrupt (bit 10) of the IC_RAW_INTR_STAT register.
+
+                            Reset value: 0x0</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>IC_CLR_GEN_CALL</name>
+                <addressOffset>0x00000068</addressOffset>
+                <description>Clear GEN_CALL Interrupt Register</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CLR_GEN_CALL</name>
+                        <description>Read this register to clear the GEN_CALL interrupt (bit 11) of IC_RAW_INTR_STAT register.
+
+                            Reset value: 0x0</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>IC_ENABLE</name>
+                <addressOffset>0x0000006c</addressOffset>
+                <description>I2C Enable Register</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>TX_CMD_BLOCK</name>
+                        <description>In Master mode: - 1&#39;b1: Blocks the transmission of data on I2C bus even if Tx FIFO has data to transmit. - 1&#39;b0: The transmission of data starts on I2C bus automatically, as soon as the first data is available in the Tx FIFO. Note: To block the execution of Master commands, set the TX_CMD_BLOCK bit only when Tx FIFO is empty (IC_STATUS[2]==1) and Master is in Idle state (IC_STATUS[5] == 0). Any further commands put in the Tx FIFO are not executed until TX_CMD_BLOCK bit is unset. Reset value:  IC_TX_CMD_BLOCK_DEFAULT</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NOT_BLOCKED</name>
+                                <value>0</value>
+                                <description>Tx Command execution not blocked</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>BLOCKED</name>
+                                <value>1</value>
+                                <description>Tx Command execution blocked</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>ABORT</name>
+                        <description>When set, the controller initiates the transfer abort. - 0: ABORT not initiated or ABORT done - 1: ABORT operation in progress The software can abort the I2C transfer in master mode by setting this bit. The software can set this bit only when ENABLE is already set; otherwise, the controller ignores any write to ABORT bit. The software cannot clear the ABORT bit once set. In response to an ABORT, the controller issues a STOP and flushes the Tx FIFO after completing the current transfer, then sets the TX_ABORT interrupt after the abort operation. The ABORT bit is cleared automatically after the abort operation.
+
+                            For a detailed description on how to abort I2C transfers, refer to &#39;Aborting I2C Transfers&#39;.
+
+                            Reset value: 0x0</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>DISABLE</name>
+                                <value>0</value>
+                                <description>ABORT operation not in progress</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ENABLED</name>
+                                <value>1</value>
+                                <description>ABORT operation in progress</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>ENABLE</name>
+                        <description>Controls whether the DW_apb_i2c is enabled. - 0: Disables DW_apb_i2c (TX and RX FIFOs are held in an erased state) - 1: Enables DW_apb_i2c Software can disable DW_apb_i2c while it is active. However, it is important that care be taken to ensure that DW_apb_i2c is disabled properly. A recommended procedure is described in &#39;Disabling DW_apb_i2c&#39;.
+
+                            When DW_apb_i2c is disabled, the following occurs: - The TX FIFO and RX FIFO get flushed. - Status bits in the IC_INTR_STAT register are still active until DW_apb_i2c goes into IDLE state. If the module is transmitting, it stops as well as deletes the contents of the transmit buffer after the current transfer is complete. If the module is receiving, the DW_apb_i2c stops the current transfer at the end of the current byte and does not acknowledge the transfer.
+
+                            In systems with asynchronous pclk and ic_clk when IC_CLK_TYPE parameter set to asynchronous (1), there is a two ic_clk delay when enabling or disabling the DW_apb_i2c. For a detailed description on how to disable DW_apb_i2c, refer to &#39;Disabling DW_apb_i2c&#39;
+
+                            Reset value: 0x0</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>DISABLED</name>
+                                <value>0</value>
+                                <description>I2C is disabled</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ENABLED</name>
+                                <value>1</value>
+                                <description>I2C is enabled</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>IC_STATUS</name>
+                <addressOffset>0x00000070</addressOffset>
+                <description>I2C Status Register
+
+                    This is a read-only register used to indicate the current transfer status and FIFO status. The status register may be read at any time. None of the bits in this register request an interrupt.
+
+                    When the I2C is disabled by writing 0 in bit 0 of the IC_ENABLE register: - Bits 1 and 2 are set to 1 - Bits 3 and 10 are set to 0 When the master or slave state machines goes to idle and ic_en=0: - Bits 5 and 6 are set to 0</description>
+                <resetValue>0x00000006</resetValue>
+                <fields>
+                    <field>
+                        <name>SLV_ACTIVITY</name>
+                        <description>Slave FSM Activity Status. When the Slave Finite State Machine (FSM) is not in the IDLE state, this bit is set. - 0: Slave FSM is in IDLE state so the Slave part of DW_apb_i2c is not Active - 1: Slave FSM is not in IDLE state so the Slave part of DW_apb_i2c is Active Reset value: 0x0</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>IDLE</name>
+                                <value>0</value>
+                                <description>Slave is idle</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ACTIVE</name>
+                                <value>1</value>
+                                <description>Slave not idle</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>MST_ACTIVITY</name>
+                        <description>Master FSM Activity Status. When the Master Finite State Machine (FSM) is not in the IDLE state, this bit is set. - 0: Master FSM is in IDLE state so the Master part of DW_apb_i2c is not Active - 1: Master FSM is not in IDLE state so the Master part of DW_apb_i2c is Active Note: IC_STATUS[0]-that is, ACTIVITY bit-is the OR of SLV_ACTIVITY and MST_ACTIVITY bits.
+
+                            Reset value: 0x0</description>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>IDLE</name>
+                                <value>0</value>
+                                <description>Master is idle</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ACTIVE</name>
+                                <value>1</value>
+                                <description>Master not idle</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>RFF</name>
+                        <description>Receive FIFO Completely Full. When the receive FIFO is completely full, this bit is set. When the receive FIFO contains one or more empty location, this bit is cleared. - 0: Receive FIFO is not full - 1: Receive FIFO is full Reset value: 0x0</description>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NOT_FULL</name>
+                                <value>0</value>
+                                <description>Rx FIFO not full</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>FULL</name>
+                                <value>1</value>
+                                <description>Rx FIFO is full</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>RFNE</name>
+                        <description>Receive FIFO Not Empty. This bit is set when the receive FIFO contains one or more entries; it is cleared when the receive FIFO is empty. - 0: Receive FIFO is empty - 1: Receive FIFO is not empty Reset value: 0x0</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>EMPTY</name>
+                                <value>0</value>
+                                <description>Rx FIFO is empty</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>NOT_EMPTY</name>
+                                <value>1</value>
+                                <description>Rx FIFO not empty</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>TFE</name>
+                        <description>Transmit FIFO Completely Empty. When the transmit FIFO is completely empty, this bit is set. When it contains one or more valid entries, this bit is cleared. This bit field does not request an interrupt. - 0: Transmit FIFO is not empty - 1: Transmit FIFO is empty Reset value: 0x1</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NON_EMPTY</name>
+                                <value>0</value>
+                                <description>Tx FIFO not empty</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>EMPTY</name>
+                                <value>1</value>
+                                <description>Tx FIFO is empty</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>TFNF</name>
+                        <description>Transmit FIFO Not Full. Set when the transmit FIFO contains one or more empty locations, and is cleared when the FIFO is full. - 0: Transmit FIFO is full - 1: Transmit FIFO is not full Reset value: 0x1</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>FULL</name>
+                                <value>0</value>
+                                <description>Tx FIFO is full</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>NOT_FULL</name>
+                                <value>1</value>
+                                <description>Tx FIFO not full</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>ACTIVITY</name>
+                        <description>I2C Activity Status. Reset value: 0x0</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>INACTIVE</name>
+                                <value>0</value>
+                                <description>I2C is idle</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ACTIVE</name>
+                                <value>1</value>
+                                <description>I2C is active</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>IC_TXFLR</name>
+                <addressOffset>0x00000074</addressOffset>
+                <description>I2C Transmit FIFO Level Register This register contains the number of valid data entries in the transmit FIFO buffer. It is cleared whenever: - The I2C is disabled - There is a transmit abort - that is, TX_ABRT bit is set in the IC_RAW_INTR_STAT register - The slave bulk transmit mode is aborted The register increments whenever data is placed into the transmit FIFO and decrements when data is taken from the transmit FIFO.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>TXFLR</name>
+                        <description>Transmit FIFO Level. Contains the number of valid data entries in the transmit FIFO.
+
+                            Reset value: 0x0</description>
+                        <bitRange>[4:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>IC_RXFLR</name>
+                <addressOffset>0x00000078</addressOffset>
+                <description>I2C Receive FIFO Level Register This register contains the number of valid data entries in the receive FIFO buffer. It is cleared whenever: - The I2C is disabled - Whenever there is a transmit abort caused by any of the events tracked in IC_TX_ABRT_SOURCE The register increments whenever data is placed into the receive FIFO and decrements when data is taken from the receive FIFO.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>RXFLR</name>
+                        <description>Receive FIFO Level. Contains the number of valid data entries in the receive FIFO.
+
+                            Reset value: 0x0</description>
+                        <bitRange>[4:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>IC_SDA_HOLD</name>
+                <addressOffset>0x0000007c</addressOffset>
+                <description>I2C SDA Hold Time Length Register
+
+                    The bits [15:0] of this register are used to control the hold time of SDA during transmit in both slave and master mode (after SCL goes from HIGH to LOW).
+
+                    The bits [23:16] of this register are used to extend the SDA transition (if any) whenever SCL is HIGH in the receiver in either master or slave mode.
+
+                    Writes to this register succeed only when IC_ENABLE[0]=0.
+
+                    The values in this register are in units of ic_clk period. The value programmed in IC_SDA_TX_HOLD must be greater than the minimum hold time in each mode (one cycle in master mode, seven cycles in slave mode) for the value to be implemented.
+
+                    The programmed SDA hold time during transmit (IC_SDA_TX_HOLD) cannot exceed at any time the duration of the low part of scl. Therefore the programmed value cannot be larger than N_SCL_LOW-2, where N_SCL_LOW is the duration of the low part of the scl period measured in ic_clk cycles.</description>
+                <resetValue>0x00000001</resetValue>
+                <fields>
+                    <field>
+                        <name>IC_SDA_RX_HOLD</name>
+                        <description>Sets the required SDA hold time in units of ic_clk period, when DW_apb_i2c acts as a receiver.
+
+                            Reset value: IC_DEFAULT_SDA_HOLD[23:16].</description>
+                        <bitRange>[23:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>IC_SDA_TX_HOLD</name>
+                        <description>Sets the required SDA hold time in units of ic_clk period, when DW_apb_i2c acts as a transmitter.
+
+                            Reset value: IC_DEFAULT_SDA_HOLD[15:0].</description>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>IC_TX_ABRT_SOURCE</name>
+                <addressOffset>0x00000080</addressOffset>
+                <description>I2C Transmit Abort Source Register
+
+                    This register has 32 bits that indicate the source of the TX_ABRT bit. Except for Bit 9, this register is cleared whenever the IC_CLR_TX_ABRT register or the IC_CLR_INTR register is read. To clear Bit 9, the source of the ABRT_SBYTE_NORSTRT must be fixed first; RESTART must be enabled (IC_CON[5]=1), the SPECIAL bit must be cleared (IC_TAR[11]), or the GC_OR_START bit must be cleared (IC_TAR[10]).
+
+                    Once the source of the ABRT_SBYTE_NORSTRT is fixed, then this bit can be cleared in the same manner as other bits in this register. If the source of the ABRT_SBYTE_NORSTRT is not fixed before attempting to clear this bit, Bit 9 clears for one cycle and is then re-asserted.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>TX_FLUSH_CNT</name>
+                        <description>This field indicates the number of Tx FIFO Data Commands which are flushed due to TX_ABRT interrupt. It is cleared whenever I2C is disabled.
+
+                            Reset value: 0x0
+
+                            Role of DW_apb_i2c:  Master-Transmitter or Slave-Transmitter</description>
+                        <bitRange>[31:23]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>ABRT_USER_ABRT</name>
+                        <description>This is a master-mode-only bit. Master has detected the transfer abort (IC_ENABLE[1])
+
+                            Reset value: 0x0
+
+                            Role of DW_apb_i2c:  Master-Transmitter</description>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>ABRT_USER_ABRT_VOID</name>
+                                <value>0</value>
+                                <description>Transfer abort detected by master- scenario not present</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ABRT_USER_ABRT_GENERATED</name>
+                                <value>1</value>
+                                <description>Transfer abort detected by master</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>ABRT_SLVRD_INTX</name>
+                        <description>1: When the processor side responds to a slave mode request for data to be transmitted to a remote master and user writes a 1 in CMD (bit 8) of IC_DATA_CMD register.
+
+                            Reset value: 0x0
+
+                            Role of DW_apb_i2c:  Slave-Transmitter</description>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>ABRT_SLVRD_INTX_VOID</name>
+                                <value>0</value>
+                                <description>Slave trying to transmit to remote master in read mode- scenario not present</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ABRT_SLVRD_INTX_GENERATED</name>
+                                <value>1</value>
+                                <description>Slave trying to transmit to remote master in read mode</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>ABRT_SLV_ARBLOST</name>
+                        <description>This field indicates that a Slave has lost the bus while transmitting data to a remote master. IC_TX_ABRT_SOURCE[12] is set at the same time. Note:  Even though the slave never &#39;owns&#39; the bus, something could go wrong on the bus. This is a fail safe check. For instance, during a data transmission at the low-to-high transition of SCL, if what is on the data bus is not what is supposed to be transmitted, then DW_apb_i2c no longer own the bus.
+
+                            Reset value: 0x0
+
+                            Role of DW_apb_i2c:  Slave-Transmitter</description>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>ABRT_SLV_ARBLOST_VOID</name>
+                                <value>0</value>
+                                <description>Slave lost arbitration to remote master- scenario not present</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ABRT_SLV_ARBLOST_GENERATED</name>
+                                <value>1</value>
+                                <description>Slave lost arbitration to remote master</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>ABRT_SLVFLUSH_TXFIFO</name>
+                        <description>This field specifies that the Slave has received a read command and some data exists in the TX FIFO, so the slave issues a TX_ABRT interrupt to flush old data in TX FIFO.
+
+                            Reset value: 0x0
+
+                            Role of DW_apb_i2c:  Slave-Transmitter</description>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>ABRT_SLVFLUSH_TXFIFO_VOID</name>
+                                <value>0</value>
+                                <description>Slave flushes existing data in TX-FIFO upon getting read command- scenario not present</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ABRT_SLVFLUSH_TXFIFO_GENERATED</name>
+                                <value>1</value>
+                                <description>Slave flushes existing data in TX-FIFO upon getting read command</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>ARB_LOST</name>
+                        <description>This field specifies that the Master has lost arbitration, or if IC_TX_ABRT_SOURCE[14] is also set, then the slave transmitter has lost arbitration.
+
+                            Reset value: 0x0
+
+                            Role of DW_apb_i2c:  Master-Transmitter or Slave-Transmitter</description>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>ABRT_LOST_VOID</name>
+                                <value>0</value>
+                                <description>Master or Slave-Transmitter lost arbitration- scenario not present</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ABRT_LOST_GENERATED</name>
+                                <value>1</value>
+                                <description>Master or Slave-Transmitter lost arbitration</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>ABRT_MASTER_DIS</name>
+                        <description>This field indicates that the User tries to initiate a Master operation with the Master mode disabled.
+
+                            Reset value: 0x0
+
+                            Role of DW_apb_i2c:  Master-Transmitter or Master-Receiver</description>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>ABRT_MASTER_DIS_VOID</name>
+                                <value>0</value>
+                                <description>User initiating master operation when MASTER disabled- scenario not present</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ABRT_MASTER_DIS_GENERATED</name>
+                                <value>1</value>
+                                <description>User initiating master operation when MASTER disabled</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>ABRT_10B_RD_NORSTRT</name>
+                        <description>This field indicates that the restart is disabled (IC_RESTART_EN bit (IC_CON[5]) =0) and the master sends a read command in 10-bit addressing mode.
+
+                            Reset value: 0x0
+
+                            Role of DW_apb_i2c:  Master-Receiver</description>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>ABRT_10B_RD_VOID</name>
+                                <value>0</value>
+                                <description>Master not trying to read in 10Bit addressing mode when RESTART disabled</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ABRT_10B_RD_GENERATED</name>
+                                <value>1</value>
+                                <description>Master trying to read in 10Bit addressing mode when RESTART disabled</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>ABRT_SBYTE_NORSTRT</name>
+                        <description>To clear Bit 9, the source of the ABRT_SBYTE_NORSTRT must be fixed first; restart must be enabled (IC_CON[5]=1), the SPECIAL bit must be cleared (IC_TAR[11]), or the GC_OR_START bit must be cleared (IC_TAR[10]). Once the source of the ABRT_SBYTE_NORSTRT is fixed, then this bit can be cleared in the same manner as other bits in this register. If the source of the ABRT_SBYTE_NORSTRT is not fixed before attempting to clear this bit, bit 9 clears for one cycle and then gets reasserted. When this field is set to 1, the restart is disabled (IC_RESTART_EN bit (IC_CON[5]) =0) and the user is trying to send a START Byte.
+
+                            Reset value: 0x0
+
+                            Role of DW_apb_i2c:  Master</description>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>ABRT_SBYTE_NORSTRT_VOID</name>
+                                <value>0</value>
+                                <description>User trying to send START byte when RESTART disabled- scenario not present</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ABRT_SBYTE_NORSTRT_GENERATED</name>
+                                <value>1</value>
+                                <description>User trying to send START byte when RESTART disabled</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>ABRT_HS_NORSTRT</name>
+                        <description>This field indicates that the restart is disabled (IC_RESTART_EN bit (IC_CON[5]) =0) and the user is trying to use the master to transfer data in High Speed mode.
+
+                            Reset value: 0x0
+
+                            Role of DW_apb_i2c:  Master-Transmitter or Master-Receiver</description>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>ABRT_HS_NORSTRT_VOID</name>
+                                <value>0</value>
+                                <description>User trying to switch Master to HS mode when RESTART disabled- scenario not present</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ABRT_HS_NORSTRT_GENERATED</name>
+                                <value>1</value>
+                                <description>User trying to switch Master to HS mode when RESTART disabled</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>ABRT_SBYTE_ACKDET</name>
+                        <description>This field indicates that the Master has sent a START Byte and the START Byte was acknowledged (wrong behavior).
+
+                            Reset value: 0x0
+
+                            Role of DW_apb_i2c:  Master</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>ABRT_SBYTE_ACKDET_VOID</name>
+                                <value>0</value>
+                                <description>ACK detected for START byte- scenario not present</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ABRT_SBYTE_ACKDET_GENERATED</name>
+                                <value>1</value>
+                                <description>ACK detected for START byte</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>ABRT_HS_ACKDET</name>
+                        <description>This field indicates that the Master is in High Speed mode and the High Speed Master code was acknowledged (wrong behavior).
+
+                            Reset value: 0x0
+
+                            Role of DW_apb_i2c:  Master</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>ABRT_HS_ACK_VOID</name>
+                                <value>0</value>
+                                <description>HS Master code ACKed in HS Mode- scenario not present</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ABRT_HS_ACK_GENERATED</name>
+                                <value>1</value>
+                                <description>HS Master code ACKed in HS Mode</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>ABRT_GCALL_READ</name>
+                        <description>This field indicates that DW_apb_i2c in the master mode has sent a General Call but the user programmed the byte following the General Call to be a read from the bus (IC_DATA_CMD[9] is set to 1).
+
+                            Reset value: 0x0
+
+                            Role of DW_apb_i2c:  Master-Transmitter</description>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>ABRT_GCALL_READ_VOID</name>
+                                <value>0</value>
+                                <description>GCALL is followed by read from bus-scenario not present</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ABRT_GCALL_READ_GENERATED</name>
+                                <value>1</value>
+                                <description>GCALL is followed by read from bus</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>ABRT_GCALL_NOACK</name>
+                        <description>This field indicates that DW_apb_i2c in master mode has sent a General Call and no slave on the bus acknowledged the General Call.
+
+                            Reset value: 0x0
+
+                            Role of DW_apb_i2c:  Master-Transmitter</description>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>ABRT_GCALL_NOACK_VOID</name>
+                                <value>0</value>
+                                <description>GCALL not ACKed by any slave-scenario not present</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ABRT_GCALL_NOACK_GENERATED</name>
+                                <value>1</value>
+                                <description>GCALL not ACKed by any slave</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>ABRT_TXDATA_NOACK</name>
+                        <description>This field indicates the master-mode only bit. When the master receives an acknowledgement for the address, but when it sends data byte(s) following the address, it did not receive an acknowledge from the remote slave(s).
+
+                            Reset value: 0x0
+
+                            Role of DW_apb_i2c:  Master-Transmitter</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>ABRT_TXDATA_NOACK_VOID</name>
+                                <value>0</value>
+                                <description>Transmitted data non-ACKed by addressed slave-scenario not present</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ABRT_TXDATA_NOACK_GENERATED</name>
+                                <value>1</value>
+                                <description>Transmitted data not ACKed by addressed slave</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>ABRT_10ADDR2_NOACK</name>
+                        <description>This field indicates that the Master is in 10-bit address mode and that the second address byte of the 10-bit address was not acknowledged by any slave.
+
+                            Reset value: 0x0
+
+                            Role of DW_apb_i2c:  Master-Transmitter or Master-Receiver</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>INACTIVE</name>
+                                <value>0</value>
+                                <description>This abort is not generated</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ACTIVE</name>
+                                <value>1</value>
+                                <description>Byte 2 of 10Bit Address not ACKed by any slave</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>ABRT_10ADDR1_NOACK</name>
+                        <description>This field indicates that the Master is in 10-bit address mode and the first 10-bit address byte was not acknowledged by any slave.
+
+                            Reset value: 0x0
+
+                            Role of DW_apb_i2c:  Master-Transmitter or Master-Receiver</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>INACTIVE</name>
+                                <value>0</value>
+                                <description>This abort is not generated</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ACTIVE</name>
+                                <value>1</value>
+                                <description>Byte 1 of 10Bit Address not ACKed by any slave</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>ABRT_7B_ADDR_NOACK</name>
+                        <description>This field indicates that the Master is in 7-bit addressing mode and the address sent was not acknowledged by any slave.
+
+                            Reset value: 0x0
+
+                            Role of DW_apb_i2c:  Master-Transmitter or Master-Receiver</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>INACTIVE</name>
+                                <value>0</value>
+                                <description>This abort is not generated</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ACTIVE</name>
+                                <value>1</value>
+                                <description>This abort is generated because of NOACK for 7-bit address</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>IC_SLV_DATA_NACK_ONLY</name>
+                <addressOffset>0x00000084</addressOffset>
+                <description>Generate Slave Data NACK Register
+
+                    The register is used to generate a NACK for the data part of a transfer when DW_apb_i2c is acting as a slave-receiver. This register only exists when the IC_SLV_DATA_NACK_ONLY parameter is set to 1. When this parameter disabled, this register does not exist and writing to the register&#39;s address has no effect.
+
+                    A write can occur on this register if both of the following conditions are met: - DW_apb_i2c is disabled (IC_ENABLE[0] = 0) - Slave part is inactive (IC_STATUS[6] = 0) Note: The IC_STATUS[6] is a register read-back location for the internal slv_activity signal; the user should poll this before writing the ic_slv_data_nack_only bit.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>NACK</name>
+                        <description>Generate NACK. This NACK generation only occurs when DW_apb_i2c is a slave-receiver. If this register is set to a value of 1, it can only generate a NACK after a data byte is received; hence, the data transfer is aborted and the data received is not pushed to the receive buffer.
+
+                            When the register is set to a value of 0, it generates NACK/ACK, depending on normal criteria. - 1: generate NACK after data byte received - 0: generate NACK/ACK normally Reset value: 0x0</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>DISABLED</name>
+                                <value>0</value>
+                                <description>Slave receiver generates NACK normally</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ENABLED</name>
+                                <value>1</value>
+                                <description>Slave receiver generates NACK upon data reception only</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>IC_DMA_CR</name>
+                <addressOffset>0x00000088</addressOffset>
+                <description>DMA Control Register
+
+                    The register is used to enable the DMA Controller interface operation. There is a separate bit for transmit and receive. This can be programmed regardless of the state of IC_ENABLE.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>TDMAE</name>
+                        <description>Transmit DMA Enable. This bit enables/disables the transmit FIFO DMA channel. Reset value: 0x0</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>DISABLED</name>
+                                <value>0</value>
+                                <description>transmit FIFO DMA channel disabled</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ENABLED</name>
+                                <value>1</value>
+                                <description>Transmit FIFO DMA channel enabled</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>RDMAE</name>
+                        <description>Receive DMA Enable. This bit enables/disables the receive FIFO DMA channel. Reset value: 0x0</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>DISABLED</name>
+                                <value>0</value>
+                                <description>Receive FIFO DMA channel disabled</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ENABLED</name>
+                                <value>1</value>
+                                <description>Receive FIFO DMA channel enabled</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>IC_DMA_TDLR</name>
+                <addressOffset>0x0000008c</addressOffset>
+                <description>DMA Transmit Data Level Register</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>DMATDL</name>
+                        <description>Transmit Data Level. This bit field controls the level at which a DMA request is made by the transmit logic. It is equal to the watermark level; that is, the dma_tx_req signal is generated when the number of valid data entries in the transmit FIFO is equal to or below this field value, and TDMAE = 1.
+
+                            Reset value: 0x0</description>
+                        <bitRange>[3:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>IC_DMA_RDLR</name>
+                <addressOffset>0x00000090</addressOffset>
+                <description>I2C Receive Data Level Register</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>DMARDL</name>
+                        <description>Receive Data Level. This bit field controls the level at which a DMA request is made by the receive logic. The watermark level = DMARDL+1; that is, dma_rx_req is generated when the number of valid data entries in the receive FIFO is equal to or more than this field value + 1, and RDMAE =1. For instance, when DMARDL is 0, then dma_rx_req is asserted when 1 or more data entries are present in the receive FIFO.
+
+                            Reset value: 0x0</description>
+                        <bitRange>[3:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>IC_SDA_SETUP</name>
+                <addressOffset>0x00000094</addressOffset>
+                <description>I2C SDA Setup Register
+
+                    This register controls the amount of time delay (in terms of number of ic_clk clock periods) introduced in the rising edge of SCL - relative to SDA changing - when DW_apb_i2c services a read request in a slave-transmitter operation. The relevant I2C requirement is tSU:DAT (note 4) as detailed in the I2C Bus Specification. This register must be programmed with a value equal to or greater than 2.
+
+                    Writes to this register succeed only when IC_ENABLE[0] = 0.
+
+                    Note: The length of setup time is calculated using [(IC_SDA_SETUP - 1) * (ic_clk_period)], so if the user requires 10 ic_clk periods of setup time, they should program a value of 11. The IC_SDA_SETUP register is only used by the DW_apb_i2c when operating as a slave transmitter.</description>
+                <resetValue>0x00000064</resetValue>
+                <fields>
+                    <field>
+                        <name>SDA_SETUP</name>
+                        <description>SDA Setup. It is recommended that if the required delay is 1000ns, then for an ic_clk frequency of 10 MHz, IC_SDA_SETUP should be programmed to a value of 11. IC_SDA_SETUP must be programmed with a minimum value of 2.</description>
+                        <bitRange>[7:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>IC_ACK_GENERAL_CALL</name>
+                <addressOffset>0x00000098</addressOffset>
+                <description>I2C ACK General Call Register
+
+                    The register controls whether DW_apb_i2c responds with a ACK or NACK when it receives an I2C General Call address.
+
+                    This register is applicable only when the DW_apb_i2c is in slave mode.</description>
+                <resetValue>0x00000001</resetValue>
+                <fields>
+                    <field>
+                        <name>ACK_GEN_CALL</name>
+                        <description>ACK General Call. When set to 1, DW_apb_i2c responds with a ACK (by asserting ic_data_oe) when it receives a General Call. Otherwise, DW_apb_i2c responds with a NACK (by negating ic_data_oe).</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>DISABLED</name>
+                                <value>0</value>
+                                <description>Generate NACK for a General Call</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ENABLED</name>
+                                <value>1</value>
+                                <description>Generate ACK for a General Call</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>IC_ENABLE_STATUS</name>
+                <addressOffset>0x0000009c</addressOffset>
+                <description>I2C Enable Status Register
+
+                    The register is used to report the DW_apb_i2c hardware status when the IC_ENABLE[0] register is set from 1 to 0; that is, when DW_apb_i2c is disabled.
+
+                    If IC_ENABLE[0] has been set to 1, bits 2:1 are forced to 0, and bit 0 is forced to 1.
+
+                    If IC_ENABLE[0] has been set to 0, bits 2:1 is only be valid as soon as bit 0 is read as &#39;0&#39;.
+
+                    Note: When IC_ENABLE[0] has been set to 0, a delay occurs for bit 0 to be read as 0 because disabling the DW_apb_i2c depends on I2C bus activities.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>SLV_RX_DATA_LOST</name>
+                        <description>Slave Received Data Lost. This bit indicates if a Slave-Receiver operation has been aborted with at least one data byte received from an I2C transfer due to the setting bit 0 of IC_ENABLE from 1 to 0. When read as 1, DW_apb_i2c is deemed to have been actively engaged in an aborted I2C transfer (with matching address) and the data phase of the I2C transfer has been entered, even though a data byte has been responded with a NACK.
+
+                            Note:  If the remote I2C master terminates the transfer with a STOP condition before the DW_apb_i2c has a chance to NACK a transfer, and IC_ENABLE[0] has been set to 0, then this bit is also set to 1.
+
+                            When read as 0, DW_apb_i2c is deemed to have been disabled without being actively involved in the data phase of a Slave-Receiver transfer.
+
+                            Note:  The CPU can safely read this bit when IC_EN (bit 0) is read as 0.
+
+                            Reset value: 0x0</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>INACTIVE</name>
+                                <value>0</value>
+                                <description>Slave RX Data is not lost</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ACTIVE</name>
+                                <value>1</value>
+                                <description>Slave RX Data is lost</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>SLV_DISABLED_WHILE_BUSY</name>
+                        <description>Slave Disabled While Busy (Transmit, Receive). This bit indicates if a potential or active Slave operation has been aborted due to the setting bit 0 of the IC_ENABLE register from 1 to 0. This bit is set when the CPU writes a 0 to the IC_ENABLE register while:
+
+                            (a) DW_apb_i2c is receiving the address byte of the Slave-Transmitter operation from a remote master;
+
+                            OR,
+
+                            (b) address and data bytes of the Slave-Receiver operation from a remote master.
+
+                            When read as 1, DW_apb_i2c is deemed to have forced a NACK during any part of an I2C transfer, irrespective of whether the I2C address matches the slave address set in DW_apb_i2c (IC_SAR register) OR if the transfer is completed before IC_ENABLE is set to 0 but has not taken effect.
+
+                            Note:  If the remote I2C master terminates the transfer with a STOP condition before the DW_apb_i2c has a chance to NACK a transfer, and IC_ENABLE[0] has been set to 0, then this bit will also be set to 1.
+
+                            When read as 0, DW_apb_i2c is deemed to have been disabled when there is master activity, or when the I2C bus is idle.
+
+                            Note:  The CPU can safely read this bit when IC_EN (bit 0) is read as 0.
+
+                            Reset value: 0x0</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>INACTIVE</name>
+                                <value>0</value>
+                                <description>Slave is disabled when it is idle</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ACTIVE</name>
+                                <value>1</value>
+                                <description>Slave is disabled when it is active</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>IC_EN</name>
+                        <description>ic_en Status. This bit always reflects the value driven on the output port ic_en. - When read as 1, DW_apb_i2c is deemed to be in an enabled state. - When read as 0, DW_apb_i2c is deemed completely inactive. Note:  The CPU can safely read this bit anytime. When this bit is read as 0, the CPU can safely read SLV_RX_DATA_LOST (bit 2) and SLV_DISABLED_WHILE_BUSY (bit 1).
+
+                            Reset value: 0x0</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>DISABLED</name>
+                                <value>0</value>
+                                <description>I2C disabled</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ENABLED</name>
+                                <value>1</value>
+                                <description>I2C enabled</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>IC_FS_SPKLEN</name>
+                <addressOffset>0x000000a0</addressOffset>
+                <description>I2C SS, FS or FM+ spike suppression limit
+
+                    This register is used to store the duration, measured in ic_clk cycles, of the longest spike that is filtered out by the spike suppression logic when the component is operating in SS, FS or FM+ modes. The relevant I2C requirement is tSP (table 4) as detailed in the I2C Bus Specification. This register must be programmed with a minimum value of 1.</description>
+                <resetValue>0x00000007</resetValue>
+                <fields>
+                    <field>
+                        <name>IC_FS_SPKLEN</name>
+                        <description>This register must be set before any I2C bus transaction can take place to ensure stable operation. This register sets the duration, measured in ic_clk cycles, of the longest spike in the SCL or SDA lines that will be filtered out by the spike suppression logic. This register can be written only when the I2C interface is disabled which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect. The minimum valid value is 1; hardware prevents values less than this being written, and if attempted results in 1 being set. or more information, refer to &#39;Spike Suppression&#39;.</description>
+                        <bitRange>[7:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>IC_CLR_RESTART_DET</name>
+                <addressOffset>0x000000a8</addressOffset>
+                <description>Clear RESTART_DET Interrupt Register</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CLR_RESTART_DET</name>
+                        <description>Read this register to clear the RESTART_DET interrupt (bit 12) of IC_RAW_INTR_STAT register.
+
+                            Reset value: 0x0</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>IC_COMP_PARAM_1</name>
+                <addressOffset>0x000000f4</addressOffset>
+                <description>Component Parameter Register 1
+
+                    Note This register is not implemented and therefore reads as 0. If it was implemented it would be a constant read-only register that contains encoded information about the component&#39;s parameter settings. Fields shown below are the settings for those parameters</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>TX_BUFFER_DEPTH</name>
+                        <description>TX Buffer Depth = 16</description>
+                        <bitRange>[23:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>RX_BUFFER_DEPTH</name>
+                        <description>RX Buffer Depth = 16</description>
+                        <bitRange>[15:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>ADD_ENCODED_PARAMS</name>
+                        <description>Encoded parameters not visible</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>HAS_DMA</name>
+                        <description>DMA handshaking signals are enabled</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>INTR_IO</name>
+                        <description>COMBINED Interrupt outputs</description>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>HC_COUNT_VALUES</name>
+                        <description>Programmable count values for each mode.</description>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>MAX_SPEED_MODE</name>
+                        <description>MAX SPEED MODE = FAST MODE</description>
+                        <bitRange>[3:2]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>APB_DATA_WIDTH</name>
+                        <description>APB data bus width is 32 bits</description>
+                        <bitRange>[1:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>IC_COMP_VERSION</name>
+                <addressOffset>0x000000f8</addressOffset>
+                <description>I2C Component Version Register</description>
+                <resetValue>0x3230312a</resetValue>
+                <fields>
+                    <field>
+                        <name>IC_COMP_VERSION</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>IC_COMP_TYPE</name>
+                <addressOffset>0x000000fc</addressOffset>
+                <description>I2C Component Type Register</description>
+                <resetValue>0x44570140</resetValue>
+                <fields>
+                    <field>
+                        <name>IC_COMP_TYPE</name>
+                        <description>Designware Component Type number = 0x44_57_01_40. This assigned unique hex value is constant and is derived from the two ASCII letters &#39;DW&#39; followed by a 16-bit unsigned number.</description>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+        </registers>
+    </peripheral>
+    <peripheral derivedFrom="I2C0">
+        <name>I2C1</name>
+        <baseAddress>0x40048000</baseAddress>
+        <interrupt>
+        <name>I2C1_IRQ</name>
+        <value>24</value>
+    </interrupt>
+    </peripheral>
+    <peripheral>
+        <name>SPI0</name>
+        <baseAddress>0x4003c000</baseAddress>
+        <addressBlock>
+            <offset>0</offset>
+            <size>4096</size>
+            <usage>registers</usage>
+        </addressBlock>
+        <interrupt>
+            <name>SPI0_IRQ</name>
+            <value>18</value>
+        </interrupt>
+        <registers>
+            <register>
+                <name>SSPCR0</name>
+                <addressOffset>0x00000000</addressOffset>
+                <description>Control register 0, SSPCR0 on page 3-4</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>SCR</name>
+                        <description>Serial clock rate. The value SCR is used to generate the transmit and receive bit rate of the PrimeCell SSP. The bit rate is: F SSPCLK CPSDVSR x (1+SCR) where CPSDVSR is an even value from 2-254, programmed through the SSPCPSR register and SCR is a value from 0-255.</description>
+                        <bitRange>[15:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SPH</name>
+                        <description>SSPCLKOUT phase, applicable to Motorola SPI frame format only. See Motorola SPI frame format on page 2-10.</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SPO</name>
+                        <description>SSPCLKOUT polarity, applicable to Motorola SPI frame format only. See Motorola SPI frame format on page 2-10.</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>FRF</name>
+                        <description>Frame format: 00 Motorola SPI frame format. 01 TI synchronous serial frame format. 10 National Microwire frame format. 11 Reserved, undefined operation.</description>
+                        <bitRange>[5:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DSS</name>
+                        <description>Data Size Select: 0000 Reserved, undefined operation. 0001 Reserved, undefined operation. 0010 Reserved, undefined operation. 0011 4-bit data. 0100 5-bit data. 0101 6-bit data. 0110 7-bit data. 0111 8-bit data. 1000 9-bit data. 1001 10-bit data. 1010 11-bit data. 1011 12-bit data. 1100 13-bit data. 1101 14-bit data. 1110 15-bit data. 1111 16-bit data.</description>
+                        <bitRange>[3:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SSPCR1</name>
+                <addressOffset>0x00000004</addressOffset>
+                <description>Control register 1, SSPCR1 on page 3-5</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>SOD</name>
+                        <description>Slave-mode output disable. This bit is relevant only in the slave mode, MS=1. In multiple-slave systems, it is possible for an PrimeCell SSP master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto its serial output line. In such systems the RXD lines from multiple slaves could be tied together. To operate in such systems, the SOD bit can be set if the PrimeCell SSP slave is not supposed to drive the SSPTXD line: 0 SSP can drive the SSPTXD output in slave mode. 1 SSP must not drive the SSPTXD output in slave mode.</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>MS</name>
+                        <description>Master or slave mode select. This bit can be modified only when the PrimeCell SSP is disabled, SSE=0: 0 Device configured as master, default. 1 Device configured as slave.</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SSE</name>
+                        <description>Synchronous serial port enable: 0 SSP operation disabled. 1 SSP operation enabled.</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LBM</name>
+                        <description>Loop back mode: 0 Normal serial port operation enabled. 1 Output of transmit serial shifter is connected to input of receive serial shifter internally.</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SSPDR</name>
+                <addressOffset>0x00000008</addressOffset>
+                <description>Data register, SSPDR on page 3-6</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>DATA</name>
+                        <description>Transmit/Receive FIFO: Read Receive FIFO. Write Transmit FIFO. You must right-justify data when the PrimeCell SSP is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies.</description>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                        <readAction>modify</readAction>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SSPSR</name>
+                <addressOffset>0x0000000c</addressOffset>
+                <description>Status register, SSPSR on page 3-7</description>
+                <resetValue>0x00000003</resetValue>
+                <fields>
+                    <field>
+                        <name>BSY</name>
+                        <description>PrimeCell SSP busy flag, RO: 0 SSP is idle. 1 SSP is currently transmitting and/or receiving a frame or the transmit FIFO is not empty.</description>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>RFF</name>
+                        <description>Receive FIFO full, RO: 0 Receive FIFO is not full. 1 Receive FIFO is full.</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>RNE</name>
+                        <description>Receive FIFO not empty, RO: 0 Receive FIFO is empty. 1 Receive FIFO is not empty.</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>TNF</name>
+                        <description>Transmit FIFO not full, RO: 0 Transmit FIFO is full. 1 Transmit FIFO is not full.</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>TFE</name>
+                        <description>Transmit FIFO empty, RO: 0 Transmit FIFO is not empty. 1 Transmit FIFO is empty.</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SSPCPSR</name>
+                <addressOffset>0x00000010</addressOffset>
+                <description>Clock prescale register, SSPCPSR on page 3-8</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CPSDVSR</name>
+                        <description>Clock prescale divisor. Must be an even number from 2-254, depending on the frequency of SSPCLK. The least significant bit always returns zero on reads.</description>
+                        <bitRange>[7:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SSPIMSC</name>
+                <addressOffset>0x00000014</addressOffset>
+                <description>Interrupt mask set or clear register, SSPIMSC on page 3-9</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>TXIM</name>
+                        <description>Transmit FIFO interrupt mask: 0 Transmit FIFO half empty or less condition interrupt is masked. 1 Transmit FIFO half empty or less condition interrupt is not masked.</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>RXIM</name>
+                        <description>Receive FIFO interrupt mask: 0 Receive FIFO half full or less condition interrupt is masked. 1 Receive FIFO half full or less condition interrupt is not masked.</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>RTIM</name>
+                        <description>Receive timeout interrupt mask: 0 Receive FIFO not empty and no read prior to timeout period interrupt is masked. 1 Receive FIFO not empty and no read prior to timeout period interrupt is not masked.</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>RORIM</name>
+                        <description>Receive overrun interrupt mask: 0 Receive FIFO written to while full condition interrupt is masked. 1 Receive FIFO written to while full condition interrupt is not masked.</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SSPRIS</name>
+                <addressOffset>0x00000018</addressOffset>
+                <description>Raw interrupt status register, SSPRIS on page 3-10</description>
+                <resetValue>0x00000008</resetValue>
+                <fields>
+                    <field>
+                        <name>TXRIS</name>
+                        <description>Gives the raw interrupt state, prior to masking, of the SSPTXINTR interrupt</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>RXRIS</name>
+                        <description>Gives the raw interrupt state, prior to masking, of the SSPRXINTR interrupt</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>RTRIS</name>
+                        <description>Gives the raw interrupt state, prior to masking, of the SSPRTINTR interrupt</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>RORRIS</name>
+                        <description>Gives the raw interrupt state, prior to masking, of the SSPRORINTR interrupt</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SSPMIS</name>
+                <addressOffset>0x0000001c</addressOffset>
+                <description>Masked interrupt status register, SSPMIS on page 3-11</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>TXMIS</name>
+                        <description>Gives the transmit FIFO masked interrupt state, after masking, of the SSPTXINTR interrupt</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>RXMIS</name>
+                        <description>Gives the receive FIFO masked interrupt state, after masking, of the SSPRXINTR interrupt</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>RTMIS</name>
+                        <description>Gives the receive timeout masked interrupt state, after masking, of the SSPRTINTR interrupt</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>RORMIS</name>
+                        <description>Gives the receive over run masked interrupt status, after masking, of the SSPRORINTR interrupt</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SSPICR</name>
+                <addressOffset>0x00000020</addressOffset>
+                <description>Interrupt clear register, SSPICR on page 3-11</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>RTIC</name>
+                        <description>Clears the SSPRTINTR interrupt</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>RORIC</name>
+                        <description>Clears the SSPRORINTR interrupt</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SSPDMACR</name>
+                <addressOffset>0x00000024</addressOffset>
+                <description>DMA control register, SSPDMACR on page 3-12</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>TXDMAE</name>
+                        <description>Transmit DMA Enable. If this bit is set to 1, DMA for the transmit FIFO is enabled.</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>RXDMAE</name>
+                        <description>Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO is enabled.</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SSPPERIPHID0</name>
+                <addressOffset>0x00000fe0</addressOffset>
+                <description>Peripheral identification registers, SSPPeriphID0-3 on page 3-13</description>
+                <resetValue>0x00000022</resetValue>
+                <fields>
+                    <field>
+                        <name>PARTNUMBER0</name>
+                        <description>These bits read back as 0x22</description>
+                        <bitRange>[7:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SSPPERIPHID1</name>
+                <addressOffset>0x00000fe4</addressOffset>
+                <description>Peripheral identification registers, SSPPeriphID0-3 on page 3-13</description>
+                <resetValue>0x00000010</resetValue>
+                <fields>
+                    <field>
+                        <name>DESIGNER0</name>
+                        <description>These bits read back as 0x1</description>
+                        <bitRange>[7:4]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>PARTNUMBER1</name>
+                        <description>These bits read back as 0x0</description>
+                        <bitRange>[3:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SSPPERIPHID2</name>
+                <addressOffset>0x00000fe8</addressOffset>
+                <description>Peripheral identification registers, SSPPeriphID0-3 on page 3-13</description>
+                <resetValue>0x00000034</resetValue>
+                <fields>
+                    <field>
+                        <name>REVISION</name>
+                        <description>These bits return the peripheral revision</description>
+                        <bitRange>[7:4]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>DESIGNER1</name>
+                        <description>These bits read back as 0x4</description>
+                        <bitRange>[3:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SSPPERIPHID3</name>
+                <addressOffset>0x00000fec</addressOffset>
+                <description>Peripheral identification registers, SSPPeriphID0-3 on page 3-13</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CONFIGURATION</name>
+                        <description>These bits read back as 0x00</description>
+                        <bitRange>[7:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SSPPCELLID0</name>
+                <addressOffset>0x00000ff0</addressOffset>
+                <description>PrimeCell identification registers, SSPPCellID0-3 on page 3-16</description>
+                <resetValue>0x0000000d</resetValue>
+                <fields>
+                    <field>
+                        <name>SSPPCELLID0</name>
+                        <description>These bits read back as 0x0D</description>
+                        <bitRange>[7:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SSPPCELLID1</name>
+                <addressOffset>0x00000ff4</addressOffset>
+                <description>PrimeCell identification registers, SSPPCellID0-3 on page 3-16</description>
+                <resetValue>0x000000f0</resetValue>
+                <fields>
+                    <field>
+                        <name>SSPPCELLID1</name>
+                        <description>These bits read back as 0xF0</description>
+                        <bitRange>[7:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SSPPCELLID2</name>
+                <addressOffset>0x00000ff8</addressOffset>
+                <description>PrimeCell identification registers, SSPPCellID0-3 on page 3-16</description>
+                <resetValue>0x00000005</resetValue>
+                <fields>
+                    <field>
+                        <name>SSPPCELLID2</name>
+                        <description>These bits read back as 0x05</description>
+                        <bitRange>[7:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SSPPCELLID3</name>
+                <addressOffset>0x00000ffc</addressOffset>
+                <description>PrimeCell identification registers, SSPPCellID0-3 on page 3-16</description>
+                <resetValue>0x000000b1</resetValue>
+                <fields>
+                    <field>
+                        <name>SSPPCELLID3</name>
+                        <description>These bits read back as 0xB1</description>
+                        <bitRange>[7:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+        </registers>
+    </peripheral>
+    <peripheral derivedFrom="SPI0">
+        <name>SPI1</name>
+        <baseAddress>0x40040000</baseAddress>
+        <interrupt>
+        <name>SPI1_IRQ</name>
+        <value>19</value>
+    </interrupt>
+    </peripheral>
+    <peripheral>
+        <name>PIO0</name>
+        <description>Programmable IO block</description>
+        <baseAddress>0x50200000</baseAddress>
+        <addressBlock>
+            <offset>0</offset>
+            <size>324</size>
+            <usage>registers</usage>
+        </addressBlock>
+        <interrupt>
+            <name>PIO0_IRQ_0</name>
+            <value>7</value>
+        </interrupt>
+        <interrupt>
+            <name>PIO0_IRQ_1</name>
+            <value>8</value>
+        </interrupt>
+        <registers>
+            <register>
+                <name>CTRL</name>
+                <addressOffset>0x00000000</addressOffset>
+                <description>PIO control register</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CLKDIV_RESTART</name>
+                        <description>Restart a state machine&#39;s clock divider from an initial phase of 0. Clock dividers are free-running, so once started, their output (including fractional jitter) is completely determined by the integer/fractional divisor configured in SMx_CLKDIV. This means that, if multiple clock dividers with the same divisor are restarted simultaneously, by writing multiple 1 bits to this field, the execution clocks of those state machines will run in precise lockstep.
+
+                            Note that setting/clearing SM_ENABLE does not stop the clock divider from running, so once multiple state machines&#39; clocks are synchronised, it is safe to disable/reenable a state machine, whilst keeping the clock dividers in sync.
+
+                            Note also that CLKDIV_RESTART can be written to whilst the state machine is running, and this is useful to resynchronise clock dividers after the divisors (SMx_CLKDIV) have been changed on-the-fly.</description>
+                        <bitRange>[11:8]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>SM_RESTART</name>
+                        <description>Write 1 to instantly clear internal SM state which may be otherwise difficult to access and will affect future execution.
+
+                            Specifically, the following are cleared: input and output shift counters; the contents of the input shift register; the delay counter; the waiting-on-IRQ state; any stalled instruction written to SMx_INSTR or run by OUT/MOV EXEC; any pin write left asserted due to OUT_STICKY.
+
+                            The program counter, the contents of the output shift register and the X/Y scratch registers are not affected.</description>
+                        <bitRange>[7:4]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>SM_ENABLE</name>
+                        <description>Enable/disable each of the four state machines by writing 1/0 to each of these four bits. When disabled, a state machine will cease executing instructions, except those written directly to SMx_INSTR by the system. Multiple bits can be set/cleared at once to run/halt multiple state machines simultaneously.</description>
+                        <bitRange>[3:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>FSTAT</name>
+                <addressOffset>0x00000004</addressOffset>
+                <description>FIFO status register</description>
+                <resetValue>0x0f000f00</resetValue>
+                <fields>
+                    <field>
+                        <name>TXEMPTY</name>
+                        <description>State machine TX FIFO is empty</description>
+                        <bitRange>[27:24]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>TXFULL</name>
+                        <description>State machine TX FIFO is full</description>
+                        <bitRange>[19:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>RXEMPTY</name>
+                        <description>State machine RX FIFO is empty</description>
+                        <bitRange>[11:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>RXFULL</name>
+                        <description>State machine RX FIFO is full</description>
+                        <bitRange>[3:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>FDEBUG</name>
+                <addressOffset>0x00000008</addressOffset>
+                <description>FIFO debug register</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>TXSTALL</name>
+                        <description>State machine has stalled on empty TX FIFO during a blocking PULL, or an OUT with autopull enabled. Write 1 to clear.</description>
+                        <bitRange>[27:24]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>TXOVER</name>
+                        <description>TX FIFO overflow (i.e. write-on-full by the system) has occurred. Write 1 to clear. Note that write-on-full does not alter the state or contents of the FIFO in any way, but the data that the system attempted to write is dropped, so if this flag is set, your software has quite likely dropped some data on the floor.</description>
+                        <bitRange>[19:16]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>RXUNDER</name>
+                        <description>RX FIFO underflow (i.e. read-on-empty by the system) has occurred. Write 1 to clear. Note that read-on-empty does not perturb the state of the FIFO in any way, but the data returned by reading from an empty FIFO is undefined, so this flag generally only becomes set due to some kind of software error.</description>
+                        <bitRange>[11:8]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>RXSTALL</name>
+                        <description>State machine has stalled on full RX FIFO during a blocking PUSH, or an IN with autopush enabled. This flag is also set when a nonblocking PUSH to a full FIFO took place, in which case the state machine has dropped data. Write 1 to clear.</description>
+                        <bitRange>[3:0]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>FLEVEL</name>
+                <addressOffset>0x0000000c</addressOffset>
+                <description>FIFO levels</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>RX3</name>
+                        <bitRange>[31:28]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>TX3</name>
+                        <bitRange>[27:24]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>RX2</name>
+                        <bitRange>[23:20]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>TX2</name>
+                        <bitRange>[19:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>RX1</name>
+                        <bitRange>[15:12]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>TX1</name>
+                        <bitRange>[11:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>RX0</name>
+                        <bitRange>[7:4]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>TX0</name>
+                        <bitRange>[3:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>TXF0</name>
+                <addressOffset>0x00000010</addressOffset>
+                <description>Direct write access to the TX FIFO for this state machine. Each write pushes one word to the FIFO. Attempting to write to a full FIFO has no effect on the FIFO state or contents, and sets the sticky FDEBUG_TXOVER error flag for this FIFO.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>TXF0</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>TXF1</name>
+                <addressOffset>0x00000014</addressOffset>
+                <description>Direct write access to the TX FIFO for this state machine. Each write pushes one word to the FIFO. Attempting to write to a full FIFO has no effect on the FIFO state or contents, and sets the sticky FDEBUG_TXOVER error flag for this FIFO.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>TXF1</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>TXF2</name>
+                <addressOffset>0x00000018</addressOffset>
+                <description>Direct write access to the TX FIFO for this state machine. Each write pushes one word to the FIFO. Attempting to write to a full FIFO has no effect on the FIFO state or contents, and sets the sticky FDEBUG_TXOVER error flag for this FIFO.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>TXF2</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>TXF3</name>
+                <addressOffset>0x0000001c</addressOffset>
+                <description>Direct write access to the TX FIFO for this state machine. Each write pushes one word to the FIFO. Attempting to write to a full FIFO has no effect on the FIFO state or contents, and sets the sticky FDEBUG_TXOVER error flag for this FIFO.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>TXF3</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>RXF0</name>
+                <addressOffset>0x00000020</addressOffset>
+                <description>Direct read access to the RX FIFO for this state machine. Each read pops one word from the FIFO. Attempting to read from an empty FIFO has no effect on the FIFO state, and sets the sticky FDEBUG_RXUNDER error flag for this FIFO. The data returned to the system on a read from an empty FIFO is undefined.</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>RXF0</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-only</access>
+                        <readAction>modify</readAction>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>RXF1</name>
+                <addressOffset>0x00000024</addressOffset>
+                <description>Direct read access to the RX FIFO for this state machine. Each read pops one word from the FIFO. Attempting to read from an empty FIFO has no effect on the FIFO state, and sets the sticky FDEBUG_RXUNDER error flag for this FIFO. The data returned to the system on a read from an empty FIFO is undefined.</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>RXF1</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-only</access>
+                        <readAction>modify</readAction>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>RXF2</name>
+                <addressOffset>0x00000028</addressOffset>
+                <description>Direct read access to the RX FIFO for this state machine. Each read pops one word from the FIFO. Attempting to read from an empty FIFO has no effect on the FIFO state, and sets the sticky FDEBUG_RXUNDER error flag for this FIFO. The data returned to the system on a read from an empty FIFO is undefined.</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>RXF2</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-only</access>
+                        <readAction>modify</readAction>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>RXF3</name>
+                <addressOffset>0x0000002c</addressOffset>
+                <description>Direct read access to the RX FIFO for this state machine. Each read pops one word from the FIFO. Attempting to read from an empty FIFO has no effect on the FIFO state, and sets the sticky FDEBUG_RXUNDER error flag for this FIFO. The data returned to the system on a read from an empty FIFO is undefined.</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>RXF3</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-only</access>
+                        <readAction>modify</readAction>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>IRQ</name>
+                <addressOffset>0x00000030</addressOffset>
+                <description>State machine IRQ flags register. Write 1 to clear. There are 8 state machine IRQ flags, which can be set, cleared, and waited on by the state machines. There&#39;s no fixed association between flags and state machines -- any state machine can use any flag.
+
+                    Any of the 8 flags can be used for timing synchronisation between state machines, using IRQ and WAIT instructions. The lower four of these flags are also routed out to system-level interrupt requests, alongside FIFO status interrupts -- see e.g. IRQ0_INTE.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>IRQ</name>
+                        <bitRange>[7:0]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>IRQ_FORCE</name>
+                <addressOffset>0x00000034</addressOffset>
+                <description>Writing a 1 to each of these bits will forcibly assert the corresponding IRQ. Note this is different to the INTF register: writing here affects PIO internal state. INTF just asserts the processor-facing IRQ signal for testing ISRs, and is not visible to the state machines.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>IRQ_FORCE</name>
+                        <bitRange>[7:0]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INPUT_SYNC_BYPASS</name>
+                <addressOffset>0x00000038</addressOffset>
+                <description>There is a 2-flipflop synchronizer on each GPIO input, which protects PIO logic from metastabilities. This increases input delay, and for fast synchronous IO (e.g. SPI) these synchronizers may need to be bypassed. Each bit in this register corresponds to one GPIO. 
+                    0 -&gt; input is synchronized (default) 
+                    1 -&gt; synchronizer is bypassed 
+                    If in doubt, leave this register as all zeroes.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>INPUT_SYNC_BYPASS</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>DBG_PADOUT</name>
+                <addressOffset>0x0000003c</addressOffset>
+                <description>Read to sample the pad output values PIO is currently driving to the GPIOs. On RP2040 there are 30 GPIOs, so the two most significant bits are hardwired to 0.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>DBG_PADOUT</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>DBG_PADOE</name>
+                <addressOffset>0x00000040</addressOffset>
+                <description>Read to sample the pad output enables (direction) PIO is currently driving to the GPIOs. On RP2040 there are 30 GPIOs, so the two most significant bits are hardwired to 0.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>DBG_PADOE</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>DBG_CFGINFO</name>
+                <addressOffset>0x00000044</addressOffset>
+                <description>The PIO hardware has some free parameters that may vary between chip products. 
+                    These should be provided in the chip datasheet, but are also exposed here.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>IMEM_SIZE</name>
+                        <description>The size of the instruction memory, measured in units of one instruction</description>
+                        <bitRange>[21:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SM_COUNT</name>
+                        <description>The number of state machines this PIO instance is equipped with.</description>
+                        <bitRange>[11:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>FIFO_DEPTH</name>
+                        <description>The depth of the state machine TX/RX FIFOs, measured in words. 
+                            Joining fifos via SHIFTCTRL_FJOIN gives one FIFO with double 
+                            this depth.</description>
+                        <bitRange>[5:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INSTR_MEM0</name>
+                <addressOffset>0x00000048</addressOffset>
+                <description>Write-only access to instruction memory location 0</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>INSTR_MEM0</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INSTR_MEM1</name>
+                <addressOffset>0x0000004c</addressOffset>
+                <description>Write-only access to instruction memory location 1</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>INSTR_MEM1</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INSTR_MEM2</name>
+                <addressOffset>0x00000050</addressOffset>
+                <description>Write-only access to instruction memory location 2</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>INSTR_MEM2</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INSTR_MEM3</name>
+                <addressOffset>0x00000054</addressOffset>
+                <description>Write-only access to instruction memory location 3</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>INSTR_MEM3</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INSTR_MEM4</name>
+                <addressOffset>0x00000058</addressOffset>
+                <description>Write-only access to instruction memory location 4</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>INSTR_MEM4</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INSTR_MEM5</name>
+                <addressOffset>0x0000005c</addressOffset>
+                <description>Write-only access to instruction memory location 5</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>INSTR_MEM5</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INSTR_MEM6</name>
+                <addressOffset>0x00000060</addressOffset>
+                <description>Write-only access to instruction memory location 6</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>INSTR_MEM6</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INSTR_MEM7</name>
+                <addressOffset>0x00000064</addressOffset>
+                <description>Write-only access to instruction memory location 7</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>INSTR_MEM7</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INSTR_MEM8</name>
+                <addressOffset>0x00000068</addressOffset>
+                <description>Write-only access to instruction memory location 8</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>INSTR_MEM8</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INSTR_MEM9</name>
+                <addressOffset>0x0000006c</addressOffset>
+                <description>Write-only access to instruction memory location 9</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>INSTR_MEM9</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INSTR_MEM10</name>
+                <addressOffset>0x00000070</addressOffset>
+                <description>Write-only access to instruction memory location 10</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>INSTR_MEM10</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INSTR_MEM11</name>
+                <addressOffset>0x00000074</addressOffset>
+                <description>Write-only access to instruction memory location 11</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>INSTR_MEM11</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INSTR_MEM12</name>
+                <addressOffset>0x00000078</addressOffset>
+                <description>Write-only access to instruction memory location 12</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>INSTR_MEM12</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INSTR_MEM13</name>
+                <addressOffset>0x0000007c</addressOffset>
+                <description>Write-only access to instruction memory location 13</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>INSTR_MEM13</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INSTR_MEM14</name>
+                <addressOffset>0x00000080</addressOffset>
+                <description>Write-only access to instruction memory location 14</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>INSTR_MEM14</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INSTR_MEM15</name>
+                <addressOffset>0x00000084</addressOffset>
+                <description>Write-only access to instruction memory location 15</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>INSTR_MEM15</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INSTR_MEM16</name>
+                <addressOffset>0x00000088</addressOffset>
+                <description>Write-only access to instruction memory location 16</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>INSTR_MEM16</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INSTR_MEM17</name>
+                <addressOffset>0x0000008c</addressOffset>
+                <description>Write-only access to instruction memory location 17</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>INSTR_MEM17</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INSTR_MEM18</name>
+                <addressOffset>0x00000090</addressOffset>
+                <description>Write-only access to instruction memory location 18</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>INSTR_MEM18</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INSTR_MEM19</name>
+                <addressOffset>0x00000094</addressOffset>
+                <description>Write-only access to instruction memory location 19</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>INSTR_MEM19</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INSTR_MEM20</name>
+                <addressOffset>0x00000098</addressOffset>
+                <description>Write-only access to instruction memory location 20</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>INSTR_MEM20</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INSTR_MEM21</name>
+                <addressOffset>0x0000009c</addressOffset>
+                <description>Write-only access to instruction memory location 21</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>INSTR_MEM21</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INSTR_MEM22</name>
+                <addressOffset>0x000000a0</addressOffset>
+                <description>Write-only access to instruction memory location 22</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>INSTR_MEM22</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INSTR_MEM23</name>
+                <addressOffset>0x000000a4</addressOffset>
+                <description>Write-only access to instruction memory location 23</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>INSTR_MEM23</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INSTR_MEM24</name>
+                <addressOffset>0x000000a8</addressOffset>
+                <description>Write-only access to instruction memory location 24</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>INSTR_MEM24</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INSTR_MEM25</name>
+                <addressOffset>0x000000ac</addressOffset>
+                <description>Write-only access to instruction memory location 25</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>INSTR_MEM25</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INSTR_MEM26</name>
+                <addressOffset>0x000000b0</addressOffset>
+                <description>Write-only access to instruction memory location 26</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>INSTR_MEM26</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INSTR_MEM27</name>
+                <addressOffset>0x000000b4</addressOffset>
+                <description>Write-only access to instruction memory location 27</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>INSTR_MEM27</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INSTR_MEM28</name>
+                <addressOffset>0x000000b8</addressOffset>
+                <description>Write-only access to instruction memory location 28</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>INSTR_MEM28</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INSTR_MEM29</name>
+                <addressOffset>0x000000bc</addressOffset>
+                <description>Write-only access to instruction memory location 29</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>INSTR_MEM29</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INSTR_MEM30</name>
+                <addressOffset>0x000000c0</addressOffset>
+                <description>Write-only access to instruction memory location 30</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>INSTR_MEM30</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INSTR_MEM31</name>
+                <addressOffset>0x000000c4</addressOffset>
+                <description>Write-only access to instruction memory location 31</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>INSTR_MEM31</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SM0_CLKDIV</name>
+                <addressOffset>0x000000c8</addressOffset>
+                <description>Clock divisor register for state machine 0 
+                    Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256)</description>
+                <resetValue>0x00010000</resetValue>
+                <fields>
+                    <field>
+                        <name>INT</name>
+                        <description>Effective frequency is sysclk/(int + frac/256). 
+                            Value of 0 is interpreted as 65536. If INT is 0, FRAC must also be 0.</description>
+                        <bitRange>[31:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>FRAC</name>
+                        <description>Fractional part of clock divisor</description>
+                        <bitRange>[15:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SM0_EXECCTRL</name>
+                <addressOffset>0x000000cc</addressOffset>
+                <description>Execution/behavioural settings for state machine 0</description>
+                <resetValue>0x0001f000</resetValue>
+                <fields>
+                    <field>
+                        <name>EXEC_STALLED</name>
+                        <description>If 1, an instruction written to SMx_INSTR is stalled, and latched by the state machine. Will clear to 0 once this instruction completes.</description>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SIDE_EN</name>
+                        <description>If 1, the MSB of the Delay/Side-set instruction field is used as side-set enable, rather than a side-set data bit. This allows instructions to perform side-set optionally, rather than on every instruction, but the maximum possible side-set width is reduced from 5 to 4. Note that the value of PINCTRL_SIDESET_COUNT is inclusive of this enable bit.</description>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SIDE_PINDIR</name>
+                        <description>If 1, side-set data is asserted to pin directions, instead of pin values</description>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>JMP_PIN</name>
+                        <description>The GPIO number to use as condition for JMP PIN. Unaffected by input mapping.</description>
+                        <bitRange>[28:24]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>OUT_EN_SEL</name>
+                        <description>Which data bit to use for inline OUT enable</description>
+                        <bitRange>[23:19]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INLINE_OUT_EN</name>
+                        <description>If 1, use a bit of OUT data as an auxiliary write enable 
+                            When used in conjunction with OUT_STICKY, writes with an enable of 0 will 
+                            deassert the latest pin write. This can create useful masking/override behaviour 
+                            due to the priority ordering of state machine pin writes (SM0 &lt; SM1 &lt; ...)</description>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>OUT_STICKY</name>
+                        <description>Continuously assert the most recent OUT/SET to the pins</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>WRAP_TOP</name>
+                        <description>After reaching this address, execution is wrapped to wrap_bottom. 
+                            If the instruction is a jump, and the jump condition is true, the jump takes priority.</description>
+                        <bitRange>[16:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>WRAP_BOTTOM</name>
+                        <description>After reaching wrap_top, execution is wrapped to this address.</description>
+                        <bitRange>[11:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>STATUS_SEL</name>
+                        <description>Comparison used for the MOV x, STATUS instruction.</description>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>TXLEVEL</name>
+                                <value>0</value>
+                                <description>All-ones if TX FIFO level &lt; N, otherwise all-zeroes</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>RXLEVEL</name>
+                                <value>1</value>
+                                <description>All-ones if RX FIFO level &lt; N, otherwise all-zeroes</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>STATUS_N</name>
+                        <description>Comparison level for the MOV x, STATUS instruction</description>
+                        <bitRange>[3:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SM0_SHIFTCTRL</name>
+                <addressOffset>0x000000d0</addressOffset>
+                <description>Control behaviour of the input/output shift registers for state machine 0</description>
+                <resetValue>0x000c0000</resetValue>
+                <fields>
+                    <field>
+                        <name>FJOIN_RX</name>
+                        <description>When 1, RX FIFO steals the TX FIFO&#39;s storage, and becomes twice as deep. 
+                            TX FIFO is disabled as a result (always reads as both full and empty). 
+                            FIFOs are flushed when this bit is changed.</description>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>FJOIN_TX</name>
+                        <description>When 1, TX FIFO steals the RX FIFO&#39;s storage, and becomes twice as deep. 
+                            RX FIFO is disabled as a result (always reads as both full and empty). 
+                            FIFOs are flushed when this bit is changed.</description>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PULL_THRESH</name>
+                        <description>Number of bits shifted out of OSR before autopull, or conditional pull (PULL IFEMPTY), will take place. 
+                            Write 0 for value of 32.</description>
+                        <bitRange>[29:25]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PUSH_THRESH</name>
+                        <description>Number of bits shifted into ISR before autopush, or conditional push (PUSH IFFULL), will take place. 
+                            Write 0 for value of 32.</description>
+                        <bitRange>[24:20]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>OUT_SHIFTDIR</name>
+                        <description>1 = shift out of output shift register to right. 0 = to left.</description>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>IN_SHIFTDIR</name>
+                        <description>1 = shift input shift register to right (data enters from left). 0 = to left.</description>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>AUTOPULL</name>
+                        <description>Pull automatically when the output shift register is emptied, i.e. on or following an OUT instruction which causes the output shift counter to reach or exceed PULL_THRESH.</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>AUTOPUSH</name>
+                        <description>Push automatically when the input shift register is filled, i.e. on an IN instruction which causes the input shift counter to reach or exceed PUSH_THRESH.</description>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SM0_ADDR</name>
+                <addressOffset>0x000000d4</addressOffset>
+                <description>Current instruction address of state machine 0</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>SM0_ADDR</name>
+                        <bitRange>[4:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SM0_INSTR</name>
+                <addressOffset>0x000000d8</addressOffset>
+                <description>Read to see the instruction currently addressed by state machine 0&#39;s program counter 
+                    Write to execute an instruction immediately (including jumps) and then resume execution.</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>SM0_INSTR</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SM0_PINCTRL</name>
+                <addressOffset>0x000000dc</addressOffset>
+                <description>State machine pin control</description>
+                <resetValue>0x14000000</resetValue>
+                <fields>
+                    <field>
+                        <name>SIDESET_COUNT</name>
+                        <description>The number of MSBs of the Delay/Side-set instruction field which are used for side-set. Inclusive of the enable bit, if present. Minimum of 0 (all delay bits, no side-set) and maximum of 5 (all side-set, no delay).</description>
+                        <bitRange>[31:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SET_COUNT</name>
+                        <description>The number of pins asserted by a SET. In the range 0 to 5 inclusive.</description>
+                        <bitRange>[28:26]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>OUT_COUNT</name>
+                        <description>The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV PINS instruction. In the range 0 to 32 inclusive.</description>
+                        <bitRange>[25:20]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>IN_BASE</name>
+                        <description>The pin which is mapped to the least-significant bit of a state machine&#39;s IN data bus. Higher-numbered pins are mapped to consecutively more-significant data bits, with a modulo of 32 applied to pin number.</description>
+                        <bitRange>[19:15]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SIDESET_BASE</name>
+                        <description>The lowest-numbered pin that will be affected by a side-set operation. The MSBs of an instruction&#39;s side-set/delay field (up to 5, determined by SIDESET_COUNT) are used for side-set data, with the remaining LSBs used for delay. The least-significant bit of the side-set portion is the bit written to this pin, with more-significant bits written to higher-numbered pins.</description>
+                        <bitRange>[14:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SET_BASE</name>
+                        <description>The lowest-numbered pin that will be affected by a SET PINS or SET PINDIRS instruction. The data written to this pin is the least-significant bit of the SET data.</description>
+                        <bitRange>[9:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>OUT_BASE</name>
+                        <description>The lowest-numbered pin that will be affected by an OUT PINS, OUT PINDIRS or MOV PINS instruction. The data written to this pin will always be the least-significant bit of the OUT or MOV data.</description>
+                        <bitRange>[4:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SM1_CLKDIV</name>
+                <addressOffset>0x000000e0</addressOffset>
+                <description>Clock divisor register for state machine 1 
+                    Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256)</description>
+                <resetValue>0x00010000</resetValue>
+                <fields>
+                    <field>
+                        <name>INT</name>
+                        <description>Effective frequency is sysclk/(int + frac/256). 
+                            Value of 0 is interpreted as 65536. If INT is 0, FRAC must also be 0.</description>
+                        <bitRange>[31:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>FRAC</name>
+                        <description>Fractional part of clock divisor</description>
+                        <bitRange>[15:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SM1_EXECCTRL</name>
+                <addressOffset>0x000000e4</addressOffset>
+                <description>Execution/behavioural settings for state machine 1</description>
+                <resetValue>0x0001f000</resetValue>
+                <fields>
+                    <field>
+                        <name>EXEC_STALLED</name>
+                        <description>If 1, an instruction written to SMx_INSTR is stalled, and latched by the state machine. Will clear to 0 once this instruction completes.</description>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SIDE_EN</name>
+                        <description>If 1, the MSB of the Delay/Side-set instruction field is used as side-set enable, rather than a side-set data bit. This allows instructions to perform side-set optionally, rather than on every instruction, but the maximum possible side-set width is reduced from 5 to 4. Note that the value of PINCTRL_SIDESET_COUNT is inclusive of this enable bit.</description>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SIDE_PINDIR</name>
+                        <description>If 1, side-set data is asserted to pin directions, instead of pin values</description>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>JMP_PIN</name>
+                        <description>The GPIO number to use as condition for JMP PIN. Unaffected by input mapping.</description>
+                        <bitRange>[28:24]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>OUT_EN_SEL</name>
+                        <description>Which data bit to use for inline OUT enable</description>
+                        <bitRange>[23:19]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INLINE_OUT_EN</name>
+                        <description>If 1, use a bit of OUT data as an auxiliary write enable 
+                            When used in conjunction with OUT_STICKY, writes with an enable of 0 will 
+                            deassert the latest pin write. This can create useful masking/override behaviour 
+                            due to the priority ordering of state machine pin writes (SM0 &lt; SM1 &lt; ...)</description>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>OUT_STICKY</name>
+                        <description>Continuously assert the most recent OUT/SET to the pins</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>WRAP_TOP</name>
+                        <description>After reaching this address, execution is wrapped to wrap_bottom. 
+                            If the instruction is a jump, and the jump condition is true, the jump takes priority.</description>
+                        <bitRange>[16:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>WRAP_BOTTOM</name>
+                        <description>After reaching wrap_top, execution is wrapped to this address.</description>
+                        <bitRange>[11:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>STATUS_SEL</name>
+                        <description>Comparison used for the MOV x, STATUS instruction.</description>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>TXLEVEL</name>
+                                <value>0</value>
+                                <description>All-ones if TX FIFO level &lt; N, otherwise all-zeroes</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>RXLEVEL</name>
+                                <value>1</value>
+                                <description>All-ones if RX FIFO level &lt; N, otherwise all-zeroes</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>STATUS_N</name>
+                        <description>Comparison level for the MOV x, STATUS instruction</description>
+                        <bitRange>[3:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SM1_SHIFTCTRL</name>
+                <addressOffset>0x000000e8</addressOffset>
+                <description>Control behaviour of the input/output shift registers for state machine 1</description>
+                <resetValue>0x000c0000</resetValue>
+                <fields>
+                    <field>
+                        <name>FJOIN_RX</name>
+                        <description>When 1, RX FIFO steals the TX FIFO&#39;s storage, and becomes twice as deep. 
+                            TX FIFO is disabled as a result (always reads as both full and empty). 
+                            FIFOs are flushed when this bit is changed.</description>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>FJOIN_TX</name>
+                        <description>When 1, TX FIFO steals the RX FIFO&#39;s storage, and becomes twice as deep. 
+                            RX FIFO is disabled as a result (always reads as both full and empty). 
+                            FIFOs are flushed when this bit is changed.</description>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PULL_THRESH</name>
+                        <description>Number of bits shifted out of OSR before autopull, or conditional pull (PULL IFEMPTY), will take place. 
+                            Write 0 for value of 32.</description>
+                        <bitRange>[29:25]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PUSH_THRESH</name>
+                        <description>Number of bits shifted into ISR before autopush, or conditional push (PUSH IFFULL), will take place. 
+                            Write 0 for value of 32.</description>
+                        <bitRange>[24:20]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>OUT_SHIFTDIR</name>
+                        <description>1 = shift out of output shift register to right. 0 = to left.</description>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>IN_SHIFTDIR</name>
+                        <description>1 = shift input shift register to right (data enters from left). 0 = to left.</description>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>AUTOPULL</name>
+                        <description>Pull automatically when the output shift register is emptied, i.e. on or following an OUT instruction which causes the output shift counter to reach or exceed PULL_THRESH.</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>AUTOPUSH</name>
+                        <description>Push automatically when the input shift register is filled, i.e. on an IN instruction which causes the input shift counter to reach or exceed PUSH_THRESH.</description>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SM1_ADDR</name>
+                <addressOffset>0x000000ec</addressOffset>
+                <description>Current instruction address of state machine 1</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>SM1_ADDR</name>
+                        <bitRange>[4:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SM1_INSTR</name>
+                <addressOffset>0x000000f0</addressOffset>
+                <description>Read to see the instruction currently addressed by state machine 1&#39;s program counter 
+                    Write to execute an instruction immediately (including jumps) and then resume execution.</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>SM1_INSTR</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SM1_PINCTRL</name>
+                <addressOffset>0x000000f4</addressOffset>
+                <description>State machine pin control</description>
+                <resetValue>0x14000000</resetValue>
+                <fields>
+                    <field>
+                        <name>SIDESET_COUNT</name>
+                        <description>The number of MSBs of the Delay/Side-set instruction field which are used for side-set. Inclusive of the enable bit, if present. Minimum of 0 (all delay bits, no side-set) and maximum of 5 (all side-set, no delay).</description>
+                        <bitRange>[31:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SET_COUNT</name>
+                        <description>The number of pins asserted by a SET. In the range 0 to 5 inclusive.</description>
+                        <bitRange>[28:26]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>OUT_COUNT</name>
+                        <description>The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV PINS instruction. In the range 0 to 32 inclusive.</description>
+                        <bitRange>[25:20]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>IN_BASE</name>
+                        <description>The pin which is mapped to the least-significant bit of a state machine&#39;s IN data bus. Higher-numbered pins are mapped to consecutively more-significant data bits, with a modulo of 32 applied to pin number.</description>
+                        <bitRange>[19:15]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SIDESET_BASE</name>
+                        <description>The lowest-numbered pin that will be affected by a side-set operation. The MSBs of an instruction&#39;s side-set/delay field (up to 5, determined by SIDESET_COUNT) are used for side-set data, with the remaining LSBs used for delay. The least-significant bit of the side-set portion is the bit written to this pin, with more-significant bits written to higher-numbered pins.</description>
+                        <bitRange>[14:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SET_BASE</name>
+                        <description>The lowest-numbered pin that will be affected by a SET PINS or SET PINDIRS instruction. The data written to this pin is the least-significant bit of the SET data.</description>
+                        <bitRange>[9:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>OUT_BASE</name>
+                        <description>The lowest-numbered pin that will be affected by an OUT PINS, OUT PINDIRS or MOV PINS instruction. The data written to this pin will always be the least-significant bit of the OUT or MOV data.</description>
+                        <bitRange>[4:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SM2_CLKDIV</name>
+                <addressOffset>0x000000f8</addressOffset>
+                <description>Clock divisor register for state machine 2 
+                    Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256)</description>
+                <resetValue>0x00010000</resetValue>
+                <fields>
+                    <field>
+                        <name>INT</name>
+                        <description>Effective frequency is sysclk/(int + frac/256). 
+                            Value of 0 is interpreted as 65536. If INT is 0, FRAC must also be 0.</description>
+                        <bitRange>[31:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>FRAC</name>
+                        <description>Fractional part of clock divisor</description>
+                        <bitRange>[15:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SM2_EXECCTRL</name>
+                <addressOffset>0x000000fc</addressOffset>
+                <description>Execution/behavioural settings for state machine 2</description>
+                <resetValue>0x0001f000</resetValue>
+                <fields>
+                    <field>
+                        <name>EXEC_STALLED</name>
+                        <description>If 1, an instruction written to SMx_INSTR is stalled, and latched by the state machine. Will clear to 0 once this instruction completes.</description>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SIDE_EN</name>
+                        <description>If 1, the MSB of the Delay/Side-set instruction field is used as side-set enable, rather than a side-set data bit. This allows instructions to perform side-set optionally, rather than on every instruction, but the maximum possible side-set width is reduced from 5 to 4. Note that the value of PINCTRL_SIDESET_COUNT is inclusive of this enable bit.</description>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SIDE_PINDIR</name>
+                        <description>If 1, side-set data is asserted to pin directions, instead of pin values</description>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>JMP_PIN</name>
+                        <description>The GPIO number to use as condition for JMP PIN. Unaffected by input mapping.</description>
+                        <bitRange>[28:24]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>OUT_EN_SEL</name>
+                        <description>Which data bit to use for inline OUT enable</description>
+                        <bitRange>[23:19]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INLINE_OUT_EN</name>
+                        <description>If 1, use a bit of OUT data as an auxiliary write enable 
+                            When used in conjunction with OUT_STICKY, writes with an enable of 0 will 
+                            deassert the latest pin write. This can create useful masking/override behaviour 
+                            due to the priority ordering of state machine pin writes (SM0 &lt; SM1 &lt; ...)</description>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>OUT_STICKY</name>
+                        <description>Continuously assert the most recent OUT/SET to the pins</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>WRAP_TOP</name>
+                        <description>After reaching this address, execution is wrapped to wrap_bottom. 
+                            If the instruction is a jump, and the jump condition is true, the jump takes priority.</description>
+                        <bitRange>[16:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>WRAP_BOTTOM</name>
+                        <description>After reaching wrap_top, execution is wrapped to this address.</description>
+                        <bitRange>[11:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>STATUS_SEL</name>
+                        <description>Comparison used for the MOV x, STATUS instruction.</description>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>TXLEVEL</name>
+                                <value>0</value>
+                                <description>All-ones if TX FIFO level &lt; N, otherwise all-zeroes</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>RXLEVEL</name>
+                                <value>1</value>
+                                <description>All-ones if RX FIFO level &lt; N, otherwise all-zeroes</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>STATUS_N</name>
+                        <description>Comparison level for the MOV x, STATUS instruction</description>
+                        <bitRange>[3:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SM2_SHIFTCTRL</name>
+                <addressOffset>0x00000100</addressOffset>
+                <description>Control behaviour of the input/output shift registers for state machine 2</description>
+                <resetValue>0x000c0000</resetValue>
+                <fields>
+                    <field>
+                        <name>FJOIN_RX</name>
+                        <description>When 1, RX FIFO steals the TX FIFO&#39;s storage, and becomes twice as deep. 
+                            TX FIFO is disabled as a result (always reads as both full and empty). 
+                            FIFOs are flushed when this bit is changed.</description>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>FJOIN_TX</name>
+                        <description>When 1, TX FIFO steals the RX FIFO&#39;s storage, and becomes twice as deep. 
+                            RX FIFO is disabled as a result (always reads as both full and empty). 
+                            FIFOs are flushed when this bit is changed.</description>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PULL_THRESH</name>
+                        <description>Number of bits shifted out of OSR before autopull, or conditional pull (PULL IFEMPTY), will take place. 
+                            Write 0 for value of 32.</description>
+                        <bitRange>[29:25]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PUSH_THRESH</name>
+                        <description>Number of bits shifted into ISR before autopush, or conditional push (PUSH IFFULL), will take place. 
+                            Write 0 for value of 32.</description>
+                        <bitRange>[24:20]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>OUT_SHIFTDIR</name>
+                        <description>1 = shift out of output shift register to right. 0 = to left.</description>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>IN_SHIFTDIR</name>
+                        <description>1 = shift input shift register to right (data enters from left). 0 = to left.</description>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>AUTOPULL</name>
+                        <description>Pull automatically when the output shift register is emptied, i.e. on or following an OUT instruction which causes the output shift counter to reach or exceed PULL_THRESH.</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>AUTOPUSH</name>
+                        <description>Push automatically when the input shift register is filled, i.e. on an IN instruction which causes the input shift counter to reach or exceed PUSH_THRESH.</description>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SM2_ADDR</name>
+                <addressOffset>0x00000104</addressOffset>
+                <description>Current instruction address of state machine 2</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>SM2_ADDR</name>
+                        <bitRange>[4:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SM2_INSTR</name>
+                <addressOffset>0x00000108</addressOffset>
+                <description>Read to see the instruction currently addressed by state machine 2&#39;s program counter 
+                    Write to execute an instruction immediately (including jumps) and then resume execution.</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>SM2_INSTR</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SM2_PINCTRL</name>
+                <addressOffset>0x0000010c</addressOffset>
+                <description>State machine pin control</description>
+                <resetValue>0x14000000</resetValue>
+                <fields>
+                    <field>
+                        <name>SIDESET_COUNT</name>
+                        <description>The number of MSBs of the Delay/Side-set instruction field which are used for side-set. Inclusive of the enable bit, if present. Minimum of 0 (all delay bits, no side-set) and maximum of 5 (all side-set, no delay).</description>
+                        <bitRange>[31:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SET_COUNT</name>
+                        <description>The number of pins asserted by a SET. In the range 0 to 5 inclusive.</description>
+                        <bitRange>[28:26]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>OUT_COUNT</name>
+                        <description>The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV PINS instruction. In the range 0 to 32 inclusive.</description>
+                        <bitRange>[25:20]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>IN_BASE</name>
+                        <description>The pin which is mapped to the least-significant bit of a state machine&#39;s IN data bus. Higher-numbered pins are mapped to consecutively more-significant data bits, with a modulo of 32 applied to pin number.</description>
+                        <bitRange>[19:15]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SIDESET_BASE</name>
+                        <description>The lowest-numbered pin that will be affected by a side-set operation. The MSBs of an instruction&#39;s side-set/delay field (up to 5, determined by SIDESET_COUNT) are used for side-set data, with the remaining LSBs used for delay. The least-significant bit of the side-set portion is the bit written to this pin, with more-significant bits written to higher-numbered pins.</description>
+                        <bitRange>[14:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SET_BASE</name>
+                        <description>The lowest-numbered pin that will be affected by a SET PINS or SET PINDIRS instruction. The data written to this pin is the least-significant bit of the SET data.</description>
+                        <bitRange>[9:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>OUT_BASE</name>
+                        <description>The lowest-numbered pin that will be affected by an OUT PINS, OUT PINDIRS or MOV PINS instruction. The data written to this pin will always be the least-significant bit of the OUT or MOV data.</description>
+                        <bitRange>[4:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SM3_CLKDIV</name>
+                <addressOffset>0x00000110</addressOffset>
+                <description>Clock divisor register for state machine 3 
+                    Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256)</description>
+                <resetValue>0x00010000</resetValue>
+                <fields>
+                    <field>
+                        <name>INT</name>
+                        <description>Effective frequency is sysclk/(int + frac/256). 
+                            Value of 0 is interpreted as 65536. If INT is 0, FRAC must also be 0.</description>
+                        <bitRange>[31:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>FRAC</name>
+                        <description>Fractional part of clock divisor</description>
+                        <bitRange>[15:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SM3_EXECCTRL</name>
+                <addressOffset>0x00000114</addressOffset>
+                <description>Execution/behavioural settings for state machine 3</description>
+                <resetValue>0x0001f000</resetValue>
+                <fields>
+                    <field>
+                        <name>EXEC_STALLED</name>
+                        <description>If 1, an instruction written to SMx_INSTR is stalled, and latched by the state machine. Will clear to 0 once this instruction completes.</description>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SIDE_EN</name>
+                        <description>If 1, the MSB of the Delay/Side-set instruction field is used as side-set enable, rather than a side-set data bit. This allows instructions to perform side-set optionally, rather than on every instruction, but the maximum possible side-set width is reduced from 5 to 4. Note that the value of PINCTRL_SIDESET_COUNT is inclusive of this enable bit.</description>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SIDE_PINDIR</name>
+                        <description>If 1, side-set data is asserted to pin directions, instead of pin values</description>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>JMP_PIN</name>
+                        <description>The GPIO number to use as condition for JMP PIN. Unaffected by input mapping.</description>
+                        <bitRange>[28:24]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>OUT_EN_SEL</name>
+                        <description>Which data bit to use for inline OUT enable</description>
+                        <bitRange>[23:19]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INLINE_OUT_EN</name>
+                        <description>If 1, use a bit of OUT data as an auxiliary write enable 
+                            When used in conjunction with OUT_STICKY, writes with an enable of 0 will 
+                            deassert the latest pin write. This can create useful masking/override behaviour 
+                            due to the priority ordering of state machine pin writes (SM0 &lt; SM1 &lt; ...)</description>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>OUT_STICKY</name>
+                        <description>Continuously assert the most recent OUT/SET to the pins</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>WRAP_TOP</name>
+                        <description>After reaching this address, execution is wrapped to wrap_bottom. 
+                            If the instruction is a jump, and the jump condition is true, the jump takes priority.</description>
+                        <bitRange>[16:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>WRAP_BOTTOM</name>
+                        <description>After reaching wrap_top, execution is wrapped to this address.</description>
+                        <bitRange>[11:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>STATUS_SEL</name>
+                        <description>Comparison used for the MOV x, STATUS instruction.</description>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>TXLEVEL</name>
+                                <value>0</value>
+                                <description>All-ones if TX FIFO level &lt; N, otherwise all-zeroes</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>RXLEVEL</name>
+                                <value>1</value>
+                                <description>All-ones if RX FIFO level &lt; N, otherwise all-zeroes</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>STATUS_N</name>
+                        <description>Comparison level for the MOV x, STATUS instruction</description>
+                        <bitRange>[3:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SM3_SHIFTCTRL</name>
+                <addressOffset>0x00000118</addressOffset>
+                <description>Control behaviour of the input/output shift registers for state machine 3</description>
+                <resetValue>0x000c0000</resetValue>
+                <fields>
+                    <field>
+                        <name>FJOIN_RX</name>
+                        <description>When 1, RX FIFO steals the TX FIFO&#39;s storage, and becomes twice as deep. 
+                            TX FIFO is disabled as a result (always reads as both full and empty). 
+                            FIFOs are flushed when this bit is changed.</description>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>FJOIN_TX</name>
+                        <description>When 1, TX FIFO steals the RX FIFO&#39;s storage, and becomes twice as deep. 
+                            RX FIFO is disabled as a result (always reads as both full and empty). 
+                            FIFOs are flushed when this bit is changed.</description>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PULL_THRESH</name>
+                        <description>Number of bits shifted out of OSR before autopull, or conditional pull (PULL IFEMPTY), will take place. 
+                            Write 0 for value of 32.</description>
+                        <bitRange>[29:25]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PUSH_THRESH</name>
+                        <description>Number of bits shifted into ISR before autopush, or conditional push (PUSH IFFULL), will take place. 
+                            Write 0 for value of 32.</description>
+                        <bitRange>[24:20]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>OUT_SHIFTDIR</name>
+                        <description>1 = shift out of output shift register to right. 0 = to left.</description>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>IN_SHIFTDIR</name>
+                        <description>1 = shift input shift register to right (data enters from left). 0 = to left.</description>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>AUTOPULL</name>
+                        <description>Pull automatically when the output shift register is emptied, i.e. on or following an OUT instruction which causes the output shift counter to reach or exceed PULL_THRESH.</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>AUTOPUSH</name>
+                        <description>Push automatically when the input shift register is filled, i.e. on an IN instruction which causes the input shift counter to reach or exceed PUSH_THRESH.</description>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SM3_ADDR</name>
+                <addressOffset>0x0000011c</addressOffset>
+                <description>Current instruction address of state machine 3</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>SM3_ADDR</name>
+                        <bitRange>[4:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SM3_INSTR</name>
+                <addressOffset>0x00000120</addressOffset>
+                <description>Read to see the instruction currently addressed by state machine 3&#39;s program counter 
+                    Write to execute an instruction immediately (including jumps) and then resume execution.</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>SM3_INSTR</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SM3_PINCTRL</name>
+                <addressOffset>0x00000124</addressOffset>
+                <description>State machine pin control</description>
+                <resetValue>0x14000000</resetValue>
+                <fields>
+                    <field>
+                        <name>SIDESET_COUNT</name>
+                        <description>The number of MSBs of the Delay/Side-set instruction field which are used for side-set. Inclusive of the enable bit, if present. Minimum of 0 (all delay bits, no side-set) and maximum of 5 (all side-set, no delay).</description>
+                        <bitRange>[31:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SET_COUNT</name>
+                        <description>The number of pins asserted by a SET. In the range 0 to 5 inclusive.</description>
+                        <bitRange>[28:26]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>OUT_COUNT</name>
+                        <description>The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV PINS instruction. In the range 0 to 32 inclusive.</description>
+                        <bitRange>[25:20]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>IN_BASE</name>
+                        <description>The pin which is mapped to the least-significant bit of a state machine&#39;s IN data bus. Higher-numbered pins are mapped to consecutively more-significant data bits, with a modulo of 32 applied to pin number.</description>
+                        <bitRange>[19:15]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SIDESET_BASE</name>
+                        <description>The lowest-numbered pin that will be affected by a side-set operation. The MSBs of an instruction&#39;s side-set/delay field (up to 5, determined by SIDESET_COUNT) are used for side-set data, with the remaining LSBs used for delay. The least-significant bit of the side-set portion is the bit written to this pin, with more-significant bits written to higher-numbered pins.</description>
+                        <bitRange>[14:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SET_BASE</name>
+                        <description>The lowest-numbered pin that will be affected by a SET PINS or SET PINDIRS instruction. The data written to this pin is the least-significant bit of the SET data.</description>
+                        <bitRange>[9:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>OUT_BASE</name>
+                        <description>The lowest-numbered pin that will be affected by an OUT PINS, OUT PINDIRS or MOV PINS instruction. The data written to this pin will always be the least-significant bit of the OUT or MOV data.</description>
+                        <bitRange>[4:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INTR</name>
+                <addressOffset>0x00000128</addressOffset>
+                <description>Raw Interrupts</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>SM3</name>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SM2</name>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SM1</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SM0</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SM3_TXNFULL</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SM2_TXNFULL</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SM1_TXNFULL</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SM0_TXNFULL</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SM3_RXNEMPTY</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SM2_RXNEMPTY</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SM1_RXNEMPTY</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SM0_RXNEMPTY</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>IRQ0_INTE</name>
+                <addressOffset>0x0000012c</addressOffset>
+                <description>Interrupt Enable for irq0</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>SM3</name>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SM2</name>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SM1</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SM0</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SM3_TXNFULL</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SM2_TXNFULL</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SM1_TXNFULL</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SM0_TXNFULL</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SM3_RXNEMPTY</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SM2_RXNEMPTY</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SM1_RXNEMPTY</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SM0_RXNEMPTY</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>IRQ0_INTF</name>
+                <addressOffset>0x00000130</addressOffset>
+                <description>Interrupt Force for irq0</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>SM3</name>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SM2</name>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SM1</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SM0</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SM3_TXNFULL</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SM2_TXNFULL</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SM1_TXNFULL</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SM0_TXNFULL</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SM3_RXNEMPTY</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SM2_RXNEMPTY</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SM1_RXNEMPTY</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SM0_RXNEMPTY</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>IRQ0_INTS</name>
+                <addressOffset>0x00000134</addressOffset>
+                <description>Interrupt status after masking &amp; forcing for irq0</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>SM3</name>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SM2</name>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SM1</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SM0</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SM3_TXNFULL</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SM2_TXNFULL</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SM1_TXNFULL</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SM0_TXNFULL</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SM3_RXNEMPTY</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SM2_RXNEMPTY</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SM1_RXNEMPTY</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SM0_RXNEMPTY</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>IRQ1_INTE</name>
+                <addressOffset>0x00000138</addressOffset>
+                <description>Interrupt Enable for irq1</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>SM3</name>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SM2</name>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SM1</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SM0</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SM3_TXNFULL</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SM2_TXNFULL</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SM1_TXNFULL</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SM0_TXNFULL</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SM3_RXNEMPTY</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SM2_RXNEMPTY</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SM1_RXNEMPTY</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SM0_RXNEMPTY</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>IRQ1_INTF</name>
+                <addressOffset>0x0000013c</addressOffset>
+                <description>Interrupt Force for irq1</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>SM3</name>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SM2</name>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SM1</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SM0</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SM3_TXNFULL</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SM2_TXNFULL</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SM1_TXNFULL</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SM0_TXNFULL</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SM3_RXNEMPTY</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SM2_RXNEMPTY</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SM1_RXNEMPTY</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SM0_RXNEMPTY</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>IRQ1_INTS</name>
+                <addressOffset>0x00000140</addressOffset>
+                <description>Interrupt status after masking &amp; forcing for irq1</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>SM3</name>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SM2</name>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SM1</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SM0</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SM3_TXNFULL</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SM2_TXNFULL</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SM1_TXNFULL</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SM0_TXNFULL</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SM3_RXNEMPTY</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SM2_RXNEMPTY</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SM1_RXNEMPTY</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SM0_RXNEMPTY</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+        </registers>
+    </peripheral>
+    <peripheral derivedFrom="PIO0">
+        <name>PIO1</name>
+        <baseAddress>0x50300000</baseAddress>
+        <interrupt>
+        <name>PIO1_IRQ_0</name>
+        <value>9</value>
+    </interrupt>
+        <interrupt>
+        <name>PIO1_IRQ_1</name>
+        <value>10</value>
+    </interrupt>
+    </peripheral>
+    <peripheral>
+        <name>BUSCTRL</name>
+        <description>Register block for busfabric control signals and performance counters</description>
+        <baseAddress>0x40030000</baseAddress>
+        <addressBlock>
+            <offset>0</offset>
+            <size>40</size>
+            <usage>registers</usage>
+        </addressBlock>
+        <registers>
+            <register>
+                <name>BUS_PRIORITY</name>
+                <addressOffset>0x00000000</addressOffset>
+                <description>Set the priority of each master for bus arbitration.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>DMA_W</name>
+                        <description>0 - low priority, 1 - high priority</description>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DMA_R</name>
+                        <description>0 - low priority, 1 - high priority</description>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PROC1</name>
+                        <description>0 - low priority, 1 - high priority</description>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PROC0</name>
+                        <description>0 - low priority, 1 - high priority</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>BUS_PRIORITY_ACK</name>
+                <addressOffset>0x00000004</addressOffset>
+                <description>Bus priority acknowledge</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>BUS_PRIORITY_ACK</name>
+                        <description>Goes to 1 once all arbiters have registered the new global priority levels. 
+                            Arbiters update their local priority when servicing a new nonsequential access. 
+                            In normal circumstances this will happen almost immediately.</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PERFCTR0</name>
+                <addressOffset>0x00000008</addressOffset>
+                <description>Bus fabric performance counter 0</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>PERFCTR0</name>
+                        <description>Busfabric saturating performance counter 0 
+                            Count some event signal from the busfabric arbiters. 
+                            Write any value to clear. Select an event to count using PERFSEL0</description>
+                        <bitRange>[23:0]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PERFSEL0</name>
+                <addressOffset>0x0000000c</addressOffset>
+                <description>Bus fabric performance event select for PERFCTR0</description>
+                <resetValue>0x0000001f</resetValue>
+                <fields>
+                    <field>
+                        <name>PERFSEL0</name>
+                        <description>Select an event for PERFCTR0. Count either contested accesses, or all accesses, on a downstream port of the main crossbar.</description>
+                        <bitRange>[4:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>apb_contested</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>apb</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>fastperi_contested</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>fastperi</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram5_contested</name>
+                                <value>4</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram5</name>
+                                <value>5</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram4_contested</name>
+                                <value>6</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram4</name>
+                                <value>7</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram3_contested</name>
+                                <value>8</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram3</name>
+                                <value>9</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram2_contested</name>
+                                <value>10</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram2</name>
+                                <value>11</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram1_contested</name>
+                                <value>12</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram1</name>
+                                <value>13</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram0_contested</name>
+                                <value>14</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram0</name>
+                                <value>15</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>xip_main_contested</name>
+                                <value>16</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>xip_main</name>
+                                <value>17</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>rom_contested</name>
+                                <value>18</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>rom</name>
+                                <value>19</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PERFCTR1</name>
+                <addressOffset>0x00000010</addressOffset>
+                <description>Bus fabric performance counter 1</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>PERFCTR1</name>
+                        <description>Busfabric saturating performance counter 1 
+                            Count some event signal from the busfabric arbiters. 
+                            Write any value to clear. Select an event to count using PERFSEL1</description>
+                        <bitRange>[23:0]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PERFSEL1</name>
+                <addressOffset>0x00000014</addressOffset>
+                <description>Bus fabric performance event select for PERFCTR1</description>
+                <resetValue>0x0000001f</resetValue>
+                <fields>
+                    <field>
+                        <name>PERFSEL1</name>
+                        <description>Select an event for PERFCTR1. Count either contested accesses, or all accesses, on a downstream port of the main crossbar.</description>
+                        <bitRange>[4:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>apb_contested</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>apb</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>fastperi_contested</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>fastperi</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram5_contested</name>
+                                <value>4</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram5</name>
+                                <value>5</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram4_contested</name>
+                                <value>6</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram4</name>
+                                <value>7</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram3_contested</name>
+                                <value>8</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram3</name>
+                                <value>9</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram2_contested</name>
+                                <value>10</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram2</name>
+                                <value>11</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram1_contested</name>
+                                <value>12</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram1</name>
+                                <value>13</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram0_contested</name>
+                                <value>14</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram0</name>
+                                <value>15</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>xip_main_contested</name>
+                                <value>16</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>xip_main</name>
+                                <value>17</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>rom_contested</name>
+                                <value>18</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>rom</name>
+                                <value>19</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PERFCTR2</name>
+                <addressOffset>0x00000018</addressOffset>
+                <description>Bus fabric performance counter 2</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>PERFCTR2</name>
+                        <description>Busfabric saturating performance counter 2 
+                            Count some event signal from the busfabric arbiters. 
+                            Write any value to clear. Select an event to count using PERFSEL2</description>
+                        <bitRange>[23:0]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PERFSEL2</name>
+                <addressOffset>0x0000001c</addressOffset>
+                <description>Bus fabric performance event select for PERFCTR2</description>
+                <resetValue>0x0000001f</resetValue>
+                <fields>
+                    <field>
+                        <name>PERFSEL2</name>
+                        <description>Select an event for PERFCTR2. Count either contested accesses, or all accesses, on a downstream port of the main crossbar.</description>
+                        <bitRange>[4:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>apb_contested</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>apb</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>fastperi_contested</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>fastperi</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram5_contested</name>
+                                <value>4</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram5</name>
+                                <value>5</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram4_contested</name>
+                                <value>6</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram4</name>
+                                <value>7</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram3_contested</name>
+                                <value>8</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram3</name>
+                                <value>9</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram2_contested</name>
+                                <value>10</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram2</name>
+                                <value>11</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram1_contested</name>
+                                <value>12</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram1</name>
+                                <value>13</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram0_contested</name>
+                                <value>14</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram0</name>
+                                <value>15</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>xip_main_contested</name>
+                                <value>16</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>xip_main</name>
+                                <value>17</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>rom_contested</name>
+                                <value>18</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>rom</name>
+                                <value>19</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PERFCTR3</name>
+                <addressOffset>0x00000020</addressOffset>
+                <description>Bus fabric performance counter 3</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>PERFCTR3</name>
+                        <description>Busfabric saturating performance counter 3 
+                            Count some event signal from the busfabric arbiters. 
+                            Write any value to clear. Select an event to count using PERFSEL3</description>
+                        <bitRange>[23:0]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PERFSEL3</name>
+                <addressOffset>0x00000024</addressOffset>
+                <description>Bus fabric performance event select for PERFCTR3</description>
+                <resetValue>0x0000001f</resetValue>
+                <fields>
+                    <field>
+                        <name>PERFSEL3</name>
+                        <description>Select an event for PERFCTR3. Count either contested accesses, or all accesses, on a downstream port of the main crossbar.</description>
+                        <bitRange>[4:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>apb_contested</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>apb</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>fastperi_contested</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>fastperi</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram5_contested</name>
+                                <value>4</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram5</name>
+                                <value>5</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram4_contested</name>
+                                <value>6</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram4</name>
+                                <value>7</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram3_contested</name>
+                                <value>8</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram3</name>
+                                <value>9</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram2_contested</name>
+                                <value>10</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram2</name>
+                                <value>11</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram1_contested</name>
+                                <value>12</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram1</name>
+                                <value>13</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram0_contested</name>
+                                <value>14</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram0</name>
+                                <value>15</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>xip_main_contested</name>
+                                <value>16</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>xip_main</name>
+                                <value>17</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>rom_contested</name>
+                                <value>18</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>rom</name>
+                                <value>19</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+        </registers>
+    </peripheral>
+    <peripheral>
+        <name>SIO</name>
+        <description>Single-cycle IO block 
+            Provides core-local and inter-core hardware for the two processors, with single-cycle access.</description>
+        <baseAddress>0xd0000000</baseAddress>
+        <addressBlock>
+            <offset>0</offset>
+            <size>384</size>
+            <usage>registers</usage>
+        </addressBlock>
+        <interrupt>
+            <name>SIO_IRQ_PROC0</name>
+            <value>15</value>
+        </interrupt>
+        <interrupt>
+            <name>SIO_IRQ_PROC1</name>
+            <value>16</value>
+        </interrupt>
+        <registers>
+            <register>
+                <name>CPUID</name>
+                <addressOffset>0x00000000</addressOffset>
+                <description>Processor core identifier</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CPUID</name>
+                        <description>Value is 0 when read from processor core 0, and 1 when read from processor core 1.</description>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO_IN</name>
+                <addressOffset>0x00000004</addressOffset>
+                <description>Input value for GPIO pins</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>GPIO_IN</name>
+                        <description>Input value for GPIO0...29</description>
+                        <bitRange>[29:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO_HI_IN</name>
+                <addressOffset>0x00000008</addressOffset>
+                <description>Input value for QSPI pins</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>GPIO_HI_IN</name>
+                        <description>Input value on QSPI IO in order 0..5: SCLK, SSn, SD0, SD1, SD2, SD3</description>
+                        <bitRange>[5:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO_OUT</name>
+                <addressOffset>0x00000010</addressOffset>
+                <description>GPIO output value</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>GPIO_OUT</name>
+                        <description>Set output level (1/0 -&gt; high/low) for GPIO0...29. 
+                            Reading back gives the last value written, NOT the input value from the pins. 
+                            If core 0 and core 1 both write to GPIO_OUT simultaneously (or to a SET/CLR/XOR alias), 
+                            the result is as though the write from core 0 took place first, 
+                            and the write from core 1 was then applied to that intermediate result.</description>
+                        <bitRange>[29:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO_OUT_SET</name>
+                <addressOffset>0x00000014</addressOffset>
+                <description>GPIO output value set</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>GPIO_OUT_SET</name>
+                        <description>Perform an atomic bit-set on GPIO_OUT, i.e. `GPIO_OUT |= wdata`</description>
+                        <bitRange>[29:0]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO_OUT_CLR</name>
+                <addressOffset>0x00000018</addressOffset>
+                <description>GPIO output value clear</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>GPIO_OUT_CLR</name>
+                        <description>Perform an atomic bit-clear on GPIO_OUT, i.e. `GPIO_OUT &amp;= ~wdata`</description>
+                        <bitRange>[29:0]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO_OUT_XOR</name>
+                <addressOffset>0x0000001c</addressOffset>
+                <description>GPIO output value XOR</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>GPIO_OUT_XOR</name>
+                        <description>Perform an atomic bitwise XOR on GPIO_OUT, i.e. `GPIO_OUT ^= wdata`</description>
+                        <bitRange>[29:0]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO_OE</name>
+                <addressOffset>0x00000020</addressOffset>
+                <description>GPIO output enable</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>GPIO_OE</name>
+                        <description>Set output enable (1/0 -&gt; output/input) for GPIO0...29. 
+                            Reading back gives the last value written. 
+                            If core 0 and core 1 both write to GPIO_OE simultaneously (or to a SET/CLR/XOR alias), 
+                            the result is as though the write from core 0 took place first, 
+                            and the write from core 1 was then applied to that intermediate result.</description>
+                        <bitRange>[29:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO_OE_SET</name>
+                <addressOffset>0x00000024</addressOffset>
+                <description>GPIO output enable set</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>GPIO_OE_SET</name>
+                        <description>Perform an atomic bit-set on GPIO_OE, i.e. `GPIO_OE |= wdata`</description>
+                        <bitRange>[29:0]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO_OE_CLR</name>
+                <addressOffset>0x00000028</addressOffset>
+                <description>GPIO output enable clear</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>GPIO_OE_CLR</name>
+                        <description>Perform an atomic bit-clear on GPIO_OE, i.e. `GPIO_OE &amp;= ~wdata`</description>
+                        <bitRange>[29:0]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO_OE_XOR</name>
+                <addressOffset>0x0000002c</addressOffset>
+                <description>GPIO output enable XOR</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>GPIO_OE_XOR</name>
+                        <description>Perform an atomic bitwise XOR on GPIO_OE, i.e. `GPIO_OE ^= wdata`</description>
+                        <bitRange>[29:0]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO_HI_OUT</name>
+                <addressOffset>0x00000030</addressOffset>
+                <description>QSPI output value</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>GPIO_HI_OUT</name>
+                        <description>Set output level (1/0 -&gt; high/low) for QSPI IO0...5. 
+                            Reading back gives the last value written, NOT the input value from the pins. 
+                            If core 0 and core 1 both write to GPIO_HI_OUT simultaneously (or to a SET/CLR/XOR alias), 
+                            the result is as though the write from core 0 took place first, 
+                            and the write from core 1 was then applied to that intermediate result.</description>
+                        <bitRange>[5:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO_HI_OUT_SET</name>
+                <addressOffset>0x00000034</addressOffset>
+                <description>QSPI output value set</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>GPIO_HI_OUT_SET</name>
+                        <description>Perform an atomic bit-set on GPIO_HI_OUT, i.e. `GPIO_HI_OUT |= wdata`</description>
+                        <bitRange>[5:0]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO_HI_OUT_CLR</name>
+                <addressOffset>0x00000038</addressOffset>
+                <description>QSPI output value clear</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>GPIO_HI_OUT_CLR</name>
+                        <description>Perform an atomic bit-clear on GPIO_HI_OUT, i.e. `GPIO_HI_OUT &amp;= ~wdata`</description>
+                        <bitRange>[5:0]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO_HI_OUT_XOR</name>
+                <addressOffset>0x0000003c</addressOffset>
+                <description>QSPI output value XOR</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>GPIO_HI_OUT_XOR</name>
+                        <description>Perform an atomic bitwise XOR on GPIO_HI_OUT, i.e. `GPIO_HI_OUT ^= wdata`</description>
+                        <bitRange>[5:0]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO_HI_OE</name>
+                <addressOffset>0x00000040</addressOffset>
+                <description>QSPI output enable</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>GPIO_HI_OE</name>
+                        <description>Set output enable (1/0 -&gt; output/input) for QSPI IO0...5. 
+                            Reading back gives the last value written. 
+                            If core 0 and core 1 both write to GPIO_HI_OE simultaneously (or to a SET/CLR/XOR alias), 
+                            the result is as though the write from core 0 took place first, 
+                            and the write from core 1 was then applied to that intermediate result.</description>
+                        <bitRange>[5:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO_HI_OE_SET</name>
+                <addressOffset>0x00000044</addressOffset>
+                <description>QSPI output enable set</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>GPIO_HI_OE_SET</name>
+                        <description>Perform an atomic bit-set on GPIO_HI_OE, i.e. `GPIO_HI_OE |= wdata`</description>
+                        <bitRange>[5:0]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO_HI_OE_CLR</name>
+                <addressOffset>0x00000048</addressOffset>
+                <description>QSPI output enable clear</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>GPIO_HI_OE_CLR</name>
+                        <description>Perform an atomic bit-clear on GPIO_HI_OE, i.e. `GPIO_HI_OE &amp;= ~wdata`</description>
+                        <bitRange>[5:0]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO_HI_OE_XOR</name>
+                <addressOffset>0x0000004c</addressOffset>
+                <description>QSPI output enable XOR</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>GPIO_HI_OE_XOR</name>
+                        <description>Perform an atomic bitwise XOR on GPIO_HI_OE, i.e. `GPIO_HI_OE ^= wdata`</description>
+                        <bitRange>[5:0]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>FIFO_ST</name>
+                <addressOffset>0x00000050</addressOffset>
+                <description>Status register for inter-core FIFOs (mailboxes). 
+                    There is one FIFO in the core 0 -&gt; core 1 direction, and one core 1 -&gt; core 0. Both are 32 bits wide and 8 words deep. 
+                    Core 0 can see the read side of the 1-&gt;0 FIFO (RX), and the write side of 0-&gt;1 FIFO (TX). 
+                    Core 1 can see the read side of the 0-&gt;1 FIFO (RX), and the write side of 1-&gt;0 FIFO (TX). 
+                    The SIO IRQ for each core is the logical OR of the VLD, WOF and ROE fields of its FIFO_ST register.</description>
+                <resetValue>0x00000002</resetValue>
+                <fields>
+                    <field>
+                        <name>ROE</name>
+                        <description>Sticky flag indicating the RX FIFO was read when empty. This read was ignored by the FIFO.</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>WOF</name>
+                        <description>Sticky flag indicating the TX FIFO was written when full. This write was ignored by the FIFO.</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>RDY</name>
+                        <description>Value is 1 if this core&#39;s TX FIFO is not full (i.e. if FIFO_WR is ready for more data)</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>VLD</name>
+                        <description>Value is 1 if this core&#39;s RX FIFO is not empty (i.e. if FIFO_RD is valid)</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>FIFO_WR</name>
+                <addressOffset>0x00000054</addressOffset>
+                <description>Write access to this core&#39;s TX FIFO</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>FIFO_WR</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>FIFO_RD</name>
+                <addressOffset>0x00000058</addressOffset>
+                <description>Read access to this core&#39;s RX FIFO</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>FIFO_RD</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-only</access>
+                        <readAction>modify</readAction>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SPINLOCK_ST</name>
+                <addressOffset>0x0000005c</addressOffset>
+                <description>Spinlock state 
+                    A bitmap containing the state of all 32 spinlocks (1=locked). 
+                    Mainly intended for debugging.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>SPINLOCK_ST</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>DIV_UDIVIDEND</name>
+                <addressOffset>0x00000060</addressOffset>
+                <description>Divider unsigned dividend 
+                    Write to the DIVIDEND operand of the divider, i.e. the p in `p / q`. 
+                    Any operand write starts a new calculation. The results appear in QUOTIENT, REMAINDER. 
+                    UDIVIDEND/SDIVIDEND are aliases of the same internal register. The U alias starts an 
+                    unsigned calculation, and the S alias starts a signed calculation.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>DIV_UDIVIDEND</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>DIV_UDIVISOR</name>
+                <addressOffset>0x00000064</addressOffset>
+                <description>Divider unsigned divisor 
+                    Write to the DIVISOR operand of the divider, i.e. the q in `p / q`. 
+                    Any operand write starts a new calculation. The results appear in QUOTIENT, REMAINDER. 
+                    UDIVISOR/SDIVISOR are aliases of the same internal register. The U alias starts an 
+                    unsigned calculation, and the S alias starts a signed calculation.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>DIV_UDIVISOR</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>DIV_SDIVIDEND</name>
+                <addressOffset>0x00000068</addressOffset>
+                <description>Divider signed dividend 
+                    The same as UDIVIDEND, but starts a signed calculation, rather than unsigned.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>DIV_SDIVIDEND</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>DIV_SDIVISOR</name>
+                <addressOffset>0x0000006c</addressOffset>
+                <description>Divider signed divisor 
+                    The same as UDIVISOR, but starts a signed calculation, rather than unsigned.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>DIV_SDIVISOR</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>DIV_QUOTIENT</name>
+                <addressOffset>0x00000070</addressOffset>
+                <description>Divider result quotient 
+                    The result of `DIVIDEND / DIVISOR` (division). Contents undefined while CSR_READY is low. 
+                    For signed calculations, QUOTIENT is negative when the signs of DIVIDEND and DIVISOR differ. 
+                    This register can be written to directly, for context save/restore purposes. This halts any 
+                    in-progress calculation and sets the CSR_READY and CSR_DIRTY flags. 
+                    Reading from QUOTIENT clears the CSR_DIRTY flag, so should read results in the order 
+                    REMAINDER, QUOTIENT if CSR_DIRTY is used.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>DIV_QUOTIENT</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>DIV_REMAINDER</name>
+                <addressOffset>0x00000074</addressOffset>
+                <description>Divider result remainder 
+                    The result of `DIVIDEND % DIVISOR` (modulo). Contents undefined while CSR_READY is low. 
+                    For signed calculations, REMAINDER is negative only when DIVIDEND is negative. 
+                    This register can be written to directly, for context save/restore purposes. This halts any 
+                    in-progress calculation and sets the CSR_READY and CSR_DIRTY flags.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>DIV_REMAINDER</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>DIV_CSR</name>
+                <addressOffset>0x00000078</addressOffset>
+                <description>Control and status register for divider.</description>
+                <resetValue>0x00000001</resetValue>
+                <fields>
+                    <field>
+                        <name>DIRTY</name>
+                        <description>Changes to 1 when any register is written, and back to 0 when QUOTIENT is read. 
+                            Software can use this flag to make save/restore more efficient (skip if not DIRTY). 
+                            If the flag is used in this way, it&#39;s recommended to either read QUOTIENT only, 
+                            or REMAINDER and then QUOTIENT, to prevent data loss on context switch.</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>READY</name>
+                        <description>Reads as 0 when a calculation is in progress, 1 otherwise. 
+                            Writing an operand (xDIVIDEND, xDIVISOR) will immediately start a new calculation, no 
+                            matter if one is already in progress. 
+                            Writing to a result register will immediately terminate any in-progress calculation 
+                            and set the READY and DIRTY flags.</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INTERP0_ACCUM0</name>
+                <addressOffset>0x00000080</addressOffset>
+                <description>Read/write access to accumulator 0</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>INTERP0_ACCUM0</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INTERP0_ACCUM1</name>
+                <addressOffset>0x00000084</addressOffset>
+                <description>Read/write access to accumulator 1</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>INTERP0_ACCUM1</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INTERP0_BASE0</name>
+                <addressOffset>0x00000088</addressOffset>
+                <description>Read/write access to BASE0 register.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>INTERP0_BASE0</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INTERP0_BASE1</name>
+                <addressOffset>0x0000008c</addressOffset>
+                <description>Read/write access to BASE1 register.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>INTERP0_BASE1</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INTERP0_BASE2</name>
+                <addressOffset>0x00000090</addressOffset>
+                <description>Read/write access to BASE2 register.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>INTERP0_BASE2</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INTERP0_POP_LANE0</name>
+                <addressOffset>0x00000094</addressOffset>
+                <description>Read LANE0 result, and simultaneously write lane results to both accumulators (POP).</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>INTERP0_POP_LANE0</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INTERP0_POP_LANE1</name>
+                <addressOffset>0x00000098</addressOffset>
+                <description>Read LANE1 result, and simultaneously write lane results to both accumulators (POP).</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>INTERP0_POP_LANE1</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INTERP0_POP_FULL</name>
+                <addressOffset>0x0000009c</addressOffset>
+                <description>Read FULL result, and simultaneously write lane results to both accumulators (POP).</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>INTERP0_POP_FULL</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INTERP0_PEEK_LANE0</name>
+                <addressOffset>0x000000a0</addressOffset>
+                <description>Read LANE0 result, without altering any internal state (PEEK).</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>INTERP0_PEEK_LANE0</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INTERP0_PEEK_LANE1</name>
+                <addressOffset>0x000000a4</addressOffset>
+                <description>Read LANE1 result, without altering any internal state (PEEK).</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>INTERP0_PEEK_LANE1</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INTERP0_PEEK_FULL</name>
+                <addressOffset>0x000000a8</addressOffset>
+                <description>Read FULL result, without altering any internal state (PEEK).</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>INTERP0_PEEK_FULL</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INTERP0_CTRL_LANE0</name>
+                <addressOffset>0x000000ac</addressOffset>
+                <description>Control register for lane 0</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>OVERF</name>
+                        <description>Set if either OVERF0 or OVERF1 is set.</description>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OVERF1</name>
+                        <description>Indicates if any masked-off MSBs in ACCUM1 are set.</description>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OVERF0</name>
+                        <description>Indicates if any masked-off MSBs in ACCUM0 are set.</description>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>BLEND</name>
+                        <description>Only present on INTERP0 on each core. If BLEND mode is enabled: 
+                            - LANE1 result is a linear interpolation between BASE0 and BASE1, controlled 
+                            by the 8 LSBs of lane 1 shift and mask value (a fractional number between 
+                            0 and 255/256ths) 
+                            - LANE0 result does not have BASE0 added (yields only the 8 LSBs of lane 1 shift+mask value) 
+                            - FULL result does not have lane 1 shift+mask value added (BASE2 + lane 0 shift+mask) 
+                            LANE1 SIGNED flag controls whether the interpolation is signed or unsigned.</description>
+                        <bitRange>[21:21]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>FORCE_MSB</name>
+                        <description>ORed into bits 29:28 of the lane result presented to the processor on the bus. 
+                            No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence 
+                            of pointers into flash or SRAM.</description>
+                        <bitRange>[20:19]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ADD_RAW</name>
+                        <description>If 1, mask + shift is bypassed for LANE0 result. This does not affect FULL result.</description>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CROSS_RESULT</name>
+                        <description>If 1, feed the opposite lane&#39;s result into this lane&#39;s accumulator on POP.</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CROSS_INPUT</name>
+                        <description>If 1, feed the opposite lane&#39;s accumulator into this lane&#39;s shift + mask hardware. 
+                            Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass)</description>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SIGNED</name>
+                        <description>If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits 
+                            before adding to BASE0, and LANE0 PEEK/POP appear extended to 32 bits when read by processor.</description>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>MASK_MSB</name>
+                        <description>The most-significant bit allowed to pass by the mask (inclusive) 
+                            Setting MSB &lt; LSB may cause chip to turn inside-out</description>
+                        <bitRange>[14:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>MASK_LSB</name>
+                        <description>The least-significant bit allowed to pass by the mask (inclusive)</description>
+                        <bitRange>[9:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SHIFT</name>
+                        <description>Logical right-shift applied to accumulator before masking</description>
+                        <bitRange>[4:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INTERP0_CTRL_LANE1</name>
+                <addressOffset>0x000000b0</addressOffset>
+                <description>Control register for lane 1</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>FORCE_MSB</name>
+                        <description>ORed into bits 29:28 of the lane result presented to the processor on the bus. 
+                            No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence 
+                            of pointers into flash or SRAM.</description>
+                        <bitRange>[20:19]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ADD_RAW</name>
+                        <description>If 1, mask + shift is bypassed for LANE1 result. This does not affect FULL result.</description>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CROSS_RESULT</name>
+                        <description>If 1, feed the opposite lane&#39;s result into this lane&#39;s accumulator on POP.</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CROSS_INPUT</name>
+                        <description>If 1, feed the opposite lane&#39;s accumulator into this lane&#39;s shift + mask hardware. 
+                            Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass)</description>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SIGNED</name>
+                        <description>If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits 
+                            before adding to BASE1, and LANE1 PEEK/POP appear extended to 32 bits when read by processor.</description>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>MASK_MSB</name>
+                        <description>The most-significant bit allowed to pass by the mask (inclusive) 
+                            Setting MSB &lt; LSB may cause chip to turn inside-out</description>
+                        <bitRange>[14:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>MASK_LSB</name>
+                        <description>The least-significant bit allowed to pass by the mask (inclusive)</description>
+                        <bitRange>[9:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SHIFT</name>
+                        <description>Logical right-shift applied to accumulator before masking</description>
+                        <bitRange>[4:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INTERP0_ACCUM0_ADD</name>
+                <addressOffset>0x000000b4</addressOffset>
+                <description>Values written here are atomically added to ACCUM0 
+                    Reading yields lane 0&#39;s raw shift and mask value (BASE0 not added).</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>INTERP0_ACCUM0_ADD</name>
+                        <bitRange>[23:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INTERP0_ACCUM1_ADD</name>
+                <addressOffset>0x000000b8</addressOffset>
+                <description>Values written here are atomically added to ACCUM1 
+                    Reading yields lane 1&#39;s raw shift and mask value (BASE1 not added).</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>INTERP0_ACCUM1_ADD</name>
+                        <bitRange>[23:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INTERP0_BASE_1AND0</name>
+                <addressOffset>0x000000bc</addressOffset>
+                <description>On write, the lower 16 bits go to BASE0, upper bits to BASE1 simultaneously. 
+                    Each half is sign-extended to 32 bits if that lane&#39;s SIGNED flag is set.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>INTERP0_BASE_1AND0</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INTERP1_ACCUM0</name>
+                <addressOffset>0x000000c0</addressOffset>
+                <description>Read/write access to accumulator 0</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>INTERP1_ACCUM0</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INTERP1_ACCUM1</name>
+                <addressOffset>0x000000c4</addressOffset>
+                <description>Read/write access to accumulator 1</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>INTERP1_ACCUM1</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INTERP1_BASE0</name>
+                <addressOffset>0x000000c8</addressOffset>
+                <description>Read/write access to BASE0 register.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>INTERP1_BASE0</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INTERP1_BASE1</name>
+                <addressOffset>0x000000cc</addressOffset>
+                <description>Read/write access to BASE1 register.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>INTERP1_BASE1</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INTERP1_BASE2</name>
+                <addressOffset>0x000000d0</addressOffset>
+                <description>Read/write access to BASE2 register.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>INTERP1_BASE2</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INTERP1_POP_LANE0</name>
+                <addressOffset>0x000000d4</addressOffset>
+                <description>Read LANE0 result, and simultaneously write lane results to both accumulators (POP).</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>INTERP1_POP_LANE0</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INTERP1_POP_LANE1</name>
+                <addressOffset>0x000000d8</addressOffset>
+                <description>Read LANE1 result, and simultaneously write lane results to both accumulators (POP).</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>INTERP1_POP_LANE1</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INTERP1_POP_FULL</name>
+                <addressOffset>0x000000dc</addressOffset>
+                <description>Read FULL result, and simultaneously write lane results to both accumulators (POP).</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>INTERP1_POP_FULL</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INTERP1_PEEK_LANE0</name>
+                <addressOffset>0x000000e0</addressOffset>
+                <description>Read LANE0 result, without altering any internal state (PEEK).</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>INTERP1_PEEK_LANE0</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INTERP1_PEEK_LANE1</name>
+                <addressOffset>0x000000e4</addressOffset>
+                <description>Read LANE1 result, without altering any internal state (PEEK).</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>INTERP1_PEEK_LANE1</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INTERP1_PEEK_FULL</name>
+                <addressOffset>0x000000e8</addressOffset>
+                <description>Read FULL result, without altering any internal state (PEEK).</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>INTERP1_PEEK_FULL</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INTERP1_CTRL_LANE0</name>
+                <addressOffset>0x000000ec</addressOffset>
+                <description>Control register for lane 0</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>OVERF</name>
+                        <description>Set if either OVERF0 or OVERF1 is set.</description>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OVERF1</name>
+                        <description>Indicates if any masked-off MSBs in ACCUM1 are set.</description>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OVERF0</name>
+                        <description>Indicates if any masked-off MSBs in ACCUM0 are set.</description>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CLAMP</name>
+                        <description>Only present on INTERP1 on each core. If CLAMP mode is enabled: 
+                            - LANE0 result is shifted and masked ACCUM0, clamped by a lower bound of 
+                            BASE0 and an upper bound of BASE1. 
+                            - Signedness of these comparisons is determined by LANE0_CTRL_SIGNED</description>
+                        <bitRange>[22:22]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>FORCE_MSB</name>
+                        <description>ORed into bits 29:28 of the lane result presented to the processor on the bus. 
+                            No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence 
+                            of pointers into flash or SRAM.</description>
+                        <bitRange>[20:19]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ADD_RAW</name>
+                        <description>If 1, mask + shift is bypassed for LANE0 result. This does not affect FULL result.</description>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CROSS_RESULT</name>
+                        <description>If 1, feed the opposite lane&#39;s result into this lane&#39;s accumulator on POP.</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CROSS_INPUT</name>
+                        <description>If 1, feed the opposite lane&#39;s accumulator into this lane&#39;s shift + mask hardware. 
+                            Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass)</description>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SIGNED</name>
+                        <description>If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits 
+                            before adding to BASE0, and LANE0 PEEK/POP appear extended to 32 bits when read by processor.</description>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>MASK_MSB</name>
+                        <description>The most-significant bit allowed to pass by the mask (inclusive) 
+                            Setting MSB &lt; LSB may cause chip to turn inside-out</description>
+                        <bitRange>[14:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>MASK_LSB</name>
+                        <description>The least-significant bit allowed to pass by the mask (inclusive)</description>
+                        <bitRange>[9:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SHIFT</name>
+                        <description>Logical right-shift applied to accumulator before masking</description>
+                        <bitRange>[4:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INTERP1_CTRL_LANE1</name>
+                <addressOffset>0x000000f0</addressOffset>
+                <description>Control register for lane 1</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>FORCE_MSB</name>
+                        <description>ORed into bits 29:28 of the lane result presented to the processor on the bus. 
+                            No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence 
+                            of pointers into flash or SRAM.</description>
+                        <bitRange>[20:19]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ADD_RAW</name>
+                        <description>If 1, mask + shift is bypassed for LANE1 result. This does not affect FULL result.</description>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CROSS_RESULT</name>
+                        <description>If 1, feed the opposite lane&#39;s result into this lane&#39;s accumulator on POP.</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CROSS_INPUT</name>
+                        <description>If 1, feed the opposite lane&#39;s accumulator into this lane&#39;s shift + mask hardware. 
+                            Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass)</description>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SIGNED</name>
+                        <description>If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits 
+                            before adding to BASE1, and LANE1 PEEK/POP appear extended to 32 bits when read by processor.</description>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>MASK_MSB</name>
+                        <description>The most-significant bit allowed to pass by the mask (inclusive) 
+                            Setting MSB &lt; LSB may cause chip to turn inside-out</description>
+                        <bitRange>[14:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>MASK_LSB</name>
+                        <description>The least-significant bit allowed to pass by the mask (inclusive)</description>
+                        <bitRange>[9:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SHIFT</name>
+                        <description>Logical right-shift applied to accumulator before masking</description>
+                        <bitRange>[4:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INTERP1_ACCUM0_ADD</name>
+                <addressOffset>0x000000f4</addressOffset>
+                <description>Values written here are atomically added to ACCUM0 
+                    Reading yields lane 0&#39;s raw shift and mask value (BASE0 not added).</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>INTERP1_ACCUM0_ADD</name>
+                        <bitRange>[23:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INTERP1_ACCUM1_ADD</name>
+                <addressOffset>0x000000f8</addressOffset>
+                <description>Values written here are atomically added to ACCUM1 
+                    Reading yields lane 1&#39;s raw shift and mask value (BASE1 not added).</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>INTERP1_ACCUM1_ADD</name>
+                        <bitRange>[23:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INTERP1_BASE_1AND0</name>
+                <addressOffset>0x000000fc</addressOffset>
+                <description>On write, the lower 16 bits go to BASE0, upper bits to BASE1 simultaneously. 
+                    Each half is sign-extended to 32 bits if that lane&#39;s SIGNED flag is set.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>INTERP1_BASE_1AND0</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SPINLOCK0</name>
+                <addressOffset>0x00000100</addressOffset>
+                <description>Reading from a spinlock address will: 
+                    - Return 0 if lock is already locked 
+                    - Otherwise return nonzero, and simultaneously claim the lock
+
+                    Writing (any value) releases the lock. 
+                    If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. 
+                    The value returned on success is 0x1 &lt;&lt; lock number.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>SPINLOCK0</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                        <readAction>modify</readAction>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SPINLOCK1</name>
+                <addressOffset>0x00000104</addressOffset>
+                <description>Reading from a spinlock address will: 
+                    - Return 0 if lock is already locked 
+                    - Otherwise return nonzero, and simultaneously claim the lock
+
+                    Writing (any value) releases the lock. 
+                    If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. 
+                    The value returned on success is 0x1 &lt;&lt; lock number.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>SPINLOCK1</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                        <readAction>modify</readAction>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SPINLOCK2</name>
+                <addressOffset>0x00000108</addressOffset>
+                <description>Reading from a spinlock address will: 
+                    - Return 0 if lock is already locked 
+                    - Otherwise return nonzero, and simultaneously claim the lock
+
+                    Writing (any value) releases the lock. 
+                    If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. 
+                    The value returned on success is 0x1 &lt;&lt; lock number.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>SPINLOCK2</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                        <readAction>modify</readAction>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SPINLOCK3</name>
+                <addressOffset>0x0000010c</addressOffset>
+                <description>Reading from a spinlock address will: 
+                    - Return 0 if lock is already locked 
+                    - Otherwise return nonzero, and simultaneously claim the lock
+
+                    Writing (any value) releases the lock. 
+                    If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. 
+                    The value returned on success is 0x1 &lt;&lt; lock number.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>SPINLOCK3</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                        <readAction>modify</readAction>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SPINLOCK4</name>
+                <addressOffset>0x00000110</addressOffset>
+                <description>Reading from a spinlock address will: 
+                    - Return 0 if lock is already locked 
+                    - Otherwise return nonzero, and simultaneously claim the lock
+
+                    Writing (any value) releases the lock. 
+                    If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. 
+                    The value returned on success is 0x1 &lt;&lt; lock number.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>SPINLOCK4</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                        <readAction>modify</readAction>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SPINLOCK5</name>
+                <addressOffset>0x00000114</addressOffset>
+                <description>Reading from a spinlock address will: 
+                    - Return 0 if lock is already locked 
+                    - Otherwise return nonzero, and simultaneously claim the lock
+
+                    Writing (any value) releases the lock. 
+                    If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. 
+                    The value returned on success is 0x1 &lt;&lt; lock number.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>SPINLOCK5</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                        <readAction>modify</readAction>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SPINLOCK6</name>
+                <addressOffset>0x00000118</addressOffset>
+                <description>Reading from a spinlock address will: 
+                    - Return 0 if lock is already locked 
+                    - Otherwise return nonzero, and simultaneously claim the lock
+
+                    Writing (any value) releases the lock. 
+                    If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. 
+                    The value returned on success is 0x1 &lt;&lt; lock number.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>SPINLOCK6</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                        <readAction>modify</readAction>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SPINLOCK7</name>
+                <addressOffset>0x0000011c</addressOffset>
+                <description>Reading from a spinlock address will: 
+                    - Return 0 if lock is already locked 
+                    - Otherwise return nonzero, and simultaneously claim the lock
+
+                    Writing (any value) releases the lock. 
+                    If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. 
+                    The value returned on success is 0x1 &lt;&lt; lock number.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>SPINLOCK7</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                        <readAction>modify</readAction>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SPINLOCK8</name>
+                <addressOffset>0x00000120</addressOffset>
+                <description>Reading from a spinlock address will: 
+                    - Return 0 if lock is already locked 
+                    - Otherwise return nonzero, and simultaneously claim the lock
+
+                    Writing (any value) releases the lock. 
+                    If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. 
+                    The value returned on success is 0x1 &lt;&lt; lock number.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>SPINLOCK8</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                        <readAction>modify</readAction>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SPINLOCK9</name>
+                <addressOffset>0x00000124</addressOffset>
+                <description>Reading from a spinlock address will: 
+                    - Return 0 if lock is already locked 
+                    - Otherwise return nonzero, and simultaneously claim the lock
+
+                    Writing (any value) releases the lock. 
+                    If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. 
+                    The value returned on success is 0x1 &lt;&lt; lock number.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>SPINLOCK9</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                        <readAction>modify</readAction>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SPINLOCK10</name>
+                <addressOffset>0x00000128</addressOffset>
+                <description>Reading from a spinlock address will: 
+                    - Return 0 if lock is already locked 
+                    - Otherwise return nonzero, and simultaneously claim the lock
+
+                    Writing (any value) releases the lock. 
+                    If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. 
+                    The value returned on success is 0x1 &lt;&lt; lock number.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>SPINLOCK10</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                        <readAction>modify</readAction>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SPINLOCK11</name>
+                <addressOffset>0x0000012c</addressOffset>
+                <description>Reading from a spinlock address will: 
+                    - Return 0 if lock is already locked 
+                    - Otherwise return nonzero, and simultaneously claim the lock
+
+                    Writing (any value) releases the lock. 
+                    If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. 
+                    The value returned on success is 0x1 &lt;&lt; lock number.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>SPINLOCK11</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                        <readAction>modify</readAction>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SPINLOCK12</name>
+                <addressOffset>0x00000130</addressOffset>
+                <description>Reading from a spinlock address will: 
+                    - Return 0 if lock is already locked 
+                    - Otherwise return nonzero, and simultaneously claim the lock
+
+                    Writing (any value) releases the lock. 
+                    If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. 
+                    The value returned on success is 0x1 &lt;&lt; lock number.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>SPINLOCK12</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                        <readAction>modify</readAction>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SPINLOCK13</name>
+                <addressOffset>0x00000134</addressOffset>
+                <description>Reading from a spinlock address will: 
+                    - Return 0 if lock is already locked 
+                    - Otherwise return nonzero, and simultaneously claim the lock
+
+                    Writing (any value) releases the lock. 
+                    If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. 
+                    The value returned on success is 0x1 &lt;&lt; lock number.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>SPINLOCK13</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                        <readAction>modify</readAction>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SPINLOCK14</name>
+                <addressOffset>0x00000138</addressOffset>
+                <description>Reading from a spinlock address will: 
+                    - Return 0 if lock is already locked 
+                    - Otherwise return nonzero, and simultaneously claim the lock
+
+                    Writing (any value) releases the lock. 
+                    If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. 
+                    The value returned on success is 0x1 &lt;&lt; lock number.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>SPINLOCK14</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                        <readAction>modify</readAction>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SPINLOCK15</name>
+                <addressOffset>0x0000013c</addressOffset>
+                <description>Reading from a spinlock address will: 
+                    - Return 0 if lock is already locked 
+                    - Otherwise return nonzero, and simultaneously claim the lock
+
+                    Writing (any value) releases the lock. 
+                    If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. 
+                    The value returned on success is 0x1 &lt;&lt; lock number.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>SPINLOCK15</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                        <readAction>modify</readAction>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SPINLOCK16</name>
+                <addressOffset>0x00000140</addressOffset>
+                <description>Reading from a spinlock address will: 
+                    - Return 0 if lock is already locked 
+                    - Otherwise return nonzero, and simultaneously claim the lock
+
+                    Writing (any value) releases the lock. 
+                    If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. 
+                    The value returned on success is 0x1 &lt;&lt; lock number.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>SPINLOCK16</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                        <readAction>modify</readAction>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SPINLOCK17</name>
+                <addressOffset>0x00000144</addressOffset>
+                <description>Reading from a spinlock address will: 
+                    - Return 0 if lock is already locked 
+                    - Otherwise return nonzero, and simultaneously claim the lock
+
+                    Writing (any value) releases the lock. 
+                    If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. 
+                    The value returned on success is 0x1 &lt;&lt; lock number.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>SPINLOCK17</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                        <readAction>modify</readAction>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SPINLOCK18</name>
+                <addressOffset>0x00000148</addressOffset>
+                <description>Reading from a spinlock address will: 
+                    - Return 0 if lock is already locked 
+                    - Otherwise return nonzero, and simultaneously claim the lock
+
+                    Writing (any value) releases the lock. 
+                    If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. 
+                    The value returned on success is 0x1 &lt;&lt; lock number.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>SPINLOCK18</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                        <readAction>modify</readAction>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SPINLOCK19</name>
+                <addressOffset>0x0000014c</addressOffset>
+                <description>Reading from a spinlock address will: 
+                    - Return 0 if lock is already locked 
+                    - Otherwise return nonzero, and simultaneously claim the lock
+
+                    Writing (any value) releases the lock. 
+                    If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. 
+                    The value returned on success is 0x1 &lt;&lt; lock number.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>SPINLOCK19</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                        <readAction>modify</readAction>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SPINLOCK20</name>
+                <addressOffset>0x00000150</addressOffset>
+                <description>Reading from a spinlock address will: 
+                    - Return 0 if lock is already locked 
+                    - Otherwise return nonzero, and simultaneously claim the lock
+
+                    Writing (any value) releases the lock. 
+                    If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. 
+                    The value returned on success is 0x1 &lt;&lt; lock number.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>SPINLOCK20</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                        <readAction>modify</readAction>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SPINLOCK21</name>
+                <addressOffset>0x00000154</addressOffset>
+                <description>Reading from a spinlock address will: 
+                    - Return 0 if lock is already locked 
+                    - Otherwise return nonzero, and simultaneously claim the lock
+
+                    Writing (any value) releases the lock. 
+                    If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. 
+                    The value returned on success is 0x1 &lt;&lt; lock number.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>SPINLOCK21</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                        <readAction>modify</readAction>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SPINLOCK22</name>
+                <addressOffset>0x00000158</addressOffset>
+                <description>Reading from a spinlock address will: 
+                    - Return 0 if lock is already locked 
+                    - Otherwise return nonzero, and simultaneously claim the lock
+
+                    Writing (any value) releases the lock. 
+                    If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. 
+                    The value returned on success is 0x1 &lt;&lt; lock number.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>SPINLOCK22</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                        <readAction>modify</readAction>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SPINLOCK23</name>
+                <addressOffset>0x0000015c</addressOffset>
+                <description>Reading from a spinlock address will: 
+                    - Return 0 if lock is already locked 
+                    - Otherwise return nonzero, and simultaneously claim the lock
+
+                    Writing (any value) releases the lock. 
+                    If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. 
+                    The value returned on success is 0x1 &lt;&lt; lock number.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>SPINLOCK23</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                        <readAction>modify</readAction>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SPINLOCK24</name>
+                <addressOffset>0x00000160</addressOffset>
+                <description>Reading from a spinlock address will: 
+                    - Return 0 if lock is already locked 
+                    - Otherwise return nonzero, and simultaneously claim the lock
+
+                    Writing (any value) releases the lock. 
+                    If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. 
+                    The value returned on success is 0x1 &lt;&lt; lock number.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>SPINLOCK24</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                        <readAction>modify</readAction>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SPINLOCK25</name>
+                <addressOffset>0x00000164</addressOffset>
+                <description>Reading from a spinlock address will: 
+                    - Return 0 if lock is already locked 
+                    - Otherwise return nonzero, and simultaneously claim the lock
+
+                    Writing (any value) releases the lock. 
+                    If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. 
+                    The value returned on success is 0x1 &lt;&lt; lock number.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>SPINLOCK25</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                        <readAction>modify</readAction>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SPINLOCK26</name>
+                <addressOffset>0x00000168</addressOffset>
+                <description>Reading from a spinlock address will: 
+                    - Return 0 if lock is already locked 
+                    - Otherwise return nonzero, and simultaneously claim the lock
+
+                    Writing (any value) releases the lock. 
+                    If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. 
+                    The value returned on success is 0x1 &lt;&lt; lock number.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>SPINLOCK26</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                        <readAction>modify</readAction>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SPINLOCK27</name>
+                <addressOffset>0x0000016c</addressOffset>
+                <description>Reading from a spinlock address will: 
+                    - Return 0 if lock is already locked 
+                    - Otherwise return nonzero, and simultaneously claim the lock
+
+                    Writing (any value) releases the lock. 
+                    If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. 
+                    The value returned on success is 0x1 &lt;&lt; lock number.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>SPINLOCK27</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                        <readAction>modify</readAction>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SPINLOCK28</name>
+                <addressOffset>0x00000170</addressOffset>
+                <description>Reading from a spinlock address will: 
+                    - Return 0 if lock is already locked 
+                    - Otherwise return nonzero, and simultaneously claim the lock
+
+                    Writing (any value) releases the lock. 
+                    If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. 
+                    The value returned on success is 0x1 &lt;&lt; lock number.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>SPINLOCK28</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                        <readAction>modify</readAction>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SPINLOCK29</name>
+                <addressOffset>0x00000174</addressOffset>
+                <description>Reading from a spinlock address will: 
+                    - Return 0 if lock is already locked 
+                    - Otherwise return nonzero, and simultaneously claim the lock
+
+                    Writing (any value) releases the lock. 
+                    If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. 
+                    The value returned on success is 0x1 &lt;&lt; lock number.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>SPINLOCK29</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                        <readAction>modify</readAction>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SPINLOCK30</name>
+                <addressOffset>0x00000178</addressOffset>
+                <description>Reading from a spinlock address will: 
+                    - Return 0 if lock is already locked 
+                    - Otherwise return nonzero, and simultaneously claim the lock
+
+                    Writing (any value) releases the lock. 
+                    If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. 
+                    The value returned on success is 0x1 &lt;&lt; lock number.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>SPINLOCK30</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                        <readAction>modify</readAction>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SPINLOCK31</name>
+                <addressOffset>0x0000017c</addressOffset>
+                <description>Reading from a spinlock address will: 
+                    - Return 0 if lock is already locked 
+                    - Otherwise return nonzero, and simultaneously claim the lock
+
+                    Writing (any value) releases the lock. 
+                    If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. 
+                    The value returned on success is 0x1 &lt;&lt; lock number.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>SPINLOCK31</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                        <readAction>modify</readAction>
+                    </field>
+                </fields>
+            </register>
+        </registers>
+    </peripheral>
+    <peripheral>
+        <name>USB</name>
+        <description>USB FS/LS controller device registers</description>
+        <baseAddress>0x50110000</baseAddress>
+        <addressBlock>
+            <offset>0</offset>
+            <size>156</size>
+            <usage>registers</usage>
+        </addressBlock>
+        <interrupt>
+            <name>USBCTRL_IRQ</name>
+            <value>5</value>
+        </interrupt>
+        <registers>
+            <register>
+                <name>ADDR_ENDP</name>
+                <addressOffset>0x00000000</addressOffset>
+                <description>Device address and endpoint control</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>ENDPOINT</name>
+                        <description>Device endpoint to send data to. Only valid for HOST mode.</description>
+                        <bitRange>[19:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ADDRESS</name>
+                        <description>In device mode, the address that the device should respond to. Set in response to a SET_ADDR setup packet from the host. In host mode set to the address of the device to communicate with.</description>
+                        <bitRange>[6:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>ADDR_ENDP1</name>
+                <addressOffset>0x00000004</addressOffset>
+                <description>Interrupt endpoint 1. Only valid for HOST mode.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>INTEP_PREAMBLE</name>
+                        <description>Interrupt EP requires preamble (is a low speed device on a full speed hub)</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTEP_DIR</name>
+                        <description>Direction of the interrupt endpoint. In=0, Out=1</description>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ENDPOINT</name>
+                        <description>Endpoint number of the interrupt endpoint</description>
+                        <bitRange>[19:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ADDRESS</name>
+                        <description>Device address</description>
+                        <bitRange>[6:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>ADDR_ENDP2</name>
+                <addressOffset>0x00000008</addressOffset>
+                <description>Interrupt endpoint 2. Only valid for HOST mode.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>INTEP_PREAMBLE</name>
+                        <description>Interrupt EP requires preamble (is a low speed device on a full speed hub)</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTEP_DIR</name>
+                        <description>Direction of the interrupt endpoint. In=0, Out=1</description>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ENDPOINT</name>
+                        <description>Endpoint number of the interrupt endpoint</description>
+                        <bitRange>[19:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ADDRESS</name>
+                        <description>Device address</description>
+                        <bitRange>[6:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>ADDR_ENDP3</name>
+                <addressOffset>0x0000000c</addressOffset>
+                <description>Interrupt endpoint 3. Only valid for HOST mode.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>INTEP_PREAMBLE</name>
+                        <description>Interrupt EP requires preamble (is a low speed device on a full speed hub)</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTEP_DIR</name>
+                        <description>Direction of the interrupt endpoint. In=0, Out=1</description>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ENDPOINT</name>
+                        <description>Endpoint number of the interrupt endpoint</description>
+                        <bitRange>[19:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ADDRESS</name>
+                        <description>Device address</description>
+                        <bitRange>[6:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>ADDR_ENDP4</name>
+                <addressOffset>0x00000010</addressOffset>
+                <description>Interrupt endpoint 4. Only valid for HOST mode.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>INTEP_PREAMBLE</name>
+                        <description>Interrupt EP requires preamble (is a low speed device on a full speed hub)</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTEP_DIR</name>
+                        <description>Direction of the interrupt endpoint. In=0, Out=1</description>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ENDPOINT</name>
+                        <description>Endpoint number of the interrupt endpoint</description>
+                        <bitRange>[19:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ADDRESS</name>
+                        <description>Device address</description>
+                        <bitRange>[6:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>ADDR_ENDP5</name>
+                <addressOffset>0x00000014</addressOffset>
+                <description>Interrupt endpoint 5. Only valid for HOST mode.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>INTEP_PREAMBLE</name>
+                        <description>Interrupt EP requires preamble (is a low speed device on a full speed hub)</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTEP_DIR</name>
+                        <description>Direction of the interrupt endpoint. In=0, Out=1</description>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ENDPOINT</name>
+                        <description>Endpoint number of the interrupt endpoint</description>
+                        <bitRange>[19:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ADDRESS</name>
+                        <description>Device address</description>
+                        <bitRange>[6:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>ADDR_ENDP6</name>
+                <addressOffset>0x00000018</addressOffset>
+                <description>Interrupt endpoint 6. Only valid for HOST mode.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>INTEP_PREAMBLE</name>
+                        <description>Interrupt EP requires preamble (is a low speed device on a full speed hub)</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTEP_DIR</name>
+                        <description>Direction of the interrupt endpoint. In=0, Out=1</description>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ENDPOINT</name>
+                        <description>Endpoint number of the interrupt endpoint</description>
+                        <bitRange>[19:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ADDRESS</name>
+                        <description>Device address</description>
+                        <bitRange>[6:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>ADDR_ENDP7</name>
+                <addressOffset>0x0000001c</addressOffset>
+                <description>Interrupt endpoint 7. Only valid for HOST mode.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>INTEP_PREAMBLE</name>
+                        <description>Interrupt EP requires preamble (is a low speed device on a full speed hub)</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTEP_DIR</name>
+                        <description>Direction of the interrupt endpoint. In=0, Out=1</description>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ENDPOINT</name>
+                        <description>Endpoint number of the interrupt endpoint</description>
+                        <bitRange>[19:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ADDRESS</name>
+                        <description>Device address</description>
+                        <bitRange>[6:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>ADDR_ENDP8</name>
+                <addressOffset>0x00000020</addressOffset>
+                <description>Interrupt endpoint 8. Only valid for HOST mode.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>INTEP_PREAMBLE</name>
+                        <description>Interrupt EP requires preamble (is a low speed device on a full speed hub)</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTEP_DIR</name>
+                        <description>Direction of the interrupt endpoint. In=0, Out=1</description>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ENDPOINT</name>
+                        <description>Endpoint number of the interrupt endpoint</description>
+                        <bitRange>[19:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ADDRESS</name>
+                        <description>Device address</description>
+                        <bitRange>[6:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>ADDR_ENDP9</name>
+                <addressOffset>0x00000024</addressOffset>
+                <description>Interrupt endpoint 9. Only valid for HOST mode.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>INTEP_PREAMBLE</name>
+                        <description>Interrupt EP requires preamble (is a low speed device on a full speed hub)</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTEP_DIR</name>
+                        <description>Direction of the interrupt endpoint. In=0, Out=1</description>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ENDPOINT</name>
+                        <description>Endpoint number of the interrupt endpoint</description>
+                        <bitRange>[19:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ADDRESS</name>
+                        <description>Device address</description>
+                        <bitRange>[6:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>ADDR_ENDP10</name>
+                <addressOffset>0x00000028</addressOffset>
+                <description>Interrupt endpoint 10. Only valid for HOST mode.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>INTEP_PREAMBLE</name>
+                        <description>Interrupt EP requires preamble (is a low speed device on a full speed hub)</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTEP_DIR</name>
+                        <description>Direction of the interrupt endpoint. In=0, Out=1</description>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ENDPOINT</name>
+                        <description>Endpoint number of the interrupt endpoint</description>
+                        <bitRange>[19:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ADDRESS</name>
+                        <description>Device address</description>
+                        <bitRange>[6:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>ADDR_ENDP11</name>
+                <addressOffset>0x0000002c</addressOffset>
+                <description>Interrupt endpoint 11. Only valid for HOST mode.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>INTEP_PREAMBLE</name>
+                        <description>Interrupt EP requires preamble (is a low speed device on a full speed hub)</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTEP_DIR</name>
+                        <description>Direction of the interrupt endpoint. In=0, Out=1</description>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ENDPOINT</name>
+                        <description>Endpoint number of the interrupt endpoint</description>
+                        <bitRange>[19:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ADDRESS</name>
+                        <description>Device address</description>
+                        <bitRange>[6:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>ADDR_ENDP12</name>
+                <addressOffset>0x00000030</addressOffset>
+                <description>Interrupt endpoint 12. Only valid for HOST mode.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>INTEP_PREAMBLE</name>
+                        <description>Interrupt EP requires preamble (is a low speed device on a full speed hub)</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTEP_DIR</name>
+                        <description>Direction of the interrupt endpoint. In=0, Out=1</description>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ENDPOINT</name>
+                        <description>Endpoint number of the interrupt endpoint</description>
+                        <bitRange>[19:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ADDRESS</name>
+                        <description>Device address</description>
+                        <bitRange>[6:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>ADDR_ENDP13</name>
+                <addressOffset>0x00000034</addressOffset>
+                <description>Interrupt endpoint 13. Only valid for HOST mode.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>INTEP_PREAMBLE</name>
+                        <description>Interrupt EP requires preamble (is a low speed device on a full speed hub)</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTEP_DIR</name>
+                        <description>Direction of the interrupt endpoint. In=0, Out=1</description>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ENDPOINT</name>
+                        <description>Endpoint number of the interrupt endpoint</description>
+                        <bitRange>[19:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ADDRESS</name>
+                        <description>Device address</description>
+                        <bitRange>[6:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>ADDR_ENDP14</name>
+                <addressOffset>0x00000038</addressOffset>
+                <description>Interrupt endpoint 14. Only valid for HOST mode.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>INTEP_PREAMBLE</name>
+                        <description>Interrupt EP requires preamble (is a low speed device on a full speed hub)</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTEP_DIR</name>
+                        <description>Direction of the interrupt endpoint. In=0, Out=1</description>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ENDPOINT</name>
+                        <description>Endpoint number of the interrupt endpoint</description>
+                        <bitRange>[19:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ADDRESS</name>
+                        <description>Device address</description>
+                        <bitRange>[6:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>ADDR_ENDP15</name>
+                <addressOffset>0x0000003c</addressOffset>
+                <description>Interrupt endpoint 15. Only valid for HOST mode.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>INTEP_PREAMBLE</name>
+                        <description>Interrupt EP requires preamble (is a low speed device on a full speed hub)</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTEP_DIR</name>
+                        <description>Direction of the interrupt endpoint. In=0, Out=1</description>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ENDPOINT</name>
+                        <description>Endpoint number of the interrupt endpoint</description>
+                        <bitRange>[19:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ADDRESS</name>
+                        <description>Device address</description>
+                        <bitRange>[6:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>MAIN_CTRL</name>
+                <addressOffset>0x00000040</addressOffset>
+                <description>Main control register</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>SIM_TIMING</name>
+                        <description>Reduced timings for simulation</description>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>HOST_NDEVICE</name>
+                        <description>Device mode = 0, Host mode = 1</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CONTROLLER_EN</name>
+                        <description>Enable controller</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SOF_WR</name>
+                <addressOffset>0x00000044</addressOffset>
+                <description>Set the SOF (Start of Frame) frame number in the host controller. The SOF packet is sent every 1ms and the host will increment the frame number by 1 each time.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>COUNT</name>
+                        <bitRange>[10:0]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SOF_RD</name>
+                <addressOffset>0x00000048</addressOffset>
+                <description>Read the last SOF (Start of Frame) frame number seen. In device mode the last SOF received from the host. In host mode the last SOF sent by the host.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>COUNT</name>
+                        <bitRange>[10:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SIE_CTRL</name>
+                <addressOffset>0x0000004c</addressOffset>
+                <description>SIE control register</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>EP0_INT_STALL</name>
+                        <description>Device: Set bit in EP_STATUS_STALL_NAK when EP0 sends a STALL</description>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>EP0_DOUBLE_BUF</name>
+                        <description>Device: EP0 single buffered = 0, double buffered = 1</description>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>EP0_INT_1BUF</name>
+                        <description>Device: Set bit in BUFF_STATUS for every buffer completed on EP0</description>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>EP0_INT_2BUF</name>
+                        <description>Device: Set bit in BUFF_STATUS for every 2 buffers completed on EP0</description>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>EP0_INT_NAK</name>
+                        <description>Device: Set bit in EP_STATUS_STALL_NAK when EP0 sends a NAK</description>
+                        <bitRange>[27:27]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DIRECT_EN</name>
+                        <description>Direct bus drive enable</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DIRECT_DP</name>
+                        <description>Direct control of DP</description>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DIRECT_DM</name>
+                        <description>Direct control of DM</description>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>TRANSCEIVER_PD</name>
+                        <description>Power down bus transceiver</description>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>RPU_OPT</name>
+                        <description>Device: Pull-up strength (0=1K2, 1=2k3)</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PULLUP_EN</name>
+                        <description>Device: Enable pull up resistor</description>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PULLDOWN_EN</name>
+                        <description>Host: Enable pull down resistors</description>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>RESET_BUS</name>
+                        <description>Host: Reset bus</description>
+                        <bitRange>[13:13]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>RESUME</name>
+                        <description>Device: Remote wakeup. Device can initiate its own resume after suspend.</description>
+                        <bitRange>[12:12]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>VBUS_EN</name>
+                        <description>Host: Enable VBUS</description>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>KEEP_ALIVE_EN</name>
+                        <description>Host: Enable keep alive packet (for low speed bus)</description>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SOF_EN</name>
+                        <description>Host: Enable SOF generation (for full speed bus)</description>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SOF_SYNC</name>
+                        <description>Host: Delay packet(s) until after SOF</description>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PREAMBLE_EN</name>
+                        <description>Host: Preable enable for LS device on FS hub</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>STOP_TRANS</name>
+                        <description>Host: Stop transaction</description>
+                        <bitRange>[4:4]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>RECEIVE_DATA</name>
+                        <description>Host: Receive transaction (IN to host)</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SEND_DATA</name>
+                        <description>Host: Send transaction (OUT from host)</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SEND_SETUP</name>
+                        <description>Host: Send Setup packet</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>START_TRANS</name>
+                        <description>Host: Start transaction</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SIE_STATUS</name>
+                <addressOffset>0x00000050</addressOffset>
+                <description>SIE status register</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>DATA_SEQ_ERROR</name>
+                        <description>Data Sequence Error.
+
+                            The device can raise a sequence error in the following conditions:
+
+                            * A SETUP packet is received followed by a DATA1 packet (data phase should always be DATA0) * An OUT packet is received from the host but doesn&#39;t match the data pid in the buffer control register read from DPSRAM
+
+                            The host can raise a data sequence error in the following conditions:
+
+                            * An IN packet from the device has the wrong data PID</description>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>ACK_REC</name>
+                        <description>ACK received. Raised by both host and device.</description>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>STALL_REC</name>
+                        <description>Host: STALL received</description>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>NAK_REC</name>
+                        <description>Host: NAK received</description>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>RX_TIMEOUT</name>
+                        <description>RX timeout is raised by both the host and device if an ACK is not received in the maximum time specified by the USB spec.</description>
+                        <bitRange>[27:27]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>RX_OVERFLOW</name>
+                        <description>RX overflow is raised by the Serial RX engine if the incoming data is too fast.</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>BIT_STUFF_ERROR</name>
+                        <description>Bit Stuff Error. Raised by the Serial RX engine.</description>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>CRC_ERROR</name>
+                        <description>CRC Error. Raised by the Serial RX engine.</description>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>BUS_RESET</name>
+                        <description>Device: bus reset received</description>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>TRANS_COMPLETE</name>
+                        <description>Transaction complete.
+
+                            Raised by device if:
+
+                            * An IN or OUT packet is sent with the `LAST_BUFF` bit set in the buffer control register
+
+                            Raised by host if:
+
+                            * A setup packet is sent when no data in or data out transaction follows * An IN packet is received and the `LAST_BUFF` bit is set in the buffer control register * An IN packet is received with zero length * An OUT packet is sent and the `LAST_BUFF` bit is set</description>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>SETUP_REC</name>
+                        <description>Device: Setup packet received</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>CONNECTED</name>
+                        <description>Device: connected</description>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>RESUME</name>
+                        <description>Host: Device has initiated a remote resume. Device: host has initiated a resume.</description>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>VBUS_OVER_CURR</name>
+                        <description>VBUS over current detected</description>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SPEED</name>
+                        <description>Host: device speed. Disconnected = 00, LS = 01, FS = 10</description>
+                        <bitRange>[9:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SUSPENDED</name>
+                        <description>Bus in suspended state. Valid for device and host. Host and device will go into suspend if neither Keep Alive / SOF frames are enabled.</description>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>LINE_STATE</name>
+                        <description>USB bus line state</description>
+                        <bitRange>[3:2]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>VBUS_DETECTED</name>
+                        <description>Device: VBUS Detected</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INT_EP_CTRL</name>
+                <addressOffset>0x00000054</addressOffset>
+                <description>interrupt endpoint control register</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>INT_EP_ACTIVE</name>
+                        <description>Host: Enable interrupt endpoint 1 =&gt; 15</description>
+                        <bitRange>[15:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>BUFF_STATUS</name>
+                <addressOffset>0x00000058</addressOffset>
+                <description>Buffer status register. A bit set here indicates that a buffer has completed on the endpoint (if the buffer interrupt is enabled). It is possible for 2 buffers to be completed, so clearing the buffer status bit may instantly re set it on the next clock cycle.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>EP15_OUT</name>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP15_IN</name>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP14_OUT</name>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP14_IN</name>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP13_OUT</name>
+                        <bitRange>[27:27]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP13_IN</name>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP12_OUT</name>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP12_IN</name>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP11_OUT</name>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP11_IN</name>
+                        <bitRange>[22:22]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP10_OUT</name>
+                        <bitRange>[21:21]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP10_IN</name>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP9_OUT</name>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP9_IN</name>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP8_OUT</name>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP8_IN</name>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP7_OUT</name>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP7_IN</name>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP6_OUT</name>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP6_IN</name>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP5_OUT</name>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP5_IN</name>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP4_OUT</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP4_IN</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP3_OUT</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP3_IN</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP2_OUT</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP2_IN</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP1_OUT</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP1_IN</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP0_OUT</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP0_IN</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>BUFF_CPU_SHOULD_HANDLE</name>
+                <addressOffset>0x0000005c</addressOffset>
+                <description>Which of the double buffers should be handled. Only valid if using an interrupt per buffer (i.e. not per 2 buffers). Not valid for host interrupt endpoint polling because they are only single buffered.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>EP15_OUT</name>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>EP15_IN</name>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>EP14_OUT</name>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>EP14_IN</name>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>EP13_OUT</name>
+                        <bitRange>[27:27]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>EP13_IN</name>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>EP12_OUT</name>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>EP12_IN</name>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>EP11_OUT</name>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>EP11_IN</name>
+                        <bitRange>[22:22]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>EP10_OUT</name>
+                        <bitRange>[21:21]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>EP10_IN</name>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>EP9_OUT</name>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>EP9_IN</name>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>EP8_OUT</name>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>EP8_IN</name>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>EP7_OUT</name>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>EP7_IN</name>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>EP6_OUT</name>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>EP6_IN</name>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>EP5_OUT</name>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>EP5_IN</name>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>EP4_OUT</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>EP4_IN</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>EP3_OUT</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>EP3_IN</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>EP2_OUT</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>EP2_IN</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>EP1_OUT</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>EP1_IN</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>EP0_OUT</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>EP0_IN</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>EP_ABORT</name>
+                <addressOffset>0x00000060</addressOffset>
+                <description>Device only: Can be set to ignore the buffer control register for this endpoint in case you would like to revoke a buffer. A NAK will be sent for every access to the endpoint until this bit is cleared. A corresponding bit in `EP_ABORT_DONE` is set when it is safe to modify the buffer control register.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>EP15_OUT</name>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>EP15_IN</name>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>EP14_OUT</name>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>EP14_IN</name>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>EP13_OUT</name>
+                        <bitRange>[27:27]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>EP13_IN</name>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>EP12_OUT</name>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>EP12_IN</name>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>EP11_OUT</name>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>EP11_IN</name>
+                        <bitRange>[22:22]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>EP10_OUT</name>
+                        <bitRange>[21:21]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>EP10_IN</name>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>EP9_OUT</name>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>EP9_IN</name>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>EP8_OUT</name>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>EP8_IN</name>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>EP7_OUT</name>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>EP7_IN</name>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>EP6_OUT</name>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>EP6_IN</name>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>EP5_OUT</name>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>EP5_IN</name>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>EP4_OUT</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>EP4_IN</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>EP3_OUT</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>EP3_IN</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>EP2_OUT</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>EP2_IN</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>EP1_OUT</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>EP1_IN</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>EP0_OUT</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>EP0_IN</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>EP_ABORT_DONE</name>
+                <addressOffset>0x00000064</addressOffset>
+                <description>Device only: Used in conjunction with `EP_ABORT`. Set once an endpoint is idle so the programmer knows it is safe to modify the buffer control register.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>EP15_OUT</name>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP15_IN</name>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP14_OUT</name>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP14_IN</name>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP13_OUT</name>
+                        <bitRange>[27:27]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP13_IN</name>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP12_OUT</name>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP12_IN</name>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP11_OUT</name>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP11_IN</name>
+                        <bitRange>[22:22]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP10_OUT</name>
+                        <bitRange>[21:21]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP10_IN</name>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP9_OUT</name>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP9_IN</name>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP8_OUT</name>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP8_IN</name>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP7_OUT</name>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP7_IN</name>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP6_OUT</name>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP6_IN</name>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP5_OUT</name>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP5_IN</name>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP4_OUT</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP4_IN</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP3_OUT</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP3_IN</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP2_OUT</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP2_IN</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP1_OUT</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP1_IN</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP0_OUT</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP0_IN</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>EP_STALL_ARM</name>
+                <addressOffset>0x00000068</addressOffset>
+                <description>Device: this bit must be set in conjunction with the `STALL` bit in the buffer control register to send a STALL on EP0. The device controller clears these bits when a SETUP packet is received because the USB spec requires that a STALL condition is cleared when a SETUP packet is received.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>EP0_OUT</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>EP0_IN</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>NAK_POLL</name>
+                <addressOffset>0x0000006c</addressOffset>
+                <description>Used by the host controller. Sets the wait time in microseconds before trying again if the device replies with a NAK.</description>
+                <resetValue>0x00100010</resetValue>
+                <fields>
+                    <field>
+                        <name>DELAY_FS</name>
+                        <description>NAK polling interval for a full speed device</description>
+                        <bitRange>[25:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DELAY_LS</name>
+                        <description>NAK polling interval for a low speed device</description>
+                        <bitRange>[9:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>EP_STATUS_STALL_NAK</name>
+                <addressOffset>0x00000070</addressOffset>
+                <description>Device: bits are set when the `IRQ_ON_NAK` or `IRQ_ON_STALL` bits are set. For EP0 this comes from `SIE_CTRL`. For all other endpoints it comes from the endpoint control register.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>EP15_OUT</name>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP15_IN</name>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP14_OUT</name>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP14_IN</name>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP13_OUT</name>
+                        <bitRange>[27:27]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP13_IN</name>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP12_OUT</name>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP12_IN</name>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP11_OUT</name>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP11_IN</name>
+                        <bitRange>[22:22]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP10_OUT</name>
+                        <bitRange>[21:21]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP10_IN</name>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP9_OUT</name>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP9_IN</name>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP8_OUT</name>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP8_IN</name>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP7_OUT</name>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP7_IN</name>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP6_OUT</name>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP6_IN</name>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP5_OUT</name>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP5_IN</name>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP4_OUT</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP4_IN</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP3_OUT</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP3_IN</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP2_OUT</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP2_IN</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP1_OUT</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP1_IN</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP0_OUT</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP0_IN</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>USB_MUXING</name>
+                <addressOffset>0x00000074</addressOffset>
+                <description>Where to connect the USB controller. Should be to_phy by default.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>SOFTCON</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>TO_DIGITAL_PAD</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>TO_EXTPHY</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>TO_PHY</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>USB_PWR</name>
+                <addressOffset>0x00000078</addressOffset>
+                <description>Overrides for the power signals in the event that the VBUS signals are not hooked up to GPIO. Set the value of the override and then the override enable so switch over to the override value.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>OVERCURR_DETECT_EN</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>OVERCURR_DETECT</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>VBUS_DETECT_OVERRIDE_EN</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>VBUS_DETECT</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>VBUS_EN_OVERRIDE_EN</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>VBUS_EN</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>USBPHY_DIRECT</name>
+                <addressOffset>0x0000007c</addressOffset>
+                <description>Note that most functions are driven directly from usb_fsls controller.  This register allows more detailed control/status from the USB PHY. Useful for debug but not expected to be used in normal operation 
+                    Use in conjunction with usbphy_direct_override register</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>DM_OVV</name>
+                        <description>Status bit from USB PHY</description>
+                        <bitRange>[22:22]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>DP_OVV</name>
+                        <description>Status bit from USB PHY</description>
+                        <bitRange>[21:21]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>DM_OVCN</name>
+                        <description>Status bit from USB PHY</description>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>DP_OVCN</name>
+                        <description>Status bit from USB PHY</description>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>RX_DM</name>
+                        <description>Status bit from USB PHY 
+                            DPM pin state</description>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>RX_DP</name>
+                        <description>Status bit from USB PHY 
+                            DPP pin state</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>RX_DD</name>
+                        <description>Status bit from USB PHY 
+                            RX Diff data</description>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>TX_DIFFMODE</name>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>TX_FSSLEW</name>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>TX_PD</name>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>RX_PD</name>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>TX_DM</name>
+                        <description>Value to drive to USB PHY when override enable is set (which will override the default value or value driven from USB controller 
+                            TX_SEMODE=0, Ignored 
+                            TX_SEMODE=1, Drives DPM only. TX_DM_OE=1 to enable drive. DPM=TX_DM</description>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>TX_DP</name>
+                        <description>Value to drive to USB PHY when override enable is set (which will override the default value or value driven from USB controller 
+                            TX_SEMODE=0, Drives DPP/DPM diff pair. TX_DP_OE=1 to enable drive. DPP=TX_DP, DPM=~TX_DP 
+                            TX_SEMODE=1, Drives DPP only. TX_DP_OE=1 to enable drive. DPP=TX_DP</description>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>TX_DM_OE</name>
+                        <description>Value to drive to USB PHY when override enable is set (which will override the default value or value driven from USB controller 
+                            TX_SEMODE=0, Ignored. 
+                            TX_SEMODE=1, OE for DPM only. 0 - DPM in Hi-Z state; 1 - DPM driving</description>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>TX_DP_OE</name>
+                        <description>Value to drive to USB PHY when override enable is set (which will override the default value or value driven from USB controller 
+                            TX_SEMODE=0, OE for DPP/DPM diff pair. 0 - DPP/DPM in Hi-Z state; 1 - DPP/DPM driving 
+                            TX_SEMODE=1, OE for DPP only. 0 - DPP in Hi-Z state; 1 - DPP driving</description>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DM_PULLDN_EN</name>
+                        <description>Value to drive to USB PHY when override enable is set (which will override the default value or value driven from USB controller 
+                            1 - Enable Rpd on DPM</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DM_PULLUP_EN</name>
+                        <description>Value to drive to USB PHY when override enable is set (which will override the default value or value driven from USB controller 
+                            1 - Enable Rpu on DPM</description>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DM_PULLUP_HISEL</name>
+                        <description>when dm_pullup_en is set high, this enables second resistor. 0 - Pull = Rpu2; 1 - Pull = Rpu1 + Rpu2</description>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DP_PULLDN_EN</name>
+                        <description>Value to drive to USB PHY when override enable is set (which will override the default value or value driven from USB controller 
+                            1 - Enable Rpd on DPP</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DP_PULLUP_EN</name>
+                        <description>Value to drive to USB PHY when override enable is set (which will override the default value or value driven from USB controller</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DP_PULLUP_HISEL</name>
+                        <description>when dp_pullup_en is set high, this enables second resistor. 0 - Pull = Rpu2; 1 - Pull = Rpu1 + Rpu2</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>USBPHY_DIRECT_OVERRIDE</name>
+                <addressOffset>0x00000080</addressOffset>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>TX_DIFFMODE_OVERRIDE_EN</name>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DM_PULLUP_OVERRIDE_EN</name>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>TX_FSSLEW_OVERRIDE_EN</name>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>TX_PD_OVERRIDE_EN</name>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>RX_PD_OVERRIDE_EN</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>TX_DM_OVERRIDE_EN</name>
+                        <description>Override default value or value driven from USB Controller to PHY</description>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>TX_DP_OVERRIDE_EN</name>
+                        <description>Override default value or value driven from USB Controller to PHY</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>TX_DM_OE_OVERRIDE_EN</name>
+                        <description>Override default value or value driven from USB Controller to PHY</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>TX_DP_OE_OVERRIDE_EN</name>
+                        <description>Override default value or value driven from USB Controller to PHY</description>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DM_PULLDN_EN_OVERRIDE_EN</name>
+                        <description>Override default value or value driven from USB Controller to PHY</description>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DP_PULLDN_EN_OVERRIDE_EN</name>
+                        <description>Override default value or value driven from USB Controller to PHY</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DP_PULLUP_EN_OVERRIDE_EN</name>
+                        <description>Override default value or value driven from USB Controller to PHY</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DM_PULLUP_HISEL_OVERRIDE_EN</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DP_PULLUP_HISEL_OVERRIDE_EN</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>USBPHY_TRIM</name>
+                <addressOffset>0x00000084</addressOffset>
+                <description>Note that most functions are driven directly from usb_fsls controller.  This register allows more detailed control/status from the USB PHY. Useful for debug but not expected to be used in normal operation</description>
+                <resetValue>0x00001f1f</resetValue>
+                <fields>
+                    <field>
+                        <name>DM_PULLDN_TRIM</name>
+                        <description>Value to drive to USB PHY 
+                            DM pulldown resistor trim control 
+                            Experimental data suggests that the reset value will work, but this register allows adjustment if required</description>
+                        <bitRange>[12:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DP_PULLDN_TRIM</name>
+                        <description>Value to drive to USB PHY 
+                            DP pulldown resistor trim control 
+                            Experimental data suggests that the reset value will work, but this register allows adjustment if required</description>
+                        <bitRange>[4:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INTR</name>
+                <addressOffset>0x0000008c</addressOffset>
+                <description>Raw Interrupts</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>EP_STALL_NAK</name>
+                        <description>Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by clearing all bits in EP_STATUS_STALL_NAK.</description>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>ABORT_DONE</name>
+                        <description>Raised when any bit in ABORT_DONE is set. Clear by clearing all bits in ABORT_DONE.</description>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>DEV_SOF</name>
+                        <description>Set every time the device receives a SOF (Start of Frame) packet. Cleared by reading SOF_RD</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SETUP_REQ</name>
+                        <description>Device. Source: SIE_STATUS.SETUP_REC</description>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>DEV_RESUME_FROM_HOST</name>
+                        <description>Set when the device receives a resume from the host. Cleared by writing to SIE_STATUS.RESUME_REMOTE</description>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>DEV_SUSPEND</name>
+                        <description>Set when the device suspend state changes. Cleared by writing to SIE_STATUS.SUSPENDED</description>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>DEV_CONN_DIS</name>
+                        <description>Set when the device connection state changes. Cleared by writing to SIE_STATUS.CONNECTED</description>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>BUS_RESET</name>
+                        <description>Source: SIE_STATUS.BUS_RESET</description>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>VBUS_DETECT</name>
+                        <description>Source: SIE_STATUS.VBUS_DETECT</description>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>STALL</name>
+                        <description>Source: SIE_STATUS.STALL_REC</description>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>ERROR_CRC</name>
+                        <description>Source: SIE_STATUS.CRC_ERROR</description>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>ERROR_BIT_STUFF</name>
+                        <description>Source: SIE_STATUS.BIT_STUFF_ERROR</description>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>ERROR_RX_OVERFLOW</name>
+                        <description>Source: SIE_STATUS.RX_OVERFLOW</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>ERROR_RX_TIMEOUT</name>
+                        <description>Source: SIE_STATUS.RX_TIMEOUT</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>ERROR_DATA_SEQ</name>
+                        <description>Source: SIE_STATUS.DATA_SEQ_ERROR</description>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>BUFF_STATUS</name>
+                        <description>Raised when any bit in BUFF_STATUS is set. Clear by clearing all bits in BUFF_STATUS.</description>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>TRANS_COMPLETE</name>
+                        <description>Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by writing to this bit.</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>HOST_SOF</name>
+                        <description>Host: raised every time the host sends a SOF (Start of Frame). Cleared by reading SOF_RD</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>HOST_RESUME</name>
+                        <description>Host: raised when a device wakes up the host. Cleared by writing to SIE_STATUS.RESUME_REMOTE</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>HOST_CONN_DIS</name>
+                        <description>Host: raised when a device is connected or disconnected (i.e. when SIE_STATUS.SPEED changes). Cleared by writing to SIE_STATUS.SPEED</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INTE</name>
+                <addressOffset>0x00000090</addressOffset>
+                <description>Interrupt Enable</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>EP_STALL_NAK</name>
+                        <description>Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by clearing all bits in EP_STATUS_STALL_NAK.</description>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ABORT_DONE</name>
+                        <description>Raised when any bit in ABORT_DONE is set. Clear by clearing all bits in ABORT_DONE.</description>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DEV_SOF</name>
+                        <description>Set every time the device receives a SOF (Start of Frame) packet. Cleared by reading SOF_RD</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SETUP_REQ</name>
+                        <description>Device. Source: SIE_STATUS.SETUP_REC</description>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DEV_RESUME_FROM_HOST</name>
+                        <description>Set when the device receives a resume from the host. Cleared by writing to SIE_STATUS.RESUME_REMOTE</description>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DEV_SUSPEND</name>
+                        <description>Set when the device suspend state changes. Cleared by writing to SIE_STATUS.SUSPENDED</description>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DEV_CONN_DIS</name>
+                        <description>Set when the device connection state changes. Cleared by writing to SIE_STATUS.CONNECTED</description>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>BUS_RESET</name>
+                        <description>Source: SIE_STATUS.BUS_RESET</description>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>VBUS_DETECT</name>
+                        <description>Source: SIE_STATUS.VBUS_DETECT</description>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>STALL</name>
+                        <description>Source: SIE_STATUS.STALL_REC</description>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ERROR_CRC</name>
+                        <description>Source: SIE_STATUS.CRC_ERROR</description>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ERROR_BIT_STUFF</name>
+                        <description>Source: SIE_STATUS.BIT_STUFF_ERROR</description>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ERROR_RX_OVERFLOW</name>
+                        <description>Source: SIE_STATUS.RX_OVERFLOW</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ERROR_RX_TIMEOUT</name>
+                        <description>Source: SIE_STATUS.RX_TIMEOUT</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ERROR_DATA_SEQ</name>
+                        <description>Source: SIE_STATUS.DATA_SEQ_ERROR</description>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>BUFF_STATUS</name>
+                        <description>Raised when any bit in BUFF_STATUS is set. Clear by clearing all bits in BUFF_STATUS.</description>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>TRANS_COMPLETE</name>
+                        <description>Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by writing to this bit.</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>HOST_SOF</name>
+                        <description>Host: raised every time the host sends a SOF (Start of Frame). Cleared by reading SOF_RD</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>HOST_RESUME</name>
+                        <description>Host: raised when a device wakes up the host. Cleared by writing to SIE_STATUS.RESUME_REMOTE</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>HOST_CONN_DIS</name>
+                        <description>Host: raised when a device is connected or disconnected (i.e. when SIE_STATUS.SPEED changes). Cleared by writing to SIE_STATUS.SPEED</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INTF</name>
+                <addressOffset>0x00000094</addressOffset>
+                <description>Interrupt Force</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>EP_STALL_NAK</name>
+                        <description>Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by clearing all bits in EP_STATUS_STALL_NAK.</description>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ABORT_DONE</name>
+                        <description>Raised when any bit in ABORT_DONE is set. Clear by clearing all bits in ABORT_DONE.</description>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DEV_SOF</name>
+                        <description>Set every time the device receives a SOF (Start of Frame) packet. Cleared by reading SOF_RD</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SETUP_REQ</name>
+                        <description>Device. Source: SIE_STATUS.SETUP_REC</description>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DEV_RESUME_FROM_HOST</name>
+                        <description>Set when the device receives a resume from the host. Cleared by writing to SIE_STATUS.RESUME_REMOTE</description>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DEV_SUSPEND</name>
+                        <description>Set when the device suspend state changes. Cleared by writing to SIE_STATUS.SUSPENDED</description>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DEV_CONN_DIS</name>
+                        <description>Set when the device connection state changes. Cleared by writing to SIE_STATUS.CONNECTED</description>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>BUS_RESET</name>
+                        <description>Source: SIE_STATUS.BUS_RESET</description>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>VBUS_DETECT</name>
+                        <description>Source: SIE_STATUS.VBUS_DETECT</description>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>STALL</name>
+                        <description>Source: SIE_STATUS.STALL_REC</description>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ERROR_CRC</name>
+                        <description>Source: SIE_STATUS.CRC_ERROR</description>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ERROR_BIT_STUFF</name>
+                        <description>Source: SIE_STATUS.BIT_STUFF_ERROR</description>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ERROR_RX_OVERFLOW</name>
+                        <description>Source: SIE_STATUS.RX_OVERFLOW</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ERROR_RX_TIMEOUT</name>
+                        <description>Source: SIE_STATUS.RX_TIMEOUT</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ERROR_DATA_SEQ</name>
+                        <description>Source: SIE_STATUS.DATA_SEQ_ERROR</description>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>BUFF_STATUS</name>
+                        <description>Raised when any bit in BUFF_STATUS is set. Clear by clearing all bits in BUFF_STATUS.</description>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>TRANS_COMPLETE</name>
+                        <description>Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by writing to this bit.</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>HOST_SOF</name>
+                        <description>Host: raised every time the host sends a SOF (Start of Frame). Cleared by reading SOF_RD</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>HOST_RESUME</name>
+                        <description>Host: raised when a device wakes up the host. Cleared by writing to SIE_STATUS.RESUME_REMOTE</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>HOST_CONN_DIS</name>
+                        <description>Host: raised when a device is connected or disconnected (i.e. when SIE_STATUS.SPEED changes). Cleared by writing to SIE_STATUS.SPEED</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INTS</name>
+                <addressOffset>0x00000098</addressOffset>
+                <description>Interrupt status after masking &amp; forcing</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>EP_STALL_NAK</name>
+                        <description>Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by clearing all bits in EP_STATUS_STALL_NAK.</description>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>ABORT_DONE</name>
+                        <description>Raised when any bit in ABORT_DONE is set. Clear by clearing all bits in ABORT_DONE.</description>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>DEV_SOF</name>
+                        <description>Set every time the device receives a SOF (Start of Frame) packet. Cleared by reading SOF_RD</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SETUP_REQ</name>
+                        <description>Device. Source: SIE_STATUS.SETUP_REC</description>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>DEV_RESUME_FROM_HOST</name>
+                        <description>Set when the device receives a resume from the host. Cleared by writing to SIE_STATUS.RESUME_REMOTE</description>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>DEV_SUSPEND</name>
+                        <description>Set when the device suspend state changes. Cleared by writing to SIE_STATUS.SUSPENDED</description>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>DEV_CONN_DIS</name>
+                        <description>Set when the device connection state changes. Cleared by writing to SIE_STATUS.CONNECTED</description>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>BUS_RESET</name>
+                        <description>Source: SIE_STATUS.BUS_RESET</description>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>VBUS_DETECT</name>
+                        <description>Source: SIE_STATUS.VBUS_DETECT</description>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>STALL</name>
+                        <description>Source: SIE_STATUS.STALL_REC</description>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>ERROR_CRC</name>
+                        <description>Source: SIE_STATUS.CRC_ERROR</description>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>ERROR_BIT_STUFF</name>
+                        <description>Source: SIE_STATUS.BIT_STUFF_ERROR</description>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>ERROR_RX_OVERFLOW</name>
+                        <description>Source: SIE_STATUS.RX_OVERFLOW</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>ERROR_RX_TIMEOUT</name>
+                        <description>Source: SIE_STATUS.RX_TIMEOUT</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>ERROR_DATA_SEQ</name>
+                        <description>Source: SIE_STATUS.DATA_SEQ_ERROR</description>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>BUFF_STATUS</name>
+                        <description>Raised when any bit in BUFF_STATUS is set. Clear by clearing all bits in BUFF_STATUS.</description>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>TRANS_COMPLETE</name>
+                        <description>Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by writing to this bit.</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>HOST_SOF</name>
+                        <description>Host: raised every time the host sends a SOF (Start of Frame). Cleared by reading SOF_RD</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>HOST_RESUME</name>
+                        <description>Host: raised when a device wakes up the host. Cleared by writing to SIE_STATUS.RESUME_REMOTE</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>HOST_CONN_DIS</name>
+                        <description>Host: raised when a device is connected or disconnected (i.e. when SIE_STATUS.SPEED changes). Cleared by writing to SIE_STATUS.SPEED</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+        </registers>
+    </peripheral>
+    <peripheral>
+        <name>USB_DPRAM</name>
+        <description>DPRAM layout for USB device.</description>
+        <baseAddress>0x50100000</baseAddress>
+        <addressBlock>
+            <offset>0</offset>
+            <size>256</size>
+            <usage>registers</usage>
+        </addressBlock>
+        <registers>
+            <register>
+                <name>SETUP_PACKET_LOW</name>
+                <addressOffset>0x00000000</addressOffset>
+                <description>Bytes 0-3 of the SETUP packet from the host.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>WVALUE</name>
+                        <bitRange>[31:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>BREQUEST</name>
+                        <bitRange>[15:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>BMREQUESTTYPE</name>
+                        <bitRange>[7:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SETUP_PACKET_HIGH</name>
+                <addressOffset>0x00000004</addressOffset>
+                <description>Bytes 4-7 of the setup packet from the host.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>WLENGTH</name>
+                        <bitRange>[31:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>WINDEX</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>EP1_IN_CONTROL</name>
+                <addressOffset>0x00000008</addressOffset>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>ENABLE</name>
+                        <description>Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.</description>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DOUBLE_BUFFERED</name>
+                        <description>This endpoint is double buffered.</description>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_PER_BUFF</name>
+                        <description>Trigger an interrupt each time a buffer is done.</description>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_PER_DOUBLE_BUFF</name>
+                        <description>Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.</description>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ENDPOINT_TYPE</name>
+                        <bitRange>[27:26]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>Control</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Isochronous</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Bulk</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Interrupt</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_ON_STALL</name>
+                        <description>Trigger an interrupt if a STALL is sent. Intended for debug only.</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_ON_NAK</name>
+                        <description>Trigger an interrupt if a NAK is sent. Intended for debug only.</description>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>BUFFER_ADDRESS</name>
+                        <description>64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.</description>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>EP1_OUT_CONTROL</name>
+                <addressOffset>0x0000000c</addressOffset>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>ENABLE</name>
+                        <description>Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.</description>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DOUBLE_BUFFERED</name>
+                        <description>This endpoint is double buffered.</description>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_PER_BUFF</name>
+                        <description>Trigger an interrupt each time a buffer is done.</description>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_PER_DOUBLE_BUFF</name>
+                        <description>Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.</description>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ENDPOINT_TYPE</name>
+                        <bitRange>[27:26]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>Control</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Isochronous</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Bulk</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Interrupt</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_ON_STALL</name>
+                        <description>Trigger an interrupt if a STALL is sent. Intended for debug only.</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_ON_NAK</name>
+                        <description>Trigger an interrupt if a NAK is sent. Intended for debug only.</description>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>BUFFER_ADDRESS</name>
+                        <description>64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.</description>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>EP2_IN_CONTROL</name>
+                <addressOffset>0x00000010</addressOffset>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>ENABLE</name>
+                        <description>Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.</description>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DOUBLE_BUFFERED</name>
+                        <description>This endpoint is double buffered.</description>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_PER_BUFF</name>
+                        <description>Trigger an interrupt each time a buffer is done.</description>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_PER_DOUBLE_BUFF</name>
+                        <description>Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.</description>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ENDPOINT_TYPE</name>
+                        <bitRange>[27:26]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>Control</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Isochronous</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Bulk</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Interrupt</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_ON_STALL</name>
+                        <description>Trigger an interrupt if a STALL is sent. Intended for debug only.</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_ON_NAK</name>
+                        <description>Trigger an interrupt if a NAK is sent. Intended for debug only.</description>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>BUFFER_ADDRESS</name>
+                        <description>64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.</description>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>EP2_OUT_CONTROL</name>
+                <addressOffset>0x00000014</addressOffset>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>ENABLE</name>
+                        <description>Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.</description>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DOUBLE_BUFFERED</name>
+                        <description>This endpoint is double buffered.</description>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_PER_BUFF</name>
+                        <description>Trigger an interrupt each time a buffer is done.</description>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_PER_DOUBLE_BUFF</name>
+                        <description>Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.</description>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ENDPOINT_TYPE</name>
+                        <bitRange>[27:26]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>Control</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Isochronous</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Bulk</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Interrupt</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_ON_STALL</name>
+                        <description>Trigger an interrupt if a STALL is sent. Intended for debug only.</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_ON_NAK</name>
+                        <description>Trigger an interrupt if a NAK is sent. Intended for debug only.</description>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>BUFFER_ADDRESS</name>
+                        <description>64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.</description>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>EP3_IN_CONTROL</name>
+                <addressOffset>0x00000018</addressOffset>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>ENABLE</name>
+                        <description>Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.</description>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DOUBLE_BUFFERED</name>
+                        <description>This endpoint is double buffered.</description>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_PER_BUFF</name>
+                        <description>Trigger an interrupt each time a buffer is done.</description>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_PER_DOUBLE_BUFF</name>
+                        <description>Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.</description>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ENDPOINT_TYPE</name>
+                        <bitRange>[27:26]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>Control</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Isochronous</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Bulk</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Interrupt</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_ON_STALL</name>
+                        <description>Trigger an interrupt if a STALL is sent. Intended for debug only.</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_ON_NAK</name>
+                        <description>Trigger an interrupt if a NAK is sent. Intended for debug only.</description>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>BUFFER_ADDRESS</name>
+                        <description>64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.</description>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>EP3_OUT_CONTROL</name>
+                <addressOffset>0x0000001c</addressOffset>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>ENABLE</name>
+                        <description>Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.</description>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DOUBLE_BUFFERED</name>
+                        <description>This endpoint is double buffered.</description>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_PER_BUFF</name>
+                        <description>Trigger an interrupt each time a buffer is done.</description>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_PER_DOUBLE_BUFF</name>
+                        <description>Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.</description>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ENDPOINT_TYPE</name>
+                        <bitRange>[27:26]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>Control</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Isochronous</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Bulk</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Interrupt</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_ON_STALL</name>
+                        <description>Trigger an interrupt if a STALL is sent. Intended for debug only.</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_ON_NAK</name>
+                        <description>Trigger an interrupt if a NAK is sent. Intended for debug only.</description>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>BUFFER_ADDRESS</name>
+                        <description>64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.</description>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>EP4_IN_CONTROL</name>
+                <addressOffset>0x00000020</addressOffset>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>ENABLE</name>
+                        <description>Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.</description>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DOUBLE_BUFFERED</name>
+                        <description>This endpoint is double buffered.</description>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_PER_BUFF</name>
+                        <description>Trigger an interrupt each time a buffer is done.</description>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_PER_DOUBLE_BUFF</name>
+                        <description>Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.</description>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ENDPOINT_TYPE</name>
+                        <bitRange>[27:26]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>Control</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Isochronous</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Bulk</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Interrupt</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_ON_STALL</name>
+                        <description>Trigger an interrupt if a STALL is sent. Intended for debug only.</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_ON_NAK</name>
+                        <description>Trigger an interrupt if a NAK is sent. Intended for debug only.</description>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>BUFFER_ADDRESS</name>
+                        <description>64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.</description>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>EP4_OUT_CONTROL</name>
+                <addressOffset>0x00000024</addressOffset>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>ENABLE</name>
+                        <description>Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.</description>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DOUBLE_BUFFERED</name>
+                        <description>This endpoint is double buffered.</description>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_PER_BUFF</name>
+                        <description>Trigger an interrupt each time a buffer is done.</description>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_PER_DOUBLE_BUFF</name>
+                        <description>Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.</description>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ENDPOINT_TYPE</name>
+                        <bitRange>[27:26]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>Control</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Isochronous</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Bulk</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Interrupt</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_ON_STALL</name>
+                        <description>Trigger an interrupt if a STALL is sent. Intended for debug only.</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_ON_NAK</name>
+                        <description>Trigger an interrupt if a NAK is sent. Intended for debug only.</description>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>BUFFER_ADDRESS</name>
+                        <description>64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.</description>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>EP5_IN_CONTROL</name>
+                <addressOffset>0x00000028</addressOffset>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>ENABLE</name>
+                        <description>Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.</description>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DOUBLE_BUFFERED</name>
+                        <description>This endpoint is double buffered.</description>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_PER_BUFF</name>
+                        <description>Trigger an interrupt each time a buffer is done.</description>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_PER_DOUBLE_BUFF</name>
+                        <description>Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.</description>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ENDPOINT_TYPE</name>
+                        <bitRange>[27:26]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>Control</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Isochronous</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Bulk</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Interrupt</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_ON_STALL</name>
+                        <description>Trigger an interrupt if a STALL is sent. Intended for debug only.</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_ON_NAK</name>
+                        <description>Trigger an interrupt if a NAK is sent. Intended for debug only.</description>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>BUFFER_ADDRESS</name>
+                        <description>64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.</description>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>EP5_OUT_CONTROL</name>
+                <addressOffset>0x0000002c</addressOffset>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>ENABLE</name>
+                        <description>Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.</description>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DOUBLE_BUFFERED</name>
+                        <description>This endpoint is double buffered.</description>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_PER_BUFF</name>
+                        <description>Trigger an interrupt each time a buffer is done.</description>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_PER_DOUBLE_BUFF</name>
+                        <description>Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.</description>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ENDPOINT_TYPE</name>
+                        <bitRange>[27:26]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>Control</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Isochronous</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Bulk</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Interrupt</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_ON_STALL</name>
+                        <description>Trigger an interrupt if a STALL is sent. Intended for debug only.</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_ON_NAK</name>
+                        <description>Trigger an interrupt if a NAK is sent. Intended for debug only.</description>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>BUFFER_ADDRESS</name>
+                        <description>64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.</description>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>EP6_IN_CONTROL</name>
+                <addressOffset>0x00000030</addressOffset>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>ENABLE</name>
+                        <description>Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.</description>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DOUBLE_BUFFERED</name>
+                        <description>This endpoint is double buffered.</description>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_PER_BUFF</name>
+                        <description>Trigger an interrupt each time a buffer is done.</description>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_PER_DOUBLE_BUFF</name>
+                        <description>Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.</description>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ENDPOINT_TYPE</name>
+                        <bitRange>[27:26]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>Control</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Isochronous</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Bulk</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Interrupt</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_ON_STALL</name>
+                        <description>Trigger an interrupt if a STALL is sent. Intended for debug only.</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_ON_NAK</name>
+                        <description>Trigger an interrupt if a NAK is sent. Intended for debug only.</description>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>BUFFER_ADDRESS</name>
+                        <description>64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.</description>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>EP6_OUT_CONTROL</name>
+                <addressOffset>0x00000034</addressOffset>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>ENABLE</name>
+                        <description>Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.</description>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DOUBLE_BUFFERED</name>
+                        <description>This endpoint is double buffered.</description>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_PER_BUFF</name>
+                        <description>Trigger an interrupt each time a buffer is done.</description>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_PER_DOUBLE_BUFF</name>
+                        <description>Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.</description>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ENDPOINT_TYPE</name>
+                        <bitRange>[27:26]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>Control</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Isochronous</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Bulk</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Interrupt</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_ON_STALL</name>
+                        <description>Trigger an interrupt if a STALL is sent. Intended for debug only.</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_ON_NAK</name>
+                        <description>Trigger an interrupt if a NAK is sent. Intended for debug only.</description>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>BUFFER_ADDRESS</name>
+                        <description>64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.</description>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>EP7_IN_CONTROL</name>
+                <addressOffset>0x00000038</addressOffset>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>ENABLE</name>
+                        <description>Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.</description>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DOUBLE_BUFFERED</name>
+                        <description>This endpoint is double buffered.</description>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_PER_BUFF</name>
+                        <description>Trigger an interrupt each time a buffer is done.</description>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_PER_DOUBLE_BUFF</name>
+                        <description>Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.</description>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ENDPOINT_TYPE</name>
+                        <bitRange>[27:26]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>Control</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Isochronous</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Bulk</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Interrupt</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_ON_STALL</name>
+                        <description>Trigger an interrupt if a STALL is sent. Intended for debug only.</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_ON_NAK</name>
+                        <description>Trigger an interrupt if a NAK is sent. Intended for debug only.</description>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>BUFFER_ADDRESS</name>
+                        <description>64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.</description>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>EP7_OUT_CONTROL</name>
+                <addressOffset>0x0000003c</addressOffset>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>ENABLE</name>
+                        <description>Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.</description>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DOUBLE_BUFFERED</name>
+                        <description>This endpoint is double buffered.</description>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_PER_BUFF</name>
+                        <description>Trigger an interrupt each time a buffer is done.</description>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_PER_DOUBLE_BUFF</name>
+                        <description>Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.</description>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ENDPOINT_TYPE</name>
+                        <bitRange>[27:26]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>Control</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Isochronous</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Bulk</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Interrupt</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_ON_STALL</name>
+                        <description>Trigger an interrupt if a STALL is sent. Intended for debug only.</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_ON_NAK</name>
+                        <description>Trigger an interrupt if a NAK is sent. Intended for debug only.</description>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>BUFFER_ADDRESS</name>
+                        <description>64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.</description>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>EP8_IN_CONTROL</name>
+                <addressOffset>0x00000040</addressOffset>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>ENABLE</name>
+                        <description>Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.</description>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DOUBLE_BUFFERED</name>
+                        <description>This endpoint is double buffered.</description>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_PER_BUFF</name>
+                        <description>Trigger an interrupt each time a buffer is done.</description>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_PER_DOUBLE_BUFF</name>
+                        <description>Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.</description>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ENDPOINT_TYPE</name>
+                        <bitRange>[27:26]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>Control</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Isochronous</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Bulk</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Interrupt</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_ON_STALL</name>
+                        <description>Trigger an interrupt if a STALL is sent. Intended for debug only.</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_ON_NAK</name>
+                        <description>Trigger an interrupt if a NAK is sent. Intended for debug only.</description>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>BUFFER_ADDRESS</name>
+                        <description>64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.</description>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>EP8_OUT_CONTROL</name>
+                <addressOffset>0x00000044</addressOffset>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>ENABLE</name>
+                        <description>Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.</description>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DOUBLE_BUFFERED</name>
+                        <description>This endpoint is double buffered.</description>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_PER_BUFF</name>
+                        <description>Trigger an interrupt each time a buffer is done.</description>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_PER_DOUBLE_BUFF</name>
+                        <description>Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.</description>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ENDPOINT_TYPE</name>
+                        <bitRange>[27:26]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>Control</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Isochronous</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Bulk</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Interrupt</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_ON_STALL</name>
+                        <description>Trigger an interrupt if a STALL is sent. Intended for debug only.</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_ON_NAK</name>
+                        <description>Trigger an interrupt if a NAK is sent. Intended for debug only.</description>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>BUFFER_ADDRESS</name>
+                        <description>64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.</description>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>EP9_IN_CONTROL</name>
+                <addressOffset>0x00000048</addressOffset>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>ENABLE</name>
+                        <description>Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.</description>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DOUBLE_BUFFERED</name>
+                        <description>This endpoint is double buffered.</description>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_PER_BUFF</name>
+                        <description>Trigger an interrupt each time a buffer is done.</description>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_PER_DOUBLE_BUFF</name>
+                        <description>Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.</description>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ENDPOINT_TYPE</name>
+                        <bitRange>[27:26]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>Control</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Isochronous</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Bulk</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Interrupt</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_ON_STALL</name>
+                        <description>Trigger an interrupt if a STALL is sent. Intended for debug only.</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_ON_NAK</name>
+                        <description>Trigger an interrupt if a NAK is sent. Intended for debug only.</description>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>BUFFER_ADDRESS</name>
+                        <description>64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.</description>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>EP9_OUT_CONTROL</name>
+                <addressOffset>0x0000004c</addressOffset>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>ENABLE</name>
+                        <description>Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.</description>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DOUBLE_BUFFERED</name>
+                        <description>This endpoint is double buffered.</description>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_PER_BUFF</name>
+                        <description>Trigger an interrupt each time a buffer is done.</description>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_PER_DOUBLE_BUFF</name>
+                        <description>Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.</description>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ENDPOINT_TYPE</name>
+                        <bitRange>[27:26]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>Control</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Isochronous</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Bulk</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Interrupt</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_ON_STALL</name>
+                        <description>Trigger an interrupt if a STALL is sent. Intended for debug only.</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_ON_NAK</name>
+                        <description>Trigger an interrupt if a NAK is sent. Intended for debug only.</description>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>BUFFER_ADDRESS</name>
+                        <description>64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.</description>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>EP10_IN_CONTROL</name>
+                <addressOffset>0x00000050</addressOffset>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>ENABLE</name>
+                        <description>Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.</description>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DOUBLE_BUFFERED</name>
+                        <description>This endpoint is double buffered.</description>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_PER_BUFF</name>
+                        <description>Trigger an interrupt each time a buffer is done.</description>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_PER_DOUBLE_BUFF</name>
+                        <description>Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.</description>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ENDPOINT_TYPE</name>
+                        <bitRange>[27:26]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>Control</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Isochronous</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Bulk</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Interrupt</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_ON_STALL</name>
+                        <description>Trigger an interrupt if a STALL is sent. Intended for debug only.</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_ON_NAK</name>
+                        <description>Trigger an interrupt if a NAK is sent. Intended for debug only.</description>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>BUFFER_ADDRESS</name>
+                        <description>64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.</description>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>EP10_OUT_CONTROL</name>
+                <addressOffset>0x00000054</addressOffset>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>ENABLE</name>
+                        <description>Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.</description>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DOUBLE_BUFFERED</name>
+                        <description>This endpoint is double buffered.</description>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_PER_BUFF</name>
+                        <description>Trigger an interrupt each time a buffer is done.</description>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_PER_DOUBLE_BUFF</name>
+                        <description>Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.</description>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ENDPOINT_TYPE</name>
+                        <bitRange>[27:26]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>Control</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Isochronous</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Bulk</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Interrupt</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_ON_STALL</name>
+                        <description>Trigger an interrupt if a STALL is sent. Intended for debug only.</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_ON_NAK</name>
+                        <description>Trigger an interrupt if a NAK is sent. Intended for debug only.</description>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>BUFFER_ADDRESS</name>
+                        <description>64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.</description>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>EP11_IN_CONTROL</name>
+                <addressOffset>0x00000058</addressOffset>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>ENABLE</name>
+                        <description>Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.</description>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DOUBLE_BUFFERED</name>
+                        <description>This endpoint is double buffered.</description>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_PER_BUFF</name>
+                        <description>Trigger an interrupt each time a buffer is done.</description>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_PER_DOUBLE_BUFF</name>
+                        <description>Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.</description>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ENDPOINT_TYPE</name>
+                        <bitRange>[27:26]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>Control</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Isochronous</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Bulk</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Interrupt</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_ON_STALL</name>
+                        <description>Trigger an interrupt if a STALL is sent. Intended for debug only.</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_ON_NAK</name>
+                        <description>Trigger an interrupt if a NAK is sent. Intended for debug only.</description>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>BUFFER_ADDRESS</name>
+                        <description>64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.</description>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>EP11_OUT_CONTROL</name>
+                <addressOffset>0x0000005c</addressOffset>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>ENABLE</name>
+                        <description>Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.</description>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DOUBLE_BUFFERED</name>
+                        <description>This endpoint is double buffered.</description>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_PER_BUFF</name>
+                        <description>Trigger an interrupt each time a buffer is done.</description>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_PER_DOUBLE_BUFF</name>
+                        <description>Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.</description>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ENDPOINT_TYPE</name>
+                        <bitRange>[27:26]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>Control</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Isochronous</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Bulk</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Interrupt</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_ON_STALL</name>
+                        <description>Trigger an interrupt if a STALL is sent. Intended for debug only.</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_ON_NAK</name>
+                        <description>Trigger an interrupt if a NAK is sent. Intended for debug only.</description>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>BUFFER_ADDRESS</name>
+                        <description>64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.</description>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>EP12_IN_CONTROL</name>
+                <addressOffset>0x00000060</addressOffset>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>ENABLE</name>
+                        <description>Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.</description>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DOUBLE_BUFFERED</name>
+                        <description>This endpoint is double buffered.</description>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_PER_BUFF</name>
+                        <description>Trigger an interrupt each time a buffer is done.</description>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_PER_DOUBLE_BUFF</name>
+                        <description>Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.</description>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ENDPOINT_TYPE</name>
+                        <bitRange>[27:26]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>Control</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Isochronous</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Bulk</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Interrupt</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_ON_STALL</name>
+                        <description>Trigger an interrupt if a STALL is sent. Intended for debug only.</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_ON_NAK</name>
+                        <description>Trigger an interrupt if a NAK is sent. Intended for debug only.</description>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>BUFFER_ADDRESS</name>
+                        <description>64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.</description>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>EP12_OUT_CONTROL</name>
+                <addressOffset>0x00000064</addressOffset>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>ENABLE</name>
+                        <description>Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.</description>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DOUBLE_BUFFERED</name>
+                        <description>This endpoint is double buffered.</description>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_PER_BUFF</name>
+                        <description>Trigger an interrupt each time a buffer is done.</description>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_PER_DOUBLE_BUFF</name>
+                        <description>Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.</description>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ENDPOINT_TYPE</name>
+                        <bitRange>[27:26]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>Control</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Isochronous</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Bulk</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Interrupt</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_ON_STALL</name>
+                        <description>Trigger an interrupt if a STALL is sent. Intended for debug only.</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_ON_NAK</name>
+                        <description>Trigger an interrupt if a NAK is sent. Intended for debug only.</description>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>BUFFER_ADDRESS</name>
+                        <description>64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.</description>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>EP13_IN_CONTROL</name>
+                <addressOffset>0x00000068</addressOffset>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>ENABLE</name>
+                        <description>Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.</description>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DOUBLE_BUFFERED</name>
+                        <description>This endpoint is double buffered.</description>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_PER_BUFF</name>
+                        <description>Trigger an interrupt each time a buffer is done.</description>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_PER_DOUBLE_BUFF</name>
+                        <description>Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.</description>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ENDPOINT_TYPE</name>
+                        <bitRange>[27:26]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>Control</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Isochronous</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Bulk</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Interrupt</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_ON_STALL</name>
+                        <description>Trigger an interrupt if a STALL is sent. Intended for debug only.</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_ON_NAK</name>
+                        <description>Trigger an interrupt if a NAK is sent. Intended for debug only.</description>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>BUFFER_ADDRESS</name>
+                        <description>64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.</description>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>EP13_OUT_CONTROL</name>
+                <addressOffset>0x0000006c</addressOffset>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>ENABLE</name>
+                        <description>Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.</description>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DOUBLE_BUFFERED</name>
+                        <description>This endpoint is double buffered.</description>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_PER_BUFF</name>
+                        <description>Trigger an interrupt each time a buffer is done.</description>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_PER_DOUBLE_BUFF</name>
+                        <description>Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.</description>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ENDPOINT_TYPE</name>
+                        <bitRange>[27:26]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>Control</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Isochronous</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Bulk</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Interrupt</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_ON_STALL</name>
+                        <description>Trigger an interrupt if a STALL is sent. Intended for debug only.</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_ON_NAK</name>
+                        <description>Trigger an interrupt if a NAK is sent. Intended for debug only.</description>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>BUFFER_ADDRESS</name>
+                        <description>64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.</description>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>EP14_IN_CONTROL</name>
+                <addressOffset>0x00000070</addressOffset>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>ENABLE</name>
+                        <description>Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.</description>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DOUBLE_BUFFERED</name>
+                        <description>This endpoint is double buffered.</description>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_PER_BUFF</name>
+                        <description>Trigger an interrupt each time a buffer is done.</description>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_PER_DOUBLE_BUFF</name>
+                        <description>Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.</description>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ENDPOINT_TYPE</name>
+                        <bitRange>[27:26]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>Control</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Isochronous</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Bulk</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Interrupt</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_ON_STALL</name>
+                        <description>Trigger an interrupt if a STALL is sent. Intended for debug only.</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_ON_NAK</name>
+                        <description>Trigger an interrupt if a NAK is sent. Intended for debug only.</description>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>BUFFER_ADDRESS</name>
+                        <description>64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.</description>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>EP14_OUT_CONTROL</name>
+                <addressOffset>0x00000074</addressOffset>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>ENABLE</name>
+                        <description>Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.</description>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DOUBLE_BUFFERED</name>
+                        <description>This endpoint is double buffered.</description>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_PER_BUFF</name>
+                        <description>Trigger an interrupt each time a buffer is done.</description>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_PER_DOUBLE_BUFF</name>
+                        <description>Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.</description>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ENDPOINT_TYPE</name>
+                        <bitRange>[27:26]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>Control</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Isochronous</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Bulk</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Interrupt</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_ON_STALL</name>
+                        <description>Trigger an interrupt if a STALL is sent. Intended for debug only.</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_ON_NAK</name>
+                        <description>Trigger an interrupt if a NAK is sent. Intended for debug only.</description>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>BUFFER_ADDRESS</name>
+                        <description>64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.</description>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>EP15_IN_CONTROL</name>
+                <addressOffset>0x00000078</addressOffset>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>ENABLE</name>
+                        <description>Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.</description>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DOUBLE_BUFFERED</name>
+                        <description>This endpoint is double buffered.</description>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_PER_BUFF</name>
+                        <description>Trigger an interrupt each time a buffer is done.</description>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_PER_DOUBLE_BUFF</name>
+                        <description>Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.</description>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ENDPOINT_TYPE</name>
+                        <bitRange>[27:26]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>Control</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Isochronous</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Bulk</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Interrupt</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_ON_STALL</name>
+                        <description>Trigger an interrupt if a STALL is sent. Intended for debug only.</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_ON_NAK</name>
+                        <description>Trigger an interrupt if a NAK is sent. Intended for debug only.</description>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>BUFFER_ADDRESS</name>
+                        <description>64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.</description>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>EP15_OUT_CONTROL</name>
+                <addressOffset>0x0000007c</addressOffset>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>ENABLE</name>
+                        <description>Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.</description>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DOUBLE_BUFFERED</name>
+                        <description>This endpoint is double buffered.</description>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_PER_BUFF</name>
+                        <description>Trigger an interrupt each time a buffer is done.</description>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_PER_DOUBLE_BUFF</name>
+                        <description>Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.</description>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ENDPOINT_TYPE</name>
+                        <bitRange>[27:26]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>Control</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Isochronous</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Bulk</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Interrupt</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_ON_STALL</name>
+                        <description>Trigger an interrupt if a STALL is sent. Intended for debug only.</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_ON_NAK</name>
+                        <description>Trigger an interrupt if a NAK is sent. Intended for debug only.</description>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>BUFFER_ADDRESS</name>
+                        <description>64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.</description>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>EP0_IN_BUFFER_CONTROL</name>
+                <addressOffset>0x00000080</addressOffset>
+                <description>Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. 
+                    Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>FULL_1</name>
+                        <description>Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LAST_1</name>
+                        <description>Buffer 1 is the last buffer of the transfer.</description>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PID_1</name>
+                        <description>The data pid of buffer 1.</description>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DOUBLE_BUFFER_ISO_OFFSET</name>
+                        <description>The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. 
+                            For a non Isochronous endpoint the offset is always 64 bytes.</description>
+                        <bitRange>[28:27]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>128</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>256</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>512</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>1024</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>AVAILABLE_1</name>
+                        <description>Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LENGTH_1</name>
+                        <description>The length of the data in buffer 1.</description>
+                        <bitRange>[25:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>FULL_0</name>
+                        <description>Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LAST_0</name>
+                        <description>Buffer 0 is the last buffer of the transfer.</description>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PID_0</name>
+                        <description>The data pid of buffer 0.</description>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>RESET</name>
+                        <description>Reset the buffer selector to buffer 0.</description>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>STALL</name>
+                        <description>Reply with a stall (valid for both buffers).</description>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>AVAILABLE_0</name>
+                        <description>Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LENGTH_0</name>
+                        <description>The length of the data in buffer 0.</description>
+                        <bitRange>[9:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>EP0_OUT_BUFFER_CONTROL</name>
+                <addressOffset>0x00000084</addressOffset>
+                <description>Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. 
+                    Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>FULL_1</name>
+                        <description>Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LAST_1</name>
+                        <description>Buffer 1 is the last buffer of the transfer.</description>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PID_1</name>
+                        <description>The data pid of buffer 1.</description>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DOUBLE_BUFFER_ISO_OFFSET</name>
+                        <description>The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. 
+                            For a non Isochronous endpoint the offset is always 64 bytes.</description>
+                        <bitRange>[28:27]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>128</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>256</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>512</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>1024</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>AVAILABLE_1</name>
+                        <description>Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LENGTH_1</name>
+                        <description>The length of the data in buffer 1.</description>
+                        <bitRange>[25:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>FULL_0</name>
+                        <description>Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LAST_0</name>
+                        <description>Buffer 0 is the last buffer of the transfer.</description>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PID_0</name>
+                        <description>The data pid of buffer 0.</description>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>RESET</name>
+                        <description>Reset the buffer selector to buffer 0.</description>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>STALL</name>
+                        <description>Reply with a stall (valid for both buffers).</description>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>AVAILABLE_0</name>
+                        <description>Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LENGTH_0</name>
+                        <description>The length of the data in buffer 0.</description>
+                        <bitRange>[9:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>EP1_IN_BUFFER_CONTROL</name>
+                <addressOffset>0x00000088</addressOffset>
+                <description>Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. 
+                    Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>FULL_1</name>
+                        <description>Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LAST_1</name>
+                        <description>Buffer 1 is the last buffer of the transfer.</description>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PID_1</name>
+                        <description>The data pid of buffer 1.</description>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DOUBLE_BUFFER_ISO_OFFSET</name>
+                        <description>The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. 
+                            For a non Isochronous endpoint the offset is always 64 bytes.</description>
+                        <bitRange>[28:27]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>128</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>256</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>512</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>1024</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>AVAILABLE_1</name>
+                        <description>Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LENGTH_1</name>
+                        <description>The length of the data in buffer 1.</description>
+                        <bitRange>[25:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>FULL_0</name>
+                        <description>Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LAST_0</name>
+                        <description>Buffer 0 is the last buffer of the transfer.</description>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PID_0</name>
+                        <description>The data pid of buffer 0.</description>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>RESET</name>
+                        <description>Reset the buffer selector to buffer 0.</description>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>STALL</name>
+                        <description>Reply with a stall (valid for both buffers).</description>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>AVAILABLE_0</name>
+                        <description>Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LENGTH_0</name>
+                        <description>The length of the data in buffer 0.</description>
+                        <bitRange>[9:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>EP1_OUT_BUFFER_CONTROL</name>
+                <addressOffset>0x0000008c</addressOffset>
+                <description>Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. 
+                    Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>FULL_1</name>
+                        <description>Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LAST_1</name>
+                        <description>Buffer 1 is the last buffer of the transfer.</description>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PID_1</name>
+                        <description>The data pid of buffer 1.</description>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DOUBLE_BUFFER_ISO_OFFSET</name>
+                        <description>The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. 
+                            For a non Isochronous endpoint the offset is always 64 bytes.</description>
+                        <bitRange>[28:27]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>128</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>256</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>512</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>1024</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>AVAILABLE_1</name>
+                        <description>Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LENGTH_1</name>
+                        <description>The length of the data in buffer 1.</description>
+                        <bitRange>[25:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>FULL_0</name>
+                        <description>Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LAST_0</name>
+                        <description>Buffer 0 is the last buffer of the transfer.</description>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PID_0</name>
+                        <description>The data pid of buffer 0.</description>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>RESET</name>
+                        <description>Reset the buffer selector to buffer 0.</description>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>STALL</name>
+                        <description>Reply with a stall (valid for both buffers).</description>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>AVAILABLE_0</name>
+                        <description>Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LENGTH_0</name>
+                        <description>The length of the data in buffer 0.</description>
+                        <bitRange>[9:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>EP2_IN_BUFFER_CONTROL</name>
+                <addressOffset>0x00000090</addressOffset>
+                <description>Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. 
+                    Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>FULL_1</name>
+                        <description>Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LAST_1</name>
+                        <description>Buffer 1 is the last buffer of the transfer.</description>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PID_1</name>
+                        <description>The data pid of buffer 1.</description>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DOUBLE_BUFFER_ISO_OFFSET</name>
+                        <description>The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. 
+                            For a non Isochronous endpoint the offset is always 64 bytes.</description>
+                        <bitRange>[28:27]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>128</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>256</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>512</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>1024</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>AVAILABLE_1</name>
+                        <description>Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LENGTH_1</name>
+                        <description>The length of the data in buffer 1.</description>
+                        <bitRange>[25:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>FULL_0</name>
+                        <description>Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LAST_0</name>
+                        <description>Buffer 0 is the last buffer of the transfer.</description>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PID_0</name>
+                        <description>The data pid of buffer 0.</description>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>RESET</name>
+                        <description>Reset the buffer selector to buffer 0.</description>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>STALL</name>
+                        <description>Reply with a stall (valid for both buffers).</description>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>AVAILABLE_0</name>
+                        <description>Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LENGTH_0</name>
+                        <description>The length of the data in buffer 0.</description>
+                        <bitRange>[9:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>EP2_OUT_BUFFER_CONTROL</name>
+                <addressOffset>0x00000094</addressOffset>
+                <description>Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. 
+                    Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>FULL_1</name>
+                        <description>Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LAST_1</name>
+                        <description>Buffer 1 is the last buffer of the transfer.</description>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PID_1</name>
+                        <description>The data pid of buffer 1.</description>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DOUBLE_BUFFER_ISO_OFFSET</name>
+                        <description>The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. 
+                            For a non Isochronous endpoint the offset is always 64 bytes.</description>
+                        <bitRange>[28:27]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>128</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>256</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>512</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>1024</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>AVAILABLE_1</name>
+                        <description>Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LENGTH_1</name>
+                        <description>The length of the data in buffer 1.</description>
+                        <bitRange>[25:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>FULL_0</name>
+                        <description>Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LAST_0</name>
+                        <description>Buffer 0 is the last buffer of the transfer.</description>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PID_0</name>
+                        <description>The data pid of buffer 0.</description>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>RESET</name>
+                        <description>Reset the buffer selector to buffer 0.</description>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>STALL</name>
+                        <description>Reply with a stall (valid for both buffers).</description>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>AVAILABLE_0</name>
+                        <description>Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LENGTH_0</name>
+                        <description>The length of the data in buffer 0.</description>
+                        <bitRange>[9:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>EP3_IN_BUFFER_CONTROL</name>
+                <addressOffset>0x00000098</addressOffset>
+                <description>Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. 
+                    Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>FULL_1</name>
+                        <description>Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LAST_1</name>
+                        <description>Buffer 1 is the last buffer of the transfer.</description>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PID_1</name>
+                        <description>The data pid of buffer 1.</description>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DOUBLE_BUFFER_ISO_OFFSET</name>
+                        <description>The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. 
+                            For a non Isochronous endpoint the offset is always 64 bytes.</description>
+                        <bitRange>[28:27]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>128</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>256</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>512</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>1024</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>AVAILABLE_1</name>
+                        <description>Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LENGTH_1</name>
+                        <description>The length of the data in buffer 1.</description>
+                        <bitRange>[25:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>FULL_0</name>
+                        <description>Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LAST_0</name>
+                        <description>Buffer 0 is the last buffer of the transfer.</description>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PID_0</name>
+                        <description>The data pid of buffer 0.</description>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>RESET</name>
+                        <description>Reset the buffer selector to buffer 0.</description>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>STALL</name>
+                        <description>Reply with a stall (valid for both buffers).</description>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>AVAILABLE_0</name>
+                        <description>Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LENGTH_0</name>
+                        <description>The length of the data in buffer 0.</description>
+                        <bitRange>[9:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>EP3_OUT_BUFFER_CONTROL</name>
+                <addressOffset>0x0000009c</addressOffset>
+                <description>Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. 
+                    Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>FULL_1</name>
+                        <description>Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LAST_1</name>
+                        <description>Buffer 1 is the last buffer of the transfer.</description>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PID_1</name>
+                        <description>The data pid of buffer 1.</description>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DOUBLE_BUFFER_ISO_OFFSET</name>
+                        <description>The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. 
+                            For a non Isochronous endpoint the offset is always 64 bytes.</description>
+                        <bitRange>[28:27]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>128</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>256</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>512</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>1024</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>AVAILABLE_1</name>
+                        <description>Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LENGTH_1</name>
+                        <description>The length of the data in buffer 1.</description>
+                        <bitRange>[25:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>FULL_0</name>
+                        <description>Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LAST_0</name>
+                        <description>Buffer 0 is the last buffer of the transfer.</description>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PID_0</name>
+                        <description>The data pid of buffer 0.</description>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>RESET</name>
+                        <description>Reset the buffer selector to buffer 0.</description>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>STALL</name>
+                        <description>Reply with a stall (valid for both buffers).</description>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>AVAILABLE_0</name>
+                        <description>Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LENGTH_0</name>
+                        <description>The length of the data in buffer 0.</description>
+                        <bitRange>[9:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>EP4_IN_BUFFER_CONTROL</name>
+                <addressOffset>0x000000a0</addressOffset>
+                <description>Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. 
+                    Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>FULL_1</name>
+                        <description>Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LAST_1</name>
+                        <description>Buffer 1 is the last buffer of the transfer.</description>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PID_1</name>
+                        <description>The data pid of buffer 1.</description>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DOUBLE_BUFFER_ISO_OFFSET</name>
+                        <description>The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. 
+                            For a non Isochronous endpoint the offset is always 64 bytes.</description>
+                        <bitRange>[28:27]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>128</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>256</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>512</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>1024</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>AVAILABLE_1</name>
+                        <description>Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LENGTH_1</name>
+                        <description>The length of the data in buffer 1.</description>
+                        <bitRange>[25:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>FULL_0</name>
+                        <description>Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LAST_0</name>
+                        <description>Buffer 0 is the last buffer of the transfer.</description>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PID_0</name>
+                        <description>The data pid of buffer 0.</description>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>RESET</name>
+                        <description>Reset the buffer selector to buffer 0.</description>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>STALL</name>
+                        <description>Reply with a stall (valid for both buffers).</description>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>AVAILABLE_0</name>
+                        <description>Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LENGTH_0</name>
+                        <description>The length of the data in buffer 0.</description>
+                        <bitRange>[9:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>EP4_OUT_BUFFER_CONTROL</name>
+                <addressOffset>0x000000a4</addressOffset>
+                <description>Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. 
+                    Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>FULL_1</name>
+                        <description>Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LAST_1</name>
+                        <description>Buffer 1 is the last buffer of the transfer.</description>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PID_1</name>
+                        <description>The data pid of buffer 1.</description>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DOUBLE_BUFFER_ISO_OFFSET</name>
+                        <description>The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. 
+                            For a non Isochronous endpoint the offset is always 64 bytes.</description>
+                        <bitRange>[28:27]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>128</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>256</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>512</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>1024</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>AVAILABLE_1</name>
+                        <description>Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LENGTH_1</name>
+                        <description>The length of the data in buffer 1.</description>
+                        <bitRange>[25:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>FULL_0</name>
+                        <description>Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LAST_0</name>
+                        <description>Buffer 0 is the last buffer of the transfer.</description>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PID_0</name>
+                        <description>The data pid of buffer 0.</description>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>RESET</name>
+                        <description>Reset the buffer selector to buffer 0.</description>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>STALL</name>
+                        <description>Reply with a stall (valid for both buffers).</description>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>AVAILABLE_0</name>
+                        <description>Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LENGTH_0</name>
+                        <description>The length of the data in buffer 0.</description>
+                        <bitRange>[9:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>EP5_IN_BUFFER_CONTROL</name>
+                <addressOffset>0x000000a8</addressOffset>
+                <description>Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. 
+                    Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>FULL_1</name>
+                        <description>Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LAST_1</name>
+                        <description>Buffer 1 is the last buffer of the transfer.</description>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PID_1</name>
+                        <description>The data pid of buffer 1.</description>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DOUBLE_BUFFER_ISO_OFFSET</name>
+                        <description>The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. 
+                            For a non Isochronous endpoint the offset is always 64 bytes.</description>
+                        <bitRange>[28:27]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>128</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>256</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>512</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>1024</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>AVAILABLE_1</name>
+                        <description>Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LENGTH_1</name>
+                        <description>The length of the data in buffer 1.</description>
+                        <bitRange>[25:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>FULL_0</name>
+                        <description>Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LAST_0</name>
+                        <description>Buffer 0 is the last buffer of the transfer.</description>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PID_0</name>
+                        <description>The data pid of buffer 0.</description>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>RESET</name>
+                        <description>Reset the buffer selector to buffer 0.</description>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>STALL</name>
+                        <description>Reply with a stall (valid for both buffers).</description>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>AVAILABLE_0</name>
+                        <description>Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LENGTH_0</name>
+                        <description>The length of the data in buffer 0.</description>
+                        <bitRange>[9:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>EP5_OUT_BUFFER_CONTROL</name>
+                <addressOffset>0x000000ac</addressOffset>
+                <description>Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. 
+                    Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>FULL_1</name>
+                        <description>Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LAST_1</name>
+                        <description>Buffer 1 is the last buffer of the transfer.</description>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PID_1</name>
+                        <description>The data pid of buffer 1.</description>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DOUBLE_BUFFER_ISO_OFFSET</name>
+                        <description>The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. 
+                            For a non Isochronous endpoint the offset is always 64 bytes.</description>
+                        <bitRange>[28:27]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>128</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>256</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>512</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>1024</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>AVAILABLE_1</name>
+                        <description>Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LENGTH_1</name>
+                        <description>The length of the data in buffer 1.</description>
+                        <bitRange>[25:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>FULL_0</name>
+                        <description>Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LAST_0</name>
+                        <description>Buffer 0 is the last buffer of the transfer.</description>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PID_0</name>
+                        <description>The data pid of buffer 0.</description>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>RESET</name>
+                        <description>Reset the buffer selector to buffer 0.</description>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>STALL</name>
+                        <description>Reply with a stall (valid for both buffers).</description>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>AVAILABLE_0</name>
+                        <description>Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LENGTH_0</name>
+                        <description>The length of the data in buffer 0.</description>
+                        <bitRange>[9:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>EP6_IN_BUFFER_CONTROL</name>
+                <addressOffset>0x000000b0</addressOffset>
+                <description>Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. 
+                    Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>FULL_1</name>
+                        <description>Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LAST_1</name>
+                        <description>Buffer 1 is the last buffer of the transfer.</description>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PID_1</name>
+                        <description>The data pid of buffer 1.</description>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DOUBLE_BUFFER_ISO_OFFSET</name>
+                        <description>The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. 
+                            For a non Isochronous endpoint the offset is always 64 bytes.</description>
+                        <bitRange>[28:27]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>128</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>256</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>512</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>1024</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>AVAILABLE_1</name>
+                        <description>Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LENGTH_1</name>
+                        <description>The length of the data in buffer 1.</description>
+                        <bitRange>[25:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>FULL_0</name>
+                        <description>Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LAST_0</name>
+                        <description>Buffer 0 is the last buffer of the transfer.</description>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PID_0</name>
+                        <description>The data pid of buffer 0.</description>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>RESET</name>
+                        <description>Reset the buffer selector to buffer 0.</description>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>STALL</name>
+                        <description>Reply with a stall (valid for both buffers).</description>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>AVAILABLE_0</name>
+                        <description>Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LENGTH_0</name>
+                        <description>The length of the data in buffer 0.</description>
+                        <bitRange>[9:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>EP6_OUT_BUFFER_CONTROL</name>
+                <addressOffset>0x000000b4</addressOffset>
+                <description>Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. 
+                    Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>FULL_1</name>
+                        <description>Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LAST_1</name>
+                        <description>Buffer 1 is the last buffer of the transfer.</description>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PID_1</name>
+                        <description>The data pid of buffer 1.</description>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DOUBLE_BUFFER_ISO_OFFSET</name>
+                        <description>The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. 
+                            For a non Isochronous endpoint the offset is always 64 bytes.</description>
+                        <bitRange>[28:27]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>128</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>256</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>512</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>1024</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>AVAILABLE_1</name>
+                        <description>Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LENGTH_1</name>
+                        <description>The length of the data in buffer 1.</description>
+                        <bitRange>[25:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>FULL_0</name>
+                        <description>Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LAST_0</name>
+                        <description>Buffer 0 is the last buffer of the transfer.</description>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PID_0</name>
+                        <description>The data pid of buffer 0.</description>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>RESET</name>
+                        <description>Reset the buffer selector to buffer 0.</description>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>STALL</name>
+                        <description>Reply with a stall (valid for both buffers).</description>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>AVAILABLE_0</name>
+                        <description>Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LENGTH_0</name>
+                        <description>The length of the data in buffer 0.</description>
+                        <bitRange>[9:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>EP7_IN_BUFFER_CONTROL</name>
+                <addressOffset>0x000000b8</addressOffset>
+                <description>Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. 
+                    Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>FULL_1</name>
+                        <description>Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LAST_1</name>
+                        <description>Buffer 1 is the last buffer of the transfer.</description>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PID_1</name>
+                        <description>The data pid of buffer 1.</description>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DOUBLE_BUFFER_ISO_OFFSET</name>
+                        <description>The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. 
+                            For a non Isochronous endpoint the offset is always 64 bytes.</description>
+                        <bitRange>[28:27]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>128</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>256</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>512</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>1024</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>AVAILABLE_1</name>
+                        <description>Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LENGTH_1</name>
+                        <description>The length of the data in buffer 1.</description>
+                        <bitRange>[25:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>FULL_0</name>
+                        <description>Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LAST_0</name>
+                        <description>Buffer 0 is the last buffer of the transfer.</description>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PID_0</name>
+                        <description>The data pid of buffer 0.</description>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>RESET</name>
+                        <description>Reset the buffer selector to buffer 0.</description>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>STALL</name>
+                        <description>Reply with a stall (valid for both buffers).</description>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>AVAILABLE_0</name>
+                        <description>Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LENGTH_0</name>
+                        <description>The length of the data in buffer 0.</description>
+                        <bitRange>[9:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>EP7_OUT_BUFFER_CONTROL</name>
+                <addressOffset>0x000000bc</addressOffset>
+                <description>Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. 
+                    Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>FULL_1</name>
+                        <description>Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LAST_1</name>
+                        <description>Buffer 1 is the last buffer of the transfer.</description>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PID_1</name>
+                        <description>The data pid of buffer 1.</description>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DOUBLE_BUFFER_ISO_OFFSET</name>
+                        <description>The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. 
+                            For a non Isochronous endpoint the offset is always 64 bytes.</description>
+                        <bitRange>[28:27]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>128</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>256</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>512</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>1024</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>AVAILABLE_1</name>
+                        <description>Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LENGTH_1</name>
+                        <description>The length of the data in buffer 1.</description>
+                        <bitRange>[25:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>FULL_0</name>
+                        <description>Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LAST_0</name>
+                        <description>Buffer 0 is the last buffer of the transfer.</description>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PID_0</name>
+                        <description>The data pid of buffer 0.</description>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>RESET</name>
+                        <description>Reset the buffer selector to buffer 0.</description>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>STALL</name>
+                        <description>Reply with a stall (valid for both buffers).</description>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>AVAILABLE_0</name>
+                        <description>Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LENGTH_0</name>
+                        <description>The length of the data in buffer 0.</description>
+                        <bitRange>[9:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>EP8_IN_BUFFER_CONTROL</name>
+                <addressOffset>0x000000c0</addressOffset>
+                <description>Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. 
+                    Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>FULL_1</name>
+                        <description>Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LAST_1</name>
+                        <description>Buffer 1 is the last buffer of the transfer.</description>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PID_1</name>
+                        <description>The data pid of buffer 1.</description>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DOUBLE_BUFFER_ISO_OFFSET</name>
+                        <description>The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. 
+                            For a non Isochronous endpoint the offset is always 64 bytes.</description>
+                        <bitRange>[28:27]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>128</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>256</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>512</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>1024</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>AVAILABLE_1</name>
+                        <description>Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LENGTH_1</name>
+                        <description>The length of the data in buffer 1.</description>
+                        <bitRange>[25:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>FULL_0</name>
+                        <description>Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LAST_0</name>
+                        <description>Buffer 0 is the last buffer of the transfer.</description>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PID_0</name>
+                        <description>The data pid of buffer 0.</description>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>RESET</name>
+                        <description>Reset the buffer selector to buffer 0.</description>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>STALL</name>
+                        <description>Reply with a stall (valid for both buffers).</description>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>AVAILABLE_0</name>
+                        <description>Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LENGTH_0</name>
+                        <description>The length of the data in buffer 0.</description>
+                        <bitRange>[9:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>EP8_OUT_BUFFER_CONTROL</name>
+                <addressOffset>0x000000c4</addressOffset>
+                <description>Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. 
+                    Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>FULL_1</name>
+                        <description>Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LAST_1</name>
+                        <description>Buffer 1 is the last buffer of the transfer.</description>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PID_1</name>
+                        <description>The data pid of buffer 1.</description>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DOUBLE_BUFFER_ISO_OFFSET</name>
+                        <description>The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. 
+                            For a non Isochronous endpoint the offset is always 64 bytes.</description>
+                        <bitRange>[28:27]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>128</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>256</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>512</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>1024</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>AVAILABLE_1</name>
+                        <description>Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LENGTH_1</name>
+                        <description>The length of the data in buffer 1.</description>
+                        <bitRange>[25:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>FULL_0</name>
+                        <description>Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LAST_0</name>
+                        <description>Buffer 0 is the last buffer of the transfer.</description>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PID_0</name>
+                        <description>The data pid of buffer 0.</description>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>RESET</name>
+                        <description>Reset the buffer selector to buffer 0.</description>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>STALL</name>
+                        <description>Reply with a stall (valid for both buffers).</description>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>AVAILABLE_0</name>
+                        <description>Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LENGTH_0</name>
+                        <description>The length of the data in buffer 0.</description>
+                        <bitRange>[9:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>EP9_IN_BUFFER_CONTROL</name>
+                <addressOffset>0x000000c8</addressOffset>
+                <description>Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. 
+                    Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>FULL_1</name>
+                        <description>Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LAST_1</name>
+                        <description>Buffer 1 is the last buffer of the transfer.</description>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PID_1</name>
+                        <description>The data pid of buffer 1.</description>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DOUBLE_BUFFER_ISO_OFFSET</name>
+                        <description>The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. 
+                            For a non Isochronous endpoint the offset is always 64 bytes.</description>
+                        <bitRange>[28:27]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>128</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>256</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>512</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>1024</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>AVAILABLE_1</name>
+                        <description>Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LENGTH_1</name>
+                        <description>The length of the data in buffer 1.</description>
+                        <bitRange>[25:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>FULL_0</name>
+                        <description>Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LAST_0</name>
+                        <description>Buffer 0 is the last buffer of the transfer.</description>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PID_0</name>
+                        <description>The data pid of buffer 0.</description>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>RESET</name>
+                        <description>Reset the buffer selector to buffer 0.</description>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>STALL</name>
+                        <description>Reply with a stall (valid for both buffers).</description>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>AVAILABLE_0</name>
+                        <description>Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LENGTH_0</name>
+                        <description>The length of the data in buffer 0.</description>
+                        <bitRange>[9:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>EP9_OUT_BUFFER_CONTROL</name>
+                <addressOffset>0x000000cc</addressOffset>
+                <description>Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. 
+                    Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>FULL_1</name>
+                        <description>Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LAST_1</name>
+                        <description>Buffer 1 is the last buffer of the transfer.</description>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PID_1</name>
+                        <description>The data pid of buffer 1.</description>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DOUBLE_BUFFER_ISO_OFFSET</name>
+                        <description>The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. 
+                            For a non Isochronous endpoint the offset is always 64 bytes.</description>
+                        <bitRange>[28:27]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>128</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>256</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>512</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>1024</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>AVAILABLE_1</name>
+                        <description>Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LENGTH_1</name>
+                        <description>The length of the data in buffer 1.</description>
+                        <bitRange>[25:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>FULL_0</name>
+                        <description>Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LAST_0</name>
+                        <description>Buffer 0 is the last buffer of the transfer.</description>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PID_0</name>
+                        <description>The data pid of buffer 0.</description>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>RESET</name>
+                        <description>Reset the buffer selector to buffer 0.</description>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>STALL</name>
+                        <description>Reply with a stall (valid for both buffers).</description>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>AVAILABLE_0</name>
+                        <description>Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LENGTH_0</name>
+                        <description>The length of the data in buffer 0.</description>
+                        <bitRange>[9:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>EP10_IN_BUFFER_CONTROL</name>
+                <addressOffset>0x000000d0</addressOffset>
+                <description>Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. 
+                    Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>FULL_1</name>
+                        <description>Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LAST_1</name>
+                        <description>Buffer 1 is the last buffer of the transfer.</description>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PID_1</name>
+                        <description>The data pid of buffer 1.</description>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DOUBLE_BUFFER_ISO_OFFSET</name>
+                        <description>The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. 
+                            For a non Isochronous endpoint the offset is always 64 bytes.</description>
+                        <bitRange>[28:27]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>128</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>256</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>512</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>1024</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>AVAILABLE_1</name>
+                        <description>Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LENGTH_1</name>
+                        <description>The length of the data in buffer 1.</description>
+                        <bitRange>[25:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>FULL_0</name>
+                        <description>Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LAST_0</name>
+                        <description>Buffer 0 is the last buffer of the transfer.</description>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PID_0</name>
+                        <description>The data pid of buffer 0.</description>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>RESET</name>
+                        <description>Reset the buffer selector to buffer 0.</description>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>STALL</name>
+                        <description>Reply with a stall (valid for both buffers).</description>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>AVAILABLE_0</name>
+                        <description>Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LENGTH_0</name>
+                        <description>The length of the data in buffer 0.</description>
+                        <bitRange>[9:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>EP10_OUT_BUFFER_CONTROL</name>
+                <addressOffset>0x000000d4</addressOffset>
+                <description>Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. 
+                    Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>FULL_1</name>
+                        <description>Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LAST_1</name>
+                        <description>Buffer 1 is the last buffer of the transfer.</description>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PID_1</name>
+                        <description>The data pid of buffer 1.</description>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DOUBLE_BUFFER_ISO_OFFSET</name>
+                        <description>The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. 
+                            For a non Isochronous endpoint the offset is always 64 bytes.</description>
+                        <bitRange>[28:27]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>128</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>256</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>512</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>1024</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>AVAILABLE_1</name>
+                        <description>Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LENGTH_1</name>
+                        <description>The length of the data in buffer 1.</description>
+                        <bitRange>[25:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>FULL_0</name>
+                        <description>Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LAST_0</name>
+                        <description>Buffer 0 is the last buffer of the transfer.</description>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PID_0</name>
+                        <description>The data pid of buffer 0.</description>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>RESET</name>
+                        <description>Reset the buffer selector to buffer 0.</description>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>STALL</name>
+                        <description>Reply with a stall (valid for both buffers).</description>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>AVAILABLE_0</name>
+                        <description>Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LENGTH_0</name>
+                        <description>The length of the data in buffer 0.</description>
+                        <bitRange>[9:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>EP11_IN_BUFFER_CONTROL</name>
+                <addressOffset>0x000000d8</addressOffset>
+                <description>Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. 
+                    Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>FULL_1</name>
+                        <description>Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LAST_1</name>
+                        <description>Buffer 1 is the last buffer of the transfer.</description>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PID_1</name>
+                        <description>The data pid of buffer 1.</description>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DOUBLE_BUFFER_ISO_OFFSET</name>
+                        <description>The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. 
+                            For a non Isochronous endpoint the offset is always 64 bytes.</description>
+                        <bitRange>[28:27]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>128</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>256</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>512</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>1024</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>AVAILABLE_1</name>
+                        <description>Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LENGTH_1</name>
+                        <description>The length of the data in buffer 1.</description>
+                        <bitRange>[25:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>FULL_0</name>
+                        <description>Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LAST_0</name>
+                        <description>Buffer 0 is the last buffer of the transfer.</description>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PID_0</name>
+                        <description>The data pid of buffer 0.</description>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>RESET</name>
+                        <description>Reset the buffer selector to buffer 0.</description>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>STALL</name>
+                        <description>Reply with a stall (valid for both buffers).</description>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>AVAILABLE_0</name>
+                        <description>Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LENGTH_0</name>
+                        <description>The length of the data in buffer 0.</description>
+                        <bitRange>[9:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>EP11_OUT_BUFFER_CONTROL</name>
+                <addressOffset>0x000000dc</addressOffset>
+                <description>Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. 
+                    Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>FULL_1</name>
+                        <description>Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LAST_1</name>
+                        <description>Buffer 1 is the last buffer of the transfer.</description>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PID_1</name>
+                        <description>The data pid of buffer 1.</description>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DOUBLE_BUFFER_ISO_OFFSET</name>
+                        <description>The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. 
+                            For a non Isochronous endpoint the offset is always 64 bytes.</description>
+                        <bitRange>[28:27]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>128</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>256</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>512</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>1024</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>AVAILABLE_1</name>
+                        <description>Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LENGTH_1</name>
+                        <description>The length of the data in buffer 1.</description>
+                        <bitRange>[25:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>FULL_0</name>
+                        <description>Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LAST_0</name>
+                        <description>Buffer 0 is the last buffer of the transfer.</description>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PID_0</name>
+                        <description>The data pid of buffer 0.</description>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>RESET</name>
+                        <description>Reset the buffer selector to buffer 0.</description>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>STALL</name>
+                        <description>Reply with a stall (valid for both buffers).</description>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>AVAILABLE_0</name>
+                        <description>Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LENGTH_0</name>
+                        <description>The length of the data in buffer 0.</description>
+                        <bitRange>[9:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>EP12_IN_BUFFER_CONTROL</name>
+                <addressOffset>0x000000e0</addressOffset>
+                <description>Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. 
+                    Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>FULL_1</name>
+                        <description>Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LAST_1</name>
+                        <description>Buffer 1 is the last buffer of the transfer.</description>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PID_1</name>
+                        <description>The data pid of buffer 1.</description>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DOUBLE_BUFFER_ISO_OFFSET</name>
+                        <description>The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. 
+                            For a non Isochronous endpoint the offset is always 64 bytes.</description>
+                        <bitRange>[28:27]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>128</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>256</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>512</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>1024</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>AVAILABLE_1</name>
+                        <description>Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LENGTH_1</name>
+                        <description>The length of the data in buffer 1.</description>
+                        <bitRange>[25:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>FULL_0</name>
+                        <description>Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LAST_0</name>
+                        <description>Buffer 0 is the last buffer of the transfer.</description>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PID_0</name>
+                        <description>The data pid of buffer 0.</description>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>RESET</name>
+                        <description>Reset the buffer selector to buffer 0.</description>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>STALL</name>
+                        <description>Reply with a stall (valid for both buffers).</description>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>AVAILABLE_0</name>
+                        <description>Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LENGTH_0</name>
+                        <description>The length of the data in buffer 0.</description>
+                        <bitRange>[9:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>EP12_OUT_BUFFER_CONTROL</name>
+                <addressOffset>0x000000e4</addressOffset>
+                <description>Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. 
+                    Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>FULL_1</name>
+                        <description>Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LAST_1</name>
+                        <description>Buffer 1 is the last buffer of the transfer.</description>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PID_1</name>
+                        <description>The data pid of buffer 1.</description>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DOUBLE_BUFFER_ISO_OFFSET</name>
+                        <description>The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. 
+                            For a non Isochronous endpoint the offset is always 64 bytes.</description>
+                        <bitRange>[28:27]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>128</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>256</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>512</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>1024</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>AVAILABLE_1</name>
+                        <description>Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LENGTH_1</name>
+                        <description>The length of the data in buffer 1.</description>
+                        <bitRange>[25:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>FULL_0</name>
+                        <description>Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LAST_0</name>
+                        <description>Buffer 0 is the last buffer of the transfer.</description>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PID_0</name>
+                        <description>The data pid of buffer 0.</description>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>RESET</name>
+                        <description>Reset the buffer selector to buffer 0.</description>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>STALL</name>
+                        <description>Reply with a stall (valid for both buffers).</description>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>AVAILABLE_0</name>
+                        <description>Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LENGTH_0</name>
+                        <description>The length of the data in buffer 0.</description>
+                        <bitRange>[9:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>EP13_IN_BUFFER_CONTROL</name>
+                <addressOffset>0x000000e8</addressOffset>
+                <description>Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. 
+                    Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>FULL_1</name>
+                        <description>Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LAST_1</name>
+                        <description>Buffer 1 is the last buffer of the transfer.</description>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PID_1</name>
+                        <description>The data pid of buffer 1.</description>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DOUBLE_BUFFER_ISO_OFFSET</name>
+                        <description>The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. 
+                            For a non Isochronous endpoint the offset is always 64 bytes.</description>
+                        <bitRange>[28:27]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>128</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>256</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>512</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>1024</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>AVAILABLE_1</name>
+                        <description>Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LENGTH_1</name>
+                        <description>The length of the data in buffer 1.</description>
+                        <bitRange>[25:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>FULL_0</name>
+                        <description>Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LAST_0</name>
+                        <description>Buffer 0 is the last buffer of the transfer.</description>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PID_0</name>
+                        <description>The data pid of buffer 0.</description>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>RESET</name>
+                        <description>Reset the buffer selector to buffer 0.</description>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>STALL</name>
+                        <description>Reply with a stall (valid for both buffers).</description>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>AVAILABLE_0</name>
+                        <description>Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LENGTH_0</name>
+                        <description>The length of the data in buffer 0.</description>
+                        <bitRange>[9:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>EP13_OUT_BUFFER_CONTROL</name>
+                <addressOffset>0x000000ec</addressOffset>
+                <description>Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. 
+                    Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>FULL_1</name>
+                        <description>Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LAST_1</name>
+                        <description>Buffer 1 is the last buffer of the transfer.</description>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PID_1</name>
+                        <description>The data pid of buffer 1.</description>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DOUBLE_BUFFER_ISO_OFFSET</name>
+                        <description>The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. 
+                            For a non Isochronous endpoint the offset is always 64 bytes.</description>
+                        <bitRange>[28:27]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>128</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>256</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>512</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>1024</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>AVAILABLE_1</name>
+                        <description>Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LENGTH_1</name>
+                        <description>The length of the data in buffer 1.</description>
+                        <bitRange>[25:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>FULL_0</name>
+                        <description>Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LAST_0</name>
+                        <description>Buffer 0 is the last buffer of the transfer.</description>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PID_0</name>
+                        <description>The data pid of buffer 0.</description>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>RESET</name>
+                        <description>Reset the buffer selector to buffer 0.</description>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>STALL</name>
+                        <description>Reply with a stall (valid for both buffers).</description>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>AVAILABLE_0</name>
+                        <description>Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LENGTH_0</name>
+                        <description>The length of the data in buffer 0.</description>
+                        <bitRange>[9:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>EP14_IN_BUFFER_CONTROL</name>
+                <addressOffset>0x000000f0</addressOffset>
+                <description>Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. 
+                    Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>FULL_1</name>
+                        <description>Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LAST_1</name>
+                        <description>Buffer 1 is the last buffer of the transfer.</description>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PID_1</name>
+                        <description>The data pid of buffer 1.</description>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DOUBLE_BUFFER_ISO_OFFSET</name>
+                        <description>The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. 
+                            For a non Isochronous endpoint the offset is always 64 bytes.</description>
+                        <bitRange>[28:27]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>128</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>256</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>512</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>1024</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>AVAILABLE_1</name>
+                        <description>Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LENGTH_1</name>
+                        <description>The length of the data in buffer 1.</description>
+                        <bitRange>[25:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>FULL_0</name>
+                        <description>Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LAST_0</name>
+                        <description>Buffer 0 is the last buffer of the transfer.</description>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PID_0</name>
+                        <description>The data pid of buffer 0.</description>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>RESET</name>
+                        <description>Reset the buffer selector to buffer 0.</description>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>STALL</name>
+                        <description>Reply with a stall (valid for both buffers).</description>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>AVAILABLE_0</name>
+                        <description>Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LENGTH_0</name>
+                        <description>The length of the data in buffer 0.</description>
+                        <bitRange>[9:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>EP14_OUT_BUFFER_CONTROL</name>
+                <addressOffset>0x000000f4</addressOffset>
+                <description>Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. 
+                    Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>FULL_1</name>
+                        <description>Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LAST_1</name>
+                        <description>Buffer 1 is the last buffer of the transfer.</description>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PID_1</name>
+                        <description>The data pid of buffer 1.</description>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DOUBLE_BUFFER_ISO_OFFSET</name>
+                        <description>The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. 
+                            For a non Isochronous endpoint the offset is always 64 bytes.</description>
+                        <bitRange>[28:27]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>128</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>256</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>512</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>1024</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>AVAILABLE_1</name>
+                        <description>Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LENGTH_1</name>
+                        <description>The length of the data in buffer 1.</description>
+                        <bitRange>[25:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>FULL_0</name>
+                        <description>Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LAST_0</name>
+                        <description>Buffer 0 is the last buffer of the transfer.</description>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PID_0</name>
+                        <description>The data pid of buffer 0.</description>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>RESET</name>
+                        <description>Reset the buffer selector to buffer 0.</description>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>STALL</name>
+                        <description>Reply with a stall (valid for both buffers).</description>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>AVAILABLE_0</name>
+                        <description>Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LENGTH_0</name>
+                        <description>The length of the data in buffer 0.</description>
+                        <bitRange>[9:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>EP15_IN_BUFFER_CONTROL</name>
+                <addressOffset>0x000000f8</addressOffset>
+                <description>Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. 
+                    Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>FULL_1</name>
+                        <description>Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LAST_1</name>
+                        <description>Buffer 1 is the last buffer of the transfer.</description>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PID_1</name>
+                        <description>The data pid of buffer 1.</description>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DOUBLE_BUFFER_ISO_OFFSET</name>
+                        <description>The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. 
+                            For a non Isochronous endpoint the offset is always 64 bytes.</description>
+                        <bitRange>[28:27]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>128</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>256</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>512</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>1024</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>AVAILABLE_1</name>
+                        <description>Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LENGTH_1</name>
+                        <description>The length of the data in buffer 1.</description>
+                        <bitRange>[25:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>FULL_0</name>
+                        <description>Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LAST_0</name>
+                        <description>Buffer 0 is the last buffer of the transfer.</description>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PID_0</name>
+                        <description>The data pid of buffer 0.</description>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>RESET</name>
+                        <description>Reset the buffer selector to buffer 0.</description>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>STALL</name>
+                        <description>Reply with a stall (valid for both buffers).</description>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>AVAILABLE_0</name>
+                        <description>Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LENGTH_0</name>
+                        <description>The length of the data in buffer 0.</description>
+                        <bitRange>[9:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>EP15_OUT_BUFFER_CONTROL</name>
+                <addressOffset>0x000000fc</addressOffset>
+                <description>Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. 
+                    Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>FULL_1</name>
+                        <description>Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LAST_1</name>
+                        <description>Buffer 1 is the last buffer of the transfer.</description>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PID_1</name>
+                        <description>The data pid of buffer 1.</description>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DOUBLE_BUFFER_ISO_OFFSET</name>
+                        <description>The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. 
+                            For a non Isochronous endpoint the offset is always 64 bytes.</description>
+                        <bitRange>[28:27]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>128</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>256</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>512</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>1024</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>AVAILABLE_1</name>
+                        <description>Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LENGTH_1</name>
+                        <description>The length of the data in buffer 1.</description>
+                        <bitRange>[25:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>FULL_0</name>
+                        <description>Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LAST_0</name>
+                        <description>Buffer 0 is the last buffer of the transfer.</description>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PID_0</name>
+                        <description>The data pid of buffer 0.</description>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>RESET</name>
+                        <description>Reset the buffer selector to buffer 0.</description>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>STALL</name>
+                        <description>Reply with a stall (valid for both buffers).</description>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>AVAILABLE_0</name>
+                        <description>Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LENGTH_0</name>
+                        <description>The length of the data in buffer 0.</description>
+                        <bitRange>[9:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+        </registers>
+    </peripheral>
+    <peripheral>
+        <name>TBMAN</name>
+        <description>Testbench manager. Allows the programmer to know what platform their software is running on.</description>
+        <baseAddress>0x4006c000</baseAddress>
+        <addressBlock>
+            <offset>0</offset>
+            <size>4</size>
+            <usage>registers</usage>
+        </addressBlock>
+        <registers>
+            <register>
+                <name>PLATFORM</name>
+                <addressOffset>0x00000000</addressOffset>
+                <description>Indicates the type of platform in use</description>
+                <resetValue>0x00000005</resetValue>
+                <fields>
+                    <field>
+                        <name>FPGA</name>
+                        <description>Indicates the platform is an FPGA</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>ASIC</name>
+                        <description>Indicates the platform is an ASIC</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+        </registers>
+    </peripheral>
+    <peripheral>
+        <name>VREG_AND_CHIP_RESET</name>
+        <description>control and status for on-chip voltage regulator and chip level reset subsystem</description>
+        <baseAddress>0x40064000</baseAddress>
+        <addressBlock>
+            <offset>0</offset>
+            <size>12</size>
+            <usage>registers</usage>
+        </addressBlock>
+        <registers>
+            <register>
+                <name>VREG</name>
+                <addressOffset>0x00000000</addressOffset>
+                <description>Voltage regulator control and status</description>
+                <resetValue>0x000000b1</resetValue>
+                <fields>
+                    <field>
+                        <name>ROK</name>
+                        <description>regulation status 
+                            0=not in regulation, 1=in regulation</description>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>VSEL</name>
+                        <description>output voltage select 
+                            0000 to 0101 - 0.80V 
+                            0110         - 0.85V 
+                            0111         - 0.90V 
+                            1000         - 0.95V 
+                            1001         - 1.00V 
+                            1010         - 1.05V 
+                            1011         - 1.10V (default) 
+                            1100         - 1.15V 
+                            1101         - 1.20V 
+                            1110         - 1.25V 
+                            1111         - 1.30V</description>
+                        <bitRange>[7:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>HIZ</name>
+                        <description>high impedance mode select 
+                            0=not in high impedance mode, 1=in high impedance mode</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>EN</name>
+                        <description>enable 
+                            0=not enabled, 1=enabled</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>BOD</name>
+                <addressOffset>0x00000004</addressOffset>
+                <description>brown-out detection control</description>
+                <resetValue>0x00000091</resetValue>
+                <fields>
+                    <field>
+                        <name>VSEL</name>
+                        <description>threshold select 
+                            0000 - 0.473V 
+                            0001 - 0.516V 
+                            0010 - 0.559V 
+                            0011 - 0.602V 
+                            0100 - 0.645V 
+                            0101 - 0.688V 
+                            0110 - 0.731V 
+                            0111 - 0.774V 
+                            1000 - 0.817V 
+                            1001 - 0.860V (default) 
+                            1010 - 0.903V 
+                            1011 - 0.946V 
+                            1100 - 0.989V 
+                            1101 - 1.032V 
+                            1110 - 1.075V 
+                            1111 - 1.118V</description>
+                        <bitRange>[7:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>EN</name>
+                        <description>enable 
+                            0=not enabled, 1=enabled</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CHIP_RESET</name>
+                <addressOffset>0x00000008</addressOffset>
+                <description>Chip reset control and status</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>PSM_RESTART_FLAG</name>
+                        <description>This is set by psm_restart from the debugger. 
+                            Its purpose is to branch bootcode to a safe mode when the debugger has issued a psm_restart in order to recover from a boot lock-up. 
+                            In the safe mode the debugger can repair the boot code, clear this flag then reboot the processor.</description>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>HAD_PSM_RESTART</name>
+                        <description>Last reset was from the debug port</description>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>HAD_RUN</name>
+                        <description>Last reset was from the RUN pin</description>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>HAD_POR</name>
+                        <description>Last reset was from the power-on reset or brown-out detection blocks</description>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+        </registers>
+    </peripheral>
+    <peripheral>
+        <name>RTC</name>
+        <description>Register block to control RTC</description>
+        <baseAddress>0x4005c000</baseAddress>
+        <addressBlock>
+            <offset>0</offset>
+            <size>48</size>
+            <usage>registers</usage>
+        </addressBlock>
+        <interrupt>
+            <name>RTC_IRQ</name>
+            <value>25</value>
+        </interrupt>
+        <registers>
+            <register>
+                <name>CLKDIV_M1</name>
+                <addressOffset>0x00000000</addressOffset>
+                <description>Divider minus 1 for the 1 second counter. Safe to change the value when RTC is not enabled.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CLKDIV_M1</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SETUP_0</name>
+                <addressOffset>0x00000004</addressOffset>
+                <description>RTC setup register 0</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>YEAR</name>
+                        <description>Year</description>
+                        <bitRange>[23:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>MONTH</name>
+                        <description>Month (1..12)</description>
+                        <bitRange>[11:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DAY</name>
+                        <description>Day of the month (1..31)</description>
+                        <bitRange>[4:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SETUP_1</name>
+                <addressOffset>0x00000008</addressOffset>
+                <description>RTC setup register 1</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>DOTW</name>
+                        <description>Day of the week: 1-Monday...0-Sunday ISO 8601 mod 7</description>
+                        <bitRange>[26:24]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>HOUR</name>
+                        <description>Hours</description>
+                        <bitRange>[20:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>MIN</name>
+                        <description>Minutes</description>
+                        <bitRange>[13:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SEC</name>
+                        <description>Seconds</description>
+                        <bitRange>[5:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CTRL</name>
+                <addressOffset>0x0000000c</addressOffset>
+                <description>RTC Control and status</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>FORCE_NOTLEAPYEAR</name>
+                        <description>If set, leapyear is forced off. 
+                            Useful for years divisible by 100 but not by 400</description>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LOAD</name>
+                        <description>Load RTC</description>
+                        <bitRange>[4:4]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>RTC_ACTIVE</name>
+                        <description>RTC enabled (running)</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>RTC_ENABLE</name>
+                        <description>Enable RTC</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>IRQ_SETUP_0</name>
+                <addressOffset>0x00000010</addressOffset>
+                <description>Interrupt setup register 0</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>MATCH_ACTIVE</name>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>MATCH_ENA</name>
+                        <description>Global match enable. Don&#39;t change any other value while this one is enabled</description>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>YEAR_ENA</name>
+                        <description>Enable year matching</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>MONTH_ENA</name>
+                        <description>Enable month matching</description>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DAY_ENA</name>
+                        <description>Enable day matching</description>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>YEAR</name>
+                        <description>Year</description>
+                        <bitRange>[23:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>MONTH</name>
+                        <description>Month (1..12)</description>
+                        <bitRange>[11:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DAY</name>
+                        <description>Day of the month (1..31)</description>
+                        <bitRange>[4:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>IRQ_SETUP_1</name>
+                <addressOffset>0x00000014</addressOffset>
+                <description>Interrupt setup register 1</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>DOTW_ENA</name>
+                        <description>Enable day of the week matching</description>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>HOUR_ENA</name>
+                        <description>Enable hour matching</description>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>MIN_ENA</name>
+                        <description>Enable minute matching</description>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SEC_ENA</name>
+                        <description>Enable second matching</description>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DOTW</name>
+                        <description>Day of the week</description>
+                        <bitRange>[26:24]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>HOUR</name>
+                        <description>Hours</description>
+                        <bitRange>[20:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>MIN</name>
+                        <description>Minutes</description>
+                        <bitRange>[13:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SEC</name>
+                        <description>Seconds</description>
+                        <bitRange>[5:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>RTC_1</name>
+                <addressOffset>0x00000018</addressOffset>
+                <description>RTC register 1.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>YEAR</name>
+                        <description>Year</description>
+                        <bitRange>[23:12]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>MONTH</name>
+                        <description>Month (1..12)</description>
+                        <bitRange>[11:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>DAY</name>
+                        <description>Day of the month (1..31)</description>
+                        <bitRange>[4:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>RTC_0</name>
+                <addressOffset>0x0000001c</addressOffset>
+                <description>RTC register 0 
+                    Read this before RTC 1!</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>DOTW</name>
+                        <description>Day of the week</description>
+                        <bitRange>[26:24]</bitRange>
+                        <access>read-only</access>
+                        <readAction>modify</readAction>
+                    </field>
+                    <field>
+                        <name>HOUR</name>
+                        <description>Hours</description>
+                        <bitRange>[20:16]</bitRange>
+                        <access>read-only</access>
+                        <readAction>modify</readAction>
+                    </field>
+                    <field>
+                        <name>MIN</name>
+                        <description>Minutes</description>
+                        <bitRange>[13:8]</bitRange>
+                        <access>read-only</access>
+                        <readAction>modify</readAction>
+                    </field>
+                    <field>
+                        <name>SEC</name>
+                        <description>Seconds</description>
+                        <bitRange>[5:0]</bitRange>
+                        <access>read-only</access>
+                        <readAction>modify</readAction>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INTR</name>
+                <addressOffset>0x00000020</addressOffset>
+                <description>Raw Interrupts</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>RTC</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INTE</name>
+                <addressOffset>0x00000024</addressOffset>
+                <description>Interrupt Enable</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>RTC</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INTF</name>
+                <addressOffset>0x00000028</addressOffset>
+                <description>Interrupt Force</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>RTC</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INTS</name>
+                <addressOffset>0x0000002c</addressOffset>
+                <description>Interrupt status after masking &amp; forcing</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>RTC</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+        </registers>
+    </peripheral>
+    <peripheral>
+      <name>SWI_IRQ</name>
+      <description>Virtual Peripheral to access unused NVIC software interrupts</description>
+      <baseAddress>0</baseAddress>
+      <registers></registers>
+      <interrupt>
+        <name>SWI_IRQ_0</name>
+        <value>26</value>
+      </interrupt>
+      <interrupt>
+        <name>SWI_IRQ_1</name>
+        <value>27</value>
+      </interrupt>
+      <interrupt>
+        <name>SWI_IRQ_2</name>
+        <value>28</value>
+      </interrupt>
+      <interrupt>
+        <name>SWI_IRQ_3</name>
+        <value>29</value>
+      </interrupt>
+      <interrupt>
+        <name>SWI_IRQ_4</name>
+        <value>30</value>
+      </interrupt>
+      <interrupt>
+        <name>SWI_IRQ_5</name>
+        <value>31</value>
+      </interrupt>
+    </peripheral>
+    </peripherals>
+</device>
diff --git a/svd/RP2350.svd b/svd/RP2350.svd
new file mode 100644
index 00000000..edab555a
--- /dev/null
+++ b/svd/RP2350.svd
@@ -0,0 +1,106183 @@
+<?xml version="1.0" encoding="utf-8"?>
+<!--
+Copyright (c) 2024 Raspberry Pi Ltd.
+
+SPDX-License-Identifier: BSD-3-Clause
+-->
+<device schemaVersion="1.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD.xsd">
+    <vendor>Raspberry Pi</vendor>
+    <name>RP2350</name>
+    <series>RP</series>
+    <version>0.1</version>
+    <description>
+        Dual Cortex-M33 or Hazard3 processors at 150MHz
+        520kB on-chip SRAM, in 10 independent banks
+        Extended low-power sleep states with optional SRAM retention: as low as 10uA DVDD
+        8kB of one-time-programmable storage (OTP)
+        Up to 16MB of external QSPI flash/PSRAM via dedicated QSPI bus
+            Additional 16MB flash/PSRAM accessible via optional second chip-select
+        On-chip switched-mode power supply to generate core voltage
+            Low-quiescent-current LDO mode can be enabled for sleep states
+        2x on-chip PLLs for internal or external clock generation
+        GPIOs are 5V-tolerant (powered), and 3.3V-failsafe (unpowered)
+        Security features:
+            Optional boot signing, enforced by on-chip mask ROM, with key fingerprint in OTP
+            Protected OTP storage for optional boot decryption key
+            Global bus filtering based on Arm or RISC-V security/privilege levels
+            Peripherals, GPIOs and DMA channels individually assignable to security domains
+            Hardware mitigations for fault injection attacks
+            Hardware SHA-256 accelerator
+        Peripherals:
+            2x UARTs
+            2x SPI controllers
+            2x I2C controllers
+            24x PWM channels
+            USB 1.1 controller and PHY, with host and device support
+            12x PIO state machines
+            1x HSTX peripheral
+    </description>
+    <width>32</width>
+    <size>32</size>
+    <resetMask>0xffffffff</resetMask>
+    <resetValue>0x00000000</resetValue>
+    <access>read-write</access>
+    <licenseText>
+        Copyright (c) 2024 Raspberry Pi Ltd.
+
+        SPDX-License-Identifier: BSD-3-Clause
+    </licenseText>
+    <cpu>
+        <name>CM33</name>
+        <revision>r1p0</revision>
+        <endian>little</endian>
+        <mpuPresent>true</mpuPresent>
+        <fpuPresent>true</fpuPresent>
+        <sauNumRegions>8</sauNumRegions>
+        <nvicPrioBits>4</nvicPrioBits>
+        <vtorPresent>1</vtorPresent>
+        <dspPresent>1</dspPresent>
+        <vendorSystickConfig>false</vendorSystickConfig>
+        <deviceNumInterrupts>52</deviceNumInterrupts>
+    </cpu>
+    <addressUnitBits>8</addressUnitBits>
+    <peripherals>
+    <peripheral>
+        <name>RESETS</name>
+        <baseAddress>0x40020000</baseAddress>
+        <addressBlock>
+            <offset>0</offset>
+            <size>12</size>
+            <usage>registers</usage>
+        </addressBlock>
+        <registers>
+            <register>
+                <name>RESET</name>
+                <addressOffset>0x00000000</addressOffset>
+                <resetValue>0x1fffffff</resetValue>
+                <fields>
+                    <field>
+                        <name>USBCTRL</name>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>UART1</name>
+                        <bitRange>[27:27]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>UART0</name>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>TRNG</name>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>TIMER1</name>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>TIMER0</name>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>TBMAN</name>
+                        <bitRange>[22:22]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SYSINFO</name>
+                        <bitRange>[21:21]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SYSCFG</name>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SPI1</name>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SPI0</name>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SHA256</name>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PWM</name>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PLL_USB</name>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PLL_SYS</name>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PIO2</name>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PIO1</name>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PIO0</name>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PADS_QSPI</name>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PADS_BANK0</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>JTAG</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>IO_QSPI</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>IO_BANK0</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>I2C1</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>I2C0</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>HSTX</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DMA</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>BUSCTRL</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ADC</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>WDSEL</name>
+                <addressOffset>0x00000004</addressOffset>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>USBCTRL</name>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>UART1</name>
+                        <bitRange>[27:27]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>UART0</name>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>TRNG</name>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>TIMER1</name>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>TIMER0</name>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>TBMAN</name>
+                        <bitRange>[22:22]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SYSINFO</name>
+                        <bitRange>[21:21]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SYSCFG</name>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SPI1</name>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SPI0</name>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SHA256</name>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PWM</name>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PLL_USB</name>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PLL_SYS</name>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PIO2</name>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PIO1</name>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PIO0</name>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PADS_QSPI</name>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PADS_BANK0</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>JTAG</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>IO_QSPI</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>IO_BANK0</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>I2C1</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>I2C0</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>HSTX</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DMA</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>BUSCTRL</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ADC</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>RESET_DONE</name>
+                <addressOffset>0x00000008</addressOffset>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>USBCTRL</name>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>UART1</name>
+                        <bitRange>[27:27]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>UART0</name>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>TRNG</name>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>TIMER1</name>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>TIMER0</name>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>TBMAN</name>
+                        <bitRange>[22:22]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SYSINFO</name>
+                        <bitRange>[21:21]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SYSCFG</name>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SPI1</name>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SPI0</name>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SHA256</name>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>PWM</name>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>PLL_USB</name>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>PLL_SYS</name>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>PIO2</name>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>PIO1</name>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>PIO0</name>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>PADS_QSPI</name>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>PADS_BANK0</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>JTAG</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>IO_QSPI</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>IO_BANK0</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>I2C1</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>I2C0</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>HSTX</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>DMA</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>BUSCTRL</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>ADC</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+        </registers>
+    </peripheral>
+    <peripheral>
+        <name>PSM</name>
+        <baseAddress>0x40018000</baseAddress>
+        <addressBlock>
+            <offset>0</offset>
+            <size>16</size>
+            <usage>registers</usage>
+        </addressBlock>
+        <registers>
+            <register>
+                <name>FRCE_ON</name>
+                <addressOffset>0x00000000</addressOffset>
+                <description>Force block out of reset (i.e. power it on)</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>PROC1</name>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PROC0</name>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ACCESSCTRL</name>
+                        <bitRange>[22:22]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SIO</name>
+                        <bitRange>[21:21]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>XIP</name>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SRAM9</name>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SRAM8</name>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SRAM7</name>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SRAM6</name>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SRAM5</name>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SRAM4</name>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SRAM3</name>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SRAM2</name>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SRAM1</name>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SRAM0</name>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>BOOTRAM</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ROM</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>BUSFABRIC</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PSM_READY</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLOCKS</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>RESETS</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>XOSC</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ROSC</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>OTP</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PROC_COLD</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>FRCE_OFF</name>
+                <addressOffset>0x00000004</addressOffset>
+                <description>Force into reset (i.e. power it off)</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>PROC1</name>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PROC0</name>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ACCESSCTRL</name>
+                        <bitRange>[22:22]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SIO</name>
+                        <bitRange>[21:21]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>XIP</name>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SRAM9</name>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SRAM8</name>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SRAM7</name>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SRAM6</name>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SRAM5</name>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SRAM4</name>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SRAM3</name>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SRAM2</name>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SRAM1</name>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SRAM0</name>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>BOOTRAM</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ROM</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>BUSFABRIC</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PSM_READY</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLOCKS</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>RESETS</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>XOSC</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ROSC</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>OTP</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PROC_COLD</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>WDSEL</name>
+                <addressOffset>0x00000008</addressOffset>
+                <description>Set to 1 if the watchdog should reset this</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>PROC1</name>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PROC0</name>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ACCESSCTRL</name>
+                        <bitRange>[22:22]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SIO</name>
+                        <bitRange>[21:21]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>XIP</name>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SRAM9</name>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SRAM8</name>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SRAM7</name>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SRAM6</name>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SRAM5</name>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SRAM4</name>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SRAM3</name>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SRAM2</name>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SRAM1</name>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SRAM0</name>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>BOOTRAM</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ROM</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>BUSFABRIC</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PSM_READY</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLOCKS</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>RESETS</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>XOSC</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ROSC</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>OTP</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PROC_COLD</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>DONE</name>
+                <addressOffset>0x0000000c</addressOffset>
+                <description>Is the subsystem ready?</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>PROC1</name>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>PROC0</name>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>ACCESSCTRL</name>
+                        <bitRange>[22:22]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SIO</name>
+                        <bitRange>[21:21]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>XIP</name>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SRAM9</name>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SRAM8</name>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SRAM7</name>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SRAM6</name>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SRAM5</name>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SRAM4</name>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SRAM3</name>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SRAM2</name>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SRAM1</name>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SRAM0</name>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>BOOTRAM</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>ROM</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>BUSFABRIC</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>PSM_READY</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CLOCKS</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>RESETS</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>XOSC</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>ROSC</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OTP</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>PROC_COLD</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+        </registers>
+    </peripheral>
+    <peripheral>
+        <name>CLOCKS</name>
+        <baseAddress>0x40010000</baseAddress>
+        <addressBlock>
+            <offset>0</offset>
+            <size>212</size>
+            <usage>registers</usage>
+        </addressBlock>
+        <interrupt>
+            <name>CLOCKS_IRQ</name>
+            <value>30</value>
+        </interrupt>
+        <registers>
+            <register>
+                <name>CLK_GPOUT0_CTRL</name>
+                <addressOffset>0x00000000</addressOffset>
+                <description>Clock control, can be changed on-the-fly (except for auxsrc)</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>ENABLED</name>
+                        <description>clock generator is enabled</description>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>NUDGE</name>
+                        <description>An edge on this signal shifts the phase of the output by 1 cycle of the input clock 
+                            This can be done at any time</description>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PHASE</name>
+                        <description>This delays the enable signal by up to 3 cycles of the input clock 
+                            This must be set before the clock is enabled to have any effect</description>
+                        <bitRange>[17:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DC50</name>
+                        <description>Enables duty cycle correction for odd divisors, can be changed on-the-fly</description>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ENABLE</name>
+                        <description>Starts and stops the clock generator cleanly</description>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>KILL</name>
+                        <description>Asynchronously kills the clock generator, enable must be set low before deasserting kill</description>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>AUXSRC</name>
+                        <description>Selects the auxiliary clock source, will glitch when switching</description>
+                        <bitRange>[8:5]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>clksrc_pll_sys</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>clksrc_gpin0</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>clksrc_gpin1</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>clksrc_pll_usb</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>clksrc_pll_usb_primary_ref_opcg</name>
+                                <value>4</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>rosc_clksrc</name>
+                                <value>5</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>xosc_clksrc</name>
+                                <value>6</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>lposc_clksrc</name>
+                                <value>7</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>clk_sys</name>
+                                <value>8</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>clk_usb</name>
+                                <value>9</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>clk_adc</name>
+                                <value>10</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>clk_ref</name>
+                                <value>11</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>clk_peri</name>
+                                <value>12</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>clk_hstx</name>
+                                <value>13</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>otp_clk2fc</name>
+                                <value>14</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CLK_GPOUT0_DIV</name>
+                <addressOffset>0x00000004</addressOffset>
+                <resetValue>0x00010000</resetValue>
+                <fields>
+                    <field>
+                        <name>INT</name>
+                        <description>Integer part of clock divisor, 0 -&gt; max+1, can be changed on-the-fly</description>
+                        <bitRange>[31:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>FRAC</name>
+                        <description>Fractional component of the divisor, can be changed on-the-fly</description>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CLK_GPOUT0_SELECTED</name>
+                <addressOffset>0x00000008</addressOffset>
+                <description>Indicates which src is currently selected (one-hot)</description>
+                <resetValue>0x00000001</resetValue>
+                <fields>
+                    <field>
+                        <name>CLK_GPOUT0_SELECTED</name>
+                        <description>This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1.</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CLK_GPOUT1_CTRL</name>
+                <addressOffset>0x0000000c</addressOffset>
+                <description>Clock control, can be changed on-the-fly (except for auxsrc)</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>ENABLED</name>
+                        <description>clock generator is enabled</description>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>NUDGE</name>
+                        <description>An edge on this signal shifts the phase of the output by 1 cycle of the input clock 
+                            This can be done at any time</description>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PHASE</name>
+                        <description>This delays the enable signal by up to 3 cycles of the input clock 
+                            This must be set before the clock is enabled to have any effect</description>
+                        <bitRange>[17:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DC50</name>
+                        <description>Enables duty cycle correction for odd divisors, can be changed on-the-fly</description>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ENABLE</name>
+                        <description>Starts and stops the clock generator cleanly</description>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>KILL</name>
+                        <description>Asynchronously kills the clock generator, enable must be set low before deasserting kill</description>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>AUXSRC</name>
+                        <description>Selects the auxiliary clock source, will glitch when switching</description>
+                        <bitRange>[8:5]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>clksrc_pll_sys</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>clksrc_gpin0</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>clksrc_gpin1</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>clksrc_pll_usb</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>clksrc_pll_usb_primary_ref_opcg</name>
+                                <value>4</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>rosc_clksrc</name>
+                                <value>5</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>xosc_clksrc</name>
+                                <value>6</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>lposc_clksrc</name>
+                                <value>7</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>clk_sys</name>
+                                <value>8</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>clk_usb</name>
+                                <value>9</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>clk_adc</name>
+                                <value>10</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>clk_ref</name>
+                                <value>11</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>clk_peri</name>
+                                <value>12</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>clk_hstx</name>
+                                <value>13</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>otp_clk2fc</name>
+                                <value>14</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CLK_GPOUT1_DIV</name>
+                <addressOffset>0x00000010</addressOffset>
+                <resetValue>0x00010000</resetValue>
+                <fields>
+                    <field>
+                        <name>INT</name>
+                        <description>Integer part of clock divisor, 0 -&gt; max+1, can be changed on-the-fly</description>
+                        <bitRange>[31:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>FRAC</name>
+                        <description>Fractional component of the divisor, can be changed on-the-fly</description>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CLK_GPOUT1_SELECTED</name>
+                <addressOffset>0x00000014</addressOffset>
+                <description>Indicates which src is currently selected (one-hot)</description>
+                <resetValue>0x00000001</resetValue>
+                <fields>
+                    <field>
+                        <name>CLK_GPOUT1_SELECTED</name>
+                        <description>This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1.</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CLK_GPOUT2_CTRL</name>
+                <addressOffset>0x00000018</addressOffset>
+                <description>Clock control, can be changed on-the-fly (except for auxsrc)</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>ENABLED</name>
+                        <description>clock generator is enabled</description>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>NUDGE</name>
+                        <description>An edge on this signal shifts the phase of the output by 1 cycle of the input clock 
+                            This can be done at any time</description>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PHASE</name>
+                        <description>This delays the enable signal by up to 3 cycles of the input clock 
+                            This must be set before the clock is enabled to have any effect</description>
+                        <bitRange>[17:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DC50</name>
+                        <description>Enables duty cycle correction for odd divisors, can be changed on-the-fly</description>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ENABLE</name>
+                        <description>Starts and stops the clock generator cleanly</description>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>KILL</name>
+                        <description>Asynchronously kills the clock generator, enable must be set low before deasserting kill</description>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>AUXSRC</name>
+                        <description>Selects the auxiliary clock source, will glitch when switching</description>
+                        <bitRange>[8:5]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>clksrc_pll_sys</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>clksrc_gpin0</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>clksrc_gpin1</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>clksrc_pll_usb</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>clksrc_pll_usb_primary_ref_opcg</name>
+                                <value>4</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>rosc_clksrc_ph</name>
+                                <value>5</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>xosc_clksrc</name>
+                                <value>6</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>lposc_clksrc</name>
+                                <value>7</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>clk_sys</name>
+                                <value>8</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>clk_usb</name>
+                                <value>9</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>clk_adc</name>
+                                <value>10</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>clk_ref</name>
+                                <value>11</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>clk_peri</name>
+                                <value>12</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>clk_hstx</name>
+                                <value>13</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>otp_clk2fc</name>
+                                <value>14</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CLK_GPOUT2_DIV</name>
+                <addressOffset>0x0000001c</addressOffset>
+                <resetValue>0x00010000</resetValue>
+                <fields>
+                    <field>
+                        <name>INT</name>
+                        <description>Integer part of clock divisor, 0 -&gt; max+1, can be changed on-the-fly</description>
+                        <bitRange>[31:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>FRAC</name>
+                        <description>Fractional component of the divisor, can be changed on-the-fly</description>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CLK_GPOUT2_SELECTED</name>
+                <addressOffset>0x00000020</addressOffset>
+                <description>Indicates which src is currently selected (one-hot)</description>
+                <resetValue>0x00000001</resetValue>
+                <fields>
+                    <field>
+                        <name>CLK_GPOUT2_SELECTED</name>
+                        <description>This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1.</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CLK_GPOUT3_CTRL</name>
+                <addressOffset>0x00000024</addressOffset>
+                <description>Clock control, can be changed on-the-fly (except for auxsrc)</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>ENABLED</name>
+                        <description>clock generator is enabled</description>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>NUDGE</name>
+                        <description>An edge on this signal shifts the phase of the output by 1 cycle of the input clock 
+                            This can be done at any time</description>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PHASE</name>
+                        <description>This delays the enable signal by up to 3 cycles of the input clock 
+                            This must be set before the clock is enabled to have any effect</description>
+                        <bitRange>[17:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DC50</name>
+                        <description>Enables duty cycle correction for odd divisors, can be changed on-the-fly</description>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ENABLE</name>
+                        <description>Starts and stops the clock generator cleanly</description>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>KILL</name>
+                        <description>Asynchronously kills the clock generator, enable must be set low before deasserting kill</description>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>AUXSRC</name>
+                        <description>Selects the auxiliary clock source, will glitch when switching</description>
+                        <bitRange>[8:5]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>clksrc_pll_sys</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>clksrc_gpin0</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>clksrc_gpin1</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>clksrc_pll_usb</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>clksrc_pll_usb_primary_ref_opcg</name>
+                                <value>4</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>rosc_clksrc_ph</name>
+                                <value>5</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>xosc_clksrc</name>
+                                <value>6</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>lposc_clksrc</name>
+                                <value>7</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>clk_sys</name>
+                                <value>8</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>clk_usb</name>
+                                <value>9</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>clk_adc</name>
+                                <value>10</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>clk_ref</name>
+                                <value>11</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>clk_peri</name>
+                                <value>12</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>clk_hstx</name>
+                                <value>13</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>otp_clk2fc</name>
+                                <value>14</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CLK_GPOUT3_DIV</name>
+                <addressOffset>0x00000028</addressOffset>
+                <resetValue>0x00010000</resetValue>
+                <fields>
+                    <field>
+                        <name>INT</name>
+                        <description>Integer part of clock divisor, 0 -&gt; max+1, can be changed on-the-fly</description>
+                        <bitRange>[31:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>FRAC</name>
+                        <description>Fractional component of the divisor, can be changed on-the-fly</description>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CLK_GPOUT3_SELECTED</name>
+                <addressOffset>0x0000002c</addressOffset>
+                <description>Indicates which src is currently selected (one-hot)</description>
+                <resetValue>0x00000001</resetValue>
+                <fields>
+                    <field>
+                        <name>CLK_GPOUT3_SELECTED</name>
+                        <description>This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1.</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CLK_REF_CTRL</name>
+                <addressOffset>0x00000030</addressOffset>
+                <description>Clock control, can be changed on-the-fly (except for auxsrc)</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>AUXSRC</name>
+                        <description>Selects the auxiliary clock source, will glitch when switching</description>
+                        <bitRange>[6:5]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>clksrc_pll_usb</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>clksrc_gpin0</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>clksrc_gpin1</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>clksrc_pll_usb_primary_ref_opcg</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>SRC</name>
+                        <description>Selects the clock source glitchlessly, can be changed on-the-fly</description>
+                        <bitRange>[1:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>rosc_clksrc_ph</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>clksrc_clk_ref_aux</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>xosc_clksrc</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>lposc_clksrc</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CLK_REF_DIV</name>
+                <addressOffset>0x00000034</addressOffset>
+                <resetValue>0x00010000</resetValue>
+                <fields>
+                    <field>
+                        <name>INT</name>
+                        <description>Integer part of clock divisor, 0 -&gt; max+1, can be changed on-the-fly</description>
+                        <bitRange>[23:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CLK_REF_SELECTED</name>
+                <addressOffset>0x00000038</addressOffset>
+                <description>Indicates which src is currently selected (one-hot)</description>
+                <resetValue>0x00000001</resetValue>
+                <fields>
+                    <field>
+                        <name>CLK_REF_SELECTED</name>
+                        <description>The glitchless multiplexer does not switch instantaneously (to avoid glitches), so software should poll this register to wait for the switch to complete. This register contains one decoded bit for each of the clock sources enumerated in the CTRL SRC field. At most one of these bits will be set at any time, indicating that clock is currently present at the output of the glitchless mux. Whilst switching is in progress, this register may briefly show all-0s.</description>
+                        <bitRange>[3:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CLK_SYS_CTRL</name>
+                <addressOffset>0x0000003c</addressOffset>
+                <description>Clock control, can be changed on-the-fly (except for auxsrc)</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>AUXSRC</name>
+                        <description>Selects the auxiliary clock source, will glitch when switching</description>
+                        <bitRange>[7:5]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>clksrc_pll_sys</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>clksrc_pll_usb</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>rosc_clksrc</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>xosc_clksrc</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>clksrc_gpin0</name>
+                                <value>4</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>clksrc_gpin1</name>
+                                <value>5</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>SRC</name>
+                        <description>Selects the clock source glitchlessly, can be changed on-the-fly</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>clk_ref</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>clksrc_clk_sys_aux</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CLK_SYS_DIV</name>
+                <addressOffset>0x00000040</addressOffset>
+                <resetValue>0x00010000</resetValue>
+                <fields>
+                    <field>
+                        <name>INT</name>
+                        <description>Integer part of clock divisor, 0 -&gt; max+1, can be changed on-the-fly</description>
+                        <bitRange>[31:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>FRAC</name>
+                        <description>Fractional component of the divisor, can be changed on-the-fly</description>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CLK_SYS_SELECTED</name>
+                <addressOffset>0x00000044</addressOffset>
+                <description>Indicates which src is currently selected (one-hot)</description>
+                <resetValue>0x00000001</resetValue>
+                <fields>
+                    <field>
+                        <name>CLK_SYS_SELECTED</name>
+                        <description>The glitchless multiplexer does not switch instantaneously (to avoid glitches), so software should poll this register to wait for the switch to complete. This register contains one decoded bit for each of the clock sources enumerated in the CTRL SRC field. At most one of these bits will be set at any time, indicating that clock is currently present at the output of the glitchless mux. Whilst switching is in progress, this register may briefly show all-0s.</description>
+                        <bitRange>[1:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CLK_PERI_CTRL</name>
+                <addressOffset>0x00000048</addressOffset>
+                <description>Clock control, can be changed on-the-fly (except for auxsrc)</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>ENABLED</name>
+                        <description>clock generator is enabled</description>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>ENABLE</name>
+                        <description>Starts and stops the clock generator cleanly</description>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>KILL</name>
+                        <description>Asynchronously kills the clock generator, enable must be set low before deasserting kill</description>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>AUXSRC</name>
+                        <description>Selects the auxiliary clock source, will glitch when switching</description>
+                        <bitRange>[7:5]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>clk_sys</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>clksrc_pll_sys</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>clksrc_pll_usb</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>rosc_clksrc_ph</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>xosc_clksrc</name>
+                                <value>4</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>clksrc_gpin0</name>
+                                <value>5</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>clksrc_gpin1</name>
+                                <value>6</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CLK_PERI_DIV</name>
+                <addressOffset>0x0000004c</addressOffset>
+                <resetValue>0x00010000</resetValue>
+                <fields>
+                    <field>
+                        <name>INT</name>
+                        <description>Integer part of clock divisor, 0 -&gt; max+1, can be changed on-the-fly</description>
+                        <bitRange>[17:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CLK_PERI_SELECTED</name>
+                <addressOffset>0x00000050</addressOffset>
+                <description>Indicates which src is currently selected (one-hot)</description>
+                <resetValue>0x00000001</resetValue>
+                <fields>
+                    <field>
+                        <name>CLK_PERI_SELECTED</name>
+                        <description>This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1.</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CLK_HSTX_CTRL</name>
+                <addressOffset>0x00000054</addressOffset>
+                <description>Clock control, can be changed on-the-fly (except for auxsrc)</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>ENABLED</name>
+                        <description>clock generator is enabled</description>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>NUDGE</name>
+                        <description>An edge on this signal shifts the phase of the output by 1 cycle of the input clock 
+                            This can be done at any time</description>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PHASE</name>
+                        <description>This delays the enable signal by up to 3 cycles of the input clock 
+                            This must be set before the clock is enabled to have any effect</description>
+                        <bitRange>[17:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ENABLE</name>
+                        <description>Starts and stops the clock generator cleanly</description>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>KILL</name>
+                        <description>Asynchronously kills the clock generator, enable must be set low before deasserting kill</description>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>AUXSRC</name>
+                        <description>Selects the auxiliary clock source, will glitch when switching</description>
+                        <bitRange>[7:5]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>clk_sys</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>clksrc_pll_sys</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>clksrc_pll_usb</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>clksrc_gpin0</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>clksrc_gpin1</name>
+                                <value>4</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CLK_HSTX_DIV</name>
+                <addressOffset>0x00000058</addressOffset>
+                <resetValue>0x00010000</resetValue>
+                <fields>
+                    <field>
+                        <name>INT</name>
+                        <description>Integer part of clock divisor, 0 -&gt; max+1, can be changed on-the-fly</description>
+                        <bitRange>[17:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CLK_HSTX_SELECTED</name>
+                <addressOffset>0x0000005c</addressOffset>
+                <description>Indicates which src is currently selected (one-hot)</description>
+                <resetValue>0x00000001</resetValue>
+                <fields>
+                    <field>
+                        <name>CLK_HSTX_SELECTED</name>
+                        <description>This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1.</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CLK_USB_CTRL</name>
+                <addressOffset>0x00000060</addressOffset>
+                <description>Clock control, can be changed on-the-fly (except for auxsrc)</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>ENABLED</name>
+                        <description>clock generator is enabled</description>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>NUDGE</name>
+                        <description>An edge on this signal shifts the phase of the output by 1 cycle of the input clock 
+                            This can be done at any time</description>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PHASE</name>
+                        <description>This delays the enable signal by up to 3 cycles of the input clock 
+                            This must be set before the clock is enabled to have any effect</description>
+                        <bitRange>[17:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ENABLE</name>
+                        <description>Starts and stops the clock generator cleanly</description>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>KILL</name>
+                        <description>Asynchronously kills the clock generator, enable must be set low before deasserting kill</description>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>AUXSRC</name>
+                        <description>Selects the auxiliary clock source, will glitch when switching</description>
+                        <bitRange>[7:5]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>clksrc_pll_usb</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>clksrc_pll_sys</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>rosc_clksrc_ph</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>xosc_clksrc</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>clksrc_gpin0</name>
+                                <value>4</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>clksrc_gpin1</name>
+                                <value>5</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CLK_USB_DIV</name>
+                <addressOffset>0x00000064</addressOffset>
+                <resetValue>0x00010000</resetValue>
+                <fields>
+                    <field>
+                        <name>INT</name>
+                        <description>Integer part of clock divisor, 0 -&gt; max+1, can be changed on-the-fly</description>
+                        <bitRange>[19:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CLK_USB_SELECTED</name>
+                <addressOffset>0x00000068</addressOffset>
+                <description>Indicates which src is currently selected (one-hot)</description>
+                <resetValue>0x00000001</resetValue>
+                <fields>
+                    <field>
+                        <name>CLK_USB_SELECTED</name>
+                        <description>This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1.</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CLK_ADC_CTRL</name>
+                <addressOffset>0x0000006c</addressOffset>
+                <description>Clock control, can be changed on-the-fly (except for auxsrc)</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>ENABLED</name>
+                        <description>clock generator is enabled</description>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>NUDGE</name>
+                        <description>An edge on this signal shifts the phase of the output by 1 cycle of the input clock 
+                            This can be done at any time</description>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PHASE</name>
+                        <description>This delays the enable signal by up to 3 cycles of the input clock 
+                            This must be set before the clock is enabled to have any effect</description>
+                        <bitRange>[17:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ENABLE</name>
+                        <description>Starts and stops the clock generator cleanly</description>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>KILL</name>
+                        <description>Asynchronously kills the clock generator, enable must be set low before deasserting kill</description>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>AUXSRC</name>
+                        <description>Selects the auxiliary clock source, will glitch when switching</description>
+                        <bitRange>[7:5]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>clksrc_pll_usb</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>clksrc_pll_sys</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>rosc_clksrc_ph</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>xosc_clksrc</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>clksrc_gpin0</name>
+                                <value>4</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>clksrc_gpin1</name>
+                                <value>5</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CLK_ADC_DIV</name>
+                <addressOffset>0x00000070</addressOffset>
+                <resetValue>0x00010000</resetValue>
+                <fields>
+                    <field>
+                        <name>INT</name>
+                        <description>Integer part of clock divisor, 0 -&gt; max+1, can be changed on-the-fly</description>
+                        <bitRange>[19:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CLK_ADC_SELECTED</name>
+                <addressOffset>0x00000074</addressOffset>
+                <description>Indicates which src is currently selected (one-hot)</description>
+                <resetValue>0x00000001</resetValue>
+                <fields>
+                    <field>
+                        <name>CLK_ADC_SELECTED</name>
+                        <description>This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1.</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>DFTCLK_XOSC_CTRL</name>
+                <addressOffset>0x00000078</addressOffset>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>SRC</name>
+                        <bitRange>[1:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NULL</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>clksrc_pll_usb_primary</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>clksrc_gpin0</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>DFTCLK_ROSC_CTRL</name>
+                <addressOffset>0x0000007c</addressOffset>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>SRC</name>
+                        <bitRange>[1:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NULL</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>clksrc_pll_sys_primary_rosc</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>clksrc_gpin1</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>DFTCLK_LPOSC_CTRL</name>
+                <addressOffset>0x00000080</addressOffset>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>SRC</name>
+                        <bitRange>[1:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NULL</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>clksrc_pll_usb_primary_lposc</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>clksrc_gpin1</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CLK_SYS_RESUS_CTRL</name>
+                <addressOffset>0x00000084</addressOffset>
+                <resetValue>0x000000ff</resetValue>
+                <fields>
+                    <field>
+                        <name>CLEAR</name>
+                        <description>For clearing the resus after the fault that triggered it has been corrected</description>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>FRCE</name>
+                        <description>Force a resus, for test purposes only</description>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ENABLE</name>
+                        <description>Enable resus</description>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>TIMEOUT</name>
+                        <description>This is expressed as a number of clk_ref cycles 
+                            and must be &gt;= 2x clk_ref_freq/min_clk_tst_freq</description>
+                        <bitRange>[7:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CLK_SYS_RESUS_STATUS</name>
+                <addressOffset>0x00000088</addressOffset>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>RESUSSED</name>
+                        <description>Clock has been resuscitated, correct the error then send ctrl_clear=1</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>FC0_REF_KHZ</name>
+                <addressOffset>0x0000008c</addressOffset>
+                <description>Reference clock frequency in kHz</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>FC0_REF_KHZ</name>
+                        <bitRange>[19:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>FC0_MIN_KHZ</name>
+                <addressOffset>0x00000090</addressOffset>
+                <description>Minimum pass frequency in kHz. This is optional. Set to 0 if you are not using the pass/fail flags</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>FC0_MIN_KHZ</name>
+                        <bitRange>[24:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>FC0_MAX_KHZ</name>
+                <addressOffset>0x00000094</addressOffset>
+                <description>Maximum pass frequency in kHz. This is optional. Set to 0x1ffffff if you are not using the pass/fail flags</description>
+                <resetValue>0x01ffffff</resetValue>
+                <fields>
+                    <field>
+                        <name>FC0_MAX_KHZ</name>
+                        <bitRange>[24:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>FC0_DELAY</name>
+                <addressOffset>0x00000098</addressOffset>
+                <description>Delays the start of frequency counting to allow the mux to settle 
+                    Delay is measured in multiples of the reference clock period</description>
+                <resetValue>0x00000001</resetValue>
+                <fields>
+                    <field>
+                        <name>FC0_DELAY</name>
+                        <bitRange>[2:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>FC0_INTERVAL</name>
+                <addressOffset>0x0000009c</addressOffset>
+                <description>The test interval is 0.98us * 2**interval, but let&#39;s call it 1us * 2**interval 
+                    The default gives a test interval of 250us</description>
+                <resetValue>0x00000008</resetValue>
+                <fields>
+                    <field>
+                        <name>FC0_INTERVAL</name>
+                        <bitRange>[3:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>FC0_SRC</name>
+                <addressOffset>0x000000a0</addressOffset>
+                <description>Clock sent to frequency counter, set to 0 when not required 
+                    Writing to this register initiates the frequency count</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>FC0_SRC</name>
+                        <bitRange>[7:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NULL</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pll_sys_clksrc_primary</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pll_usb_clksrc_primary</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>rosc_clksrc</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>rosc_clksrc_ph</name>
+                                <value>4</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>xosc_clksrc</name>
+                                <value>5</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>clksrc_gpin0</name>
+                                <value>6</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>clksrc_gpin1</name>
+                                <value>7</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>clk_ref</name>
+                                <value>8</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>clk_sys</name>
+                                <value>9</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>clk_peri</name>
+                                <value>10</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>clk_usb</name>
+                                <value>11</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>clk_adc</name>
+                                <value>12</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>clk_hstx</name>
+                                <value>13</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>lposc_clksrc</name>
+                                <value>14</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>otp_clk2fc</name>
+                                <value>15</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pll_usb_clksrc_primary_dft</name>
+                                <value>16</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>FC0_STATUS</name>
+                <addressOffset>0x000000a4</addressOffset>
+                <description>Frequency counter status</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>DIED</name>
+                        <description>Test clock stopped during test</description>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>FAST</name>
+                        <description>Test clock faster than expected, only valid when status_done=1</description>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SLOW</name>
+                        <description>Test clock slower than expected, only valid when status_done=1</description>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>FAIL</name>
+                        <description>Test failed</description>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>WAITING</name>
+                        <description>Waiting for test clock to start</description>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>RUNNING</name>
+                        <description>Test running</description>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>DONE</name>
+                        <description>Test complete</description>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>PASS</name>
+                        <description>Test passed</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>FC0_RESULT</name>
+                <addressOffset>0x000000a8</addressOffset>
+                <description>Result of frequency measurement, only valid when status_done=1</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>KHZ</name>
+                        <bitRange>[29:5]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>FRAC</name>
+                        <bitRange>[4:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>WAKE_EN0</name>
+                <addressOffset>0x000000ac</addressOffset>
+                <description>enable clock in wake mode</description>
+                <resetValue>0xffffffff</resetValue>
+                <fields>
+                    <field>
+                        <name>CLK_SYS_SIO</name>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_SHA256</name>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_PSM</name>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_ROSC</name>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_ROM</name>
+                        <bitRange>[27:27]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_RESETS</name>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_PWM</name>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_POWMAN</name>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_REF_POWMAN</name>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_PLL_USB</name>
+                        <bitRange>[22:22]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_PLL_SYS</name>
+                        <bitRange>[21:21]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_PIO2</name>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_PIO1</name>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_PIO0</name>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_PADS</name>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_OTP</name>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_REF_OTP</name>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_JTAG</name>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_IO</name>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_I2C1</name>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_I2C0</name>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_HSTX</name>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_HSTX</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_GLITCH_DETECTOR</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_DMA</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_BUSFABRIC</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_BUSCTRL</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_BOOTRAM</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_ADC</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_ADC</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_ACCESSCTRL</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_CLOCKS</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>WAKE_EN1</name>
+                <addressOffset>0x000000b0</addressOffset>
+                <description>enable clock in wake mode</description>
+                <resetValue>0x7fffffff</resetValue>
+                <fields>
+                    <field>
+                        <name>CLK_SYS_XOSC</name>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_XIP</name>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_WATCHDOG</name>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_USB</name>
+                        <bitRange>[27:27]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_USBCTRL</name>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_UART1</name>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_PERI_UART1</name>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_UART0</name>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_PERI_UART0</name>
+                        <bitRange>[22:22]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_TRNG</name>
+                        <bitRange>[21:21]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_TIMER1</name>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_TIMER0</name>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_TICKS</name>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_REF_TICKS</name>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_TBMAN</name>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_SYSINFO</name>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_SYSCFG</name>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_SRAM9</name>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_SRAM8</name>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_SRAM7</name>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_SRAM6</name>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_SRAM5</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_SRAM4</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_SRAM3</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_SRAM2</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_SRAM1</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_SRAM0</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_SPI1</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_PERI_SPI1</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_SPI0</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_PERI_SPI0</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SLEEP_EN0</name>
+                <addressOffset>0x000000b4</addressOffset>
+                <description>enable clock in sleep mode</description>
+                <resetValue>0xffffffff</resetValue>
+                <fields>
+                    <field>
+                        <name>CLK_SYS_SIO</name>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_SHA256</name>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_PSM</name>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_ROSC</name>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_ROM</name>
+                        <bitRange>[27:27]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_RESETS</name>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_PWM</name>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_POWMAN</name>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_REF_POWMAN</name>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_PLL_USB</name>
+                        <bitRange>[22:22]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_PLL_SYS</name>
+                        <bitRange>[21:21]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_PIO2</name>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_PIO1</name>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_PIO0</name>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_PADS</name>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_OTP</name>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_REF_OTP</name>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_JTAG</name>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_IO</name>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_I2C1</name>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_I2C0</name>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_HSTX</name>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_HSTX</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_GLITCH_DETECTOR</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_DMA</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_BUSFABRIC</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_BUSCTRL</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_BOOTRAM</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_ADC</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_ADC</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_ACCESSCTRL</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_CLOCKS</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SLEEP_EN1</name>
+                <addressOffset>0x000000b8</addressOffset>
+                <description>enable clock in sleep mode</description>
+                <resetValue>0x7fffffff</resetValue>
+                <fields>
+                    <field>
+                        <name>CLK_SYS_XOSC</name>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_XIP</name>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_WATCHDOG</name>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_USB</name>
+                        <bitRange>[27:27]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_USBCTRL</name>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_UART1</name>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_PERI_UART1</name>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_UART0</name>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_PERI_UART0</name>
+                        <bitRange>[22:22]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_TRNG</name>
+                        <bitRange>[21:21]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_TIMER1</name>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_TIMER0</name>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_TICKS</name>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_REF_TICKS</name>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_TBMAN</name>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_SYSINFO</name>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_SYSCFG</name>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_SRAM9</name>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_SRAM8</name>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_SRAM7</name>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_SRAM6</name>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_SRAM5</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_SRAM4</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_SRAM3</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_SRAM2</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_SRAM1</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_SRAM0</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_SPI1</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_PERI_SPI1</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_SPI0</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLK_PERI_SPI0</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>ENABLED0</name>
+                <addressOffset>0x000000bc</addressOffset>
+                <description>indicates the state of the clock enable</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CLK_SYS_SIO</name>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_SHA256</name>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_PSM</name>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_ROSC</name>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_ROM</name>
+                        <bitRange>[27:27]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_RESETS</name>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_PWM</name>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_POWMAN</name>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CLK_REF_POWMAN</name>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_PLL_USB</name>
+                        <bitRange>[22:22]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_PLL_SYS</name>
+                        <bitRange>[21:21]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_PIO2</name>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_PIO1</name>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_PIO0</name>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_PADS</name>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_OTP</name>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CLK_REF_OTP</name>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_JTAG</name>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_IO</name>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_I2C1</name>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_I2C0</name>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_HSTX</name>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CLK_HSTX</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_GLITCH_DETECTOR</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_DMA</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_BUSFABRIC</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_BUSCTRL</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_BOOTRAM</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_ADC</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CLK_ADC</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_ACCESSCTRL</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_CLOCKS</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>ENABLED1</name>
+                <addressOffset>0x000000c0</addressOffset>
+                <description>indicates the state of the clock enable</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CLK_SYS_XOSC</name>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_XIP</name>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_WATCHDOG</name>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CLK_USB</name>
+                        <bitRange>[27:27]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_USBCTRL</name>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_UART1</name>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CLK_PERI_UART1</name>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_UART0</name>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CLK_PERI_UART0</name>
+                        <bitRange>[22:22]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_TRNG</name>
+                        <bitRange>[21:21]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_TIMER1</name>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_TIMER0</name>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_TICKS</name>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CLK_REF_TICKS</name>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_TBMAN</name>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_SYSINFO</name>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_SYSCFG</name>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_SRAM9</name>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_SRAM8</name>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_SRAM7</name>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_SRAM6</name>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_SRAM5</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_SRAM4</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_SRAM3</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_SRAM2</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_SRAM1</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_SRAM0</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_SPI1</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CLK_PERI_SPI1</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CLK_SYS_SPI0</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CLK_PERI_SPI0</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INTR</name>
+                <addressOffset>0x000000c4</addressOffset>
+                <description>Raw Interrupts</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CLK_SYS_RESUS</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INTE</name>
+                <addressOffset>0x000000c8</addressOffset>
+                <description>Interrupt Enable</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CLK_SYS_RESUS</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INTF</name>
+                <addressOffset>0x000000cc</addressOffset>
+                <description>Interrupt Force</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CLK_SYS_RESUS</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INTS</name>
+                <addressOffset>0x000000d0</addressOffset>
+                <description>Interrupt status after masking &amp; forcing</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CLK_SYS_RESUS</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+        </registers>
+    </peripheral>
+    <peripheral>
+        <name>TICKS</name>
+        <baseAddress>0x40108000</baseAddress>
+        <addressBlock>
+            <offset>0</offset>
+            <size>72</size>
+            <usage>registers</usage>
+        </addressBlock>
+        <registers>
+            <register>
+                <name>PROC0_CTRL</name>
+                <addressOffset>0x00000000</addressOffset>
+                <description>Controls the tick generator</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>RUNNING</name>
+                        <description>Is the tick generator running?</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>ENABLE</name>
+                        <description>start / stop tick generation</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PROC0_CYCLES</name>
+                <addressOffset>0x00000004</addressOffset>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>PROC0_CYCLES</name>
+                        <description>Total number of clk_tick cycles before the next tick.</description>
+                        <bitRange>[8:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PROC0_COUNT</name>
+                <addressOffset>0x00000008</addressOffset>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>PROC0_COUNT</name>
+                        <description>Count down timer: the remaining number clk_tick cycles before the next tick is generated.</description>
+                        <bitRange>[8:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PROC1_CTRL</name>
+                <addressOffset>0x0000000c</addressOffset>
+                <description>Controls the tick generator</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>RUNNING</name>
+                        <description>Is the tick generator running?</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>ENABLE</name>
+                        <description>start / stop tick generation</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PROC1_CYCLES</name>
+                <addressOffset>0x00000010</addressOffset>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>PROC1_CYCLES</name>
+                        <description>Total number of clk_tick cycles before the next tick.</description>
+                        <bitRange>[8:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PROC1_COUNT</name>
+                <addressOffset>0x00000014</addressOffset>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>PROC1_COUNT</name>
+                        <description>Count down timer: the remaining number clk_tick cycles before the next tick is generated.</description>
+                        <bitRange>[8:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>TIMER0_CTRL</name>
+                <addressOffset>0x00000018</addressOffset>
+                <description>Controls the tick generator</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>RUNNING</name>
+                        <description>Is the tick generator running?</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>ENABLE</name>
+                        <description>start / stop tick generation</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>TIMER0_CYCLES</name>
+                <addressOffset>0x0000001c</addressOffset>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>TIMER0_CYCLES</name>
+                        <description>Total number of clk_tick cycles before the next tick.</description>
+                        <bitRange>[8:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>TIMER0_COUNT</name>
+                <addressOffset>0x00000020</addressOffset>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>TIMER0_COUNT</name>
+                        <description>Count down timer: the remaining number clk_tick cycles before the next tick is generated.</description>
+                        <bitRange>[8:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>TIMER1_CTRL</name>
+                <addressOffset>0x00000024</addressOffset>
+                <description>Controls the tick generator</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>RUNNING</name>
+                        <description>Is the tick generator running?</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>ENABLE</name>
+                        <description>start / stop tick generation</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>TIMER1_CYCLES</name>
+                <addressOffset>0x00000028</addressOffset>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>TIMER1_CYCLES</name>
+                        <description>Total number of clk_tick cycles before the next tick.</description>
+                        <bitRange>[8:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>TIMER1_COUNT</name>
+                <addressOffset>0x0000002c</addressOffset>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>TIMER1_COUNT</name>
+                        <description>Count down timer: the remaining number clk_tick cycles before the next tick is generated.</description>
+                        <bitRange>[8:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>WATCHDOG_CTRL</name>
+                <addressOffset>0x00000030</addressOffset>
+                <description>Controls the tick generator</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>RUNNING</name>
+                        <description>Is the tick generator running?</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>ENABLE</name>
+                        <description>start / stop tick generation</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>WATCHDOG_CYCLES</name>
+                <addressOffset>0x00000034</addressOffset>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>WATCHDOG_CYCLES</name>
+                        <description>Total number of clk_tick cycles before the next tick.</description>
+                        <bitRange>[8:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>WATCHDOG_COUNT</name>
+                <addressOffset>0x00000038</addressOffset>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>WATCHDOG_COUNT</name>
+                        <description>Count down timer: the remaining number clk_tick cycles before the next tick is generated.</description>
+                        <bitRange>[8:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>RISCV_CTRL</name>
+                <addressOffset>0x0000003c</addressOffset>
+                <description>Controls the tick generator</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>RUNNING</name>
+                        <description>Is the tick generator running?</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>ENABLE</name>
+                        <description>start / stop tick generation</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>RISCV_CYCLES</name>
+                <addressOffset>0x00000040</addressOffset>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>RISCV_CYCLES</name>
+                        <description>Total number of clk_tick cycles before the next tick.</description>
+                        <bitRange>[8:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>RISCV_COUNT</name>
+                <addressOffset>0x00000044</addressOffset>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>RISCV_COUNT</name>
+                        <description>Count down timer: the remaining number clk_tick cycles before the next tick is generated.</description>
+                        <bitRange>[8:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+        </registers>
+    </peripheral>
+    <peripheral>
+        <name>PADS_BANK0</name>
+        <baseAddress>0x40038000</baseAddress>
+        <addressBlock>
+            <offset>0</offset>
+            <size>204</size>
+            <usage>registers</usage>
+        </addressBlock>
+        <registers>
+            <register>
+                <name>VOLTAGE_SELECT</name>
+                <addressOffset>0x00000000</addressOffset>
+                <description>Voltage select. Per bank control</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>VOLTAGE_SELECT</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>3v3</name>
+                                <value>0</value>
+                                <description>Set voltage to 3.3V (DVDD &gt;= 2V5)</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>1v8</name>
+                                <value>1</value>
+                                <description>Set voltage to 1.8V (DVDD &lt;= 1V8)</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO0</name>
+                <addressOffset>0x00000004</addressOffset>
+                <resetValue>0x00000116</resetValue>
+                <fields>
+                    <field>
+                        <name>ISO</name>
+                        <description>Pad isolation control. Remove this once the pad is configured by software.</description>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>OD</name>
+                        <description>Output disable. Has priority over output enable from peripherals</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>IE</name>
+                        <description>Input enable</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DRIVE</name>
+                        <description>Drive strength.</description>
+                        <bitRange>[5:4]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>2mA</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>4mA</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>8mA</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>12mA</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>PUE</name>
+                        <description>Pull up enable</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PDE</name>
+                        <description>Pull down enable</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SCHMITT</name>
+                        <description>Enable schmitt trigger</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SLEWFAST</name>
+                        <description>Slew rate control. 1 = Fast, 0 = Slow</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO1</name>
+                <addressOffset>0x00000008</addressOffset>
+                <resetValue>0x00000116</resetValue>
+                <fields>
+                    <field>
+                        <name>ISO</name>
+                        <description>Pad isolation control. Remove this once the pad is configured by software.</description>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>OD</name>
+                        <description>Output disable. Has priority over output enable from peripherals</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>IE</name>
+                        <description>Input enable</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DRIVE</name>
+                        <description>Drive strength.</description>
+                        <bitRange>[5:4]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>2mA</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>4mA</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>8mA</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>12mA</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>PUE</name>
+                        <description>Pull up enable</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PDE</name>
+                        <description>Pull down enable</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SCHMITT</name>
+                        <description>Enable schmitt trigger</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SLEWFAST</name>
+                        <description>Slew rate control. 1 = Fast, 0 = Slow</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO2</name>
+                <addressOffset>0x0000000c</addressOffset>
+                <resetValue>0x00000116</resetValue>
+                <fields>
+                    <field>
+                        <name>ISO</name>
+                        <description>Pad isolation control. Remove this once the pad is configured by software.</description>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>OD</name>
+                        <description>Output disable. Has priority over output enable from peripherals</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>IE</name>
+                        <description>Input enable</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DRIVE</name>
+                        <description>Drive strength.</description>
+                        <bitRange>[5:4]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>2mA</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>4mA</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>8mA</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>12mA</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>PUE</name>
+                        <description>Pull up enable</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PDE</name>
+                        <description>Pull down enable</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SCHMITT</name>
+                        <description>Enable schmitt trigger</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SLEWFAST</name>
+                        <description>Slew rate control. 1 = Fast, 0 = Slow</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO3</name>
+                <addressOffset>0x00000010</addressOffset>
+                <resetValue>0x00000116</resetValue>
+                <fields>
+                    <field>
+                        <name>ISO</name>
+                        <description>Pad isolation control. Remove this once the pad is configured by software.</description>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>OD</name>
+                        <description>Output disable. Has priority over output enable from peripherals</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>IE</name>
+                        <description>Input enable</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DRIVE</name>
+                        <description>Drive strength.</description>
+                        <bitRange>[5:4]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>2mA</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>4mA</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>8mA</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>12mA</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>PUE</name>
+                        <description>Pull up enable</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PDE</name>
+                        <description>Pull down enable</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SCHMITT</name>
+                        <description>Enable schmitt trigger</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SLEWFAST</name>
+                        <description>Slew rate control. 1 = Fast, 0 = Slow</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO4</name>
+                <addressOffset>0x00000014</addressOffset>
+                <resetValue>0x00000116</resetValue>
+                <fields>
+                    <field>
+                        <name>ISO</name>
+                        <description>Pad isolation control. Remove this once the pad is configured by software.</description>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>OD</name>
+                        <description>Output disable. Has priority over output enable from peripherals</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>IE</name>
+                        <description>Input enable</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DRIVE</name>
+                        <description>Drive strength.</description>
+                        <bitRange>[5:4]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>2mA</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>4mA</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>8mA</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>12mA</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>PUE</name>
+                        <description>Pull up enable</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PDE</name>
+                        <description>Pull down enable</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SCHMITT</name>
+                        <description>Enable schmitt trigger</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SLEWFAST</name>
+                        <description>Slew rate control. 1 = Fast, 0 = Slow</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO5</name>
+                <addressOffset>0x00000018</addressOffset>
+                <resetValue>0x00000116</resetValue>
+                <fields>
+                    <field>
+                        <name>ISO</name>
+                        <description>Pad isolation control. Remove this once the pad is configured by software.</description>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>OD</name>
+                        <description>Output disable. Has priority over output enable from peripherals</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>IE</name>
+                        <description>Input enable</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DRIVE</name>
+                        <description>Drive strength.</description>
+                        <bitRange>[5:4]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>2mA</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>4mA</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>8mA</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>12mA</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>PUE</name>
+                        <description>Pull up enable</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PDE</name>
+                        <description>Pull down enable</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SCHMITT</name>
+                        <description>Enable schmitt trigger</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SLEWFAST</name>
+                        <description>Slew rate control. 1 = Fast, 0 = Slow</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO6</name>
+                <addressOffset>0x0000001c</addressOffset>
+                <resetValue>0x00000116</resetValue>
+                <fields>
+                    <field>
+                        <name>ISO</name>
+                        <description>Pad isolation control. Remove this once the pad is configured by software.</description>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>OD</name>
+                        <description>Output disable. Has priority over output enable from peripherals</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>IE</name>
+                        <description>Input enable</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DRIVE</name>
+                        <description>Drive strength.</description>
+                        <bitRange>[5:4]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>2mA</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>4mA</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>8mA</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>12mA</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>PUE</name>
+                        <description>Pull up enable</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PDE</name>
+                        <description>Pull down enable</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SCHMITT</name>
+                        <description>Enable schmitt trigger</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SLEWFAST</name>
+                        <description>Slew rate control. 1 = Fast, 0 = Slow</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO7</name>
+                <addressOffset>0x00000020</addressOffset>
+                <resetValue>0x00000116</resetValue>
+                <fields>
+                    <field>
+                        <name>ISO</name>
+                        <description>Pad isolation control. Remove this once the pad is configured by software.</description>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>OD</name>
+                        <description>Output disable. Has priority over output enable from peripherals</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>IE</name>
+                        <description>Input enable</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DRIVE</name>
+                        <description>Drive strength.</description>
+                        <bitRange>[5:4]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>2mA</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>4mA</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>8mA</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>12mA</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>PUE</name>
+                        <description>Pull up enable</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PDE</name>
+                        <description>Pull down enable</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SCHMITT</name>
+                        <description>Enable schmitt trigger</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SLEWFAST</name>
+                        <description>Slew rate control. 1 = Fast, 0 = Slow</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO8</name>
+                <addressOffset>0x00000024</addressOffset>
+                <resetValue>0x00000116</resetValue>
+                <fields>
+                    <field>
+                        <name>ISO</name>
+                        <description>Pad isolation control. Remove this once the pad is configured by software.</description>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>OD</name>
+                        <description>Output disable. Has priority over output enable from peripherals</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>IE</name>
+                        <description>Input enable</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DRIVE</name>
+                        <description>Drive strength.</description>
+                        <bitRange>[5:4]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>2mA</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>4mA</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>8mA</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>12mA</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>PUE</name>
+                        <description>Pull up enable</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PDE</name>
+                        <description>Pull down enable</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SCHMITT</name>
+                        <description>Enable schmitt trigger</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SLEWFAST</name>
+                        <description>Slew rate control. 1 = Fast, 0 = Slow</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO9</name>
+                <addressOffset>0x00000028</addressOffset>
+                <resetValue>0x00000116</resetValue>
+                <fields>
+                    <field>
+                        <name>ISO</name>
+                        <description>Pad isolation control. Remove this once the pad is configured by software.</description>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>OD</name>
+                        <description>Output disable. Has priority over output enable from peripherals</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>IE</name>
+                        <description>Input enable</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DRIVE</name>
+                        <description>Drive strength.</description>
+                        <bitRange>[5:4]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>2mA</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>4mA</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>8mA</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>12mA</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>PUE</name>
+                        <description>Pull up enable</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PDE</name>
+                        <description>Pull down enable</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SCHMITT</name>
+                        <description>Enable schmitt trigger</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SLEWFAST</name>
+                        <description>Slew rate control. 1 = Fast, 0 = Slow</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO10</name>
+                <addressOffset>0x0000002c</addressOffset>
+                <resetValue>0x00000116</resetValue>
+                <fields>
+                    <field>
+                        <name>ISO</name>
+                        <description>Pad isolation control. Remove this once the pad is configured by software.</description>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>OD</name>
+                        <description>Output disable. Has priority over output enable from peripherals</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>IE</name>
+                        <description>Input enable</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DRIVE</name>
+                        <description>Drive strength.</description>
+                        <bitRange>[5:4]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>2mA</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>4mA</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>8mA</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>12mA</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>PUE</name>
+                        <description>Pull up enable</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PDE</name>
+                        <description>Pull down enable</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SCHMITT</name>
+                        <description>Enable schmitt trigger</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SLEWFAST</name>
+                        <description>Slew rate control. 1 = Fast, 0 = Slow</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO11</name>
+                <addressOffset>0x00000030</addressOffset>
+                <resetValue>0x00000116</resetValue>
+                <fields>
+                    <field>
+                        <name>ISO</name>
+                        <description>Pad isolation control. Remove this once the pad is configured by software.</description>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>OD</name>
+                        <description>Output disable. Has priority over output enable from peripherals</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>IE</name>
+                        <description>Input enable</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DRIVE</name>
+                        <description>Drive strength.</description>
+                        <bitRange>[5:4]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>2mA</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>4mA</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>8mA</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>12mA</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>PUE</name>
+                        <description>Pull up enable</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PDE</name>
+                        <description>Pull down enable</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SCHMITT</name>
+                        <description>Enable schmitt trigger</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SLEWFAST</name>
+                        <description>Slew rate control. 1 = Fast, 0 = Slow</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO12</name>
+                <addressOffset>0x00000034</addressOffset>
+                <resetValue>0x00000116</resetValue>
+                <fields>
+                    <field>
+                        <name>ISO</name>
+                        <description>Pad isolation control. Remove this once the pad is configured by software.</description>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>OD</name>
+                        <description>Output disable. Has priority over output enable from peripherals</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>IE</name>
+                        <description>Input enable</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DRIVE</name>
+                        <description>Drive strength.</description>
+                        <bitRange>[5:4]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>2mA</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>4mA</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>8mA</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>12mA</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>PUE</name>
+                        <description>Pull up enable</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PDE</name>
+                        <description>Pull down enable</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SCHMITT</name>
+                        <description>Enable schmitt trigger</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SLEWFAST</name>
+                        <description>Slew rate control. 1 = Fast, 0 = Slow</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO13</name>
+                <addressOffset>0x00000038</addressOffset>
+                <resetValue>0x00000116</resetValue>
+                <fields>
+                    <field>
+                        <name>ISO</name>
+                        <description>Pad isolation control. Remove this once the pad is configured by software.</description>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>OD</name>
+                        <description>Output disable. Has priority over output enable from peripherals</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>IE</name>
+                        <description>Input enable</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DRIVE</name>
+                        <description>Drive strength.</description>
+                        <bitRange>[5:4]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>2mA</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>4mA</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>8mA</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>12mA</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>PUE</name>
+                        <description>Pull up enable</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PDE</name>
+                        <description>Pull down enable</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SCHMITT</name>
+                        <description>Enable schmitt trigger</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SLEWFAST</name>
+                        <description>Slew rate control. 1 = Fast, 0 = Slow</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO14</name>
+                <addressOffset>0x0000003c</addressOffset>
+                <resetValue>0x00000116</resetValue>
+                <fields>
+                    <field>
+                        <name>ISO</name>
+                        <description>Pad isolation control. Remove this once the pad is configured by software.</description>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>OD</name>
+                        <description>Output disable. Has priority over output enable from peripherals</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>IE</name>
+                        <description>Input enable</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DRIVE</name>
+                        <description>Drive strength.</description>
+                        <bitRange>[5:4]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>2mA</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>4mA</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>8mA</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>12mA</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>PUE</name>
+                        <description>Pull up enable</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PDE</name>
+                        <description>Pull down enable</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SCHMITT</name>
+                        <description>Enable schmitt trigger</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SLEWFAST</name>
+                        <description>Slew rate control. 1 = Fast, 0 = Slow</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO15</name>
+                <addressOffset>0x00000040</addressOffset>
+                <resetValue>0x00000116</resetValue>
+                <fields>
+                    <field>
+                        <name>ISO</name>
+                        <description>Pad isolation control. Remove this once the pad is configured by software.</description>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>OD</name>
+                        <description>Output disable. Has priority over output enable from peripherals</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>IE</name>
+                        <description>Input enable</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DRIVE</name>
+                        <description>Drive strength.</description>
+                        <bitRange>[5:4]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>2mA</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>4mA</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>8mA</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>12mA</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>PUE</name>
+                        <description>Pull up enable</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PDE</name>
+                        <description>Pull down enable</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SCHMITT</name>
+                        <description>Enable schmitt trigger</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SLEWFAST</name>
+                        <description>Slew rate control. 1 = Fast, 0 = Slow</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO16</name>
+                <addressOffset>0x00000044</addressOffset>
+                <resetValue>0x00000116</resetValue>
+                <fields>
+                    <field>
+                        <name>ISO</name>
+                        <description>Pad isolation control. Remove this once the pad is configured by software.</description>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>OD</name>
+                        <description>Output disable. Has priority over output enable from peripherals</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>IE</name>
+                        <description>Input enable</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DRIVE</name>
+                        <description>Drive strength.</description>
+                        <bitRange>[5:4]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>2mA</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>4mA</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>8mA</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>12mA</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>PUE</name>
+                        <description>Pull up enable</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PDE</name>
+                        <description>Pull down enable</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SCHMITT</name>
+                        <description>Enable schmitt trigger</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SLEWFAST</name>
+                        <description>Slew rate control. 1 = Fast, 0 = Slow</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO17</name>
+                <addressOffset>0x00000048</addressOffset>
+                <resetValue>0x00000116</resetValue>
+                <fields>
+                    <field>
+                        <name>ISO</name>
+                        <description>Pad isolation control. Remove this once the pad is configured by software.</description>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>OD</name>
+                        <description>Output disable. Has priority over output enable from peripherals</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>IE</name>
+                        <description>Input enable</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DRIVE</name>
+                        <description>Drive strength.</description>
+                        <bitRange>[5:4]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>2mA</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>4mA</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>8mA</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>12mA</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>PUE</name>
+                        <description>Pull up enable</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PDE</name>
+                        <description>Pull down enable</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SCHMITT</name>
+                        <description>Enable schmitt trigger</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SLEWFAST</name>
+                        <description>Slew rate control. 1 = Fast, 0 = Slow</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO18</name>
+                <addressOffset>0x0000004c</addressOffset>
+                <resetValue>0x00000116</resetValue>
+                <fields>
+                    <field>
+                        <name>ISO</name>
+                        <description>Pad isolation control. Remove this once the pad is configured by software.</description>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>OD</name>
+                        <description>Output disable. Has priority over output enable from peripherals</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>IE</name>
+                        <description>Input enable</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DRIVE</name>
+                        <description>Drive strength.</description>
+                        <bitRange>[5:4]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>2mA</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>4mA</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>8mA</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>12mA</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>PUE</name>
+                        <description>Pull up enable</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PDE</name>
+                        <description>Pull down enable</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SCHMITT</name>
+                        <description>Enable schmitt trigger</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SLEWFAST</name>
+                        <description>Slew rate control. 1 = Fast, 0 = Slow</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO19</name>
+                <addressOffset>0x00000050</addressOffset>
+                <resetValue>0x00000116</resetValue>
+                <fields>
+                    <field>
+                        <name>ISO</name>
+                        <description>Pad isolation control. Remove this once the pad is configured by software.</description>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>OD</name>
+                        <description>Output disable. Has priority over output enable from peripherals</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>IE</name>
+                        <description>Input enable</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DRIVE</name>
+                        <description>Drive strength.</description>
+                        <bitRange>[5:4]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>2mA</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>4mA</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>8mA</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>12mA</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>PUE</name>
+                        <description>Pull up enable</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PDE</name>
+                        <description>Pull down enable</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SCHMITT</name>
+                        <description>Enable schmitt trigger</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SLEWFAST</name>
+                        <description>Slew rate control. 1 = Fast, 0 = Slow</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO20</name>
+                <addressOffset>0x00000054</addressOffset>
+                <resetValue>0x00000116</resetValue>
+                <fields>
+                    <field>
+                        <name>ISO</name>
+                        <description>Pad isolation control. Remove this once the pad is configured by software.</description>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>OD</name>
+                        <description>Output disable. Has priority over output enable from peripherals</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>IE</name>
+                        <description>Input enable</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DRIVE</name>
+                        <description>Drive strength.</description>
+                        <bitRange>[5:4]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>2mA</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>4mA</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>8mA</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>12mA</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>PUE</name>
+                        <description>Pull up enable</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PDE</name>
+                        <description>Pull down enable</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SCHMITT</name>
+                        <description>Enable schmitt trigger</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SLEWFAST</name>
+                        <description>Slew rate control. 1 = Fast, 0 = Slow</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO21</name>
+                <addressOffset>0x00000058</addressOffset>
+                <resetValue>0x00000116</resetValue>
+                <fields>
+                    <field>
+                        <name>ISO</name>
+                        <description>Pad isolation control. Remove this once the pad is configured by software.</description>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>OD</name>
+                        <description>Output disable. Has priority over output enable from peripherals</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>IE</name>
+                        <description>Input enable</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DRIVE</name>
+                        <description>Drive strength.</description>
+                        <bitRange>[5:4]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>2mA</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>4mA</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>8mA</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>12mA</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>PUE</name>
+                        <description>Pull up enable</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PDE</name>
+                        <description>Pull down enable</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SCHMITT</name>
+                        <description>Enable schmitt trigger</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SLEWFAST</name>
+                        <description>Slew rate control. 1 = Fast, 0 = Slow</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO22</name>
+                <addressOffset>0x0000005c</addressOffset>
+                <resetValue>0x00000116</resetValue>
+                <fields>
+                    <field>
+                        <name>ISO</name>
+                        <description>Pad isolation control. Remove this once the pad is configured by software.</description>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>OD</name>
+                        <description>Output disable. Has priority over output enable from peripherals</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>IE</name>
+                        <description>Input enable</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DRIVE</name>
+                        <description>Drive strength.</description>
+                        <bitRange>[5:4]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>2mA</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>4mA</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>8mA</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>12mA</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>PUE</name>
+                        <description>Pull up enable</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PDE</name>
+                        <description>Pull down enable</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SCHMITT</name>
+                        <description>Enable schmitt trigger</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SLEWFAST</name>
+                        <description>Slew rate control. 1 = Fast, 0 = Slow</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO23</name>
+                <addressOffset>0x00000060</addressOffset>
+                <resetValue>0x00000116</resetValue>
+                <fields>
+                    <field>
+                        <name>ISO</name>
+                        <description>Pad isolation control. Remove this once the pad is configured by software.</description>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>OD</name>
+                        <description>Output disable. Has priority over output enable from peripherals</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>IE</name>
+                        <description>Input enable</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DRIVE</name>
+                        <description>Drive strength.</description>
+                        <bitRange>[5:4]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>2mA</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>4mA</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>8mA</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>12mA</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>PUE</name>
+                        <description>Pull up enable</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PDE</name>
+                        <description>Pull down enable</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SCHMITT</name>
+                        <description>Enable schmitt trigger</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SLEWFAST</name>
+                        <description>Slew rate control. 1 = Fast, 0 = Slow</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO24</name>
+                <addressOffset>0x00000064</addressOffset>
+                <resetValue>0x00000116</resetValue>
+                <fields>
+                    <field>
+                        <name>ISO</name>
+                        <description>Pad isolation control. Remove this once the pad is configured by software.</description>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>OD</name>
+                        <description>Output disable. Has priority over output enable from peripherals</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>IE</name>
+                        <description>Input enable</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DRIVE</name>
+                        <description>Drive strength.</description>
+                        <bitRange>[5:4]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>2mA</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>4mA</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>8mA</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>12mA</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>PUE</name>
+                        <description>Pull up enable</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PDE</name>
+                        <description>Pull down enable</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SCHMITT</name>
+                        <description>Enable schmitt trigger</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SLEWFAST</name>
+                        <description>Slew rate control. 1 = Fast, 0 = Slow</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO25</name>
+                <addressOffset>0x00000068</addressOffset>
+                <resetValue>0x00000116</resetValue>
+                <fields>
+                    <field>
+                        <name>ISO</name>
+                        <description>Pad isolation control. Remove this once the pad is configured by software.</description>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>OD</name>
+                        <description>Output disable. Has priority over output enable from peripherals</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>IE</name>
+                        <description>Input enable</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DRIVE</name>
+                        <description>Drive strength.</description>
+                        <bitRange>[5:4]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>2mA</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>4mA</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>8mA</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>12mA</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>PUE</name>
+                        <description>Pull up enable</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PDE</name>
+                        <description>Pull down enable</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SCHMITT</name>
+                        <description>Enable schmitt trigger</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SLEWFAST</name>
+                        <description>Slew rate control. 1 = Fast, 0 = Slow</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO26</name>
+                <addressOffset>0x0000006c</addressOffset>
+                <resetValue>0x00000116</resetValue>
+                <fields>
+                    <field>
+                        <name>ISO</name>
+                        <description>Pad isolation control. Remove this once the pad is configured by software.</description>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>OD</name>
+                        <description>Output disable. Has priority over output enable from peripherals</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>IE</name>
+                        <description>Input enable</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DRIVE</name>
+                        <description>Drive strength.</description>
+                        <bitRange>[5:4]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>2mA</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>4mA</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>8mA</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>12mA</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>PUE</name>
+                        <description>Pull up enable</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PDE</name>
+                        <description>Pull down enable</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SCHMITT</name>
+                        <description>Enable schmitt trigger</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SLEWFAST</name>
+                        <description>Slew rate control. 1 = Fast, 0 = Slow</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO27</name>
+                <addressOffset>0x00000070</addressOffset>
+                <resetValue>0x00000116</resetValue>
+                <fields>
+                    <field>
+                        <name>ISO</name>
+                        <description>Pad isolation control. Remove this once the pad is configured by software.</description>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>OD</name>
+                        <description>Output disable. Has priority over output enable from peripherals</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>IE</name>
+                        <description>Input enable</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DRIVE</name>
+                        <description>Drive strength.</description>
+                        <bitRange>[5:4]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>2mA</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>4mA</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>8mA</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>12mA</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>PUE</name>
+                        <description>Pull up enable</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PDE</name>
+                        <description>Pull down enable</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SCHMITT</name>
+                        <description>Enable schmitt trigger</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SLEWFAST</name>
+                        <description>Slew rate control. 1 = Fast, 0 = Slow</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO28</name>
+                <addressOffset>0x00000074</addressOffset>
+                <resetValue>0x00000116</resetValue>
+                <fields>
+                    <field>
+                        <name>ISO</name>
+                        <description>Pad isolation control. Remove this once the pad is configured by software.</description>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>OD</name>
+                        <description>Output disable. Has priority over output enable from peripherals</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>IE</name>
+                        <description>Input enable</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DRIVE</name>
+                        <description>Drive strength.</description>
+                        <bitRange>[5:4]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>2mA</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>4mA</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>8mA</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>12mA</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>PUE</name>
+                        <description>Pull up enable</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PDE</name>
+                        <description>Pull down enable</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SCHMITT</name>
+                        <description>Enable schmitt trigger</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SLEWFAST</name>
+                        <description>Slew rate control. 1 = Fast, 0 = Slow</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO29</name>
+                <addressOffset>0x00000078</addressOffset>
+                <resetValue>0x00000116</resetValue>
+                <fields>
+                    <field>
+                        <name>ISO</name>
+                        <description>Pad isolation control. Remove this once the pad is configured by software.</description>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>OD</name>
+                        <description>Output disable. Has priority over output enable from peripherals</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>IE</name>
+                        <description>Input enable</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DRIVE</name>
+                        <description>Drive strength.</description>
+                        <bitRange>[5:4]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>2mA</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>4mA</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>8mA</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>12mA</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>PUE</name>
+                        <description>Pull up enable</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PDE</name>
+                        <description>Pull down enable</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SCHMITT</name>
+                        <description>Enable schmitt trigger</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SLEWFAST</name>
+                        <description>Slew rate control. 1 = Fast, 0 = Slow</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO30</name>
+                <addressOffset>0x0000007c</addressOffset>
+                <resetValue>0x00000116</resetValue>
+                <fields>
+                    <field>
+                        <name>ISO</name>
+                        <description>Pad isolation control. Remove this once the pad is configured by software.</description>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>OD</name>
+                        <description>Output disable. Has priority over output enable from peripherals</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>IE</name>
+                        <description>Input enable</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DRIVE</name>
+                        <description>Drive strength.</description>
+                        <bitRange>[5:4]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>2mA</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>4mA</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>8mA</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>12mA</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>PUE</name>
+                        <description>Pull up enable</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PDE</name>
+                        <description>Pull down enable</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SCHMITT</name>
+                        <description>Enable schmitt trigger</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SLEWFAST</name>
+                        <description>Slew rate control. 1 = Fast, 0 = Slow</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO31</name>
+                <addressOffset>0x00000080</addressOffset>
+                <resetValue>0x00000116</resetValue>
+                <fields>
+                    <field>
+                        <name>ISO</name>
+                        <description>Pad isolation control. Remove this once the pad is configured by software.</description>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>OD</name>
+                        <description>Output disable. Has priority over output enable from peripherals</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>IE</name>
+                        <description>Input enable</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DRIVE</name>
+                        <description>Drive strength.</description>
+                        <bitRange>[5:4]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>2mA</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>4mA</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>8mA</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>12mA</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>PUE</name>
+                        <description>Pull up enable</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PDE</name>
+                        <description>Pull down enable</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SCHMITT</name>
+                        <description>Enable schmitt trigger</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SLEWFAST</name>
+                        <description>Slew rate control. 1 = Fast, 0 = Slow</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO32</name>
+                <addressOffset>0x00000084</addressOffset>
+                <resetValue>0x00000116</resetValue>
+                <fields>
+                    <field>
+                        <name>ISO</name>
+                        <description>Pad isolation control. Remove this once the pad is configured by software.</description>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>OD</name>
+                        <description>Output disable. Has priority over output enable from peripherals</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>IE</name>
+                        <description>Input enable</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DRIVE</name>
+                        <description>Drive strength.</description>
+                        <bitRange>[5:4]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>2mA</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>4mA</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>8mA</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>12mA</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>PUE</name>
+                        <description>Pull up enable</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PDE</name>
+                        <description>Pull down enable</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SCHMITT</name>
+                        <description>Enable schmitt trigger</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SLEWFAST</name>
+                        <description>Slew rate control. 1 = Fast, 0 = Slow</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO33</name>
+                <addressOffset>0x00000088</addressOffset>
+                <resetValue>0x00000116</resetValue>
+                <fields>
+                    <field>
+                        <name>ISO</name>
+                        <description>Pad isolation control. Remove this once the pad is configured by software.</description>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>OD</name>
+                        <description>Output disable. Has priority over output enable from peripherals</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>IE</name>
+                        <description>Input enable</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DRIVE</name>
+                        <description>Drive strength.</description>
+                        <bitRange>[5:4]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>2mA</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>4mA</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>8mA</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>12mA</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>PUE</name>
+                        <description>Pull up enable</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PDE</name>
+                        <description>Pull down enable</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SCHMITT</name>
+                        <description>Enable schmitt trigger</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SLEWFAST</name>
+                        <description>Slew rate control. 1 = Fast, 0 = Slow</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO34</name>
+                <addressOffset>0x0000008c</addressOffset>
+                <resetValue>0x00000116</resetValue>
+                <fields>
+                    <field>
+                        <name>ISO</name>
+                        <description>Pad isolation control. Remove this once the pad is configured by software.</description>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>OD</name>
+                        <description>Output disable. Has priority over output enable from peripherals</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>IE</name>
+                        <description>Input enable</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DRIVE</name>
+                        <description>Drive strength.</description>
+                        <bitRange>[5:4]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>2mA</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>4mA</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>8mA</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>12mA</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>PUE</name>
+                        <description>Pull up enable</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PDE</name>
+                        <description>Pull down enable</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SCHMITT</name>
+                        <description>Enable schmitt trigger</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SLEWFAST</name>
+                        <description>Slew rate control. 1 = Fast, 0 = Slow</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO35</name>
+                <addressOffset>0x00000090</addressOffset>
+                <resetValue>0x00000116</resetValue>
+                <fields>
+                    <field>
+                        <name>ISO</name>
+                        <description>Pad isolation control. Remove this once the pad is configured by software.</description>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>OD</name>
+                        <description>Output disable. Has priority over output enable from peripherals</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>IE</name>
+                        <description>Input enable</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DRIVE</name>
+                        <description>Drive strength.</description>
+                        <bitRange>[5:4]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>2mA</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>4mA</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>8mA</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>12mA</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>PUE</name>
+                        <description>Pull up enable</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PDE</name>
+                        <description>Pull down enable</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SCHMITT</name>
+                        <description>Enable schmitt trigger</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SLEWFAST</name>
+                        <description>Slew rate control. 1 = Fast, 0 = Slow</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO36</name>
+                <addressOffset>0x00000094</addressOffset>
+                <resetValue>0x00000116</resetValue>
+                <fields>
+                    <field>
+                        <name>ISO</name>
+                        <description>Pad isolation control. Remove this once the pad is configured by software.</description>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>OD</name>
+                        <description>Output disable. Has priority over output enable from peripherals</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>IE</name>
+                        <description>Input enable</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DRIVE</name>
+                        <description>Drive strength.</description>
+                        <bitRange>[5:4]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>2mA</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>4mA</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>8mA</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>12mA</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>PUE</name>
+                        <description>Pull up enable</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PDE</name>
+                        <description>Pull down enable</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SCHMITT</name>
+                        <description>Enable schmitt trigger</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SLEWFAST</name>
+                        <description>Slew rate control. 1 = Fast, 0 = Slow</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO37</name>
+                <addressOffset>0x00000098</addressOffset>
+                <resetValue>0x00000116</resetValue>
+                <fields>
+                    <field>
+                        <name>ISO</name>
+                        <description>Pad isolation control. Remove this once the pad is configured by software.</description>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>OD</name>
+                        <description>Output disable. Has priority over output enable from peripherals</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>IE</name>
+                        <description>Input enable</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DRIVE</name>
+                        <description>Drive strength.</description>
+                        <bitRange>[5:4]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>2mA</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>4mA</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>8mA</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>12mA</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>PUE</name>
+                        <description>Pull up enable</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PDE</name>
+                        <description>Pull down enable</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SCHMITT</name>
+                        <description>Enable schmitt trigger</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SLEWFAST</name>
+                        <description>Slew rate control. 1 = Fast, 0 = Slow</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO38</name>
+                <addressOffset>0x0000009c</addressOffset>
+                <resetValue>0x00000116</resetValue>
+                <fields>
+                    <field>
+                        <name>ISO</name>
+                        <description>Pad isolation control. Remove this once the pad is configured by software.</description>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>OD</name>
+                        <description>Output disable. Has priority over output enable from peripherals</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>IE</name>
+                        <description>Input enable</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DRIVE</name>
+                        <description>Drive strength.</description>
+                        <bitRange>[5:4]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>2mA</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>4mA</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>8mA</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>12mA</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>PUE</name>
+                        <description>Pull up enable</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PDE</name>
+                        <description>Pull down enable</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SCHMITT</name>
+                        <description>Enable schmitt trigger</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SLEWFAST</name>
+                        <description>Slew rate control. 1 = Fast, 0 = Slow</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO39</name>
+                <addressOffset>0x000000a0</addressOffset>
+                <resetValue>0x00000116</resetValue>
+                <fields>
+                    <field>
+                        <name>ISO</name>
+                        <description>Pad isolation control. Remove this once the pad is configured by software.</description>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>OD</name>
+                        <description>Output disable. Has priority over output enable from peripherals</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>IE</name>
+                        <description>Input enable</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DRIVE</name>
+                        <description>Drive strength.</description>
+                        <bitRange>[5:4]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>2mA</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>4mA</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>8mA</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>12mA</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>PUE</name>
+                        <description>Pull up enable</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PDE</name>
+                        <description>Pull down enable</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SCHMITT</name>
+                        <description>Enable schmitt trigger</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SLEWFAST</name>
+                        <description>Slew rate control. 1 = Fast, 0 = Slow</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO40</name>
+                <addressOffset>0x000000a4</addressOffset>
+                <resetValue>0x00000116</resetValue>
+                <fields>
+                    <field>
+                        <name>ISO</name>
+                        <description>Pad isolation control. Remove this once the pad is configured by software.</description>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>OD</name>
+                        <description>Output disable. Has priority over output enable from peripherals</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>IE</name>
+                        <description>Input enable</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DRIVE</name>
+                        <description>Drive strength.</description>
+                        <bitRange>[5:4]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>2mA</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>4mA</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>8mA</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>12mA</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>PUE</name>
+                        <description>Pull up enable</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PDE</name>
+                        <description>Pull down enable</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SCHMITT</name>
+                        <description>Enable schmitt trigger</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SLEWFAST</name>
+                        <description>Slew rate control. 1 = Fast, 0 = Slow</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO41</name>
+                <addressOffset>0x000000a8</addressOffset>
+                <resetValue>0x00000116</resetValue>
+                <fields>
+                    <field>
+                        <name>ISO</name>
+                        <description>Pad isolation control. Remove this once the pad is configured by software.</description>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>OD</name>
+                        <description>Output disable. Has priority over output enable from peripherals</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>IE</name>
+                        <description>Input enable</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DRIVE</name>
+                        <description>Drive strength.</description>
+                        <bitRange>[5:4]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>2mA</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>4mA</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>8mA</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>12mA</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>PUE</name>
+                        <description>Pull up enable</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PDE</name>
+                        <description>Pull down enable</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SCHMITT</name>
+                        <description>Enable schmitt trigger</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SLEWFAST</name>
+                        <description>Slew rate control. 1 = Fast, 0 = Slow</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO42</name>
+                <addressOffset>0x000000ac</addressOffset>
+                <resetValue>0x00000116</resetValue>
+                <fields>
+                    <field>
+                        <name>ISO</name>
+                        <description>Pad isolation control. Remove this once the pad is configured by software.</description>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>OD</name>
+                        <description>Output disable. Has priority over output enable from peripherals</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>IE</name>
+                        <description>Input enable</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DRIVE</name>
+                        <description>Drive strength.</description>
+                        <bitRange>[5:4]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>2mA</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>4mA</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>8mA</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>12mA</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>PUE</name>
+                        <description>Pull up enable</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PDE</name>
+                        <description>Pull down enable</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SCHMITT</name>
+                        <description>Enable schmitt trigger</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SLEWFAST</name>
+                        <description>Slew rate control. 1 = Fast, 0 = Slow</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO43</name>
+                <addressOffset>0x000000b0</addressOffset>
+                <resetValue>0x00000116</resetValue>
+                <fields>
+                    <field>
+                        <name>ISO</name>
+                        <description>Pad isolation control. Remove this once the pad is configured by software.</description>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>OD</name>
+                        <description>Output disable. Has priority over output enable from peripherals</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>IE</name>
+                        <description>Input enable</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DRIVE</name>
+                        <description>Drive strength.</description>
+                        <bitRange>[5:4]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>2mA</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>4mA</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>8mA</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>12mA</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>PUE</name>
+                        <description>Pull up enable</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PDE</name>
+                        <description>Pull down enable</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SCHMITT</name>
+                        <description>Enable schmitt trigger</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SLEWFAST</name>
+                        <description>Slew rate control. 1 = Fast, 0 = Slow</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO44</name>
+                <addressOffset>0x000000b4</addressOffset>
+                <resetValue>0x00000116</resetValue>
+                <fields>
+                    <field>
+                        <name>ISO</name>
+                        <description>Pad isolation control. Remove this once the pad is configured by software.</description>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>OD</name>
+                        <description>Output disable. Has priority over output enable from peripherals</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>IE</name>
+                        <description>Input enable</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DRIVE</name>
+                        <description>Drive strength.</description>
+                        <bitRange>[5:4]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>2mA</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>4mA</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>8mA</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>12mA</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>PUE</name>
+                        <description>Pull up enable</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PDE</name>
+                        <description>Pull down enable</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SCHMITT</name>
+                        <description>Enable schmitt trigger</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SLEWFAST</name>
+                        <description>Slew rate control. 1 = Fast, 0 = Slow</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO45</name>
+                <addressOffset>0x000000b8</addressOffset>
+                <resetValue>0x00000116</resetValue>
+                <fields>
+                    <field>
+                        <name>ISO</name>
+                        <description>Pad isolation control. Remove this once the pad is configured by software.</description>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>OD</name>
+                        <description>Output disable. Has priority over output enable from peripherals</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>IE</name>
+                        <description>Input enable</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DRIVE</name>
+                        <description>Drive strength.</description>
+                        <bitRange>[5:4]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>2mA</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>4mA</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>8mA</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>12mA</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>PUE</name>
+                        <description>Pull up enable</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PDE</name>
+                        <description>Pull down enable</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SCHMITT</name>
+                        <description>Enable schmitt trigger</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SLEWFAST</name>
+                        <description>Slew rate control. 1 = Fast, 0 = Slow</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO46</name>
+                <addressOffset>0x000000bc</addressOffset>
+                <resetValue>0x00000116</resetValue>
+                <fields>
+                    <field>
+                        <name>ISO</name>
+                        <description>Pad isolation control. Remove this once the pad is configured by software.</description>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>OD</name>
+                        <description>Output disable. Has priority over output enable from peripherals</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>IE</name>
+                        <description>Input enable</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DRIVE</name>
+                        <description>Drive strength.</description>
+                        <bitRange>[5:4]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>2mA</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>4mA</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>8mA</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>12mA</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>PUE</name>
+                        <description>Pull up enable</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PDE</name>
+                        <description>Pull down enable</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SCHMITT</name>
+                        <description>Enable schmitt trigger</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SLEWFAST</name>
+                        <description>Slew rate control. 1 = Fast, 0 = Slow</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO47</name>
+                <addressOffset>0x000000c0</addressOffset>
+                <resetValue>0x00000116</resetValue>
+                <fields>
+                    <field>
+                        <name>ISO</name>
+                        <description>Pad isolation control. Remove this once the pad is configured by software.</description>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>OD</name>
+                        <description>Output disable. Has priority over output enable from peripherals</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>IE</name>
+                        <description>Input enable</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DRIVE</name>
+                        <description>Drive strength.</description>
+                        <bitRange>[5:4]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>2mA</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>4mA</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>8mA</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>12mA</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>PUE</name>
+                        <description>Pull up enable</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PDE</name>
+                        <description>Pull down enable</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SCHMITT</name>
+                        <description>Enable schmitt trigger</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SLEWFAST</name>
+                        <description>Slew rate control. 1 = Fast, 0 = Slow</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SWCLK</name>
+                <addressOffset>0x000000c4</addressOffset>
+                <resetValue>0x0000005a</resetValue>
+                <fields>
+                    <field>
+                        <name>ISO</name>
+                        <description>Pad isolation control. Remove this once the pad is configured by software.</description>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>OD</name>
+                        <description>Output disable. Has priority over output enable from peripherals</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>IE</name>
+                        <description>Input enable</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DRIVE</name>
+                        <description>Drive strength.</description>
+                        <bitRange>[5:4]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>2mA</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>4mA</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>8mA</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>12mA</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>PUE</name>
+                        <description>Pull up enable</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PDE</name>
+                        <description>Pull down enable</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SCHMITT</name>
+                        <description>Enable schmitt trigger</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SLEWFAST</name>
+                        <description>Slew rate control. 1 = Fast, 0 = Slow</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SWD</name>
+                <addressOffset>0x000000c8</addressOffset>
+                <resetValue>0x0000005a</resetValue>
+                <fields>
+                    <field>
+                        <name>ISO</name>
+                        <description>Pad isolation control. Remove this once the pad is configured by software.</description>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>OD</name>
+                        <description>Output disable. Has priority over output enable from peripherals</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>IE</name>
+                        <description>Input enable</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DRIVE</name>
+                        <description>Drive strength.</description>
+                        <bitRange>[5:4]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>2mA</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>4mA</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>8mA</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>12mA</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>PUE</name>
+                        <description>Pull up enable</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PDE</name>
+                        <description>Pull down enable</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SCHMITT</name>
+                        <description>Enable schmitt trigger</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SLEWFAST</name>
+                        <description>Slew rate control. 1 = Fast, 0 = Slow</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+        </registers>
+    </peripheral>
+    <peripheral>
+        <name>PADS_QSPI</name>
+        <baseAddress>0x40040000</baseAddress>
+        <addressBlock>
+            <offset>0</offset>
+            <size>28</size>
+            <usage>registers</usage>
+        </addressBlock>
+        <registers>
+            <register>
+                <name>VOLTAGE_SELECT</name>
+                <addressOffset>0x00000000</addressOffset>
+                <description>Voltage select. Per bank control</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>VOLTAGE_SELECT</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>3v3</name>
+                                <value>0</value>
+                                <description>Set voltage to 3.3V (DVDD &gt;= 2V5)</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>1v8</name>
+                                <value>1</value>
+                                <description>Set voltage to 1.8V (DVDD &lt;= 1V8)</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO_QSPI_SCLK</name>
+                <addressOffset>0x00000004</addressOffset>
+                <resetValue>0x00000156</resetValue>
+                <fields>
+                    <field>
+                        <name>ISO</name>
+                        <description>Pad isolation control. Remove this once the pad is configured by software.</description>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>OD</name>
+                        <description>Output disable. Has priority over output enable from peripherals</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>IE</name>
+                        <description>Input enable</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DRIVE</name>
+                        <description>Drive strength.</description>
+                        <bitRange>[5:4]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>2mA</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>4mA</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>8mA</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>12mA</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>PUE</name>
+                        <description>Pull up enable</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PDE</name>
+                        <description>Pull down enable</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SCHMITT</name>
+                        <description>Enable schmitt trigger</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SLEWFAST</name>
+                        <description>Slew rate control. 1 = Fast, 0 = Slow</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO_QSPI_SD0</name>
+                <addressOffset>0x00000008</addressOffset>
+                <resetValue>0x00000156</resetValue>
+                <fields>
+                    <field>
+                        <name>ISO</name>
+                        <description>Pad isolation control. Remove this once the pad is configured by software.</description>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>OD</name>
+                        <description>Output disable. Has priority over output enable from peripherals</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>IE</name>
+                        <description>Input enable</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DRIVE</name>
+                        <description>Drive strength.</description>
+                        <bitRange>[5:4]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>2mA</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>4mA</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>8mA</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>12mA</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>PUE</name>
+                        <description>Pull up enable</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PDE</name>
+                        <description>Pull down enable</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SCHMITT</name>
+                        <description>Enable schmitt trigger</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SLEWFAST</name>
+                        <description>Slew rate control. 1 = Fast, 0 = Slow</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO_QSPI_SD1</name>
+                <addressOffset>0x0000000c</addressOffset>
+                <resetValue>0x00000156</resetValue>
+                <fields>
+                    <field>
+                        <name>ISO</name>
+                        <description>Pad isolation control. Remove this once the pad is configured by software.</description>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>OD</name>
+                        <description>Output disable. Has priority over output enable from peripherals</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>IE</name>
+                        <description>Input enable</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DRIVE</name>
+                        <description>Drive strength.</description>
+                        <bitRange>[5:4]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>2mA</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>4mA</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>8mA</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>12mA</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>PUE</name>
+                        <description>Pull up enable</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PDE</name>
+                        <description>Pull down enable</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SCHMITT</name>
+                        <description>Enable schmitt trigger</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SLEWFAST</name>
+                        <description>Slew rate control. 1 = Fast, 0 = Slow</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO_QSPI_SD2</name>
+                <addressOffset>0x00000010</addressOffset>
+                <resetValue>0x0000015a</resetValue>
+                <fields>
+                    <field>
+                        <name>ISO</name>
+                        <description>Pad isolation control. Remove this once the pad is configured by software.</description>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>OD</name>
+                        <description>Output disable. Has priority over output enable from peripherals</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>IE</name>
+                        <description>Input enable</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DRIVE</name>
+                        <description>Drive strength.</description>
+                        <bitRange>[5:4]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>2mA</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>4mA</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>8mA</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>12mA</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>PUE</name>
+                        <description>Pull up enable</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PDE</name>
+                        <description>Pull down enable</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SCHMITT</name>
+                        <description>Enable schmitt trigger</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SLEWFAST</name>
+                        <description>Slew rate control. 1 = Fast, 0 = Slow</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO_QSPI_SD3</name>
+                <addressOffset>0x00000014</addressOffset>
+                <resetValue>0x0000015a</resetValue>
+                <fields>
+                    <field>
+                        <name>ISO</name>
+                        <description>Pad isolation control. Remove this once the pad is configured by software.</description>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>OD</name>
+                        <description>Output disable. Has priority over output enable from peripherals</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>IE</name>
+                        <description>Input enable</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DRIVE</name>
+                        <description>Drive strength.</description>
+                        <bitRange>[5:4]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>2mA</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>4mA</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>8mA</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>12mA</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>PUE</name>
+                        <description>Pull up enable</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PDE</name>
+                        <description>Pull down enable</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SCHMITT</name>
+                        <description>Enable schmitt trigger</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SLEWFAST</name>
+                        <description>Slew rate control. 1 = Fast, 0 = Slow</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO_QSPI_SS</name>
+                <addressOffset>0x00000018</addressOffset>
+                <resetValue>0x0000015a</resetValue>
+                <fields>
+                    <field>
+                        <name>ISO</name>
+                        <description>Pad isolation control. Remove this once the pad is configured by software.</description>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>OD</name>
+                        <description>Output disable. Has priority over output enable from peripherals</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>IE</name>
+                        <description>Input enable</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DRIVE</name>
+                        <description>Drive strength.</description>
+                        <bitRange>[5:4]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>2mA</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>4mA</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>8mA</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>12mA</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>PUE</name>
+                        <description>Pull up enable</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PDE</name>
+                        <description>Pull down enable</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SCHMITT</name>
+                        <description>Enable schmitt trigger</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SLEWFAST</name>
+                        <description>Slew rate control. 1 = Fast, 0 = Slow</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+        </registers>
+    </peripheral>
+    <peripheral>
+        <name>IO_QSPI</name>
+        <baseAddress>0x40030000</baseAddress>
+        <addressBlock>
+            <offset>0</offset>
+            <size>576</size>
+            <usage>registers</usage>
+        </addressBlock>
+        <interrupt>
+            <name>IO_IRQ_QSPI</name>
+            <value>23</value>
+        </interrupt>
+        <interrupt>
+            <name>IO_IRQ_QSPI_NS</name>
+            <value>24</value>
+        </interrupt>
+        <registers>
+            <register>
+                <name>USBPHY_DP_STATUS</name>
+                <addressOffset>0x00000000</addressOffset>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>IRQTOPROC</name>
+                        <description>interrupt to processors, after override is applied</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>INFROMPAD</name>
+                        <description>input signal from pad, before filtering and override are applied</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OETOPAD</name>
+                        <description>output enable to pad after register override is applied</description>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OUTTOPAD</name>
+                        <description>output signal to pad after register override is applied</description>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>USBPHY_DP_CTRL</name>
+                <addressOffset>0x00000004</addressOffset>
+                <resetValue>0x0000001f</resetValue>
+                <fields>
+                    <field>
+                        <name>IRQOVER</name>
+                        <bitRange>[29:28]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>don&#39;t invert the interrupt</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>invert the interrupt</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive interrupt low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive interrupt high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>INOVER</name>
+                        <bitRange>[17:16]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>don&#39;t invert the peri input</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>invert the peri input</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive peri input low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive peri input high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>OEOVER</name>
+                        <bitRange>[15:14]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>drive output enable from peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>DISABLE</name>
+                                <value>2</value>
+                                <description>disable output</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ENABLE</name>
+                                <value>3</value>
+                                <description>enable output</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>OUTOVER</name>
+                        <bitRange>[13:12]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>drive output from peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>drive output from inverse of peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive output low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive output high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>FUNCSEL</name>
+                        <description>0-31 -&gt; selects pin function according to the gpio table 
+                            31 == NULL</description>
+                        <bitRange>[4:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>uart1_tx</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>i2c0_sda</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>siob_proc_56</name>
+                                <value>5</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>null</name>
+                                <value>31</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>USBPHY_DM_STATUS</name>
+                <addressOffset>0x00000008</addressOffset>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>IRQTOPROC</name>
+                        <description>interrupt to processors, after override is applied</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>INFROMPAD</name>
+                        <description>input signal from pad, before filtering and override are applied</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OETOPAD</name>
+                        <description>output enable to pad after register override is applied</description>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OUTTOPAD</name>
+                        <description>output signal to pad after register override is applied</description>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>USBPHY_DM_CTRL</name>
+                <addressOffset>0x0000000c</addressOffset>
+                <resetValue>0x0000001f</resetValue>
+                <fields>
+                    <field>
+                        <name>IRQOVER</name>
+                        <bitRange>[29:28]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>don&#39;t invert the interrupt</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>invert the interrupt</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive interrupt low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive interrupt high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>INOVER</name>
+                        <bitRange>[17:16]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>don&#39;t invert the peri input</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>invert the peri input</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive peri input low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive peri input high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>OEOVER</name>
+                        <bitRange>[15:14]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>drive output enable from peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>DISABLE</name>
+                                <value>2</value>
+                                <description>disable output</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ENABLE</name>
+                                <value>3</value>
+                                <description>enable output</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>OUTOVER</name>
+                        <bitRange>[13:12]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>drive output from peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>drive output from inverse of peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive output low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive output high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>FUNCSEL</name>
+                        <description>0-31 -&gt; selects pin function according to the gpio table 
+                            31 == NULL</description>
+                        <bitRange>[4:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>uart1_rx</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>i2c0_scl</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>siob_proc_57</name>
+                                <value>5</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>null</name>
+                                <value>31</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO_QSPI_SCLK_STATUS</name>
+                <addressOffset>0x00000010</addressOffset>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>IRQTOPROC</name>
+                        <description>interrupt to processors, after override is applied</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>INFROMPAD</name>
+                        <description>input signal from pad, before filtering and override are applied</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OETOPAD</name>
+                        <description>output enable to pad after register override is applied</description>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OUTTOPAD</name>
+                        <description>output signal to pad after register override is applied</description>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO_QSPI_SCLK_CTRL</name>
+                <addressOffset>0x00000014</addressOffset>
+                <resetValue>0x0000001f</resetValue>
+                <fields>
+                    <field>
+                        <name>IRQOVER</name>
+                        <bitRange>[29:28]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>don&#39;t invert the interrupt</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>invert the interrupt</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive interrupt low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive interrupt high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>INOVER</name>
+                        <bitRange>[17:16]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>don&#39;t invert the peri input</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>invert the peri input</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive peri input low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive peri input high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>OEOVER</name>
+                        <bitRange>[15:14]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>drive output enable from peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>DISABLE</name>
+                                <value>2</value>
+                                <description>disable output</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ENABLE</name>
+                                <value>3</value>
+                                <description>enable output</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>OUTOVER</name>
+                        <bitRange>[13:12]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>drive output from peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>drive output from inverse of peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive output low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive output high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>FUNCSEL</name>
+                        <description>0-31 -&gt; selects pin function according to the gpio table 
+                            31 == NULL</description>
+                        <bitRange>[4:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>xip_sclk</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>uart1_cts</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>i2c1_sda</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>siob_proc_58</name>
+                                <value>5</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>uart1_tx</name>
+                                <value>11</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>null</name>
+                                <value>31</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO_QSPI_SS_STATUS</name>
+                <addressOffset>0x00000018</addressOffset>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>IRQTOPROC</name>
+                        <description>interrupt to processors, after override is applied</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>INFROMPAD</name>
+                        <description>input signal from pad, before filtering and override are applied</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OETOPAD</name>
+                        <description>output enable to pad after register override is applied</description>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OUTTOPAD</name>
+                        <description>output signal to pad after register override is applied</description>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO_QSPI_SS_CTRL</name>
+                <addressOffset>0x0000001c</addressOffset>
+                <resetValue>0x0000001f</resetValue>
+                <fields>
+                    <field>
+                        <name>IRQOVER</name>
+                        <bitRange>[29:28]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>don&#39;t invert the interrupt</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>invert the interrupt</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive interrupt low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive interrupt high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>INOVER</name>
+                        <bitRange>[17:16]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>don&#39;t invert the peri input</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>invert the peri input</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive peri input low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive peri input high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>OEOVER</name>
+                        <bitRange>[15:14]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>drive output enable from peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>DISABLE</name>
+                                <value>2</value>
+                                <description>disable output</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ENABLE</name>
+                                <value>3</value>
+                                <description>enable output</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>OUTOVER</name>
+                        <bitRange>[13:12]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>drive output from peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>drive output from inverse of peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive output low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive output high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>FUNCSEL</name>
+                        <description>0-31 -&gt; selects pin function according to the gpio table 
+                            31 == NULL</description>
+                        <bitRange>[4:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>xip_ss_n_0</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>uart1_rts</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>i2c1_scl</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>siob_proc_59</name>
+                                <value>5</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>uart1_rx</name>
+                                <value>11</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>null</name>
+                                <value>31</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO_QSPI_SD0_STATUS</name>
+                <addressOffset>0x00000020</addressOffset>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>IRQTOPROC</name>
+                        <description>interrupt to processors, after override is applied</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>INFROMPAD</name>
+                        <description>input signal from pad, before filtering and override are applied</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OETOPAD</name>
+                        <description>output enable to pad after register override is applied</description>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OUTTOPAD</name>
+                        <description>output signal to pad after register override is applied</description>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO_QSPI_SD0_CTRL</name>
+                <addressOffset>0x00000024</addressOffset>
+                <resetValue>0x0000001f</resetValue>
+                <fields>
+                    <field>
+                        <name>IRQOVER</name>
+                        <bitRange>[29:28]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>don&#39;t invert the interrupt</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>invert the interrupt</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive interrupt low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive interrupt high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>INOVER</name>
+                        <bitRange>[17:16]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>don&#39;t invert the peri input</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>invert the peri input</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive peri input low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive peri input high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>OEOVER</name>
+                        <bitRange>[15:14]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>drive output enable from peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>DISABLE</name>
+                                <value>2</value>
+                                <description>disable output</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ENABLE</name>
+                                <value>3</value>
+                                <description>enable output</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>OUTOVER</name>
+                        <bitRange>[13:12]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>drive output from peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>drive output from inverse of peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive output low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive output high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>FUNCSEL</name>
+                        <description>0-31 -&gt; selects pin function according to the gpio table 
+                            31 == NULL</description>
+                        <bitRange>[4:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>xip_sd0</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>uart0_tx</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>i2c0_sda</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>siob_proc_60</name>
+                                <value>5</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>null</name>
+                                <value>31</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO_QSPI_SD1_STATUS</name>
+                <addressOffset>0x00000028</addressOffset>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>IRQTOPROC</name>
+                        <description>interrupt to processors, after override is applied</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>INFROMPAD</name>
+                        <description>input signal from pad, before filtering and override are applied</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OETOPAD</name>
+                        <description>output enable to pad after register override is applied</description>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OUTTOPAD</name>
+                        <description>output signal to pad after register override is applied</description>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO_QSPI_SD1_CTRL</name>
+                <addressOffset>0x0000002c</addressOffset>
+                <resetValue>0x0000001f</resetValue>
+                <fields>
+                    <field>
+                        <name>IRQOVER</name>
+                        <bitRange>[29:28]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>don&#39;t invert the interrupt</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>invert the interrupt</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive interrupt low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive interrupt high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>INOVER</name>
+                        <bitRange>[17:16]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>don&#39;t invert the peri input</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>invert the peri input</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive peri input low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive peri input high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>OEOVER</name>
+                        <bitRange>[15:14]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>drive output enable from peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>DISABLE</name>
+                                <value>2</value>
+                                <description>disable output</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ENABLE</name>
+                                <value>3</value>
+                                <description>enable output</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>OUTOVER</name>
+                        <bitRange>[13:12]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>drive output from peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>drive output from inverse of peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive output low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive output high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>FUNCSEL</name>
+                        <description>0-31 -&gt; selects pin function according to the gpio table 
+                            31 == NULL</description>
+                        <bitRange>[4:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>xip_sd1</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>uart0_rx</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>i2c0_scl</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>siob_proc_61</name>
+                                <value>5</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>null</name>
+                                <value>31</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO_QSPI_SD2_STATUS</name>
+                <addressOffset>0x00000030</addressOffset>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>IRQTOPROC</name>
+                        <description>interrupt to processors, after override is applied</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>INFROMPAD</name>
+                        <description>input signal from pad, before filtering and override are applied</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OETOPAD</name>
+                        <description>output enable to pad after register override is applied</description>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OUTTOPAD</name>
+                        <description>output signal to pad after register override is applied</description>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO_QSPI_SD2_CTRL</name>
+                <addressOffset>0x00000034</addressOffset>
+                <resetValue>0x0000001f</resetValue>
+                <fields>
+                    <field>
+                        <name>IRQOVER</name>
+                        <bitRange>[29:28]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>don&#39;t invert the interrupt</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>invert the interrupt</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive interrupt low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive interrupt high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>INOVER</name>
+                        <bitRange>[17:16]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>don&#39;t invert the peri input</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>invert the peri input</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive peri input low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive peri input high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>OEOVER</name>
+                        <bitRange>[15:14]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>drive output enable from peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>DISABLE</name>
+                                <value>2</value>
+                                <description>disable output</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ENABLE</name>
+                                <value>3</value>
+                                <description>enable output</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>OUTOVER</name>
+                        <bitRange>[13:12]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>drive output from peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>drive output from inverse of peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive output low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive output high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>FUNCSEL</name>
+                        <description>0-31 -&gt; selects pin function according to the gpio table 
+                            31 == NULL</description>
+                        <bitRange>[4:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>xip_sd2</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>uart0_cts</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>i2c1_sda</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>siob_proc_62</name>
+                                <value>5</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>uart0_tx</name>
+                                <value>11</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>null</name>
+                                <value>31</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO_QSPI_SD3_STATUS</name>
+                <addressOffset>0x00000038</addressOffset>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>IRQTOPROC</name>
+                        <description>interrupt to processors, after override is applied</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>INFROMPAD</name>
+                        <description>input signal from pad, before filtering and override are applied</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OETOPAD</name>
+                        <description>output enable to pad after register override is applied</description>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OUTTOPAD</name>
+                        <description>output signal to pad after register override is applied</description>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO_QSPI_SD3_CTRL</name>
+                <addressOffset>0x0000003c</addressOffset>
+                <resetValue>0x0000001f</resetValue>
+                <fields>
+                    <field>
+                        <name>IRQOVER</name>
+                        <bitRange>[29:28]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>don&#39;t invert the interrupt</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>invert the interrupt</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive interrupt low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive interrupt high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>INOVER</name>
+                        <bitRange>[17:16]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>don&#39;t invert the peri input</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>invert the peri input</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive peri input low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive peri input high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>OEOVER</name>
+                        <bitRange>[15:14]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>drive output enable from peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>DISABLE</name>
+                                <value>2</value>
+                                <description>disable output</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ENABLE</name>
+                                <value>3</value>
+                                <description>enable output</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>OUTOVER</name>
+                        <bitRange>[13:12]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>drive output from peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>drive output from inverse of peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive output low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive output high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>FUNCSEL</name>
+                        <description>0-31 -&gt; selects pin function according to the gpio table 
+                            31 == NULL</description>
+                        <bitRange>[4:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>xip_sd3</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>uart0_rts</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>i2c1_scl</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>siob_proc_63</name>
+                                <value>5</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>uart0_rx</name>
+                                <value>11</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>null</name>
+                                <value>31</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>IRQSUMMARY_PROC0_SECURE</name>
+                <addressOffset>0x00000200</addressOffset>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>GPIO_QSPI_SD3</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD2</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD1</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD0</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SS</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SCLK</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>USBPHY_DM</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>USBPHY_DP</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>IRQSUMMARY_PROC0_NONSECURE</name>
+                <addressOffset>0x00000204</addressOffset>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>GPIO_QSPI_SD3</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD2</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD1</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD0</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SS</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SCLK</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>USBPHY_DM</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>USBPHY_DP</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>IRQSUMMARY_PROC1_SECURE</name>
+                <addressOffset>0x00000208</addressOffset>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>GPIO_QSPI_SD3</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD2</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD1</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD0</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SS</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SCLK</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>USBPHY_DM</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>USBPHY_DP</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>IRQSUMMARY_PROC1_NONSECURE</name>
+                <addressOffset>0x0000020c</addressOffset>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>GPIO_QSPI_SD3</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD2</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD1</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD0</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SS</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SCLK</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>USBPHY_DM</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>USBPHY_DP</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>IRQSUMMARY_DORMANT_WAKE_SECURE</name>
+                <addressOffset>0x00000210</addressOffset>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>GPIO_QSPI_SD3</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD2</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD1</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD0</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SS</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SCLK</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>USBPHY_DM</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>USBPHY_DP</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>IRQSUMMARY_DORMANT_WAKE_NONSECURE</name>
+                <addressOffset>0x00000214</addressOffset>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>GPIO_QSPI_SD3</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD2</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD1</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD0</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SS</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SCLK</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>USBPHY_DM</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>USBPHY_DP</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INTR</name>
+                <addressOffset>0x00000218</addressOffset>
+                <description>Raw Interrupts</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>GPIO_QSPI_SD3_EDGE_HIGH</name>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD3_EDGE_LOW</name>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD3_LEVEL_HIGH</name>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD3_LEVEL_LOW</name>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD2_EDGE_HIGH</name>
+                        <bitRange>[27:27]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD2_EDGE_LOW</name>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD2_LEVEL_HIGH</name>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD2_LEVEL_LOW</name>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD1_EDGE_HIGH</name>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD1_EDGE_LOW</name>
+                        <bitRange>[22:22]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD1_LEVEL_HIGH</name>
+                        <bitRange>[21:21]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD1_LEVEL_LOW</name>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD0_EDGE_HIGH</name>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD0_EDGE_LOW</name>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD0_LEVEL_HIGH</name>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD0_LEVEL_LOW</name>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SS_EDGE_HIGH</name>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SS_EDGE_LOW</name>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SS_LEVEL_HIGH</name>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SS_LEVEL_LOW</name>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SCLK_EDGE_HIGH</name>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SCLK_EDGE_LOW</name>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SCLK_LEVEL_HIGH</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SCLK_LEVEL_LOW</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>USBPHY_DM_EDGE_HIGH</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>USBPHY_DM_EDGE_LOW</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>USBPHY_DM_LEVEL_HIGH</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>USBPHY_DM_LEVEL_LOW</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>USBPHY_DP_EDGE_HIGH</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>USBPHY_DP_EDGE_LOW</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>USBPHY_DP_LEVEL_HIGH</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>USBPHY_DP_LEVEL_LOW</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PROC0_INTE</name>
+                <addressOffset>0x0000021c</addressOffset>
+                <description>Interrupt Enable for proc0</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>GPIO_QSPI_SD3_EDGE_HIGH</name>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD3_EDGE_LOW</name>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD3_LEVEL_HIGH</name>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD3_LEVEL_LOW</name>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD2_EDGE_HIGH</name>
+                        <bitRange>[27:27]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD2_EDGE_LOW</name>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD2_LEVEL_HIGH</name>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD2_LEVEL_LOW</name>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD1_EDGE_HIGH</name>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD1_EDGE_LOW</name>
+                        <bitRange>[22:22]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD1_LEVEL_HIGH</name>
+                        <bitRange>[21:21]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD1_LEVEL_LOW</name>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD0_EDGE_HIGH</name>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD0_EDGE_LOW</name>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD0_LEVEL_HIGH</name>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD0_LEVEL_LOW</name>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SS_EDGE_HIGH</name>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SS_EDGE_LOW</name>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SS_LEVEL_HIGH</name>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SS_LEVEL_LOW</name>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SCLK_EDGE_HIGH</name>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SCLK_EDGE_LOW</name>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SCLK_LEVEL_HIGH</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SCLK_LEVEL_LOW</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>USBPHY_DM_EDGE_HIGH</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>USBPHY_DM_EDGE_LOW</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>USBPHY_DM_LEVEL_HIGH</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>USBPHY_DM_LEVEL_LOW</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>USBPHY_DP_EDGE_HIGH</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>USBPHY_DP_EDGE_LOW</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>USBPHY_DP_LEVEL_HIGH</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>USBPHY_DP_LEVEL_LOW</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PROC0_INTF</name>
+                <addressOffset>0x00000220</addressOffset>
+                <description>Interrupt Force for proc0</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>GPIO_QSPI_SD3_EDGE_HIGH</name>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD3_EDGE_LOW</name>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD3_LEVEL_HIGH</name>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD3_LEVEL_LOW</name>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD2_EDGE_HIGH</name>
+                        <bitRange>[27:27]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD2_EDGE_LOW</name>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD2_LEVEL_HIGH</name>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD2_LEVEL_LOW</name>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD1_EDGE_HIGH</name>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD1_EDGE_LOW</name>
+                        <bitRange>[22:22]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD1_LEVEL_HIGH</name>
+                        <bitRange>[21:21]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD1_LEVEL_LOW</name>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD0_EDGE_HIGH</name>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD0_EDGE_LOW</name>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD0_LEVEL_HIGH</name>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD0_LEVEL_LOW</name>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SS_EDGE_HIGH</name>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SS_EDGE_LOW</name>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SS_LEVEL_HIGH</name>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SS_LEVEL_LOW</name>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SCLK_EDGE_HIGH</name>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SCLK_EDGE_LOW</name>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SCLK_LEVEL_HIGH</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SCLK_LEVEL_LOW</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>USBPHY_DM_EDGE_HIGH</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>USBPHY_DM_EDGE_LOW</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>USBPHY_DM_LEVEL_HIGH</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>USBPHY_DM_LEVEL_LOW</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>USBPHY_DP_EDGE_HIGH</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>USBPHY_DP_EDGE_LOW</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>USBPHY_DP_LEVEL_HIGH</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>USBPHY_DP_LEVEL_LOW</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PROC0_INTS</name>
+                <addressOffset>0x00000224</addressOffset>
+                <description>Interrupt status after masking &amp; forcing for proc0</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>GPIO_QSPI_SD3_EDGE_HIGH</name>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD3_EDGE_LOW</name>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD3_LEVEL_HIGH</name>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD3_LEVEL_LOW</name>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD2_EDGE_HIGH</name>
+                        <bitRange>[27:27]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD2_EDGE_LOW</name>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD2_LEVEL_HIGH</name>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD2_LEVEL_LOW</name>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD1_EDGE_HIGH</name>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD1_EDGE_LOW</name>
+                        <bitRange>[22:22]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD1_LEVEL_HIGH</name>
+                        <bitRange>[21:21]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD1_LEVEL_LOW</name>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD0_EDGE_HIGH</name>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD0_EDGE_LOW</name>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD0_LEVEL_HIGH</name>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD0_LEVEL_LOW</name>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SS_EDGE_HIGH</name>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SS_EDGE_LOW</name>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SS_LEVEL_HIGH</name>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SS_LEVEL_LOW</name>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SCLK_EDGE_HIGH</name>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SCLK_EDGE_LOW</name>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SCLK_LEVEL_HIGH</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SCLK_LEVEL_LOW</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>USBPHY_DM_EDGE_HIGH</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>USBPHY_DM_EDGE_LOW</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>USBPHY_DM_LEVEL_HIGH</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>USBPHY_DM_LEVEL_LOW</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>USBPHY_DP_EDGE_HIGH</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>USBPHY_DP_EDGE_LOW</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>USBPHY_DP_LEVEL_HIGH</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>USBPHY_DP_LEVEL_LOW</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PROC1_INTE</name>
+                <addressOffset>0x00000228</addressOffset>
+                <description>Interrupt Enable for proc1</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>GPIO_QSPI_SD3_EDGE_HIGH</name>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD3_EDGE_LOW</name>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD3_LEVEL_HIGH</name>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD3_LEVEL_LOW</name>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD2_EDGE_HIGH</name>
+                        <bitRange>[27:27]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD2_EDGE_LOW</name>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD2_LEVEL_HIGH</name>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD2_LEVEL_LOW</name>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD1_EDGE_HIGH</name>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD1_EDGE_LOW</name>
+                        <bitRange>[22:22]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD1_LEVEL_HIGH</name>
+                        <bitRange>[21:21]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD1_LEVEL_LOW</name>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD0_EDGE_HIGH</name>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD0_EDGE_LOW</name>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD0_LEVEL_HIGH</name>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD0_LEVEL_LOW</name>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SS_EDGE_HIGH</name>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SS_EDGE_LOW</name>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SS_LEVEL_HIGH</name>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SS_LEVEL_LOW</name>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SCLK_EDGE_HIGH</name>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SCLK_EDGE_LOW</name>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SCLK_LEVEL_HIGH</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SCLK_LEVEL_LOW</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>USBPHY_DM_EDGE_HIGH</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>USBPHY_DM_EDGE_LOW</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>USBPHY_DM_LEVEL_HIGH</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>USBPHY_DM_LEVEL_LOW</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>USBPHY_DP_EDGE_HIGH</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>USBPHY_DP_EDGE_LOW</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>USBPHY_DP_LEVEL_HIGH</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>USBPHY_DP_LEVEL_LOW</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PROC1_INTF</name>
+                <addressOffset>0x0000022c</addressOffset>
+                <description>Interrupt Force for proc1</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>GPIO_QSPI_SD3_EDGE_HIGH</name>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD3_EDGE_LOW</name>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD3_LEVEL_HIGH</name>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD3_LEVEL_LOW</name>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD2_EDGE_HIGH</name>
+                        <bitRange>[27:27]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD2_EDGE_LOW</name>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD2_LEVEL_HIGH</name>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD2_LEVEL_LOW</name>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD1_EDGE_HIGH</name>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD1_EDGE_LOW</name>
+                        <bitRange>[22:22]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD1_LEVEL_HIGH</name>
+                        <bitRange>[21:21]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD1_LEVEL_LOW</name>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD0_EDGE_HIGH</name>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD0_EDGE_LOW</name>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD0_LEVEL_HIGH</name>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD0_LEVEL_LOW</name>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SS_EDGE_HIGH</name>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SS_EDGE_LOW</name>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SS_LEVEL_HIGH</name>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SS_LEVEL_LOW</name>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SCLK_EDGE_HIGH</name>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SCLK_EDGE_LOW</name>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SCLK_LEVEL_HIGH</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SCLK_LEVEL_LOW</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>USBPHY_DM_EDGE_HIGH</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>USBPHY_DM_EDGE_LOW</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>USBPHY_DM_LEVEL_HIGH</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>USBPHY_DM_LEVEL_LOW</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>USBPHY_DP_EDGE_HIGH</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>USBPHY_DP_EDGE_LOW</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>USBPHY_DP_LEVEL_HIGH</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>USBPHY_DP_LEVEL_LOW</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PROC1_INTS</name>
+                <addressOffset>0x00000230</addressOffset>
+                <description>Interrupt status after masking &amp; forcing for proc1</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>GPIO_QSPI_SD3_EDGE_HIGH</name>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD3_EDGE_LOW</name>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD3_LEVEL_HIGH</name>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD3_LEVEL_LOW</name>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD2_EDGE_HIGH</name>
+                        <bitRange>[27:27]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD2_EDGE_LOW</name>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD2_LEVEL_HIGH</name>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD2_LEVEL_LOW</name>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD1_EDGE_HIGH</name>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD1_EDGE_LOW</name>
+                        <bitRange>[22:22]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD1_LEVEL_HIGH</name>
+                        <bitRange>[21:21]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD1_LEVEL_LOW</name>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD0_EDGE_HIGH</name>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD0_EDGE_LOW</name>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD0_LEVEL_HIGH</name>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD0_LEVEL_LOW</name>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SS_EDGE_HIGH</name>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SS_EDGE_LOW</name>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SS_LEVEL_HIGH</name>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SS_LEVEL_LOW</name>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SCLK_EDGE_HIGH</name>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SCLK_EDGE_LOW</name>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SCLK_LEVEL_HIGH</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SCLK_LEVEL_LOW</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>USBPHY_DM_EDGE_HIGH</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>USBPHY_DM_EDGE_LOW</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>USBPHY_DM_LEVEL_HIGH</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>USBPHY_DM_LEVEL_LOW</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>USBPHY_DP_EDGE_HIGH</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>USBPHY_DP_EDGE_LOW</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>USBPHY_DP_LEVEL_HIGH</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>USBPHY_DP_LEVEL_LOW</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>DORMANT_WAKE_INTE</name>
+                <addressOffset>0x00000234</addressOffset>
+                <description>Interrupt Enable for dormant_wake</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>GPIO_QSPI_SD3_EDGE_HIGH</name>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD3_EDGE_LOW</name>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD3_LEVEL_HIGH</name>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD3_LEVEL_LOW</name>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD2_EDGE_HIGH</name>
+                        <bitRange>[27:27]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD2_EDGE_LOW</name>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD2_LEVEL_HIGH</name>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD2_LEVEL_LOW</name>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD1_EDGE_HIGH</name>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD1_EDGE_LOW</name>
+                        <bitRange>[22:22]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD1_LEVEL_HIGH</name>
+                        <bitRange>[21:21]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD1_LEVEL_LOW</name>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD0_EDGE_HIGH</name>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD0_EDGE_LOW</name>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD0_LEVEL_HIGH</name>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD0_LEVEL_LOW</name>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SS_EDGE_HIGH</name>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SS_EDGE_LOW</name>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SS_LEVEL_HIGH</name>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SS_LEVEL_LOW</name>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SCLK_EDGE_HIGH</name>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SCLK_EDGE_LOW</name>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SCLK_LEVEL_HIGH</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SCLK_LEVEL_LOW</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>USBPHY_DM_EDGE_HIGH</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>USBPHY_DM_EDGE_LOW</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>USBPHY_DM_LEVEL_HIGH</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>USBPHY_DM_LEVEL_LOW</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>USBPHY_DP_EDGE_HIGH</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>USBPHY_DP_EDGE_LOW</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>USBPHY_DP_LEVEL_HIGH</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>USBPHY_DP_LEVEL_LOW</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>DORMANT_WAKE_INTF</name>
+                <addressOffset>0x00000238</addressOffset>
+                <description>Interrupt Force for dormant_wake</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>GPIO_QSPI_SD3_EDGE_HIGH</name>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD3_EDGE_LOW</name>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD3_LEVEL_HIGH</name>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD3_LEVEL_LOW</name>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD2_EDGE_HIGH</name>
+                        <bitRange>[27:27]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD2_EDGE_LOW</name>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD2_LEVEL_HIGH</name>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD2_LEVEL_LOW</name>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD1_EDGE_HIGH</name>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD1_EDGE_LOW</name>
+                        <bitRange>[22:22]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD1_LEVEL_HIGH</name>
+                        <bitRange>[21:21]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD1_LEVEL_LOW</name>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD0_EDGE_HIGH</name>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD0_EDGE_LOW</name>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD0_LEVEL_HIGH</name>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD0_LEVEL_LOW</name>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SS_EDGE_HIGH</name>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SS_EDGE_LOW</name>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SS_LEVEL_HIGH</name>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SS_LEVEL_LOW</name>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SCLK_EDGE_HIGH</name>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SCLK_EDGE_LOW</name>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SCLK_LEVEL_HIGH</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SCLK_LEVEL_LOW</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>USBPHY_DM_EDGE_HIGH</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>USBPHY_DM_EDGE_LOW</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>USBPHY_DM_LEVEL_HIGH</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>USBPHY_DM_LEVEL_LOW</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>USBPHY_DP_EDGE_HIGH</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>USBPHY_DP_EDGE_LOW</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>USBPHY_DP_LEVEL_HIGH</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>USBPHY_DP_LEVEL_LOW</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>DORMANT_WAKE_INTS</name>
+                <addressOffset>0x0000023c</addressOffset>
+                <description>Interrupt status after masking &amp; forcing for dormant_wake</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>GPIO_QSPI_SD3_EDGE_HIGH</name>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD3_EDGE_LOW</name>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD3_LEVEL_HIGH</name>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD3_LEVEL_LOW</name>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD2_EDGE_HIGH</name>
+                        <bitRange>[27:27]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD2_EDGE_LOW</name>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD2_LEVEL_HIGH</name>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD2_LEVEL_LOW</name>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD1_EDGE_HIGH</name>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD1_EDGE_LOW</name>
+                        <bitRange>[22:22]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD1_LEVEL_HIGH</name>
+                        <bitRange>[21:21]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD1_LEVEL_LOW</name>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD0_EDGE_HIGH</name>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD0_EDGE_LOW</name>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD0_LEVEL_HIGH</name>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SD0_LEVEL_LOW</name>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SS_EDGE_HIGH</name>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SS_EDGE_LOW</name>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SS_LEVEL_HIGH</name>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SS_LEVEL_LOW</name>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SCLK_EDGE_HIGH</name>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SCLK_EDGE_LOW</name>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SCLK_LEVEL_HIGH</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO_QSPI_SCLK_LEVEL_LOW</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>USBPHY_DM_EDGE_HIGH</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>USBPHY_DM_EDGE_LOW</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>USBPHY_DM_LEVEL_HIGH</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>USBPHY_DM_LEVEL_LOW</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>USBPHY_DP_EDGE_HIGH</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>USBPHY_DP_EDGE_LOW</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>USBPHY_DP_LEVEL_HIGH</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>USBPHY_DP_LEVEL_LOW</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+        </registers>
+    </peripheral>
+    <peripheral>
+        <name>IO_BANK0</name>
+        <baseAddress>0x40028000</baseAddress>
+        <addressBlock>
+            <offset>0</offset>
+            <size>800</size>
+            <usage>registers</usage>
+        </addressBlock>
+        <interrupt>
+            <name>IO_IRQ_BANK0</name>
+            <value>21</value>
+        </interrupt>
+        <interrupt>
+            <name>IO_IRQ_BANK0_NS</name>
+            <value>22</value>
+        </interrupt>
+        <registers>
+            <register>
+                <name>GPIO0_STATUS</name>
+                <addressOffset>0x00000000</addressOffset>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>IRQTOPROC</name>
+                        <description>interrupt to processors, after override is applied</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>INFROMPAD</name>
+                        <description>input signal from pad, before filtering and override are applied</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OETOPAD</name>
+                        <description>output enable to pad after register override is applied</description>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OUTTOPAD</name>
+                        <description>output signal to pad after register override is applied</description>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO0_CTRL</name>
+                <addressOffset>0x00000004</addressOffset>
+                <resetValue>0x0000001f</resetValue>
+                <fields>
+                    <field>
+                        <name>IRQOVER</name>
+                        <bitRange>[29:28]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>don&#39;t invert the interrupt</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>invert the interrupt</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive interrupt low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive interrupt high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>INOVER</name>
+                        <bitRange>[17:16]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>don&#39;t invert the peri input</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>invert the peri input</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive peri input low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive peri input high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>OEOVER</name>
+                        <bitRange>[15:14]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>drive output enable from peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>DISABLE</name>
+                                <value>2</value>
+                                <description>disable output</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ENABLE</name>
+                                <value>3</value>
+                                <description>enable output</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>OUTOVER</name>
+                        <bitRange>[13:12]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>drive output from peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>drive output from inverse of peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive output low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive output high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>FUNCSEL</name>
+                        <description>0-31 -&gt; selects pin function according to the gpio table 
+                            31 == NULL</description>
+                        <bitRange>[4:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>jtag_tck</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>spi0_rx</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>uart0_tx</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>i2c0_sda</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pwm_a_0</name>
+                                <value>4</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>siob_proc_0</name>
+                                <value>5</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio0_0</name>
+                                <value>6</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio1_0</name>
+                                <value>7</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio2_0</name>
+                                <value>8</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>xip_ss_n_1</name>
+                                <value>9</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>usb_muxing_overcurr_detect</name>
+                                <value>10</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>null</name>
+                                <value>31</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO1_STATUS</name>
+                <addressOffset>0x00000008</addressOffset>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>IRQTOPROC</name>
+                        <description>interrupt to processors, after override is applied</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>INFROMPAD</name>
+                        <description>input signal from pad, before filtering and override are applied</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OETOPAD</name>
+                        <description>output enable to pad after register override is applied</description>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OUTTOPAD</name>
+                        <description>output signal to pad after register override is applied</description>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO1_CTRL</name>
+                <addressOffset>0x0000000c</addressOffset>
+                <resetValue>0x0000001f</resetValue>
+                <fields>
+                    <field>
+                        <name>IRQOVER</name>
+                        <bitRange>[29:28]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>don&#39;t invert the interrupt</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>invert the interrupt</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive interrupt low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive interrupt high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>INOVER</name>
+                        <bitRange>[17:16]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>don&#39;t invert the peri input</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>invert the peri input</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive peri input low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive peri input high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>OEOVER</name>
+                        <bitRange>[15:14]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>drive output enable from peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>DISABLE</name>
+                                <value>2</value>
+                                <description>disable output</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ENABLE</name>
+                                <value>3</value>
+                                <description>enable output</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>OUTOVER</name>
+                        <bitRange>[13:12]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>drive output from peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>drive output from inverse of peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive output low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive output high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>FUNCSEL</name>
+                        <description>0-31 -&gt; selects pin function according to the gpio table 
+                            31 == NULL</description>
+                        <bitRange>[4:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>jtag_tms</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>spi0_ss_n</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>uart0_rx</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>i2c0_scl</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pwm_b_0</name>
+                                <value>4</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>siob_proc_1</name>
+                                <value>5</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio0_1</name>
+                                <value>6</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio1_1</name>
+                                <value>7</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio2_1</name>
+                                <value>8</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>coresight_traceclk</name>
+                                <value>9</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>usb_muxing_vbus_detect</name>
+                                <value>10</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>null</name>
+                                <value>31</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO2_STATUS</name>
+                <addressOffset>0x00000010</addressOffset>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>IRQTOPROC</name>
+                        <description>interrupt to processors, after override is applied</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>INFROMPAD</name>
+                        <description>input signal from pad, before filtering and override are applied</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OETOPAD</name>
+                        <description>output enable to pad after register override is applied</description>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OUTTOPAD</name>
+                        <description>output signal to pad after register override is applied</description>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO2_CTRL</name>
+                <addressOffset>0x00000014</addressOffset>
+                <resetValue>0x0000001f</resetValue>
+                <fields>
+                    <field>
+                        <name>IRQOVER</name>
+                        <bitRange>[29:28]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>don&#39;t invert the interrupt</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>invert the interrupt</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive interrupt low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive interrupt high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>INOVER</name>
+                        <bitRange>[17:16]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>don&#39;t invert the peri input</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>invert the peri input</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive peri input low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive peri input high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>OEOVER</name>
+                        <bitRange>[15:14]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>drive output enable from peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>DISABLE</name>
+                                <value>2</value>
+                                <description>disable output</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ENABLE</name>
+                                <value>3</value>
+                                <description>enable output</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>OUTOVER</name>
+                        <bitRange>[13:12]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>drive output from peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>drive output from inverse of peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive output low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive output high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>FUNCSEL</name>
+                        <description>0-31 -&gt; selects pin function according to the gpio table 
+                            31 == NULL</description>
+                        <bitRange>[4:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>jtag_tdi</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>spi0_sclk</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>uart0_cts</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>i2c1_sda</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pwm_a_1</name>
+                                <value>4</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>siob_proc_2</name>
+                                <value>5</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio0_2</name>
+                                <value>6</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio1_2</name>
+                                <value>7</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio2_2</name>
+                                <value>8</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>coresight_tracedata_0</name>
+                                <value>9</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>usb_muxing_vbus_en</name>
+                                <value>10</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>uart0_tx</name>
+                                <value>11</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>null</name>
+                                <value>31</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO3_STATUS</name>
+                <addressOffset>0x00000018</addressOffset>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>IRQTOPROC</name>
+                        <description>interrupt to processors, after override is applied</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>INFROMPAD</name>
+                        <description>input signal from pad, before filtering and override are applied</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OETOPAD</name>
+                        <description>output enable to pad after register override is applied</description>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OUTTOPAD</name>
+                        <description>output signal to pad after register override is applied</description>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO3_CTRL</name>
+                <addressOffset>0x0000001c</addressOffset>
+                <resetValue>0x0000001f</resetValue>
+                <fields>
+                    <field>
+                        <name>IRQOVER</name>
+                        <bitRange>[29:28]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>don&#39;t invert the interrupt</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>invert the interrupt</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive interrupt low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive interrupt high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>INOVER</name>
+                        <bitRange>[17:16]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>don&#39;t invert the peri input</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>invert the peri input</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive peri input low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive peri input high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>OEOVER</name>
+                        <bitRange>[15:14]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>drive output enable from peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>DISABLE</name>
+                                <value>2</value>
+                                <description>disable output</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ENABLE</name>
+                                <value>3</value>
+                                <description>enable output</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>OUTOVER</name>
+                        <bitRange>[13:12]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>drive output from peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>drive output from inverse of peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive output low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive output high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>FUNCSEL</name>
+                        <description>0-31 -&gt; selects pin function according to the gpio table 
+                            31 == NULL</description>
+                        <bitRange>[4:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>jtag_tdo</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>spi0_tx</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>uart0_rts</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>i2c1_scl</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pwm_b_1</name>
+                                <value>4</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>siob_proc_3</name>
+                                <value>5</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio0_3</name>
+                                <value>6</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio1_3</name>
+                                <value>7</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio2_3</name>
+                                <value>8</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>coresight_tracedata_1</name>
+                                <value>9</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>usb_muxing_overcurr_detect</name>
+                                <value>10</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>uart0_rx</name>
+                                <value>11</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>null</name>
+                                <value>31</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO4_STATUS</name>
+                <addressOffset>0x00000020</addressOffset>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>IRQTOPROC</name>
+                        <description>interrupt to processors, after override is applied</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>INFROMPAD</name>
+                        <description>input signal from pad, before filtering and override are applied</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OETOPAD</name>
+                        <description>output enable to pad after register override is applied</description>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OUTTOPAD</name>
+                        <description>output signal to pad after register override is applied</description>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO4_CTRL</name>
+                <addressOffset>0x00000024</addressOffset>
+                <resetValue>0x0000001f</resetValue>
+                <fields>
+                    <field>
+                        <name>IRQOVER</name>
+                        <bitRange>[29:28]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>don&#39;t invert the interrupt</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>invert the interrupt</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive interrupt low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive interrupt high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>INOVER</name>
+                        <bitRange>[17:16]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>don&#39;t invert the peri input</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>invert the peri input</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive peri input low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive peri input high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>OEOVER</name>
+                        <bitRange>[15:14]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>drive output enable from peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>DISABLE</name>
+                                <value>2</value>
+                                <description>disable output</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ENABLE</name>
+                                <value>3</value>
+                                <description>enable output</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>OUTOVER</name>
+                        <bitRange>[13:12]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>drive output from peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>drive output from inverse of peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive output low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive output high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>FUNCSEL</name>
+                        <description>0-31 -&gt; selects pin function according to the gpio table 
+                            31 == NULL</description>
+                        <bitRange>[4:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>spi0_rx</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>uart1_tx</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>i2c0_sda</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pwm_a_2</name>
+                                <value>4</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>siob_proc_4</name>
+                                <value>5</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio0_4</name>
+                                <value>6</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio1_4</name>
+                                <value>7</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio2_4</name>
+                                <value>8</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>coresight_tracedata_2</name>
+                                <value>9</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>usb_muxing_vbus_detect</name>
+                                <value>10</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>null</name>
+                                <value>31</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO5_STATUS</name>
+                <addressOffset>0x00000028</addressOffset>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>IRQTOPROC</name>
+                        <description>interrupt to processors, after override is applied</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>INFROMPAD</name>
+                        <description>input signal from pad, before filtering and override are applied</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OETOPAD</name>
+                        <description>output enable to pad after register override is applied</description>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OUTTOPAD</name>
+                        <description>output signal to pad after register override is applied</description>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO5_CTRL</name>
+                <addressOffset>0x0000002c</addressOffset>
+                <resetValue>0x0000001f</resetValue>
+                <fields>
+                    <field>
+                        <name>IRQOVER</name>
+                        <bitRange>[29:28]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>don&#39;t invert the interrupt</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>invert the interrupt</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive interrupt low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive interrupt high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>INOVER</name>
+                        <bitRange>[17:16]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>don&#39;t invert the peri input</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>invert the peri input</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive peri input low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive peri input high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>OEOVER</name>
+                        <bitRange>[15:14]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>drive output enable from peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>DISABLE</name>
+                                <value>2</value>
+                                <description>disable output</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ENABLE</name>
+                                <value>3</value>
+                                <description>enable output</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>OUTOVER</name>
+                        <bitRange>[13:12]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>drive output from peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>drive output from inverse of peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive output low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive output high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>FUNCSEL</name>
+                        <description>0-31 -&gt; selects pin function according to the gpio table 
+                            31 == NULL</description>
+                        <bitRange>[4:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>spi0_ss_n</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>uart1_rx</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>i2c0_scl</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pwm_b_2</name>
+                                <value>4</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>siob_proc_5</name>
+                                <value>5</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio0_5</name>
+                                <value>6</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio1_5</name>
+                                <value>7</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio2_5</name>
+                                <value>8</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>coresight_tracedata_3</name>
+                                <value>9</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>usb_muxing_vbus_en</name>
+                                <value>10</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>null</name>
+                                <value>31</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO6_STATUS</name>
+                <addressOffset>0x00000030</addressOffset>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>IRQTOPROC</name>
+                        <description>interrupt to processors, after override is applied</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>INFROMPAD</name>
+                        <description>input signal from pad, before filtering and override are applied</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OETOPAD</name>
+                        <description>output enable to pad after register override is applied</description>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OUTTOPAD</name>
+                        <description>output signal to pad after register override is applied</description>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO6_CTRL</name>
+                <addressOffset>0x00000034</addressOffset>
+                <resetValue>0x0000001f</resetValue>
+                <fields>
+                    <field>
+                        <name>IRQOVER</name>
+                        <bitRange>[29:28]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>don&#39;t invert the interrupt</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>invert the interrupt</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive interrupt low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive interrupt high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>INOVER</name>
+                        <bitRange>[17:16]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>don&#39;t invert the peri input</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>invert the peri input</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive peri input low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive peri input high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>OEOVER</name>
+                        <bitRange>[15:14]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>drive output enable from peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>DISABLE</name>
+                                <value>2</value>
+                                <description>disable output</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ENABLE</name>
+                                <value>3</value>
+                                <description>enable output</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>OUTOVER</name>
+                        <bitRange>[13:12]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>drive output from peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>drive output from inverse of peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive output low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive output high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>FUNCSEL</name>
+                        <description>0-31 -&gt; selects pin function according to the gpio table 
+                            31 == NULL</description>
+                        <bitRange>[4:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>spi0_sclk</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>uart1_cts</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>i2c1_sda</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pwm_a_3</name>
+                                <value>4</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>siob_proc_6</name>
+                                <value>5</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio0_6</name>
+                                <value>6</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio1_6</name>
+                                <value>7</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio2_6</name>
+                                <value>8</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>usb_muxing_overcurr_detect</name>
+                                <value>10</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>uart1_tx</name>
+                                <value>11</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>null</name>
+                                <value>31</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO7_STATUS</name>
+                <addressOffset>0x00000038</addressOffset>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>IRQTOPROC</name>
+                        <description>interrupt to processors, after override is applied</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>INFROMPAD</name>
+                        <description>input signal from pad, before filtering and override are applied</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OETOPAD</name>
+                        <description>output enable to pad after register override is applied</description>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OUTTOPAD</name>
+                        <description>output signal to pad after register override is applied</description>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO7_CTRL</name>
+                <addressOffset>0x0000003c</addressOffset>
+                <resetValue>0x0000001f</resetValue>
+                <fields>
+                    <field>
+                        <name>IRQOVER</name>
+                        <bitRange>[29:28]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>don&#39;t invert the interrupt</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>invert the interrupt</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive interrupt low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive interrupt high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>INOVER</name>
+                        <bitRange>[17:16]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>don&#39;t invert the peri input</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>invert the peri input</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive peri input low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive peri input high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>OEOVER</name>
+                        <bitRange>[15:14]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>drive output enable from peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>DISABLE</name>
+                                <value>2</value>
+                                <description>disable output</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ENABLE</name>
+                                <value>3</value>
+                                <description>enable output</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>OUTOVER</name>
+                        <bitRange>[13:12]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>drive output from peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>drive output from inverse of peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive output low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive output high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>FUNCSEL</name>
+                        <description>0-31 -&gt; selects pin function according to the gpio table 
+                            31 == NULL</description>
+                        <bitRange>[4:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>spi0_tx</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>uart1_rts</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>i2c1_scl</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pwm_b_3</name>
+                                <value>4</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>siob_proc_7</name>
+                                <value>5</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio0_7</name>
+                                <value>6</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio1_7</name>
+                                <value>7</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio2_7</name>
+                                <value>8</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>usb_muxing_vbus_detect</name>
+                                <value>10</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>uart1_rx</name>
+                                <value>11</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>null</name>
+                                <value>31</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO8_STATUS</name>
+                <addressOffset>0x00000040</addressOffset>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>IRQTOPROC</name>
+                        <description>interrupt to processors, after override is applied</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>INFROMPAD</name>
+                        <description>input signal from pad, before filtering and override are applied</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OETOPAD</name>
+                        <description>output enable to pad after register override is applied</description>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OUTTOPAD</name>
+                        <description>output signal to pad after register override is applied</description>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO8_CTRL</name>
+                <addressOffset>0x00000044</addressOffset>
+                <resetValue>0x0000001f</resetValue>
+                <fields>
+                    <field>
+                        <name>IRQOVER</name>
+                        <bitRange>[29:28]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>don&#39;t invert the interrupt</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>invert the interrupt</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive interrupt low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive interrupt high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>INOVER</name>
+                        <bitRange>[17:16]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>don&#39;t invert the peri input</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>invert the peri input</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive peri input low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive peri input high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>OEOVER</name>
+                        <bitRange>[15:14]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>drive output enable from peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>DISABLE</name>
+                                <value>2</value>
+                                <description>disable output</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ENABLE</name>
+                                <value>3</value>
+                                <description>enable output</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>OUTOVER</name>
+                        <bitRange>[13:12]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>drive output from peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>drive output from inverse of peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive output low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive output high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>FUNCSEL</name>
+                        <description>0-31 -&gt; selects pin function according to the gpio table 
+                            31 == NULL</description>
+                        <bitRange>[4:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>spi1_rx</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>uart1_tx</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>i2c0_sda</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pwm_a_4</name>
+                                <value>4</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>siob_proc_8</name>
+                                <value>5</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio0_8</name>
+                                <value>6</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio1_8</name>
+                                <value>7</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio2_8</name>
+                                <value>8</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>xip_ss_n_1</name>
+                                <value>9</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>usb_muxing_vbus_en</name>
+                                <value>10</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>null</name>
+                                <value>31</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO9_STATUS</name>
+                <addressOffset>0x00000048</addressOffset>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>IRQTOPROC</name>
+                        <description>interrupt to processors, after override is applied</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>INFROMPAD</name>
+                        <description>input signal from pad, before filtering and override are applied</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OETOPAD</name>
+                        <description>output enable to pad after register override is applied</description>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OUTTOPAD</name>
+                        <description>output signal to pad after register override is applied</description>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO9_CTRL</name>
+                <addressOffset>0x0000004c</addressOffset>
+                <resetValue>0x0000001f</resetValue>
+                <fields>
+                    <field>
+                        <name>IRQOVER</name>
+                        <bitRange>[29:28]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>don&#39;t invert the interrupt</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>invert the interrupt</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive interrupt low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive interrupt high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>INOVER</name>
+                        <bitRange>[17:16]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>don&#39;t invert the peri input</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>invert the peri input</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive peri input low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive peri input high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>OEOVER</name>
+                        <bitRange>[15:14]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>drive output enable from peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>DISABLE</name>
+                                <value>2</value>
+                                <description>disable output</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ENABLE</name>
+                                <value>3</value>
+                                <description>enable output</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>OUTOVER</name>
+                        <bitRange>[13:12]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>drive output from peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>drive output from inverse of peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive output low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive output high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>FUNCSEL</name>
+                        <description>0-31 -&gt; selects pin function according to the gpio table 
+                            31 == NULL</description>
+                        <bitRange>[4:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>spi1_ss_n</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>uart1_rx</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>i2c0_scl</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pwm_b_4</name>
+                                <value>4</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>siob_proc_9</name>
+                                <value>5</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio0_9</name>
+                                <value>6</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio1_9</name>
+                                <value>7</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio2_9</name>
+                                <value>8</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>usb_muxing_overcurr_detect</name>
+                                <value>10</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>null</name>
+                                <value>31</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO10_STATUS</name>
+                <addressOffset>0x00000050</addressOffset>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>IRQTOPROC</name>
+                        <description>interrupt to processors, after override is applied</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>INFROMPAD</name>
+                        <description>input signal from pad, before filtering and override are applied</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OETOPAD</name>
+                        <description>output enable to pad after register override is applied</description>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OUTTOPAD</name>
+                        <description>output signal to pad after register override is applied</description>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO10_CTRL</name>
+                <addressOffset>0x00000054</addressOffset>
+                <resetValue>0x0000001f</resetValue>
+                <fields>
+                    <field>
+                        <name>IRQOVER</name>
+                        <bitRange>[29:28]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>don&#39;t invert the interrupt</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>invert the interrupt</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive interrupt low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive interrupt high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>INOVER</name>
+                        <bitRange>[17:16]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>don&#39;t invert the peri input</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>invert the peri input</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive peri input low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive peri input high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>OEOVER</name>
+                        <bitRange>[15:14]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>drive output enable from peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>DISABLE</name>
+                                <value>2</value>
+                                <description>disable output</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ENABLE</name>
+                                <value>3</value>
+                                <description>enable output</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>OUTOVER</name>
+                        <bitRange>[13:12]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>drive output from peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>drive output from inverse of peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive output low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive output high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>FUNCSEL</name>
+                        <description>0-31 -&gt; selects pin function according to the gpio table 
+                            31 == NULL</description>
+                        <bitRange>[4:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>spi1_sclk</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>uart1_cts</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>i2c1_sda</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pwm_a_5</name>
+                                <value>4</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>siob_proc_10</name>
+                                <value>5</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio0_10</name>
+                                <value>6</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio1_10</name>
+                                <value>7</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio2_10</name>
+                                <value>8</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>usb_muxing_vbus_detect</name>
+                                <value>10</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>uart1_tx</name>
+                                <value>11</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>null</name>
+                                <value>31</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO11_STATUS</name>
+                <addressOffset>0x00000058</addressOffset>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>IRQTOPROC</name>
+                        <description>interrupt to processors, after override is applied</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>INFROMPAD</name>
+                        <description>input signal from pad, before filtering and override are applied</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OETOPAD</name>
+                        <description>output enable to pad after register override is applied</description>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OUTTOPAD</name>
+                        <description>output signal to pad after register override is applied</description>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO11_CTRL</name>
+                <addressOffset>0x0000005c</addressOffset>
+                <resetValue>0x0000001f</resetValue>
+                <fields>
+                    <field>
+                        <name>IRQOVER</name>
+                        <bitRange>[29:28]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>don&#39;t invert the interrupt</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>invert the interrupt</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive interrupt low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive interrupt high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>INOVER</name>
+                        <bitRange>[17:16]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>don&#39;t invert the peri input</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>invert the peri input</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive peri input low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive peri input high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>OEOVER</name>
+                        <bitRange>[15:14]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>drive output enable from peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>DISABLE</name>
+                                <value>2</value>
+                                <description>disable output</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ENABLE</name>
+                                <value>3</value>
+                                <description>enable output</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>OUTOVER</name>
+                        <bitRange>[13:12]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>drive output from peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>drive output from inverse of peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive output low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive output high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>FUNCSEL</name>
+                        <description>0-31 -&gt; selects pin function according to the gpio table 
+                            31 == NULL</description>
+                        <bitRange>[4:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>spi1_tx</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>uart1_rts</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>i2c1_scl</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pwm_b_5</name>
+                                <value>4</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>siob_proc_11</name>
+                                <value>5</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio0_11</name>
+                                <value>6</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio1_11</name>
+                                <value>7</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio2_11</name>
+                                <value>8</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>usb_muxing_vbus_en</name>
+                                <value>10</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>uart1_rx</name>
+                                <value>11</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>null</name>
+                                <value>31</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO12_STATUS</name>
+                <addressOffset>0x00000060</addressOffset>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>IRQTOPROC</name>
+                        <description>interrupt to processors, after override is applied</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>INFROMPAD</name>
+                        <description>input signal from pad, before filtering and override are applied</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OETOPAD</name>
+                        <description>output enable to pad after register override is applied</description>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OUTTOPAD</name>
+                        <description>output signal to pad after register override is applied</description>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO12_CTRL</name>
+                <addressOffset>0x00000064</addressOffset>
+                <resetValue>0x0000001f</resetValue>
+                <fields>
+                    <field>
+                        <name>IRQOVER</name>
+                        <bitRange>[29:28]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>don&#39;t invert the interrupt</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>invert the interrupt</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive interrupt low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive interrupt high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>INOVER</name>
+                        <bitRange>[17:16]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>don&#39;t invert the peri input</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>invert the peri input</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive peri input low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive peri input high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>OEOVER</name>
+                        <bitRange>[15:14]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>drive output enable from peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>DISABLE</name>
+                                <value>2</value>
+                                <description>disable output</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ENABLE</name>
+                                <value>3</value>
+                                <description>enable output</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>OUTOVER</name>
+                        <bitRange>[13:12]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>drive output from peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>drive output from inverse of peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive output low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive output high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>FUNCSEL</name>
+                        <description>0-31 -&gt; selects pin function according to the gpio table 
+                            31 == NULL</description>
+                        <bitRange>[4:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>hstx_0</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>spi1_rx</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>uart0_tx</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>i2c0_sda</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pwm_a_6</name>
+                                <value>4</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>siob_proc_12</name>
+                                <value>5</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio0_12</name>
+                                <value>6</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio1_12</name>
+                                <value>7</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio2_12</name>
+                                <value>8</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>clocks_gpin_0</name>
+                                <value>9</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>usb_muxing_overcurr_detect</name>
+                                <value>10</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>null</name>
+                                <value>31</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO13_STATUS</name>
+                <addressOffset>0x00000068</addressOffset>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>IRQTOPROC</name>
+                        <description>interrupt to processors, after override is applied</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>INFROMPAD</name>
+                        <description>input signal from pad, before filtering and override are applied</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OETOPAD</name>
+                        <description>output enable to pad after register override is applied</description>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OUTTOPAD</name>
+                        <description>output signal to pad after register override is applied</description>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO13_CTRL</name>
+                <addressOffset>0x0000006c</addressOffset>
+                <resetValue>0x0000001f</resetValue>
+                <fields>
+                    <field>
+                        <name>IRQOVER</name>
+                        <bitRange>[29:28]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>don&#39;t invert the interrupt</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>invert the interrupt</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive interrupt low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive interrupt high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>INOVER</name>
+                        <bitRange>[17:16]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>don&#39;t invert the peri input</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>invert the peri input</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive peri input low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive peri input high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>OEOVER</name>
+                        <bitRange>[15:14]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>drive output enable from peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>DISABLE</name>
+                                <value>2</value>
+                                <description>disable output</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ENABLE</name>
+                                <value>3</value>
+                                <description>enable output</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>OUTOVER</name>
+                        <bitRange>[13:12]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>drive output from peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>drive output from inverse of peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive output low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive output high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>FUNCSEL</name>
+                        <description>0-31 -&gt; selects pin function according to the gpio table 
+                            31 == NULL</description>
+                        <bitRange>[4:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>hstx_1</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>spi1_ss_n</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>uart0_rx</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>i2c0_scl</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pwm_b_6</name>
+                                <value>4</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>siob_proc_13</name>
+                                <value>5</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio0_13</name>
+                                <value>6</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio1_13</name>
+                                <value>7</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio2_13</name>
+                                <value>8</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>clocks_gpout_0</name>
+                                <value>9</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>usb_muxing_vbus_detect</name>
+                                <value>10</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>null</name>
+                                <value>31</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO14_STATUS</name>
+                <addressOffset>0x00000070</addressOffset>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>IRQTOPROC</name>
+                        <description>interrupt to processors, after override is applied</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>INFROMPAD</name>
+                        <description>input signal from pad, before filtering and override are applied</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OETOPAD</name>
+                        <description>output enable to pad after register override is applied</description>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OUTTOPAD</name>
+                        <description>output signal to pad after register override is applied</description>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO14_CTRL</name>
+                <addressOffset>0x00000074</addressOffset>
+                <resetValue>0x0000001f</resetValue>
+                <fields>
+                    <field>
+                        <name>IRQOVER</name>
+                        <bitRange>[29:28]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>don&#39;t invert the interrupt</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>invert the interrupt</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive interrupt low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive interrupt high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>INOVER</name>
+                        <bitRange>[17:16]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>don&#39;t invert the peri input</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>invert the peri input</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive peri input low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive peri input high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>OEOVER</name>
+                        <bitRange>[15:14]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>drive output enable from peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>DISABLE</name>
+                                <value>2</value>
+                                <description>disable output</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ENABLE</name>
+                                <value>3</value>
+                                <description>enable output</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>OUTOVER</name>
+                        <bitRange>[13:12]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>drive output from peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>drive output from inverse of peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive output low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive output high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>FUNCSEL</name>
+                        <description>0-31 -&gt; selects pin function according to the gpio table 
+                            31 == NULL</description>
+                        <bitRange>[4:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>hstx_2</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>spi1_sclk</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>uart0_cts</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>i2c1_sda</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pwm_a_7</name>
+                                <value>4</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>siob_proc_14</name>
+                                <value>5</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio0_14</name>
+                                <value>6</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio1_14</name>
+                                <value>7</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio2_14</name>
+                                <value>8</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>clocks_gpin_1</name>
+                                <value>9</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>usb_muxing_vbus_en</name>
+                                <value>10</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>uart0_tx</name>
+                                <value>11</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>null</name>
+                                <value>31</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO15_STATUS</name>
+                <addressOffset>0x00000078</addressOffset>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>IRQTOPROC</name>
+                        <description>interrupt to processors, after override is applied</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>INFROMPAD</name>
+                        <description>input signal from pad, before filtering and override are applied</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OETOPAD</name>
+                        <description>output enable to pad after register override is applied</description>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OUTTOPAD</name>
+                        <description>output signal to pad after register override is applied</description>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO15_CTRL</name>
+                <addressOffset>0x0000007c</addressOffset>
+                <resetValue>0x0000001f</resetValue>
+                <fields>
+                    <field>
+                        <name>IRQOVER</name>
+                        <bitRange>[29:28]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>don&#39;t invert the interrupt</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>invert the interrupt</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive interrupt low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive interrupt high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>INOVER</name>
+                        <bitRange>[17:16]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>don&#39;t invert the peri input</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>invert the peri input</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive peri input low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive peri input high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>OEOVER</name>
+                        <bitRange>[15:14]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>drive output enable from peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>DISABLE</name>
+                                <value>2</value>
+                                <description>disable output</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ENABLE</name>
+                                <value>3</value>
+                                <description>enable output</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>OUTOVER</name>
+                        <bitRange>[13:12]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>drive output from peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>drive output from inverse of peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive output low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive output high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>FUNCSEL</name>
+                        <description>0-31 -&gt; selects pin function according to the gpio table 
+                            31 == NULL</description>
+                        <bitRange>[4:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>hstx_3</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>spi1_tx</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>uart0_rts</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>i2c1_scl</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pwm_b_7</name>
+                                <value>4</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>siob_proc_15</name>
+                                <value>5</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio0_15</name>
+                                <value>6</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio1_15</name>
+                                <value>7</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio2_15</name>
+                                <value>8</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>clocks_gpout_1</name>
+                                <value>9</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>usb_muxing_overcurr_detect</name>
+                                <value>10</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>uart0_rx</name>
+                                <value>11</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>null</name>
+                                <value>31</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO16_STATUS</name>
+                <addressOffset>0x00000080</addressOffset>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>IRQTOPROC</name>
+                        <description>interrupt to processors, after override is applied</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>INFROMPAD</name>
+                        <description>input signal from pad, before filtering and override are applied</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OETOPAD</name>
+                        <description>output enable to pad after register override is applied</description>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OUTTOPAD</name>
+                        <description>output signal to pad after register override is applied</description>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO16_CTRL</name>
+                <addressOffset>0x00000084</addressOffset>
+                <resetValue>0x0000001f</resetValue>
+                <fields>
+                    <field>
+                        <name>IRQOVER</name>
+                        <bitRange>[29:28]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>don&#39;t invert the interrupt</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>invert the interrupt</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive interrupt low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive interrupt high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>INOVER</name>
+                        <bitRange>[17:16]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>don&#39;t invert the peri input</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>invert the peri input</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive peri input low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive peri input high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>OEOVER</name>
+                        <bitRange>[15:14]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>drive output enable from peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>DISABLE</name>
+                                <value>2</value>
+                                <description>disable output</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ENABLE</name>
+                                <value>3</value>
+                                <description>enable output</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>OUTOVER</name>
+                        <bitRange>[13:12]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>drive output from peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>drive output from inverse of peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive output low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive output high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>FUNCSEL</name>
+                        <description>0-31 -&gt; selects pin function according to the gpio table 
+                            31 == NULL</description>
+                        <bitRange>[4:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>hstx_4</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>spi0_rx</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>uart0_tx</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>i2c0_sda</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pwm_a_0</name>
+                                <value>4</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>siob_proc_16</name>
+                                <value>5</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio0_16</name>
+                                <value>6</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio1_16</name>
+                                <value>7</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio2_16</name>
+                                <value>8</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>usb_muxing_vbus_detect</name>
+                                <value>10</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>null</name>
+                                <value>31</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO17_STATUS</name>
+                <addressOffset>0x00000088</addressOffset>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>IRQTOPROC</name>
+                        <description>interrupt to processors, after override is applied</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>INFROMPAD</name>
+                        <description>input signal from pad, before filtering and override are applied</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OETOPAD</name>
+                        <description>output enable to pad after register override is applied</description>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OUTTOPAD</name>
+                        <description>output signal to pad after register override is applied</description>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO17_CTRL</name>
+                <addressOffset>0x0000008c</addressOffset>
+                <resetValue>0x0000001f</resetValue>
+                <fields>
+                    <field>
+                        <name>IRQOVER</name>
+                        <bitRange>[29:28]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>don&#39;t invert the interrupt</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>invert the interrupt</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive interrupt low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive interrupt high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>INOVER</name>
+                        <bitRange>[17:16]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>don&#39;t invert the peri input</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>invert the peri input</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive peri input low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive peri input high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>OEOVER</name>
+                        <bitRange>[15:14]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>drive output enable from peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>DISABLE</name>
+                                <value>2</value>
+                                <description>disable output</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ENABLE</name>
+                                <value>3</value>
+                                <description>enable output</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>OUTOVER</name>
+                        <bitRange>[13:12]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>drive output from peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>drive output from inverse of peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive output low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive output high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>FUNCSEL</name>
+                        <description>0-31 -&gt; selects pin function according to the gpio table 
+                            31 == NULL</description>
+                        <bitRange>[4:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>hstx_5</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>spi0_ss_n</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>uart0_rx</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>i2c0_scl</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pwm_b_0</name>
+                                <value>4</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>siob_proc_17</name>
+                                <value>5</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio0_17</name>
+                                <value>6</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio1_17</name>
+                                <value>7</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio2_17</name>
+                                <value>8</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>usb_muxing_vbus_en</name>
+                                <value>10</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>null</name>
+                                <value>31</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO18_STATUS</name>
+                <addressOffset>0x00000090</addressOffset>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>IRQTOPROC</name>
+                        <description>interrupt to processors, after override is applied</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>INFROMPAD</name>
+                        <description>input signal from pad, before filtering and override are applied</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OETOPAD</name>
+                        <description>output enable to pad after register override is applied</description>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OUTTOPAD</name>
+                        <description>output signal to pad after register override is applied</description>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO18_CTRL</name>
+                <addressOffset>0x00000094</addressOffset>
+                <resetValue>0x0000001f</resetValue>
+                <fields>
+                    <field>
+                        <name>IRQOVER</name>
+                        <bitRange>[29:28]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>don&#39;t invert the interrupt</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>invert the interrupt</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive interrupt low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive interrupt high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>INOVER</name>
+                        <bitRange>[17:16]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>don&#39;t invert the peri input</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>invert the peri input</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive peri input low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive peri input high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>OEOVER</name>
+                        <bitRange>[15:14]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>drive output enable from peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>DISABLE</name>
+                                <value>2</value>
+                                <description>disable output</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ENABLE</name>
+                                <value>3</value>
+                                <description>enable output</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>OUTOVER</name>
+                        <bitRange>[13:12]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>drive output from peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>drive output from inverse of peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive output low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive output high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>FUNCSEL</name>
+                        <description>0-31 -&gt; selects pin function according to the gpio table 
+                            31 == NULL</description>
+                        <bitRange>[4:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>hstx_6</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>spi0_sclk</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>uart0_cts</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>i2c1_sda</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pwm_a_1</name>
+                                <value>4</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>siob_proc_18</name>
+                                <value>5</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio0_18</name>
+                                <value>6</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio1_18</name>
+                                <value>7</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio2_18</name>
+                                <value>8</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>usb_muxing_overcurr_detect</name>
+                                <value>10</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>uart0_tx</name>
+                                <value>11</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>null</name>
+                                <value>31</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO19_STATUS</name>
+                <addressOffset>0x00000098</addressOffset>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>IRQTOPROC</name>
+                        <description>interrupt to processors, after override is applied</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>INFROMPAD</name>
+                        <description>input signal from pad, before filtering and override are applied</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OETOPAD</name>
+                        <description>output enable to pad after register override is applied</description>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OUTTOPAD</name>
+                        <description>output signal to pad after register override is applied</description>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO19_CTRL</name>
+                <addressOffset>0x0000009c</addressOffset>
+                <resetValue>0x0000001f</resetValue>
+                <fields>
+                    <field>
+                        <name>IRQOVER</name>
+                        <bitRange>[29:28]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>don&#39;t invert the interrupt</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>invert the interrupt</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive interrupt low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive interrupt high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>INOVER</name>
+                        <bitRange>[17:16]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>don&#39;t invert the peri input</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>invert the peri input</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive peri input low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive peri input high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>OEOVER</name>
+                        <bitRange>[15:14]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>drive output enable from peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>DISABLE</name>
+                                <value>2</value>
+                                <description>disable output</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ENABLE</name>
+                                <value>3</value>
+                                <description>enable output</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>OUTOVER</name>
+                        <bitRange>[13:12]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>drive output from peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>drive output from inverse of peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive output low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive output high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>FUNCSEL</name>
+                        <description>0-31 -&gt; selects pin function according to the gpio table 
+                            31 == NULL</description>
+                        <bitRange>[4:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>hstx_7</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>spi0_tx</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>uart0_rts</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>i2c1_scl</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pwm_b_1</name>
+                                <value>4</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>siob_proc_19</name>
+                                <value>5</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio0_19</name>
+                                <value>6</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio1_19</name>
+                                <value>7</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio2_19</name>
+                                <value>8</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>xip_ss_n_1</name>
+                                <value>9</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>usb_muxing_vbus_detect</name>
+                                <value>10</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>uart0_rx</name>
+                                <value>11</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>null</name>
+                                <value>31</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO20_STATUS</name>
+                <addressOffset>0x000000a0</addressOffset>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>IRQTOPROC</name>
+                        <description>interrupt to processors, after override is applied</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>INFROMPAD</name>
+                        <description>input signal from pad, before filtering and override are applied</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OETOPAD</name>
+                        <description>output enable to pad after register override is applied</description>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OUTTOPAD</name>
+                        <description>output signal to pad after register override is applied</description>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO20_CTRL</name>
+                <addressOffset>0x000000a4</addressOffset>
+                <resetValue>0x0000001f</resetValue>
+                <fields>
+                    <field>
+                        <name>IRQOVER</name>
+                        <bitRange>[29:28]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>don&#39;t invert the interrupt</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>invert the interrupt</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive interrupt low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive interrupt high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>INOVER</name>
+                        <bitRange>[17:16]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>don&#39;t invert the peri input</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>invert the peri input</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive peri input low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive peri input high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>OEOVER</name>
+                        <bitRange>[15:14]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>drive output enable from peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>DISABLE</name>
+                                <value>2</value>
+                                <description>disable output</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ENABLE</name>
+                                <value>3</value>
+                                <description>enable output</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>OUTOVER</name>
+                        <bitRange>[13:12]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>drive output from peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>drive output from inverse of peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive output low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive output high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>FUNCSEL</name>
+                        <description>0-31 -&gt; selects pin function according to the gpio table 
+                            31 == NULL</description>
+                        <bitRange>[4:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>spi0_rx</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>uart1_tx</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>i2c0_sda</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pwm_a_2</name>
+                                <value>4</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>siob_proc_20</name>
+                                <value>5</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio0_20</name>
+                                <value>6</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio1_20</name>
+                                <value>7</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio2_20</name>
+                                <value>8</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>clocks_gpin_0</name>
+                                <value>9</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>usb_muxing_vbus_en</name>
+                                <value>10</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>null</name>
+                                <value>31</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO21_STATUS</name>
+                <addressOffset>0x000000a8</addressOffset>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>IRQTOPROC</name>
+                        <description>interrupt to processors, after override is applied</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>INFROMPAD</name>
+                        <description>input signal from pad, before filtering and override are applied</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OETOPAD</name>
+                        <description>output enable to pad after register override is applied</description>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OUTTOPAD</name>
+                        <description>output signal to pad after register override is applied</description>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO21_CTRL</name>
+                <addressOffset>0x000000ac</addressOffset>
+                <resetValue>0x0000001f</resetValue>
+                <fields>
+                    <field>
+                        <name>IRQOVER</name>
+                        <bitRange>[29:28]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>don&#39;t invert the interrupt</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>invert the interrupt</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive interrupt low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive interrupt high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>INOVER</name>
+                        <bitRange>[17:16]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>don&#39;t invert the peri input</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>invert the peri input</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive peri input low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive peri input high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>OEOVER</name>
+                        <bitRange>[15:14]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>drive output enable from peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>DISABLE</name>
+                                <value>2</value>
+                                <description>disable output</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ENABLE</name>
+                                <value>3</value>
+                                <description>enable output</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>OUTOVER</name>
+                        <bitRange>[13:12]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>drive output from peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>drive output from inverse of peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive output low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive output high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>FUNCSEL</name>
+                        <description>0-31 -&gt; selects pin function according to the gpio table 
+                            31 == NULL</description>
+                        <bitRange>[4:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>spi0_ss_n</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>uart1_rx</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>i2c0_scl</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pwm_b_2</name>
+                                <value>4</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>siob_proc_21</name>
+                                <value>5</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio0_21</name>
+                                <value>6</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio1_21</name>
+                                <value>7</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio2_21</name>
+                                <value>8</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>clocks_gpout_0</name>
+                                <value>9</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>usb_muxing_overcurr_detect</name>
+                                <value>10</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>null</name>
+                                <value>31</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO22_STATUS</name>
+                <addressOffset>0x000000b0</addressOffset>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>IRQTOPROC</name>
+                        <description>interrupt to processors, after override is applied</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>INFROMPAD</name>
+                        <description>input signal from pad, before filtering and override are applied</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OETOPAD</name>
+                        <description>output enable to pad after register override is applied</description>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OUTTOPAD</name>
+                        <description>output signal to pad after register override is applied</description>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO22_CTRL</name>
+                <addressOffset>0x000000b4</addressOffset>
+                <resetValue>0x0000001f</resetValue>
+                <fields>
+                    <field>
+                        <name>IRQOVER</name>
+                        <bitRange>[29:28]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>don&#39;t invert the interrupt</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>invert the interrupt</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive interrupt low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive interrupt high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>INOVER</name>
+                        <bitRange>[17:16]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>don&#39;t invert the peri input</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>invert the peri input</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive peri input low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive peri input high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>OEOVER</name>
+                        <bitRange>[15:14]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>drive output enable from peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>DISABLE</name>
+                                <value>2</value>
+                                <description>disable output</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ENABLE</name>
+                                <value>3</value>
+                                <description>enable output</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>OUTOVER</name>
+                        <bitRange>[13:12]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>drive output from peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>drive output from inverse of peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive output low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive output high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>FUNCSEL</name>
+                        <description>0-31 -&gt; selects pin function according to the gpio table 
+                            31 == NULL</description>
+                        <bitRange>[4:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>spi0_sclk</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>uart1_cts</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>i2c1_sda</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pwm_a_3</name>
+                                <value>4</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>siob_proc_22</name>
+                                <value>5</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio0_22</name>
+                                <value>6</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio1_22</name>
+                                <value>7</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio2_22</name>
+                                <value>8</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>clocks_gpin_1</name>
+                                <value>9</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>usb_muxing_vbus_detect</name>
+                                <value>10</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>uart1_tx</name>
+                                <value>11</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>null</name>
+                                <value>31</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO23_STATUS</name>
+                <addressOffset>0x000000b8</addressOffset>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>IRQTOPROC</name>
+                        <description>interrupt to processors, after override is applied</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>INFROMPAD</name>
+                        <description>input signal from pad, before filtering and override are applied</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OETOPAD</name>
+                        <description>output enable to pad after register override is applied</description>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OUTTOPAD</name>
+                        <description>output signal to pad after register override is applied</description>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO23_CTRL</name>
+                <addressOffset>0x000000bc</addressOffset>
+                <resetValue>0x0000001f</resetValue>
+                <fields>
+                    <field>
+                        <name>IRQOVER</name>
+                        <bitRange>[29:28]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>don&#39;t invert the interrupt</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>invert the interrupt</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive interrupt low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive interrupt high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>INOVER</name>
+                        <bitRange>[17:16]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>don&#39;t invert the peri input</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>invert the peri input</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive peri input low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive peri input high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>OEOVER</name>
+                        <bitRange>[15:14]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>drive output enable from peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>DISABLE</name>
+                                <value>2</value>
+                                <description>disable output</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ENABLE</name>
+                                <value>3</value>
+                                <description>enable output</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>OUTOVER</name>
+                        <bitRange>[13:12]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>drive output from peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>drive output from inverse of peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive output low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive output high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>FUNCSEL</name>
+                        <description>0-31 -&gt; selects pin function according to the gpio table 
+                            31 == NULL</description>
+                        <bitRange>[4:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>spi0_tx</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>uart1_rts</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>i2c1_scl</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pwm_b_3</name>
+                                <value>4</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>siob_proc_23</name>
+                                <value>5</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio0_23</name>
+                                <value>6</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio1_23</name>
+                                <value>7</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio2_23</name>
+                                <value>8</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>clocks_gpout_1</name>
+                                <value>9</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>usb_muxing_vbus_en</name>
+                                <value>10</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>uart1_rx</name>
+                                <value>11</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>null</name>
+                                <value>31</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO24_STATUS</name>
+                <addressOffset>0x000000c0</addressOffset>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>IRQTOPROC</name>
+                        <description>interrupt to processors, after override is applied</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>INFROMPAD</name>
+                        <description>input signal from pad, before filtering and override are applied</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OETOPAD</name>
+                        <description>output enable to pad after register override is applied</description>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OUTTOPAD</name>
+                        <description>output signal to pad after register override is applied</description>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO24_CTRL</name>
+                <addressOffset>0x000000c4</addressOffset>
+                <resetValue>0x0000001f</resetValue>
+                <fields>
+                    <field>
+                        <name>IRQOVER</name>
+                        <bitRange>[29:28]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>don&#39;t invert the interrupt</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>invert the interrupt</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive interrupt low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive interrupt high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>INOVER</name>
+                        <bitRange>[17:16]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>don&#39;t invert the peri input</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>invert the peri input</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive peri input low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive peri input high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>OEOVER</name>
+                        <bitRange>[15:14]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>drive output enable from peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>DISABLE</name>
+                                <value>2</value>
+                                <description>disable output</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ENABLE</name>
+                                <value>3</value>
+                                <description>enable output</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>OUTOVER</name>
+                        <bitRange>[13:12]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>drive output from peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>drive output from inverse of peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive output low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive output high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>FUNCSEL</name>
+                        <description>0-31 -&gt; selects pin function according to the gpio table 
+                            31 == NULL</description>
+                        <bitRange>[4:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>spi1_rx</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>uart1_tx</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>i2c0_sda</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pwm_a_4</name>
+                                <value>4</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>siob_proc_24</name>
+                                <value>5</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio0_24</name>
+                                <value>6</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio1_24</name>
+                                <value>7</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio2_24</name>
+                                <value>8</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>clocks_gpout_2</name>
+                                <value>9</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>usb_muxing_overcurr_detect</name>
+                                <value>10</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>null</name>
+                                <value>31</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO25_STATUS</name>
+                <addressOffset>0x000000c8</addressOffset>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>IRQTOPROC</name>
+                        <description>interrupt to processors, after override is applied</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>INFROMPAD</name>
+                        <description>input signal from pad, before filtering and override are applied</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OETOPAD</name>
+                        <description>output enable to pad after register override is applied</description>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OUTTOPAD</name>
+                        <description>output signal to pad after register override is applied</description>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO25_CTRL</name>
+                <addressOffset>0x000000cc</addressOffset>
+                <resetValue>0x0000001f</resetValue>
+                <fields>
+                    <field>
+                        <name>IRQOVER</name>
+                        <bitRange>[29:28]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>don&#39;t invert the interrupt</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>invert the interrupt</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive interrupt low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive interrupt high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>INOVER</name>
+                        <bitRange>[17:16]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>don&#39;t invert the peri input</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>invert the peri input</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive peri input low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive peri input high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>OEOVER</name>
+                        <bitRange>[15:14]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>drive output enable from peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>DISABLE</name>
+                                <value>2</value>
+                                <description>disable output</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ENABLE</name>
+                                <value>3</value>
+                                <description>enable output</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>OUTOVER</name>
+                        <bitRange>[13:12]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>drive output from peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>drive output from inverse of peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive output low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive output high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>FUNCSEL</name>
+                        <description>0-31 -&gt; selects pin function according to the gpio table 
+                            31 == NULL</description>
+                        <bitRange>[4:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>spi1_ss_n</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>uart1_rx</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>i2c0_scl</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pwm_b_4</name>
+                                <value>4</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>siob_proc_25</name>
+                                <value>5</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio0_25</name>
+                                <value>6</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio1_25</name>
+                                <value>7</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio2_25</name>
+                                <value>8</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>clocks_gpout_3</name>
+                                <value>9</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>usb_muxing_vbus_detect</name>
+                                <value>10</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>null</name>
+                                <value>31</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO26_STATUS</name>
+                <addressOffset>0x000000d0</addressOffset>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>IRQTOPROC</name>
+                        <description>interrupt to processors, after override is applied</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>INFROMPAD</name>
+                        <description>input signal from pad, before filtering and override are applied</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OETOPAD</name>
+                        <description>output enable to pad after register override is applied</description>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OUTTOPAD</name>
+                        <description>output signal to pad after register override is applied</description>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO26_CTRL</name>
+                <addressOffset>0x000000d4</addressOffset>
+                <resetValue>0x0000001f</resetValue>
+                <fields>
+                    <field>
+                        <name>IRQOVER</name>
+                        <bitRange>[29:28]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>don&#39;t invert the interrupt</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>invert the interrupt</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive interrupt low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive interrupt high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>INOVER</name>
+                        <bitRange>[17:16]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>don&#39;t invert the peri input</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>invert the peri input</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive peri input low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive peri input high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>OEOVER</name>
+                        <bitRange>[15:14]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>drive output enable from peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>DISABLE</name>
+                                <value>2</value>
+                                <description>disable output</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ENABLE</name>
+                                <value>3</value>
+                                <description>enable output</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>OUTOVER</name>
+                        <bitRange>[13:12]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>drive output from peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>drive output from inverse of peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive output low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive output high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>FUNCSEL</name>
+                        <description>0-31 -&gt; selects pin function according to the gpio table 
+                            31 == NULL</description>
+                        <bitRange>[4:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>spi1_sclk</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>uart1_cts</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>i2c1_sda</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pwm_a_5</name>
+                                <value>4</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>siob_proc_26</name>
+                                <value>5</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio0_26</name>
+                                <value>6</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio1_26</name>
+                                <value>7</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio2_26</name>
+                                <value>8</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>usb_muxing_vbus_en</name>
+                                <value>10</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>uart1_tx</name>
+                                <value>11</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>null</name>
+                                <value>31</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO27_STATUS</name>
+                <addressOffset>0x000000d8</addressOffset>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>IRQTOPROC</name>
+                        <description>interrupt to processors, after override is applied</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>INFROMPAD</name>
+                        <description>input signal from pad, before filtering and override are applied</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OETOPAD</name>
+                        <description>output enable to pad after register override is applied</description>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OUTTOPAD</name>
+                        <description>output signal to pad after register override is applied</description>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO27_CTRL</name>
+                <addressOffset>0x000000dc</addressOffset>
+                <resetValue>0x0000001f</resetValue>
+                <fields>
+                    <field>
+                        <name>IRQOVER</name>
+                        <bitRange>[29:28]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>don&#39;t invert the interrupt</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>invert the interrupt</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive interrupt low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive interrupt high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>INOVER</name>
+                        <bitRange>[17:16]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>don&#39;t invert the peri input</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>invert the peri input</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive peri input low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive peri input high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>OEOVER</name>
+                        <bitRange>[15:14]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>drive output enable from peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>DISABLE</name>
+                                <value>2</value>
+                                <description>disable output</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ENABLE</name>
+                                <value>3</value>
+                                <description>enable output</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>OUTOVER</name>
+                        <bitRange>[13:12]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>drive output from peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>drive output from inverse of peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive output low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive output high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>FUNCSEL</name>
+                        <description>0-31 -&gt; selects pin function according to the gpio table 
+                            31 == NULL</description>
+                        <bitRange>[4:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>spi1_tx</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>uart1_rts</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>i2c1_scl</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pwm_b_5</name>
+                                <value>4</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>siob_proc_27</name>
+                                <value>5</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio0_27</name>
+                                <value>6</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio1_27</name>
+                                <value>7</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio2_27</name>
+                                <value>8</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>usb_muxing_overcurr_detect</name>
+                                <value>10</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>uart1_rx</name>
+                                <value>11</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>null</name>
+                                <value>31</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO28_STATUS</name>
+                <addressOffset>0x000000e0</addressOffset>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>IRQTOPROC</name>
+                        <description>interrupt to processors, after override is applied</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>INFROMPAD</name>
+                        <description>input signal from pad, before filtering and override are applied</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OETOPAD</name>
+                        <description>output enable to pad after register override is applied</description>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OUTTOPAD</name>
+                        <description>output signal to pad after register override is applied</description>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO28_CTRL</name>
+                <addressOffset>0x000000e4</addressOffset>
+                <resetValue>0x0000001f</resetValue>
+                <fields>
+                    <field>
+                        <name>IRQOVER</name>
+                        <bitRange>[29:28]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>don&#39;t invert the interrupt</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>invert the interrupt</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive interrupt low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive interrupt high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>INOVER</name>
+                        <bitRange>[17:16]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>don&#39;t invert the peri input</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>invert the peri input</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive peri input low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive peri input high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>OEOVER</name>
+                        <bitRange>[15:14]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>drive output enable from peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>DISABLE</name>
+                                <value>2</value>
+                                <description>disable output</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ENABLE</name>
+                                <value>3</value>
+                                <description>enable output</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>OUTOVER</name>
+                        <bitRange>[13:12]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>drive output from peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>drive output from inverse of peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive output low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive output high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>FUNCSEL</name>
+                        <description>0-31 -&gt; selects pin function according to the gpio table 
+                            31 == NULL</description>
+                        <bitRange>[4:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>spi1_rx</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>uart0_tx</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>i2c0_sda</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pwm_a_6</name>
+                                <value>4</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>siob_proc_28</name>
+                                <value>5</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio0_28</name>
+                                <value>6</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio1_28</name>
+                                <value>7</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio2_28</name>
+                                <value>8</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>usb_muxing_vbus_detect</name>
+                                <value>10</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>null</name>
+                                <value>31</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO29_STATUS</name>
+                <addressOffset>0x000000e8</addressOffset>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>IRQTOPROC</name>
+                        <description>interrupt to processors, after override is applied</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>INFROMPAD</name>
+                        <description>input signal from pad, before filtering and override are applied</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OETOPAD</name>
+                        <description>output enable to pad after register override is applied</description>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OUTTOPAD</name>
+                        <description>output signal to pad after register override is applied</description>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO29_CTRL</name>
+                <addressOffset>0x000000ec</addressOffset>
+                <resetValue>0x0000001f</resetValue>
+                <fields>
+                    <field>
+                        <name>IRQOVER</name>
+                        <bitRange>[29:28]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>don&#39;t invert the interrupt</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>invert the interrupt</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive interrupt low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive interrupt high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>INOVER</name>
+                        <bitRange>[17:16]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>don&#39;t invert the peri input</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>invert the peri input</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive peri input low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive peri input high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>OEOVER</name>
+                        <bitRange>[15:14]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>drive output enable from peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>DISABLE</name>
+                                <value>2</value>
+                                <description>disable output</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ENABLE</name>
+                                <value>3</value>
+                                <description>enable output</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>OUTOVER</name>
+                        <bitRange>[13:12]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>drive output from peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>drive output from inverse of peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive output low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive output high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>FUNCSEL</name>
+                        <description>0-31 -&gt; selects pin function according to the gpio table 
+                            31 == NULL</description>
+                        <bitRange>[4:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>spi1_ss_n</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>uart0_rx</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>i2c0_scl</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pwm_b_6</name>
+                                <value>4</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>siob_proc_29</name>
+                                <value>5</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio0_29</name>
+                                <value>6</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio1_29</name>
+                                <value>7</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio2_29</name>
+                                <value>8</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>usb_muxing_vbus_en</name>
+                                <value>10</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>null</name>
+                                <value>31</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO30_STATUS</name>
+                <addressOffset>0x000000f0</addressOffset>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>IRQTOPROC</name>
+                        <description>interrupt to processors, after override is applied</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>INFROMPAD</name>
+                        <description>input signal from pad, before filtering and override are applied</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OETOPAD</name>
+                        <description>output enable to pad after register override is applied</description>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OUTTOPAD</name>
+                        <description>output signal to pad after register override is applied</description>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO30_CTRL</name>
+                <addressOffset>0x000000f4</addressOffset>
+                <resetValue>0x0000001f</resetValue>
+                <fields>
+                    <field>
+                        <name>IRQOVER</name>
+                        <bitRange>[29:28]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>don&#39;t invert the interrupt</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>invert the interrupt</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive interrupt low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive interrupt high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>INOVER</name>
+                        <bitRange>[17:16]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>don&#39;t invert the peri input</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>invert the peri input</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive peri input low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive peri input high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>OEOVER</name>
+                        <bitRange>[15:14]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>drive output enable from peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>DISABLE</name>
+                                <value>2</value>
+                                <description>disable output</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ENABLE</name>
+                                <value>3</value>
+                                <description>enable output</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>OUTOVER</name>
+                        <bitRange>[13:12]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>drive output from peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>drive output from inverse of peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive output low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive output high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>FUNCSEL</name>
+                        <description>0-31 -&gt; selects pin function according to the gpio table 
+                            31 == NULL</description>
+                        <bitRange>[4:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>spi1_sclk</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>uart0_cts</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>i2c1_sda</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pwm_a_7</name>
+                                <value>4</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>siob_proc_30</name>
+                                <value>5</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio0_30</name>
+                                <value>6</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio1_30</name>
+                                <value>7</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio2_30</name>
+                                <value>8</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>usb_muxing_overcurr_detect</name>
+                                <value>10</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>uart0_tx</name>
+                                <value>11</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>null</name>
+                                <value>31</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO31_STATUS</name>
+                <addressOffset>0x000000f8</addressOffset>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>IRQTOPROC</name>
+                        <description>interrupt to processors, after override is applied</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>INFROMPAD</name>
+                        <description>input signal from pad, before filtering and override are applied</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OETOPAD</name>
+                        <description>output enable to pad after register override is applied</description>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OUTTOPAD</name>
+                        <description>output signal to pad after register override is applied</description>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO31_CTRL</name>
+                <addressOffset>0x000000fc</addressOffset>
+                <resetValue>0x0000001f</resetValue>
+                <fields>
+                    <field>
+                        <name>IRQOVER</name>
+                        <bitRange>[29:28]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>don&#39;t invert the interrupt</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>invert the interrupt</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive interrupt low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive interrupt high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>INOVER</name>
+                        <bitRange>[17:16]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>don&#39;t invert the peri input</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>invert the peri input</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive peri input low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive peri input high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>OEOVER</name>
+                        <bitRange>[15:14]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>drive output enable from peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>DISABLE</name>
+                                <value>2</value>
+                                <description>disable output</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ENABLE</name>
+                                <value>3</value>
+                                <description>enable output</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>OUTOVER</name>
+                        <bitRange>[13:12]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>drive output from peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>drive output from inverse of peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive output low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive output high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>FUNCSEL</name>
+                        <description>0-31 -&gt; selects pin function according to the gpio table 
+                            31 == NULL</description>
+                        <bitRange>[4:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>spi1_tx</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>uart0_rts</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>i2c1_scl</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pwm_b_7</name>
+                                <value>4</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>siob_proc_31</name>
+                                <value>5</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio0_31</name>
+                                <value>6</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio1_31</name>
+                                <value>7</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio2_31</name>
+                                <value>8</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>usb_muxing_vbus_detect</name>
+                                <value>10</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>uart0_rx</name>
+                                <value>11</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>null</name>
+                                <value>31</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO32_STATUS</name>
+                <addressOffset>0x00000100</addressOffset>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>IRQTOPROC</name>
+                        <description>interrupt to processors, after override is applied</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>INFROMPAD</name>
+                        <description>input signal from pad, before filtering and override are applied</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OETOPAD</name>
+                        <description>output enable to pad after register override is applied</description>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OUTTOPAD</name>
+                        <description>output signal to pad after register override is applied</description>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO32_CTRL</name>
+                <addressOffset>0x00000104</addressOffset>
+                <resetValue>0x0000001f</resetValue>
+                <fields>
+                    <field>
+                        <name>IRQOVER</name>
+                        <bitRange>[29:28]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>don&#39;t invert the interrupt</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>invert the interrupt</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive interrupt low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive interrupt high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>INOVER</name>
+                        <bitRange>[17:16]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>don&#39;t invert the peri input</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>invert the peri input</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive peri input low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive peri input high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>OEOVER</name>
+                        <bitRange>[15:14]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>drive output enable from peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>DISABLE</name>
+                                <value>2</value>
+                                <description>disable output</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ENABLE</name>
+                                <value>3</value>
+                                <description>enable output</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>OUTOVER</name>
+                        <bitRange>[13:12]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>drive output from peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>drive output from inverse of peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive output low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive output high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>FUNCSEL</name>
+                        <description>0-31 -&gt; selects pin function according to the gpio table 
+                            31 == NULL</description>
+                        <bitRange>[4:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>spi0_rx</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>uart0_tx</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>i2c0_sda</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pwm_a_8</name>
+                                <value>4</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>siob_proc_32</name>
+                                <value>5</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio0_32</name>
+                                <value>6</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio1_32</name>
+                                <value>7</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio2_32</name>
+                                <value>8</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>usb_muxing_vbus_en</name>
+                                <value>10</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>null</name>
+                                <value>31</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO33_STATUS</name>
+                <addressOffset>0x00000108</addressOffset>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>IRQTOPROC</name>
+                        <description>interrupt to processors, after override is applied</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>INFROMPAD</name>
+                        <description>input signal from pad, before filtering and override are applied</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OETOPAD</name>
+                        <description>output enable to pad after register override is applied</description>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OUTTOPAD</name>
+                        <description>output signal to pad after register override is applied</description>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO33_CTRL</name>
+                <addressOffset>0x0000010c</addressOffset>
+                <resetValue>0x0000001f</resetValue>
+                <fields>
+                    <field>
+                        <name>IRQOVER</name>
+                        <bitRange>[29:28]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>don&#39;t invert the interrupt</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>invert the interrupt</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive interrupt low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive interrupt high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>INOVER</name>
+                        <bitRange>[17:16]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>don&#39;t invert the peri input</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>invert the peri input</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive peri input low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive peri input high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>OEOVER</name>
+                        <bitRange>[15:14]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>drive output enable from peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>DISABLE</name>
+                                <value>2</value>
+                                <description>disable output</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ENABLE</name>
+                                <value>3</value>
+                                <description>enable output</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>OUTOVER</name>
+                        <bitRange>[13:12]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>drive output from peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>drive output from inverse of peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive output low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive output high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>FUNCSEL</name>
+                        <description>0-31 -&gt; selects pin function according to the gpio table 
+                            31 == NULL</description>
+                        <bitRange>[4:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>spi0_ss_n</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>uart0_rx</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>i2c0_scl</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pwm_b_8</name>
+                                <value>4</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>siob_proc_33</name>
+                                <value>5</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio0_33</name>
+                                <value>6</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio1_33</name>
+                                <value>7</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio2_33</name>
+                                <value>8</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>usb_muxing_overcurr_detect</name>
+                                <value>10</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>null</name>
+                                <value>31</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO34_STATUS</name>
+                <addressOffset>0x00000110</addressOffset>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>IRQTOPROC</name>
+                        <description>interrupt to processors, after override is applied</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>INFROMPAD</name>
+                        <description>input signal from pad, before filtering and override are applied</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OETOPAD</name>
+                        <description>output enable to pad after register override is applied</description>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OUTTOPAD</name>
+                        <description>output signal to pad after register override is applied</description>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO34_CTRL</name>
+                <addressOffset>0x00000114</addressOffset>
+                <resetValue>0x0000001f</resetValue>
+                <fields>
+                    <field>
+                        <name>IRQOVER</name>
+                        <bitRange>[29:28]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>don&#39;t invert the interrupt</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>invert the interrupt</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive interrupt low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive interrupt high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>INOVER</name>
+                        <bitRange>[17:16]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>don&#39;t invert the peri input</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>invert the peri input</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive peri input low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive peri input high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>OEOVER</name>
+                        <bitRange>[15:14]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>drive output enable from peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>DISABLE</name>
+                                <value>2</value>
+                                <description>disable output</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ENABLE</name>
+                                <value>3</value>
+                                <description>enable output</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>OUTOVER</name>
+                        <bitRange>[13:12]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>drive output from peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>drive output from inverse of peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive output low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive output high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>FUNCSEL</name>
+                        <description>0-31 -&gt; selects pin function according to the gpio table 
+                            31 == NULL</description>
+                        <bitRange>[4:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>spi0_sclk</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>uart0_cts</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>i2c1_sda</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pwm_a_9</name>
+                                <value>4</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>siob_proc_34</name>
+                                <value>5</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio0_34</name>
+                                <value>6</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio1_34</name>
+                                <value>7</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio2_34</name>
+                                <value>8</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>usb_muxing_vbus_detect</name>
+                                <value>10</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>uart0_tx</name>
+                                <value>11</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>null</name>
+                                <value>31</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO35_STATUS</name>
+                <addressOffset>0x00000118</addressOffset>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>IRQTOPROC</name>
+                        <description>interrupt to processors, after override is applied</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>INFROMPAD</name>
+                        <description>input signal from pad, before filtering and override are applied</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OETOPAD</name>
+                        <description>output enable to pad after register override is applied</description>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OUTTOPAD</name>
+                        <description>output signal to pad after register override is applied</description>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO35_CTRL</name>
+                <addressOffset>0x0000011c</addressOffset>
+                <resetValue>0x0000001f</resetValue>
+                <fields>
+                    <field>
+                        <name>IRQOVER</name>
+                        <bitRange>[29:28]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>don&#39;t invert the interrupt</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>invert the interrupt</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive interrupt low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive interrupt high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>INOVER</name>
+                        <bitRange>[17:16]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>don&#39;t invert the peri input</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>invert the peri input</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive peri input low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive peri input high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>OEOVER</name>
+                        <bitRange>[15:14]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>drive output enable from peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>DISABLE</name>
+                                <value>2</value>
+                                <description>disable output</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ENABLE</name>
+                                <value>3</value>
+                                <description>enable output</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>OUTOVER</name>
+                        <bitRange>[13:12]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>drive output from peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>drive output from inverse of peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive output low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive output high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>FUNCSEL</name>
+                        <description>0-31 -&gt; selects pin function according to the gpio table 
+                            31 == NULL</description>
+                        <bitRange>[4:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>spi0_tx</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>uart0_rts</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>i2c1_scl</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pwm_b_9</name>
+                                <value>4</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>siob_proc_35</name>
+                                <value>5</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio0_35</name>
+                                <value>6</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio1_35</name>
+                                <value>7</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio2_35</name>
+                                <value>8</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>usb_muxing_vbus_en</name>
+                                <value>10</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>uart0_rx</name>
+                                <value>11</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>null</name>
+                                <value>31</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO36_STATUS</name>
+                <addressOffset>0x00000120</addressOffset>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>IRQTOPROC</name>
+                        <description>interrupt to processors, after override is applied</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>INFROMPAD</name>
+                        <description>input signal from pad, before filtering and override are applied</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OETOPAD</name>
+                        <description>output enable to pad after register override is applied</description>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OUTTOPAD</name>
+                        <description>output signal to pad after register override is applied</description>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO36_CTRL</name>
+                <addressOffset>0x00000124</addressOffset>
+                <resetValue>0x0000001f</resetValue>
+                <fields>
+                    <field>
+                        <name>IRQOVER</name>
+                        <bitRange>[29:28]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>don&#39;t invert the interrupt</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>invert the interrupt</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive interrupt low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive interrupt high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>INOVER</name>
+                        <bitRange>[17:16]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>don&#39;t invert the peri input</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>invert the peri input</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive peri input low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive peri input high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>OEOVER</name>
+                        <bitRange>[15:14]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>drive output enable from peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>DISABLE</name>
+                                <value>2</value>
+                                <description>disable output</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ENABLE</name>
+                                <value>3</value>
+                                <description>enable output</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>OUTOVER</name>
+                        <bitRange>[13:12]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>drive output from peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>drive output from inverse of peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive output low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive output high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>FUNCSEL</name>
+                        <description>0-31 -&gt; selects pin function according to the gpio table 
+                            31 == NULL</description>
+                        <bitRange>[4:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>spi0_rx</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>uart1_tx</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>i2c0_sda</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pwm_a_10</name>
+                                <value>4</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>siob_proc_36</name>
+                                <value>5</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio0_36</name>
+                                <value>6</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio1_36</name>
+                                <value>7</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio2_36</name>
+                                <value>8</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>usb_muxing_overcurr_detect</name>
+                                <value>10</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>null</name>
+                                <value>31</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO37_STATUS</name>
+                <addressOffset>0x00000128</addressOffset>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>IRQTOPROC</name>
+                        <description>interrupt to processors, after override is applied</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>INFROMPAD</name>
+                        <description>input signal from pad, before filtering and override are applied</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OETOPAD</name>
+                        <description>output enable to pad after register override is applied</description>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OUTTOPAD</name>
+                        <description>output signal to pad after register override is applied</description>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO37_CTRL</name>
+                <addressOffset>0x0000012c</addressOffset>
+                <resetValue>0x0000001f</resetValue>
+                <fields>
+                    <field>
+                        <name>IRQOVER</name>
+                        <bitRange>[29:28]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>don&#39;t invert the interrupt</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>invert the interrupt</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive interrupt low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive interrupt high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>INOVER</name>
+                        <bitRange>[17:16]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>don&#39;t invert the peri input</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>invert the peri input</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive peri input low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive peri input high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>OEOVER</name>
+                        <bitRange>[15:14]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>drive output enable from peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>DISABLE</name>
+                                <value>2</value>
+                                <description>disable output</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ENABLE</name>
+                                <value>3</value>
+                                <description>enable output</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>OUTOVER</name>
+                        <bitRange>[13:12]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>drive output from peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>drive output from inverse of peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive output low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive output high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>FUNCSEL</name>
+                        <description>0-31 -&gt; selects pin function according to the gpio table 
+                            31 == NULL</description>
+                        <bitRange>[4:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>spi0_ss_n</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>uart1_rx</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>i2c0_scl</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pwm_b_10</name>
+                                <value>4</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>siob_proc_37</name>
+                                <value>5</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio0_37</name>
+                                <value>6</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio1_37</name>
+                                <value>7</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio2_37</name>
+                                <value>8</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>usb_muxing_vbus_detect</name>
+                                <value>10</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>null</name>
+                                <value>31</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO38_STATUS</name>
+                <addressOffset>0x00000130</addressOffset>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>IRQTOPROC</name>
+                        <description>interrupt to processors, after override is applied</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>INFROMPAD</name>
+                        <description>input signal from pad, before filtering and override are applied</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OETOPAD</name>
+                        <description>output enable to pad after register override is applied</description>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OUTTOPAD</name>
+                        <description>output signal to pad after register override is applied</description>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO38_CTRL</name>
+                <addressOffset>0x00000134</addressOffset>
+                <resetValue>0x0000001f</resetValue>
+                <fields>
+                    <field>
+                        <name>IRQOVER</name>
+                        <bitRange>[29:28]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>don&#39;t invert the interrupt</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>invert the interrupt</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive interrupt low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive interrupt high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>INOVER</name>
+                        <bitRange>[17:16]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>don&#39;t invert the peri input</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>invert the peri input</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive peri input low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive peri input high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>OEOVER</name>
+                        <bitRange>[15:14]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>drive output enable from peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>DISABLE</name>
+                                <value>2</value>
+                                <description>disable output</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ENABLE</name>
+                                <value>3</value>
+                                <description>enable output</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>OUTOVER</name>
+                        <bitRange>[13:12]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>drive output from peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>drive output from inverse of peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive output low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive output high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>FUNCSEL</name>
+                        <description>0-31 -&gt; selects pin function according to the gpio table 
+                            31 == NULL</description>
+                        <bitRange>[4:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>spi0_sclk</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>uart1_cts</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>i2c1_sda</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pwm_a_11</name>
+                                <value>4</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>siob_proc_38</name>
+                                <value>5</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio0_38</name>
+                                <value>6</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio1_38</name>
+                                <value>7</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio2_38</name>
+                                <value>8</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>usb_muxing_vbus_en</name>
+                                <value>10</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>uart1_tx</name>
+                                <value>11</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>null</name>
+                                <value>31</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO39_STATUS</name>
+                <addressOffset>0x00000138</addressOffset>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>IRQTOPROC</name>
+                        <description>interrupt to processors, after override is applied</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>INFROMPAD</name>
+                        <description>input signal from pad, before filtering and override are applied</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OETOPAD</name>
+                        <description>output enable to pad after register override is applied</description>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OUTTOPAD</name>
+                        <description>output signal to pad after register override is applied</description>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO39_CTRL</name>
+                <addressOffset>0x0000013c</addressOffset>
+                <resetValue>0x0000001f</resetValue>
+                <fields>
+                    <field>
+                        <name>IRQOVER</name>
+                        <bitRange>[29:28]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>don&#39;t invert the interrupt</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>invert the interrupt</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive interrupt low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive interrupt high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>INOVER</name>
+                        <bitRange>[17:16]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>don&#39;t invert the peri input</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>invert the peri input</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive peri input low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive peri input high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>OEOVER</name>
+                        <bitRange>[15:14]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>drive output enable from peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>DISABLE</name>
+                                <value>2</value>
+                                <description>disable output</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ENABLE</name>
+                                <value>3</value>
+                                <description>enable output</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>OUTOVER</name>
+                        <bitRange>[13:12]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>drive output from peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>drive output from inverse of peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive output low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive output high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>FUNCSEL</name>
+                        <description>0-31 -&gt; selects pin function according to the gpio table 
+                            31 == NULL</description>
+                        <bitRange>[4:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>spi0_tx</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>uart1_rts</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>i2c1_scl</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pwm_b_11</name>
+                                <value>4</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>siob_proc_39</name>
+                                <value>5</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio0_39</name>
+                                <value>6</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio1_39</name>
+                                <value>7</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio2_39</name>
+                                <value>8</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>usb_muxing_overcurr_detect</name>
+                                <value>10</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>uart1_rx</name>
+                                <value>11</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>null</name>
+                                <value>31</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO40_STATUS</name>
+                <addressOffset>0x00000140</addressOffset>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>IRQTOPROC</name>
+                        <description>interrupt to processors, after override is applied</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>INFROMPAD</name>
+                        <description>input signal from pad, before filtering and override are applied</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OETOPAD</name>
+                        <description>output enable to pad after register override is applied</description>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OUTTOPAD</name>
+                        <description>output signal to pad after register override is applied</description>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO40_CTRL</name>
+                <addressOffset>0x00000144</addressOffset>
+                <resetValue>0x0000001f</resetValue>
+                <fields>
+                    <field>
+                        <name>IRQOVER</name>
+                        <bitRange>[29:28]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>don&#39;t invert the interrupt</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>invert the interrupt</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive interrupt low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive interrupt high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>INOVER</name>
+                        <bitRange>[17:16]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>don&#39;t invert the peri input</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>invert the peri input</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive peri input low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive peri input high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>OEOVER</name>
+                        <bitRange>[15:14]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>drive output enable from peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>DISABLE</name>
+                                <value>2</value>
+                                <description>disable output</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ENABLE</name>
+                                <value>3</value>
+                                <description>enable output</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>OUTOVER</name>
+                        <bitRange>[13:12]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>drive output from peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>drive output from inverse of peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive output low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive output high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>FUNCSEL</name>
+                        <description>0-31 -&gt; selects pin function according to the gpio table 
+                            31 == NULL</description>
+                        <bitRange>[4:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>spi1_rx</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>uart1_tx</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>i2c0_sda</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pwm_a_8</name>
+                                <value>4</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>siob_proc_40</name>
+                                <value>5</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio0_40</name>
+                                <value>6</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio1_40</name>
+                                <value>7</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio2_40</name>
+                                <value>8</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>usb_muxing_vbus_detect</name>
+                                <value>10</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>null</name>
+                                <value>31</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO41_STATUS</name>
+                <addressOffset>0x00000148</addressOffset>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>IRQTOPROC</name>
+                        <description>interrupt to processors, after override is applied</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>INFROMPAD</name>
+                        <description>input signal from pad, before filtering and override are applied</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OETOPAD</name>
+                        <description>output enable to pad after register override is applied</description>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OUTTOPAD</name>
+                        <description>output signal to pad after register override is applied</description>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO41_CTRL</name>
+                <addressOffset>0x0000014c</addressOffset>
+                <resetValue>0x0000001f</resetValue>
+                <fields>
+                    <field>
+                        <name>IRQOVER</name>
+                        <bitRange>[29:28]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>don&#39;t invert the interrupt</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>invert the interrupt</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive interrupt low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive interrupt high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>INOVER</name>
+                        <bitRange>[17:16]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>don&#39;t invert the peri input</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>invert the peri input</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive peri input low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive peri input high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>OEOVER</name>
+                        <bitRange>[15:14]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>drive output enable from peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>DISABLE</name>
+                                <value>2</value>
+                                <description>disable output</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ENABLE</name>
+                                <value>3</value>
+                                <description>enable output</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>OUTOVER</name>
+                        <bitRange>[13:12]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>drive output from peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>drive output from inverse of peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive output low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive output high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>FUNCSEL</name>
+                        <description>0-31 -&gt; selects pin function according to the gpio table 
+                            31 == NULL</description>
+                        <bitRange>[4:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>spi1_ss_n</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>uart1_rx</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>i2c0_scl</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pwm_b_8</name>
+                                <value>4</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>siob_proc_41</name>
+                                <value>5</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio0_41</name>
+                                <value>6</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio1_41</name>
+                                <value>7</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio2_41</name>
+                                <value>8</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>usb_muxing_vbus_en</name>
+                                <value>10</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>null</name>
+                                <value>31</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO42_STATUS</name>
+                <addressOffset>0x00000150</addressOffset>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>IRQTOPROC</name>
+                        <description>interrupt to processors, after override is applied</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>INFROMPAD</name>
+                        <description>input signal from pad, before filtering and override are applied</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OETOPAD</name>
+                        <description>output enable to pad after register override is applied</description>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OUTTOPAD</name>
+                        <description>output signal to pad after register override is applied</description>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO42_CTRL</name>
+                <addressOffset>0x00000154</addressOffset>
+                <resetValue>0x0000001f</resetValue>
+                <fields>
+                    <field>
+                        <name>IRQOVER</name>
+                        <bitRange>[29:28]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>don&#39;t invert the interrupt</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>invert the interrupt</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive interrupt low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive interrupt high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>INOVER</name>
+                        <bitRange>[17:16]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>don&#39;t invert the peri input</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>invert the peri input</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive peri input low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive peri input high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>OEOVER</name>
+                        <bitRange>[15:14]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>drive output enable from peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>DISABLE</name>
+                                <value>2</value>
+                                <description>disable output</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ENABLE</name>
+                                <value>3</value>
+                                <description>enable output</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>OUTOVER</name>
+                        <bitRange>[13:12]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>drive output from peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>drive output from inverse of peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive output low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive output high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>FUNCSEL</name>
+                        <description>0-31 -&gt; selects pin function according to the gpio table 
+                            31 == NULL</description>
+                        <bitRange>[4:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>spi1_sclk</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>uart1_cts</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>i2c1_sda</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pwm_a_9</name>
+                                <value>4</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>siob_proc_42</name>
+                                <value>5</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio0_42</name>
+                                <value>6</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio1_42</name>
+                                <value>7</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio2_42</name>
+                                <value>8</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>usb_muxing_overcurr_detect</name>
+                                <value>10</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>uart1_tx</name>
+                                <value>11</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>null</name>
+                                <value>31</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO43_STATUS</name>
+                <addressOffset>0x00000158</addressOffset>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>IRQTOPROC</name>
+                        <description>interrupt to processors, after override is applied</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>INFROMPAD</name>
+                        <description>input signal from pad, before filtering and override are applied</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OETOPAD</name>
+                        <description>output enable to pad after register override is applied</description>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OUTTOPAD</name>
+                        <description>output signal to pad after register override is applied</description>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO43_CTRL</name>
+                <addressOffset>0x0000015c</addressOffset>
+                <resetValue>0x0000001f</resetValue>
+                <fields>
+                    <field>
+                        <name>IRQOVER</name>
+                        <bitRange>[29:28]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>don&#39;t invert the interrupt</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>invert the interrupt</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive interrupt low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive interrupt high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>INOVER</name>
+                        <bitRange>[17:16]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>don&#39;t invert the peri input</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>invert the peri input</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive peri input low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive peri input high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>OEOVER</name>
+                        <bitRange>[15:14]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>drive output enable from peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>DISABLE</name>
+                                <value>2</value>
+                                <description>disable output</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ENABLE</name>
+                                <value>3</value>
+                                <description>enable output</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>OUTOVER</name>
+                        <bitRange>[13:12]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>drive output from peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>drive output from inverse of peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive output low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive output high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>FUNCSEL</name>
+                        <description>0-31 -&gt; selects pin function according to the gpio table 
+                            31 == NULL</description>
+                        <bitRange>[4:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>spi1_tx</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>uart1_rts</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>i2c1_scl</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pwm_b_9</name>
+                                <value>4</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>siob_proc_43</name>
+                                <value>5</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio0_43</name>
+                                <value>6</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio1_43</name>
+                                <value>7</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio2_43</name>
+                                <value>8</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>usb_muxing_vbus_detect</name>
+                                <value>10</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>uart1_rx</name>
+                                <value>11</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>null</name>
+                                <value>31</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO44_STATUS</name>
+                <addressOffset>0x00000160</addressOffset>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>IRQTOPROC</name>
+                        <description>interrupt to processors, after override is applied</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>INFROMPAD</name>
+                        <description>input signal from pad, before filtering and override are applied</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OETOPAD</name>
+                        <description>output enable to pad after register override is applied</description>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OUTTOPAD</name>
+                        <description>output signal to pad after register override is applied</description>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO44_CTRL</name>
+                <addressOffset>0x00000164</addressOffset>
+                <resetValue>0x0000001f</resetValue>
+                <fields>
+                    <field>
+                        <name>IRQOVER</name>
+                        <bitRange>[29:28]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>don&#39;t invert the interrupt</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>invert the interrupt</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive interrupt low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive interrupt high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>INOVER</name>
+                        <bitRange>[17:16]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>don&#39;t invert the peri input</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>invert the peri input</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive peri input low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive peri input high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>OEOVER</name>
+                        <bitRange>[15:14]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>drive output enable from peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>DISABLE</name>
+                                <value>2</value>
+                                <description>disable output</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ENABLE</name>
+                                <value>3</value>
+                                <description>enable output</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>OUTOVER</name>
+                        <bitRange>[13:12]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>drive output from peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>drive output from inverse of peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive output low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive output high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>FUNCSEL</name>
+                        <description>0-31 -&gt; selects pin function according to the gpio table 
+                            31 == NULL</description>
+                        <bitRange>[4:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>spi1_rx</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>uart0_tx</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>i2c0_sda</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pwm_a_10</name>
+                                <value>4</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>siob_proc_44</name>
+                                <value>5</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio0_44</name>
+                                <value>6</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio1_44</name>
+                                <value>7</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio2_44</name>
+                                <value>8</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>usb_muxing_vbus_en</name>
+                                <value>10</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>null</name>
+                                <value>31</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO45_STATUS</name>
+                <addressOffset>0x00000168</addressOffset>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>IRQTOPROC</name>
+                        <description>interrupt to processors, after override is applied</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>INFROMPAD</name>
+                        <description>input signal from pad, before filtering and override are applied</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OETOPAD</name>
+                        <description>output enable to pad after register override is applied</description>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OUTTOPAD</name>
+                        <description>output signal to pad after register override is applied</description>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO45_CTRL</name>
+                <addressOffset>0x0000016c</addressOffset>
+                <resetValue>0x0000001f</resetValue>
+                <fields>
+                    <field>
+                        <name>IRQOVER</name>
+                        <bitRange>[29:28]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>don&#39;t invert the interrupt</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>invert the interrupt</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive interrupt low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive interrupt high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>INOVER</name>
+                        <bitRange>[17:16]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>don&#39;t invert the peri input</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>invert the peri input</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive peri input low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive peri input high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>OEOVER</name>
+                        <bitRange>[15:14]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>drive output enable from peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>DISABLE</name>
+                                <value>2</value>
+                                <description>disable output</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ENABLE</name>
+                                <value>3</value>
+                                <description>enable output</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>OUTOVER</name>
+                        <bitRange>[13:12]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>drive output from peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>drive output from inverse of peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive output low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive output high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>FUNCSEL</name>
+                        <description>0-31 -&gt; selects pin function according to the gpio table 
+                            31 == NULL</description>
+                        <bitRange>[4:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>spi1_ss_n</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>uart0_rx</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>i2c0_scl</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pwm_b_10</name>
+                                <value>4</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>siob_proc_45</name>
+                                <value>5</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio0_45</name>
+                                <value>6</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio1_45</name>
+                                <value>7</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio2_45</name>
+                                <value>8</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>usb_muxing_overcurr_detect</name>
+                                <value>10</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>null</name>
+                                <value>31</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO46_STATUS</name>
+                <addressOffset>0x00000170</addressOffset>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>IRQTOPROC</name>
+                        <description>interrupt to processors, after override is applied</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>INFROMPAD</name>
+                        <description>input signal from pad, before filtering and override are applied</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OETOPAD</name>
+                        <description>output enable to pad after register override is applied</description>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OUTTOPAD</name>
+                        <description>output signal to pad after register override is applied</description>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO46_CTRL</name>
+                <addressOffset>0x00000174</addressOffset>
+                <resetValue>0x0000001f</resetValue>
+                <fields>
+                    <field>
+                        <name>IRQOVER</name>
+                        <bitRange>[29:28]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>don&#39;t invert the interrupt</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>invert the interrupt</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive interrupt low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive interrupt high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>INOVER</name>
+                        <bitRange>[17:16]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>don&#39;t invert the peri input</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>invert the peri input</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive peri input low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive peri input high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>OEOVER</name>
+                        <bitRange>[15:14]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>drive output enable from peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>DISABLE</name>
+                                <value>2</value>
+                                <description>disable output</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ENABLE</name>
+                                <value>3</value>
+                                <description>enable output</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>OUTOVER</name>
+                        <bitRange>[13:12]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>drive output from peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>drive output from inverse of peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive output low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive output high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>FUNCSEL</name>
+                        <description>0-31 -&gt; selects pin function according to the gpio table 
+                            31 == NULL</description>
+                        <bitRange>[4:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>spi1_sclk</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>uart0_cts</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>i2c1_sda</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pwm_a_11</name>
+                                <value>4</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>siob_proc_46</name>
+                                <value>5</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio0_46</name>
+                                <value>6</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio1_46</name>
+                                <value>7</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio2_46</name>
+                                <value>8</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>usb_muxing_vbus_detect</name>
+                                <value>10</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>uart0_tx</name>
+                                <value>11</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>null</name>
+                                <value>31</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO47_STATUS</name>
+                <addressOffset>0x00000178</addressOffset>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>IRQTOPROC</name>
+                        <description>interrupt to processors, after override is applied</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>INFROMPAD</name>
+                        <description>input signal from pad, before filtering and override are applied</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OETOPAD</name>
+                        <description>output enable to pad after register override is applied</description>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OUTTOPAD</name>
+                        <description>output signal to pad after register override is applied</description>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO47_CTRL</name>
+                <addressOffset>0x0000017c</addressOffset>
+                <resetValue>0x0000001f</resetValue>
+                <fields>
+                    <field>
+                        <name>IRQOVER</name>
+                        <bitRange>[29:28]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>don&#39;t invert the interrupt</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>invert the interrupt</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive interrupt low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive interrupt high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>INOVER</name>
+                        <bitRange>[17:16]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>don&#39;t invert the peri input</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>invert the peri input</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive peri input low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive peri input high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>OEOVER</name>
+                        <bitRange>[15:14]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>drive output enable from peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>DISABLE</name>
+                                <value>2</value>
+                                <description>disable output</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ENABLE</name>
+                                <value>3</value>
+                                <description>enable output</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>OUTOVER</name>
+                        <bitRange>[13:12]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                                <description>drive output from peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INVERT</name>
+                                <value>1</value>
+                                <description>drive output from inverse of peripheral signal selected by funcsel</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>2</value>
+                                <description>drive output low</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>drive output high</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>FUNCSEL</name>
+                        <description>0-31 -&gt; selects pin function according to the gpio table 
+                            31 == NULL</description>
+                        <bitRange>[4:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>spi1_tx</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>uart0_rts</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>i2c1_scl</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pwm_b_11</name>
+                                <value>4</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>siob_proc_47</name>
+                                <value>5</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio0_47</name>
+                                <value>6</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio1_47</name>
+                                <value>7</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>pio2_47</name>
+                                <value>8</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>xip_ss_n_1</name>
+                                <value>9</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>usb_muxing_vbus_en</name>
+                                <value>10</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>uart0_rx</name>
+                                <value>11</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>null</name>
+                                <value>31</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>IRQSUMMARY_PROC0_SECURE0</name>
+                <addressOffset>0x00000200</addressOffset>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>GPIO31</name>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO30</name>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO29</name>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO28</name>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO27</name>
+                        <bitRange>[27:27]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO26</name>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO25</name>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO24</name>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO23</name>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO22</name>
+                        <bitRange>[22:22]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO21</name>
+                        <bitRange>[21:21]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO20</name>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO19</name>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO18</name>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO17</name>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO16</name>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO15</name>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO14</name>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO13</name>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO12</name>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO11</name>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO10</name>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO9</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO8</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO7</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO6</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO5</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO4</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO3</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO2</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO1</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO0</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>IRQSUMMARY_PROC0_SECURE1</name>
+                <addressOffset>0x00000204</addressOffset>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>GPIO47</name>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO46</name>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO45</name>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO44</name>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO43</name>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO42</name>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO41</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO40</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO39</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO38</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO37</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO36</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO35</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO34</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO33</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO32</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>IRQSUMMARY_PROC0_NONSECURE0</name>
+                <addressOffset>0x00000208</addressOffset>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>GPIO31</name>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO30</name>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO29</name>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO28</name>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO27</name>
+                        <bitRange>[27:27]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO26</name>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO25</name>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO24</name>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO23</name>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO22</name>
+                        <bitRange>[22:22]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO21</name>
+                        <bitRange>[21:21]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO20</name>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO19</name>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO18</name>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO17</name>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO16</name>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO15</name>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO14</name>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO13</name>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO12</name>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO11</name>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO10</name>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO9</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO8</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO7</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO6</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO5</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO4</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO3</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO2</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO1</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO0</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>IRQSUMMARY_PROC0_NONSECURE1</name>
+                <addressOffset>0x0000020c</addressOffset>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>GPIO47</name>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO46</name>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO45</name>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO44</name>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO43</name>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO42</name>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO41</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO40</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO39</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO38</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO37</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO36</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO35</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO34</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO33</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO32</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>IRQSUMMARY_PROC1_SECURE0</name>
+                <addressOffset>0x00000210</addressOffset>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>GPIO31</name>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO30</name>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO29</name>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO28</name>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO27</name>
+                        <bitRange>[27:27]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO26</name>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO25</name>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO24</name>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO23</name>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO22</name>
+                        <bitRange>[22:22]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO21</name>
+                        <bitRange>[21:21]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO20</name>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO19</name>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO18</name>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO17</name>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO16</name>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO15</name>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO14</name>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO13</name>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO12</name>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO11</name>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO10</name>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO9</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO8</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO7</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO6</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO5</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO4</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO3</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO2</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO1</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO0</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>IRQSUMMARY_PROC1_SECURE1</name>
+                <addressOffset>0x00000214</addressOffset>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>GPIO47</name>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO46</name>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO45</name>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO44</name>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO43</name>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO42</name>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO41</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO40</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO39</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO38</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO37</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO36</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO35</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO34</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO33</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO32</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>IRQSUMMARY_PROC1_NONSECURE0</name>
+                <addressOffset>0x00000218</addressOffset>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>GPIO31</name>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO30</name>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO29</name>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO28</name>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO27</name>
+                        <bitRange>[27:27]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO26</name>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO25</name>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO24</name>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO23</name>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO22</name>
+                        <bitRange>[22:22]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO21</name>
+                        <bitRange>[21:21]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO20</name>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO19</name>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO18</name>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO17</name>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO16</name>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO15</name>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO14</name>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO13</name>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO12</name>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO11</name>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO10</name>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO9</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO8</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO7</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO6</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO5</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO4</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO3</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO2</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO1</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO0</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>IRQSUMMARY_PROC1_NONSECURE1</name>
+                <addressOffset>0x0000021c</addressOffset>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>GPIO47</name>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO46</name>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO45</name>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO44</name>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO43</name>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO42</name>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO41</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO40</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO39</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO38</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO37</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO36</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO35</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO34</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO33</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO32</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>IRQSUMMARY_DORMANT_WAKE_SECURE0</name>
+                <addressOffset>0x00000220</addressOffset>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>GPIO31</name>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO30</name>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO29</name>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO28</name>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO27</name>
+                        <bitRange>[27:27]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO26</name>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO25</name>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO24</name>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO23</name>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO22</name>
+                        <bitRange>[22:22]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO21</name>
+                        <bitRange>[21:21]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO20</name>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO19</name>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO18</name>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO17</name>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO16</name>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO15</name>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO14</name>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO13</name>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO12</name>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO11</name>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO10</name>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO9</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO8</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO7</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO6</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO5</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO4</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO3</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO2</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO1</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO0</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>IRQSUMMARY_DORMANT_WAKE_SECURE1</name>
+                <addressOffset>0x00000224</addressOffset>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>GPIO47</name>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO46</name>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO45</name>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO44</name>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO43</name>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO42</name>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO41</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO40</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO39</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO38</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO37</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO36</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO35</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO34</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO33</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO32</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>IRQSUMMARY_DORMANT_WAKE_NONSECURE0</name>
+                <addressOffset>0x00000228</addressOffset>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>GPIO31</name>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO30</name>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO29</name>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO28</name>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO27</name>
+                        <bitRange>[27:27]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO26</name>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO25</name>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO24</name>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO23</name>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO22</name>
+                        <bitRange>[22:22]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO21</name>
+                        <bitRange>[21:21]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO20</name>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO19</name>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO18</name>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO17</name>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO16</name>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO15</name>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO14</name>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO13</name>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO12</name>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO11</name>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO10</name>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO9</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO8</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO7</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO6</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO5</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO4</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO3</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO2</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO1</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO0</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>IRQSUMMARY_DORMANT_WAKE_NONSECURE1</name>
+                <addressOffset>0x0000022c</addressOffset>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>GPIO47</name>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO46</name>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO45</name>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO44</name>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO43</name>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO42</name>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO41</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO40</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO39</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO38</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO37</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO36</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO35</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO34</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO33</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO32</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INTR0</name>
+                <addressOffset>0x00000230</addressOffset>
+                <description>Raw Interrupts</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>GPIO7_EDGE_HIGH</name>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>GPIO7_EDGE_LOW</name>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>GPIO7_LEVEL_HIGH</name>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO7_LEVEL_LOW</name>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO6_EDGE_HIGH</name>
+                        <bitRange>[27:27]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>GPIO6_EDGE_LOW</name>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>GPIO6_LEVEL_HIGH</name>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO6_LEVEL_LOW</name>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO5_EDGE_HIGH</name>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>GPIO5_EDGE_LOW</name>
+                        <bitRange>[22:22]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>GPIO5_LEVEL_HIGH</name>
+                        <bitRange>[21:21]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO5_LEVEL_LOW</name>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO4_EDGE_HIGH</name>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>GPIO4_EDGE_LOW</name>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>GPIO4_LEVEL_HIGH</name>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO4_LEVEL_LOW</name>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO3_EDGE_HIGH</name>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>GPIO3_EDGE_LOW</name>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>GPIO3_LEVEL_HIGH</name>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO3_LEVEL_LOW</name>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO2_EDGE_HIGH</name>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>GPIO2_EDGE_LOW</name>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>GPIO2_LEVEL_HIGH</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO2_LEVEL_LOW</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO1_EDGE_HIGH</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>GPIO1_EDGE_LOW</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>GPIO1_LEVEL_HIGH</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO1_LEVEL_LOW</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO0_EDGE_HIGH</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>GPIO0_EDGE_LOW</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>GPIO0_LEVEL_HIGH</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO0_LEVEL_LOW</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INTR1</name>
+                <addressOffset>0x00000234</addressOffset>
+                <description>Raw Interrupts</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>GPIO15_EDGE_HIGH</name>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>GPIO15_EDGE_LOW</name>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>GPIO15_LEVEL_HIGH</name>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO15_LEVEL_LOW</name>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO14_EDGE_HIGH</name>
+                        <bitRange>[27:27]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>GPIO14_EDGE_LOW</name>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>GPIO14_LEVEL_HIGH</name>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO14_LEVEL_LOW</name>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO13_EDGE_HIGH</name>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>GPIO13_EDGE_LOW</name>
+                        <bitRange>[22:22]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>GPIO13_LEVEL_HIGH</name>
+                        <bitRange>[21:21]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO13_LEVEL_LOW</name>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO12_EDGE_HIGH</name>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>GPIO12_EDGE_LOW</name>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>GPIO12_LEVEL_HIGH</name>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO12_LEVEL_LOW</name>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO11_EDGE_HIGH</name>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>GPIO11_EDGE_LOW</name>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>GPIO11_LEVEL_HIGH</name>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO11_LEVEL_LOW</name>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO10_EDGE_HIGH</name>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>GPIO10_EDGE_LOW</name>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>GPIO10_LEVEL_HIGH</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO10_LEVEL_LOW</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO9_EDGE_HIGH</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>GPIO9_EDGE_LOW</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>GPIO9_LEVEL_HIGH</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO9_LEVEL_LOW</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO8_EDGE_HIGH</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>GPIO8_EDGE_LOW</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>GPIO8_LEVEL_HIGH</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO8_LEVEL_LOW</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INTR2</name>
+                <addressOffset>0x00000238</addressOffset>
+                <description>Raw Interrupts</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>GPIO23_EDGE_HIGH</name>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>GPIO23_EDGE_LOW</name>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>GPIO23_LEVEL_HIGH</name>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO23_LEVEL_LOW</name>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO22_EDGE_HIGH</name>
+                        <bitRange>[27:27]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>GPIO22_EDGE_LOW</name>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>GPIO22_LEVEL_HIGH</name>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO22_LEVEL_LOW</name>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO21_EDGE_HIGH</name>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>GPIO21_EDGE_LOW</name>
+                        <bitRange>[22:22]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>GPIO21_LEVEL_HIGH</name>
+                        <bitRange>[21:21]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO21_LEVEL_LOW</name>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO20_EDGE_HIGH</name>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>GPIO20_EDGE_LOW</name>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>GPIO20_LEVEL_HIGH</name>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO20_LEVEL_LOW</name>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO19_EDGE_HIGH</name>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>GPIO19_EDGE_LOW</name>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>GPIO19_LEVEL_HIGH</name>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO19_LEVEL_LOW</name>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO18_EDGE_HIGH</name>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>GPIO18_EDGE_LOW</name>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>GPIO18_LEVEL_HIGH</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO18_LEVEL_LOW</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO17_EDGE_HIGH</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>GPIO17_EDGE_LOW</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>GPIO17_LEVEL_HIGH</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO17_LEVEL_LOW</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO16_EDGE_HIGH</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>GPIO16_EDGE_LOW</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>GPIO16_LEVEL_HIGH</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO16_LEVEL_LOW</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INTR3</name>
+                <addressOffset>0x0000023c</addressOffset>
+                <description>Raw Interrupts</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>GPIO31_EDGE_HIGH</name>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>GPIO31_EDGE_LOW</name>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>GPIO31_LEVEL_HIGH</name>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO31_LEVEL_LOW</name>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO30_EDGE_HIGH</name>
+                        <bitRange>[27:27]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>GPIO30_EDGE_LOW</name>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>GPIO30_LEVEL_HIGH</name>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO30_LEVEL_LOW</name>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO29_EDGE_HIGH</name>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>GPIO29_EDGE_LOW</name>
+                        <bitRange>[22:22]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>GPIO29_LEVEL_HIGH</name>
+                        <bitRange>[21:21]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO29_LEVEL_LOW</name>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO28_EDGE_HIGH</name>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>GPIO28_EDGE_LOW</name>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>GPIO28_LEVEL_HIGH</name>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO28_LEVEL_LOW</name>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO27_EDGE_HIGH</name>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>GPIO27_EDGE_LOW</name>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>GPIO27_LEVEL_HIGH</name>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO27_LEVEL_LOW</name>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO26_EDGE_HIGH</name>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>GPIO26_EDGE_LOW</name>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>GPIO26_LEVEL_HIGH</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO26_LEVEL_LOW</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO25_EDGE_HIGH</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>GPIO25_EDGE_LOW</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>GPIO25_LEVEL_HIGH</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO25_LEVEL_LOW</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO24_EDGE_HIGH</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>GPIO24_EDGE_LOW</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>GPIO24_LEVEL_HIGH</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO24_LEVEL_LOW</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INTR4</name>
+                <addressOffset>0x00000240</addressOffset>
+                <description>Raw Interrupts</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>GPIO39_EDGE_HIGH</name>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>GPIO39_EDGE_LOW</name>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>GPIO39_LEVEL_HIGH</name>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO39_LEVEL_LOW</name>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO38_EDGE_HIGH</name>
+                        <bitRange>[27:27]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>GPIO38_EDGE_LOW</name>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>GPIO38_LEVEL_HIGH</name>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO38_LEVEL_LOW</name>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO37_EDGE_HIGH</name>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>GPIO37_EDGE_LOW</name>
+                        <bitRange>[22:22]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>GPIO37_LEVEL_HIGH</name>
+                        <bitRange>[21:21]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO37_LEVEL_LOW</name>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO36_EDGE_HIGH</name>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>GPIO36_EDGE_LOW</name>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>GPIO36_LEVEL_HIGH</name>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO36_LEVEL_LOW</name>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO35_EDGE_HIGH</name>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>GPIO35_EDGE_LOW</name>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>GPIO35_LEVEL_HIGH</name>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO35_LEVEL_LOW</name>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO34_EDGE_HIGH</name>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>GPIO34_EDGE_LOW</name>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>GPIO34_LEVEL_HIGH</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO34_LEVEL_LOW</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO33_EDGE_HIGH</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>GPIO33_EDGE_LOW</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>GPIO33_LEVEL_HIGH</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO33_LEVEL_LOW</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO32_EDGE_HIGH</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>GPIO32_EDGE_LOW</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>GPIO32_LEVEL_HIGH</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO32_LEVEL_LOW</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INTR5</name>
+                <addressOffset>0x00000244</addressOffset>
+                <description>Raw Interrupts</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>GPIO47_EDGE_HIGH</name>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>GPIO47_EDGE_LOW</name>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>GPIO47_LEVEL_HIGH</name>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO47_LEVEL_LOW</name>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO46_EDGE_HIGH</name>
+                        <bitRange>[27:27]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>GPIO46_EDGE_LOW</name>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>GPIO46_LEVEL_HIGH</name>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO46_LEVEL_LOW</name>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO45_EDGE_HIGH</name>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>GPIO45_EDGE_LOW</name>
+                        <bitRange>[22:22]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>GPIO45_LEVEL_HIGH</name>
+                        <bitRange>[21:21]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO45_LEVEL_LOW</name>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO44_EDGE_HIGH</name>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>GPIO44_EDGE_LOW</name>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>GPIO44_LEVEL_HIGH</name>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO44_LEVEL_LOW</name>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO43_EDGE_HIGH</name>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>GPIO43_EDGE_LOW</name>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>GPIO43_LEVEL_HIGH</name>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO43_LEVEL_LOW</name>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO42_EDGE_HIGH</name>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>GPIO42_EDGE_LOW</name>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>GPIO42_LEVEL_HIGH</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO42_LEVEL_LOW</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO41_EDGE_HIGH</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>GPIO41_EDGE_LOW</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>GPIO41_LEVEL_HIGH</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO41_LEVEL_LOW</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO40_EDGE_HIGH</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>GPIO40_EDGE_LOW</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>GPIO40_LEVEL_HIGH</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO40_LEVEL_LOW</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PROC0_INTE0</name>
+                <addressOffset>0x00000248</addressOffset>
+                <description>Interrupt Enable for proc0</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>GPIO7_EDGE_HIGH</name>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO7_EDGE_LOW</name>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO7_LEVEL_HIGH</name>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO7_LEVEL_LOW</name>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO6_EDGE_HIGH</name>
+                        <bitRange>[27:27]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO6_EDGE_LOW</name>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO6_LEVEL_HIGH</name>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO6_LEVEL_LOW</name>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO5_EDGE_HIGH</name>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO5_EDGE_LOW</name>
+                        <bitRange>[22:22]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO5_LEVEL_HIGH</name>
+                        <bitRange>[21:21]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO5_LEVEL_LOW</name>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO4_EDGE_HIGH</name>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO4_EDGE_LOW</name>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO4_LEVEL_HIGH</name>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO4_LEVEL_LOW</name>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO3_EDGE_HIGH</name>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO3_EDGE_LOW</name>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO3_LEVEL_HIGH</name>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO3_LEVEL_LOW</name>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO2_EDGE_HIGH</name>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO2_EDGE_LOW</name>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO2_LEVEL_HIGH</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO2_LEVEL_LOW</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO1_EDGE_HIGH</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO1_EDGE_LOW</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO1_LEVEL_HIGH</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO1_LEVEL_LOW</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO0_EDGE_HIGH</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO0_EDGE_LOW</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO0_LEVEL_HIGH</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO0_LEVEL_LOW</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PROC0_INTE1</name>
+                <addressOffset>0x0000024c</addressOffset>
+                <description>Interrupt Enable for proc0</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>GPIO15_EDGE_HIGH</name>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO15_EDGE_LOW</name>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO15_LEVEL_HIGH</name>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO15_LEVEL_LOW</name>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO14_EDGE_HIGH</name>
+                        <bitRange>[27:27]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO14_EDGE_LOW</name>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO14_LEVEL_HIGH</name>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO14_LEVEL_LOW</name>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO13_EDGE_HIGH</name>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO13_EDGE_LOW</name>
+                        <bitRange>[22:22]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO13_LEVEL_HIGH</name>
+                        <bitRange>[21:21]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO13_LEVEL_LOW</name>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO12_EDGE_HIGH</name>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO12_EDGE_LOW</name>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO12_LEVEL_HIGH</name>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO12_LEVEL_LOW</name>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO11_EDGE_HIGH</name>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO11_EDGE_LOW</name>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO11_LEVEL_HIGH</name>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO11_LEVEL_LOW</name>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO10_EDGE_HIGH</name>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO10_EDGE_LOW</name>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO10_LEVEL_HIGH</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO10_LEVEL_LOW</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO9_EDGE_HIGH</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO9_EDGE_LOW</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO9_LEVEL_HIGH</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO9_LEVEL_LOW</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO8_EDGE_HIGH</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO8_EDGE_LOW</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO8_LEVEL_HIGH</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO8_LEVEL_LOW</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PROC0_INTE2</name>
+                <addressOffset>0x00000250</addressOffset>
+                <description>Interrupt Enable for proc0</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>GPIO23_EDGE_HIGH</name>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO23_EDGE_LOW</name>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO23_LEVEL_HIGH</name>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO23_LEVEL_LOW</name>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO22_EDGE_HIGH</name>
+                        <bitRange>[27:27]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO22_EDGE_LOW</name>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO22_LEVEL_HIGH</name>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO22_LEVEL_LOW</name>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO21_EDGE_HIGH</name>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO21_EDGE_LOW</name>
+                        <bitRange>[22:22]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO21_LEVEL_HIGH</name>
+                        <bitRange>[21:21]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO21_LEVEL_LOW</name>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO20_EDGE_HIGH</name>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO20_EDGE_LOW</name>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO20_LEVEL_HIGH</name>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO20_LEVEL_LOW</name>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO19_EDGE_HIGH</name>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO19_EDGE_LOW</name>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO19_LEVEL_HIGH</name>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO19_LEVEL_LOW</name>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO18_EDGE_HIGH</name>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO18_EDGE_LOW</name>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO18_LEVEL_HIGH</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO18_LEVEL_LOW</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO17_EDGE_HIGH</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO17_EDGE_LOW</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO17_LEVEL_HIGH</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO17_LEVEL_LOW</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO16_EDGE_HIGH</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO16_EDGE_LOW</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO16_LEVEL_HIGH</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO16_LEVEL_LOW</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PROC0_INTE3</name>
+                <addressOffset>0x00000254</addressOffset>
+                <description>Interrupt Enable for proc0</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>GPIO31_EDGE_HIGH</name>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO31_EDGE_LOW</name>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO31_LEVEL_HIGH</name>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO31_LEVEL_LOW</name>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO30_EDGE_HIGH</name>
+                        <bitRange>[27:27]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO30_EDGE_LOW</name>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO30_LEVEL_HIGH</name>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO30_LEVEL_LOW</name>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO29_EDGE_HIGH</name>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO29_EDGE_LOW</name>
+                        <bitRange>[22:22]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO29_LEVEL_HIGH</name>
+                        <bitRange>[21:21]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO29_LEVEL_LOW</name>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO28_EDGE_HIGH</name>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO28_EDGE_LOW</name>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO28_LEVEL_HIGH</name>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO28_LEVEL_LOW</name>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO27_EDGE_HIGH</name>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO27_EDGE_LOW</name>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO27_LEVEL_HIGH</name>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO27_LEVEL_LOW</name>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO26_EDGE_HIGH</name>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO26_EDGE_LOW</name>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO26_LEVEL_HIGH</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO26_LEVEL_LOW</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO25_EDGE_HIGH</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO25_EDGE_LOW</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO25_LEVEL_HIGH</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO25_LEVEL_LOW</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO24_EDGE_HIGH</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO24_EDGE_LOW</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO24_LEVEL_HIGH</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO24_LEVEL_LOW</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PROC0_INTE4</name>
+                <addressOffset>0x00000258</addressOffset>
+                <description>Interrupt Enable for proc0</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>GPIO39_EDGE_HIGH</name>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO39_EDGE_LOW</name>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO39_LEVEL_HIGH</name>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO39_LEVEL_LOW</name>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO38_EDGE_HIGH</name>
+                        <bitRange>[27:27]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO38_EDGE_LOW</name>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO38_LEVEL_HIGH</name>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO38_LEVEL_LOW</name>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO37_EDGE_HIGH</name>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO37_EDGE_LOW</name>
+                        <bitRange>[22:22]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO37_LEVEL_HIGH</name>
+                        <bitRange>[21:21]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO37_LEVEL_LOW</name>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO36_EDGE_HIGH</name>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO36_EDGE_LOW</name>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO36_LEVEL_HIGH</name>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO36_LEVEL_LOW</name>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO35_EDGE_HIGH</name>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO35_EDGE_LOW</name>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO35_LEVEL_HIGH</name>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO35_LEVEL_LOW</name>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO34_EDGE_HIGH</name>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO34_EDGE_LOW</name>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO34_LEVEL_HIGH</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO34_LEVEL_LOW</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO33_EDGE_HIGH</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO33_EDGE_LOW</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO33_LEVEL_HIGH</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO33_LEVEL_LOW</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO32_EDGE_HIGH</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO32_EDGE_LOW</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO32_LEVEL_HIGH</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO32_LEVEL_LOW</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PROC0_INTE5</name>
+                <addressOffset>0x0000025c</addressOffset>
+                <description>Interrupt Enable for proc0</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>GPIO47_EDGE_HIGH</name>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO47_EDGE_LOW</name>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO47_LEVEL_HIGH</name>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO47_LEVEL_LOW</name>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO46_EDGE_HIGH</name>
+                        <bitRange>[27:27]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO46_EDGE_LOW</name>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO46_LEVEL_HIGH</name>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO46_LEVEL_LOW</name>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO45_EDGE_HIGH</name>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO45_EDGE_LOW</name>
+                        <bitRange>[22:22]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO45_LEVEL_HIGH</name>
+                        <bitRange>[21:21]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO45_LEVEL_LOW</name>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO44_EDGE_HIGH</name>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO44_EDGE_LOW</name>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO44_LEVEL_HIGH</name>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO44_LEVEL_LOW</name>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO43_EDGE_HIGH</name>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO43_EDGE_LOW</name>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO43_LEVEL_HIGH</name>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO43_LEVEL_LOW</name>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO42_EDGE_HIGH</name>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO42_EDGE_LOW</name>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO42_LEVEL_HIGH</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO42_LEVEL_LOW</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO41_EDGE_HIGH</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO41_EDGE_LOW</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO41_LEVEL_HIGH</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO41_LEVEL_LOW</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO40_EDGE_HIGH</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO40_EDGE_LOW</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO40_LEVEL_HIGH</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO40_LEVEL_LOW</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PROC0_INTF0</name>
+                <addressOffset>0x00000260</addressOffset>
+                <description>Interrupt Force for proc0</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>GPIO7_EDGE_HIGH</name>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO7_EDGE_LOW</name>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO7_LEVEL_HIGH</name>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO7_LEVEL_LOW</name>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO6_EDGE_HIGH</name>
+                        <bitRange>[27:27]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO6_EDGE_LOW</name>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO6_LEVEL_HIGH</name>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO6_LEVEL_LOW</name>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO5_EDGE_HIGH</name>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO5_EDGE_LOW</name>
+                        <bitRange>[22:22]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO5_LEVEL_HIGH</name>
+                        <bitRange>[21:21]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO5_LEVEL_LOW</name>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO4_EDGE_HIGH</name>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO4_EDGE_LOW</name>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO4_LEVEL_HIGH</name>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO4_LEVEL_LOW</name>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO3_EDGE_HIGH</name>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO3_EDGE_LOW</name>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO3_LEVEL_HIGH</name>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO3_LEVEL_LOW</name>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO2_EDGE_HIGH</name>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO2_EDGE_LOW</name>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO2_LEVEL_HIGH</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO2_LEVEL_LOW</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO1_EDGE_HIGH</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO1_EDGE_LOW</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO1_LEVEL_HIGH</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO1_LEVEL_LOW</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO0_EDGE_HIGH</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO0_EDGE_LOW</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO0_LEVEL_HIGH</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO0_LEVEL_LOW</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PROC0_INTF1</name>
+                <addressOffset>0x00000264</addressOffset>
+                <description>Interrupt Force for proc0</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>GPIO15_EDGE_HIGH</name>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO15_EDGE_LOW</name>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO15_LEVEL_HIGH</name>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO15_LEVEL_LOW</name>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO14_EDGE_HIGH</name>
+                        <bitRange>[27:27]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO14_EDGE_LOW</name>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO14_LEVEL_HIGH</name>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO14_LEVEL_LOW</name>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO13_EDGE_HIGH</name>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO13_EDGE_LOW</name>
+                        <bitRange>[22:22]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO13_LEVEL_HIGH</name>
+                        <bitRange>[21:21]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO13_LEVEL_LOW</name>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO12_EDGE_HIGH</name>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO12_EDGE_LOW</name>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO12_LEVEL_HIGH</name>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO12_LEVEL_LOW</name>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO11_EDGE_HIGH</name>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO11_EDGE_LOW</name>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO11_LEVEL_HIGH</name>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO11_LEVEL_LOW</name>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO10_EDGE_HIGH</name>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO10_EDGE_LOW</name>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO10_LEVEL_HIGH</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO10_LEVEL_LOW</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO9_EDGE_HIGH</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO9_EDGE_LOW</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO9_LEVEL_HIGH</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO9_LEVEL_LOW</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO8_EDGE_HIGH</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO8_EDGE_LOW</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO8_LEVEL_HIGH</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO8_LEVEL_LOW</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PROC0_INTF2</name>
+                <addressOffset>0x00000268</addressOffset>
+                <description>Interrupt Force for proc0</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>GPIO23_EDGE_HIGH</name>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO23_EDGE_LOW</name>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO23_LEVEL_HIGH</name>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO23_LEVEL_LOW</name>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO22_EDGE_HIGH</name>
+                        <bitRange>[27:27]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO22_EDGE_LOW</name>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO22_LEVEL_HIGH</name>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO22_LEVEL_LOW</name>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO21_EDGE_HIGH</name>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO21_EDGE_LOW</name>
+                        <bitRange>[22:22]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO21_LEVEL_HIGH</name>
+                        <bitRange>[21:21]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO21_LEVEL_LOW</name>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO20_EDGE_HIGH</name>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO20_EDGE_LOW</name>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO20_LEVEL_HIGH</name>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO20_LEVEL_LOW</name>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO19_EDGE_HIGH</name>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO19_EDGE_LOW</name>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO19_LEVEL_HIGH</name>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO19_LEVEL_LOW</name>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO18_EDGE_HIGH</name>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO18_EDGE_LOW</name>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO18_LEVEL_HIGH</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO18_LEVEL_LOW</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO17_EDGE_HIGH</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO17_EDGE_LOW</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO17_LEVEL_HIGH</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO17_LEVEL_LOW</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO16_EDGE_HIGH</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO16_EDGE_LOW</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO16_LEVEL_HIGH</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO16_LEVEL_LOW</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PROC0_INTF3</name>
+                <addressOffset>0x0000026c</addressOffset>
+                <description>Interrupt Force for proc0</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>GPIO31_EDGE_HIGH</name>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO31_EDGE_LOW</name>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO31_LEVEL_HIGH</name>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO31_LEVEL_LOW</name>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO30_EDGE_HIGH</name>
+                        <bitRange>[27:27]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO30_EDGE_LOW</name>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO30_LEVEL_HIGH</name>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO30_LEVEL_LOW</name>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO29_EDGE_HIGH</name>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO29_EDGE_LOW</name>
+                        <bitRange>[22:22]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO29_LEVEL_HIGH</name>
+                        <bitRange>[21:21]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO29_LEVEL_LOW</name>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO28_EDGE_HIGH</name>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO28_EDGE_LOW</name>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO28_LEVEL_HIGH</name>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO28_LEVEL_LOW</name>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO27_EDGE_HIGH</name>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO27_EDGE_LOW</name>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO27_LEVEL_HIGH</name>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO27_LEVEL_LOW</name>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO26_EDGE_HIGH</name>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO26_EDGE_LOW</name>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO26_LEVEL_HIGH</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO26_LEVEL_LOW</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO25_EDGE_HIGH</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO25_EDGE_LOW</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO25_LEVEL_HIGH</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO25_LEVEL_LOW</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO24_EDGE_HIGH</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO24_EDGE_LOW</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO24_LEVEL_HIGH</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO24_LEVEL_LOW</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PROC0_INTF4</name>
+                <addressOffset>0x00000270</addressOffset>
+                <description>Interrupt Force for proc0</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>GPIO39_EDGE_HIGH</name>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO39_EDGE_LOW</name>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO39_LEVEL_HIGH</name>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO39_LEVEL_LOW</name>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO38_EDGE_HIGH</name>
+                        <bitRange>[27:27]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO38_EDGE_LOW</name>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO38_LEVEL_HIGH</name>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO38_LEVEL_LOW</name>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO37_EDGE_HIGH</name>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO37_EDGE_LOW</name>
+                        <bitRange>[22:22]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO37_LEVEL_HIGH</name>
+                        <bitRange>[21:21]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO37_LEVEL_LOW</name>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO36_EDGE_HIGH</name>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO36_EDGE_LOW</name>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO36_LEVEL_HIGH</name>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO36_LEVEL_LOW</name>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO35_EDGE_HIGH</name>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO35_EDGE_LOW</name>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO35_LEVEL_HIGH</name>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO35_LEVEL_LOW</name>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO34_EDGE_HIGH</name>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO34_EDGE_LOW</name>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO34_LEVEL_HIGH</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO34_LEVEL_LOW</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO33_EDGE_HIGH</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO33_EDGE_LOW</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO33_LEVEL_HIGH</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO33_LEVEL_LOW</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO32_EDGE_HIGH</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO32_EDGE_LOW</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO32_LEVEL_HIGH</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO32_LEVEL_LOW</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PROC0_INTF5</name>
+                <addressOffset>0x00000274</addressOffset>
+                <description>Interrupt Force for proc0</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>GPIO47_EDGE_HIGH</name>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO47_EDGE_LOW</name>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO47_LEVEL_HIGH</name>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO47_LEVEL_LOW</name>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO46_EDGE_HIGH</name>
+                        <bitRange>[27:27]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO46_EDGE_LOW</name>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO46_LEVEL_HIGH</name>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO46_LEVEL_LOW</name>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO45_EDGE_HIGH</name>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO45_EDGE_LOW</name>
+                        <bitRange>[22:22]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO45_LEVEL_HIGH</name>
+                        <bitRange>[21:21]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO45_LEVEL_LOW</name>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO44_EDGE_HIGH</name>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO44_EDGE_LOW</name>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO44_LEVEL_HIGH</name>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO44_LEVEL_LOW</name>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO43_EDGE_HIGH</name>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO43_EDGE_LOW</name>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO43_LEVEL_HIGH</name>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO43_LEVEL_LOW</name>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO42_EDGE_HIGH</name>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO42_EDGE_LOW</name>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO42_LEVEL_HIGH</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO42_LEVEL_LOW</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO41_EDGE_HIGH</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO41_EDGE_LOW</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO41_LEVEL_HIGH</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO41_LEVEL_LOW</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO40_EDGE_HIGH</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO40_EDGE_LOW</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO40_LEVEL_HIGH</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO40_LEVEL_LOW</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PROC0_INTS0</name>
+                <addressOffset>0x00000278</addressOffset>
+                <description>Interrupt status after masking &amp; forcing for proc0</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>GPIO7_EDGE_HIGH</name>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO7_EDGE_LOW</name>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO7_LEVEL_HIGH</name>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO7_LEVEL_LOW</name>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO6_EDGE_HIGH</name>
+                        <bitRange>[27:27]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO6_EDGE_LOW</name>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO6_LEVEL_HIGH</name>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO6_LEVEL_LOW</name>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO5_EDGE_HIGH</name>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO5_EDGE_LOW</name>
+                        <bitRange>[22:22]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO5_LEVEL_HIGH</name>
+                        <bitRange>[21:21]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO5_LEVEL_LOW</name>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO4_EDGE_HIGH</name>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO4_EDGE_LOW</name>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO4_LEVEL_HIGH</name>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO4_LEVEL_LOW</name>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO3_EDGE_HIGH</name>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO3_EDGE_LOW</name>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO3_LEVEL_HIGH</name>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO3_LEVEL_LOW</name>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO2_EDGE_HIGH</name>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO2_EDGE_LOW</name>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO2_LEVEL_HIGH</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO2_LEVEL_LOW</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO1_EDGE_HIGH</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO1_EDGE_LOW</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO1_LEVEL_HIGH</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO1_LEVEL_LOW</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO0_EDGE_HIGH</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO0_EDGE_LOW</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO0_LEVEL_HIGH</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO0_LEVEL_LOW</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PROC0_INTS1</name>
+                <addressOffset>0x0000027c</addressOffset>
+                <description>Interrupt status after masking &amp; forcing for proc0</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>GPIO15_EDGE_HIGH</name>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO15_EDGE_LOW</name>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO15_LEVEL_HIGH</name>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO15_LEVEL_LOW</name>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO14_EDGE_HIGH</name>
+                        <bitRange>[27:27]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO14_EDGE_LOW</name>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO14_LEVEL_HIGH</name>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO14_LEVEL_LOW</name>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO13_EDGE_HIGH</name>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO13_EDGE_LOW</name>
+                        <bitRange>[22:22]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO13_LEVEL_HIGH</name>
+                        <bitRange>[21:21]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO13_LEVEL_LOW</name>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO12_EDGE_HIGH</name>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO12_EDGE_LOW</name>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO12_LEVEL_HIGH</name>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO12_LEVEL_LOW</name>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO11_EDGE_HIGH</name>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO11_EDGE_LOW</name>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO11_LEVEL_HIGH</name>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO11_LEVEL_LOW</name>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO10_EDGE_HIGH</name>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO10_EDGE_LOW</name>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO10_LEVEL_HIGH</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO10_LEVEL_LOW</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO9_EDGE_HIGH</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO9_EDGE_LOW</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO9_LEVEL_HIGH</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO9_LEVEL_LOW</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO8_EDGE_HIGH</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO8_EDGE_LOW</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO8_LEVEL_HIGH</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO8_LEVEL_LOW</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PROC0_INTS2</name>
+                <addressOffset>0x00000280</addressOffset>
+                <description>Interrupt status after masking &amp; forcing for proc0</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>GPIO23_EDGE_HIGH</name>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO23_EDGE_LOW</name>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO23_LEVEL_HIGH</name>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO23_LEVEL_LOW</name>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO22_EDGE_HIGH</name>
+                        <bitRange>[27:27]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO22_EDGE_LOW</name>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO22_LEVEL_HIGH</name>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO22_LEVEL_LOW</name>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO21_EDGE_HIGH</name>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO21_EDGE_LOW</name>
+                        <bitRange>[22:22]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO21_LEVEL_HIGH</name>
+                        <bitRange>[21:21]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO21_LEVEL_LOW</name>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO20_EDGE_HIGH</name>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO20_EDGE_LOW</name>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO20_LEVEL_HIGH</name>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO20_LEVEL_LOW</name>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO19_EDGE_HIGH</name>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO19_EDGE_LOW</name>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO19_LEVEL_HIGH</name>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO19_LEVEL_LOW</name>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO18_EDGE_HIGH</name>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO18_EDGE_LOW</name>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO18_LEVEL_HIGH</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO18_LEVEL_LOW</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO17_EDGE_HIGH</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO17_EDGE_LOW</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO17_LEVEL_HIGH</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO17_LEVEL_LOW</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO16_EDGE_HIGH</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO16_EDGE_LOW</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO16_LEVEL_HIGH</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO16_LEVEL_LOW</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PROC0_INTS3</name>
+                <addressOffset>0x00000284</addressOffset>
+                <description>Interrupt status after masking &amp; forcing for proc0</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>GPIO31_EDGE_HIGH</name>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO31_EDGE_LOW</name>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO31_LEVEL_HIGH</name>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO31_LEVEL_LOW</name>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO30_EDGE_HIGH</name>
+                        <bitRange>[27:27]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO30_EDGE_LOW</name>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO30_LEVEL_HIGH</name>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO30_LEVEL_LOW</name>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO29_EDGE_HIGH</name>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO29_EDGE_LOW</name>
+                        <bitRange>[22:22]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO29_LEVEL_HIGH</name>
+                        <bitRange>[21:21]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO29_LEVEL_LOW</name>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO28_EDGE_HIGH</name>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO28_EDGE_LOW</name>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO28_LEVEL_HIGH</name>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO28_LEVEL_LOW</name>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO27_EDGE_HIGH</name>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO27_EDGE_LOW</name>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO27_LEVEL_HIGH</name>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO27_LEVEL_LOW</name>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO26_EDGE_HIGH</name>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO26_EDGE_LOW</name>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO26_LEVEL_HIGH</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO26_LEVEL_LOW</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO25_EDGE_HIGH</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO25_EDGE_LOW</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO25_LEVEL_HIGH</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO25_LEVEL_LOW</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO24_EDGE_HIGH</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO24_EDGE_LOW</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO24_LEVEL_HIGH</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO24_LEVEL_LOW</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PROC0_INTS4</name>
+                <addressOffset>0x00000288</addressOffset>
+                <description>Interrupt status after masking &amp; forcing for proc0</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>GPIO39_EDGE_HIGH</name>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO39_EDGE_LOW</name>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO39_LEVEL_HIGH</name>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO39_LEVEL_LOW</name>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO38_EDGE_HIGH</name>
+                        <bitRange>[27:27]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO38_EDGE_LOW</name>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO38_LEVEL_HIGH</name>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO38_LEVEL_LOW</name>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO37_EDGE_HIGH</name>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO37_EDGE_LOW</name>
+                        <bitRange>[22:22]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO37_LEVEL_HIGH</name>
+                        <bitRange>[21:21]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO37_LEVEL_LOW</name>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO36_EDGE_HIGH</name>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO36_EDGE_LOW</name>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO36_LEVEL_HIGH</name>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO36_LEVEL_LOW</name>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO35_EDGE_HIGH</name>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO35_EDGE_LOW</name>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO35_LEVEL_HIGH</name>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO35_LEVEL_LOW</name>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO34_EDGE_HIGH</name>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO34_EDGE_LOW</name>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO34_LEVEL_HIGH</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO34_LEVEL_LOW</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO33_EDGE_HIGH</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO33_EDGE_LOW</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO33_LEVEL_HIGH</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO33_LEVEL_LOW</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO32_EDGE_HIGH</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO32_EDGE_LOW</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO32_LEVEL_HIGH</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO32_LEVEL_LOW</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PROC0_INTS5</name>
+                <addressOffset>0x0000028c</addressOffset>
+                <description>Interrupt status after masking &amp; forcing for proc0</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>GPIO47_EDGE_HIGH</name>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO47_EDGE_LOW</name>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO47_LEVEL_HIGH</name>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO47_LEVEL_LOW</name>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO46_EDGE_HIGH</name>
+                        <bitRange>[27:27]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO46_EDGE_LOW</name>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO46_LEVEL_HIGH</name>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO46_LEVEL_LOW</name>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO45_EDGE_HIGH</name>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO45_EDGE_LOW</name>
+                        <bitRange>[22:22]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO45_LEVEL_HIGH</name>
+                        <bitRange>[21:21]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO45_LEVEL_LOW</name>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO44_EDGE_HIGH</name>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO44_EDGE_LOW</name>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO44_LEVEL_HIGH</name>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO44_LEVEL_LOW</name>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO43_EDGE_HIGH</name>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO43_EDGE_LOW</name>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO43_LEVEL_HIGH</name>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO43_LEVEL_LOW</name>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO42_EDGE_HIGH</name>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO42_EDGE_LOW</name>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO42_LEVEL_HIGH</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO42_LEVEL_LOW</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO41_EDGE_HIGH</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO41_EDGE_LOW</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO41_LEVEL_HIGH</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO41_LEVEL_LOW</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO40_EDGE_HIGH</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO40_EDGE_LOW</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO40_LEVEL_HIGH</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO40_LEVEL_LOW</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PROC1_INTE0</name>
+                <addressOffset>0x00000290</addressOffset>
+                <description>Interrupt Enable for proc1</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>GPIO7_EDGE_HIGH</name>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO7_EDGE_LOW</name>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO7_LEVEL_HIGH</name>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO7_LEVEL_LOW</name>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO6_EDGE_HIGH</name>
+                        <bitRange>[27:27]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO6_EDGE_LOW</name>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO6_LEVEL_HIGH</name>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO6_LEVEL_LOW</name>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO5_EDGE_HIGH</name>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO5_EDGE_LOW</name>
+                        <bitRange>[22:22]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO5_LEVEL_HIGH</name>
+                        <bitRange>[21:21]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO5_LEVEL_LOW</name>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO4_EDGE_HIGH</name>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO4_EDGE_LOW</name>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO4_LEVEL_HIGH</name>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO4_LEVEL_LOW</name>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO3_EDGE_HIGH</name>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO3_EDGE_LOW</name>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO3_LEVEL_HIGH</name>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO3_LEVEL_LOW</name>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO2_EDGE_HIGH</name>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO2_EDGE_LOW</name>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO2_LEVEL_HIGH</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO2_LEVEL_LOW</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO1_EDGE_HIGH</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO1_EDGE_LOW</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO1_LEVEL_HIGH</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO1_LEVEL_LOW</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO0_EDGE_HIGH</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO0_EDGE_LOW</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO0_LEVEL_HIGH</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO0_LEVEL_LOW</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PROC1_INTE1</name>
+                <addressOffset>0x00000294</addressOffset>
+                <description>Interrupt Enable for proc1</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>GPIO15_EDGE_HIGH</name>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO15_EDGE_LOW</name>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO15_LEVEL_HIGH</name>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO15_LEVEL_LOW</name>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO14_EDGE_HIGH</name>
+                        <bitRange>[27:27]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO14_EDGE_LOW</name>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO14_LEVEL_HIGH</name>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO14_LEVEL_LOW</name>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO13_EDGE_HIGH</name>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO13_EDGE_LOW</name>
+                        <bitRange>[22:22]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO13_LEVEL_HIGH</name>
+                        <bitRange>[21:21]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO13_LEVEL_LOW</name>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO12_EDGE_HIGH</name>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO12_EDGE_LOW</name>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO12_LEVEL_HIGH</name>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO12_LEVEL_LOW</name>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO11_EDGE_HIGH</name>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO11_EDGE_LOW</name>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO11_LEVEL_HIGH</name>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO11_LEVEL_LOW</name>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO10_EDGE_HIGH</name>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO10_EDGE_LOW</name>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO10_LEVEL_HIGH</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO10_LEVEL_LOW</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO9_EDGE_HIGH</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO9_EDGE_LOW</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO9_LEVEL_HIGH</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO9_LEVEL_LOW</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO8_EDGE_HIGH</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO8_EDGE_LOW</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO8_LEVEL_HIGH</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO8_LEVEL_LOW</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PROC1_INTE2</name>
+                <addressOffset>0x00000298</addressOffset>
+                <description>Interrupt Enable for proc1</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>GPIO23_EDGE_HIGH</name>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO23_EDGE_LOW</name>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO23_LEVEL_HIGH</name>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO23_LEVEL_LOW</name>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO22_EDGE_HIGH</name>
+                        <bitRange>[27:27]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO22_EDGE_LOW</name>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO22_LEVEL_HIGH</name>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO22_LEVEL_LOW</name>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO21_EDGE_HIGH</name>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO21_EDGE_LOW</name>
+                        <bitRange>[22:22]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO21_LEVEL_HIGH</name>
+                        <bitRange>[21:21]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO21_LEVEL_LOW</name>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO20_EDGE_HIGH</name>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO20_EDGE_LOW</name>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO20_LEVEL_HIGH</name>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO20_LEVEL_LOW</name>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO19_EDGE_HIGH</name>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO19_EDGE_LOW</name>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO19_LEVEL_HIGH</name>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO19_LEVEL_LOW</name>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO18_EDGE_HIGH</name>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO18_EDGE_LOW</name>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO18_LEVEL_HIGH</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO18_LEVEL_LOW</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO17_EDGE_HIGH</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO17_EDGE_LOW</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO17_LEVEL_HIGH</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO17_LEVEL_LOW</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO16_EDGE_HIGH</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO16_EDGE_LOW</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO16_LEVEL_HIGH</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO16_LEVEL_LOW</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PROC1_INTE3</name>
+                <addressOffset>0x0000029c</addressOffset>
+                <description>Interrupt Enable for proc1</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>GPIO31_EDGE_HIGH</name>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO31_EDGE_LOW</name>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO31_LEVEL_HIGH</name>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO31_LEVEL_LOW</name>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO30_EDGE_HIGH</name>
+                        <bitRange>[27:27]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO30_EDGE_LOW</name>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO30_LEVEL_HIGH</name>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO30_LEVEL_LOW</name>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO29_EDGE_HIGH</name>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO29_EDGE_LOW</name>
+                        <bitRange>[22:22]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO29_LEVEL_HIGH</name>
+                        <bitRange>[21:21]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO29_LEVEL_LOW</name>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO28_EDGE_HIGH</name>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO28_EDGE_LOW</name>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO28_LEVEL_HIGH</name>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO28_LEVEL_LOW</name>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO27_EDGE_HIGH</name>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO27_EDGE_LOW</name>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO27_LEVEL_HIGH</name>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO27_LEVEL_LOW</name>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO26_EDGE_HIGH</name>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO26_EDGE_LOW</name>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO26_LEVEL_HIGH</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO26_LEVEL_LOW</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO25_EDGE_HIGH</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO25_EDGE_LOW</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO25_LEVEL_HIGH</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO25_LEVEL_LOW</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO24_EDGE_HIGH</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO24_EDGE_LOW</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO24_LEVEL_HIGH</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO24_LEVEL_LOW</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PROC1_INTE4</name>
+                <addressOffset>0x000002a0</addressOffset>
+                <description>Interrupt Enable for proc1</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>GPIO39_EDGE_HIGH</name>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO39_EDGE_LOW</name>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO39_LEVEL_HIGH</name>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO39_LEVEL_LOW</name>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO38_EDGE_HIGH</name>
+                        <bitRange>[27:27]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO38_EDGE_LOW</name>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO38_LEVEL_HIGH</name>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO38_LEVEL_LOW</name>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO37_EDGE_HIGH</name>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO37_EDGE_LOW</name>
+                        <bitRange>[22:22]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO37_LEVEL_HIGH</name>
+                        <bitRange>[21:21]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO37_LEVEL_LOW</name>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO36_EDGE_HIGH</name>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO36_EDGE_LOW</name>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO36_LEVEL_HIGH</name>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO36_LEVEL_LOW</name>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO35_EDGE_HIGH</name>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO35_EDGE_LOW</name>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO35_LEVEL_HIGH</name>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO35_LEVEL_LOW</name>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO34_EDGE_HIGH</name>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO34_EDGE_LOW</name>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO34_LEVEL_HIGH</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO34_LEVEL_LOW</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO33_EDGE_HIGH</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO33_EDGE_LOW</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO33_LEVEL_HIGH</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO33_LEVEL_LOW</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO32_EDGE_HIGH</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO32_EDGE_LOW</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO32_LEVEL_HIGH</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO32_LEVEL_LOW</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PROC1_INTE5</name>
+                <addressOffset>0x000002a4</addressOffset>
+                <description>Interrupt Enable for proc1</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>GPIO47_EDGE_HIGH</name>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO47_EDGE_LOW</name>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO47_LEVEL_HIGH</name>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO47_LEVEL_LOW</name>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO46_EDGE_HIGH</name>
+                        <bitRange>[27:27]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO46_EDGE_LOW</name>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO46_LEVEL_HIGH</name>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO46_LEVEL_LOW</name>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO45_EDGE_HIGH</name>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO45_EDGE_LOW</name>
+                        <bitRange>[22:22]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO45_LEVEL_HIGH</name>
+                        <bitRange>[21:21]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO45_LEVEL_LOW</name>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO44_EDGE_HIGH</name>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO44_EDGE_LOW</name>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO44_LEVEL_HIGH</name>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO44_LEVEL_LOW</name>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO43_EDGE_HIGH</name>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO43_EDGE_LOW</name>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO43_LEVEL_HIGH</name>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO43_LEVEL_LOW</name>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO42_EDGE_HIGH</name>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO42_EDGE_LOW</name>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO42_LEVEL_HIGH</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO42_LEVEL_LOW</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO41_EDGE_HIGH</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO41_EDGE_LOW</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO41_LEVEL_HIGH</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO41_LEVEL_LOW</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO40_EDGE_HIGH</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO40_EDGE_LOW</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO40_LEVEL_HIGH</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO40_LEVEL_LOW</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PROC1_INTF0</name>
+                <addressOffset>0x000002a8</addressOffset>
+                <description>Interrupt Force for proc1</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>GPIO7_EDGE_HIGH</name>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO7_EDGE_LOW</name>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO7_LEVEL_HIGH</name>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO7_LEVEL_LOW</name>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO6_EDGE_HIGH</name>
+                        <bitRange>[27:27]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO6_EDGE_LOW</name>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO6_LEVEL_HIGH</name>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO6_LEVEL_LOW</name>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO5_EDGE_HIGH</name>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO5_EDGE_LOW</name>
+                        <bitRange>[22:22]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO5_LEVEL_HIGH</name>
+                        <bitRange>[21:21]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO5_LEVEL_LOW</name>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO4_EDGE_HIGH</name>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO4_EDGE_LOW</name>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO4_LEVEL_HIGH</name>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO4_LEVEL_LOW</name>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO3_EDGE_HIGH</name>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO3_EDGE_LOW</name>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO3_LEVEL_HIGH</name>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO3_LEVEL_LOW</name>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO2_EDGE_HIGH</name>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO2_EDGE_LOW</name>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO2_LEVEL_HIGH</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO2_LEVEL_LOW</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO1_EDGE_HIGH</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO1_EDGE_LOW</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO1_LEVEL_HIGH</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO1_LEVEL_LOW</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO0_EDGE_HIGH</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO0_EDGE_LOW</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO0_LEVEL_HIGH</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO0_LEVEL_LOW</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PROC1_INTF1</name>
+                <addressOffset>0x000002ac</addressOffset>
+                <description>Interrupt Force for proc1</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>GPIO15_EDGE_HIGH</name>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO15_EDGE_LOW</name>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO15_LEVEL_HIGH</name>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO15_LEVEL_LOW</name>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO14_EDGE_HIGH</name>
+                        <bitRange>[27:27]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO14_EDGE_LOW</name>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO14_LEVEL_HIGH</name>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO14_LEVEL_LOW</name>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO13_EDGE_HIGH</name>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO13_EDGE_LOW</name>
+                        <bitRange>[22:22]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO13_LEVEL_HIGH</name>
+                        <bitRange>[21:21]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO13_LEVEL_LOW</name>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO12_EDGE_HIGH</name>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO12_EDGE_LOW</name>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO12_LEVEL_HIGH</name>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO12_LEVEL_LOW</name>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO11_EDGE_HIGH</name>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO11_EDGE_LOW</name>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO11_LEVEL_HIGH</name>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO11_LEVEL_LOW</name>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO10_EDGE_HIGH</name>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO10_EDGE_LOW</name>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO10_LEVEL_HIGH</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO10_LEVEL_LOW</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO9_EDGE_HIGH</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO9_EDGE_LOW</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO9_LEVEL_HIGH</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO9_LEVEL_LOW</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO8_EDGE_HIGH</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO8_EDGE_LOW</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO8_LEVEL_HIGH</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO8_LEVEL_LOW</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PROC1_INTF2</name>
+                <addressOffset>0x000002b0</addressOffset>
+                <description>Interrupt Force for proc1</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>GPIO23_EDGE_HIGH</name>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO23_EDGE_LOW</name>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO23_LEVEL_HIGH</name>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO23_LEVEL_LOW</name>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO22_EDGE_HIGH</name>
+                        <bitRange>[27:27]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO22_EDGE_LOW</name>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO22_LEVEL_HIGH</name>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO22_LEVEL_LOW</name>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO21_EDGE_HIGH</name>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO21_EDGE_LOW</name>
+                        <bitRange>[22:22]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO21_LEVEL_HIGH</name>
+                        <bitRange>[21:21]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO21_LEVEL_LOW</name>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO20_EDGE_HIGH</name>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO20_EDGE_LOW</name>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO20_LEVEL_HIGH</name>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO20_LEVEL_LOW</name>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO19_EDGE_HIGH</name>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO19_EDGE_LOW</name>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO19_LEVEL_HIGH</name>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO19_LEVEL_LOW</name>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO18_EDGE_HIGH</name>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO18_EDGE_LOW</name>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO18_LEVEL_HIGH</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO18_LEVEL_LOW</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO17_EDGE_HIGH</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO17_EDGE_LOW</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO17_LEVEL_HIGH</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO17_LEVEL_LOW</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO16_EDGE_HIGH</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO16_EDGE_LOW</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO16_LEVEL_HIGH</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO16_LEVEL_LOW</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PROC1_INTF3</name>
+                <addressOffset>0x000002b4</addressOffset>
+                <description>Interrupt Force for proc1</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>GPIO31_EDGE_HIGH</name>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO31_EDGE_LOW</name>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO31_LEVEL_HIGH</name>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO31_LEVEL_LOW</name>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO30_EDGE_HIGH</name>
+                        <bitRange>[27:27]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO30_EDGE_LOW</name>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO30_LEVEL_HIGH</name>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO30_LEVEL_LOW</name>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO29_EDGE_HIGH</name>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO29_EDGE_LOW</name>
+                        <bitRange>[22:22]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO29_LEVEL_HIGH</name>
+                        <bitRange>[21:21]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO29_LEVEL_LOW</name>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO28_EDGE_HIGH</name>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO28_EDGE_LOW</name>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO28_LEVEL_HIGH</name>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO28_LEVEL_LOW</name>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO27_EDGE_HIGH</name>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO27_EDGE_LOW</name>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO27_LEVEL_HIGH</name>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO27_LEVEL_LOW</name>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO26_EDGE_HIGH</name>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO26_EDGE_LOW</name>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO26_LEVEL_HIGH</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO26_LEVEL_LOW</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO25_EDGE_HIGH</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO25_EDGE_LOW</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO25_LEVEL_HIGH</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO25_LEVEL_LOW</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO24_EDGE_HIGH</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO24_EDGE_LOW</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO24_LEVEL_HIGH</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO24_LEVEL_LOW</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PROC1_INTF4</name>
+                <addressOffset>0x000002b8</addressOffset>
+                <description>Interrupt Force for proc1</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>GPIO39_EDGE_HIGH</name>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO39_EDGE_LOW</name>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO39_LEVEL_HIGH</name>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO39_LEVEL_LOW</name>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO38_EDGE_HIGH</name>
+                        <bitRange>[27:27]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO38_EDGE_LOW</name>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO38_LEVEL_HIGH</name>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO38_LEVEL_LOW</name>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO37_EDGE_HIGH</name>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO37_EDGE_LOW</name>
+                        <bitRange>[22:22]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO37_LEVEL_HIGH</name>
+                        <bitRange>[21:21]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO37_LEVEL_LOW</name>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO36_EDGE_HIGH</name>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO36_EDGE_LOW</name>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO36_LEVEL_HIGH</name>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO36_LEVEL_LOW</name>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO35_EDGE_HIGH</name>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO35_EDGE_LOW</name>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO35_LEVEL_HIGH</name>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO35_LEVEL_LOW</name>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO34_EDGE_HIGH</name>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO34_EDGE_LOW</name>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO34_LEVEL_HIGH</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO34_LEVEL_LOW</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO33_EDGE_HIGH</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO33_EDGE_LOW</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO33_LEVEL_HIGH</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO33_LEVEL_LOW</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO32_EDGE_HIGH</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO32_EDGE_LOW</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO32_LEVEL_HIGH</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO32_LEVEL_LOW</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PROC1_INTF5</name>
+                <addressOffset>0x000002bc</addressOffset>
+                <description>Interrupt Force for proc1</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>GPIO47_EDGE_HIGH</name>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO47_EDGE_LOW</name>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO47_LEVEL_HIGH</name>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO47_LEVEL_LOW</name>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO46_EDGE_HIGH</name>
+                        <bitRange>[27:27]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO46_EDGE_LOW</name>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO46_LEVEL_HIGH</name>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO46_LEVEL_LOW</name>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO45_EDGE_HIGH</name>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO45_EDGE_LOW</name>
+                        <bitRange>[22:22]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO45_LEVEL_HIGH</name>
+                        <bitRange>[21:21]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO45_LEVEL_LOW</name>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO44_EDGE_HIGH</name>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO44_EDGE_LOW</name>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO44_LEVEL_HIGH</name>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO44_LEVEL_LOW</name>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO43_EDGE_HIGH</name>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO43_EDGE_LOW</name>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO43_LEVEL_HIGH</name>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO43_LEVEL_LOW</name>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO42_EDGE_HIGH</name>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO42_EDGE_LOW</name>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO42_LEVEL_HIGH</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO42_LEVEL_LOW</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO41_EDGE_HIGH</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO41_EDGE_LOW</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO41_LEVEL_HIGH</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO41_LEVEL_LOW</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO40_EDGE_HIGH</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO40_EDGE_LOW</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO40_LEVEL_HIGH</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO40_LEVEL_LOW</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PROC1_INTS0</name>
+                <addressOffset>0x000002c0</addressOffset>
+                <description>Interrupt status after masking &amp; forcing for proc1</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>GPIO7_EDGE_HIGH</name>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO7_EDGE_LOW</name>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO7_LEVEL_HIGH</name>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO7_LEVEL_LOW</name>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO6_EDGE_HIGH</name>
+                        <bitRange>[27:27]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO6_EDGE_LOW</name>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO6_LEVEL_HIGH</name>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO6_LEVEL_LOW</name>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO5_EDGE_HIGH</name>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO5_EDGE_LOW</name>
+                        <bitRange>[22:22]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO5_LEVEL_HIGH</name>
+                        <bitRange>[21:21]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO5_LEVEL_LOW</name>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO4_EDGE_HIGH</name>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO4_EDGE_LOW</name>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO4_LEVEL_HIGH</name>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO4_LEVEL_LOW</name>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO3_EDGE_HIGH</name>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO3_EDGE_LOW</name>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO3_LEVEL_HIGH</name>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO3_LEVEL_LOW</name>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO2_EDGE_HIGH</name>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO2_EDGE_LOW</name>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO2_LEVEL_HIGH</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO2_LEVEL_LOW</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO1_EDGE_HIGH</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO1_EDGE_LOW</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO1_LEVEL_HIGH</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO1_LEVEL_LOW</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO0_EDGE_HIGH</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO0_EDGE_LOW</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO0_LEVEL_HIGH</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO0_LEVEL_LOW</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PROC1_INTS1</name>
+                <addressOffset>0x000002c4</addressOffset>
+                <description>Interrupt status after masking &amp; forcing for proc1</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>GPIO15_EDGE_HIGH</name>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO15_EDGE_LOW</name>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO15_LEVEL_HIGH</name>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO15_LEVEL_LOW</name>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO14_EDGE_HIGH</name>
+                        <bitRange>[27:27]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO14_EDGE_LOW</name>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO14_LEVEL_HIGH</name>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO14_LEVEL_LOW</name>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO13_EDGE_HIGH</name>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO13_EDGE_LOW</name>
+                        <bitRange>[22:22]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO13_LEVEL_HIGH</name>
+                        <bitRange>[21:21]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO13_LEVEL_LOW</name>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO12_EDGE_HIGH</name>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO12_EDGE_LOW</name>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO12_LEVEL_HIGH</name>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO12_LEVEL_LOW</name>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO11_EDGE_HIGH</name>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO11_EDGE_LOW</name>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO11_LEVEL_HIGH</name>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO11_LEVEL_LOW</name>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO10_EDGE_HIGH</name>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO10_EDGE_LOW</name>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO10_LEVEL_HIGH</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO10_LEVEL_LOW</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO9_EDGE_HIGH</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO9_EDGE_LOW</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO9_LEVEL_HIGH</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO9_LEVEL_LOW</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO8_EDGE_HIGH</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO8_EDGE_LOW</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO8_LEVEL_HIGH</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO8_LEVEL_LOW</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PROC1_INTS2</name>
+                <addressOffset>0x000002c8</addressOffset>
+                <description>Interrupt status after masking &amp; forcing for proc1</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>GPIO23_EDGE_HIGH</name>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO23_EDGE_LOW</name>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO23_LEVEL_HIGH</name>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO23_LEVEL_LOW</name>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO22_EDGE_HIGH</name>
+                        <bitRange>[27:27]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO22_EDGE_LOW</name>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO22_LEVEL_HIGH</name>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO22_LEVEL_LOW</name>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO21_EDGE_HIGH</name>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO21_EDGE_LOW</name>
+                        <bitRange>[22:22]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO21_LEVEL_HIGH</name>
+                        <bitRange>[21:21]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO21_LEVEL_LOW</name>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO20_EDGE_HIGH</name>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO20_EDGE_LOW</name>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO20_LEVEL_HIGH</name>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO20_LEVEL_LOW</name>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO19_EDGE_HIGH</name>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO19_EDGE_LOW</name>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO19_LEVEL_HIGH</name>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO19_LEVEL_LOW</name>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO18_EDGE_HIGH</name>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO18_EDGE_LOW</name>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO18_LEVEL_HIGH</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO18_LEVEL_LOW</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO17_EDGE_HIGH</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO17_EDGE_LOW</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO17_LEVEL_HIGH</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO17_LEVEL_LOW</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO16_EDGE_HIGH</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO16_EDGE_LOW</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO16_LEVEL_HIGH</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO16_LEVEL_LOW</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PROC1_INTS3</name>
+                <addressOffset>0x000002cc</addressOffset>
+                <description>Interrupt status after masking &amp; forcing for proc1</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>GPIO31_EDGE_HIGH</name>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO31_EDGE_LOW</name>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO31_LEVEL_HIGH</name>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO31_LEVEL_LOW</name>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO30_EDGE_HIGH</name>
+                        <bitRange>[27:27]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO30_EDGE_LOW</name>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO30_LEVEL_HIGH</name>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO30_LEVEL_LOW</name>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO29_EDGE_HIGH</name>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO29_EDGE_LOW</name>
+                        <bitRange>[22:22]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO29_LEVEL_HIGH</name>
+                        <bitRange>[21:21]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO29_LEVEL_LOW</name>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO28_EDGE_HIGH</name>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO28_EDGE_LOW</name>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO28_LEVEL_HIGH</name>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO28_LEVEL_LOW</name>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO27_EDGE_HIGH</name>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO27_EDGE_LOW</name>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO27_LEVEL_HIGH</name>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO27_LEVEL_LOW</name>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO26_EDGE_HIGH</name>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO26_EDGE_LOW</name>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO26_LEVEL_HIGH</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO26_LEVEL_LOW</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO25_EDGE_HIGH</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO25_EDGE_LOW</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO25_LEVEL_HIGH</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO25_LEVEL_LOW</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO24_EDGE_HIGH</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO24_EDGE_LOW</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO24_LEVEL_HIGH</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO24_LEVEL_LOW</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PROC1_INTS4</name>
+                <addressOffset>0x000002d0</addressOffset>
+                <description>Interrupt status after masking &amp; forcing for proc1</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>GPIO39_EDGE_HIGH</name>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO39_EDGE_LOW</name>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO39_LEVEL_HIGH</name>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO39_LEVEL_LOW</name>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO38_EDGE_HIGH</name>
+                        <bitRange>[27:27]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO38_EDGE_LOW</name>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO38_LEVEL_HIGH</name>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO38_LEVEL_LOW</name>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO37_EDGE_HIGH</name>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO37_EDGE_LOW</name>
+                        <bitRange>[22:22]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO37_LEVEL_HIGH</name>
+                        <bitRange>[21:21]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO37_LEVEL_LOW</name>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO36_EDGE_HIGH</name>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO36_EDGE_LOW</name>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO36_LEVEL_HIGH</name>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO36_LEVEL_LOW</name>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO35_EDGE_HIGH</name>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO35_EDGE_LOW</name>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO35_LEVEL_HIGH</name>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO35_LEVEL_LOW</name>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO34_EDGE_HIGH</name>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO34_EDGE_LOW</name>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO34_LEVEL_HIGH</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO34_LEVEL_LOW</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO33_EDGE_HIGH</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO33_EDGE_LOW</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO33_LEVEL_HIGH</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO33_LEVEL_LOW</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO32_EDGE_HIGH</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO32_EDGE_LOW</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO32_LEVEL_HIGH</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO32_LEVEL_LOW</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PROC1_INTS5</name>
+                <addressOffset>0x000002d4</addressOffset>
+                <description>Interrupt status after masking &amp; forcing for proc1</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>GPIO47_EDGE_HIGH</name>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO47_EDGE_LOW</name>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO47_LEVEL_HIGH</name>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO47_LEVEL_LOW</name>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO46_EDGE_HIGH</name>
+                        <bitRange>[27:27]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO46_EDGE_LOW</name>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO46_LEVEL_HIGH</name>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO46_LEVEL_LOW</name>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO45_EDGE_HIGH</name>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO45_EDGE_LOW</name>
+                        <bitRange>[22:22]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO45_LEVEL_HIGH</name>
+                        <bitRange>[21:21]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO45_LEVEL_LOW</name>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO44_EDGE_HIGH</name>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO44_EDGE_LOW</name>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO44_LEVEL_HIGH</name>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO44_LEVEL_LOW</name>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO43_EDGE_HIGH</name>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO43_EDGE_LOW</name>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO43_LEVEL_HIGH</name>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO43_LEVEL_LOW</name>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO42_EDGE_HIGH</name>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO42_EDGE_LOW</name>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO42_LEVEL_HIGH</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO42_LEVEL_LOW</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO41_EDGE_HIGH</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO41_EDGE_LOW</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO41_LEVEL_HIGH</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO41_LEVEL_LOW</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO40_EDGE_HIGH</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO40_EDGE_LOW</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO40_LEVEL_HIGH</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO40_LEVEL_LOW</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>DORMANT_WAKE_INTE0</name>
+                <addressOffset>0x000002d8</addressOffset>
+                <description>Interrupt Enable for dormant_wake</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>GPIO7_EDGE_HIGH</name>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO7_EDGE_LOW</name>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO7_LEVEL_HIGH</name>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO7_LEVEL_LOW</name>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO6_EDGE_HIGH</name>
+                        <bitRange>[27:27]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO6_EDGE_LOW</name>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO6_LEVEL_HIGH</name>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO6_LEVEL_LOW</name>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO5_EDGE_HIGH</name>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO5_EDGE_LOW</name>
+                        <bitRange>[22:22]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO5_LEVEL_HIGH</name>
+                        <bitRange>[21:21]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO5_LEVEL_LOW</name>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO4_EDGE_HIGH</name>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO4_EDGE_LOW</name>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO4_LEVEL_HIGH</name>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO4_LEVEL_LOW</name>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO3_EDGE_HIGH</name>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO3_EDGE_LOW</name>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO3_LEVEL_HIGH</name>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO3_LEVEL_LOW</name>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO2_EDGE_HIGH</name>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO2_EDGE_LOW</name>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO2_LEVEL_HIGH</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO2_LEVEL_LOW</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO1_EDGE_HIGH</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO1_EDGE_LOW</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO1_LEVEL_HIGH</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO1_LEVEL_LOW</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO0_EDGE_HIGH</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO0_EDGE_LOW</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO0_LEVEL_HIGH</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO0_LEVEL_LOW</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>DORMANT_WAKE_INTE1</name>
+                <addressOffset>0x000002dc</addressOffset>
+                <description>Interrupt Enable for dormant_wake</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>GPIO15_EDGE_HIGH</name>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO15_EDGE_LOW</name>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO15_LEVEL_HIGH</name>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO15_LEVEL_LOW</name>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO14_EDGE_HIGH</name>
+                        <bitRange>[27:27]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO14_EDGE_LOW</name>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO14_LEVEL_HIGH</name>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO14_LEVEL_LOW</name>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO13_EDGE_HIGH</name>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO13_EDGE_LOW</name>
+                        <bitRange>[22:22]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO13_LEVEL_HIGH</name>
+                        <bitRange>[21:21]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO13_LEVEL_LOW</name>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO12_EDGE_HIGH</name>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO12_EDGE_LOW</name>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO12_LEVEL_HIGH</name>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO12_LEVEL_LOW</name>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO11_EDGE_HIGH</name>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO11_EDGE_LOW</name>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO11_LEVEL_HIGH</name>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO11_LEVEL_LOW</name>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO10_EDGE_HIGH</name>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO10_EDGE_LOW</name>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO10_LEVEL_HIGH</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO10_LEVEL_LOW</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO9_EDGE_HIGH</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO9_EDGE_LOW</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO9_LEVEL_HIGH</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO9_LEVEL_LOW</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO8_EDGE_HIGH</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO8_EDGE_LOW</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO8_LEVEL_HIGH</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO8_LEVEL_LOW</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>DORMANT_WAKE_INTE2</name>
+                <addressOffset>0x000002e0</addressOffset>
+                <description>Interrupt Enable for dormant_wake</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>GPIO23_EDGE_HIGH</name>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO23_EDGE_LOW</name>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO23_LEVEL_HIGH</name>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO23_LEVEL_LOW</name>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO22_EDGE_HIGH</name>
+                        <bitRange>[27:27]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO22_EDGE_LOW</name>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO22_LEVEL_HIGH</name>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO22_LEVEL_LOW</name>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO21_EDGE_HIGH</name>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO21_EDGE_LOW</name>
+                        <bitRange>[22:22]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO21_LEVEL_HIGH</name>
+                        <bitRange>[21:21]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO21_LEVEL_LOW</name>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO20_EDGE_HIGH</name>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO20_EDGE_LOW</name>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO20_LEVEL_HIGH</name>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO20_LEVEL_LOW</name>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO19_EDGE_HIGH</name>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO19_EDGE_LOW</name>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO19_LEVEL_HIGH</name>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO19_LEVEL_LOW</name>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO18_EDGE_HIGH</name>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO18_EDGE_LOW</name>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO18_LEVEL_HIGH</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO18_LEVEL_LOW</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO17_EDGE_HIGH</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO17_EDGE_LOW</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO17_LEVEL_HIGH</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO17_LEVEL_LOW</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO16_EDGE_HIGH</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO16_EDGE_LOW</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO16_LEVEL_HIGH</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO16_LEVEL_LOW</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>DORMANT_WAKE_INTE3</name>
+                <addressOffset>0x000002e4</addressOffset>
+                <description>Interrupt Enable for dormant_wake</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>GPIO31_EDGE_HIGH</name>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO31_EDGE_LOW</name>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO31_LEVEL_HIGH</name>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO31_LEVEL_LOW</name>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO30_EDGE_HIGH</name>
+                        <bitRange>[27:27]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO30_EDGE_LOW</name>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO30_LEVEL_HIGH</name>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO30_LEVEL_LOW</name>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO29_EDGE_HIGH</name>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO29_EDGE_LOW</name>
+                        <bitRange>[22:22]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO29_LEVEL_HIGH</name>
+                        <bitRange>[21:21]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO29_LEVEL_LOW</name>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO28_EDGE_HIGH</name>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO28_EDGE_LOW</name>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO28_LEVEL_HIGH</name>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO28_LEVEL_LOW</name>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO27_EDGE_HIGH</name>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO27_EDGE_LOW</name>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO27_LEVEL_HIGH</name>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO27_LEVEL_LOW</name>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO26_EDGE_HIGH</name>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO26_EDGE_LOW</name>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO26_LEVEL_HIGH</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO26_LEVEL_LOW</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO25_EDGE_HIGH</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO25_EDGE_LOW</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO25_LEVEL_HIGH</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO25_LEVEL_LOW</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO24_EDGE_HIGH</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO24_EDGE_LOW</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO24_LEVEL_HIGH</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO24_LEVEL_LOW</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>DORMANT_WAKE_INTE4</name>
+                <addressOffset>0x000002e8</addressOffset>
+                <description>Interrupt Enable for dormant_wake</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>GPIO39_EDGE_HIGH</name>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO39_EDGE_LOW</name>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO39_LEVEL_HIGH</name>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO39_LEVEL_LOW</name>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO38_EDGE_HIGH</name>
+                        <bitRange>[27:27]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO38_EDGE_LOW</name>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO38_LEVEL_HIGH</name>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO38_LEVEL_LOW</name>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO37_EDGE_HIGH</name>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO37_EDGE_LOW</name>
+                        <bitRange>[22:22]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO37_LEVEL_HIGH</name>
+                        <bitRange>[21:21]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO37_LEVEL_LOW</name>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO36_EDGE_HIGH</name>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO36_EDGE_LOW</name>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO36_LEVEL_HIGH</name>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO36_LEVEL_LOW</name>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO35_EDGE_HIGH</name>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO35_EDGE_LOW</name>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO35_LEVEL_HIGH</name>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO35_LEVEL_LOW</name>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO34_EDGE_HIGH</name>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO34_EDGE_LOW</name>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO34_LEVEL_HIGH</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO34_LEVEL_LOW</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO33_EDGE_HIGH</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO33_EDGE_LOW</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO33_LEVEL_HIGH</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO33_LEVEL_LOW</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO32_EDGE_HIGH</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO32_EDGE_LOW</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO32_LEVEL_HIGH</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO32_LEVEL_LOW</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>DORMANT_WAKE_INTE5</name>
+                <addressOffset>0x000002ec</addressOffset>
+                <description>Interrupt Enable for dormant_wake</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>GPIO47_EDGE_HIGH</name>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO47_EDGE_LOW</name>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO47_LEVEL_HIGH</name>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO47_LEVEL_LOW</name>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO46_EDGE_HIGH</name>
+                        <bitRange>[27:27]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO46_EDGE_LOW</name>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO46_LEVEL_HIGH</name>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO46_LEVEL_LOW</name>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO45_EDGE_HIGH</name>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO45_EDGE_LOW</name>
+                        <bitRange>[22:22]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO45_LEVEL_HIGH</name>
+                        <bitRange>[21:21]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO45_LEVEL_LOW</name>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO44_EDGE_HIGH</name>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO44_EDGE_LOW</name>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO44_LEVEL_HIGH</name>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO44_LEVEL_LOW</name>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO43_EDGE_HIGH</name>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO43_EDGE_LOW</name>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO43_LEVEL_HIGH</name>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO43_LEVEL_LOW</name>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO42_EDGE_HIGH</name>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO42_EDGE_LOW</name>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO42_LEVEL_HIGH</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO42_LEVEL_LOW</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO41_EDGE_HIGH</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO41_EDGE_LOW</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO41_LEVEL_HIGH</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO41_LEVEL_LOW</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO40_EDGE_HIGH</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO40_EDGE_LOW</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO40_LEVEL_HIGH</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO40_LEVEL_LOW</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>DORMANT_WAKE_INTF0</name>
+                <addressOffset>0x000002f0</addressOffset>
+                <description>Interrupt Force for dormant_wake</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>GPIO7_EDGE_HIGH</name>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO7_EDGE_LOW</name>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO7_LEVEL_HIGH</name>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO7_LEVEL_LOW</name>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO6_EDGE_HIGH</name>
+                        <bitRange>[27:27]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO6_EDGE_LOW</name>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO6_LEVEL_HIGH</name>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO6_LEVEL_LOW</name>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO5_EDGE_HIGH</name>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO5_EDGE_LOW</name>
+                        <bitRange>[22:22]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO5_LEVEL_HIGH</name>
+                        <bitRange>[21:21]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO5_LEVEL_LOW</name>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO4_EDGE_HIGH</name>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO4_EDGE_LOW</name>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO4_LEVEL_HIGH</name>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO4_LEVEL_LOW</name>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO3_EDGE_HIGH</name>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO3_EDGE_LOW</name>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO3_LEVEL_HIGH</name>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO3_LEVEL_LOW</name>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO2_EDGE_HIGH</name>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO2_EDGE_LOW</name>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO2_LEVEL_HIGH</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO2_LEVEL_LOW</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO1_EDGE_HIGH</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO1_EDGE_LOW</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO1_LEVEL_HIGH</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO1_LEVEL_LOW</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO0_EDGE_HIGH</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO0_EDGE_LOW</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO0_LEVEL_HIGH</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO0_LEVEL_LOW</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>DORMANT_WAKE_INTF1</name>
+                <addressOffset>0x000002f4</addressOffset>
+                <description>Interrupt Force for dormant_wake</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>GPIO15_EDGE_HIGH</name>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO15_EDGE_LOW</name>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO15_LEVEL_HIGH</name>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO15_LEVEL_LOW</name>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO14_EDGE_HIGH</name>
+                        <bitRange>[27:27]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO14_EDGE_LOW</name>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO14_LEVEL_HIGH</name>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO14_LEVEL_LOW</name>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO13_EDGE_HIGH</name>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO13_EDGE_LOW</name>
+                        <bitRange>[22:22]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO13_LEVEL_HIGH</name>
+                        <bitRange>[21:21]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO13_LEVEL_LOW</name>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO12_EDGE_HIGH</name>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO12_EDGE_LOW</name>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO12_LEVEL_HIGH</name>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO12_LEVEL_LOW</name>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO11_EDGE_HIGH</name>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO11_EDGE_LOW</name>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO11_LEVEL_HIGH</name>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO11_LEVEL_LOW</name>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO10_EDGE_HIGH</name>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO10_EDGE_LOW</name>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO10_LEVEL_HIGH</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO10_LEVEL_LOW</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO9_EDGE_HIGH</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO9_EDGE_LOW</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO9_LEVEL_HIGH</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO9_LEVEL_LOW</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO8_EDGE_HIGH</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO8_EDGE_LOW</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO8_LEVEL_HIGH</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO8_LEVEL_LOW</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>DORMANT_WAKE_INTF2</name>
+                <addressOffset>0x000002f8</addressOffset>
+                <description>Interrupt Force for dormant_wake</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>GPIO23_EDGE_HIGH</name>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO23_EDGE_LOW</name>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO23_LEVEL_HIGH</name>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO23_LEVEL_LOW</name>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO22_EDGE_HIGH</name>
+                        <bitRange>[27:27]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO22_EDGE_LOW</name>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO22_LEVEL_HIGH</name>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO22_LEVEL_LOW</name>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO21_EDGE_HIGH</name>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO21_EDGE_LOW</name>
+                        <bitRange>[22:22]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO21_LEVEL_HIGH</name>
+                        <bitRange>[21:21]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO21_LEVEL_LOW</name>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO20_EDGE_HIGH</name>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO20_EDGE_LOW</name>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO20_LEVEL_HIGH</name>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO20_LEVEL_LOW</name>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO19_EDGE_HIGH</name>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO19_EDGE_LOW</name>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO19_LEVEL_HIGH</name>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO19_LEVEL_LOW</name>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO18_EDGE_HIGH</name>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO18_EDGE_LOW</name>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO18_LEVEL_HIGH</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO18_LEVEL_LOW</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO17_EDGE_HIGH</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO17_EDGE_LOW</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO17_LEVEL_HIGH</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO17_LEVEL_LOW</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO16_EDGE_HIGH</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO16_EDGE_LOW</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO16_LEVEL_HIGH</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO16_LEVEL_LOW</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>DORMANT_WAKE_INTF3</name>
+                <addressOffset>0x000002fc</addressOffset>
+                <description>Interrupt Force for dormant_wake</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>GPIO31_EDGE_HIGH</name>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO31_EDGE_LOW</name>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO31_LEVEL_HIGH</name>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO31_LEVEL_LOW</name>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO30_EDGE_HIGH</name>
+                        <bitRange>[27:27]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO30_EDGE_LOW</name>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO30_LEVEL_HIGH</name>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO30_LEVEL_LOW</name>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO29_EDGE_HIGH</name>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO29_EDGE_LOW</name>
+                        <bitRange>[22:22]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO29_LEVEL_HIGH</name>
+                        <bitRange>[21:21]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO29_LEVEL_LOW</name>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO28_EDGE_HIGH</name>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO28_EDGE_LOW</name>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO28_LEVEL_HIGH</name>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO28_LEVEL_LOW</name>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO27_EDGE_HIGH</name>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO27_EDGE_LOW</name>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO27_LEVEL_HIGH</name>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO27_LEVEL_LOW</name>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO26_EDGE_HIGH</name>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO26_EDGE_LOW</name>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO26_LEVEL_HIGH</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO26_LEVEL_LOW</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO25_EDGE_HIGH</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO25_EDGE_LOW</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO25_LEVEL_HIGH</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO25_LEVEL_LOW</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO24_EDGE_HIGH</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO24_EDGE_LOW</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO24_LEVEL_HIGH</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO24_LEVEL_LOW</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>DORMANT_WAKE_INTF4</name>
+                <addressOffset>0x00000300</addressOffset>
+                <description>Interrupt Force for dormant_wake</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>GPIO39_EDGE_HIGH</name>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO39_EDGE_LOW</name>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO39_LEVEL_HIGH</name>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO39_LEVEL_LOW</name>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO38_EDGE_HIGH</name>
+                        <bitRange>[27:27]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO38_EDGE_LOW</name>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO38_LEVEL_HIGH</name>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO38_LEVEL_LOW</name>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO37_EDGE_HIGH</name>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO37_EDGE_LOW</name>
+                        <bitRange>[22:22]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO37_LEVEL_HIGH</name>
+                        <bitRange>[21:21]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO37_LEVEL_LOW</name>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO36_EDGE_HIGH</name>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO36_EDGE_LOW</name>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO36_LEVEL_HIGH</name>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO36_LEVEL_LOW</name>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO35_EDGE_HIGH</name>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO35_EDGE_LOW</name>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO35_LEVEL_HIGH</name>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO35_LEVEL_LOW</name>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO34_EDGE_HIGH</name>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO34_EDGE_LOW</name>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO34_LEVEL_HIGH</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO34_LEVEL_LOW</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO33_EDGE_HIGH</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO33_EDGE_LOW</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO33_LEVEL_HIGH</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO33_LEVEL_LOW</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO32_EDGE_HIGH</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO32_EDGE_LOW</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO32_LEVEL_HIGH</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO32_LEVEL_LOW</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>DORMANT_WAKE_INTF5</name>
+                <addressOffset>0x00000304</addressOffset>
+                <description>Interrupt Force for dormant_wake</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>GPIO47_EDGE_HIGH</name>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO47_EDGE_LOW</name>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO47_LEVEL_HIGH</name>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO47_LEVEL_LOW</name>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO46_EDGE_HIGH</name>
+                        <bitRange>[27:27]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO46_EDGE_LOW</name>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO46_LEVEL_HIGH</name>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO46_LEVEL_LOW</name>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO45_EDGE_HIGH</name>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO45_EDGE_LOW</name>
+                        <bitRange>[22:22]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO45_LEVEL_HIGH</name>
+                        <bitRange>[21:21]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO45_LEVEL_LOW</name>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO44_EDGE_HIGH</name>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO44_EDGE_LOW</name>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO44_LEVEL_HIGH</name>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO44_LEVEL_LOW</name>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO43_EDGE_HIGH</name>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO43_EDGE_LOW</name>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO43_LEVEL_HIGH</name>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO43_LEVEL_LOW</name>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO42_EDGE_HIGH</name>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO42_EDGE_LOW</name>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO42_LEVEL_HIGH</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO42_LEVEL_LOW</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO41_EDGE_HIGH</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO41_EDGE_LOW</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO41_LEVEL_HIGH</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO41_LEVEL_LOW</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO40_EDGE_HIGH</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO40_EDGE_LOW</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO40_LEVEL_HIGH</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO40_LEVEL_LOW</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>DORMANT_WAKE_INTS0</name>
+                <addressOffset>0x00000308</addressOffset>
+                <description>Interrupt status after masking &amp; forcing for dormant_wake</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>GPIO7_EDGE_HIGH</name>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO7_EDGE_LOW</name>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO7_LEVEL_HIGH</name>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO7_LEVEL_LOW</name>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO6_EDGE_HIGH</name>
+                        <bitRange>[27:27]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO6_EDGE_LOW</name>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO6_LEVEL_HIGH</name>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO6_LEVEL_LOW</name>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO5_EDGE_HIGH</name>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO5_EDGE_LOW</name>
+                        <bitRange>[22:22]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO5_LEVEL_HIGH</name>
+                        <bitRange>[21:21]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO5_LEVEL_LOW</name>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO4_EDGE_HIGH</name>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO4_EDGE_LOW</name>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO4_LEVEL_HIGH</name>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO4_LEVEL_LOW</name>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO3_EDGE_HIGH</name>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO3_EDGE_LOW</name>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO3_LEVEL_HIGH</name>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO3_LEVEL_LOW</name>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO2_EDGE_HIGH</name>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO2_EDGE_LOW</name>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO2_LEVEL_HIGH</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO2_LEVEL_LOW</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO1_EDGE_HIGH</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO1_EDGE_LOW</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO1_LEVEL_HIGH</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO1_LEVEL_LOW</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO0_EDGE_HIGH</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO0_EDGE_LOW</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO0_LEVEL_HIGH</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO0_LEVEL_LOW</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>DORMANT_WAKE_INTS1</name>
+                <addressOffset>0x0000030c</addressOffset>
+                <description>Interrupt status after masking &amp; forcing for dormant_wake</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>GPIO15_EDGE_HIGH</name>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO15_EDGE_LOW</name>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO15_LEVEL_HIGH</name>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO15_LEVEL_LOW</name>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO14_EDGE_HIGH</name>
+                        <bitRange>[27:27]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO14_EDGE_LOW</name>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO14_LEVEL_HIGH</name>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO14_LEVEL_LOW</name>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO13_EDGE_HIGH</name>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO13_EDGE_LOW</name>
+                        <bitRange>[22:22]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO13_LEVEL_HIGH</name>
+                        <bitRange>[21:21]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO13_LEVEL_LOW</name>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO12_EDGE_HIGH</name>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO12_EDGE_LOW</name>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO12_LEVEL_HIGH</name>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO12_LEVEL_LOW</name>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO11_EDGE_HIGH</name>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO11_EDGE_LOW</name>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO11_LEVEL_HIGH</name>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO11_LEVEL_LOW</name>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO10_EDGE_HIGH</name>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO10_EDGE_LOW</name>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO10_LEVEL_HIGH</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO10_LEVEL_LOW</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO9_EDGE_HIGH</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO9_EDGE_LOW</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO9_LEVEL_HIGH</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO9_LEVEL_LOW</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO8_EDGE_HIGH</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO8_EDGE_LOW</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO8_LEVEL_HIGH</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO8_LEVEL_LOW</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>DORMANT_WAKE_INTS2</name>
+                <addressOffset>0x00000310</addressOffset>
+                <description>Interrupt status after masking &amp; forcing for dormant_wake</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>GPIO23_EDGE_HIGH</name>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO23_EDGE_LOW</name>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO23_LEVEL_HIGH</name>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO23_LEVEL_LOW</name>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO22_EDGE_HIGH</name>
+                        <bitRange>[27:27]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO22_EDGE_LOW</name>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO22_LEVEL_HIGH</name>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO22_LEVEL_LOW</name>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO21_EDGE_HIGH</name>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO21_EDGE_LOW</name>
+                        <bitRange>[22:22]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO21_LEVEL_HIGH</name>
+                        <bitRange>[21:21]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO21_LEVEL_LOW</name>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO20_EDGE_HIGH</name>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO20_EDGE_LOW</name>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO20_LEVEL_HIGH</name>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO20_LEVEL_LOW</name>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO19_EDGE_HIGH</name>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO19_EDGE_LOW</name>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO19_LEVEL_HIGH</name>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO19_LEVEL_LOW</name>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO18_EDGE_HIGH</name>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO18_EDGE_LOW</name>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO18_LEVEL_HIGH</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO18_LEVEL_LOW</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO17_EDGE_HIGH</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO17_EDGE_LOW</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO17_LEVEL_HIGH</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO17_LEVEL_LOW</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO16_EDGE_HIGH</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO16_EDGE_LOW</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO16_LEVEL_HIGH</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO16_LEVEL_LOW</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>DORMANT_WAKE_INTS3</name>
+                <addressOffset>0x00000314</addressOffset>
+                <description>Interrupt status after masking &amp; forcing for dormant_wake</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>GPIO31_EDGE_HIGH</name>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO31_EDGE_LOW</name>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO31_LEVEL_HIGH</name>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO31_LEVEL_LOW</name>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO30_EDGE_HIGH</name>
+                        <bitRange>[27:27]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO30_EDGE_LOW</name>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO30_LEVEL_HIGH</name>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO30_LEVEL_LOW</name>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO29_EDGE_HIGH</name>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO29_EDGE_LOW</name>
+                        <bitRange>[22:22]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO29_LEVEL_HIGH</name>
+                        <bitRange>[21:21]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO29_LEVEL_LOW</name>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO28_EDGE_HIGH</name>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO28_EDGE_LOW</name>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO28_LEVEL_HIGH</name>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO28_LEVEL_LOW</name>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO27_EDGE_HIGH</name>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO27_EDGE_LOW</name>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO27_LEVEL_HIGH</name>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO27_LEVEL_LOW</name>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO26_EDGE_HIGH</name>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO26_EDGE_LOW</name>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO26_LEVEL_HIGH</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO26_LEVEL_LOW</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO25_EDGE_HIGH</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO25_EDGE_LOW</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO25_LEVEL_HIGH</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO25_LEVEL_LOW</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO24_EDGE_HIGH</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO24_EDGE_LOW</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO24_LEVEL_HIGH</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO24_LEVEL_LOW</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>DORMANT_WAKE_INTS4</name>
+                <addressOffset>0x00000318</addressOffset>
+                <description>Interrupt status after masking &amp; forcing for dormant_wake</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>GPIO39_EDGE_HIGH</name>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO39_EDGE_LOW</name>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO39_LEVEL_HIGH</name>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO39_LEVEL_LOW</name>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO38_EDGE_HIGH</name>
+                        <bitRange>[27:27]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO38_EDGE_LOW</name>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO38_LEVEL_HIGH</name>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO38_LEVEL_LOW</name>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO37_EDGE_HIGH</name>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO37_EDGE_LOW</name>
+                        <bitRange>[22:22]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO37_LEVEL_HIGH</name>
+                        <bitRange>[21:21]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO37_LEVEL_LOW</name>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO36_EDGE_HIGH</name>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO36_EDGE_LOW</name>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO36_LEVEL_HIGH</name>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO36_LEVEL_LOW</name>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO35_EDGE_HIGH</name>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO35_EDGE_LOW</name>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO35_LEVEL_HIGH</name>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO35_LEVEL_LOW</name>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO34_EDGE_HIGH</name>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO34_EDGE_LOW</name>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO34_LEVEL_HIGH</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO34_LEVEL_LOW</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO33_EDGE_HIGH</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO33_EDGE_LOW</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO33_LEVEL_HIGH</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO33_LEVEL_LOW</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO32_EDGE_HIGH</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO32_EDGE_LOW</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO32_LEVEL_HIGH</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO32_LEVEL_LOW</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>DORMANT_WAKE_INTS5</name>
+                <addressOffset>0x0000031c</addressOffset>
+                <description>Interrupt status after masking &amp; forcing for dormant_wake</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>GPIO47_EDGE_HIGH</name>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO47_EDGE_LOW</name>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO47_LEVEL_HIGH</name>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO47_LEVEL_LOW</name>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO46_EDGE_HIGH</name>
+                        <bitRange>[27:27]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO46_EDGE_LOW</name>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO46_LEVEL_HIGH</name>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO46_LEVEL_LOW</name>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO45_EDGE_HIGH</name>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO45_EDGE_LOW</name>
+                        <bitRange>[22:22]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO45_LEVEL_HIGH</name>
+                        <bitRange>[21:21]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO45_LEVEL_LOW</name>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO44_EDGE_HIGH</name>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO44_EDGE_LOW</name>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO44_LEVEL_HIGH</name>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO44_LEVEL_LOW</name>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO43_EDGE_HIGH</name>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO43_EDGE_LOW</name>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO43_LEVEL_HIGH</name>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO43_LEVEL_LOW</name>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO42_EDGE_HIGH</name>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO42_EDGE_LOW</name>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO42_LEVEL_HIGH</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO42_LEVEL_LOW</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO41_EDGE_HIGH</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO41_EDGE_LOW</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO41_LEVEL_HIGH</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO41_LEVEL_LOW</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO40_EDGE_HIGH</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO40_EDGE_LOW</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO40_LEVEL_HIGH</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO40_LEVEL_LOW</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+        </registers>
+    </peripheral>
+    <peripheral>
+        <name>SYSINFO</name>
+        <baseAddress>0x40000000</baseAddress>
+        <addressBlock>
+            <offset>0</offset>
+            <size>24</size>
+            <usage>registers</usage>
+        </addressBlock>
+        <registers>
+            <register>
+                <name>CHIP_ID</name>
+                <addressOffset>0x00000000</addressOffset>
+                <description>JEDEC JEP-106 compliant chip identifier.</description>
+                <resetValue>0x00000001</resetValue>
+                <fields>
+                    <field>
+                        <name>REVISION</name>
+                        <bitRange>[31:28]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>PART</name>
+                        <bitRange>[27:12]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>MANUFACTURER</name>
+                        <bitRange>[11:1]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>STOP_BIT</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PACKAGE_SEL</name>
+                <addressOffset>0x00000004</addressOffset>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>PACKAGE_SEL</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PLATFORM</name>
+                <addressOffset>0x00000008</addressOffset>
+                <description>Platform register. Allows software to know what environment it is running in during pre-production development. Post-production, the PLATFORM is always ASIC, non-SIM.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>GATESIM</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>BATCHSIM</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>HDLSIM</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>ASIC</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>FPGA</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GITREF_RP2350</name>
+                <addressOffset>0x00000014</addressOffset>
+                <description>Git hash of the chip source. Used to identify chip version.</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>GITREF_RP2350</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+        </registers>
+    </peripheral>
+    <peripheral>
+        <name>SHA256</name>
+        <description>SHA-256 hash function implementation</description>
+        <baseAddress>0x400f8000</baseAddress>
+        <addressBlock>
+            <offset>0</offset>
+            <size>40</size>
+            <usage>registers</usage>
+        </addressBlock>
+        <registers>
+            <register>
+                <name>CSR</name>
+                <addressOffset>0x00000000</addressOffset>
+                <description>Control and status register</description>
+                <resetValue>0x00001206</resetValue>
+                <fields>
+                    <field>
+                        <name>BSWAP</name>
+                        <description>Enable byte swapping of 32-bit values at the point they are committed to the SHA message scheduler.
+
+                            This block&#39;s bus interface assembles byte/halfword data into message words in little-endian order, so that DMAing the same buffer with different transfer sizes always gives the same result on a little-endian system like RP2350.
+
+                            However, when marshalling bytes into blocks, SHA expects that the first byte is the *most significant* in each message word. To resolve this, once the bus interface has accumulated 32 bits of data (either a word write, two halfword writes in little-endian order, or four byte writes in little-endian order) the final value can be byte-swapped before passing to the actual SHA core.
+
+                            This feature is enabled by default because using the SHA core to checksum byte buffers is expected to be more common than having preformatted SHA message words lying around.</description>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DMA_SIZE</name>
+                        <description>Configure DREQ logic for the correct DMA data size. Must be configured before the DMA channel is triggered.
+
+                            The SHA-256 core&#39;s DREQ logic requests one entire block of data at once, since there is no FIFO, and data goes straight into the core&#39;s message schedule and digest hardware. Therefore, when transferring data with DMA, CSR_DMA_SIZE must be configured in advance so that the correct number of transfers can be requested per block.</description>
+                        <bitRange>[9:8]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>8bit</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>16bit</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>32bit</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>ERR_WDATA_NOT_RDY</name>
+                        <description>Set when a write occurs whilst the SHA-256 core is not ready for data (WDATA_RDY is low). Write one to clear.</description>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>SUM_VLD</name>
+                        <description>If 1, the SHA-256 checksum presented in registers SUM0 through SUM7 is currently valid.
+
+                            Goes low when WDATA is first written, then returns high once 16 words have been written and the digest of the current 512-bit block has subsequently completed.</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>WDATA_RDY</name>
+                        <description>If 1, the SHA-256 core is ready to accept more data through the WDATA register.
+
+                            After writing 16 words, this flag will go low for 57 cycles whilst the core completes its digest.</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>START</name>
+                        <description>Write 1 to prepare the SHA-256 core for a new checksum.
+
+                            The SUMx registers are initialised to the proper values (fractional bits of square roots of first 8 primes) and internal counters are cleared. This immediately forces WDATA_RDY and SUM_VLD high.
+
+                            START must be written before initiating a DMA transfer to the SHA-256 core, because the core will always request 16 transfers at a time (1 512-bit block). Additionally, the DMA channel should be configured for a multiple of 16 32-bit transfers.</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>WDATA</name>
+                <addressOffset>0x00000004</addressOffset>
+                <description>Write data register</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>WDATA</name>
+                        <description>After pulsing START and writing 16 words of data to this register, WDATA_RDY will go low and the SHA-256 core will complete the digest of the current 512-bit block.
+
+                            Software is responsible for ensuring the data is correctly padded and terminated to a whole number of 512-bit blocks.
+
+                            After this, WDATA_RDY will return high, and more data can be written (if any).
+
+                            This register supports word, halfword and byte writes, so that DMA from non-word-aligned buffers can be supported. The total amount of data per block remains the same (16 words, 32 halfwords or 64 bytes) and byte/halfword transfers must not be mixed within a block.</description>
+                        <bitRange>[31:0]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SUM0</name>
+                <addressOffset>0x00000008</addressOffset>
+                <description>256-bit checksum result. Contents are undefined when CSR_SUM_VLD is 0.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>SUM0</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SUM1</name>
+                <addressOffset>0x0000000c</addressOffset>
+                <description>256-bit checksum result. Contents are undefined when CSR_SUM_VLD is 0.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>SUM1</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SUM2</name>
+                <addressOffset>0x00000010</addressOffset>
+                <description>256-bit checksum result. Contents are undefined when CSR_SUM_VLD is 0.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>SUM2</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SUM3</name>
+                <addressOffset>0x00000014</addressOffset>
+                <description>256-bit checksum result. Contents are undefined when CSR_SUM_VLD is 0.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>SUM3</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SUM4</name>
+                <addressOffset>0x00000018</addressOffset>
+                <description>256-bit checksum result. Contents are undefined when CSR_SUM_VLD is 0.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>SUM4</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SUM5</name>
+                <addressOffset>0x0000001c</addressOffset>
+                <description>256-bit checksum result. Contents are undefined when CSR_SUM_VLD is 0.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>SUM5</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SUM6</name>
+                <addressOffset>0x00000020</addressOffset>
+                <description>256-bit checksum result. Contents are undefined when CSR_SUM_VLD is 0.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>SUM6</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SUM7</name>
+                <addressOffset>0x00000024</addressOffset>
+                <description>256-bit checksum result. Contents are undefined when CSR_SUM_VLD is 0.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>SUM7</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+        </registers>
+    </peripheral>
+    <peripheral>
+        <name>HSTX_FIFO</name>
+        <description>FIFO status and write access for HSTX</description>
+        <baseAddress>0x50600000</baseAddress>
+        <addressBlock>
+            <offset>0</offset>
+            <size>8</size>
+            <usage>registers</usage>
+        </addressBlock>
+        <registers>
+            <register>
+                <name>STAT</name>
+                <addressOffset>0x00000000</addressOffset>
+                <description>FIFO status</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>WOF</name>
+                        <description>FIFO was written when full. Write 1 to clear.</description>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EMPTY</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>FULL</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>LEVEL</name>
+                        <bitRange>[7:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>FIFO</name>
+                <addressOffset>0x00000004</addressOffset>
+                <description>Write access to FIFO</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>FIFO</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                </fields>
+            </register>
+        </registers>
+    </peripheral>
+    <peripheral>
+        <name>HSTX_CTRL</name>
+        <description>Control interface to HSTX. For FIFO write access and status, see the HSTX_FIFO register block.</description>
+        <baseAddress>0x400c0000</baseAddress>
+        <addressBlock>
+            <offset>0</offset>
+            <size>44</size>
+            <usage>registers</usage>
+        </addressBlock>
+        <registers>
+            <register>
+                <name>CSR</name>
+                <addressOffset>0x00000000</addressOffset>
+                <resetValue>0x10050600</resetValue>
+                <fields>
+                    <field>
+                        <name>CLKDIV</name>
+                        <description>Clock period of the generated clock, measured in HSTX clock cycles. Can be odd or even. The generated clock advances only on cycles where the shift register shifts.
+
+                            For example, a clkdiv of 5 would generate a complete output clock period for every 5 HSTX clocks (or every 10 half-clocks).
+
+                            A CLKDIV value of 0 is mapped to a period of 16 HSTX clock cycles.</description>
+                        <bitRange>[31:28]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLKPHASE</name>
+                        <description>Set the initial phase of the generated clock.
+
+                            A CLKPHASE of 0 means the clock is initially low, and the first rising edge occurs after one half period of the generated clock (i.e. CLKDIV/2 cycles of clk_hstx). Incrementing CLKPHASE by 1 will advance the initial clock phase by one half clk_hstx period. For example, if CLKDIV=2 and CLKPHASE=1:
+
+                            * The clock will be initially low
+
+                            * The first rising edge will be 0.5 clk_hstx cycles after asserting first data
+
+                            * The first falling edge will be 1.5 clk_hstx cycles after asserting first data
+
+                            This configuration would be suitable for serialising at a bit rate of clk_hstx with a centre-aligned DDR clock.
+
+                            When the HSTX is halted by clearing CSR_EN, the clock generator will return to its initial phase as configured by the CLKPHASE field.
+
+                            Note CLKPHASE must be strictly less than double the value of CLKDIV (one full period), else its operation is undefined.</description>
+                        <bitRange>[27:24]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>N_SHIFTS</name>
+                        <description>Number of times to shift the shift register before refilling it from the FIFO. (A count of how many times it has been shifted, *not* the total shift distance.)
+
+                            A register value of 0 means shift 32 times.</description>
+                        <bitRange>[20:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SHIFT</name>
+                        <description>How many bits to right-rotate the shift register by each cycle.
+
+                            The use of a rotate rather than a shift allows left shifts to be emulated, by subtracting the left-shift amount from 32. It also allows data to be repeated, when the product of SHIFT and N_SHIFTS is greater than 32.</description>
+                        <bitRange>[12:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>COUPLED_SEL</name>
+                        <description>Select which PIO to use for coupled mode operation.</description>
+                        <bitRange>[6:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>COUPLED_MODE</name>
+                        <description>Enable the PIO-to-HSTX 1:1 connection. The HSTX must be clocked *directly* from the system clock (not just from some other clock source of the same frequency) for this synchronous interface to function correctly.
+
+                            When COUPLED_MODE is set, BITx_SEL_P and SEL_N indices 24 through 31 will select bits from the 8-bit PIO-to-HSTX path, rather than shifter bits. Indices of 0 through 23 will still index the shift register as normal.
+
+                            The PIO outputs connected to the PIO-to-HSTX bus are those same outputs that would appear on the HSTX-capable pins if those pins&#39; FUNCSELs were set to PIO instead of HSTX.
+
+                            For example, if HSTX is on GPIOs 12 through 19, then PIO outputs 12 through 19 are connected to the HSTX when coupled mode is engaged.</description>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>EXPAND_EN</name>
+                        <description>Enable the command expander. When 0, raw FIFO data is passed directly to the output shift register. When 1, the command expander can perform simple operations such as run length decoding on data between the FIFO and the shift register.
+
+                            Do not change CXPD_EN whilst EN is set. It&#39;s safe to set CXPD_EN simultaneously with setting EN.</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>EN</name>
+                        <description>When EN is 1, the HSTX will shift out data as it appears in the FIFO. As long as there is data, the HSTX shift register will shift once per clock cycle, and the frequency of popping from the FIFO is determined by the ratio of SHIFT and SHIFT_THRESH.
+
+                            When EN is 0, the FIFO is not popped. The shift counter and clock generator are also reset to their initial state for as long as EN is low. Note the initial phase of the clock generator can be configured by the CLKPHASE field.
+
+                            Once the HSTX is enabled again, and data is pushed to the FIFO, the generated clock&#39;s first rising edge will be one half-period after the first data is launched.</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>BIT0</name>
+                <addressOffset>0x00000004</addressOffset>
+                <description>Data control register for output bit 0</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CLK</name>
+                        <description>Connect this output to the generated clock, rather than the data shift register. SEL_P and SEL_N are ignored if this bit is set, but INV can still be set to generate an antiphase clock.</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INV</name>
+                        <description>Invert this data output (logical NOT)</description>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SEL_N</name>
+                        <description>Shift register data bit select for the second half of the HSTX clock cycle</description>
+                        <bitRange>[12:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SEL_P</name>
+                        <description>Shift register data bit select for the first half of the HSTX clock cycle</description>
+                        <bitRange>[4:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>BIT1</name>
+                <addressOffset>0x00000008</addressOffset>
+                <description>Data control register for output bit 1</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CLK</name>
+                        <description>Connect this output to the generated clock, rather than the data shift register. SEL_P and SEL_N are ignored if this bit is set, but INV can still be set to generate an antiphase clock.</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INV</name>
+                        <description>Invert this data output (logical NOT)</description>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SEL_N</name>
+                        <description>Shift register data bit select for the second half of the HSTX clock cycle</description>
+                        <bitRange>[12:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SEL_P</name>
+                        <description>Shift register data bit select for the first half of the HSTX clock cycle</description>
+                        <bitRange>[4:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>BIT2</name>
+                <addressOffset>0x0000000c</addressOffset>
+                <description>Data control register for output bit 2</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CLK</name>
+                        <description>Connect this output to the generated clock, rather than the data shift register. SEL_P and SEL_N are ignored if this bit is set, but INV can still be set to generate an antiphase clock.</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INV</name>
+                        <description>Invert this data output (logical NOT)</description>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SEL_N</name>
+                        <description>Shift register data bit select for the second half of the HSTX clock cycle</description>
+                        <bitRange>[12:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SEL_P</name>
+                        <description>Shift register data bit select for the first half of the HSTX clock cycle</description>
+                        <bitRange>[4:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>BIT3</name>
+                <addressOffset>0x00000010</addressOffset>
+                <description>Data control register for output bit 3</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CLK</name>
+                        <description>Connect this output to the generated clock, rather than the data shift register. SEL_P and SEL_N are ignored if this bit is set, but INV can still be set to generate an antiphase clock.</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INV</name>
+                        <description>Invert this data output (logical NOT)</description>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SEL_N</name>
+                        <description>Shift register data bit select for the second half of the HSTX clock cycle</description>
+                        <bitRange>[12:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SEL_P</name>
+                        <description>Shift register data bit select for the first half of the HSTX clock cycle</description>
+                        <bitRange>[4:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>BIT4</name>
+                <addressOffset>0x00000014</addressOffset>
+                <description>Data control register for output bit 4</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CLK</name>
+                        <description>Connect this output to the generated clock, rather than the data shift register. SEL_P and SEL_N are ignored if this bit is set, but INV can still be set to generate an antiphase clock.</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INV</name>
+                        <description>Invert this data output (logical NOT)</description>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SEL_N</name>
+                        <description>Shift register data bit select for the second half of the HSTX clock cycle</description>
+                        <bitRange>[12:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SEL_P</name>
+                        <description>Shift register data bit select for the first half of the HSTX clock cycle</description>
+                        <bitRange>[4:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>BIT5</name>
+                <addressOffset>0x00000018</addressOffset>
+                <description>Data control register for output bit 5</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CLK</name>
+                        <description>Connect this output to the generated clock, rather than the data shift register. SEL_P and SEL_N are ignored if this bit is set, but INV can still be set to generate an antiphase clock.</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INV</name>
+                        <description>Invert this data output (logical NOT)</description>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SEL_N</name>
+                        <description>Shift register data bit select for the second half of the HSTX clock cycle</description>
+                        <bitRange>[12:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SEL_P</name>
+                        <description>Shift register data bit select for the first half of the HSTX clock cycle</description>
+                        <bitRange>[4:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>BIT6</name>
+                <addressOffset>0x0000001c</addressOffset>
+                <description>Data control register for output bit 6</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CLK</name>
+                        <description>Connect this output to the generated clock, rather than the data shift register. SEL_P and SEL_N are ignored if this bit is set, but INV can still be set to generate an antiphase clock.</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INV</name>
+                        <description>Invert this data output (logical NOT)</description>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SEL_N</name>
+                        <description>Shift register data bit select for the second half of the HSTX clock cycle</description>
+                        <bitRange>[12:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SEL_P</name>
+                        <description>Shift register data bit select for the first half of the HSTX clock cycle</description>
+                        <bitRange>[4:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>BIT7</name>
+                <addressOffset>0x00000020</addressOffset>
+                <description>Data control register for output bit 7</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CLK</name>
+                        <description>Connect this output to the generated clock, rather than the data shift register. SEL_P and SEL_N are ignored if this bit is set, but INV can still be set to generate an antiphase clock.</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INV</name>
+                        <description>Invert this data output (logical NOT)</description>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SEL_N</name>
+                        <description>Shift register data bit select for the second half of the HSTX clock cycle</description>
+                        <bitRange>[12:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SEL_P</name>
+                        <description>Shift register data bit select for the first half of the HSTX clock cycle</description>
+                        <bitRange>[4:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>EXPAND_SHIFT</name>
+                <addressOffset>0x00000024</addressOffset>
+                <description>Configure the optional shifter inside the command expander</description>
+                <resetValue>0x01000100</resetValue>
+                <fields>
+                    <field>
+                        <name>ENC_N_SHIFTS</name>
+                        <description>Number of times to consume from the shift register before refilling it from the FIFO, when the current command is an encoded data command (e.g. TMDS). A register value of 0 means shift 32 times.</description>
+                        <bitRange>[28:24]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ENC_SHIFT</name>
+                        <description>How many bits to right-rotate the shift register by each time data is pushed to the output shifter, when the current command is an encoded data command (e.g. TMDS).</description>
+                        <bitRange>[20:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>RAW_N_SHIFTS</name>
+                        <description>Number of times to consume from the shift register before refilling it from the FIFO, when the current command is a raw data command. A register value of 0 means shift 32 times.</description>
+                        <bitRange>[12:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>RAW_SHIFT</name>
+                        <description>How many bits to right-rotate the shift register by each time data is pushed to the output shifter, when the current command is a raw data command.</description>
+                        <bitRange>[4:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>EXPAND_TMDS</name>
+                <addressOffset>0x00000028</addressOffset>
+                <description>Configure the optional TMDS encoder inside the command expander</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>L2_NBITS</name>
+                        <description>Number of valid data bits for the lane 2 TMDS encoder, starting from bit 7 of the rotated data. Field values of 0 -&gt; 7 encode counts of 1 -&gt; 8 bits.</description>
+                        <bitRange>[23:21]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>L2_ROT</name>
+                        <description>Right-rotate applied to the current shifter data before the lane 2 TMDS encoder.</description>
+                        <bitRange>[20:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>L1_NBITS</name>
+                        <description>Number of valid data bits for the lane 1 TMDS encoder, starting from bit 7 of the rotated data. Field values of 0 -&gt; 7 encode counts of 1 -&gt; 8 bits.</description>
+                        <bitRange>[15:13]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>L1_ROT</name>
+                        <description>Right-rotate applied to the current shifter data before the lane 1 TMDS encoder.</description>
+                        <bitRange>[12:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>L0_NBITS</name>
+                        <description>Number of valid data bits for the lane 0 TMDS encoder, starting from bit 7 of the rotated data. Field values of 0 -&gt; 7 encode counts of 1 -&gt; 8 bits.</description>
+                        <bitRange>[7:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>L0_ROT</name>
+                        <description>Right-rotate applied to the current shifter data before the lane 0 TMDS encoder.</description>
+                        <bitRange>[4:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+        </registers>
+    </peripheral>
+    <peripheral>
+        <name>EPPB</name>
+        <description>Cortex-M33 EPPB vendor register block for RP2350</description>
+        <baseAddress>0xe0080000</baseAddress>
+        <addressBlock>
+            <offset>0</offset>
+            <size>12</size>
+            <usage>registers</usage>
+        </addressBlock>
+        <registers>
+            <register>
+                <name>NMI_MASK0</name>
+                <addressOffset>0x00000000</addressOffset>
+                <description>NMI mask for IRQs 0 through 31. This register is core-local, and is reset by a processor warm reset.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>NMI_MASK0</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>NMI_MASK1</name>
+                <addressOffset>0x00000004</addressOffset>
+                <description>NMI mask for IRQs 0 though 51. This register is core-local, and is reset by a processor warm reset.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>NMI_MASK1</name>
+                        <bitRange>[19:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SLEEPCTRL</name>
+                <addressOffset>0x00000008</addressOffset>
+                <description>Nonstandard sleep control register</description>
+                <resetValue>0x00000002</resetValue>
+                <fields>
+                    <field>
+                        <name>WICENACK</name>
+                        <description>Status signal from the processor&#39;s interrupt controller. Changes to WICENREQ are eventually reflected in WICENACK.</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>WICENREQ</name>
+                        <description>Request that the next processor deep sleep is a WIC sleep. After setting this bit, before sleeping, poll WICENACK to ensure the processor interrupt controller has acknowledged the change.</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LIGHT_SLEEP</name>
+                        <description>By default, any processor sleep will deassert the system-level clock request. Reenabling the clocks incurs 5 cycles of additional latency on wakeup.
+
+                            Setting LIGHT_SLEEP to 1 keeps the clock request asserted during a normal sleep (Arm SCR.SLEEPDEEP = 0), for faster wakeup. Processor deep sleep (Arm SCR.SLEEPDEEP = 1) is not affected, and will always deassert the system-level clock request.</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+        </registers>
+    </peripheral>
+    <peripheral>
+        <name>PPB</name>
+        <description>TEAL registers accessible through the debug interface</description>
+        <baseAddress>0xe0000000</baseAddress>
+        <addressBlock>
+            <offset>0</offset>
+            <size>274432</size>
+            <usage>registers</usage>
+        </addressBlock>
+        <registers>
+            <register>
+                <name>ITM_STIM0</name>
+                <addressOffset>0x00000000</addressOffset>
+                <description>Provides the interface for generating Instrumentation packets</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>STIMULUS</name>
+                        <description>Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated.</description>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>ITM_STIM1</name>
+                <addressOffset>0x00000004</addressOffset>
+                <description>Provides the interface for generating Instrumentation packets</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>STIMULUS</name>
+                        <description>Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated.</description>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>ITM_STIM2</name>
+                <addressOffset>0x00000008</addressOffset>
+                <description>Provides the interface for generating Instrumentation packets</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>STIMULUS</name>
+                        <description>Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated.</description>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>ITM_STIM3</name>
+                <addressOffset>0x0000000c</addressOffset>
+                <description>Provides the interface for generating Instrumentation packets</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>STIMULUS</name>
+                        <description>Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated.</description>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>ITM_STIM4</name>
+                <addressOffset>0x00000010</addressOffset>
+                <description>Provides the interface for generating Instrumentation packets</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>STIMULUS</name>
+                        <description>Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated.</description>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>ITM_STIM5</name>
+                <addressOffset>0x00000014</addressOffset>
+                <description>Provides the interface for generating Instrumentation packets</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>STIMULUS</name>
+                        <description>Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated.</description>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>ITM_STIM6</name>
+                <addressOffset>0x00000018</addressOffset>
+                <description>Provides the interface for generating Instrumentation packets</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>STIMULUS</name>
+                        <description>Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated.</description>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>ITM_STIM7</name>
+                <addressOffset>0x0000001c</addressOffset>
+                <description>Provides the interface for generating Instrumentation packets</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>STIMULUS</name>
+                        <description>Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated.</description>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>ITM_STIM8</name>
+                <addressOffset>0x00000020</addressOffset>
+                <description>Provides the interface for generating Instrumentation packets</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>STIMULUS</name>
+                        <description>Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated.</description>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>ITM_STIM9</name>
+                <addressOffset>0x00000024</addressOffset>
+                <description>Provides the interface for generating Instrumentation packets</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>STIMULUS</name>
+                        <description>Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated.</description>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>ITM_STIM10</name>
+                <addressOffset>0x00000028</addressOffset>
+                <description>Provides the interface for generating Instrumentation packets</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>STIMULUS</name>
+                        <description>Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated.</description>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>ITM_STIM11</name>
+                <addressOffset>0x0000002c</addressOffset>
+                <description>Provides the interface for generating Instrumentation packets</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>STIMULUS</name>
+                        <description>Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated.</description>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>ITM_STIM12</name>
+                <addressOffset>0x00000030</addressOffset>
+                <description>Provides the interface for generating Instrumentation packets</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>STIMULUS</name>
+                        <description>Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated.</description>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>ITM_STIM13</name>
+                <addressOffset>0x00000034</addressOffset>
+                <description>Provides the interface for generating Instrumentation packets</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>STIMULUS</name>
+                        <description>Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated.</description>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>ITM_STIM14</name>
+                <addressOffset>0x00000038</addressOffset>
+                <description>Provides the interface for generating Instrumentation packets</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>STIMULUS</name>
+                        <description>Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated.</description>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>ITM_STIM15</name>
+                <addressOffset>0x0000003c</addressOffset>
+                <description>Provides the interface for generating Instrumentation packets</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>STIMULUS</name>
+                        <description>Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated.</description>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>ITM_STIM16</name>
+                <addressOffset>0x00000040</addressOffset>
+                <description>Provides the interface for generating Instrumentation packets</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>STIMULUS</name>
+                        <description>Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated.</description>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>ITM_STIM17</name>
+                <addressOffset>0x00000044</addressOffset>
+                <description>Provides the interface for generating Instrumentation packets</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>STIMULUS</name>
+                        <description>Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated.</description>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>ITM_STIM18</name>
+                <addressOffset>0x00000048</addressOffset>
+                <description>Provides the interface for generating Instrumentation packets</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>STIMULUS</name>
+                        <description>Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated.</description>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>ITM_STIM19</name>
+                <addressOffset>0x0000004c</addressOffset>
+                <description>Provides the interface for generating Instrumentation packets</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>STIMULUS</name>
+                        <description>Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated.</description>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>ITM_STIM20</name>
+                <addressOffset>0x00000050</addressOffset>
+                <description>Provides the interface for generating Instrumentation packets</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>STIMULUS</name>
+                        <description>Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated.</description>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>ITM_STIM21</name>
+                <addressOffset>0x00000054</addressOffset>
+                <description>Provides the interface for generating Instrumentation packets</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>STIMULUS</name>
+                        <description>Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated.</description>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>ITM_STIM22</name>
+                <addressOffset>0x00000058</addressOffset>
+                <description>Provides the interface for generating Instrumentation packets</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>STIMULUS</name>
+                        <description>Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated.</description>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>ITM_STIM23</name>
+                <addressOffset>0x0000005c</addressOffset>
+                <description>Provides the interface for generating Instrumentation packets</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>STIMULUS</name>
+                        <description>Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated.</description>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>ITM_STIM24</name>
+                <addressOffset>0x00000060</addressOffset>
+                <description>Provides the interface for generating Instrumentation packets</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>STIMULUS</name>
+                        <description>Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated.</description>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>ITM_STIM25</name>
+                <addressOffset>0x00000064</addressOffset>
+                <description>Provides the interface for generating Instrumentation packets</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>STIMULUS</name>
+                        <description>Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated.</description>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>ITM_STIM26</name>
+                <addressOffset>0x00000068</addressOffset>
+                <description>Provides the interface for generating Instrumentation packets</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>STIMULUS</name>
+                        <description>Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated.</description>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>ITM_STIM27</name>
+                <addressOffset>0x0000006c</addressOffset>
+                <description>Provides the interface for generating Instrumentation packets</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>STIMULUS</name>
+                        <description>Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated.</description>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>ITM_STIM28</name>
+                <addressOffset>0x00000070</addressOffset>
+                <description>Provides the interface for generating Instrumentation packets</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>STIMULUS</name>
+                        <description>Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated.</description>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>ITM_STIM29</name>
+                <addressOffset>0x00000074</addressOffset>
+                <description>Provides the interface for generating Instrumentation packets</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>STIMULUS</name>
+                        <description>Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated.</description>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>ITM_STIM30</name>
+                <addressOffset>0x00000078</addressOffset>
+                <description>Provides the interface for generating Instrumentation packets</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>STIMULUS</name>
+                        <description>Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated.</description>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>ITM_STIM31</name>
+                <addressOffset>0x0000007c</addressOffset>
+                <description>Provides the interface for generating Instrumentation packets</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>STIMULUS</name>
+                        <description>Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated.</description>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>ITM_TER0</name>
+                <addressOffset>0x00000e00</addressOffset>
+                <description>Provide an individual enable bit for each ITM_STIM register</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>STIMENA</name>
+                        <description>For STIMENA[m] in ITM_TER*n, controls whether ITM_STIM(32*n + m) is enabled</description>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>ITM_TPR</name>
+                <addressOffset>0x00000e40</addressOffset>
+                <description>Controls which stimulus ports can be accessed by unprivileged code</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>PRIVMASK</name>
+                        <description>Bit mask to enable tracing on ITM stimulus ports</description>
+                        <bitRange>[3:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>ITM_TCR</name>
+                <addressOffset>0x00000e80</addressOffset>
+                <description>Configures and controls transfers through the ITM interface</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>BUSY</name>
+                        <description>Indicates whether the ITM is currently processing events</description>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>TRACEBUSID</name>
+                        <description>Identifier for multi-source trace stream formatting. If multi-source trace is in use, the debugger must write a unique non-zero trace ID value to this field</description>
+                        <bitRange>[22:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GTSFREQ</name>
+                        <description>Defines how often the ITM generates a global timestamp, based on the global timestamp clock frequency, or disables generation of global timestamps</description>
+                        <bitRange>[11:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>TSPRESCALE</name>
+                        <description>Local timestamp prescaler, used with the trace packet reference clock</description>
+                        <bitRange>[9:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>STALLENA</name>
+                        <description>Stall the PE to guarantee delivery of Data Trace packets.</description>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SWOENA</name>
+                        <description>Enables asynchronous clocking of the timestamp counter</description>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>TXENA</name>
+                        <description>Enables forwarding of hardware event packet from the DWT unit to the ITM for output to the TPIU</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SYNCENA</name>
+                        <description>Enables Synchronization packet transmission for a synchronous TPIU</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>TSENA</name>
+                        <description>Enables Local timestamp generation</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ITMENA</name>
+                        <description>Enables the ITM</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INT_ATREADY</name>
+                <addressOffset>0x00000ef0</addressOffset>
+                <description>Integration Mode: Read ATB Ready</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>AFVALID</name>
+                        <description>A read of this bit returns the value of AFVALID</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>ATREADY</name>
+                        <description>A read of this bit returns the value of ATREADY</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INT_ATVALID</name>
+                <addressOffset>0x00000ef8</addressOffset>
+                <description>Integration Mode: Write ATB Valid</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>AFREADY</name>
+                        <description>A write to this bit gives the value of AFREADY</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ATREADY</name>
+                        <description>A write to this bit gives the value of ATVALID</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>ITM_ITCTRL</name>
+                <addressOffset>0x00000f00</addressOffset>
+                <description>Integration Mode Control Register</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>IME</name>
+                        <description>Integration mode enable bit - The possible values are:  0 - The trace unit is not in integration mode. 1 - The trace unit is in integration mode. This mode enables: A debug agent to perform topology detection. SoC test software to perform integration testing.</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>ITM_DEVARCH</name>
+                <addressOffset>0x00000fbc</addressOffset>
+                <description>Provides CoreSight discovery information for the ITM</description>
+                <resetValue>0x47701a01</resetValue>
+                <fields>
+                    <field>
+                        <name>ARCHITECT</name>
+                        <description>Defines the architect of the component. Bits [31:28] are the JEP106 continuation code (JEP106 bank ID, minus 1) and bits [27:21] are the JEP106 ID code.</description>
+                        <bitRange>[31:21]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>PRESENT</name>
+                        <description>Defines that the DEVARCH register is present</description>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>REVISION</name>
+                        <description>Defines the architecture revision of the component</description>
+                        <bitRange>[19:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>ARCHVER</name>
+                        <description>Defines the architecture version of the component</description>
+                        <bitRange>[15:12]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>ARCHPART</name>
+                        <description>Defines the architecture of the component</description>
+                        <bitRange>[11:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>ITM_DEVTYPE</name>
+                <addressOffset>0x00000fcc</addressOffset>
+                <description>Provides CoreSight discovery information for the ITM</description>
+                <resetValue>0x00000043</resetValue>
+                <fields>
+                    <field>
+                        <name>SUB</name>
+                        <description>Component sub-type</description>
+                        <bitRange>[7:4]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>MAJOR</name>
+                        <description>Component major type</description>
+                        <bitRange>[3:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>ITM_PIDR4</name>
+                <addressOffset>0x00000fd0</addressOffset>
+                <description>Provides CoreSight discovery information for the ITM</description>
+                <resetValue>0x00000004</resetValue>
+                <fields>
+                    <field>
+                        <name>SIZE</name>
+                        <description>See CoreSight Architecture Specification</description>
+                        <bitRange>[7:4]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>DES_2</name>
+                        <description>See CoreSight Architecture Specification</description>
+                        <bitRange>[3:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>ITM_PIDR5</name>
+                <addressOffset>0x00000fd4</addressOffset>
+                <description>Provides CoreSight discovery information for the ITM</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>ITM_PIDR5</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>ITM_PIDR6</name>
+                <addressOffset>0x00000fd8</addressOffset>
+                <description>Provides CoreSight discovery information for the ITM</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>ITM_PIDR6</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>ITM_PIDR7</name>
+                <addressOffset>0x00000fdc</addressOffset>
+                <description>Provides CoreSight discovery information for the ITM</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>ITM_PIDR7</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>ITM_PIDR0</name>
+                <addressOffset>0x00000fe0</addressOffset>
+                <description>Provides CoreSight discovery information for the ITM</description>
+                <resetValue>0x00000021</resetValue>
+                <fields>
+                    <field>
+                        <name>PART_0</name>
+                        <description>See CoreSight Architecture Specification</description>
+                        <bitRange>[7:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>ITM_PIDR1</name>
+                <addressOffset>0x00000fe4</addressOffset>
+                <description>Provides CoreSight discovery information for the ITM</description>
+                <resetValue>0x000000bd</resetValue>
+                <fields>
+                    <field>
+                        <name>DES_0</name>
+                        <description>See CoreSight Architecture Specification</description>
+                        <bitRange>[7:4]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>PART_1</name>
+                        <description>See CoreSight Architecture Specification</description>
+                        <bitRange>[3:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>ITM_PIDR2</name>
+                <addressOffset>0x00000fe8</addressOffset>
+                <description>Provides CoreSight discovery information for the ITM</description>
+                <resetValue>0x0000000b</resetValue>
+                <fields>
+                    <field>
+                        <name>REVISION</name>
+                        <description>See CoreSight Architecture Specification</description>
+                        <bitRange>[7:4]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>JEDEC</name>
+                        <description>See CoreSight Architecture Specification</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>DES_1</name>
+                        <description>See CoreSight Architecture Specification</description>
+                        <bitRange>[2:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>ITM_PIDR3</name>
+                <addressOffset>0x00000fec</addressOffset>
+                <description>Provides CoreSight discovery information for the ITM</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>REVAND</name>
+                        <description>See CoreSight Architecture Specification</description>
+                        <bitRange>[7:4]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CMOD</name>
+                        <description>See CoreSight Architecture Specification</description>
+                        <bitRange>[3:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>ITM_CIDR0</name>
+                <addressOffset>0x00000ff0</addressOffset>
+                <description>Provides CoreSight discovery information for the ITM</description>
+                <resetValue>0x0000000d</resetValue>
+                <fields>
+                    <field>
+                        <name>PRMBL_0</name>
+                        <description>See CoreSight Architecture Specification</description>
+                        <bitRange>[7:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>ITM_CIDR1</name>
+                <addressOffset>0x00000ff4</addressOffset>
+                <description>Provides CoreSight discovery information for the ITM</description>
+                <resetValue>0x00000090</resetValue>
+                <fields>
+                    <field>
+                        <name>CLASS</name>
+                        <description>See CoreSight Architecture Specification</description>
+                        <bitRange>[7:4]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>PRMBL_1</name>
+                        <description>See CoreSight Architecture Specification</description>
+                        <bitRange>[3:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>ITM_CIDR2</name>
+                <addressOffset>0x00000ff8</addressOffset>
+                <description>Provides CoreSight discovery information for the ITM</description>
+                <resetValue>0x00000005</resetValue>
+                <fields>
+                    <field>
+                        <name>PRMBL_2</name>
+                        <description>See CoreSight Architecture Specification</description>
+                        <bitRange>[7:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>ITM_CIDR3</name>
+                <addressOffset>0x00000ffc</addressOffset>
+                <description>Provides CoreSight discovery information for the ITM</description>
+                <resetValue>0x000000b1</resetValue>
+                <fields>
+                    <field>
+                        <name>PRMBL_3</name>
+                        <description>See CoreSight Architecture Specification</description>
+                        <bitRange>[7:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>DWT_CTRL</name>
+                <addressOffset>0x00001000</addressOffset>
+                <description>Provides configuration and status information for the DWT unit, and used to control features of the unit</description>
+                <resetValue>0x73741824</resetValue>
+                <fields>
+                    <field>
+                        <name>NUMCOMP</name>
+                        <description>Number of DWT comparators implemented</description>
+                        <bitRange>[31:28]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>NOTRCPKT</name>
+                        <description>Indicates whether the implementation does not support trace</description>
+                        <bitRange>[27:27]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>NOEXTTRIG</name>
+                        <description>Reserved, RAZ</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>NOCYCCNT</name>
+                        <description>Indicates whether the implementation does not include a cycle counter</description>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>NOPRFCNT</name>
+                        <description>Indicates whether the implementation does not include the profiling counters</description>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CYCDISS</name>
+                        <description>Controls whether the cycle counter is disabled in Secure state</description>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CYCEVTENA</name>
+                        <description>Enables Event Counter packet generation on POSTCNT underflow</description>
+                        <bitRange>[22:22]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>FOLDEVTENA</name>
+                        <description>Enables DWT_FOLDCNT counter</description>
+                        <bitRange>[21:21]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LSUEVTENA</name>
+                        <description>Enables DWT_LSUCNT counter</description>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SLEEPEVTENA</name>
+                        <description>Enable DWT_SLEEPCNT counter</description>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>EXCEVTENA</name>
+                        <description>Enables DWT_EXCCNT counter</description>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CPIEVTENA</name>
+                        <description>Enables DWT_CPICNT counter</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>EXTTRCENA</name>
+                        <description>Enables generation of Exception Trace packets</description>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PCSAMPLENA</name>
+                        <description>Enables use of POSTCNT counter as a timer for Periodic PC Sample packet generation</description>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SYNCTAP</name>
+                        <description>Selects the position of the synchronization packet counter tap on the CYCCNT counter. This determines the Synchronization packet rate</description>
+                        <bitRange>[11:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CYCTAP</name>
+                        <description>Selects the position of the POSTCNT tap on the CYCCNT counter</description>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>POSTINIT</name>
+                        <description>Initial value for the POSTCNT counter</description>
+                        <bitRange>[8:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>POSTPRESET</name>
+                        <description>Reload value for the POSTCNT counter</description>
+                        <bitRange>[4:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CYCCNTENA</name>
+                        <description>Enables CYCCNT</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>DWT_CYCCNT</name>
+                <addressOffset>0x00001004</addressOffset>
+                <description>Shows or sets the value of the processor cycle counter, CYCCNT</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CYCCNT</name>
+                        <description>Increments one on each processor clock cycle when DWT_CTRL.CYCCNTENA == 1 and DEMCR.TRCENA == 1. On overflow, CYCCNT wraps to zero</description>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>DWT_EXCCNT</name>
+                <addressOffset>0x0000100c</addressOffset>
+                <description>Counts the total cycles spent in exception processing</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>EXCCNT</name>
+                        <description>Counts one on each cycle when all of the following are true: - DWT_CTRL.EXCEVTENA == 1 and DEMCR.TRCENA == 1. - No instruction is executed, see DWT_CPICNT. - An exception-entry or exception-exit related operation is in progress. - Either SecureNoninvasiveDebugAllowed() == TRUE, or NS-Req for the operation is set to Non-secure and NoninvasiveDebugAllowed() == TRUE.</description>
+                        <bitRange>[7:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>DWT_LSUCNT</name>
+                <addressOffset>0x00001014</addressOffset>
+                <description>Increments on the additional cycles required to execute all load or store instructions</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>LSUCNT</name>
+                        <description>Counts one on each cycle when all of the following are true: - DWT_CTRL.LSUEVTENA == 1 and DEMCR.TRCENA == 1. - No instruction is executed, see DWT_CPICNT. - No exception-entry or exception-exit operation is in progress, see DWT_EXCCNT. - A load-store operation is in progress. - Either SecureNoninvasiveDebugAllowed() == TRUE, or NS-Req for the operation is set to Non-secure and NoninvasiveDebugAllowed() == TRUE.</description>
+                        <bitRange>[7:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>DWT_FOLDCNT</name>
+                <addressOffset>0x00001018</addressOffset>
+                <description>Increments on the additional cycles required to execute all load or store instructions</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>FOLDCNT</name>
+                        <description>Counts on each cycle when all of the following are true: - DWT_CTRL.FOLDEVTENA == 1 and DEMCR.TRCENA == 1. - At least two instructions are executed, see DWT_CPICNT. - Either SecureNoninvasiveDebugAllowed() == TRUE, or the PE is in Non-secure state and NoninvasiveDebugAllowed() == TRUE. The counter is incremented by the number of instructions executed, minus one</description>
+                        <bitRange>[7:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>DWT_COMP0</name>
+                <addressOffset>0x00001020</addressOffset>
+                <description>Provides a reference value for use by watchpoint comparator 0</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>DWT_COMP0</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>DWT_FUNCTION0</name>
+                <addressOffset>0x00001028</addressOffset>
+                <description>Controls the operation of watchpoint comparator 0</description>
+                <resetValue>0x58000000</resetValue>
+                <fields>
+                    <field>
+                        <name>ID</name>
+                        <description>Identifies the capabilities for MATCH for comparator *n</description>
+                        <bitRange>[31:27]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>MATCHED</name>
+                        <description>Set to 1 when the comparator matches</description>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>DATAVSIZE</name>
+                        <description>Defines the size of the object being watched for by Data Value and Data Address comparators</description>
+                        <bitRange>[11:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ACTION</name>
+                        <description>Defines the action on a match. This field is ignored and the comparator generates no actions if it is disabled by MATCH</description>
+                        <bitRange>[5:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>MATCH</name>
+                        <description>Controls the type of match generated by this comparator</description>
+                        <bitRange>[3:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>DWT_COMP1</name>
+                <addressOffset>0x00001030</addressOffset>
+                <description>Provides a reference value for use by watchpoint comparator 1</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>DWT_COMP1</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>DWT_FUNCTION1</name>
+                <addressOffset>0x00001038</addressOffset>
+                <description>Controls the operation of watchpoint comparator 1</description>
+                <resetValue>0x89000828</resetValue>
+                <fields>
+                    <field>
+                        <name>ID</name>
+                        <description>Identifies the capabilities for MATCH for comparator *n</description>
+                        <bitRange>[31:27]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>MATCHED</name>
+                        <description>Set to 1 when the comparator matches</description>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>DATAVSIZE</name>
+                        <description>Defines the size of the object being watched for by Data Value and Data Address comparators</description>
+                        <bitRange>[11:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ACTION</name>
+                        <description>Defines the action on a match. This field is ignored and the comparator generates no actions if it is disabled by MATCH</description>
+                        <bitRange>[5:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>MATCH</name>
+                        <description>Controls the type of match generated by this comparator</description>
+                        <bitRange>[3:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>DWT_COMP2</name>
+                <addressOffset>0x00001040</addressOffset>
+                <description>Provides a reference value for use by watchpoint comparator 2</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>DWT_COMP2</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>DWT_FUNCTION2</name>
+                <addressOffset>0x00001048</addressOffset>
+                <description>Controls the operation of watchpoint comparator 2</description>
+                <resetValue>0x50000000</resetValue>
+                <fields>
+                    <field>
+                        <name>ID</name>
+                        <description>Identifies the capabilities for MATCH for comparator *n</description>
+                        <bitRange>[31:27]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>MATCHED</name>
+                        <description>Set to 1 when the comparator matches</description>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>DATAVSIZE</name>
+                        <description>Defines the size of the object being watched for by Data Value and Data Address comparators</description>
+                        <bitRange>[11:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ACTION</name>
+                        <description>Defines the action on a match. This field is ignored and the comparator generates no actions if it is disabled by MATCH</description>
+                        <bitRange>[5:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>MATCH</name>
+                        <description>Controls the type of match generated by this comparator</description>
+                        <bitRange>[3:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>DWT_COMP3</name>
+                <addressOffset>0x00001050</addressOffset>
+                <description>Provides a reference value for use by watchpoint comparator 3</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>DWT_COMP3</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>DWT_FUNCTION3</name>
+                <addressOffset>0x00001058</addressOffset>
+                <description>Controls the operation of watchpoint comparator 3</description>
+                <resetValue>0x20000800</resetValue>
+                <fields>
+                    <field>
+                        <name>ID</name>
+                        <description>Identifies the capabilities for MATCH for comparator *n</description>
+                        <bitRange>[31:27]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>MATCHED</name>
+                        <description>Set to 1 when the comparator matches</description>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>DATAVSIZE</name>
+                        <description>Defines the size of the object being watched for by Data Value and Data Address comparators</description>
+                        <bitRange>[11:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ACTION</name>
+                        <description>Defines the action on a match. This field is ignored and the comparator generates no actions if it is disabled by MATCH</description>
+                        <bitRange>[5:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>MATCH</name>
+                        <description>Controls the type of match generated by this comparator</description>
+                        <bitRange>[3:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>DWT_DEVARCH</name>
+                <addressOffset>0x00001fbc</addressOffset>
+                <description>Provides CoreSight discovery information for the DWT</description>
+                <resetValue>0x47701a02</resetValue>
+                <fields>
+                    <field>
+                        <name>ARCHITECT</name>
+                        <description>Defines the architect of the component. Bits [31:28] are the JEP106 continuation code (JEP106 bank ID, minus 1) and bits [27:21] are the JEP106 ID code.</description>
+                        <bitRange>[31:21]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>PRESENT</name>
+                        <description>Defines that the DEVARCH register is present</description>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>REVISION</name>
+                        <description>Defines the architecture revision of the component</description>
+                        <bitRange>[19:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>ARCHVER</name>
+                        <description>Defines the architecture version of the component</description>
+                        <bitRange>[15:12]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>ARCHPART</name>
+                        <description>Defines the architecture of the component</description>
+                        <bitRange>[11:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>DWT_DEVTYPE</name>
+                <addressOffset>0x00001fcc</addressOffset>
+                <description>Provides CoreSight discovery information for the DWT</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>SUB</name>
+                        <description>Component sub-type</description>
+                        <bitRange>[7:4]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>MAJOR</name>
+                        <description>Component major type</description>
+                        <bitRange>[3:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>DWT_PIDR4</name>
+                <addressOffset>0x00001fd0</addressOffset>
+                <description>Provides CoreSight discovery information for the DWT</description>
+                <resetValue>0x00000004</resetValue>
+                <fields>
+                    <field>
+                        <name>SIZE</name>
+                        <description>See CoreSight Architecture Specification</description>
+                        <bitRange>[7:4]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>DES_2</name>
+                        <description>See CoreSight Architecture Specification</description>
+                        <bitRange>[3:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>DWT_PIDR5</name>
+                <addressOffset>0x00001fd4</addressOffset>
+                <description>Provides CoreSight discovery information for the DWT</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>DWT_PIDR5</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>DWT_PIDR6</name>
+                <addressOffset>0x00001fd8</addressOffset>
+                <description>Provides CoreSight discovery information for the DWT</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>DWT_PIDR6</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>DWT_PIDR7</name>
+                <addressOffset>0x00001fdc</addressOffset>
+                <description>Provides CoreSight discovery information for the DWT</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>DWT_PIDR7</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>DWT_PIDR0</name>
+                <addressOffset>0x00001fe0</addressOffset>
+                <description>Provides CoreSight discovery information for the DWT</description>
+                <resetValue>0x00000021</resetValue>
+                <fields>
+                    <field>
+                        <name>PART_0</name>
+                        <description>See CoreSight Architecture Specification</description>
+                        <bitRange>[7:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>DWT_PIDR1</name>
+                <addressOffset>0x00001fe4</addressOffset>
+                <description>Provides CoreSight discovery information for the DWT</description>
+                <resetValue>0x000000bd</resetValue>
+                <fields>
+                    <field>
+                        <name>DES_0</name>
+                        <description>See CoreSight Architecture Specification</description>
+                        <bitRange>[7:4]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>PART_1</name>
+                        <description>See CoreSight Architecture Specification</description>
+                        <bitRange>[3:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>DWT_PIDR2</name>
+                <addressOffset>0x00001fe8</addressOffset>
+                <description>Provides CoreSight discovery information for the DWT</description>
+                <resetValue>0x0000000b</resetValue>
+                <fields>
+                    <field>
+                        <name>REVISION</name>
+                        <description>See CoreSight Architecture Specification</description>
+                        <bitRange>[7:4]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>JEDEC</name>
+                        <description>See CoreSight Architecture Specification</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>DES_1</name>
+                        <description>See CoreSight Architecture Specification</description>
+                        <bitRange>[2:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>DWT_PIDR3</name>
+                <addressOffset>0x00001fec</addressOffset>
+                <description>Provides CoreSight discovery information for the DWT</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>REVAND</name>
+                        <description>See CoreSight Architecture Specification</description>
+                        <bitRange>[7:4]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CMOD</name>
+                        <description>See CoreSight Architecture Specification</description>
+                        <bitRange>[3:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>DWT_CIDR0</name>
+                <addressOffset>0x00001ff0</addressOffset>
+                <description>Provides CoreSight discovery information for the DWT</description>
+                <resetValue>0x0000000d</resetValue>
+                <fields>
+                    <field>
+                        <name>PRMBL_0</name>
+                        <description>See CoreSight Architecture Specification</description>
+                        <bitRange>[7:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>DWT_CIDR1</name>
+                <addressOffset>0x00001ff4</addressOffset>
+                <description>Provides CoreSight discovery information for the DWT</description>
+                <resetValue>0x00000090</resetValue>
+                <fields>
+                    <field>
+                        <name>CLASS</name>
+                        <description>See CoreSight Architecture Specification</description>
+                        <bitRange>[7:4]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>PRMBL_1</name>
+                        <description>See CoreSight Architecture Specification</description>
+                        <bitRange>[3:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>DWT_CIDR2</name>
+                <addressOffset>0x00001ff8</addressOffset>
+                <description>Provides CoreSight discovery information for the DWT</description>
+                <resetValue>0x00000005</resetValue>
+                <fields>
+                    <field>
+                        <name>PRMBL_2</name>
+                        <description>See CoreSight Architecture Specification</description>
+                        <bitRange>[7:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>DWT_CIDR3</name>
+                <addressOffset>0x00001ffc</addressOffset>
+                <description>Provides CoreSight discovery information for the DWT</description>
+                <resetValue>0x000000b1</resetValue>
+                <fields>
+                    <field>
+                        <name>PRMBL_3</name>
+                        <description>See CoreSight Architecture Specification</description>
+                        <bitRange>[7:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>FP_CTRL</name>
+                <addressOffset>0x00002000</addressOffset>
+                <description>Provides FPB implementation information, and the global enable for the FPB unit</description>
+                <resetValue>0x60005580</resetValue>
+                <fields>
+                    <field>
+                        <name>REV</name>
+                        <description>Flash Patch and Breakpoint Unit architecture revision</description>
+                        <bitRange>[31:28]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>NUM_CODE_14_12_</name>
+                        <description>Indicates the number of implemented instruction address comparators. Zero indicates no Instruction Address comparators are implemented. The Instruction Address comparators are numbered from 0 to NUM_CODE - 1</description>
+                        <bitRange>[14:12]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>NUM_LIT</name>
+                        <description>Indicates the number of implemented literal address comparators. The Literal Address comparators are numbered from NUM_CODE to NUM_CODE + NUM_LIT - 1</description>
+                        <bitRange>[11:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>NUM_CODE_7_4_</name>
+                        <description>Indicates the number of implemented instruction address comparators. Zero indicates no Instruction Address comparators are implemented. The Instruction Address comparators are numbered from 0 to NUM_CODE - 1</description>
+                        <bitRange>[7:4]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>KEY</name>
+                        <description>Writes to the FP_CTRL are ignored unless KEY is concurrently written to one</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ENABLE</name>
+                        <description>Enables the FPB</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>FP_REMAP</name>
+                <addressOffset>0x00002004</addressOffset>
+                <description>Indicates whether the implementation supports Flash Patch remap and, if it does, holds the target address for remap</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>RMPSPT</name>
+                        <description>Indicates whether the FPB unit supports the Flash Patch remap function</description>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>REMAP</name>
+                        <description>Holds the bits[28:5] of the Flash Patch remap address</description>
+                        <bitRange>[28:5]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>FP_COMP0</name>
+                <addressOffset>0x00002008</addressOffset>
+                <description>Holds an address for comparison. The effect of the match depends on the configuration of the FPB and whether the comparator is an instruction address comparator or a literal address comparator</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>BE</name>
+                        <description>Selects between flashpatch and breakpoint functionality</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>FP_COMP1</name>
+                <addressOffset>0x0000200c</addressOffset>
+                <description>Holds an address for comparison. The effect of the match depends on the configuration of the FPB and whether the comparator is an instruction address comparator or a literal address comparator</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>BE</name>
+                        <description>Selects between flashpatch and breakpoint functionality</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>FP_COMP2</name>
+                <addressOffset>0x00002010</addressOffset>
+                <description>Holds an address for comparison. The effect of the match depends on the configuration of the FPB and whether the comparator is an instruction address comparator or a literal address comparator</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>BE</name>
+                        <description>Selects between flashpatch and breakpoint functionality</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>FP_COMP3</name>
+                <addressOffset>0x00002014</addressOffset>
+                <description>Holds an address for comparison. The effect of the match depends on the configuration of the FPB and whether the comparator is an instruction address comparator or a literal address comparator</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>BE</name>
+                        <description>Selects between flashpatch and breakpoint functionality</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>FP_COMP4</name>
+                <addressOffset>0x00002018</addressOffset>
+                <description>Holds an address for comparison. The effect of the match depends on the configuration of the FPB and whether the comparator is an instruction address comparator or a literal address comparator</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>BE</name>
+                        <description>Selects between flashpatch and breakpoint functionality</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>FP_COMP5</name>
+                <addressOffset>0x0000201c</addressOffset>
+                <description>Holds an address for comparison. The effect of the match depends on the configuration of the FPB and whether the comparator is an instruction address comparator or a literal address comparator</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>BE</name>
+                        <description>Selects between flashpatch and breakpoint functionality</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>FP_COMP6</name>
+                <addressOffset>0x00002020</addressOffset>
+                <description>Holds an address for comparison. The effect of the match depends on the configuration of the FPB and whether the comparator is an instruction address comparator or a literal address comparator</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>BE</name>
+                        <description>Selects between flashpatch and breakpoint functionality</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>FP_COMP7</name>
+                <addressOffset>0x00002024</addressOffset>
+                <description>Holds an address for comparison. The effect of the match depends on the configuration of the FPB and whether the comparator is an instruction address comparator or a literal address comparator</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>BE</name>
+                        <description>Selects between flashpatch and breakpoint functionality</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>FP_DEVARCH</name>
+                <addressOffset>0x00002fbc</addressOffset>
+                <description>Provides CoreSight discovery information for the FPB</description>
+                <resetValue>0x47701a03</resetValue>
+                <fields>
+                    <field>
+                        <name>ARCHITECT</name>
+                        <description>Defines the architect of the component. Bits [31:28] are the JEP106 continuation code (JEP106 bank ID, minus 1) and bits [27:21] are the JEP106 ID code.</description>
+                        <bitRange>[31:21]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>PRESENT</name>
+                        <description>Defines that the DEVARCH register is present</description>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>REVISION</name>
+                        <description>Defines the architecture revision of the component</description>
+                        <bitRange>[19:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>ARCHVER</name>
+                        <description>Defines the architecture version of the component</description>
+                        <bitRange>[15:12]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>ARCHPART</name>
+                        <description>Defines the architecture of the component</description>
+                        <bitRange>[11:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>FP_DEVTYPE</name>
+                <addressOffset>0x00002fcc</addressOffset>
+                <description>Provides CoreSight discovery information for the FPB</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>SUB</name>
+                        <description>Component sub-type</description>
+                        <bitRange>[7:4]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>MAJOR</name>
+                        <description>Component major type</description>
+                        <bitRange>[3:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>FP_PIDR4</name>
+                <addressOffset>0x00002fd0</addressOffset>
+                <description>Provides CoreSight discovery information for the FP</description>
+                <resetValue>0x00000004</resetValue>
+                <fields>
+                    <field>
+                        <name>SIZE</name>
+                        <description>See CoreSight Architecture Specification</description>
+                        <bitRange>[7:4]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>DES_2</name>
+                        <description>See CoreSight Architecture Specification</description>
+                        <bitRange>[3:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>FP_PIDR5</name>
+                <addressOffset>0x00002fd4</addressOffset>
+                <description>Provides CoreSight discovery information for the FP</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>FP_PIDR5</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>FP_PIDR6</name>
+                <addressOffset>0x00002fd8</addressOffset>
+                <description>Provides CoreSight discovery information for the FP</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>FP_PIDR6</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>FP_PIDR7</name>
+                <addressOffset>0x00002fdc</addressOffset>
+                <description>Provides CoreSight discovery information for the FP</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>FP_PIDR7</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>FP_PIDR0</name>
+                <addressOffset>0x00002fe0</addressOffset>
+                <description>Provides CoreSight discovery information for the FP</description>
+                <resetValue>0x00000021</resetValue>
+                <fields>
+                    <field>
+                        <name>PART_0</name>
+                        <description>See CoreSight Architecture Specification</description>
+                        <bitRange>[7:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>FP_PIDR1</name>
+                <addressOffset>0x00002fe4</addressOffset>
+                <description>Provides CoreSight discovery information for the FP</description>
+                <resetValue>0x000000bd</resetValue>
+                <fields>
+                    <field>
+                        <name>DES_0</name>
+                        <description>See CoreSight Architecture Specification</description>
+                        <bitRange>[7:4]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>PART_1</name>
+                        <description>See CoreSight Architecture Specification</description>
+                        <bitRange>[3:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>FP_PIDR2</name>
+                <addressOffset>0x00002fe8</addressOffset>
+                <description>Provides CoreSight discovery information for the FP</description>
+                <resetValue>0x0000000b</resetValue>
+                <fields>
+                    <field>
+                        <name>REVISION</name>
+                        <description>See CoreSight Architecture Specification</description>
+                        <bitRange>[7:4]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>JEDEC</name>
+                        <description>See CoreSight Architecture Specification</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>DES_1</name>
+                        <description>See CoreSight Architecture Specification</description>
+                        <bitRange>[2:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>FP_PIDR3</name>
+                <addressOffset>0x00002fec</addressOffset>
+                <description>Provides CoreSight discovery information for the FP</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>REVAND</name>
+                        <description>See CoreSight Architecture Specification</description>
+                        <bitRange>[7:4]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CMOD</name>
+                        <description>See CoreSight Architecture Specification</description>
+                        <bitRange>[3:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>FP_CIDR0</name>
+                <addressOffset>0x00002ff0</addressOffset>
+                <description>Provides CoreSight discovery information for the FP</description>
+                <resetValue>0x0000000d</resetValue>
+                <fields>
+                    <field>
+                        <name>PRMBL_0</name>
+                        <description>See CoreSight Architecture Specification</description>
+                        <bitRange>[7:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>FP_CIDR1</name>
+                <addressOffset>0x00002ff4</addressOffset>
+                <description>Provides CoreSight discovery information for the FP</description>
+                <resetValue>0x00000090</resetValue>
+                <fields>
+                    <field>
+                        <name>CLASS</name>
+                        <description>See CoreSight Architecture Specification</description>
+                        <bitRange>[7:4]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>PRMBL_1</name>
+                        <description>See CoreSight Architecture Specification</description>
+                        <bitRange>[3:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>FP_CIDR2</name>
+                <addressOffset>0x00002ff8</addressOffset>
+                <description>Provides CoreSight discovery information for the FP</description>
+                <resetValue>0x00000005</resetValue>
+                <fields>
+                    <field>
+                        <name>PRMBL_2</name>
+                        <description>See CoreSight Architecture Specification</description>
+                        <bitRange>[7:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>FP_CIDR3</name>
+                <addressOffset>0x00002ffc</addressOffset>
+                <description>Provides CoreSight discovery information for the FP</description>
+                <resetValue>0x000000b1</resetValue>
+                <fields>
+                    <field>
+                        <name>PRMBL_3</name>
+                        <description>See CoreSight Architecture Specification</description>
+                        <bitRange>[7:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>ICTR</name>
+                <addressOffset>0x0000e004</addressOffset>
+                <description>Provides information about the interrupt controller</description>
+                <resetValue>0x00000001</resetValue>
+                <fields>
+                    <field>
+                        <name>INTLINESNUM</name>
+                        <description>Indicates the number of the highest implemented register in each of the NVIC control register sets, or in the case of NVIC_IPR*n, 4×INTLINESNUM</description>
+                        <bitRange>[3:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>ACTLR</name>
+                <addressOffset>0x0000e008</addressOffset>
+                <description>Provides IMPLEMENTATION DEFINED configuration and control options</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>EXTEXCLALL</name>
+                        <description>External Exclusives Allowed with no MPU</description>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DISITMATBFLUSH</name>
+                        <description>Disable ATB Flush</description>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>FPEXCODIS</name>
+                        <description>Disable FPU exception outputs</description>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DISOOFP</name>
+                        <description>Disable out-of-order FP instruction completion</description>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DISFOLD</name>
+                        <description>Disable dual-issue.</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DISMCYCINT</name>
+                        <description>Disable dual-issue.</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SYST_CSR</name>
+                <addressOffset>0x0000e010</addressOffset>
+                <description>Use the SysTick Control and Status Register to enable the SysTick features.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>COUNTFLAG</name>
+                        <description>Returns 1 if timer counted to 0 since last time this was read. Clears on read by application or debugger.</description>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CLKSOURCE</name>
+                        <description>SysTick clock source. Always reads as one if SYST_CALIB reports NOREF. 
+                            Selects the SysTick timer clock source: 
+                            0 = External reference clock. 
+                            1 = Processor clock.</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>TICKINT</name>
+                        <description>Enables SysTick exception request: 
+                            0 = Counting down to zero does not assert the SysTick exception request. 
+                            1 = Counting down to zero to asserts the SysTick exception request.</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ENABLE</name>
+                        <description>Enable SysTick counter: 
+                            0 = Counter disabled. 
+                            1 = Counter enabled.</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SYST_RVR</name>
+                <addressOffset>0x0000e014</addressOffset>
+                <description>Use the SysTick Reload Value Register to specify the start value to load into the current value register when the counter reaches 0. It can be any value between 0 and 0x00FFFFFF. A start value of 0 is possible, but has no effect because the SysTick interrupt and COUNTFLAG are activated when counting from 1 to 0. The reset value of this register is UNKNOWN. 
+                    To generate a multi-shot timer with a period of N processor clock cycles, use a RELOAD value of N-1. For example, if the SysTick interrupt is required every 100 clock pulses, set RELOAD to 99.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>RELOAD</name>
+                        <description>Value to load into the SysTick Current Value Register when the counter reaches 0.</description>
+                        <bitRange>[23:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SYST_CVR</name>
+                <addressOffset>0x0000e018</addressOffset>
+                <description>Use the SysTick Current Value Register to find the current value in the register. The reset value of this register is UNKNOWN.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CURRENT</name>
+                        <description>Reads return the current value of the SysTick counter. This register is write-clear. Writing to it with any value clears the register to 0. Clearing this register also clears the COUNTFLAG bit of the SysTick Control and Status Register.</description>
+                        <bitRange>[23:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SYST_CALIB</name>
+                <addressOffset>0x0000e01c</addressOffset>
+                <description>Use the SysTick Calibration Value Register to enable software to scale to any required speed using divide and multiply.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>NOREF</name>
+                        <description>If reads as 1, the Reference clock is not provided - the CLKSOURCE bit of the SysTick Control and Status register will be forced to 1 and cannot be cleared to 0.</description>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SKEW</name>
+                        <description>If reads as 1, the calibration value for 10ms is inexact (due to clock frequency).</description>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>TENMS</name>
+                        <description>An optional Reload value to be used for 10ms (100Hz) timing, subject to system clock skew errors. If the value reads as 0, the calibration value is not known.</description>
+                        <bitRange>[23:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>NVIC_ISER0</name>
+                <addressOffset>0x0000e100</addressOffset>
+                <description>Enables or reads the enabled state of each group of 32 interrupts</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>SETENA</name>
+                        <description>For SETENA[m] in NVIC_ISER*n, indicates whether interrupt 32*n + m is enabled</description>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>NVIC_ISER1</name>
+                <addressOffset>0x0000e104</addressOffset>
+                <description>Enables or reads the enabled state of each group of 32 interrupts</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>SETENA</name>
+                        <description>For SETENA[m] in NVIC_ISER*n, indicates whether interrupt 32*n + m is enabled</description>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>NVIC_ICER0</name>
+                <addressOffset>0x0000e180</addressOffset>
+                <description>Clears or reads the enabled state of each group of 32 interrupts</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CLRENA</name>
+                        <description>For CLRENA[m] in NVIC_ICER*n, indicates whether interrupt 32*n + m is enabled</description>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>NVIC_ICER1</name>
+                <addressOffset>0x0000e184</addressOffset>
+                <description>Clears or reads the enabled state of each group of 32 interrupts</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CLRENA</name>
+                        <description>For CLRENA[m] in NVIC_ICER*n, indicates whether interrupt 32*n + m is enabled</description>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>NVIC_ISPR0</name>
+                <addressOffset>0x0000e200</addressOffset>
+                <description>Enables or reads the pending state of each group of 32 interrupts</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>SETPEND</name>
+                        <description>For SETPEND[m] in NVIC_ISPR*n, indicates whether interrupt 32*n + m is pending</description>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>NVIC_ISPR1</name>
+                <addressOffset>0x0000e204</addressOffset>
+                <description>Enables or reads the pending state of each group of 32 interrupts</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>SETPEND</name>
+                        <description>For SETPEND[m] in NVIC_ISPR*n, indicates whether interrupt 32*n + m is pending</description>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>NVIC_ICPR0</name>
+                <addressOffset>0x0000e280</addressOffset>
+                <description>Clears or reads the pending state of each group of 32 interrupts</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CLRPEND</name>
+                        <description>For CLRPEND[m] in NVIC_ICPR*n, indicates whether interrupt 32*n + m is pending</description>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>NVIC_ICPR1</name>
+                <addressOffset>0x0000e284</addressOffset>
+                <description>Clears or reads the pending state of each group of 32 interrupts</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CLRPEND</name>
+                        <description>For CLRPEND[m] in NVIC_ICPR*n, indicates whether interrupt 32*n + m is pending</description>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>NVIC_IABR0</name>
+                <addressOffset>0x0000e300</addressOffset>
+                <description>For each group of 32 interrupts, shows the active state of each interrupt</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>ACTIVE</name>
+                        <description>For ACTIVE[m] in NVIC_IABR*n, indicates the active state for interrupt 32*n+m</description>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>NVIC_IABR1</name>
+                <addressOffset>0x0000e304</addressOffset>
+                <description>For each group of 32 interrupts, shows the active state of each interrupt</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>ACTIVE</name>
+                        <description>For ACTIVE[m] in NVIC_IABR*n, indicates the active state for interrupt 32*n+m</description>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>NVIC_ITNS0</name>
+                <addressOffset>0x0000e380</addressOffset>
+                <description>For each group of 32 interrupts, determines whether each interrupt targets Non-secure or Secure state</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>ITNS</name>
+                        <description>For ITNS[m] in NVIC_ITNS*n, `IAAMO the target Security state for interrupt 32*n+m</description>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>NVIC_ITNS1</name>
+                <addressOffset>0x0000e384</addressOffset>
+                <description>For each group of 32 interrupts, determines whether each interrupt targets Non-secure or Secure state</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>ITNS</name>
+                        <description>For ITNS[m] in NVIC_ITNS*n, `IAAMO the target Security state for interrupt 32*n+m</description>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>NVIC_IPR0</name>
+                <addressOffset>0x0000e400</addressOffset>
+                <description>Sets or reads interrupt priorities</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>PRI_N3</name>
+                        <description>For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt</description>
+                        <bitRange>[31:28]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PRI_N2</name>
+                        <description>For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt</description>
+                        <bitRange>[23:20]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PRI_N1</name>
+                        <description>For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt</description>
+                        <bitRange>[15:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PRI_N0</name>
+                        <description>For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt</description>
+                        <bitRange>[7:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>NVIC_IPR1</name>
+                <addressOffset>0x0000e404</addressOffset>
+                <description>Sets or reads interrupt priorities</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>PRI_N3</name>
+                        <description>For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt</description>
+                        <bitRange>[31:28]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PRI_N2</name>
+                        <description>For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt</description>
+                        <bitRange>[23:20]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PRI_N1</name>
+                        <description>For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt</description>
+                        <bitRange>[15:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PRI_N0</name>
+                        <description>For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt</description>
+                        <bitRange>[7:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>NVIC_IPR2</name>
+                <addressOffset>0x0000e408</addressOffset>
+                <description>Sets or reads interrupt priorities</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>PRI_N3</name>
+                        <description>For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt</description>
+                        <bitRange>[31:28]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PRI_N2</name>
+                        <description>For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt</description>
+                        <bitRange>[23:20]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PRI_N1</name>
+                        <description>For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt</description>
+                        <bitRange>[15:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PRI_N0</name>
+                        <description>For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt</description>
+                        <bitRange>[7:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>NVIC_IPR3</name>
+                <addressOffset>0x0000e40c</addressOffset>
+                <description>Sets or reads interrupt priorities</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>PRI_N3</name>
+                        <description>For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt</description>
+                        <bitRange>[31:28]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PRI_N2</name>
+                        <description>For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt</description>
+                        <bitRange>[23:20]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PRI_N1</name>
+                        <description>For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt</description>
+                        <bitRange>[15:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PRI_N0</name>
+                        <description>For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt</description>
+                        <bitRange>[7:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>NVIC_IPR4</name>
+                <addressOffset>0x0000e410</addressOffset>
+                <description>Sets or reads interrupt priorities</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>PRI_N3</name>
+                        <description>For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt</description>
+                        <bitRange>[31:28]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PRI_N2</name>
+                        <description>For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt</description>
+                        <bitRange>[23:20]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PRI_N1</name>
+                        <description>For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt</description>
+                        <bitRange>[15:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PRI_N0</name>
+                        <description>For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt</description>
+                        <bitRange>[7:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>NVIC_IPR5</name>
+                <addressOffset>0x0000e414</addressOffset>
+                <description>Sets or reads interrupt priorities</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>PRI_N3</name>
+                        <description>For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt</description>
+                        <bitRange>[31:28]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PRI_N2</name>
+                        <description>For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt</description>
+                        <bitRange>[23:20]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PRI_N1</name>
+                        <description>For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt</description>
+                        <bitRange>[15:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PRI_N0</name>
+                        <description>For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt</description>
+                        <bitRange>[7:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>NVIC_IPR6</name>
+                <addressOffset>0x0000e418</addressOffset>
+                <description>Sets or reads interrupt priorities</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>PRI_N3</name>
+                        <description>For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt</description>
+                        <bitRange>[31:28]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PRI_N2</name>
+                        <description>For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt</description>
+                        <bitRange>[23:20]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PRI_N1</name>
+                        <description>For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt</description>
+                        <bitRange>[15:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PRI_N0</name>
+                        <description>For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt</description>
+                        <bitRange>[7:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>NVIC_IPR7</name>
+                <addressOffset>0x0000e41c</addressOffset>
+                <description>Sets or reads interrupt priorities</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>PRI_N3</name>
+                        <description>For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt</description>
+                        <bitRange>[31:28]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PRI_N2</name>
+                        <description>For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt</description>
+                        <bitRange>[23:20]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PRI_N1</name>
+                        <description>For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt</description>
+                        <bitRange>[15:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PRI_N0</name>
+                        <description>For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt</description>
+                        <bitRange>[7:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>NVIC_IPR8</name>
+                <addressOffset>0x0000e420</addressOffset>
+                <description>Sets or reads interrupt priorities</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>PRI_N3</name>
+                        <description>For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt</description>
+                        <bitRange>[31:28]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PRI_N2</name>
+                        <description>For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt</description>
+                        <bitRange>[23:20]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PRI_N1</name>
+                        <description>For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt</description>
+                        <bitRange>[15:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PRI_N0</name>
+                        <description>For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt</description>
+                        <bitRange>[7:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>NVIC_IPR9</name>
+                <addressOffset>0x0000e424</addressOffset>
+                <description>Sets or reads interrupt priorities</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>PRI_N3</name>
+                        <description>For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt</description>
+                        <bitRange>[31:28]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PRI_N2</name>
+                        <description>For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt</description>
+                        <bitRange>[23:20]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PRI_N1</name>
+                        <description>For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt</description>
+                        <bitRange>[15:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PRI_N0</name>
+                        <description>For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt</description>
+                        <bitRange>[7:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>NVIC_IPR10</name>
+                <addressOffset>0x0000e428</addressOffset>
+                <description>Sets or reads interrupt priorities</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>PRI_N3</name>
+                        <description>For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt</description>
+                        <bitRange>[31:28]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PRI_N2</name>
+                        <description>For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt</description>
+                        <bitRange>[23:20]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PRI_N1</name>
+                        <description>For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt</description>
+                        <bitRange>[15:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PRI_N0</name>
+                        <description>For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt</description>
+                        <bitRange>[7:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>NVIC_IPR11</name>
+                <addressOffset>0x0000e42c</addressOffset>
+                <description>Sets or reads interrupt priorities</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>PRI_N3</name>
+                        <description>For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt</description>
+                        <bitRange>[31:28]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PRI_N2</name>
+                        <description>For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt</description>
+                        <bitRange>[23:20]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PRI_N1</name>
+                        <description>For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt</description>
+                        <bitRange>[15:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PRI_N0</name>
+                        <description>For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt</description>
+                        <bitRange>[7:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>NVIC_IPR12</name>
+                <addressOffset>0x0000e430</addressOffset>
+                <description>Sets or reads interrupt priorities</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>PRI_N3</name>
+                        <description>For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt</description>
+                        <bitRange>[31:28]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PRI_N2</name>
+                        <description>For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt</description>
+                        <bitRange>[23:20]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PRI_N1</name>
+                        <description>For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt</description>
+                        <bitRange>[15:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PRI_N0</name>
+                        <description>For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt</description>
+                        <bitRange>[7:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>NVIC_IPR13</name>
+                <addressOffset>0x0000e434</addressOffset>
+                <description>Sets or reads interrupt priorities</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>PRI_N3</name>
+                        <description>For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt</description>
+                        <bitRange>[31:28]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PRI_N2</name>
+                        <description>For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt</description>
+                        <bitRange>[23:20]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PRI_N1</name>
+                        <description>For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt</description>
+                        <bitRange>[15:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PRI_N0</name>
+                        <description>For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt</description>
+                        <bitRange>[7:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>NVIC_IPR14</name>
+                <addressOffset>0x0000e438</addressOffset>
+                <description>Sets or reads interrupt priorities</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>PRI_N3</name>
+                        <description>For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt</description>
+                        <bitRange>[31:28]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PRI_N2</name>
+                        <description>For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt</description>
+                        <bitRange>[23:20]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PRI_N1</name>
+                        <description>For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt</description>
+                        <bitRange>[15:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PRI_N0</name>
+                        <description>For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt</description>
+                        <bitRange>[7:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>NVIC_IPR15</name>
+                <addressOffset>0x0000e43c</addressOffset>
+                <description>Sets or reads interrupt priorities</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>PRI_N3</name>
+                        <description>For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt</description>
+                        <bitRange>[31:28]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PRI_N2</name>
+                        <description>For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt</description>
+                        <bitRange>[23:20]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PRI_N1</name>
+                        <description>For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt</description>
+                        <bitRange>[15:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PRI_N0</name>
+                        <description>For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt</description>
+                        <bitRange>[7:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CPUID</name>
+                <addressOffset>0x0000ed00</addressOffset>
+                <description>Provides identification information for the PE, including an implementer code for the device and a device ID number</description>
+                <resetValue>0x411fd210</resetValue>
+                <fields>
+                    <field>
+                        <name>IMPLEMENTER</name>
+                        <description>This field must hold an implementer code that has been assigned by ARM</description>
+                        <bitRange>[31:24]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>VARIANT</name>
+                        <description>IMPLEMENTATION DEFINED variant number. Typically, this field is used to distinguish between different product variants, or major revisions of a product</description>
+                        <bitRange>[23:20]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>ARCHITECTURE</name>
+                        <description>Defines the Architecture implemented by the PE</description>
+                        <bitRange>[19:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>PARTNO</name>
+                        <description>IMPLEMENTATION DEFINED primary part number for the device</description>
+                        <bitRange>[15:4]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>REVISION</name>
+                        <description>IMPLEMENTATION DEFINED revision number for the device</description>
+                        <bitRange>[3:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>ICSR</name>
+                <addressOffset>0x0000ed04</addressOffset>
+                <description>Controls and provides status information for NMI, PendSV, SysTick and interrupts</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>PENDNMISET</name>
+                        <description>Indicates whether the NMI exception is pending</description>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>PENDNMICLR</name>
+                        <description>Allows the NMI exception pend state to be cleared</description>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PENDSVSET</name>
+                        <description>Indicates whether the PendSV `FTSSS exception is pending</description>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>PENDSVCLR</name>
+                        <description>Allows the PendSV exception pend state to be cleared `FTSSS</description>
+                        <bitRange>[27:27]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PENDSTSET</name>
+                        <description>Indicates whether the SysTick `FTSSS exception is pending</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>PENDSTCLR</name>
+                        <description>Allows the SysTick exception pend state to be cleared `FTSSS</description>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>STTNS</name>
+                        <description>Controls whether in a single SysTick implementation, the SysTick is Secure or Non-secure</description>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ISRPREEMPT</name>
+                        <description>Indicates whether a pending exception will be serviced on exit from debug halt state</description>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>ISRPENDING</name>
+                        <description>Indicates whether an external interrupt, generated by the NVIC, is pending</description>
+                        <bitRange>[22:22]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>VECTPENDING</name>
+                        <description>The exception number of the highest priority pending and enabled interrupt</description>
+                        <bitRange>[20:12]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>RETTOBASE</name>
+                        <description>In Handler mode, indicates whether there is more than one active exception</description>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>VECTACTIVE</name>
+                        <description>The exception number of the current executing exception</description>
+                        <bitRange>[8:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>VTOR</name>
+                <addressOffset>0x0000ed08</addressOffset>
+                <description>The VTOR indicates the offset of the vector table base address from memory address 0x00000000.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>TBLOFF</name>
+                        <description>Vector table base offset field. It contains bits[31:7] of the offset of the table base from the bottom of the memory map.</description>
+                        <bitRange>[31:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>AIRCR</name>
+                <addressOffset>0x0000ed0c</addressOffset>
+                <description>Use the Application Interrupt and Reset Control Register to: determine data endianness, clear all active state information from debug halt mode, request a system reset.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>VECTKEY</name>
+                        <description>Register key: 
+                            Reads as Unknown 
+                            On writes, write 0x05FA to VECTKEY, otherwise the write is ignored.</description>
+                        <bitRange>[31:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ENDIANESS</name>
+                        <description>Data endianness implemented: 
+                            0 = Little-endian.</description>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>PRIS</name>
+                        <description>Prioritize Secure exceptions. The value of this bit defines whether Secure exception priority boosting is enabled. 
+                            0	Priority ranges of Secure and Non-secure exceptions are identical. 
+                            1	Non-secure exceptions are de-prioritized.</description>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>BFHFNMINS</name>
+                        <description>BusFault, HardFault, and NMI Non-secure enable. 
+                            0	BusFault, HardFault, and NMI are Secure. 
+                            1	BusFault and NMI are Non-secure and exceptions can target Non-secure HardFault.</description>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PRIGROUP</name>
+                        <description>Interrupt priority grouping field. This field determines the split of group priority from subpriority. 
+                            See https://developer.arm.com/documentation/100235/0004/the-cortex-m33-peripherals/system-control-block/application-interrupt-and-reset-control-register?lang=en</description>
+                        <bitRange>[10:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SYSRESETREQS</name>
+                        <description>System reset request, Secure state only. 
+                            0	SYSRESETREQ functionality is available to both Security states. 
+                            1 SYSRESETREQ functionality is only available to Secure state.</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SYSRESETREQ</name>
+                        <description>Writing 1 to this bit causes the SYSRESETREQ signal to the outer system to be asserted to request a reset. The intention is to force a large system reset of all major components except for debug. The C_HALT bit in the DHCSR is cleared as a result of the system reset requested. The debugger does not lose contact with the device.</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>VECTCLRACTIVE</name>
+                        <description>Clears all active state information for fixed and configurable exceptions. This bit: is self-clearing, can only be set by the DAP when the core is halted.  When set: clears all active exception status of the processor, forces a return to Thread mode, forces an IPSR of 0. A debugger must re-initialize the stack.</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SCR</name>
+                <addressOffset>0x0000ed10</addressOffset>
+                <description>System Control Register. Use the System Control Register for power-management functions: signal to the system when the processor can enter a low power state, control how the processor enters and exits low power states.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>SEVONPEND</name>
+                        <description>Send Event on Pending bit: 
+                            0 = Only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded. 
+                            1 = Enabled events and all interrupts, including disabled interrupts, can wakeup the processor. 
+                            When an event or interrupt becomes pending, the event signal wakes up the processor from WFE. If the 
+                            processor is not waiting for an event, the event is registered and affects the next WFE. 
+                            The processor also wakes up on execution of an SEV instruction or an external event.</description>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SLEEPDEEPS</name>
+                        <description>0 SLEEPDEEP is available to both security states 
+                            1 SLEEPDEEP is only available to Secure state</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SLEEPDEEP</name>
+                        <description>Controls whether the processor uses sleep or deep sleep as its low power mode: 
+                            0 = Sleep. 
+                            1 = Deep sleep.</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SLEEPONEXIT</name>
+                        <description>Indicates sleep-on-exit when returning from Handler mode to Thread mode: 
+                            0 = Do not sleep when returning to Thread mode. 
+                            1 = Enter sleep, or deep sleep, on return from an ISR to Thread mode. 
+                            Setting this bit to 1 enables an interrupt driven application to avoid returning to an empty main application.</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CCR</name>
+                <addressOffset>0x0000ed14</addressOffset>
+                <description>Sets or returns configuration and control data</description>
+                <resetValue>0x00000201</resetValue>
+                <fields>
+                    <field>
+                        <name>BP</name>
+                        <description>Enables program flow prediction `FTSSS</description>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>IC</name>
+                        <description>This is a global enable bit for instruction caches in the selected Security state</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>DC</name>
+                        <description>Enables data caching of all data accesses to Normal memory `FTSSS</description>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>STKOFHFNMIGN</name>
+                        <description>Controls the effect of a stack limit violation while executing at a requested priority less than 0</description>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>RES1</name>
+                        <description>Reserved, RES1</description>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>BFHFNMIGN</name>
+                        <description>Determines the effect of precise BusFaults on handlers running at a requested priority less than 0</description>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DIV_0_TRP</name>
+                        <description>Controls the generation of a DIVBYZERO UsageFault when attempting to perform integer division by zero</description>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>UNALIGN_TRP</name>
+                        <description>Controls the trapping of unaligned word or halfword accesses</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>USERSETMPEND</name>
+                        <description>Determines whether unprivileged accesses are permitted to pend interrupts via the STIR</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>RES1_1</name>
+                        <description>Reserved, RES1</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SHPR1</name>
+                <addressOffset>0x0000ed18</addressOffset>
+                <description>Sets or returns priority for system handlers 4 - 7</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>PRI_7_3</name>
+                        <description>Priority of system handler 7, SecureFault</description>
+                        <bitRange>[31:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PRI_6_3</name>
+                        <description>Priority of system handler 6, SecureFault</description>
+                        <bitRange>[23:21]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PRI_5_3</name>
+                        <description>Priority of system handler 5, SecureFault</description>
+                        <bitRange>[15:13]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PRI_4_3</name>
+                        <description>Priority of system handler 4, SecureFault</description>
+                        <bitRange>[7:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SHPR2</name>
+                <addressOffset>0x0000ed1c</addressOffset>
+                <description>Sets or returns priority for system handlers 8 - 11</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>PRI_11_3</name>
+                        <description>Priority of system handler 11, SecureFault</description>
+                        <bitRange>[31:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PRI_10</name>
+                        <description>Reserved, RES0</description>
+                        <bitRange>[23:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>PRI_9</name>
+                        <description>Reserved, RES0</description>
+                        <bitRange>[15:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>PRI_8</name>
+                        <description>Reserved, RES0</description>
+                        <bitRange>[7:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SHPR3</name>
+                <addressOffset>0x0000ed20</addressOffset>
+                <description>Sets or returns priority for system handlers 12 - 15</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>PRI_15_3</name>
+                        <description>Priority of system handler 15, SecureFault</description>
+                        <bitRange>[31:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PRI_14_3</name>
+                        <description>Priority of system handler 14, SecureFault</description>
+                        <bitRange>[23:21]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PRI_13</name>
+                        <description>Reserved, RES0</description>
+                        <bitRange>[15:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>PRI_12_3</name>
+                        <description>Priority of system handler 12, SecureFault</description>
+                        <bitRange>[7:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SHCSR</name>
+                <addressOffset>0x0000ed24</addressOffset>
+                <description>Provides access to the active and pending status of system exceptions</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>HARDFAULTPENDED</name>
+                        <description>`IAAMO the pending state of the HardFault exception `CTTSSS</description>
+                        <bitRange>[21:21]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SECUREFAULTPENDED</name>
+                        <description>`IAAMO the pending state of the SecureFault exception</description>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SECUREFAULTENA</name>
+                        <description>`DW the SecureFault exception is enabled</description>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>USGFAULTENA</name>
+                        <description>`DW the UsageFault exception is enabled `FTSSS</description>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>BUSFAULTENA</name>
+                        <description>`DW the BusFault exception is enabled</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>MEMFAULTENA</name>
+                        <description>`DW the MemManage exception is enabled `FTSSS</description>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SVCALLPENDED</name>
+                        <description>`IAAMO the pending state of the SVCall exception `FTSSS</description>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>BUSFAULTPENDED</name>
+                        <description>`IAAMO the pending state of the BusFault exception</description>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>MEMFAULTPENDED</name>
+                        <description>`IAAMO the pending state of the MemManage exception `FTSSS</description>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>USGFAULTPENDED</name>
+                        <description>The UsageFault exception is banked between Security states, `IAAMO the pending state of the UsageFault exception `FTSSS</description>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SYSTICKACT</name>
+                        <description>`IAAMO the active state of the SysTick exception `FTSSS</description>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PENDSVACT</name>
+                        <description>`IAAMO the active state of the PendSV exception `FTSSS</description>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>MONITORACT</name>
+                        <description>`IAAMO the active state of the DebugMonitor exception</description>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SVCALLACT</name>
+                        <description>`IAAMO the active state of the SVCall exception `FTSSS</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>NMIACT</name>
+                        <description>`IAAMO the active state of the NMI exception</description>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SECUREFAULTACT</name>
+                        <description>`IAAMO the active state of the SecureFault exception</description>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>USGFAULTACT</name>
+                        <description>`IAAMO the active state of the UsageFault exception `FTSSS</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>HARDFAULTACT</name>
+                        <description>Indicates and allows limited modification of the active state of the HardFault exception `FTSSS</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>BUSFAULTACT</name>
+                        <description>`IAAMO the active state of the BusFault exception</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>MEMFAULTACT</name>
+                        <description>`IAAMO the active state of the MemManage exception `FTSSS</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CFSR</name>
+                <addressOffset>0x0000ed28</addressOffset>
+                <description>Contains the three Configurable Fault Status Registers.
+
+                    31:16 UFSR: Provides information on UsageFault exceptions
+
+                    15:8 BFSR: Provides information on BusFault exceptions
+
+                    7:0 MMFSR: Provides information on MemManage exceptions</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>UFSR_DIVBYZERO</name>
+                        <description>Sticky flag indicating whether an integer division by zero error has occurred</description>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>UFSR_UNALIGNED</name>
+                        <description>Sticky flag indicating whether an unaligned access error has occurred</description>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>UFSR_STKOF</name>
+                        <description>Sticky flag indicating whether a stack overflow error has occurred</description>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>UFSR_NOCP</name>
+                        <description>Sticky flag indicating whether a coprocessor disabled or not present error has occurred</description>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>UFSR_INVPC</name>
+                        <description>Sticky flag indicating whether an integrity check error has occurred</description>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>UFSR_INVSTATE</name>
+                        <description>Sticky flag indicating whether an EPSR.T or EPSR.IT validity error has occurred</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>UFSR_UNDEFINSTR</name>
+                        <description>Sticky flag indicating whether an undefined instruction error has occurred</description>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>BFSR_BFARVALID</name>
+                        <description>Indicates validity of the contents of the BFAR register</description>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>BFSR_LSPERR</name>
+                        <description>Records whether a BusFault occurred during FP lazy state preservation</description>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>BFSR_STKERR</name>
+                        <description>Records whether a derived BusFault occurred during exception entry stacking</description>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>BFSR_UNSTKERR</name>
+                        <description>Records whether a derived BusFault occurred during exception return unstacking</description>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>BFSR_IMPRECISERR</name>
+                        <description>Records whether an imprecise data access error has occurred</description>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>BFSR_PRECISERR</name>
+                        <description>Records whether a precise data access error has occurred</description>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>BFSR_IBUSERR</name>
+                        <description>Records whether a BusFault on an instruction prefetch has occurred</description>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>MMFSR</name>
+                        <description>Provides information on MemManage exceptions</description>
+                        <bitRange>[7:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>HFSR</name>
+                <addressOffset>0x0000ed2c</addressOffset>
+                <description>Shows the cause of any HardFaults</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>DEBUGEVT</name>
+                        <description>Indicates when a Debug event has occurred</description>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>FORCED</name>
+                        <description>Indicates that a fault with configurable priority has been escalated to a HardFault exception, because it could not be made active, because of priority, or because it was disabled</description>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>VECTTBL</name>
+                        <description>Indicates when a fault has occurred because of a vector table read error on exception processing</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>DFSR</name>
+                <addressOffset>0x0000ed30</addressOffset>
+                <description>Shows which debug event occurred</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>EXTERNAL</name>
+                        <description>Sticky flag indicating whether an External debug request debug event has occurred</description>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>VCATCH</name>
+                        <description>Sticky flag indicating whether a Vector catch debug event has occurred</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DWTTRAP</name>
+                        <description>Sticky flag indicating whether a Watchpoint debug event has occurred</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>BKPT</name>
+                        <description>Sticky flag indicating whether a Breakpoint debug event has occurred</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>HALTED</name>
+                        <description>Sticky flag indicating that a Halt request debug event or Step debug event has occurred</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>MMFAR</name>
+                <addressOffset>0x0000ed34</addressOffset>
+                <description>Shows the address of the memory location that caused an MPU fault</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>ADDRESS</name>
+                        <description>This register is updated with the address of a location that produced a MemManage fault. The MMFSR shows the cause of the fault, and whether this field is valid. This field is valid only when MMFSR.MMARVALID is set, otherwise it is UNKNOWN</description>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>BFAR</name>
+                <addressOffset>0x0000ed38</addressOffset>
+                <description>Shows the address associated with a precise data access BusFault</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>ADDRESS</name>
+                        <description>This register is updated with the address of a location that produced a BusFault. The BFSR shows the reason for the fault. This field is valid only when BFSR.BFARVALID is set, otherwise it is UNKNOWN</description>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>ID_PFR0</name>
+                <addressOffset>0x0000ed40</addressOffset>
+                <description>Gives top-level information about the instruction set supported by the PE</description>
+                <resetValue>0x00000030</resetValue>
+                <fields>
+                    <field>
+                        <name>STATE1</name>
+                        <description>T32 instruction set support</description>
+                        <bitRange>[7:4]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>STATE0</name>
+                        <description>A32 instruction set support</description>
+                        <bitRange>[3:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>ID_PFR1</name>
+                <addressOffset>0x0000ed44</addressOffset>
+                <description>Gives information about the programmers&#39; model and Extensions support</description>
+                <resetValue>0x00000520</resetValue>
+                <fields>
+                    <field>
+                        <name>MPROGMOD</name>
+                        <description>Identifies support for the M-Profile programmers&#39; model support</description>
+                        <bitRange>[11:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SECURITY</name>
+                        <description>Identifies whether the Security Extension is implemented</description>
+                        <bitRange>[7:4]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>ID_DFR0</name>
+                <addressOffset>0x0000ed48</addressOffset>
+                <description>Provides top level information about the debug system</description>
+                <resetValue>0x00200000</resetValue>
+                <fields>
+                    <field>
+                        <name>MPROFDBG</name>
+                        <description>Indicates the supported M-profile debug architecture</description>
+                        <bitRange>[23:20]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>ID_AFR0</name>
+                <addressOffset>0x0000ed4c</addressOffset>
+                <description>Provides information about the IMPLEMENTATION DEFINED features of the PE</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>IMPDEF3</name>
+                        <description>IMPLEMENTATION DEFINED meaning</description>
+                        <bitRange>[15:12]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>IMPDEF2</name>
+                        <description>IMPLEMENTATION DEFINED meaning</description>
+                        <bitRange>[11:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>IMPDEF1</name>
+                        <description>IMPLEMENTATION DEFINED meaning</description>
+                        <bitRange>[7:4]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>IMPDEF0</name>
+                        <description>IMPLEMENTATION DEFINED meaning</description>
+                        <bitRange>[3:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>ID_MMFR0</name>
+                <addressOffset>0x0000ed50</addressOffset>
+                <description>Provides information about the implemented memory model and memory management support</description>
+                <resetValue>0x00101f40</resetValue>
+                <fields>
+                    <field>
+                        <name>AUXREG</name>
+                        <description>Indicates support for Auxiliary Control Registers</description>
+                        <bitRange>[23:20]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>TCM</name>
+                        <description>Indicates support for tightly coupled memories (TCMs)</description>
+                        <bitRange>[19:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SHARELVL</name>
+                        <description>Indicates the number of shareability levels implemented</description>
+                        <bitRange>[15:12]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OUTERSHR</name>
+                        <description>Indicates the outermost shareability domain implemented</description>
+                        <bitRange>[11:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>PMSA</name>
+                        <description>Indicates support for the protected memory system architecture (PMSA)</description>
+                        <bitRange>[7:4]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>ID_MMFR1</name>
+                <addressOffset>0x0000ed54</addressOffset>
+                <description>Provides information about the implemented memory model and memory management support</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>ID_MMFR1</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>ID_MMFR2</name>
+                <addressOffset>0x0000ed58</addressOffset>
+                <description>Provides information about the implemented memory model and memory management support</description>
+                <resetValue>0x01000000</resetValue>
+                <fields>
+                    <field>
+                        <name>WFISTALL</name>
+                        <description>Indicates the support for Wait For Interrupt (WFI) stalling</description>
+                        <bitRange>[27:24]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>ID_MMFR3</name>
+                <addressOffset>0x0000ed5c</addressOffset>
+                <description>Provides information about the implemented memory model and memory management support</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>BPMAINT</name>
+                        <description>Indicates the supported branch predictor maintenance</description>
+                        <bitRange>[11:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CMAINTSW</name>
+                        <description>Indicates the supported cache maintenance operations by set/way</description>
+                        <bitRange>[7:4]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CMAINTVA</name>
+                        <description>Indicates the supported cache maintenance operations by address</description>
+                        <bitRange>[3:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>ID_ISAR0</name>
+                <addressOffset>0x0000ed60</addressOffset>
+                <description>Provides information about the instruction set implemented by the PE</description>
+                <resetValue>0x08092300</resetValue>
+                <fields>
+                    <field>
+                        <name>DIVIDE</name>
+                        <description>Indicates the supported Divide instructions</description>
+                        <bitRange>[27:24]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>DEBUG</name>
+                        <description>Indicates the implemented Debug instructions</description>
+                        <bitRange>[23:20]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>COPROC</name>
+                        <description>Indicates the supported Coprocessor instructions</description>
+                        <bitRange>[19:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CMPBRANCH</name>
+                        <description>Indicates the supported combined Compare and Branch instructions</description>
+                        <bitRange>[15:12]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>BITFIELD</name>
+                        <description>Indicates the supported bit field instructions</description>
+                        <bitRange>[11:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>BITCOUNT</name>
+                        <description>Indicates the supported bit count instructions</description>
+                        <bitRange>[7:4]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>ID_ISAR1</name>
+                <addressOffset>0x0000ed64</addressOffset>
+                <description>Provides information about the instruction set implemented by the PE</description>
+                <resetValue>0x05725000</resetValue>
+                <fields>
+                    <field>
+                        <name>INTERWORK</name>
+                        <description>Indicates the implemented Interworking instructions</description>
+                        <bitRange>[27:24]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>IMMEDIATE</name>
+                        <description>Indicates the implemented for data-processing instructions with long immediates</description>
+                        <bitRange>[23:20]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>IFTHEN</name>
+                        <description>Indicates the implemented If-Then instructions</description>
+                        <bitRange>[19:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>EXTEND</name>
+                        <description>Indicates the implemented Extend instructions</description>
+                        <bitRange>[15:12]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>ID_ISAR2</name>
+                <addressOffset>0x0000ed68</addressOffset>
+                <description>Provides information about the instruction set implemented by the PE</description>
+                <resetValue>0x30173426</resetValue>
+                <fields>
+                    <field>
+                        <name>REVERSAL</name>
+                        <description>Indicates the implemented Reversal instructions</description>
+                        <bitRange>[31:28]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>MULTU</name>
+                        <description>Indicates the implemented advanced unsigned Multiply instructions</description>
+                        <bitRange>[23:20]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>MULTS</name>
+                        <description>Indicates the implemented advanced signed Multiply instructions</description>
+                        <bitRange>[19:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>MULT</name>
+                        <description>Indicates the implemented additional Multiply instructions</description>
+                        <bitRange>[15:12]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>MULTIACCESSINT</name>
+                        <description>Indicates the support for interruptible multi-access instructions</description>
+                        <bitRange>[11:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>MEMHINT</name>
+                        <description>Indicates the implemented Memory Hint instructions</description>
+                        <bitRange>[7:4]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>LOADSTORE</name>
+                        <description>Indicates the implemented additional load/store instructions</description>
+                        <bitRange>[3:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>ID_ISAR3</name>
+                <addressOffset>0x0000ed6c</addressOffset>
+                <description>Provides information about the instruction set implemented by the PE</description>
+                <resetValue>0x07895729</resetValue>
+                <fields>
+                    <field>
+                        <name>TRUENOP</name>
+                        <description>Indicates the implemented true NOP instructions</description>
+                        <bitRange>[27:24]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>T32COPY</name>
+                        <description>Indicates the support for T32 non flag-setting MOV instructions</description>
+                        <bitRange>[23:20]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>TABBRANCH</name>
+                        <description>Indicates the implemented Table Branch instructions</description>
+                        <bitRange>[19:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SYNCHPRIM</name>
+                        <description>Used in conjunction with ID_ISAR4.SynchPrim_frac to indicate the implemented Synchronization Primitive instructions</description>
+                        <bitRange>[15:12]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SVC</name>
+                        <description>Indicates the implemented SVC instructions</description>
+                        <bitRange>[11:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SIMD</name>
+                        <description>Indicates the implemented SIMD instructions</description>
+                        <bitRange>[7:4]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SATURATE</name>
+                        <description>Indicates the implemented saturating instructions</description>
+                        <bitRange>[3:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>ID_ISAR4</name>
+                <addressOffset>0x0000ed70</addressOffset>
+                <description>Provides information about the instruction set implemented by the PE</description>
+                <resetValue>0x01310132</resetValue>
+                <fields>
+                    <field>
+                        <name>PSR_M</name>
+                        <description>Indicates the implemented M profile instructions to modify the PSRs</description>
+                        <bitRange>[27:24]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SYNCPRIM_FRAC</name>
+                        <description>Used in conjunction with ID_ISAR3.SynchPrim to indicate the implemented Synchronization Primitive instructions</description>
+                        <bitRange>[23:20]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>BARRIER</name>
+                        <description>Indicates the implemented Barrier instructions</description>
+                        <bitRange>[19:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>WRITEBACK</name>
+                        <description>Indicates the support for writeback addressing modes</description>
+                        <bitRange>[11:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>WITHSHIFTS</name>
+                        <description>Indicates the support for writeback addressing modes</description>
+                        <bitRange>[7:4]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>UNPRIV</name>
+                        <description>Indicates the implemented unprivileged instructions</description>
+                        <bitRange>[3:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>ID_ISAR5</name>
+                <addressOffset>0x0000ed74</addressOffset>
+                <description>Provides information about the instruction set implemented by the PE</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>ID_ISAR5</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CTR</name>
+                <addressOffset>0x0000ed7c</addressOffset>
+                <description>Provides information about the architecture of the caches. CTR is RES0 if CLIDR is zero.</description>
+                <resetValue>0x8000c000</resetValue>
+                <fields>
+                    <field>
+                        <name>RES1</name>
+                        <description>Reserved, RES1</description>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CWG</name>
+                        <description>Log2 of the number of words of the maximum size of memory that can be overwritten as a result of the eviction of a cache entry that has had a memory location in it modified</description>
+                        <bitRange>[27:24]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>ERG</name>
+                        <description>Log2 of the number of words of the maximum size of the reservation granule that has been implemented for the Load-Exclusive and Store-Exclusive instructions</description>
+                        <bitRange>[23:20]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>DMINLINE</name>
+                        <description>Log2 of the number of words in the smallest cache line of all the data caches and unified caches that are controlled by the PE</description>
+                        <bitRange>[19:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>RES1_1</name>
+                        <description>Reserved, RES1</description>
+                        <bitRange>[15:14]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>IMINLINE</name>
+                        <description>Log2 of the number of words in the smallest cache line of all the instruction caches that are controlled by the PE</description>
+                        <bitRange>[3:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CPACR</name>
+                <addressOffset>0x0000ed88</addressOffset>
+                <description>Specifies the access privileges for coprocessors and the FP Extension</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CP11</name>
+                        <description>The value in this field is ignored. If the implementation does not include the FP Extension, this field is RAZ/WI. If the value of this bit is not programmed to the same value as the CP10 field, then the value is UNKNOWN</description>
+                        <bitRange>[23:22]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CP10</name>
+                        <description>Defines the access rights for the floating-point functionality</description>
+                        <bitRange>[21:20]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CP7</name>
+                        <description>Controls access privileges for coprocessor 7</description>
+                        <bitRange>[15:14]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CP6</name>
+                        <description>Controls access privileges for coprocessor 6</description>
+                        <bitRange>[13:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CP5</name>
+                        <description>Controls access privileges for coprocessor 5</description>
+                        <bitRange>[11:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CP4</name>
+                        <description>Controls access privileges for coprocessor 4</description>
+                        <bitRange>[9:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CP3</name>
+                        <description>Controls access privileges for coprocessor 3</description>
+                        <bitRange>[7:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CP2</name>
+                        <description>Controls access privileges for coprocessor 2</description>
+                        <bitRange>[5:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CP1</name>
+                        <description>Controls access privileges for coprocessor 1</description>
+                        <bitRange>[3:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CP0</name>
+                        <description>Controls access privileges for coprocessor 0</description>
+                        <bitRange>[1:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>NSACR</name>
+                <addressOffset>0x0000ed8c</addressOffset>
+                <description>Defines the Non-secure access permissions for both the FP Extension and coprocessors CP0 to CP7</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CP11</name>
+                        <description>Enables Non-secure access to the Floating-point Extension</description>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CP10</name>
+                        <description>Enables Non-secure access to the Floating-point Extension</description>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CP7</name>
+                        <description>Enables Non-secure access to coprocessor CP7</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CP6</name>
+                        <description>Enables Non-secure access to coprocessor CP6</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CP5</name>
+                        <description>Enables Non-secure access to coprocessor CP5</description>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CP4</name>
+                        <description>Enables Non-secure access to coprocessor CP4</description>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CP3</name>
+                        <description>Enables Non-secure access to coprocessor CP3</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CP2</name>
+                        <description>Enables Non-secure access to coprocessor CP2</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CP1</name>
+                        <description>Enables Non-secure access to coprocessor CP1</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CP0</name>
+                        <description>Enables Non-secure access to coprocessor CP0</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>MPU_TYPE</name>
+                <addressOffset>0x0000ed90</addressOffset>
+                <description>The MPU Type Register indicates how many regions the MPU `FTSSS supports</description>
+                <resetValue>0x00000800</resetValue>
+                <fields>
+                    <field>
+                        <name>DREGION</name>
+                        <description>Number of regions supported by the MPU</description>
+                        <bitRange>[15:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SEPARATE</name>
+                        <description>Indicates support for separate instructions and data address regions</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>MPU_CTRL</name>
+                <addressOffset>0x0000ed94</addressOffset>
+                <description>Enables the MPU and, when the MPU is enabled, controls whether the default memory map is enabled as a background region for privileged accesses, and whether the MPU is enabled for HardFaults, NMIs, and exception handlers when FAULTMASK is set to 1</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>PRIVDEFENA</name>
+                        <description>Controls whether the default memory map is enabled for privileged software</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>HFNMIENA</name>
+                        <description>Controls whether handlers executing with priority less than 0 access memory with the MPU enabled or disabled. This applies to HardFaults, NMIs, and exception handlers when FAULTMASK is set to 1</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ENABLE</name>
+                        <description>Enables the MPU</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>MPU_RNR</name>
+                <addressOffset>0x0000ed98</addressOffset>
+                <description>Selects the region currently accessed by MPU_RBAR and MPU_RLAR</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>REGION</name>
+                        <description>Indicates the memory region accessed by MPU_RBAR and MPU_RLAR</description>
+                        <bitRange>[2:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>MPU_RBAR</name>
+                <addressOffset>0x0000ed9c</addressOffset>
+                <description>Provides indirect read and write access to the base address of the currently selected MPU region `FTSSS</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>BASE</name>
+                        <description>Contains bits [31:5] of the lower inclusive limit of the selected MPU memory region. This value is zero extended to provide the base address to be checked against</description>
+                        <bitRange>[31:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SH</name>
+                        <description>Defines the Shareability domain of this region for Normal memory</description>
+                        <bitRange>[4:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>AP</name>
+                        <description>Defines the access permissions for this region</description>
+                        <bitRange>[2:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>XN</name>
+                        <description>Defines whether code can be executed from this region</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>MPU_RLAR</name>
+                <addressOffset>0x0000eda0</addressOffset>
+                <description>Provides indirect read and write access to the limit address of the currently selected MPU region `FTSSS</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>LIMIT</name>
+                        <description>Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region. This value is postfixed with 0x1F to provide the limit address to be checked against</description>
+                        <bitRange>[31:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ATTRINDX</name>
+                        <description>Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields</description>
+                        <bitRange>[3:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>EN</name>
+                        <description>Region enable</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>MPU_RBAR_A1</name>
+                <addressOffset>0x0000eda4</addressOffset>
+                <description>Provides indirect read and write access to the base address of the MPU region selected by MPU_RNR[7:2]:(1[1:0]) `FTSSS</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>BASE</name>
+                        <description>Contains bits [31:5] of the lower inclusive limit of the selected MPU memory region. This value is zero extended to provide the base address to be checked against</description>
+                        <bitRange>[31:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SH</name>
+                        <description>Defines the Shareability domain of this region for Normal memory</description>
+                        <bitRange>[4:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>AP</name>
+                        <description>Defines the access permissions for this region</description>
+                        <bitRange>[2:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>XN</name>
+                        <description>Defines whether code can be executed from this region</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>MPU_RLAR_A1</name>
+                <addressOffset>0x0000eda8</addressOffset>
+                <description>Provides indirect read and write access to the limit address of the currently selected MPU region selected by MPU_RNR[7:2]:(1[1:0]) `FTSSS</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>LIMIT</name>
+                        <description>Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region. This value is postfixed with 0x1F to provide the limit address to be checked against</description>
+                        <bitRange>[31:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ATTRINDX</name>
+                        <description>Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields</description>
+                        <bitRange>[3:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>EN</name>
+                        <description>Region enable</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>MPU_RBAR_A2</name>
+                <addressOffset>0x0000edac</addressOffset>
+                <description>Provides indirect read and write access to the base address of the MPU region selected by MPU_RNR[7:2]:(2[1:0]) `FTSSS</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>BASE</name>
+                        <description>Contains bits [31:5] of the lower inclusive limit of the selected MPU memory region. This value is zero extended to provide the base address to be checked against</description>
+                        <bitRange>[31:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SH</name>
+                        <description>Defines the Shareability domain of this region for Normal memory</description>
+                        <bitRange>[4:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>AP</name>
+                        <description>Defines the access permissions for this region</description>
+                        <bitRange>[2:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>XN</name>
+                        <description>Defines whether code can be executed from this region</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>MPU_RLAR_A2</name>
+                <addressOffset>0x0000edb0</addressOffset>
+                <description>Provides indirect read and write access to the limit address of the currently selected MPU region selected by MPU_RNR[7:2]:(2[1:0]) `FTSSS</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>LIMIT</name>
+                        <description>Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region. This value is postfixed with 0x1F to provide the limit address to be checked against</description>
+                        <bitRange>[31:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ATTRINDX</name>
+                        <description>Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields</description>
+                        <bitRange>[3:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>EN</name>
+                        <description>Region enable</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>MPU_RBAR_A3</name>
+                <addressOffset>0x0000edb4</addressOffset>
+                <description>Provides indirect read and write access to the base address of the MPU region selected by MPU_RNR[7:2]:(3[1:0]) `FTSSS</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>BASE</name>
+                        <description>Contains bits [31:5] of the lower inclusive limit of the selected MPU memory region. This value is zero extended to provide the base address to be checked against</description>
+                        <bitRange>[31:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SH</name>
+                        <description>Defines the Shareability domain of this region for Normal memory</description>
+                        <bitRange>[4:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>AP</name>
+                        <description>Defines the access permissions for this region</description>
+                        <bitRange>[2:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>XN</name>
+                        <description>Defines whether code can be executed from this region</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>MPU_RLAR_A3</name>
+                <addressOffset>0x0000edb8</addressOffset>
+                <description>Provides indirect read and write access to the limit address of the currently selected MPU region selected by MPU_RNR[7:2]:(3[1:0]) `FTSSS</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>LIMIT</name>
+                        <description>Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region. This value is postfixed with 0x1F to provide the limit address to be checked against</description>
+                        <bitRange>[31:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ATTRINDX</name>
+                        <description>Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields</description>
+                        <bitRange>[3:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>EN</name>
+                        <description>Region enable</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>MPU_MAIR0</name>
+                <addressOffset>0x0000edc0</addressOffset>
+                <description>Along with MPU_MAIR1, provides the memory attribute encodings corresponding to the AttrIndex values</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>ATTR3</name>
+                        <description>Memory attribute encoding for MPU regions with an AttrIndex of 3</description>
+                        <bitRange>[31:24]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ATTR2</name>
+                        <description>Memory attribute encoding for MPU regions with an AttrIndex of 2</description>
+                        <bitRange>[23:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ATTR1</name>
+                        <description>Memory attribute encoding for MPU regions with an AttrIndex of 1</description>
+                        <bitRange>[15:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ATTR0</name>
+                        <description>Memory attribute encoding for MPU regions with an AttrIndex of 0</description>
+                        <bitRange>[7:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>MPU_MAIR1</name>
+                <addressOffset>0x0000edc4</addressOffset>
+                <description>Along with MPU_MAIR0, provides the memory attribute encodings corresponding to the AttrIndex values</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>ATTR7</name>
+                        <description>Memory attribute encoding for MPU regions with an AttrIndex of 7</description>
+                        <bitRange>[31:24]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ATTR6</name>
+                        <description>Memory attribute encoding for MPU regions with an AttrIndex of 6</description>
+                        <bitRange>[23:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ATTR5</name>
+                        <description>Memory attribute encoding for MPU regions with an AttrIndex of 5</description>
+                        <bitRange>[15:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ATTR4</name>
+                        <description>Memory attribute encoding for MPU regions with an AttrIndex of 4</description>
+                        <bitRange>[7:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SAU_CTRL</name>
+                <addressOffset>0x0000edd0</addressOffset>
+                <description>Allows enabling of the Security Attribution Unit</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>ALLNS</name>
+                        <description>When SAU_CTRL.ENABLE is 0 this bit controls if the memory is marked as Non-secure or Secure</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ENABLE</name>
+                        <description>Enables the SAU</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SAU_TYPE</name>
+                <addressOffset>0x0000edd4</addressOffset>
+                <description>Indicates the number of regions implemented by the Security Attribution Unit</description>
+                <resetValue>0x00000008</resetValue>
+                <fields>
+                    <field>
+                        <name>SREGION</name>
+                        <description>The number of implemented SAU regions</description>
+                        <bitRange>[7:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SAU_RNR</name>
+                <addressOffset>0x0000edd8</addressOffset>
+                <description>Selects the region currently accessed by SAU_RBAR and SAU_RLAR</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>REGION</name>
+                        <description>Indicates the SAU region accessed by SAU_RBAR and SAU_RLAR</description>
+                        <bitRange>[7:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SAU_RBAR</name>
+                <addressOffset>0x0000eddc</addressOffset>
+                <description>Provides indirect read and write access to the base address of the currently selected SAU region</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>BADDR</name>
+                        <description>Holds bits [31:5] of the base address for the selected SAU region</description>
+                        <bitRange>[31:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SAU_RLAR</name>
+                <addressOffset>0x0000ede0</addressOffset>
+                <description>Provides indirect read and write access to the limit address of the currently selected SAU region</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>LADDR</name>
+                        <description>Holds bits [31:5] of the limit address for the selected SAU region</description>
+                        <bitRange>[31:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>NSC</name>
+                        <description>Controls whether Non-secure state is permitted to execute an SG instruction from this region</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ENABLE</name>
+                        <description>SAU region enable</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SFSR</name>
+                <addressOffset>0x0000ede4</addressOffset>
+                <description>Provides information about any security related faults</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>LSERR</name>
+                        <description>Sticky flag indicating that an error occurred during lazy state activation or deactivation</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SFARVALID</name>
+                        <description>This bit is set when the SFAR register contains a valid value. As with similar fields, such as BFSR.BFARVALID and MMFSR.MMARVALID, this bit can be cleared by other exceptions, such as BusFault</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LSPERR</name>
+                        <description>Stick flag indicating that an SAU or IDAU violation occurred during the lazy preservation of floating-point state</description>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INVTRAN</name>
+                        <description>Sticky flag indicating that an exception was raised due to a branch that was not flagged as being domain crossing causing a transition from Secure to Non-secure memory</description>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>AUVIOL</name>
+                        <description>Sticky flag indicating that an attempt was made to access parts of the address space that are marked as Secure with NS-Req for the transaction set to Non-secure. This bit is not set if the violation occurred during lazy state preservation. See LSPERR</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INVER</name>
+                        <description>This can be caused by EXC_RETURN.DCRS being set to 0 when returning from an exception in the Non-secure state, or by EXC_RETURN.ES being set to 1 when returning from an exception in the Non-secure state</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INVIS</name>
+                        <description>This bit is set if the integrity signature in an exception stack frame is found to be invalid during the unstacking operation</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INVEP</name>
+                        <description>This bit is set if a function call from the Non-secure state or exception targets a non-SG instruction in the Secure state. This bit is also set if the target address is a SG instruction, but there is no matching SAU/IDAU region with the NSC flag set</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SFAR</name>
+                <addressOffset>0x0000ede8</addressOffset>
+                <description>Shows the address of the memory location that caused a Security violation</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>ADDRESS</name>
+                        <description>The address of an access that caused a attribution unit violation. This field is only valid when SFSR.SFARVALID is set. This allows the actual flip flops associated with this register to be shared with other fault address registers. If an implementation chooses to share the storage in this way, care must be taken to not leak Secure address information to the Non-secure state. One way of achieving this is to share the SFAR register with the MMFAR_S register, which is not accessible to the Non-secure state</description>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>DHCSR</name>
+                <addressOffset>0x0000edf0</addressOffset>
+                <description>Controls halting debug</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>S_RESTART_ST</name>
+                        <description>Indicates the PE has processed a request to clear DHCSR.C_HALT to 0. That is, either a write to DHCSR that clears DHCSR.C_HALT from 1 to 0, or an External Restart Request</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>S_RESET_ST</name>
+                        <description>Indicates whether the PE has been reset since the last read of the DHCSR</description>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>S_RETIRE_ST</name>
+                        <description>Set to 1 every time the PE retires one of more instructions</description>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>S_SDE</name>
+                        <description>Indicates whether Secure invasive debug is allowed</description>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>S_LOCKUP</name>
+                        <description>Indicates whether the PE is in Lockup state</description>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>S_SLEEP</name>
+                        <description>Indicates whether the PE is sleeping</description>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>S_HALT</name>
+                        <description>Indicates whether the PE is in Debug state</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>S_REGRDY</name>
+                        <description>Handshake flag to transfers through the DCRDR</description>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>C_SNAPSTALL</name>
+                        <description>Allow imprecise entry to Debug state</description>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>C_MASKINTS</name>
+                        <description>When debug is enabled, the debugger can write to this bit to mask PendSV, SysTick and external configurable interrupts</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>C_STEP</name>
+                        <description>Enable single instruction step</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>C_HALT</name>
+                        <description>PE enter Debug state halt request</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>C_DEBUGEN</name>
+                        <description>Enable Halting debug</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>DCRSR</name>
+                <addressOffset>0x0000edf4</addressOffset>
+                <description>With the DCRDR, provides debug access to the general-purpose registers, special-purpose registers, and the FP extension registers. A write to the DCRSR specifies the register to transfer, whether the transfer is a read or write, and starts the transfer</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>REGWNR</name>
+                        <description>Specifies the access type for the transfer</description>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>REGSEL</name>
+                        <description>Specifies the general-purpose register, special-purpose register, or FP register to transfer</description>
+                        <bitRange>[6:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>DCRDR</name>
+                <addressOffset>0x0000edf8</addressOffset>
+                <description>With the DCRSR, provides debug access to the general-purpose registers, special-purpose registers, and the FP Extension registers. If the Main Extension is implemented, it can also be used for message passing between an external debugger and a debug agent running on the PE</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>DBGTMP</name>
+                        <description>Provides debug access for reading and writing the general-purpose registers, special-purpose registers, and Floating-point Extension registers</description>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>DEMCR</name>
+                <addressOffset>0x0000edfc</addressOffset>
+                <description>Manages vector catch behavior and DebugMonitor handling when debugging</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>TRCENA</name>
+                        <description>Global enable for all DWT and ITM features</description>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SDME</name>
+                        <description>Indicates whether the DebugMonitor targets the Secure or the Non-secure state and whether debug events are allowed in Secure state</description>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>MON_REQ</name>
+                        <description>DebugMonitor semaphore bit</description>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>MON_STEP</name>
+                        <description>Enable DebugMonitor stepping</description>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>MON_PEND</name>
+                        <description>Sets or clears the pending state of the DebugMonitor exception</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>MON_EN</name>
+                        <description>Enable the DebugMonitor exception</description>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>VC_SFERR</name>
+                        <description>SecureFault exception halting debug vector catch enable</description>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>VC_HARDERR</name>
+                        <description>HardFault exception halting debug vector catch enable</description>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>VC_INTERR</name>
+                        <description>Enable halting debug vector catch for faults during exception entry and return</description>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>VC_BUSERR</name>
+                        <description>BusFault exception halting debug vector catch enable</description>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>VC_STATERR</name>
+                        <description>Enable halting debug trap on a UsageFault exception caused by a state information error, for example an Undefined Instruction exception</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>VC_CHKERR</name>
+                        <description>Enable halting debug trap on a UsageFault exception caused by a checking error, for example an alignment check error</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>VC_NOCPERR</name>
+                        <description>Enable halting debug trap on a UsageFault caused by an access to a coprocessor</description>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>VC_MMERR</name>
+                        <description>Enable halting debug trap on a MemManage exception</description>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>VC_CORERESET</name>
+                        <description>Enable Reset Vector Catch. This causes a warm reset to halt a running system</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>DSCSR</name>
+                <addressOffset>0x0000ee08</addressOffset>
+                <description>Provides control and status information for Secure debug</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CDSKEY</name>
+                        <description>Writes to the CDS bit are ignored unless CDSKEY is concurrently written to zero</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CDS</name>
+                        <description>This field indicates the current Security state of the processor</description>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SBRSEL</name>
+                        <description>If SBRSELEN is 1 this bit selects whether the Non-secure or the Secure version of the memory-mapped Banked registers are accessible to the debugger</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SBRSELEN</name>
+                        <description>Controls whether the SBRSEL field or the current Security state of the processor selects which version of the memory-mapped Banked registers are accessed to the debugger</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>STIR</name>
+                <addressOffset>0x0000ef00</addressOffset>
+                <description>Provides a mechanism for software to generate an interrupt</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>INTID</name>
+                        <description>Indicates the interrupt to be pended. The value written is (ExceptionNumber - 16)</description>
+                        <bitRange>[8:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>FPCCR</name>
+                <addressOffset>0x0000ef34</addressOffset>
+                <description>Holds control data for the Floating-point extension</description>
+                <resetValue>0x20000472</resetValue>
+                <fields>
+                    <field>
+                        <name>ASPEN</name>
+                        <description>When this bit is set to 1, execution of a floating-point instruction sets the CONTROL.FPCA bit to 1</description>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LSPEN</name>
+                        <description>Enables lazy context save of floating-point state</description>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LSPENS</name>
+                        <description>This bit controls whether the LSPEN bit is writeable from the Non-secure state</description>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLRONRET</name>
+                        <description>Clear floating-point caller saved registers on exception return</description>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLRONRETS</name>
+                        <description>This bit controls whether the CLRONRET bit is writeable from the Non-secure state</description>
+                        <bitRange>[27:27]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>TS</name>
+                        <description>Treat floating-point registers as Secure enable</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>UFRDY</name>
+                        <description>Indicates whether the software executing when the PE allocated the floating-point stack frame was able to set the UsageFault exception to pending</description>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SPLIMVIOL</name>
+                        <description>This bit is banked between the Security states and indicates whether the floating-point context violates the stack pointer limit that was active when lazy state preservation was activated. SPLIMVIOL modifies the lazy floating-point state preservation behavior</description>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>MONRDY</name>
+                        <description>Indicates whether the software executing when the PE allocated the floating-point stack frame was able to set the DebugMonitor exception to pending</description>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SFRDY</name>
+                        <description>Indicates whether the software executing when the PE allocated the floating-point stack frame was able to set the SecureFault exception to pending. This bit is only present in the Secure version of the register, and behaves as RAZ/WI when accessed from the Non-secure state</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>BFRDY</name>
+                        <description>Indicates whether the software executing when the PE allocated the floating-point stack frame was able to set the BusFault exception to pending</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>MMRDY</name>
+                        <description>Indicates whether the software executing when the PE allocated the floating-point stack frame was able to set the MemManage exception to pending</description>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>HFRDY</name>
+                        <description>Indicates whether the software executing when the PE allocated the floating-point stack frame was able to set the HardFault exception to pending</description>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>THREAD</name>
+                        <description>Indicates the PE mode when it allocated the floating-point stack frame</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>S</name>
+                        <description>Security status of the floating-point context. This bit is only present in the Secure version of the register, and behaves as RAZ/WI when accessed from the Non-secure state. This bit is updated whenever lazy state preservation is activated, or when a floating-point instruction is executed</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>USER</name>
+                        <description>Indicates the privilege level of the software executing when the PE allocated the floating-point stack frame</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LSPACT</name>
+                        <description>Indicates whether lazy preservation of the floating-point state is active</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>FPCAR</name>
+                <addressOffset>0x0000ef38</addressOffset>
+                <description>Holds the location of the unpopulated floating-point register space allocated on an exception stack frame</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>ADDRESS</name>
+                        <description>The location of the unpopulated floating-point register space allocated on an exception stack frame</description>
+                        <bitRange>[31:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>FPDSCR</name>
+                <addressOffset>0x0000ef3c</addressOffset>
+                <description>Holds the default values for the floating-point status control data that the PE assigns to the FPSCR when it creates a new floating-point context</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>AHP</name>
+                        <description>Default value for FPSCR.AHP</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DN</name>
+                        <description>Default value for FPSCR.DN</description>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>FZ</name>
+                        <description>Default value for FPSCR.FZ</description>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>RMODE</name>
+                        <description>Default value for FPSCR.RMode</description>
+                        <bitRange>[23:22]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>MVFR0</name>
+                <addressOffset>0x0000ef40</addressOffset>
+                <description>Describes the features provided by the Floating-point Extension</description>
+                <resetValue>0x60540601</resetValue>
+                <fields>
+                    <field>
+                        <name>FPROUND</name>
+                        <description>Indicates the rounding modes supported by the FP Extension</description>
+                        <bitRange>[31:28]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>FPSQRT</name>
+                        <description>Indicates the support for FP square root operations</description>
+                        <bitRange>[23:20]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>FPDIVIDE</name>
+                        <description>Indicates the support for FP divide operations</description>
+                        <bitRange>[19:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>FPDP</name>
+                        <description>Indicates support for FP double-precision operations</description>
+                        <bitRange>[11:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>FPSP</name>
+                        <description>Indicates support for FP single-precision operations</description>
+                        <bitRange>[7:4]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SIMDREG</name>
+                        <description>Indicates size of FP register file</description>
+                        <bitRange>[3:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>MVFR1</name>
+                <addressOffset>0x0000ef44</addressOffset>
+                <description>Describes the features provided by the Floating-point Extension</description>
+                <resetValue>0x85000089</resetValue>
+                <fields>
+                    <field>
+                        <name>FMAC</name>
+                        <description>Indicates whether the FP Extension implements the fused multiply accumulate instructions</description>
+                        <bitRange>[31:28]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>FPHP</name>
+                        <description>Indicates whether the FP Extension implements half-precision FP conversion instructions</description>
+                        <bitRange>[27:24]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>FPDNAN</name>
+                        <description>Indicates whether the FP hardware implementation supports NaN propagation</description>
+                        <bitRange>[7:4]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>FPFTZ</name>
+                        <description>Indicates whether subnormals are always flushed-to-zero</description>
+                        <bitRange>[3:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>MVFR2</name>
+                <addressOffset>0x0000ef48</addressOffset>
+                <description>Describes the features provided by the Floating-point Extension</description>
+                <resetValue>0x00000060</resetValue>
+                <fields>
+                    <field>
+                        <name>FPMISC</name>
+                        <description>Indicates support for miscellaneous FP features</description>
+                        <bitRange>[7:4]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>DDEVARCH</name>
+                <addressOffset>0x0000efbc</addressOffset>
+                <description>Provides CoreSight discovery information for the SCS</description>
+                <resetValue>0x47702a04</resetValue>
+                <fields>
+                    <field>
+                        <name>ARCHITECT</name>
+                        <description>Defines the architect of the component. Bits [31:28] are the JEP106 continuation code (JEP106 bank ID, minus 1) and bits [27:21] are the JEP106 ID code.</description>
+                        <bitRange>[31:21]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>PRESENT</name>
+                        <description>Defines that the DEVARCH register is present</description>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>REVISION</name>
+                        <description>Defines the architecture revision of the component</description>
+                        <bitRange>[19:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>ARCHVER</name>
+                        <description>Defines the architecture version of the component</description>
+                        <bitRange>[15:12]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>ARCHPART</name>
+                        <description>Defines the architecture of the component</description>
+                        <bitRange>[11:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>DDEVTYPE</name>
+                <addressOffset>0x0000efcc</addressOffset>
+                <description>Provides CoreSight discovery information for the SCS</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>SUB</name>
+                        <description>Component sub-type</description>
+                        <bitRange>[7:4]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>MAJOR</name>
+                        <description>CoreSight major type</description>
+                        <bitRange>[3:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>DPIDR4</name>
+                <addressOffset>0x0000efd0</addressOffset>
+                <description>Provides CoreSight discovery information for the SCS</description>
+                <resetValue>0x00000004</resetValue>
+                <fields>
+                    <field>
+                        <name>SIZE</name>
+                        <description>See CoreSight Architecture Specification</description>
+                        <bitRange>[7:4]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>DES_2</name>
+                        <description>See CoreSight Architecture Specification</description>
+                        <bitRange>[3:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>DPIDR5</name>
+                <addressOffset>0x0000efd4</addressOffset>
+                <description>Provides CoreSight discovery information for the SCS</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>DPIDR5</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>DPIDR6</name>
+                <addressOffset>0x0000efd8</addressOffset>
+                <description>Provides CoreSight discovery information for the SCS</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>DPIDR6</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>DPIDR7</name>
+                <addressOffset>0x0000efdc</addressOffset>
+                <description>Provides CoreSight discovery information for the SCS</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>DPIDR7</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>DPIDR0</name>
+                <addressOffset>0x0000efe0</addressOffset>
+                <description>Provides CoreSight discovery information for the SCS</description>
+                <resetValue>0x00000021</resetValue>
+                <fields>
+                    <field>
+                        <name>PART_0</name>
+                        <description>See CoreSight Architecture Specification</description>
+                        <bitRange>[7:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>DPIDR1</name>
+                <addressOffset>0x0000efe4</addressOffset>
+                <description>Provides CoreSight discovery information for the SCS</description>
+                <resetValue>0x000000bd</resetValue>
+                <fields>
+                    <field>
+                        <name>DES_0</name>
+                        <description>See CoreSight Architecture Specification</description>
+                        <bitRange>[7:4]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>PART_1</name>
+                        <description>See CoreSight Architecture Specification</description>
+                        <bitRange>[3:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>DPIDR2</name>
+                <addressOffset>0x0000efe8</addressOffset>
+                <description>Provides CoreSight discovery information for the SCS</description>
+                <resetValue>0x0000000b</resetValue>
+                <fields>
+                    <field>
+                        <name>REVISION</name>
+                        <description>See CoreSight Architecture Specification</description>
+                        <bitRange>[7:4]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>JEDEC</name>
+                        <description>See CoreSight Architecture Specification</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>DES_1</name>
+                        <description>See CoreSight Architecture Specification</description>
+                        <bitRange>[2:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>DPIDR3</name>
+                <addressOffset>0x0000efec</addressOffset>
+                <description>Provides CoreSight discovery information for the SCS</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>REVAND</name>
+                        <description>See CoreSight Architecture Specification</description>
+                        <bitRange>[7:4]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CMOD</name>
+                        <description>See CoreSight Architecture Specification</description>
+                        <bitRange>[3:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>DCIDR0</name>
+                <addressOffset>0x0000eff0</addressOffset>
+                <description>Provides CoreSight discovery information for the SCS</description>
+                <resetValue>0x0000000d</resetValue>
+                <fields>
+                    <field>
+                        <name>PRMBL_0</name>
+                        <description>See CoreSight Architecture Specification</description>
+                        <bitRange>[7:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>DCIDR1</name>
+                <addressOffset>0x0000eff4</addressOffset>
+                <description>Provides CoreSight discovery information for the SCS</description>
+                <resetValue>0x00000090</resetValue>
+                <fields>
+                    <field>
+                        <name>CLASS</name>
+                        <description>See CoreSight Architecture Specification</description>
+                        <bitRange>[7:4]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>PRMBL_1</name>
+                        <description>See CoreSight Architecture Specification</description>
+                        <bitRange>[3:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>DCIDR2</name>
+                <addressOffset>0x0000eff8</addressOffset>
+                <description>Provides CoreSight discovery information for the SCS</description>
+                <resetValue>0x00000005</resetValue>
+                <fields>
+                    <field>
+                        <name>PRMBL_2</name>
+                        <description>See CoreSight Architecture Specification</description>
+                        <bitRange>[7:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>DCIDR3</name>
+                <addressOffset>0x0000effc</addressOffset>
+                <description>Provides CoreSight discovery information for the SCS</description>
+                <resetValue>0x000000b1</resetValue>
+                <fields>
+                    <field>
+                        <name>PRMBL_3</name>
+                        <description>See CoreSight Architecture Specification</description>
+                        <bitRange>[7:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>TRCPRGCTLR</name>
+                <addressOffset>0x00041004</addressOffset>
+                <description>Programming Control Register</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>EN</name>
+                        <description>Trace Unit Enable</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>TRCSTATR</name>
+                <addressOffset>0x0004100c</addressOffset>
+                <description>The TRCSTATR indicates the ETM-Teal status</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>PMSTABLE</name>
+                        <description>Indicates whether the ETM-Teal registers are stable and can be read</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>IDLE</name>
+                        <description>Indicates that the trace unit is inactive</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>TRCCONFIGR</name>
+                <addressOffset>0x00041010</addressOffset>
+                <description>The TRCCONFIGR sets the basic tracing options for the trace unit</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>RS</name>
+                        <description>Return stack enable</description>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>TS</name>
+                        <description>Global timestamp tracing</description>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>COND</name>
+                        <description>Conditional instruction tracing</description>
+                        <bitRange>[10:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CCI</name>
+                        <description>Cycle counting in instruction trace</description>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>BB</name>
+                        <description>Branch broadcast mode</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>TRCEVENTCTL0R</name>
+                <addressOffset>0x00041020</addressOffset>
+                <description>The TRCEVENTCTL0R controls the tracing of events in the trace stream. The events also drive the ETM-Teal external outputs.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>TYPE1</name>
+                        <description>Selects the resource type for event 1</description>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SEL1</name>
+                        <description>Selects the resource number, based on the value of TYPE1: When TYPE1 is 0, selects a single selected resource from 0-15 defined by SEL1[2:0].  When TYPE1 is 1, selects a Boolean combined resource pair from 0-7 defined by SEL1[2:0]</description>
+                        <bitRange>[10:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>TYPE0</name>
+                        <description>Selects the resource type for event 0</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SEL0</name>
+                        <description>Selects the resource number, based on the value of TYPE0: When TYPE1 is 0, selects a single selected resource from 0-15 defined by SEL0[2:0].  When TYPE1 is 1, selects a Boolean combined resource pair from 0-7 defined by SEL0[2:0]</description>
+                        <bitRange>[2:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>TRCEVENTCTL1R</name>
+                <addressOffset>0x00041024</addressOffset>
+                <description>The TRCEVENTCTL1R controls how the events selected by TRCEVENTCTL0R behave</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>LPOVERRIDE</name>
+                        <description>Low power state behavior override</description>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ATB</name>
+                        <description>ATB enabled</description>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INSTEN1</name>
+                        <description>One bit per event, to enable generation of an event element in the instruction trace stream when the selected event occurs</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INSTEN0</name>
+                        <description>One bit per event, to enable generation of an event element in the instruction trace stream when the selected event occurs</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>TRCSTALLCTLR</name>
+                <addressOffset>0x0004102c</addressOffset>
+                <description>The TRCSTALLCTLR enables ETM-Teal to stall the processor if the ETM-Teal FIFO goes over the programmed level to minimize risk of overflow</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>INSTPRIORITY</name>
+                        <description>Reserved, RES0</description>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>ISTALL</name>
+                        <description>Stall processor based on instruction trace buffer space</description>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LEVEL</name>
+                        <description>Threshold at which stalling becomes active. This provides four levels. This level can be varied to optimize the level of invasion caused by stalling, balanced against the risk of a FIFO overflow</description>
+                        <bitRange>[3:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>TRCTSCTLR</name>
+                <addressOffset>0x00041030</addressOffset>
+                <description>The TRCTSCTLR controls the insertion of global timestamps into the trace stream. A timestamp is always inserted into the instruction trace stream</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>TYPE0</name>
+                        <description>Selects the resource type for event 0</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SEL0</name>
+                        <description>Selects the resource number, based on the value of TYPE0: When TYPE1 is 0, selects a single selected resource from 0-15 defined by SEL0[2:0].  When TYPE1 is 1, selects a Boolean combined resource pair from 0-7 defined by SEL0[2:0]</description>
+                        <bitRange>[1:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>TRCSYNCPR</name>
+                <addressOffset>0x00041034</addressOffset>
+                <description>The TRCSYNCPR specifies the period of trace synchronization of the trace streams. TRCSYNCPR defines a number of bytes of trace between requests for trace synchronization. This value is always a power of two</description>
+                <resetValue>0x0000000a</resetValue>
+                <fields>
+                    <field>
+                        <name>PERIOD</name>
+                        <description>Defines the number of bytes of trace between trace synchronization requests as a total of the number of bytes generated by the instruction stream. The number of bytes is 2N where N is the value of this field: - A value of zero disables these periodic trace synchronization requests, but does not disable other trace synchronization requests.  - The minimum value that can be programmed, other than zero, is 8, providing a minimum trace synchronization period of 256 bytes.  - The maximum value is 20, providing a maximum trace synchronization period of 2^20 bytes</description>
+                        <bitRange>[4:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>TRCCCCTLR</name>
+                <addressOffset>0x00041038</addressOffset>
+                <description>The TRCCCCTLR sets the threshold value for instruction trace cycle counting. The threshold represents the minimum interval between cycle count trace packets</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>THRESHOLD</name>
+                        <description>Instruction trace cycle count threshold</description>
+                        <bitRange>[11:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>TRCVICTLR</name>
+                <addressOffset>0x00041080</addressOffset>
+                <description>The TRCVICTLR controls instruction trace filtering</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>EXLEVEL_S3</name>
+                        <description>In Secure state, each bit controls whether instruction tracing is enabled for the corresponding exception level</description>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>EXLEVEL_S0</name>
+                        <description>In Secure state, each bit controls whether instruction tracing is enabled for the corresponding exception level</description>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>TRCERR</name>
+                        <description>Selects whether a system error exception must always be traced</description>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>TRCRESET</name>
+                        <description>Selects whether a reset exception must always be traced</description>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SSSTATUS</name>
+                        <description>Indicates the current status of the start/stop logic</description>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>TYPE0</name>
+                        <description>Selects the resource type for event 0</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SEL0</name>
+                        <description>Selects the resource number, based on the value of TYPE0: When TYPE1 is 0, selects a single selected resource from 0-15 defined by SEL0[2:0].  When TYPE1 is 1, selects a Boolean combined resource pair from 0-7 defined by SEL0[2:0]</description>
+                        <bitRange>[1:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>TRCCNTRLDVR0</name>
+                <addressOffset>0x00041140</addressOffset>
+                <description>The TRCCNTRLDVR defines the reload value for the reduced function counter</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>VALUE</name>
+                        <description>Defines the reload value for the counter. This value is loaded into the counter each time the reload event occurs</description>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>TRCIDR8</name>
+                <addressOffset>0x00041180</addressOffset>
+                <description>TRCIDR8</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>MAXSPEC</name>
+                        <description>reads as `ImpDef</description>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>TRCIDR9</name>
+                <addressOffset>0x00041184</addressOffset>
+                <description>TRCIDR9</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>NUMP0KEY</name>
+                        <description>reads as `ImpDef</description>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>TRCIDR10</name>
+                <addressOffset>0x00041188</addressOffset>
+                <description>TRCIDR10</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>NUMP1KEY</name>
+                        <description>reads as `ImpDef</description>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>TRCIDR11</name>
+                <addressOffset>0x0004118c</addressOffset>
+                <description>TRCIDR11</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>NUMP1SPC</name>
+                        <description>reads as `ImpDef</description>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>TRCIDR12</name>
+                <addressOffset>0x00041190</addressOffset>
+                <description>TRCIDR12</description>
+                <resetValue>0x00000001</resetValue>
+                <fields>
+                    <field>
+                        <name>NUMCONDKEY</name>
+                        <description>reads as `ImpDef</description>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>TRCIDR13</name>
+                <addressOffset>0x00041194</addressOffset>
+                <description>TRCIDR13</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>NUMCONDSPC</name>
+                        <description>reads as `ImpDef</description>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>TRCIMSPEC</name>
+                <addressOffset>0x000411c0</addressOffset>
+                <description>The TRCIMSPEC shows the presence of any IMPLEMENTATION SPECIFIC features, and enables any features that are provided</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>SUPPORT</name>
+                        <description>Reserved, RES0</description>
+                        <bitRange>[3:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>TRCIDR0</name>
+                <addressOffset>0x000411e0</addressOffset>
+                <description>TRCIDR0</description>
+                <resetValue>0x280006e1</resetValue>
+                <fields>
+                    <field>
+                        <name>COMMOPT</name>
+                        <description>reads as `ImpDef</description>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>TSSIZE</name>
+                        <description>reads as `ImpDef</description>
+                        <bitRange>[28:24]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>TRCEXDATA</name>
+                        <description>reads as `ImpDef</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>QSUPP</name>
+                        <description>reads as `ImpDef</description>
+                        <bitRange>[16:15]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>QFILT</name>
+                        <description>reads as `ImpDef</description>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CONDTYPE</name>
+                        <description>reads as `ImpDef</description>
+                        <bitRange>[13:12]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>NUMEVENT</name>
+                        <description>reads as `ImpDef</description>
+                        <bitRange>[11:10]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>RETSTACK</name>
+                        <description>reads as `ImpDef</description>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>TRCCCI</name>
+                        <description>reads as `ImpDef</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>TRCCOND</name>
+                        <description>reads as `ImpDef</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>TRCBB</name>
+                        <description>reads as `ImpDef</description>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>TRCDATA</name>
+                        <description>reads as `ImpDef</description>
+                        <bitRange>[4:3]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>INSTP0</name>
+                        <description>reads as `ImpDef</description>
+                        <bitRange>[2:1]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>RES1</name>
+                        <description>Reserved, RES1</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>TRCIDR1</name>
+                <addressOffset>0x000411e4</addressOffset>
+                <description>TRCIDR1</description>
+                <resetValue>0x4100f421</resetValue>
+                <fields>
+                    <field>
+                        <name>DESIGNER</name>
+                        <description>reads as `ImpDef</description>
+                        <bitRange>[31:24]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>RES1</name>
+                        <description>Reserved, RES1</description>
+                        <bitRange>[15:12]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>TRCARCHMAJ</name>
+                        <description>reads as 0b0100</description>
+                        <bitRange>[11:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>TRCARCHMIN</name>
+                        <description>reads as 0b0000</description>
+                        <bitRange>[7:4]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>REVISION</name>
+                        <description>reads as `ImpDef</description>
+                        <bitRange>[3:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>TRCIDR2</name>
+                <addressOffset>0x000411e8</addressOffset>
+                <description>TRCIDR2</description>
+                <resetValue>0x00000004</resetValue>
+                <fields>
+                    <field>
+                        <name>CCSIZE</name>
+                        <description>reads as `ImpDef</description>
+                        <bitRange>[28:25]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>DVSIZE</name>
+                        <description>reads as `ImpDef</description>
+                        <bitRange>[24:20]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>DASIZE</name>
+                        <description>reads as `ImpDef</description>
+                        <bitRange>[19:15]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>VMIDSIZE</name>
+                        <description>reads as `ImpDef</description>
+                        <bitRange>[14:10]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CIDSIZE</name>
+                        <description>reads as `ImpDef</description>
+                        <bitRange>[9:5]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>IASIZE</name>
+                        <description>reads as `ImpDef</description>
+                        <bitRange>[4:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>TRCIDR3</name>
+                <addressOffset>0x000411ec</addressOffset>
+                <description>TRCIDR3</description>
+                <resetValue>0x0f090004</resetValue>
+                <fields>
+                    <field>
+                        <name>NOOVERFLOW</name>
+                        <description>reads as `ImpDef</description>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>NUMPROC</name>
+                        <description>reads as `ImpDef</description>
+                        <bitRange>[30:28]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SYSSTALL</name>
+                        <description>reads as `ImpDef</description>
+                        <bitRange>[27:27]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>STALLCTL</name>
+                        <description>reads as `ImpDef</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SYNCPR</name>
+                        <description>reads as `ImpDef</description>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>TRCERR</name>
+                        <description>reads as `ImpDef</description>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>EXLEVEL_NS</name>
+                        <description>reads as `ImpDef</description>
+                        <bitRange>[23:20]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>EXLEVEL_S</name>
+                        <description>reads as `ImpDef</description>
+                        <bitRange>[19:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CCITMIN</name>
+                        <description>reads as `ImpDef</description>
+                        <bitRange>[11:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>TRCIDR4</name>
+                <addressOffset>0x000411f0</addressOffset>
+                <description>TRCIDR4</description>
+                <resetValue>0x00114000</resetValue>
+                <fields>
+                    <field>
+                        <name>NUMVMIDC</name>
+                        <description>reads as `ImpDef</description>
+                        <bitRange>[31:28]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>NUMCIDC</name>
+                        <description>reads as `ImpDef</description>
+                        <bitRange>[27:24]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>NUMSSCC</name>
+                        <description>reads as `ImpDef</description>
+                        <bitRange>[23:20]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>NUMRSPAIR</name>
+                        <description>reads as `ImpDef</description>
+                        <bitRange>[19:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>NUMPC</name>
+                        <description>reads as `ImpDef</description>
+                        <bitRange>[15:12]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SUPPDAC</name>
+                        <description>reads as `ImpDef</description>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>NUMDVC</name>
+                        <description>reads as `ImpDef</description>
+                        <bitRange>[7:4]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>NUMACPAIRS</name>
+                        <description>reads as `ImpDef</description>
+                        <bitRange>[3:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>TRCIDR5</name>
+                <addressOffset>0x000411f4</addressOffset>
+                <description>TRCIDR5</description>
+                <resetValue>0x90c70004</resetValue>
+                <fields>
+                    <field>
+                        <name>REDFUNCNTR</name>
+                        <description>reads as `ImpDef</description>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>NUMCNTR</name>
+                        <description>reads as `ImpDef</description>
+                        <bitRange>[30:28]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>NUMSEQSTATE</name>
+                        <description>reads as `ImpDef</description>
+                        <bitRange>[27:25]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>LPOVERRIDE</name>
+                        <description>reads as `ImpDef</description>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>ATBTRIG</name>
+                        <description>reads as `ImpDef</description>
+                        <bitRange>[22:22]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>TRACEIDSIZE</name>
+                        <description>reads as 0x07</description>
+                        <bitRange>[21:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>NUMEXTINSEL</name>
+                        <description>reads as `ImpDef</description>
+                        <bitRange>[11:9]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>NUMEXTIN</name>
+                        <description>reads as `ImpDef</description>
+                        <bitRange>[8:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>TRCIDR6</name>
+                <addressOffset>0x000411f8</addressOffset>
+                <description>TRCIDR6</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>TRCIDR6</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>TRCIDR7</name>
+                <addressOffset>0x000411fc</addressOffset>
+                <description>TRCIDR7</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>TRCIDR7</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>TRCRSCTLR2</name>
+                <addressOffset>0x00041208</addressOffset>
+                <description>The TRCRSCTLR controls the trace resources</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>PAIRINV</name>
+                        <description>Inverts the result of a combined pair of resources.  This bit is only implemented on the lower register for a pair of resource selectors</description>
+                        <bitRange>[21:21]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INV</name>
+                        <description>Inverts the selected resources</description>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GROUP</name>
+                        <description>Selects a group of resource</description>
+                        <bitRange>[18:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SELECT</name>
+                        <description>Selects one or more resources from the wanted group. One bit is provided per resource from the group</description>
+                        <bitRange>[7:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>TRCRSCTLR3</name>
+                <addressOffset>0x0004120c</addressOffset>
+                <description>The TRCRSCTLR controls the trace resources</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>PAIRINV</name>
+                        <description>Inverts the result of a combined pair of resources.  This bit is only implemented on the lower register for a pair of resource selectors</description>
+                        <bitRange>[21:21]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INV</name>
+                        <description>Inverts the selected resources</description>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GROUP</name>
+                        <description>Selects a group of resource</description>
+                        <bitRange>[18:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SELECT</name>
+                        <description>Selects one or more resources from the wanted group. One bit is provided per resource from the group</description>
+                        <bitRange>[7:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>TRCSSCSR</name>
+                <addressOffset>0x000412a0</addressOffset>
+                <description>Controls the corresponding single-shot comparator resource</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>STATUS</name>
+                        <description>Single-shot status bit. Indicates if any of the comparators, that TRCSSCCRn.SAC or TRCSSCCRn.ARC selects, have matched</description>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PC</name>
+                        <description>Reserved, RES1</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>DV</name>
+                        <description>Reserved, RES0</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>DA</name>
+                        <description>Reserved, RES0</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>INST</name>
+                        <description>Reserved, RES0</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>TRCSSPCICR</name>
+                <addressOffset>0x000412c0</addressOffset>
+                <description>Selects the PE comparator inputs for Single-shot control</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>PC</name>
+                        <description>Selects one or more PE comparator inputs for Single-shot control.  TRCIDR4.NUMPC defines the size of the PC field.  1 bit is provided for each implemented PE comparator input.  For example, if bit[1] == 1 this selects PE comparator input 1 for Single-shot control</description>
+                        <bitRange>[3:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>TRCPDCR</name>
+                <addressOffset>0x00041310</addressOffset>
+                <description>Requests the system to provide power to the trace unit</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>PU</name>
+                        <description>Powerup request bit:</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>TRCPDSR</name>
+                <addressOffset>0x00041314</addressOffset>
+                <description>Returns the following information about the trace unit: - OS Lock status.  - Core power domain status.  - Power interruption status</description>
+                <resetValue>0x00000003</resetValue>
+                <fields>
+                    <field>
+                        <name>OSLK</name>
+                        <description>OS Lock status bit:</description>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>STICKYPD</name>
+                        <description>Sticky powerdown status bit. Indicates whether the trace register state is valid:</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>POWER</name>
+                        <description>Power status bit:</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>TRCITATBIDR</name>
+                <addressOffset>0x00041ee4</addressOffset>
+                <description>Trace Integration ATB Identification Register</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>ID</name>
+                        <description>Trace ID</description>
+                        <bitRange>[6:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>TRCITIATBINR</name>
+                <addressOffset>0x00041ef4</addressOffset>
+                <description>Trace Integration Instruction ATB In Register</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>AFVALIDM</name>
+                        <description>Integration Mode instruction AFVALIDM in</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ATREADYM</name>
+                        <description>Integration Mode instruction ATREADYM in</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>TRCITIATBOUTR</name>
+                <addressOffset>0x00041efc</addressOffset>
+                <description>Trace Integration Instruction ATB Out Register</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>AFREADY</name>
+                        <description>Integration Mode instruction AFREADY out</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ATVALID</name>
+                        <description>Integration Mode instruction ATVALID out</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>TRCCLAIMSET</name>
+                <addressOffset>0x00041fa0</addressOffset>
+                <description>Claim Tag Set Register</description>
+                <resetValue>0x0000000f</resetValue>
+                <fields>
+                    <field>
+                        <name>SET3</name>
+                        <description>When a write to one of these bits occurs, with the value:</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SET2</name>
+                        <description>When a write to one of these bits occurs, with the value:</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SET1</name>
+                        <description>When a write to one of these bits occurs, with the value:</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SET0</name>
+                        <description>When a write to one of these bits occurs, with the value:</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>TRCCLAIMCLR</name>
+                <addressOffset>0x00041fa4</addressOffset>
+                <description>Claim Tag Clear Register</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CLR3</name>
+                        <description>When a write to one of these bits occurs, with the value:</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLR2</name>
+                        <description>When a write to one of these bits occurs, with the value:</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLR1</name>
+                        <description>When a write to one of these bits occurs, with the value:</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLR0</name>
+                        <description>When a write to one of these bits occurs, with the value:</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>TRCAUTHSTATUS</name>
+                <addressOffset>0x00041fb8</addressOffset>
+                <description>Returns the level of tracing that the trace unit can support</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>SNID</name>
+                        <description>Indicates whether the system enables the trace unit to support Secure non-invasive debug:</description>
+                        <bitRange>[7:6]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SID</name>
+                        <description>Indicates whether the trace unit supports Secure invasive debug:</description>
+                        <bitRange>[5:4]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>NSNID</name>
+                        <description>Indicates whether the system enables the trace unit to support Non-secure non-invasive debug:</description>
+                        <bitRange>[3:2]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>NSID</name>
+                        <description>Indicates whether the trace unit supports Non-secure invasive debug:</description>
+                        <bitRange>[1:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>TRCDEVARCH</name>
+                <addressOffset>0x00041fbc</addressOffset>
+                <description>TRCDEVARCH</description>
+                <resetValue>0x47724a13</resetValue>
+                <fields>
+                    <field>
+                        <name>ARCHITECT</name>
+                        <description>reads as 0b01000111011</description>
+                        <bitRange>[31:21]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>PRESENT</name>
+                        <description>reads as 0b1</description>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>REVISION</name>
+                        <description>reads as 0b0000</description>
+                        <bitRange>[19:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>ARCHID</name>
+                        <description>reads as 0b0100101000010011</description>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>TRCDEVID</name>
+                <addressOffset>0x00041fc8</addressOffset>
+                <description>TRCDEVID</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>TRCDEVID</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>TRCDEVTYPE</name>
+                <addressOffset>0x00041fcc</addressOffset>
+                <description>TRCDEVTYPE</description>
+                <resetValue>0x00000013</resetValue>
+                <fields>
+                    <field>
+                        <name>SUB</name>
+                        <description>reads as 0b0001</description>
+                        <bitRange>[7:4]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>MAJOR</name>
+                        <description>reads as 0b0011</description>
+                        <bitRange>[3:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>TRCPIDR4</name>
+                <addressOffset>0x00041fd0</addressOffset>
+                <description>TRCPIDR4</description>
+                <resetValue>0x00000004</resetValue>
+                <fields>
+                    <field>
+                        <name>SIZE</name>
+                        <description>reads as `ImpDef</description>
+                        <bitRange>[7:4]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>DES_2</name>
+                        <description>reads as `ImpDef</description>
+                        <bitRange>[3:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>TRCPIDR5</name>
+                <addressOffset>0x00041fd4</addressOffset>
+                <description>TRCPIDR5</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>TRCPIDR5</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>TRCPIDR6</name>
+                <addressOffset>0x00041fd8</addressOffset>
+                <description>TRCPIDR6</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>TRCPIDR6</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>TRCPIDR7</name>
+                <addressOffset>0x00041fdc</addressOffset>
+                <description>TRCPIDR7</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>TRCPIDR7</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>TRCPIDR0</name>
+                <addressOffset>0x00041fe0</addressOffset>
+                <description>TRCPIDR0</description>
+                <resetValue>0x00000021</resetValue>
+                <fields>
+                    <field>
+                        <name>PART_0</name>
+                        <description>reads as `ImpDef</description>
+                        <bitRange>[7:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>TRCPIDR1</name>
+                <addressOffset>0x00041fe4</addressOffset>
+                <description>TRCPIDR1</description>
+                <resetValue>0x000000bd</resetValue>
+                <fields>
+                    <field>
+                        <name>DES_0</name>
+                        <description>reads as `ImpDef</description>
+                        <bitRange>[7:4]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>PART_0</name>
+                        <description>reads as `ImpDef</description>
+                        <bitRange>[3:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>TRCPIDR2</name>
+                <addressOffset>0x00041fe8</addressOffset>
+                <description>TRCPIDR2</description>
+                <resetValue>0x0000002b</resetValue>
+                <fields>
+                    <field>
+                        <name>REVISION</name>
+                        <description>reads as `ImpDef</description>
+                        <bitRange>[7:4]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>JEDEC</name>
+                        <description>reads as 0b1</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>DES_0</name>
+                        <description>reads as `ImpDef</description>
+                        <bitRange>[2:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>TRCPIDR3</name>
+                <addressOffset>0x00041fec</addressOffset>
+                <description>TRCPIDR3</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>REVAND</name>
+                        <description>reads as `ImpDef</description>
+                        <bitRange>[7:4]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CMOD</name>
+                        <description>reads as `ImpDef</description>
+                        <bitRange>[3:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>TRCCIDR0</name>
+                <addressOffset>0x00041ff0</addressOffset>
+                <description>TRCCIDR0</description>
+                <resetValue>0x0000000d</resetValue>
+                <fields>
+                    <field>
+                        <name>PRMBL_0</name>
+                        <description>reads as 0b00001101</description>
+                        <bitRange>[7:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>TRCCIDR1</name>
+                <addressOffset>0x00041ff4</addressOffset>
+                <description>TRCCIDR1</description>
+                <resetValue>0x00000090</resetValue>
+                <fields>
+                    <field>
+                        <name>CLASS</name>
+                        <description>reads as 0b1001</description>
+                        <bitRange>[7:4]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>PRMBL_1</name>
+                        <description>reads as 0b0000</description>
+                        <bitRange>[3:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>TRCCIDR2</name>
+                <addressOffset>0x00041ff8</addressOffset>
+                <description>TRCCIDR2</description>
+                <resetValue>0x00000005</resetValue>
+                <fields>
+                    <field>
+                        <name>PRMBL_2</name>
+                        <description>reads as 0b00000101</description>
+                        <bitRange>[7:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>TRCCIDR3</name>
+                <addressOffset>0x00041ffc</addressOffset>
+                <description>TRCCIDR3</description>
+                <resetValue>0x000000b1</resetValue>
+                <fields>
+                    <field>
+                        <name>PRMBL_3</name>
+                        <description>reads as 0b10110001</description>
+                        <bitRange>[7:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CTICONTROL</name>
+                <addressOffset>0x00042000</addressOffset>
+                <description>CTI Control Register</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>GLBEN</name>
+                        <description>Enables or disables the CTI</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CTIINTACK</name>
+                <addressOffset>0x00042010</addressOffset>
+                <description>CTI Interrupt Acknowledge Register</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>INTACK</name>
+                        <description>Acknowledges the corresponding ctitrigout output. There is one bit of the register for each ctitrigout output. When a 1 is written to a bit in this register, the corresponding ctitrigout is acknowledged, causing it to be cleared.</description>
+                        <bitRange>[7:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CTIAPPSET</name>
+                <addressOffset>0x00042014</addressOffset>
+                <description>CTI Application Trigger Set Register</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>APPSET</name>
+                        <description>Setting a bit HIGH generates a channel event for the selected channel. There is one bit of the register for each channel</description>
+                        <bitRange>[3:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CTIAPPCLEAR</name>
+                <addressOffset>0x00042018</addressOffset>
+                <description>CTI Application Trigger Clear Register</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>APPCLEAR</name>
+                        <description>Sets the corresponding bits in the CTIAPPSET to 0. There is one bit of the register for each channel.</description>
+                        <bitRange>[3:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CTIAPPPULSE</name>
+                <addressOffset>0x0004201c</addressOffset>
+                <description>CTI Application Pulse Register</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>APPULSE</name>
+                        <description>Setting a bit HIGH generates a channel event pulse for the selected channel. There is one bit of the register for each channel.</description>
+                        <bitRange>[3:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CTIINEN0</name>
+                <addressOffset>0x00042020</addressOffset>
+                <description>CTI Trigger to Channel Enable Registers</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>TRIGINEN</name>
+                        <description>Enables a cross trigger event to the corresponding channel when a ctitrigin input is activated. There is one bit of the field for each of the four channels</description>
+                        <bitRange>[3:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CTIINEN1</name>
+                <addressOffset>0x00042024</addressOffset>
+                <description>CTI Trigger to Channel Enable Registers</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>TRIGINEN</name>
+                        <description>Enables a cross trigger event to the corresponding channel when a ctitrigin input is activated. There is one bit of the field for each of the four channels</description>
+                        <bitRange>[3:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CTIINEN2</name>
+                <addressOffset>0x00042028</addressOffset>
+                <description>CTI Trigger to Channel Enable Registers</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>TRIGINEN</name>
+                        <description>Enables a cross trigger event to the corresponding channel when a ctitrigin input is activated. There is one bit of the field for each of the four channels</description>
+                        <bitRange>[3:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CTIINEN3</name>
+                <addressOffset>0x0004202c</addressOffset>
+                <description>CTI Trigger to Channel Enable Registers</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>TRIGINEN</name>
+                        <description>Enables a cross trigger event to the corresponding channel when a ctitrigin input is activated. There is one bit of the field for each of the four channels</description>
+                        <bitRange>[3:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CTIINEN4</name>
+                <addressOffset>0x00042030</addressOffset>
+                <description>CTI Trigger to Channel Enable Registers</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>TRIGINEN</name>
+                        <description>Enables a cross trigger event to the corresponding channel when a ctitrigin input is activated. There is one bit of the field for each of the four channels</description>
+                        <bitRange>[3:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CTIINEN5</name>
+                <addressOffset>0x00042034</addressOffset>
+                <description>CTI Trigger to Channel Enable Registers</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>TRIGINEN</name>
+                        <description>Enables a cross trigger event to the corresponding channel when a ctitrigin input is activated. There is one bit of the field for each of the four channels</description>
+                        <bitRange>[3:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CTIINEN6</name>
+                <addressOffset>0x00042038</addressOffset>
+                <description>CTI Trigger to Channel Enable Registers</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>TRIGINEN</name>
+                        <description>Enables a cross trigger event to the corresponding channel when a ctitrigin input is activated. There is one bit of the field for each of the four channels</description>
+                        <bitRange>[3:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CTIINEN7</name>
+                <addressOffset>0x0004203c</addressOffset>
+                <description>CTI Trigger to Channel Enable Registers</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>TRIGINEN</name>
+                        <description>Enables a cross trigger event to the corresponding channel when a ctitrigin input is activated. There is one bit of the field for each of the four channels</description>
+                        <bitRange>[3:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CTIOUTEN0</name>
+                <addressOffset>0x000420a0</addressOffset>
+                <description>CTI Trigger to Channel Enable Registers</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>TRIGOUTEN</name>
+                        <description>Enables a cross trigger event to ctitrigout when the corresponding channel is activated. There is one bit of the field for each of the four channels.</description>
+                        <bitRange>[3:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CTIOUTEN1</name>
+                <addressOffset>0x000420a4</addressOffset>
+                <description>CTI Trigger to Channel Enable Registers</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>TRIGOUTEN</name>
+                        <description>Enables a cross trigger event to ctitrigout when the corresponding channel is activated. There is one bit of the field for each of the four channels.</description>
+                        <bitRange>[3:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CTIOUTEN2</name>
+                <addressOffset>0x000420a8</addressOffset>
+                <description>CTI Trigger to Channel Enable Registers</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>TRIGOUTEN</name>
+                        <description>Enables a cross trigger event to ctitrigout when the corresponding channel is activated. There is one bit of the field for each of the four channels.</description>
+                        <bitRange>[3:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CTIOUTEN3</name>
+                <addressOffset>0x000420ac</addressOffset>
+                <description>CTI Trigger to Channel Enable Registers</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>TRIGOUTEN</name>
+                        <description>Enables a cross trigger event to ctitrigout when the corresponding channel is activated. There is one bit of the field for each of the four channels.</description>
+                        <bitRange>[3:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CTIOUTEN4</name>
+                <addressOffset>0x000420b0</addressOffset>
+                <description>CTI Trigger to Channel Enable Registers</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>TRIGOUTEN</name>
+                        <description>Enables a cross trigger event to ctitrigout when the corresponding channel is activated. There is one bit of the field for each of the four channels.</description>
+                        <bitRange>[3:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CTIOUTEN5</name>
+                <addressOffset>0x000420b4</addressOffset>
+                <description>CTI Trigger to Channel Enable Registers</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>TRIGOUTEN</name>
+                        <description>Enables a cross trigger event to ctitrigout when the corresponding channel is activated. There is one bit of the field for each of the four channels.</description>
+                        <bitRange>[3:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CTIOUTEN6</name>
+                <addressOffset>0x000420b8</addressOffset>
+                <description>CTI Trigger to Channel Enable Registers</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>TRIGOUTEN</name>
+                        <description>Enables a cross trigger event to ctitrigout when the corresponding channel is activated. There is one bit of the field for each of the four channels.</description>
+                        <bitRange>[3:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CTIOUTEN7</name>
+                <addressOffset>0x000420bc</addressOffset>
+                <description>CTI Trigger to Channel Enable Registers</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>TRIGOUTEN</name>
+                        <description>Enables a cross trigger event to ctitrigout when the corresponding channel is activated. There is one bit of the field for each of the four channels.</description>
+                        <bitRange>[3:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CTITRIGINSTATUS</name>
+                <addressOffset>0x00042130</addressOffset>
+                <description>CTI Trigger to Channel Enable Registers</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>TRIGINSTATUS</name>
+                        <description>Shows the status of the ctitrigin inputs. There is one bit of the field for each trigger input.Because the register provides a view of the raw ctitrigin inputs, the reset value is UNKNOWN.</description>
+                        <bitRange>[7:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CTITRIGOUTSTATUS</name>
+                <addressOffset>0x00042134</addressOffset>
+                <description>CTI Trigger In Status Register</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>TRIGOUTSTATUS</name>
+                        <description>Shows the status of the ctitrigout outputs. There is one bit of the field for each trigger output.</description>
+                        <bitRange>[7:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CTICHINSTATUS</name>
+                <addressOffset>0x00042138</addressOffset>
+                <description>CTI Channel In Status Register</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CTICHOUTSTATUS</name>
+                        <description>Shows the status of the ctichout outputs. There is one bit of the field for each channel output</description>
+                        <bitRange>[3:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CTIGATE</name>
+                <addressOffset>0x00042140</addressOffset>
+                <description>Enable CTI Channel Gate register</description>
+                <resetValue>0x0000000f</resetValue>
+                <fields>
+                    <field>
+                        <name>CTIGATEEN3</name>
+                        <description>Enable ctichout3. Set to 0 to disable channel propagation.</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CTIGATEEN2</name>
+                        <description>Enable ctichout2. Set to 0 to disable channel propagation.</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CTIGATEEN1</name>
+                        <description>Enable ctichout1. Set to 0 to disable channel propagation.</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CTIGATEEN0</name>
+                        <description>Enable ctichout0. Set to 0 to disable channel propagation.</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>ASICCTL</name>
+                <addressOffset>0x00042144</addressOffset>
+                <description>External Multiplexer Control register</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>ASICCTL</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>ITCHOUT</name>
+                <addressOffset>0x00042ee4</addressOffset>
+                <description>Integration Test Channel Output register</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CTCHOUT</name>
+                        <description>Sets the value of the ctichout outputs</description>
+                        <bitRange>[3:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>ITTRIGOUT</name>
+                <addressOffset>0x00042ee8</addressOffset>
+                <description>Integration Test Trigger Output register</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CTTRIGOUT</name>
+                        <description>Sets the value of the ctitrigout outputs</description>
+                        <bitRange>[7:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>ITCHIN</name>
+                <addressOffset>0x00042ef4</addressOffset>
+                <description>Integration Test Channel Input register</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CTCHIN</name>
+                        <description>Reads the value of the ctichin inputs.</description>
+                        <bitRange>[3:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>ITCTRL</name>
+                <addressOffset>0x00042f00</addressOffset>
+                <description>Integration Mode Control register</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>IME</name>
+                        <description>Integration Mode Enable</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>DEVARCH</name>
+                <addressOffset>0x00042fbc</addressOffset>
+                <description>Device Architecture register</description>
+                <resetValue>0x47701a14</resetValue>
+                <fields>
+                    <field>
+                        <name>ARCHITECT</name>
+                        <description>Indicates the component architect</description>
+                        <bitRange>[31:21]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>PRESENT</name>
+                        <description>Indicates whether the DEVARCH register is present</description>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>REVISION</name>
+                        <description>Indicates the architecture revision</description>
+                        <bitRange>[19:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>ARCHID</name>
+                        <description>Indicates the component</description>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>DEVID</name>
+                <addressOffset>0x00042fc8</addressOffset>
+                <description>Device Configuration register</description>
+                <resetValue>0x00040800</resetValue>
+                <fields>
+                    <field>
+                        <name>NUMCH</name>
+                        <description>Number of ECT channels available</description>
+                        <bitRange>[19:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>NUMTRIG</name>
+                        <description>Number of ECT triggers available.</description>
+                        <bitRange>[15:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>EXTMUXNUM</name>
+                        <description>Indicates the number of multiplexers available on Trigger Inputs and Trigger Outputs that are using asicctl. The default value of 0b00000 indicates that no multiplexing is present. This value of this bit depends on the Verilog define EXTMUXNUM that you must change accordingly.</description>
+                        <bitRange>[4:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>DEVTYPE</name>
+                <addressOffset>0x00042fcc</addressOffset>
+                <description>Device Type Identifier register</description>
+                <resetValue>0x00000014</resetValue>
+                <fields>
+                    <field>
+                        <name>SUB</name>
+                        <description>Sub-classification of the type of the debug component as specified in the ARM Architecture Specification within the major classification as specified in the MAJOR field.</description>
+                        <bitRange>[7:4]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>MAJOR</name>
+                        <description>Major classification of the type of the debug component as specified in the ARM Architecture Specification for this debug and trace component.</description>
+                        <bitRange>[3:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PIDR4</name>
+                <addressOffset>0x00042fd0</addressOffset>
+                <description>CoreSight Peripheral ID4</description>
+                <resetValue>0x00000004</resetValue>
+                <fields>
+                    <field>
+                        <name>SIZE</name>
+                        <description>Always 0b0000. Indicates that the device only occupies 4KB of memory</description>
+                        <bitRange>[7:4]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>DES_2</name>
+                        <description>Together, PIDR1.DES_0, PIDR2.DES_1, and PIDR4.DES_2 identify the designer of the component.</description>
+                        <bitRange>[3:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PIDR5</name>
+                <addressOffset>0x00042fd4</addressOffset>
+                <description>CoreSight Peripheral ID5</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>PIDR5</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PIDR6</name>
+                <addressOffset>0x00042fd8</addressOffset>
+                <description>CoreSight Peripheral ID6</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>PIDR6</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PIDR7</name>
+                <addressOffset>0x00042fdc</addressOffset>
+                <description>CoreSight Peripheral ID7</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>PIDR7</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PIDR0</name>
+                <addressOffset>0x00042fe0</addressOffset>
+                <description>CoreSight Peripheral ID0</description>
+                <resetValue>0x00000021</resetValue>
+                <fields>
+                    <field>
+                        <name>PART_0</name>
+                        <description>Bits[7:0] of the 12-bit part number of the component. The designer of the component assigns this part number.</description>
+                        <bitRange>[7:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PIDR1</name>
+                <addressOffset>0x00042fe4</addressOffset>
+                <description>CoreSight Peripheral ID1</description>
+                <resetValue>0x000000bd</resetValue>
+                <fields>
+                    <field>
+                        <name>DES_0</name>
+                        <description>Together, PIDR1.DES_0, PIDR2.DES_1, and PIDR4.DES_2 identify the designer of the component.</description>
+                        <bitRange>[7:4]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>PART_1</name>
+                        <description>Bits[11:8] of the 12-bit part number of the component. The designer of the component assigns this part number.</description>
+                        <bitRange>[3:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PIDR2</name>
+                <addressOffset>0x00042fe8</addressOffset>
+                <description>CoreSight Peripheral ID2</description>
+                <resetValue>0x0000000b</resetValue>
+                <fields>
+                    <field>
+                        <name>REVISION</name>
+                        <description>This device is at r1p0</description>
+                        <bitRange>[7:4]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>JEDEC</name>
+                        <description>Always 1. Indicates that the JEDEC-assigned designer ID is used.</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>DES_1</name>
+                        <description>Together, PIDR1.DES_0, PIDR2.DES_1, and PIDR4.DES_2 identify the designer of the component.</description>
+                        <bitRange>[2:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PIDR3</name>
+                <addressOffset>0x00042fec</addressOffset>
+                <description>CoreSight Peripheral ID3</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>REVAND</name>
+                        <description>Indicates minor errata fixes specific to the revision of the component being used, for example metal fixes after implementation. In most cases, this field is 0b0000. ARM recommends that the component designers ensure that a metal fix can change this field if required, for example, by driving it from registers that reset to 0b0000.</description>
+                        <bitRange>[7:4]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CMOD</name>
+                        <description>Customer Modified. Indicates whether the customer has modified the behavior of the component. In most cases, this field is 0b0000. Customers change this value when they make authorized modifications to this component.</description>
+                        <bitRange>[3:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CIDR0</name>
+                <addressOffset>0x00042ff0</addressOffset>
+                <description>CoreSight Component ID0</description>
+                <resetValue>0x0000000d</resetValue>
+                <fields>
+                    <field>
+                        <name>PRMBL_0</name>
+                        <description>Preamble[0]. Contains bits[7:0] of the component identification code</description>
+                        <bitRange>[7:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CIDR1</name>
+                <addressOffset>0x00042ff4</addressOffset>
+                <description>CoreSight Component ID1</description>
+                <resetValue>0x00000090</resetValue>
+                <fields>
+                    <field>
+                        <name>CLASS</name>
+                        <description>Class of the component, for example, whether the component is a ROM table or a generic CoreSight component. Contains bits[15:12] of the component identification code.</description>
+                        <bitRange>[7:4]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>PRMBL_1</name>
+                        <description>Preamble[1]. Contains bits[11:8] of the component identification code.</description>
+                        <bitRange>[3:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CIDR2</name>
+                <addressOffset>0x00042ff8</addressOffset>
+                <description>CoreSight Component ID2</description>
+                <resetValue>0x00000005</resetValue>
+                <fields>
+                    <field>
+                        <name>PRMBL_2</name>
+                        <description>Preamble[2]. Contains bits[23:16] of the component identification code.</description>
+                        <bitRange>[7:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CIDR3</name>
+                <addressOffset>0x00042ffc</addressOffset>
+                <description>CoreSight Component ID3</description>
+                <resetValue>0x000000b1</resetValue>
+                <fields>
+                    <field>
+                        <name>PRMBL_3</name>
+                        <description>Preamble[3]. Contains bits[31:24] of the component identification code.</description>
+                        <bitRange>[7:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+        </registers>
+    </peripheral>
+    <peripheral derivedFrom="PPB">
+        <name>PPB_NS</name>
+        <baseAddress>0xe0020000</baseAddress>
+    </peripheral>
+    <peripheral>
+        <name>QMI</name>
+        <description>QSPI Memory Interface.
+
+            Provides a memory-mapped interface to up to two SPI/DSPI/QSPI flash or PSRAM devices. Also provides a serial interface for programming and configuration of the external device.</description>
+        <baseAddress>0x400d0000</baseAddress>
+        <addressBlock>
+            <offset>0</offset>
+            <size>84</size>
+            <usage>registers</usage>
+        </addressBlock>
+        <registers>
+            <register>
+                <name>DIRECT_CSR</name>
+                <addressOffset>0x00000000</addressOffset>
+                <description>Control and status for direct serial mode
+
+                    Direct serial mode allows the processor to send and receive raw serial frames, for programming, configuration and control of the external memory devices. Only SPI mode 0 (CPOL=0 CPHA=0) is supported.</description>
+                <resetValue>0x01800000</resetValue>
+                <fields>
+                    <field>
+                        <name>RXDELAY</name>
+                        <description>Delay the read data sample timing, in units of one half of a system clock cycle. (Not necessarily half of an SCK cycle.)</description>
+                        <bitRange>[31:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLKDIV</name>
+                        <description>Clock divisor for direct serial mode. Divisors of 1..255 are encoded directly, and the maximum divisor of 256 is encoded by a value of CLKDIV=0.
+
+                            The clock divisor can be changed on-the-fly by software, without halting or otherwise coordinating with the serial interface. The serial interface will sample the latest clock divisor each time it begins the transmission of a new byte.</description>
+                        <bitRange>[29:22]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>RXLEVEL</name>
+                        <description>Current level of DIRECT_RX FIFO</description>
+                        <bitRange>[20:18]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>RXFULL</name>
+                        <description>When 1, the DIRECT_RX FIFO is currently full. The serial interface will be stalled until data is popped; the interface will not begin a new serial frame when the DIRECT_TX FIFO is empty or the DIRECT_RX FIFO is full.</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>RXEMPTY</name>
+                        <description>When 1, the DIRECT_RX FIFO is currently empty. If the processor attempts to read more data, the FIFO state is not affected, but the value returned to the processor is undefined.</description>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>TXLEVEL</name>
+                        <description>Current level of DIRECT_TX FIFO</description>
+                        <bitRange>[14:12]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>TXEMPTY</name>
+                        <description>When 1, the DIRECT_TX FIFO is currently empty. Unless the processor pushes more data, transmission will stop and BUSY will go low once the current 8-bit serial frame completes.</description>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>TXFULL</name>
+                        <description>When 1, the DIRECT_TX FIFO is currently full. If the processor tries to write more data, that data will be ignored.</description>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>AUTO_CS1N</name>
+                        <description>When 1, automatically assert the CS1n chip select line whenever the BUSY flag is set.</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>AUTO_CS0N</name>
+                        <description>When 1, automatically assert the CS0n chip select line whenever the BUSY flag is set.</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ASSERT_CS1N</name>
+                        <description>When 1, assert (i.e. drive low) the CS1n chip select line.
+
+                            Note that this applies even when DIRECT_CSR_EN is 0.</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ASSERT_CS0N</name>
+                        <description>When 1, assert (i.e. drive low) the CS0n chip select line.
+
+                            Note that this applies even when DIRECT_CSR_EN is 0.</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>BUSY</name>
+                        <description>Direct mode busy flag. If 1, data is currently being shifted in/out (or would be if the interface were not stalled on the RX FIFO), and the chip select must not yet be deasserted.
+
+                            The busy flag will also be set to 1 if a memory-mapped transfer is still in progress when direct mode is enabled. Direct mode blocks new memory-mapped transfers, but can&#39;t halt a transfer that is already in progress. If there is a chance that memory-mapped transfers may be in progress, the busy flag should be polled for 0 before asserting the chip select.
+
+                            (In practice you will usually discover this timing condition through other means, because any subsequent memory-mapped transfers when direct mode is enabled will return bus errors, which are difficult to ignore.)</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>EN</name>
+                        <description>Enable direct mode.
+
+                            In direct mode, software controls the chip select lines, and can perform direct SPI transfers by pushing data to the DIRECT_TX FIFO, and popping the same amount of data from the DIRECT_RX FIFO.
+
+                            Memory-mapped accesses will generate bus errors when direct serial mode is enabled.</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>DIRECT_TX</name>
+                <addressOffset>0x00000004</addressOffset>
+                <description>Transmit FIFO for direct mode</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>NOPUSH</name>
+                        <description>Inhibit the RX FIFO push that would correspond to this TX FIFO entry.
+
+                            Useful to avoid garbage appearing in the RX FIFO when pushing the command at the beginning of a SPI transfer.</description>
+                        <bitRange>[20:20]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>OE</name>
+                        <description>Output enable (active-high). For single width (SPI), this field is ignored, and SD0 is always set to output, with SD1 always set to input.
+
+                            For dual and quad width (DSPI/QSPI), this sets whether the relevant SDx pads are set to output whilst transferring this FIFO record. In this case the command/address should have OE set, and the data transfer should have OE set or clear depending on the direction of the transfer.</description>
+                        <bitRange>[19:19]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>DWIDTH</name>
+                        <description>Data width. If 0, hardware will transmit the 8 LSBs of the DIRECT_TX DATA field, and return an 8-bit value in the 8 LSBs of DIRECT_RX. If 1, the full 16-bit width is used. 8-bit and 16-bit transfers can be mixed freely.</description>
+                        <bitRange>[18:18]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>IWIDTH</name>
+                        <description>Configure whether this FIFO record is transferred with single/dual/quad interface width (0/1/2). Different widths can be mixed freely.</description>
+                        <bitRange>[17:16]</bitRange>
+                        <access>write-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>S</name>
+                                <value>0</value>
+                                <description>Single width</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>D</name>
+                                <value>1</value>
+                                <description>Dual width</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Q</name>
+                                <value>2</value>
+                                <description>Quad width</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>DATA</name>
+                        <description>Data pushed here will be clocked out falling edges of SCK (or before the very first rising edge of SCK, if this is the first pulse). For each byte clocked out, the interface will simultaneously sample one byte, on rising edges of SCK, and push this to the DIRECT_RX FIFO.
+
+                            For 16-bit data, the least-significant byte is transmitted first.</description>
+                        <bitRange>[15:0]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>DIRECT_RX</name>
+                <addressOffset>0x00000008</addressOffset>
+                <description>Receive FIFO for direct mode</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>DIRECT_RX</name>
+                        <description>With each byte clocked out on the serial interface, one byte will simultaneously be clocked in, and will appear in this FIFO. The serial interface will stall when this FIFO is full, to avoid dropping data.
+
+                            When 16-bit data is pushed into the TX FIFO, the corresponding RX FIFO push will also contain 16 bits of data. The least-significant byte is the first one received.</description>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-only</access>
+                        <readAction>modify</readAction>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>M0_TIMING</name>
+                <addressOffset>0x0000000c</addressOffset>
+                <description>Timing configuration register for memory address window 0.</description>
+                <resetValue>0x40000004</resetValue>
+                <fields>
+                    <field>
+                        <name>COOLDOWN</name>
+                        <description>Chip select cooldown period. When a memory transfer finishes, the chip select remains asserted for 64 x COOLDOWN system clock cycles, plus half an SCK clock period (rounded up for odd SCK divisors). After this cooldown expires, the chip select is always deasserted to save power.
+
+                            If the next memory access arrives within the cooldown period, the QMI may be able to append more SCK cycles to the currently ongoing SPI transfer, rather than starting a new transfer. This reduces access latency and increases bus throughput.
+
+                            Specifically, the next access must be in the same direction (read/write), access the same memory window (chip select 0/1), and follow sequentially the address of the last transfer. If any of these are false, the new access will first deassert the chip select, then begin a new transfer.
+
+                            If COOLDOWN is 0, the address alignment configured by PAGEBREAK has been reached, or the total chip select assertion limit MAX_SELECT has been reached, the cooldown period is skipped, and the chip select will always be deasserted one half SCK period after the transfer finishes.</description>
+                        <bitRange>[31:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PAGEBREAK</name>
+                        <description>When page break is enabled, chip select will automatically deassert when crossing certain power-of-2-aligned address boundaries. The next access will always begin a new read/write SPI burst, even if the address of the next access follows in sequence with the last access before the page boundary.
+
+                            Some flash and PSRAM devices forbid crossing page boundaries with a single read/write transfer, or restrict the operating frequency for transfers that do cross page a boundary. This option allows the QMI to safely support those devices.
+
+                            This field has no effect when COOLDOWN is disabled.</description>
+                        <bitRange>[29:28]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NONE</name>
+                                <value>0</value>
+                                <description>No page boundary is enforced</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>256</name>
+                                <value>1</value>
+                                <description>Break bursts crossing a 256-byte page boundary</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>1024</name>
+                                <value>2</value>
+                                <description>Break bursts crossing a 1024-byte quad-page boundary</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>4096</name>
+                                <value>3</value>
+                                <description>Break bursts crossing a 4096-byte sector boundary</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>SELECT_SETUP</name>
+                        <description>Add up to one additional system clock cycle of setup between chip select assertion and the first rising edge of SCK.
+
+                            The default setup time is one half SCK period, which is usually sufficient except for very high SCK frequencies with some flash devices.</description>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SELECT_HOLD</name>
+                        <description>Add up to three additional system clock cycles of active hold between the last falling edge of SCK and the deassertion of this window&#39;s chip select.
+
+                            The default hold time is one system clock cycle. Note that flash datasheets usually give chip select active hold time from the last *rising* edge of SCK, and so even zero hold from the last falling edge would be safe.
+
+                            Note that this is a minimum hold time guaranteed by the QMI: the actual chip select active hold may be slightly longer for read transfers with low clock divisors and/or high sample delays. Specifically, if the point two cycles after the last RX data sample is later than the last SCK falling edge, then the hold time is measured from *this* point.
+
+                            Note also that, in case the final SCK pulse is masked to save energy (true for non-DTR reads when COOLDOWN is disabled or PAGE_BREAK is reached), all of QMI&#39;s timing logic behaves as though the clock pulse were still present. The SELECT_HOLD time is applied from the point where the last SCK falling edge would be if the clock pulse were not masked.</description>
+                        <bitRange>[24:23]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>MAX_SELECT</name>
+                        <description>Enforce a maximum assertion duration for this window&#39;s chip select, in units of 64 system clock cycles. If 0, the QMI is permitted to keep the chip select asserted indefinitely when servicing sequential memory accesses (see COOLDOWN).
+
+                            This feature is required to meet timing constraints of PSRAM devices, which specify a maximum chip select assertion so they can perform DRAM refresh cycles. See also MIN_DESELECT, which can enforce a minimum deselect time.
+
+                            If a memory access is in progress at the time MAX_SELECT is reached, the QMI will wait for the access to complete before deasserting the chip select. This additional time must be accounted for to calculate a safe MAX_SELECT value. In the worst case, this may be a fully-formed serial transfer, including command prefix and address, with a data payload as large as one cache line.</description>
+                        <bitRange>[22:17]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>MIN_DESELECT</name>
+                        <description>After this window&#39;s chip select is deasserted, it remains deasserted for half an SCK cycle (rounded up to an integer number of system clock cycles), plus MIN_DESELECT additional system clock cycles, before the QMI reasserts either chip select pin.
+
+                            Nonzero values may be required for PSRAM devices which enforce a longer minimum CS deselect time, so that they can perform internal DRAM refresh cycles whilst deselected.</description>
+                        <bitRange>[16:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>RXDELAY</name>
+                        <description>Delay the read data sample timing, in units of one half of a system clock cycle. (Not necessarily half of an SCK cycle.) An RXDELAY of 0 means the sample is captured at the SDI input registers simultaneously with the rising edge of SCK launched from the SCK output register.
+
+                            At higher SCK frequencies, RXDELAY may need to be increased to account for the round trip delay of the pads, and the clock-to-Q delay of the QSPI memory device.</description>
+                        <bitRange>[10:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLKDIV</name>
+                        <description>Clock divisor. Odd and even divisors are supported. Defines the SCK clock period in units of 1 system clock cycle. Divisors 1..255 are encoded directly, and a divisor of 256 is encoded with a value of CLKDIV=0.
+
+                            The clock divisor can be changed on-the-fly, even when the QMI is currently accessing memory in this address window. All other parameters must only be changed when the QMI is idle.
+
+                            If software is increasing CLKDIV in anticipation of an increase in the system clock frequency, a dummy access to either memory window (and appropriate processor barriers/fences) must be inserted after the Mx_TIMING write to ensure the SCK divisor change is in effect _before_ the system clock is changed.</description>
+                        <bitRange>[7:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>M0_RFMT</name>
+                <addressOffset>0x00000010</addressOffset>
+                <description>Read transfer format configuration for memory address window 0.
+
+                    Configure the bus width of each transfer phase individually, and configure the length or presence of the command prefix, command suffix and dummy/turnaround transfer phases. Only 24-bit addresses are supported.
+
+                    The reset value of the M0_RFMT register is configured to support a basic 03h serial read transfer with no additional configuration.</description>
+                <resetValue>0x00001000</resetValue>
+                <fields>
+                    <field>
+                        <name>DTR</name>
+                        <description>Enable double transfer rate (DTR) for read commands: address, suffix and read data phases are active on both edges of SCK. SDO data is launched centre-aligned on each SCK edge, and SDI data is captured on the SCK edge that follows its launch.
+
+                            DTR is implemented by halving the clock rate; SCK has a period of 2 x CLK_DIV throughout the transfer. The prefix and dummy phases are still single transfer rate.
+
+                            If the suffix is quad-width, it must be 0 or 8 bits in length, to ensure an even number of SCK edges.</description>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DUMMY_LEN</name>
+                        <description>Length of dummy phase between command suffix and data phase, in units of 4 bits. (i.e. 1 cycle for quad width, 2 for dual, 4 for single)</description>
+                        <bitRange>[18:16]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NONE</name>
+                                <value>0</value>
+                                <description>No dummy phase</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>4</name>
+                                <value>1</value>
+                                <description>4 dummy bits</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>8</name>
+                                <value>2</value>
+                                <description>8 dummy bits</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>12</name>
+                                <value>3</value>
+                                <description>12 dummy bits</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>16</name>
+                                <value>4</value>
+                                <description>16 dummy bits</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>20</name>
+                                <value>5</value>
+                                <description>20 dummy bits</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>24</name>
+                                <value>6</value>
+                                <description>24 dummy bits</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>28</name>
+                                <value>7</value>
+                                <description>28 dummy bits</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>SUFFIX_LEN</name>
+                        <description>Length of post-address command suffix, in units of 4 bits. (i.e. 1 cycle for quad width, 2 for dual, 4 for single)
+
+                            Only values of 0 and 8 bits are supported.</description>
+                        <bitRange>[15:14]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NONE</name>
+                                <value>0</value>
+                                <description>No suffix</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>8</name>
+                                <value>2</value>
+                                <description>8-bit suffix</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>PREFIX_LEN</name>
+                        <description>Length of command prefix, in units of 8 bits. (i.e. 2 cycles for quad width, 4 for dual, 8 for single)</description>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NONE</name>
+                                <value>0</value>
+                                <description>No prefix</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>8</name>
+                                <value>1</value>
+                                <description>8-bit prefix</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>DATA_WIDTH</name>
+                        <description>The width used for the data transfer</description>
+                        <bitRange>[9:8]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>S</name>
+                                <value>0</value>
+                                <description>Single width</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>D</name>
+                                <value>1</value>
+                                <description>Dual width</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Q</name>
+                                <value>2</value>
+                                <description>Quad width</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>DUMMY_WIDTH</name>
+                        <description>The width used for the dummy phase, if any.
+
+                            If width is single, SD0/MOSI is held asserted low during the dummy phase, and SD1...SD3 are tristated. If width is dual/quad, all IOs are tristated during the dummy phase.</description>
+                        <bitRange>[7:6]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>S</name>
+                                <value>0</value>
+                                <description>Single width</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>D</name>
+                                <value>1</value>
+                                <description>Dual width</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Q</name>
+                                <value>2</value>
+                                <description>Quad width</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>SUFFIX_WIDTH</name>
+                        <description>The width used for the post-address command suffix, if any</description>
+                        <bitRange>[5:4]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>S</name>
+                                <value>0</value>
+                                <description>Single width</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>D</name>
+                                <value>1</value>
+                                <description>Dual width</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Q</name>
+                                <value>2</value>
+                                <description>Quad width</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>ADDR_WIDTH</name>
+                        <description>The transfer width used for the address. The address phase always transfers 24 bits in total.</description>
+                        <bitRange>[3:2]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>S</name>
+                                <value>0</value>
+                                <description>Single width</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>D</name>
+                                <value>1</value>
+                                <description>Dual width</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Q</name>
+                                <value>2</value>
+                                <description>Quad width</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>PREFIX_WIDTH</name>
+                        <description>The transfer width used for the command prefix, if any</description>
+                        <bitRange>[1:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>S</name>
+                                <value>0</value>
+                                <description>Single width</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>D</name>
+                                <value>1</value>
+                                <description>Dual width</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Q</name>
+                                <value>2</value>
+                                <description>Quad width</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>M0_RCMD</name>
+                <addressOffset>0x00000014</addressOffset>
+                <description>Command constants used for reads from memory address window 0.
+
+                    The reset value of the M0_RCMD register is configured to support a basic 03h serial read transfer with no additional configuration.</description>
+                <resetValue>0x0000a003</resetValue>
+                <fields>
+                    <field>
+                        <name>SUFFIX</name>
+                        <description>The command suffix bits following the address, if Mx_RFMT_SUFFIX_LEN is nonzero.</description>
+                        <bitRange>[15:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PREFIX</name>
+                        <description>The command prefix bits to prepend on each new transfer, if Mx_RFMT_PREFIX_LEN is nonzero.</description>
+                        <bitRange>[7:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>M0_WFMT</name>
+                <addressOffset>0x00000018</addressOffset>
+                <description>Write transfer format configuration for memory address window 0.
+
+                    Configure the bus width of each transfer phase individually, and configure the length or presence of the command prefix, command suffix and dummy/turnaround transfer phases. Only 24-bit addresses are supported.
+
+                    The reset value of the M0_WFMT register is configured to support a basic 02h serial write transfer. However, writes to this window must first be enabled via the XIP_CTRL_WRITABLE_M0 bit, as XIP memory is read-only by default.</description>
+                <resetValue>0x00001000</resetValue>
+                <fields>
+                    <field>
+                        <name>DTR</name>
+                        <description>Enable double transfer rate (DTR) for write commands: address, suffix and write data phases are active on both edges of SCK. SDO data is launched centre-aligned on each SCK edge, and SDI data is captured on the SCK edge that follows its launch.
+
+                            DTR is implemented by halving the clock rate; SCK has a period of 2 x CLK_DIV throughout the transfer. The prefix and dummy phases are still single transfer rate.
+
+                            If the suffix is quad-width, it must be 0 or 8 bits in length, to ensure an even number of SCK edges.</description>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DUMMY_LEN</name>
+                        <description>Length of dummy phase between command suffix and data phase, in units of 4 bits. (i.e. 1 cycle for quad width, 2 for dual, 4 for single)</description>
+                        <bitRange>[18:16]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NONE</name>
+                                <value>0</value>
+                                <description>No dummy phase</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>4</name>
+                                <value>1</value>
+                                <description>4 dummy bits</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>8</name>
+                                <value>2</value>
+                                <description>8 dummy bits</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>12</name>
+                                <value>3</value>
+                                <description>12 dummy bits</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>16</name>
+                                <value>4</value>
+                                <description>16 dummy bits</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>20</name>
+                                <value>5</value>
+                                <description>20 dummy bits</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>24</name>
+                                <value>6</value>
+                                <description>24 dummy bits</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>28</name>
+                                <value>7</value>
+                                <description>28 dummy bits</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>SUFFIX_LEN</name>
+                        <description>Length of post-address command suffix, in units of 4 bits. (i.e. 1 cycle for quad width, 2 for dual, 4 for single)
+
+                            Only values of 0 and 8 bits are supported.</description>
+                        <bitRange>[15:14]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NONE</name>
+                                <value>0</value>
+                                <description>No suffix</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>8</name>
+                                <value>2</value>
+                                <description>8-bit suffix</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>PREFIX_LEN</name>
+                        <description>Length of command prefix, in units of 8 bits. (i.e. 2 cycles for quad width, 4 for dual, 8 for single)</description>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NONE</name>
+                                <value>0</value>
+                                <description>No prefix</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>8</name>
+                                <value>1</value>
+                                <description>8-bit prefix</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>DATA_WIDTH</name>
+                        <description>The width used for the data transfer</description>
+                        <bitRange>[9:8]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>S</name>
+                                <value>0</value>
+                                <description>Single width</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>D</name>
+                                <value>1</value>
+                                <description>Dual width</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Q</name>
+                                <value>2</value>
+                                <description>Quad width</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>DUMMY_WIDTH</name>
+                        <description>The width used for the dummy phase, if any.
+
+                            If width is single, SD0/MOSI is held asserted low during the dummy phase, and SD1...SD3 are tristated. If width is dual/quad, all IOs are tristated during the dummy phase.</description>
+                        <bitRange>[7:6]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>S</name>
+                                <value>0</value>
+                                <description>Single width</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>D</name>
+                                <value>1</value>
+                                <description>Dual width</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Q</name>
+                                <value>2</value>
+                                <description>Quad width</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>SUFFIX_WIDTH</name>
+                        <description>The width used for the post-address command suffix, if any</description>
+                        <bitRange>[5:4]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>S</name>
+                                <value>0</value>
+                                <description>Single width</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>D</name>
+                                <value>1</value>
+                                <description>Dual width</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Q</name>
+                                <value>2</value>
+                                <description>Quad width</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>ADDR_WIDTH</name>
+                        <description>The transfer width used for the address. The address phase always transfers 24 bits in total.</description>
+                        <bitRange>[3:2]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>S</name>
+                                <value>0</value>
+                                <description>Single width</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>D</name>
+                                <value>1</value>
+                                <description>Dual width</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Q</name>
+                                <value>2</value>
+                                <description>Quad width</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>PREFIX_WIDTH</name>
+                        <description>The transfer width used for the command prefix, if any</description>
+                        <bitRange>[1:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>S</name>
+                                <value>0</value>
+                                <description>Single width</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>D</name>
+                                <value>1</value>
+                                <description>Dual width</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Q</name>
+                                <value>2</value>
+                                <description>Quad width</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>M0_WCMD</name>
+                <addressOffset>0x0000001c</addressOffset>
+                <description>Command constants used for writes to memory address window 0.
+
+                    The reset value of the M0_WCMD register is configured to support a basic 02h serial write transfer with no additional configuration.</description>
+                <resetValue>0x0000a002</resetValue>
+                <fields>
+                    <field>
+                        <name>SUFFIX</name>
+                        <description>The command suffix bits following the address, if Mx_WFMT_SUFFIX_LEN is nonzero.</description>
+                        <bitRange>[15:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PREFIX</name>
+                        <description>The command prefix bits to prepend on each new transfer, if Mx_WFMT_PREFIX_LEN is nonzero.</description>
+                        <bitRange>[7:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>M1_TIMING</name>
+                <addressOffset>0x00000020</addressOffset>
+                <description>Timing configuration register for memory address window 1.</description>
+                <resetValue>0x40000004</resetValue>
+                <fields>
+                    <field>
+                        <name>COOLDOWN</name>
+                        <description>Chip select cooldown period. When a memory transfer finishes, the chip select remains asserted for 64 x COOLDOWN system clock cycles, plus half an SCK clock period (rounded up for odd SCK divisors). After this cooldown expires, the chip select is always deasserted to save power.
+
+                            If the next memory access arrives within the cooldown period, the QMI may be able to append more SCK cycles to the currently ongoing SPI transfer, rather than starting a new transfer. This reduces access latency and increases bus throughput.
+
+                            Specifically, the next access must be in the same direction (read/write), access the same memory window (chip select 0/1), and follow sequentially the address of the last transfer. If any of these are false, the new access will first deassert the chip select, then begin a new transfer.
+
+                            If COOLDOWN is 0, the address alignment configured by PAGEBREAK has been reached, or the total chip select assertion limit MAX_SELECT has been reached, the cooldown period is skipped, and the chip select will always be deasserted one half SCK period after the transfer finishes.</description>
+                        <bitRange>[31:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PAGEBREAK</name>
+                        <description>When page break is enabled, chip select will automatically deassert when crossing certain power-of-2-aligned address boundaries. The next access will always begin a new read/write SPI burst, even if the address of the next access follows in sequence with the last access before the page boundary.
+
+                            Some flash and PSRAM devices forbid crossing page boundaries with a single read/write transfer, or restrict the operating frequency for transfers that do cross page a boundary. This option allows the QMI to safely support those devices.
+
+                            This field has no effect when COOLDOWN is disabled.</description>
+                        <bitRange>[29:28]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NONE</name>
+                                <value>0</value>
+                                <description>No page boundary is enforced</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>256</name>
+                                <value>1</value>
+                                <description>Break bursts crossing a 256-byte page boundary</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>1024</name>
+                                <value>2</value>
+                                <description>Break bursts crossing a 1024-byte quad-page boundary</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>4096</name>
+                                <value>3</value>
+                                <description>Break bursts crossing a 4096-byte sector boundary</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>SELECT_SETUP</name>
+                        <description>Add up to one additional system clock cycle of setup between chip select assertion and the first rising edge of SCK.
+
+                            The default setup time is one half SCK period, which is usually sufficient except for very high SCK frequencies with some flash devices.</description>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SELECT_HOLD</name>
+                        <description>Add up to three additional system clock cycles of active hold between the last falling edge of SCK and the deassertion of this window&#39;s chip select.
+
+                            The default hold time is one system clock cycle. Note that flash datasheets usually give chip select active hold time from the last *rising* edge of SCK, and so even zero hold from the last falling edge would be safe.
+
+                            Note that this is a minimum hold time guaranteed by the QMI: the actual chip select active hold may be slightly longer for read transfers with low clock divisors and/or high sample delays. Specifically, if the point two cycles after the last RX data sample is later than the last SCK falling edge, then the hold time is measured from *this* point.
+
+                            Note also that, in case the final SCK pulse is masked to save energy (true for non-DTR reads when COOLDOWN is disabled or PAGE_BREAK is reached), all of QMI&#39;s timing logic behaves as though the clock pulse were still present. The SELECT_HOLD time is applied from the point where the last SCK falling edge would be if the clock pulse were not masked.</description>
+                        <bitRange>[24:23]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>MAX_SELECT</name>
+                        <description>Enforce a maximum assertion duration for this window&#39;s chip select, in units of 64 system clock cycles. If 0, the QMI is permitted to keep the chip select asserted indefinitely when servicing sequential memory accesses (see COOLDOWN).
+
+                            This feature is required to meet timing constraints of PSRAM devices, which specify a maximum chip select assertion so they can perform DRAM refresh cycles. See also MIN_DESELECT, which can enforce a minimum deselect time.
+
+                            If a memory access is in progress at the time MAX_SELECT is reached, the QMI will wait for the access to complete before deasserting the chip select. This additional time must be accounted for to calculate a safe MAX_SELECT value. In the worst case, this may be a fully-formed serial transfer, including command prefix and address, with a data payload as large as one cache line.</description>
+                        <bitRange>[22:17]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>MIN_DESELECT</name>
+                        <description>After this window&#39;s chip select is deasserted, it remains deasserted for half an SCK cycle (rounded up to an integer number of system clock cycles), plus MIN_DESELECT additional system clock cycles, before the QMI reasserts either chip select pin.
+
+                            Nonzero values may be required for PSRAM devices which enforce a longer minimum CS deselect time, so that they can perform internal DRAM refresh cycles whilst deselected.</description>
+                        <bitRange>[16:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>RXDELAY</name>
+                        <description>Delay the read data sample timing, in units of one half of a system clock cycle. (Not necessarily half of an SCK cycle.) An RXDELAY of 0 means the sample is captured at the SDI input registers simultaneously with the rising edge of SCK launched from the SCK output register.
+
+                            At higher SCK frequencies, RXDELAY may need to be increased to account for the round trip delay of the pads, and the clock-to-Q delay of the QSPI memory device.</description>
+                        <bitRange>[10:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLKDIV</name>
+                        <description>Clock divisor. Odd and even divisors are supported. Defines the SCK clock period in units of 1 system clock cycle. Divisors 1..255 are encoded directly, and a divisor of 256 is encoded with a value of CLKDIV=0.
+
+                            The clock divisor can be changed on-the-fly, even when the QMI is currently accessing memory in this address window. All other parameters must only be changed when the QMI is idle.
+
+                            If software is increasing CLKDIV in anticipation of an increase in the system clock frequency, a dummy access to either memory window (and appropriate processor barriers/fences) must be inserted after the Mx_TIMING write to ensure the SCK divisor change is in effect _before_ the system clock is changed.</description>
+                        <bitRange>[7:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>M1_RFMT</name>
+                <addressOffset>0x00000024</addressOffset>
+                <description>Read transfer format configuration for memory address window 1.
+
+                    Configure the bus width of each transfer phase individually, and configure the length or presence of the command prefix, command suffix and dummy/turnaround transfer phases. Only 24-bit addresses are supported.
+
+                    The reset value of the M1_RFMT register is configured to support a basic 03h serial read transfer with no additional configuration.</description>
+                <resetValue>0x00001000</resetValue>
+                <fields>
+                    <field>
+                        <name>DTR</name>
+                        <description>Enable double transfer rate (DTR) for read commands: address, suffix and read data phases are active on both edges of SCK. SDO data is launched centre-aligned on each SCK edge, and SDI data is captured on the SCK edge that follows its launch.
+
+                            DTR is implemented by halving the clock rate; SCK has a period of 2 x CLK_DIV throughout the transfer. The prefix and dummy phases are still single transfer rate.
+
+                            If the suffix is quad-width, it must be 0 or 8 bits in length, to ensure an even number of SCK edges.</description>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DUMMY_LEN</name>
+                        <description>Length of dummy phase between command suffix and data phase, in units of 4 bits. (i.e. 1 cycle for quad width, 2 for dual, 4 for single)</description>
+                        <bitRange>[18:16]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NONE</name>
+                                <value>0</value>
+                                <description>No dummy phase</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>4</name>
+                                <value>1</value>
+                                <description>4 dummy bits</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>8</name>
+                                <value>2</value>
+                                <description>8 dummy bits</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>12</name>
+                                <value>3</value>
+                                <description>12 dummy bits</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>16</name>
+                                <value>4</value>
+                                <description>16 dummy bits</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>20</name>
+                                <value>5</value>
+                                <description>20 dummy bits</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>24</name>
+                                <value>6</value>
+                                <description>24 dummy bits</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>28</name>
+                                <value>7</value>
+                                <description>28 dummy bits</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>SUFFIX_LEN</name>
+                        <description>Length of post-address command suffix, in units of 4 bits. (i.e. 1 cycle for quad width, 2 for dual, 4 for single)
+
+                            Only values of 0 and 8 bits are supported.</description>
+                        <bitRange>[15:14]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NONE</name>
+                                <value>0</value>
+                                <description>No suffix</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>8</name>
+                                <value>2</value>
+                                <description>8-bit suffix</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>PREFIX_LEN</name>
+                        <description>Length of command prefix, in units of 8 bits. (i.e. 2 cycles for quad width, 4 for dual, 8 for single)</description>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NONE</name>
+                                <value>0</value>
+                                <description>No prefix</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>8</name>
+                                <value>1</value>
+                                <description>8-bit prefix</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>DATA_WIDTH</name>
+                        <description>The width used for the data transfer</description>
+                        <bitRange>[9:8]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>S</name>
+                                <value>0</value>
+                                <description>Single width</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>D</name>
+                                <value>1</value>
+                                <description>Dual width</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Q</name>
+                                <value>2</value>
+                                <description>Quad width</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>DUMMY_WIDTH</name>
+                        <description>The width used for the dummy phase, if any.
+
+                            If width is single, SD0/MOSI is held asserted low during the dummy phase, and SD1...SD3 are tristated. If width is dual/quad, all IOs are tristated during the dummy phase.</description>
+                        <bitRange>[7:6]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>S</name>
+                                <value>0</value>
+                                <description>Single width</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>D</name>
+                                <value>1</value>
+                                <description>Dual width</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Q</name>
+                                <value>2</value>
+                                <description>Quad width</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>SUFFIX_WIDTH</name>
+                        <description>The width used for the post-address command suffix, if any</description>
+                        <bitRange>[5:4]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>S</name>
+                                <value>0</value>
+                                <description>Single width</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>D</name>
+                                <value>1</value>
+                                <description>Dual width</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Q</name>
+                                <value>2</value>
+                                <description>Quad width</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>ADDR_WIDTH</name>
+                        <description>The transfer width used for the address. The address phase always transfers 24 bits in total.</description>
+                        <bitRange>[3:2]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>S</name>
+                                <value>0</value>
+                                <description>Single width</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>D</name>
+                                <value>1</value>
+                                <description>Dual width</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Q</name>
+                                <value>2</value>
+                                <description>Quad width</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>PREFIX_WIDTH</name>
+                        <description>The transfer width used for the command prefix, if any</description>
+                        <bitRange>[1:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>S</name>
+                                <value>0</value>
+                                <description>Single width</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>D</name>
+                                <value>1</value>
+                                <description>Dual width</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Q</name>
+                                <value>2</value>
+                                <description>Quad width</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>M1_RCMD</name>
+                <addressOffset>0x00000028</addressOffset>
+                <description>Command constants used for reads from memory address window 1.
+
+                    The reset value of the M1_RCMD register is configured to support a basic 03h serial read transfer with no additional configuration.</description>
+                <resetValue>0x0000a003</resetValue>
+                <fields>
+                    <field>
+                        <name>SUFFIX</name>
+                        <description>The command suffix bits following the address, if Mx_RFMT_SUFFIX_LEN is nonzero.</description>
+                        <bitRange>[15:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PREFIX</name>
+                        <description>The command prefix bits to prepend on each new transfer, if Mx_RFMT_PREFIX_LEN is nonzero.</description>
+                        <bitRange>[7:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>M1_WFMT</name>
+                <addressOffset>0x0000002c</addressOffset>
+                <description>Write transfer format configuration for memory address window 1.
+
+                    Configure the bus width of each transfer phase individually, and configure the length or presence of the command prefix, command suffix and dummy/turnaround transfer phases. Only 24-bit addresses are supported.
+
+                    The reset value of the M1_WFMT register is configured to support a basic 02h serial write transfer. However, writes to this window must first be enabled via the XIP_CTRL_WRITABLE_M1 bit, as XIP memory is read-only by default.</description>
+                <resetValue>0x00001000</resetValue>
+                <fields>
+                    <field>
+                        <name>DTR</name>
+                        <description>Enable double transfer rate (DTR) for write commands: address, suffix and write data phases are active on both edges of SCK. SDO data is launched centre-aligned on each SCK edge, and SDI data is captured on the SCK edge that follows its launch.
+
+                            DTR is implemented by halving the clock rate; SCK has a period of 2 x CLK_DIV throughout the transfer. The prefix and dummy phases are still single transfer rate.
+
+                            If the suffix is quad-width, it must be 0 or 8 bits in length, to ensure an even number of SCK edges.</description>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DUMMY_LEN</name>
+                        <description>Length of dummy phase between command suffix and data phase, in units of 4 bits. (i.e. 1 cycle for quad width, 2 for dual, 4 for single)</description>
+                        <bitRange>[18:16]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NONE</name>
+                                <value>0</value>
+                                <description>No dummy phase</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>4</name>
+                                <value>1</value>
+                                <description>4 dummy bits</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>8</name>
+                                <value>2</value>
+                                <description>8 dummy bits</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>12</name>
+                                <value>3</value>
+                                <description>12 dummy bits</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>16</name>
+                                <value>4</value>
+                                <description>16 dummy bits</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>20</name>
+                                <value>5</value>
+                                <description>20 dummy bits</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>24</name>
+                                <value>6</value>
+                                <description>24 dummy bits</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>28</name>
+                                <value>7</value>
+                                <description>28 dummy bits</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>SUFFIX_LEN</name>
+                        <description>Length of post-address command suffix, in units of 4 bits. (i.e. 1 cycle for quad width, 2 for dual, 4 for single)
+
+                            Only values of 0 and 8 bits are supported.</description>
+                        <bitRange>[15:14]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NONE</name>
+                                <value>0</value>
+                                <description>No suffix</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>8</name>
+                                <value>2</value>
+                                <description>8-bit suffix</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>PREFIX_LEN</name>
+                        <description>Length of command prefix, in units of 8 bits. (i.e. 2 cycles for quad width, 4 for dual, 8 for single)</description>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NONE</name>
+                                <value>0</value>
+                                <description>No prefix</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>8</name>
+                                <value>1</value>
+                                <description>8-bit prefix</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>DATA_WIDTH</name>
+                        <description>The width used for the data transfer</description>
+                        <bitRange>[9:8]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>S</name>
+                                <value>0</value>
+                                <description>Single width</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>D</name>
+                                <value>1</value>
+                                <description>Dual width</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Q</name>
+                                <value>2</value>
+                                <description>Quad width</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>DUMMY_WIDTH</name>
+                        <description>The width used for the dummy phase, if any.
+
+                            If width is single, SD0/MOSI is held asserted low during the dummy phase, and SD1...SD3 are tristated. If width is dual/quad, all IOs are tristated during the dummy phase.</description>
+                        <bitRange>[7:6]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>S</name>
+                                <value>0</value>
+                                <description>Single width</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>D</name>
+                                <value>1</value>
+                                <description>Dual width</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Q</name>
+                                <value>2</value>
+                                <description>Quad width</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>SUFFIX_WIDTH</name>
+                        <description>The width used for the post-address command suffix, if any</description>
+                        <bitRange>[5:4]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>S</name>
+                                <value>0</value>
+                                <description>Single width</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>D</name>
+                                <value>1</value>
+                                <description>Dual width</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Q</name>
+                                <value>2</value>
+                                <description>Quad width</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>ADDR_WIDTH</name>
+                        <description>The transfer width used for the address. The address phase always transfers 24 bits in total.</description>
+                        <bitRange>[3:2]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>S</name>
+                                <value>0</value>
+                                <description>Single width</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>D</name>
+                                <value>1</value>
+                                <description>Dual width</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Q</name>
+                                <value>2</value>
+                                <description>Quad width</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>PREFIX_WIDTH</name>
+                        <description>The transfer width used for the command prefix, if any</description>
+                        <bitRange>[1:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>S</name>
+                                <value>0</value>
+                                <description>Single width</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>D</name>
+                                <value>1</value>
+                                <description>Dual width</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Q</name>
+                                <value>2</value>
+                                <description>Quad width</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>M1_WCMD</name>
+                <addressOffset>0x00000030</addressOffset>
+                <description>Command constants used for writes to memory address window 1.
+
+                    The reset value of the M1_WCMD register is configured to support a basic 02h serial write transfer with no additional configuration.</description>
+                <resetValue>0x0000a002</resetValue>
+                <fields>
+                    <field>
+                        <name>SUFFIX</name>
+                        <description>The command suffix bits following the address, if Mx_WFMT_SUFFIX_LEN is nonzero.</description>
+                        <bitRange>[15:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PREFIX</name>
+                        <description>The command prefix bits to prepend on each new transfer, if Mx_WFMT_PREFIX_LEN is nonzero.</description>
+                        <bitRange>[7:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>ATRANS0</name>
+                <addressOffset>0x00000034</addressOffset>
+                <description>Configure address translation for XIP virtual addresses 0x000000 through 0x3fffff (a 4 MiB window starting at +0 MiB).
+
+                    Address translation allows a program image to be executed in place at multiple physical flash addresses (for example, a double-buffered flash image for over-the-air updates), without the overhead of position-independent code.
+
+                    At reset, the address translation registers are initialised to an identity mapping, so that they can be ignored if address translation is not required.
+
+                    Note that the XIP cache is fully virtually addressed, so a cache flush is required after changing the address translation.</description>
+                <resetValue>0x04000000</resetValue>
+                <fields>
+                    <field>
+                        <name>SIZE</name>
+                        <description>Translation aperture size for this virtual address range, in units of 4 kiB (one flash sector).
+
+                            Bits 21:12 of the virtual address are compared to SIZE. Offsets greater than SIZE return a bus error, and do not cause a QSPI access.</description>
+                        <bitRange>[26:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>BASE</name>
+                        <description>Physical address base for this virtual address range, in units of 4 kiB (one flash sector).
+
+                            Taking a 24-bit virtual address, firstly bits 23:22 (the two MSBs) are masked to zero, and then BASE is added to bits 23:12 (the upper 12 bits) to form the physical address. Translation wraps on a 16 MiB boundary.</description>
+                        <bitRange>[11:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>ATRANS1</name>
+                <addressOffset>0x00000038</addressOffset>
+                <description>Configure address translation for XIP virtual addresses 0x400000 through 0x7fffff (a 4 MiB window starting at +4 MiB).
+
+                    Address translation allows a program image to be executed in place at multiple physical flash addresses (for example, a double-buffered flash image for over-the-air updates), without the overhead of position-independent code.
+
+                    At reset, the address translation registers are initialised to an identity mapping, so that they can be ignored if address translation is not required.
+
+                    Note that the XIP cache is fully virtually addressed, so a cache flush is required after changing the address translation.</description>
+                <resetValue>0x04000400</resetValue>
+                <fields>
+                    <field>
+                        <name>SIZE</name>
+                        <description>Translation aperture size for this virtual address range, in units of 4 kiB (one flash sector).
+
+                            Bits 21:12 of the virtual address are compared to SIZE. Offsets greater than SIZE return a bus error, and do not cause a QSPI access.</description>
+                        <bitRange>[26:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>BASE</name>
+                        <description>Physical address base for this virtual address range, in units of 4 kiB (one flash sector).
+
+                            Taking a 24-bit virtual address, firstly bits 23:22 (the two MSBs) are masked to zero, and then BASE is added to bits 23:12 (the upper 12 bits) to form the physical address. Translation wraps on a 16 MiB boundary.</description>
+                        <bitRange>[11:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>ATRANS2</name>
+                <addressOffset>0x0000003c</addressOffset>
+                <description>Configure address translation for XIP virtual addresses 0x800000 through 0xbfffff (a 4 MiB window starting at +8 MiB).
+
+                    Address translation allows a program image to be executed in place at multiple physical flash addresses (for example, a double-buffered flash image for over-the-air updates), without the overhead of position-independent code.
+
+                    At reset, the address translation registers are initialised to an identity mapping, so that they can be ignored if address translation is not required.
+
+                    Note that the XIP cache is fully virtually addressed, so a cache flush is required after changing the address translation.</description>
+                <resetValue>0x04000800</resetValue>
+                <fields>
+                    <field>
+                        <name>SIZE</name>
+                        <description>Translation aperture size for this virtual address range, in units of 4 kiB (one flash sector).
+
+                            Bits 21:12 of the virtual address are compared to SIZE. Offsets greater than SIZE return a bus error, and do not cause a QSPI access.</description>
+                        <bitRange>[26:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>BASE</name>
+                        <description>Physical address base for this virtual address range, in units of 4 kiB (one flash sector).
+
+                            Taking a 24-bit virtual address, firstly bits 23:22 (the two MSBs) are masked to zero, and then BASE is added to bits 23:12 (the upper 12 bits) to form the physical address. Translation wraps on a 16 MiB boundary.</description>
+                        <bitRange>[11:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>ATRANS3</name>
+                <addressOffset>0x00000040</addressOffset>
+                <description>Configure address translation for XIP virtual addresses 0xc00000 through 0xffffff (a 4 MiB window starting at +12 MiB).
+
+                    Address translation allows a program image to be executed in place at multiple physical flash addresses (for example, a double-buffered flash image for over-the-air updates), without the overhead of position-independent code.
+
+                    At reset, the address translation registers are initialised to an identity mapping, so that they can be ignored if address translation is not required.
+
+                    Note that the XIP cache is fully virtually addressed, so a cache flush is required after changing the address translation.</description>
+                <resetValue>0x04000c00</resetValue>
+                <fields>
+                    <field>
+                        <name>SIZE</name>
+                        <description>Translation aperture size for this virtual address range, in units of 4 kiB (one flash sector).
+
+                            Bits 21:12 of the virtual address are compared to SIZE. Offsets greater than SIZE return a bus error, and do not cause a QSPI access.</description>
+                        <bitRange>[26:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>BASE</name>
+                        <description>Physical address base for this virtual address range, in units of 4 kiB (one flash sector).
+
+                            Taking a 24-bit virtual address, firstly bits 23:22 (the two MSBs) are masked to zero, and then BASE is added to bits 23:12 (the upper 12 bits) to form the physical address. Translation wraps on a 16 MiB boundary.</description>
+                        <bitRange>[11:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>ATRANS4</name>
+                <addressOffset>0x00000044</addressOffset>
+                <description>Configure address translation for XIP virtual addresses 0x1000000 through 0x13fffff (a 4 MiB window starting at +16 MiB).
+
+                    Address translation allows a program image to be executed in place at multiple physical flash addresses (for example, a double-buffered flash image for over-the-air updates), without the overhead of position-independent code.
+
+                    At reset, the address translation registers are initialised to an identity mapping, so that they can be ignored if address translation is not required.
+
+                    Note that the XIP cache is fully virtually addressed, so a cache flush is required after changing the address translation.</description>
+                <resetValue>0x04000000</resetValue>
+                <fields>
+                    <field>
+                        <name>SIZE</name>
+                        <description>Translation aperture size for this virtual address range, in units of 4 kiB (one flash sector).
+
+                            Bits 21:12 of the virtual address are compared to SIZE. Offsets greater than SIZE return a bus error, and do not cause a QSPI access.</description>
+                        <bitRange>[26:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>BASE</name>
+                        <description>Physical address base for this virtual address range, in units of 4 kiB (one flash sector).
+
+                            Taking a 24-bit virtual address, firstly bits 23:22 (the two MSBs) are masked to zero, and then BASE is added to bits 23:12 (the upper 12 bits) to form the physical address. Translation wraps on a 16 MiB boundary.</description>
+                        <bitRange>[11:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>ATRANS5</name>
+                <addressOffset>0x00000048</addressOffset>
+                <description>Configure address translation for XIP virtual addresses 0x1400000 through 0x17fffff (a 4 MiB window starting at +20 MiB).
+
+                    Address translation allows a program image to be executed in place at multiple physical flash addresses (for example, a double-buffered flash image for over-the-air updates), without the overhead of position-independent code.
+
+                    At reset, the address translation registers are initialised to an identity mapping, so that they can be ignored if address translation is not required.
+
+                    Note that the XIP cache is fully virtually addressed, so a cache flush is required after changing the address translation.</description>
+                <resetValue>0x04000400</resetValue>
+                <fields>
+                    <field>
+                        <name>SIZE</name>
+                        <description>Translation aperture size for this virtual address range, in units of 4 kiB (one flash sector).
+
+                            Bits 21:12 of the virtual address are compared to SIZE. Offsets greater than SIZE return a bus error, and do not cause a QSPI access.</description>
+                        <bitRange>[26:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>BASE</name>
+                        <description>Physical address base for this virtual address range, in units of 4 kiB (one flash sector).
+
+                            Taking a 24-bit virtual address, firstly bits 23:22 (the two MSBs) are masked to zero, and then BASE is added to bits 23:12 (the upper 12 bits) to form the physical address. Translation wraps on a 16 MiB boundary.</description>
+                        <bitRange>[11:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>ATRANS6</name>
+                <addressOffset>0x0000004c</addressOffset>
+                <description>Configure address translation for XIP virtual addresses 0x1800000 through 0x1bfffff (a 4 MiB window starting at +24 MiB).
+
+                    Address translation allows a program image to be executed in place at multiple physical flash addresses (for example, a double-buffered flash image for over-the-air updates), without the overhead of position-independent code.
+
+                    At reset, the address translation registers are initialised to an identity mapping, so that they can be ignored if address translation is not required.
+
+                    Note that the XIP cache is fully virtually addressed, so a cache flush is required after changing the address translation.</description>
+                <resetValue>0x04000800</resetValue>
+                <fields>
+                    <field>
+                        <name>SIZE</name>
+                        <description>Translation aperture size for this virtual address range, in units of 4 kiB (one flash sector).
+
+                            Bits 21:12 of the virtual address are compared to SIZE. Offsets greater than SIZE return a bus error, and do not cause a QSPI access.</description>
+                        <bitRange>[26:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>BASE</name>
+                        <description>Physical address base for this virtual address range, in units of 4 kiB (one flash sector).
+
+                            Taking a 24-bit virtual address, firstly bits 23:22 (the two MSBs) are masked to zero, and then BASE is added to bits 23:12 (the upper 12 bits) to form the physical address. Translation wraps on a 16 MiB boundary.</description>
+                        <bitRange>[11:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>ATRANS7</name>
+                <addressOffset>0x00000050</addressOffset>
+                <description>Configure address translation for XIP virtual addresses 0x1c00000 through 0x1ffffff (a 4 MiB window starting at +28 MiB).
+
+                    Address translation allows a program image to be executed in place at multiple physical flash addresses (for example, a double-buffered flash image for over-the-air updates), without the overhead of position-independent code.
+
+                    At reset, the address translation registers are initialised to an identity mapping, so that they can be ignored if address translation is not required.
+
+                    Note that the XIP cache is fully virtually addressed, so a cache flush is required after changing the address translation.</description>
+                <resetValue>0x04000c00</resetValue>
+                <fields>
+                    <field>
+                        <name>SIZE</name>
+                        <description>Translation aperture size for this virtual address range, in units of 4 kiB (one flash sector).
+
+                            Bits 21:12 of the virtual address are compared to SIZE. Offsets greater than SIZE return a bus error, and do not cause a QSPI access.</description>
+                        <bitRange>[26:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>BASE</name>
+                        <description>Physical address base for this virtual address range, in units of 4 kiB (one flash sector).
+
+                            Taking a 24-bit virtual address, firstly bits 23:22 (the two MSBs) are masked to zero, and then BASE is added to bits 23:12 (the upper 12 bits) to form the physical address. Translation wraps on a 16 MiB boundary.</description>
+                        <bitRange>[11:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+        </registers>
+    </peripheral>
+    <peripheral>
+        <name>XIP_CTRL</name>
+        <description>QSPI flash execute-in-place block</description>
+        <baseAddress>0x400c8000</baseAddress>
+        <addressBlock>
+            <offset>0</offset>
+            <size>32</size>
+            <usage>registers</usage>
+        </addressBlock>
+        <registers>
+            <register>
+                <name>CTRL</name>
+                <addressOffset>0x00000000</addressOffset>
+                <description>Cache control register. Read-only from a Non-secure context.</description>
+                <resetValue>0x00000083</resetValue>
+                <fields>
+                    <field>
+                        <name>WRITABLE_M1</name>
+                        <description>If 1, enable writes to XIP memory window 1 (addresses 0x11000000 through 0x11ffffff, and their uncached mirrors). If 0, this region is read-only.
+
+                            XIP memory is *read-only by default*. This bit must be set to enable writes if a RAM device is attached on QSPI chip select 1.
+
+                            The default read-only behaviour avoids two issues with writing to a read-only QSPI device (e.g. flash). First, a write will initially appear to succeed due to caching, but the data will eventually be lost when the written line is evicted, causing unpredictable behaviour.
+
+                            Second, when a written line is evicted, it will cause a write command to be issued to the flash, which can break the flash out of its continuous read mode. After this point, flash reads will return garbage. This is a security concern, as it allows Non-secure software to break Secure flash reads if it has permission to write to any flash address.
+
+                            Note the read-only behaviour is implemented by downgrading writes to reads, so writes will still cause allocation of an address, but have no other effect.</description>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>WRITABLE_M0</name>
+                        <description>If 1, enable writes to XIP memory window 0 (addresses 0x10000000 through 0x10ffffff, and their uncached mirrors). If 0, this region is read-only.
+
+                            XIP memory is *read-only by default*. This bit must be set to enable writes if a RAM device is attached on QSPI chip select 0.
+
+                            The default read-only behaviour avoids two issues with writing to a read-only QSPI device (e.g. flash). First, a write will initially appear to succeed due to caching, but the data will eventually be lost when the written line is evicted, causing unpredictable behaviour.
+
+                            Second, when a written line is evicted, it will cause a write command to be issued to the flash, which can break the flash out of its continuous read mode. After this point, flash reads will return garbage. This is a security concern, as it allows Non-secure software to break Secure flash reads if it has permission to write to any flash address.
+
+                            Note the read-only behaviour is implemented by downgrading writes to reads, so writes will still cause allocation of an address, but have no other effect.</description>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SPLIT_WAYS</name>
+                        <description>When 1, route all cached+Secure accesses to way 0 of the cache, and route all cached+Non-secure accesses to way 1 of the cache.
+
+                            This partitions the cache into two half-sized direct-mapped regions, such that Non-secure code can not observe cache line state changes caused by Secure execution.
+
+                            A full cache flush is required when changing the value of SPLIT_WAYS. The flush should be performed whilst SPLIT_WAYS is 0, so that both cache ways are accessible for invalidation.</description>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>MAINT_NONSEC</name>
+                        <description>When 0, Non-secure accesses to the cache maintenance address window (addr[27] == 1, addr[26] == 0) will generate a bus error. When 1, Non-secure accesses can perform cache maintenance operations by writing to the cache maintenance address window.
+
+                            Cache maintenance operations may be used to corrupt Secure data by invalidating cache lines inappropriately, or map Secure content into a Non-secure region by pinning cache lines. Therefore this bit should generally be set to 0, unless Secure code is not using the cache.
+
+                            Care should also be taken to clear the cache data memory and tag memory before granting maintenance operations to Non-secure code.</description>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>NO_UNTRANSLATED_NONSEC</name>
+                        <description>When 1, Non-secure accesses to the uncached, untranslated window (addr[27:26] == 3) will generate a bus error.</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>NO_UNTRANSLATED_SEC</name>
+                        <description>When 1, Secure accesses to the uncached, untranslated window (addr[27:26] == 3) will generate a bus error.</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>NO_UNCACHED_NONSEC</name>
+                        <description>When 1, Non-secure accesses to the uncached window (addr[27:26] == 1) will generate a bus error. This may reduce the number of SAU/MPU/PMP regions required to protect flash contents.
+
+                            Note this does not disable access to the uncached, untranslated window -- see NO_UNTRANSLATED_SEC.</description>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>NO_UNCACHED_SEC</name>
+                        <description>When 1, Secure accesses to the uncached window (addr[27:26] == 1) will generate a bus error. This may reduce the number of SAU/MPU/PMP regions required to protect flash contents.
+
+                            Note this does not disable access to the uncached, untranslated window -- see NO_UNTRANSLATED_SEC.</description>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>POWER_DOWN</name>
+                        <description>When 1, the cache memories are powered down. They retain state, but can not be accessed. This reduces static power dissipation. Writing 1 to this bit forces CTRL_EN_SECURE and CTRL_EN_NONSECURE to 0, i.e. the cache cannot be enabled when powered down.</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>EN_NONSECURE</name>
+                        <description>When 1, enable the cache for Non-secure accesses. When enabled, Non-secure XIP accesses to the cached (addr[26] == 0) window will query the cache, and QSPI accesses are performed only if the requested data is not present. When disabled, Secure access ignore the cache contents, and always access the QSPI interface.
+
+                            Accesses to the uncached (addr[26] == 1) window will never query the cache, irrespective of this bit.</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>EN_SECURE</name>
+                        <description>When 1, enable the cache for Secure accesses. When enabled, Secure XIP accesses to the cached (addr[26] == 0) window will query the cache, and QSPI accesses are performed only if the requested data is not present. When disabled, Secure access ignore the cache contents, and always access the QSPI interface.
+
+                            Accesses to the uncached (addr[26] == 1) window will never query the cache, irrespective of this bit.
+
+                            There is no cache-as-SRAM address window. Cache lines are allocated for SRAM-like use by individually pinning them, and keeping the cache enabled.</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>STAT</name>
+                <addressOffset>0x00000008</addressOffset>
+                <resetValue>0x00000002</resetValue>
+                <fields>
+                    <field>
+                        <name>FIFO_FULL</name>
+                        <description>When 1, indicates the XIP streaming FIFO is completely full. 
+                            The streaming FIFO is 2 entries deep, so the full and empty 
+                            flag allow its level to be ascertained.</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>FIFO_EMPTY</name>
+                        <description>When 1, indicates the XIP streaming FIFO is completely empty.</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CTR_HIT</name>
+                <addressOffset>0x0000000c</addressOffset>
+                <description>Cache Hit counter</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CTR_HIT</name>
+                        <description>A 32 bit saturating counter that increments upon each cache hit, 
+                            i.e. when an XIP access is serviced directly from cached data. 
+                            Write any value to clear.</description>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CTR_ACC</name>
+                <addressOffset>0x00000010</addressOffset>
+                <description>Cache Access counter</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CTR_ACC</name>
+                        <description>A 32 bit saturating counter that increments upon each XIP access, 
+                            whether the cache is hit or not. This includes noncacheable accesses. 
+                            Write any value to clear.</description>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>STREAM_ADDR</name>
+                <addressOffset>0x00000014</addressOffset>
+                <description>FIFO stream address</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>STREAM_ADDR</name>
+                        <description>The address of the next word to be streamed from flash to the streaming FIFO. 
+                            Increments automatically after each flash access. 
+                            Write the initial access address here before starting a streaming read.</description>
+                        <bitRange>[31:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>STREAM_CTR</name>
+                <addressOffset>0x00000018</addressOffset>
+                <description>FIFO stream control</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>STREAM_CTR</name>
+                        <description>Write a nonzero value to start a streaming read. This will then 
+                            progress in the background, using flash idle cycles to transfer 
+                            a linear data block from flash to the streaming FIFO. 
+                            Decrements automatically (1 at a time) as the stream 
+                            progresses, and halts on reaching 0. 
+                            Write 0 to halt an in-progress stream, and discard any in-flight 
+                            read, so that a new stream can immediately be started (after 
+                            draining the FIFO and reinitialising STREAM_ADDR)</description>
+                        <bitRange>[21:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>STREAM_FIFO</name>
+                <addressOffset>0x0000001c</addressOffset>
+                <description>FIFO stream data</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>STREAM_FIFO</name>
+                        <description>Streamed data is buffered here, for retrieval by the system DMA. 
+                            This FIFO can also be accessed via the XIP_AUX slave, to avoid exposing 
+                            the DMA to bus stalls caused by other XIP traffic.</description>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-only</access>
+                        <readAction>modify</readAction>
+                    </field>
+                </fields>
+            </register>
+        </registers>
+    </peripheral>
+    <peripheral>
+        <name>XIP_AUX</name>
+        <description>Auxiliary DMA access to XIP FIFOs, via fast AHB bus access</description>
+        <baseAddress>0x50500000</baseAddress>
+        <addressBlock>
+            <offset>0</offset>
+            <size>12</size>
+            <usage>registers</usage>
+        </addressBlock>
+        <registers>
+            <register>
+                <name>STREAM</name>
+                <addressOffset>0x00000000</addressOffset>
+                <description>Read the XIP stream FIFO (fast bus access to XIP_CTRL_STREAM_FIFO)</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>STREAM</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-only</access>
+                        <readAction>modify</readAction>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>QMI_DIRECT_TX</name>
+                <addressOffset>0x00000004</addressOffset>
+                <description>Write to the QMI direct-mode TX FIFO (fast bus access to QMI_DIRECT_TX)</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>NOPUSH</name>
+                        <description>Inhibit the RX FIFO push that would correspond to this TX FIFO entry.
+
+                            Useful to avoid garbage appearing in the RX FIFO when pushing the command at the beginning of a SPI transfer.</description>
+                        <bitRange>[20:20]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>OE</name>
+                        <description>Output enable (active-high). For single width (SPI), this field is ignored, and SD0 is always set to output, with SD1 always set to input.
+
+                            For dual and quad width (DSPI/QSPI), this sets whether the relevant SDx pads are set to output whilst transferring this FIFO record. In this case the command/address should have OE set, and the data transfer should have OE set or clear depending on the direction of the transfer.</description>
+                        <bitRange>[19:19]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>DWIDTH</name>
+                        <description>Data width. If 0, hardware will transmit the 8 LSBs of the DIRECT_TX DATA field, and return an 8-bit value in the 8 LSBs of DIRECT_RX. If 1, the full 16-bit width is used. 8-bit and 16-bit transfers can be mixed freely.</description>
+                        <bitRange>[18:18]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>IWIDTH</name>
+                        <description>Configure whether this FIFO record is transferred with single/dual/quad interface width (0/1/2). Different widths can be mixed freely.</description>
+                        <bitRange>[17:16]</bitRange>
+                        <access>write-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>S</name>
+                                <value>0</value>
+                                <description>Single width</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>D</name>
+                                <value>1</value>
+                                <description>Dual width</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Q</name>
+                                <value>2</value>
+                                <description>Quad width</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>DATA</name>
+                        <description>Data pushed here will be clocked out falling edges of SCK (or before the very first rising edge of SCK, if this is the first pulse). For each byte clocked out, the interface will simultaneously sample one byte, on rising edges of SCK, and push this to the DIRECT_RX FIFO.
+
+                            For 16-bit data, the least-significant byte is transmitted first.</description>
+                        <bitRange>[15:0]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>QMI_DIRECT_RX</name>
+                <addressOffset>0x00000008</addressOffset>
+                <description>Read from the QMI direct-mode RX FIFO (fast bus access to QMI_DIRECT_RX)</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>QMI_DIRECT_RX</name>
+                        <description>With each byte clocked out on the serial interface, one byte will simultaneously be clocked in, and will appear in this FIFO. The serial interface will stall when this FIFO is full, to avoid dropping data.
+
+                            When 16-bit data is pushed into the TX FIFO, the corresponding RX FIFO push will also contain 16 bits of data. The least-significant byte is the first one received.</description>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-only</access>
+                        <readAction>modify</readAction>
+                    </field>
+                </fields>
+            </register>
+        </registers>
+    </peripheral>
+    <peripheral>
+        <name>SYSCFG</name>
+        <description>Register block for various chip control signals</description>
+        <baseAddress>0x40008000</baseAddress>
+        <addressBlock>
+            <offset>0</offset>
+            <size>24</size>
+            <usage>registers</usage>
+        </addressBlock>
+        <registers>
+            <register>
+                <name>PROC_CONFIG</name>
+                <addressOffset>0x00000000</addressOffset>
+                <description>Configuration for processors</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>PROC1_HALTED</name>
+                        <description>Indication that proc1 has halted</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>PROC0_HALTED</name>
+                        <description>Indication that proc0 has halted</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PROC_IN_SYNC_BYPASS</name>
+                <addressOffset>0x00000004</addressOffset>
+                <description>For each bit, if 1, bypass the input synchronizer between that GPIO 
+                    and the GPIO input register in the SIO. The input synchronizers should 
+                    generally be unbypassed, to avoid injecting metastabilities into processors. 
+                    If you&#39;re feeling brave, you can bypass to save two cycles of input 
+                    latency. This register applies to GPIO 0...31.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>GPIO</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PROC_IN_SYNC_BYPASS_HI</name>
+                <addressOffset>0x00000008</addressOffset>
+                <description>For each bit, if 1, bypass the input synchronizer between that GPIO 
+                    and the GPIO input register in the SIO. The input synchronizers should 
+                    generally be unbypassed, to avoid injecting metastabilities into processors. 
+                    If you&#39;re feeling brave, you can bypass to save two cycles of input 
+                    latency. This register applies to GPIO 32...47. USB GPIO 56..57 QSPI GPIO 58..63</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>QSPI_SD</name>
+                        <bitRange>[31:28]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>QSPI_CSN</name>
+                        <bitRange>[27:27]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>QSPI_SCK</name>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>USB_DM</name>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>USB_DP</name>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>DBGFORCE</name>
+                <addressOffset>0x0000000c</addressOffset>
+                <description>Directly control the chip SWD debug port</description>
+                <resetValue>0x00000006</resetValue>
+                <fields>
+                    <field>
+                        <name>ATTACH</name>
+                        <description>Attach chip debug port to syscfg controls, and disconnect it from external SWD pads.</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SWCLK</name>
+                        <description>Directly drive SWCLK, if ATTACH is set</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SWDI</name>
+                        <description>Directly drive SWDIO input, if ATTACH is set</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SWDO</name>
+                        <description>Observe the value of SWDIO output.</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>MEMPOWERDOWN</name>
+                <addressOffset>0x00000010</addressOffset>
+                <description>Control PD pins to memories. 
+                    Set high to put memories to a low power state. In this state the memories will retain contents but not be accessible 
+                    Use with caution</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>BOOTRAM</name>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ROM</name>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>USB</name>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SRAM9</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SRAM8</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SRAM7</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SRAM6</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SRAM5</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SRAM4</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SRAM3</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SRAM2</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SRAM1</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SRAM0</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>AUXCTRL</name>
+                <addressOffset>0x00000014</addressOffset>
+                <description>Auxiliary system control register</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>AUXCTRL</name>
+                        <description>* Bits 7:2: Reserved
+
+                            * Bit 1: When clear, the LPOSC output is XORed into the TRNG ROSC output as an additional, uncorrelated entropy source. When set, this behaviour is disabled.
+
+                            * Bit 0: Force POWMAN clock to switch to LPOSC, by asserting its WDRESET input. This must be set before initiating a watchdog reset of the RSM from a stage that includes CLOCKS, if POWMAN is running from clk_ref at the point that the watchdog reset takes place. Otherwise, the short pulse generated on clk_ref by the reset of the CLOCKS block may affect POWMAN register state.</description>
+                        <bitRange>[7:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+        </registers>
+    </peripheral>
+    <peripheral>
+        <name>XOSC</name>
+        <description>Controls the crystal oscillator</description>
+        <baseAddress>0x40048000</baseAddress>
+        <addressBlock>
+            <offset>0</offset>
+            <size>20</size>
+            <usage>registers</usage>
+        </addressBlock>
+        <registers>
+            <register>
+                <name>CTRL</name>
+                <addressOffset>0x00000000</addressOffset>
+                <description>Crystal Oscillator Control</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>ENABLE</name>
+                        <description>On power-up this field is initialised to DISABLE and the chip runs from the ROSC. 
+                            If the chip has subsequently been programmed to run from the XOSC then setting this field to DISABLE may lock-up the chip. If  this is a concern then run the clk_ref from the ROSC and enable the clk_sys RESUS feature. 
+                            The 12-bit code is intended to give some protection against accidental writes. An invalid setting will retain the previous value. The actual value being used can be read from STATUS_ENABLED</description>
+                        <bitRange>[23:12]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>DISABLE</name>
+                                <value>3358</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ENABLE</name>
+                                <value>4011</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>FREQ_RANGE</name>
+                        <description>The 12-bit code is intended to give some protection against accidental writes. An invalid setting will retain the previous value. The actual value being used can be read from STATUS_FREQ_RANGE</description>
+                        <bitRange>[11:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>1_15MHZ</name>
+                                <value>2720</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>10_30MHZ</name>
+                                <value>2721</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>25_60MHZ</name>
+                                <value>2722</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>40_100MHZ</name>
+                                <value>2723</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>STATUS</name>
+                <addressOffset>0x00000004</addressOffset>
+                <description>Crystal Oscillator Status</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>STABLE</name>
+                        <description>Oscillator is running and stable</description>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>BADWRITE</name>
+                        <description>An invalid value has been written to CTRL_ENABLE or CTRL_FREQ_RANGE or DORMANT</description>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>ENABLED</name>
+                        <description>Oscillator is enabled but not necessarily running and stable, resets to 0</description>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>FREQ_RANGE</name>
+                        <description>The current frequency range setting</description>
+                        <bitRange>[1:0]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>1_15MHZ</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>10_30MHZ</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>25_60MHZ</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>40_100MHZ</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>DORMANT</name>
+                <addressOffset>0x00000008</addressOffset>
+                <description>Crystal Oscillator pause control</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>DORMANT</name>
+                        <description>This is used to save power by pausing the XOSC 
+                            On power-up this field is initialised to WAKE 
+                            An invalid write will also select WAKE 
+                            Warning: stop the PLLs before selecting dormant mode 
+                            Warning: setup the irq before selecting dormant mode</description>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>dormant</name>
+                                <value>1668246881</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>WAKE</name>
+                                <value>2002873189</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>STARTUP</name>
+                <addressOffset>0x0000000c</addressOffset>
+                <description>Controls the startup delay</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>X4</name>
+                        <description>Multiplies the startup_delay by 4, just in case. The reset value is controlled by a mask-programmable tiecell and is provided in case we are booting from XOSC and the default startup delay is insufficient. The reset value is 0x0.</description>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DELAY</name>
+                        <description>in multiples of 256*xtal_period. The reset value of 0xc4 corresponds to approx 50 000 cycles.</description>
+                        <bitRange>[13:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>COUNT</name>
+                <addressOffset>0x00000010</addressOffset>
+                <description>A down counter running at the xosc frequency which counts to zero and stops. 
+                    Can be used for short software pauses when setting up time sensitive hardware. 
+                    To start the counter, write a non-zero value. Reads will return 1 while the count is running and 0 when it has finished. 
+                    Minimum count value is 4. Count values &lt;4 will be treated as count value =4. 
+                    Note that synchronisation to the register clock domain costs 2 register clock cycles and the counter cannot compensate for that.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>COUNT</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+        </registers>
+    </peripheral>
+    <peripheral>
+        <name>PLL_SYS</name>
+        <baseAddress>0x40050000</baseAddress>
+        <addressBlock>
+            <offset>0</offset>
+            <size>32</size>
+            <usage>registers</usage>
+        </addressBlock>
+        <interrupt>
+            <name>PLL_SYS_IRQ</name>
+            <value>42</value>
+        </interrupt>
+        <registers>
+            <register>
+                <name>CS</name>
+                <addressOffset>0x00000000</addressOffset>
+                <description>Control and Status 
+                    GENERAL CONSTRAINTS: 
+                    Reference clock frequency min=5MHz, max=800MHz 
+                    Feedback divider min=16, max=320 
+                    VCO frequency min=750MHz, max=1600MHz</description>
+                <resetValue>0x00000001</resetValue>
+                <fields>
+                    <field>
+                        <name>LOCK</name>
+                        <description>PLL is locked</description>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>LOCK_N</name>
+                        <description>PLL is not locked 
+                            Ideally this is cleared when PLL lock is seen and this should never normally be set</description>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>BYPASS</name>
+                        <description>Passes the reference clock to the output instead of the divided VCO. The VCO continues to run so the user can switch between the reference clock and the divided VCO but the output will glitch when doing so.</description>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>REFDIV</name>
+                        <description>Divides the PLL input reference clock. 
+                            Behaviour is undefined for div=0. 
+                            PLL output will be unpredictable during refdiv changes, wait for lock=1 before using it.</description>
+                        <bitRange>[5:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PWR</name>
+                <addressOffset>0x00000004</addressOffset>
+                <description>Controls the PLL power modes.</description>
+                <resetValue>0x0000002d</resetValue>
+                <fields>
+                    <field>
+                        <name>VCOPD</name>
+                        <description>PLL VCO powerdown 
+                            To save power set high when PLL output not required or bypass=1.</description>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>POSTDIVPD</name>
+                        <description>PLL post divider powerdown 
+                            To save power set high when PLL output not required or bypass=1.</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DSMPD</name>
+                        <description>PLL DSM powerdown 
+                            Nothing is achieved by setting this low.</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PD</name>
+                        <description>PLL powerdown 
+                            To save power set high when PLL output not required.</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>FBDIV_INT</name>
+                <addressOffset>0x00000008</addressOffset>
+                <description>Feedback divisor 
+                    (note: this PLL does not support fractional division)</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>FBDIV_INT</name>
+                        <description>see ctrl reg description for constraints</description>
+                        <bitRange>[11:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PRIM</name>
+                <addressOffset>0x0000000c</addressOffset>
+                <description>Controls the PLL post dividers for the primary output 
+                    (note: this PLL does not have a secondary output) 
+                    the primary output is driven from VCO divided by postdiv1*postdiv2</description>
+                <resetValue>0x00077000</resetValue>
+                <fields>
+                    <field>
+                        <name>POSTDIV1</name>
+                        <description>divide by 1-7</description>
+                        <bitRange>[18:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>POSTDIV2</name>
+                        <description>divide by 1-7</description>
+                        <bitRange>[14:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INTR</name>
+                <addressOffset>0x00000010</addressOffset>
+                <description>Raw Interrupts</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>LOCK_N_STICKY</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INTE</name>
+                <addressOffset>0x00000014</addressOffset>
+                <description>Interrupt Enable</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>LOCK_N_STICKY</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INTF</name>
+                <addressOffset>0x00000018</addressOffset>
+                <description>Interrupt Force</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>LOCK_N_STICKY</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INTS</name>
+                <addressOffset>0x0000001c</addressOffset>
+                <description>Interrupt status after masking &amp; forcing</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>LOCK_N_STICKY</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+        </registers>
+    </peripheral>
+    <peripheral derivedFrom="PLL_SYS">
+        <name>PLL_USB</name>
+        <baseAddress>0x40058000</baseAddress>
+        <interrupt>
+        <name>PLL_USB_IRQ</name>
+        <value>43</value>
+    </interrupt>
+    </peripheral>
+    <peripheral>
+        <name>ACCESSCTRL</name>
+        <description>Hardware access control registers</description>
+        <baseAddress>0x40060000</baseAddress>
+        <addressBlock>
+            <offset>0</offset>
+            <size>236</size>
+            <usage>registers</usage>
+        </addressBlock>
+        <registers>
+            <register>
+                <name>LOCK</name>
+                <addressOffset>0x00000000</addressOffset>
+                <description>Once a LOCK bit is written to 1, ACCESSCTRL silently ignores writes from that master. LOCK is writable only by a Secure, Privileged processor or debugger.
+
+                    LOCK bits are only writable when their value is zero. Once set, they can never be cleared, except by a full reset of ACCESSCTRL
+
+                    Setting the LOCK bit does not affect whether an access raises a bus error. Unprivileged writes, or writes from the DMA, will continue to raise bus errors. All other accesses will continue not to.</description>
+                <resetValue>0x00000004</resetValue>
+                <fields>
+                    <field>
+                        <name>DEBUG</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DMA</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CORE1</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CORE0</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>FORCE_CORE_NS</name>
+                <addressOffset>0x00000004</addressOffset>
+                <description>Force core 1&#39;s bus accesses to always be Non-secure, no matter the core&#39;s internal state.
+
+                    Useful for schemes where one core is designated as the Non-secure core, since some peripherals may filter individual registers internally based on security state but not on master ID.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CORE1</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CFGRESET</name>
+                <addressOffset>0x00000008</addressOffset>
+                <description>Write 1 to reset all ACCESSCTRL configuration, except for the LOCK and FORCE_CORE_NS registers.
+
+                    This bit is used in the RP2350 bootrom to quickly restore ACCESSCTRL to a known state during the boot path.
+
+                    Note that, like all registers in ACCESSCTRL, this register is not writable when the writer&#39;s corresponding LOCK bit is set, therefore a master which has been locked out of ACCESSCTRL can not use the CFGRESET register to disturb its contents.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CFGRESET</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO_NSMASK0</name>
+                <addressOffset>0x0000000c</addressOffset>
+                <description>Control whether GPIO0...31 are accessible to Non-secure code. Writable only by a Secure, Privileged processor or debugger.
+
+                    0 -&gt; Secure access only
+
+                    1 -&gt; Secure + Non-secure access</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>GPIO_NSMASK0</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO_NSMASK1</name>
+                <addressOffset>0x00000010</addressOffset>
+                <description>Control whether GPIO32..47 are accessible to Non-secure code, and whether QSPI and USB bitbang are accessible through the Non-secure SIO. Writable only by a Secure, Privileged processor or debugger.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>QSPI_SD</name>
+                        <bitRange>[31:28]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>QSPI_CSN</name>
+                        <bitRange>[27:27]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>QSPI_SCK</name>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>USB_DM</name>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>USB_DP</name>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>ROM</name>
+                <addressOffset>0x00000014</addressOffset>
+                <description>Control whether debugger, DMA, core 0 and core 1 can access ROM, and at what security/privilege levels they can do so.
+
+                    Defaults to fully open access.
+
+                    This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set.</description>
+                <resetValue>0x000000ff</resetValue>
+                <fields>
+                    <field>
+                        <name>DBG</name>
+                        <description>If 1, ROM can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DMA</name>
+                        <description>If 1, ROM can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CORE1</name>
+                        <description>If 1, ROM can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CORE0</name>
+                        <description>If 1, ROM can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SP</name>
+                        <description>If 1, ROM can be accessed from a Secure, Privileged context.</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SU</name>
+                        <description>If 1, and SP is also set, ROM can be accessed from a Secure, Unprivileged context.</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>NSP</name>
+                        <description>If 1, ROM can be accessed from a Non-secure, Privileged context.</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>NSU</name>
+                        <description>If 1, and NSP is also set, ROM can be accessed from a Non-secure, Unprivileged context.
+
+                            This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set.</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>XIP_MAIN</name>
+                <addressOffset>0x00000018</addressOffset>
+                <description>Control whether debugger, DMA, core 0 and core 1 can access XIP_MAIN, and at what security/privilege levels they can do so.
+
+                    Defaults to fully open access.
+
+                    This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set.</description>
+                <resetValue>0x000000ff</resetValue>
+                <fields>
+                    <field>
+                        <name>DBG</name>
+                        <description>If 1, XIP_MAIN can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DMA</name>
+                        <description>If 1, XIP_MAIN can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CORE1</name>
+                        <description>If 1, XIP_MAIN can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CORE0</name>
+                        <description>If 1, XIP_MAIN can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SP</name>
+                        <description>If 1, XIP_MAIN can be accessed from a Secure, Privileged context.</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SU</name>
+                        <description>If 1, and SP is also set, XIP_MAIN can be accessed from a Secure, Unprivileged context.</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>NSP</name>
+                        <description>If 1, XIP_MAIN can be accessed from a Non-secure, Privileged context.</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>NSU</name>
+                        <description>If 1, and NSP is also set, XIP_MAIN can be accessed from a Non-secure, Unprivileged context.
+
+                            This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set.</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SRAM0</name>
+                <addressOffset>0x0000001c</addressOffset>
+                <description>Control whether debugger, DMA, core 0 and core 1 can access SRAM0, and at what security/privilege levels they can do so.
+
+                    Defaults to fully open access.
+
+                    This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set.</description>
+                <resetValue>0x000000ff</resetValue>
+                <fields>
+                    <field>
+                        <name>DBG</name>
+                        <description>If 1, SRAM0 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DMA</name>
+                        <description>If 1, SRAM0 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CORE1</name>
+                        <description>If 1, SRAM0 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CORE0</name>
+                        <description>If 1, SRAM0 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SP</name>
+                        <description>If 1, SRAM0 can be accessed from a Secure, Privileged context.</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SU</name>
+                        <description>If 1, and SP is also set, SRAM0 can be accessed from a Secure, Unprivileged context.</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>NSP</name>
+                        <description>If 1, SRAM0 can be accessed from a Non-secure, Privileged context.</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>NSU</name>
+                        <description>If 1, and NSP is also set, SRAM0 can be accessed from a Non-secure, Unprivileged context.
+
+                            This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set.</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SRAM1</name>
+                <addressOffset>0x00000020</addressOffset>
+                <description>Control whether debugger, DMA, core 0 and core 1 can access SRAM1, and at what security/privilege levels they can do so.
+
+                    Defaults to fully open access.
+
+                    This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set.</description>
+                <resetValue>0x000000ff</resetValue>
+                <fields>
+                    <field>
+                        <name>DBG</name>
+                        <description>If 1, SRAM1 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DMA</name>
+                        <description>If 1, SRAM1 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CORE1</name>
+                        <description>If 1, SRAM1 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CORE0</name>
+                        <description>If 1, SRAM1 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SP</name>
+                        <description>If 1, SRAM1 can be accessed from a Secure, Privileged context.</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SU</name>
+                        <description>If 1, and SP is also set, SRAM1 can be accessed from a Secure, Unprivileged context.</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>NSP</name>
+                        <description>If 1, SRAM1 can be accessed from a Non-secure, Privileged context.</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>NSU</name>
+                        <description>If 1, and NSP is also set, SRAM1 can be accessed from a Non-secure, Unprivileged context.
+
+                            This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set.</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SRAM2</name>
+                <addressOffset>0x00000024</addressOffset>
+                <description>Control whether debugger, DMA, core 0 and core 1 can access SRAM2, and at what security/privilege levels they can do so.
+
+                    Defaults to fully open access.
+
+                    This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set.</description>
+                <resetValue>0x000000ff</resetValue>
+                <fields>
+                    <field>
+                        <name>DBG</name>
+                        <description>If 1, SRAM2 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DMA</name>
+                        <description>If 1, SRAM2 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CORE1</name>
+                        <description>If 1, SRAM2 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CORE0</name>
+                        <description>If 1, SRAM2 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SP</name>
+                        <description>If 1, SRAM2 can be accessed from a Secure, Privileged context.</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SU</name>
+                        <description>If 1, and SP is also set, SRAM2 can be accessed from a Secure, Unprivileged context.</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>NSP</name>
+                        <description>If 1, SRAM2 can be accessed from a Non-secure, Privileged context.</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>NSU</name>
+                        <description>If 1, and NSP is also set, SRAM2 can be accessed from a Non-secure, Unprivileged context.
+
+                            This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set.</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SRAM3</name>
+                <addressOffset>0x00000028</addressOffset>
+                <description>Control whether debugger, DMA, core 0 and core 1 can access SRAM3, and at what security/privilege levels they can do so.
+
+                    Defaults to fully open access.
+
+                    This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set.</description>
+                <resetValue>0x000000ff</resetValue>
+                <fields>
+                    <field>
+                        <name>DBG</name>
+                        <description>If 1, SRAM3 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DMA</name>
+                        <description>If 1, SRAM3 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CORE1</name>
+                        <description>If 1, SRAM3 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CORE0</name>
+                        <description>If 1, SRAM3 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SP</name>
+                        <description>If 1, SRAM3 can be accessed from a Secure, Privileged context.</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SU</name>
+                        <description>If 1, and SP is also set, SRAM3 can be accessed from a Secure, Unprivileged context.</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>NSP</name>
+                        <description>If 1, SRAM3 can be accessed from a Non-secure, Privileged context.</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>NSU</name>
+                        <description>If 1, and NSP is also set, SRAM3 can be accessed from a Non-secure, Unprivileged context.
+
+                            This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set.</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SRAM4</name>
+                <addressOffset>0x0000002c</addressOffset>
+                <description>Control whether debugger, DMA, core 0 and core 1 can access SRAM4, and at what security/privilege levels they can do so.
+
+                    Defaults to fully open access.
+
+                    This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set.</description>
+                <resetValue>0x000000ff</resetValue>
+                <fields>
+                    <field>
+                        <name>DBG</name>
+                        <description>If 1, SRAM4 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DMA</name>
+                        <description>If 1, SRAM4 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CORE1</name>
+                        <description>If 1, SRAM4 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CORE0</name>
+                        <description>If 1, SRAM4 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SP</name>
+                        <description>If 1, SRAM4 can be accessed from a Secure, Privileged context.</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SU</name>
+                        <description>If 1, and SP is also set, SRAM4 can be accessed from a Secure, Unprivileged context.</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>NSP</name>
+                        <description>If 1, SRAM4 can be accessed from a Non-secure, Privileged context.</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>NSU</name>
+                        <description>If 1, and NSP is also set, SRAM4 can be accessed from a Non-secure, Unprivileged context.
+
+                            This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set.</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SRAM5</name>
+                <addressOffset>0x00000030</addressOffset>
+                <description>Control whether debugger, DMA, core 0 and core 1 can access SRAM5, and at what security/privilege levels they can do so.
+
+                    Defaults to fully open access.
+
+                    This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set.</description>
+                <resetValue>0x000000ff</resetValue>
+                <fields>
+                    <field>
+                        <name>DBG</name>
+                        <description>If 1, SRAM5 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DMA</name>
+                        <description>If 1, SRAM5 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CORE1</name>
+                        <description>If 1, SRAM5 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CORE0</name>
+                        <description>If 1, SRAM5 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SP</name>
+                        <description>If 1, SRAM5 can be accessed from a Secure, Privileged context.</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SU</name>
+                        <description>If 1, and SP is also set, SRAM5 can be accessed from a Secure, Unprivileged context.</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>NSP</name>
+                        <description>If 1, SRAM5 can be accessed from a Non-secure, Privileged context.</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>NSU</name>
+                        <description>If 1, and NSP is also set, SRAM5 can be accessed from a Non-secure, Unprivileged context.
+
+                            This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set.</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SRAM6</name>
+                <addressOffset>0x00000034</addressOffset>
+                <description>Control whether debugger, DMA, core 0 and core 1 can access SRAM6, and at what security/privilege levels they can do so.
+
+                    Defaults to fully open access.
+
+                    This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set.</description>
+                <resetValue>0x000000ff</resetValue>
+                <fields>
+                    <field>
+                        <name>DBG</name>
+                        <description>If 1, SRAM6 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DMA</name>
+                        <description>If 1, SRAM6 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CORE1</name>
+                        <description>If 1, SRAM6 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CORE0</name>
+                        <description>If 1, SRAM6 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SP</name>
+                        <description>If 1, SRAM6 can be accessed from a Secure, Privileged context.</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SU</name>
+                        <description>If 1, and SP is also set, SRAM6 can be accessed from a Secure, Unprivileged context.</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>NSP</name>
+                        <description>If 1, SRAM6 can be accessed from a Non-secure, Privileged context.</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>NSU</name>
+                        <description>If 1, and NSP is also set, SRAM6 can be accessed from a Non-secure, Unprivileged context.
+
+                            This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set.</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SRAM7</name>
+                <addressOffset>0x00000038</addressOffset>
+                <description>Control whether debugger, DMA, core 0 and core 1 can access SRAM7, and at what security/privilege levels they can do so.
+
+                    Defaults to fully open access.
+
+                    This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set.</description>
+                <resetValue>0x000000ff</resetValue>
+                <fields>
+                    <field>
+                        <name>DBG</name>
+                        <description>If 1, SRAM7 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DMA</name>
+                        <description>If 1, SRAM7 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CORE1</name>
+                        <description>If 1, SRAM7 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CORE0</name>
+                        <description>If 1, SRAM7 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SP</name>
+                        <description>If 1, SRAM7 can be accessed from a Secure, Privileged context.</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SU</name>
+                        <description>If 1, and SP is also set, SRAM7 can be accessed from a Secure, Unprivileged context.</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>NSP</name>
+                        <description>If 1, SRAM7 can be accessed from a Non-secure, Privileged context.</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>NSU</name>
+                        <description>If 1, and NSP is also set, SRAM7 can be accessed from a Non-secure, Unprivileged context.
+
+                            This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set.</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SRAM8</name>
+                <addressOffset>0x0000003c</addressOffset>
+                <description>Control whether debugger, DMA, core 0 and core 1 can access SRAM8, and at what security/privilege levels they can do so.
+
+                    Defaults to fully open access.
+
+                    This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set.</description>
+                <resetValue>0x000000ff</resetValue>
+                <fields>
+                    <field>
+                        <name>DBG</name>
+                        <description>If 1, SRAM8 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DMA</name>
+                        <description>If 1, SRAM8 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CORE1</name>
+                        <description>If 1, SRAM8 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CORE0</name>
+                        <description>If 1, SRAM8 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SP</name>
+                        <description>If 1, SRAM8 can be accessed from a Secure, Privileged context.</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SU</name>
+                        <description>If 1, and SP is also set, SRAM8 can be accessed from a Secure, Unprivileged context.</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>NSP</name>
+                        <description>If 1, SRAM8 can be accessed from a Non-secure, Privileged context.</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>NSU</name>
+                        <description>If 1, and NSP is also set, SRAM8 can be accessed from a Non-secure, Unprivileged context.
+
+                            This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set.</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SRAM9</name>
+                <addressOffset>0x00000040</addressOffset>
+                <description>Control whether debugger, DMA, core 0 and core 1 can access SRAM9, and at what security/privilege levels they can do so.
+
+                    Defaults to fully open access.
+
+                    This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set.</description>
+                <resetValue>0x000000ff</resetValue>
+                <fields>
+                    <field>
+                        <name>DBG</name>
+                        <description>If 1, SRAM9 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DMA</name>
+                        <description>If 1, SRAM9 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CORE1</name>
+                        <description>If 1, SRAM9 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CORE0</name>
+                        <description>If 1, SRAM9 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SP</name>
+                        <description>If 1, SRAM9 can be accessed from a Secure, Privileged context.</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SU</name>
+                        <description>If 1, and SP is also set, SRAM9 can be accessed from a Secure, Unprivileged context.</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>NSP</name>
+                        <description>If 1, SRAM9 can be accessed from a Non-secure, Privileged context.</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>NSU</name>
+                        <description>If 1, and NSP is also set, SRAM9 can be accessed from a Non-secure, Unprivileged context.
+
+                            This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set.</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>DMA</name>
+                <addressOffset>0x00000044</addressOffset>
+                <description>Control whether debugger, DMA, core 0 and core 1 can access DMA, and at what security/privilege levels they can do so.
+
+                    Defaults to Secure access from any master.
+
+                    This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set.</description>
+                <resetValue>0x000000fc</resetValue>
+                <fields>
+                    <field>
+                        <name>DBG</name>
+                        <description>If 1, DMA can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DMA</name>
+                        <description>If 1, DMA can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CORE1</name>
+                        <description>If 1, DMA can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CORE0</name>
+                        <description>If 1, DMA can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SP</name>
+                        <description>If 1, DMA can be accessed from a Secure, Privileged context.</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SU</name>
+                        <description>If 1, and SP is also set, DMA can be accessed from a Secure, Unprivileged context.</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>NSP</name>
+                        <description>If 1, DMA can be accessed from a Non-secure, Privileged context.</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>NSU</name>
+                        <description>If 1, and NSP is also set, DMA can be accessed from a Non-secure, Unprivileged context.
+
+                            This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set.</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>USBCTRL</name>
+                <addressOffset>0x00000048</addressOffset>
+                <description>Control whether debugger, DMA, core 0 and core 1 can access USBCTRL, and at what security/privilege levels they can do so.
+
+                    Defaults to Secure access from any master.
+
+                    This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set.</description>
+                <resetValue>0x000000fc</resetValue>
+                <fields>
+                    <field>
+                        <name>DBG</name>
+                        <description>If 1, USBCTRL can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DMA</name>
+                        <description>If 1, USBCTRL can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CORE1</name>
+                        <description>If 1, USBCTRL can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CORE0</name>
+                        <description>If 1, USBCTRL can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SP</name>
+                        <description>If 1, USBCTRL can be accessed from a Secure, Privileged context.</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SU</name>
+                        <description>If 1, and SP is also set, USBCTRL can be accessed from a Secure, Unprivileged context.</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>NSP</name>
+                        <description>If 1, USBCTRL can be accessed from a Non-secure, Privileged context.</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>NSU</name>
+                        <description>If 1, and NSP is also set, USBCTRL can be accessed from a Non-secure, Unprivileged context.
+
+                            This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set.</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PIO0</name>
+                <addressOffset>0x0000004c</addressOffset>
+                <description>Control whether debugger, DMA, core 0 and core 1 can access PIO0, and at what security/privilege levels they can do so.
+
+                    Defaults to Secure access from any master.
+
+                    This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set.</description>
+                <resetValue>0x000000fc</resetValue>
+                <fields>
+                    <field>
+                        <name>DBG</name>
+                        <description>If 1, PIO0 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DMA</name>
+                        <description>If 1, PIO0 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CORE1</name>
+                        <description>If 1, PIO0 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CORE0</name>
+                        <description>If 1, PIO0 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SP</name>
+                        <description>If 1, PIO0 can be accessed from a Secure, Privileged context.</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SU</name>
+                        <description>If 1, and SP is also set, PIO0 can be accessed from a Secure, Unprivileged context.</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>NSP</name>
+                        <description>If 1, PIO0 can be accessed from a Non-secure, Privileged context.</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>NSU</name>
+                        <description>If 1, and NSP is also set, PIO0 can be accessed from a Non-secure, Unprivileged context.
+
+                            This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set.</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PIO1</name>
+                <addressOffset>0x00000050</addressOffset>
+                <description>Control whether debugger, DMA, core 0 and core 1 can access PIO1, and at what security/privilege levels they can do so.
+
+                    Defaults to Secure access from any master.
+
+                    This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set.</description>
+                <resetValue>0x000000fc</resetValue>
+                <fields>
+                    <field>
+                        <name>DBG</name>
+                        <description>If 1, PIO1 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DMA</name>
+                        <description>If 1, PIO1 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CORE1</name>
+                        <description>If 1, PIO1 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CORE0</name>
+                        <description>If 1, PIO1 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SP</name>
+                        <description>If 1, PIO1 can be accessed from a Secure, Privileged context.</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SU</name>
+                        <description>If 1, and SP is also set, PIO1 can be accessed from a Secure, Unprivileged context.</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>NSP</name>
+                        <description>If 1, PIO1 can be accessed from a Non-secure, Privileged context.</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>NSU</name>
+                        <description>If 1, and NSP is also set, PIO1 can be accessed from a Non-secure, Unprivileged context.
+
+                            This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set.</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PIO2</name>
+                <addressOffset>0x00000054</addressOffset>
+                <description>Control whether debugger, DMA, core 0 and core 1 can access PIO2, and at what security/privilege levels they can do so.
+
+                    Defaults to Secure access from any master.
+
+                    This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set.</description>
+                <resetValue>0x000000fc</resetValue>
+                <fields>
+                    <field>
+                        <name>DBG</name>
+                        <description>If 1, PIO2 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DMA</name>
+                        <description>If 1, PIO2 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CORE1</name>
+                        <description>If 1, PIO2 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CORE0</name>
+                        <description>If 1, PIO2 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SP</name>
+                        <description>If 1, PIO2 can be accessed from a Secure, Privileged context.</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SU</name>
+                        <description>If 1, and SP is also set, PIO2 can be accessed from a Secure, Unprivileged context.</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>NSP</name>
+                        <description>If 1, PIO2 can be accessed from a Non-secure, Privileged context.</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>NSU</name>
+                        <description>If 1, and NSP is also set, PIO2 can be accessed from a Non-secure, Unprivileged context.
+
+                            This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set.</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CORESIGHT_TRACE</name>
+                <addressOffset>0x00000058</addressOffset>
+                <description>Control whether debugger, DMA, core 0 and core 1 can access CORESIGHT_TRACE, and at what security/privilege levels they can do so.
+
+                    Defaults to Secure, Privileged processor or debug access only.
+
+                    This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set.</description>
+                <resetValue>0x000000b8</resetValue>
+                <fields>
+                    <field>
+                        <name>DBG</name>
+                        <description>If 1, CORESIGHT_TRACE can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DMA</name>
+                        <description>If 1, CORESIGHT_TRACE can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CORE1</name>
+                        <description>If 1, CORESIGHT_TRACE can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CORE0</name>
+                        <description>If 1, CORESIGHT_TRACE can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SP</name>
+                        <description>If 1, CORESIGHT_TRACE can be accessed from a Secure, Privileged context.</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SU</name>
+                        <description>If 1, and SP is also set, CORESIGHT_TRACE can be accessed from a Secure, Unprivileged context.</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>NSP</name>
+                        <description>If 1, CORESIGHT_TRACE can be accessed from a Non-secure, Privileged context.</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>NSU</name>
+                        <description>If 1, and NSP is also set, CORESIGHT_TRACE can be accessed from a Non-secure, Unprivileged context.
+
+                            This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set.</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CORESIGHT_PERIPH</name>
+                <addressOffset>0x0000005c</addressOffset>
+                <description>Control whether debugger, DMA, core 0 and core 1 can access CORESIGHT_PERIPH, and at what security/privilege levels they can do so.
+
+                    Defaults to Secure, Privileged processor or debug access only.
+
+                    This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set.</description>
+                <resetValue>0x000000b8</resetValue>
+                <fields>
+                    <field>
+                        <name>DBG</name>
+                        <description>If 1, CORESIGHT_PERIPH can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DMA</name>
+                        <description>If 1, CORESIGHT_PERIPH can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CORE1</name>
+                        <description>If 1, CORESIGHT_PERIPH can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CORE0</name>
+                        <description>If 1, CORESIGHT_PERIPH can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SP</name>
+                        <description>If 1, CORESIGHT_PERIPH can be accessed from a Secure, Privileged context.</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SU</name>
+                        <description>If 1, and SP is also set, CORESIGHT_PERIPH can be accessed from a Secure, Unprivileged context.</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>NSP</name>
+                        <description>If 1, CORESIGHT_PERIPH can be accessed from a Non-secure, Privileged context.</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>NSU</name>
+                        <description>If 1, and NSP is also set, CORESIGHT_PERIPH can be accessed from a Non-secure, Unprivileged context.
+
+                            This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set.</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SYSINFO</name>
+                <addressOffset>0x00000060</addressOffset>
+                <description>Control whether debugger, DMA, core 0 and core 1 can access SYSINFO, and at what security/privilege levels they can do so.
+
+                    Defaults to fully open access.
+
+                    This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set.</description>
+                <resetValue>0x000000ff</resetValue>
+                <fields>
+                    <field>
+                        <name>DBG</name>
+                        <description>If 1, SYSINFO can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DMA</name>
+                        <description>If 1, SYSINFO can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CORE1</name>
+                        <description>If 1, SYSINFO can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CORE0</name>
+                        <description>If 1, SYSINFO can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SP</name>
+                        <description>If 1, SYSINFO can be accessed from a Secure, Privileged context.</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SU</name>
+                        <description>If 1, and SP is also set, SYSINFO can be accessed from a Secure, Unprivileged context.</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>NSP</name>
+                        <description>If 1, SYSINFO can be accessed from a Non-secure, Privileged context.</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>NSU</name>
+                        <description>If 1, and NSP is also set, SYSINFO can be accessed from a Non-secure, Unprivileged context.
+
+                            This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set.</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>RESETS</name>
+                <addressOffset>0x00000064</addressOffset>
+                <description>Control whether debugger, DMA, core 0 and core 1 can access RESETS, and at what security/privilege levels they can do so.
+
+                    Defaults to Secure access from any master.
+
+                    This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set.</description>
+                <resetValue>0x000000fc</resetValue>
+                <fields>
+                    <field>
+                        <name>DBG</name>
+                        <description>If 1, RESETS can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DMA</name>
+                        <description>If 1, RESETS can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CORE1</name>
+                        <description>If 1, RESETS can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CORE0</name>
+                        <description>If 1, RESETS can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SP</name>
+                        <description>If 1, RESETS can be accessed from a Secure, Privileged context.</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SU</name>
+                        <description>If 1, and SP is also set, RESETS can be accessed from a Secure, Unprivileged context.</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>NSP</name>
+                        <description>If 1, RESETS can be accessed from a Non-secure, Privileged context.</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>NSU</name>
+                        <description>If 1, and NSP is also set, RESETS can be accessed from a Non-secure, Unprivileged context.
+
+                            This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set.</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>IO_BANK0</name>
+                <addressOffset>0x00000068</addressOffset>
+                <description>Control whether debugger, DMA, core 0 and core 1 can access IO_BANK0, and at what security/privilege levels they can do so.
+
+                    Defaults to Secure access from any master.
+
+                    This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set.</description>
+                <resetValue>0x000000fc</resetValue>
+                <fields>
+                    <field>
+                        <name>DBG</name>
+                        <description>If 1, IO_BANK0 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DMA</name>
+                        <description>If 1, IO_BANK0 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CORE1</name>
+                        <description>If 1, IO_BANK0 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CORE0</name>
+                        <description>If 1, IO_BANK0 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SP</name>
+                        <description>If 1, IO_BANK0 can be accessed from a Secure, Privileged context.</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SU</name>
+                        <description>If 1, and SP is also set, IO_BANK0 can be accessed from a Secure, Unprivileged context.</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>NSP</name>
+                        <description>If 1, IO_BANK0 can be accessed from a Non-secure, Privileged context.</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>NSU</name>
+                        <description>If 1, and NSP is also set, IO_BANK0 can be accessed from a Non-secure, Unprivileged context.
+
+                            This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set.</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>IO_BANK1</name>
+                <addressOffset>0x0000006c</addressOffset>
+                <description>Control whether debugger, DMA, core 0 and core 1 can access IO_BANK1, and at what security/privilege levels they can do so.
+
+                    Defaults to Secure access from any master.
+
+                    This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set.</description>
+                <resetValue>0x000000fc</resetValue>
+                <fields>
+                    <field>
+                        <name>DBG</name>
+                        <description>If 1, IO_BANK1 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DMA</name>
+                        <description>If 1, IO_BANK1 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CORE1</name>
+                        <description>If 1, IO_BANK1 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CORE0</name>
+                        <description>If 1, IO_BANK1 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SP</name>
+                        <description>If 1, IO_BANK1 can be accessed from a Secure, Privileged context.</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SU</name>
+                        <description>If 1, and SP is also set, IO_BANK1 can be accessed from a Secure, Unprivileged context.</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>NSP</name>
+                        <description>If 1, IO_BANK1 can be accessed from a Non-secure, Privileged context.</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>NSU</name>
+                        <description>If 1, and NSP is also set, IO_BANK1 can be accessed from a Non-secure, Unprivileged context.
+
+                            This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set.</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PADS_BANK0</name>
+                <addressOffset>0x00000070</addressOffset>
+                <description>Control whether debugger, DMA, core 0 and core 1 can access PADS_BANK0, and at what security/privilege levels they can do so.
+
+                    Defaults to Secure access from any master.
+
+                    This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set.</description>
+                <resetValue>0x000000fc</resetValue>
+                <fields>
+                    <field>
+                        <name>DBG</name>
+                        <description>If 1, PADS_BANK0 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DMA</name>
+                        <description>If 1, PADS_BANK0 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CORE1</name>
+                        <description>If 1, PADS_BANK0 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CORE0</name>
+                        <description>If 1, PADS_BANK0 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SP</name>
+                        <description>If 1, PADS_BANK0 can be accessed from a Secure, Privileged context.</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SU</name>
+                        <description>If 1, and SP is also set, PADS_BANK0 can be accessed from a Secure, Unprivileged context.</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>NSP</name>
+                        <description>If 1, PADS_BANK0 can be accessed from a Non-secure, Privileged context.</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>NSU</name>
+                        <description>If 1, and NSP is also set, PADS_BANK0 can be accessed from a Non-secure, Unprivileged context.
+
+                            This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set.</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PADS_QSPI</name>
+                <addressOffset>0x00000074</addressOffset>
+                <description>Control whether debugger, DMA, core 0 and core 1 can access PADS_QSPI, and at what security/privilege levels they can do so.
+
+                    Defaults to Secure access from any master.
+
+                    This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set.</description>
+                <resetValue>0x000000fc</resetValue>
+                <fields>
+                    <field>
+                        <name>DBG</name>
+                        <description>If 1, PADS_QSPI can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DMA</name>
+                        <description>If 1, PADS_QSPI can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CORE1</name>
+                        <description>If 1, PADS_QSPI can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CORE0</name>
+                        <description>If 1, PADS_QSPI can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SP</name>
+                        <description>If 1, PADS_QSPI can be accessed from a Secure, Privileged context.</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SU</name>
+                        <description>If 1, and SP is also set, PADS_QSPI can be accessed from a Secure, Unprivileged context.</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>NSP</name>
+                        <description>If 1, PADS_QSPI can be accessed from a Non-secure, Privileged context.</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>NSU</name>
+                        <description>If 1, and NSP is also set, PADS_QSPI can be accessed from a Non-secure, Unprivileged context.
+
+                            This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set.</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>BUSCTRL</name>
+                <addressOffset>0x00000078</addressOffset>
+                <description>Control whether debugger, DMA, core 0 and core 1 can access BUSCTRL, and at what security/privilege levels they can do so.
+
+                    Defaults to Secure access from any master.
+
+                    This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set.</description>
+                <resetValue>0x000000fc</resetValue>
+                <fields>
+                    <field>
+                        <name>DBG</name>
+                        <description>If 1, BUSCTRL can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DMA</name>
+                        <description>If 1, BUSCTRL can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CORE1</name>
+                        <description>If 1, BUSCTRL can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CORE0</name>
+                        <description>If 1, BUSCTRL can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SP</name>
+                        <description>If 1, BUSCTRL can be accessed from a Secure, Privileged context.</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SU</name>
+                        <description>If 1, and SP is also set, BUSCTRL can be accessed from a Secure, Unprivileged context.</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>NSP</name>
+                        <description>If 1, BUSCTRL can be accessed from a Non-secure, Privileged context.</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>NSU</name>
+                        <description>If 1, and NSP is also set, BUSCTRL can be accessed from a Non-secure, Unprivileged context.
+
+                            This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set.</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>ADC0</name>
+                <addressOffset>0x0000007c</addressOffset>
+                <description>Control whether debugger, DMA, core 0 and core 1 can access ADC0, and at what security/privilege levels they can do so.
+
+                    Defaults to Secure access from any master.
+
+                    This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set.</description>
+                <resetValue>0x000000fc</resetValue>
+                <fields>
+                    <field>
+                        <name>DBG</name>
+                        <description>If 1, ADC0 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DMA</name>
+                        <description>If 1, ADC0 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CORE1</name>
+                        <description>If 1, ADC0 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CORE0</name>
+                        <description>If 1, ADC0 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SP</name>
+                        <description>If 1, ADC0 can be accessed from a Secure, Privileged context.</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SU</name>
+                        <description>If 1, and SP is also set, ADC0 can be accessed from a Secure, Unprivileged context.</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>NSP</name>
+                        <description>If 1, ADC0 can be accessed from a Non-secure, Privileged context.</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>NSU</name>
+                        <description>If 1, and NSP is also set, ADC0 can be accessed from a Non-secure, Unprivileged context.
+
+                            This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set.</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>HSTX</name>
+                <addressOffset>0x00000080</addressOffset>
+                <description>Control whether debugger, DMA, core 0 and core 1 can access HSTX, and at what security/privilege levels they can do so.
+
+                    Defaults to Secure access from any master.
+
+                    This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set.</description>
+                <resetValue>0x000000fc</resetValue>
+                <fields>
+                    <field>
+                        <name>DBG</name>
+                        <description>If 1, HSTX can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DMA</name>
+                        <description>If 1, HSTX can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CORE1</name>
+                        <description>If 1, HSTX can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CORE0</name>
+                        <description>If 1, HSTX can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SP</name>
+                        <description>If 1, HSTX can be accessed from a Secure, Privileged context.</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SU</name>
+                        <description>If 1, and SP is also set, HSTX can be accessed from a Secure, Unprivileged context.</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>NSP</name>
+                        <description>If 1, HSTX can be accessed from a Non-secure, Privileged context.</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>NSU</name>
+                        <description>If 1, and NSP is also set, HSTX can be accessed from a Non-secure, Unprivileged context.
+
+                            This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set.</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>I2C0</name>
+                <addressOffset>0x00000084</addressOffset>
+                <description>Control whether debugger, DMA, core 0 and core 1 can access I2C0, and at what security/privilege levels they can do so.
+
+                    Defaults to Secure access from any master.
+
+                    This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set.</description>
+                <resetValue>0x000000fc</resetValue>
+                <fields>
+                    <field>
+                        <name>DBG</name>
+                        <description>If 1, I2C0 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DMA</name>
+                        <description>If 1, I2C0 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CORE1</name>
+                        <description>If 1, I2C0 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CORE0</name>
+                        <description>If 1, I2C0 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SP</name>
+                        <description>If 1, I2C0 can be accessed from a Secure, Privileged context.</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SU</name>
+                        <description>If 1, and SP is also set, I2C0 can be accessed from a Secure, Unprivileged context.</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>NSP</name>
+                        <description>If 1, I2C0 can be accessed from a Non-secure, Privileged context.</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>NSU</name>
+                        <description>If 1, and NSP is also set, I2C0 can be accessed from a Non-secure, Unprivileged context.
+
+                            This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set.</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>I2C1</name>
+                <addressOffset>0x00000088</addressOffset>
+                <description>Control whether debugger, DMA, core 0 and core 1 can access I2C1, and at what security/privilege levels they can do so.
+
+                    Defaults to Secure access from any master.
+
+                    This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set.</description>
+                <resetValue>0x000000fc</resetValue>
+                <fields>
+                    <field>
+                        <name>DBG</name>
+                        <description>If 1, I2C1 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DMA</name>
+                        <description>If 1, I2C1 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CORE1</name>
+                        <description>If 1, I2C1 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CORE0</name>
+                        <description>If 1, I2C1 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SP</name>
+                        <description>If 1, I2C1 can be accessed from a Secure, Privileged context.</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SU</name>
+                        <description>If 1, and SP is also set, I2C1 can be accessed from a Secure, Unprivileged context.</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>NSP</name>
+                        <description>If 1, I2C1 can be accessed from a Non-secure, Privileged context.</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>NSU</name>
+                        <description>If 1, and NSP is also set, I2C1 can be accessed from a Non-secure, Unprivileged context.
+
+                            This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set.</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PWM</name>
+                <addressOffset>0x0000008c</addressOffset>
+                <description>Control whether debugger, DMA, core 0 and core 1 can access PWM, and at what security/privilege levels they can do so.
+
+                    Defaults to Secure access from any master.
+
+                    This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set.</description>
+                <resetValue>0x000000fc</resetValue>
+                <fields>
+                    <field>
+                        <name>DBG</name>
+                        <description>If 1, PWM can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DMA</name>
+                        <description>If 1, PWM can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CORE1</name>
+                        <description>If 1, PWM can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CORE0</name>
+                        <description>If 1, PWM can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SP</name>
+                        <description>If 1, PWM can be accessed from a Secure, Privileged context.</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SU</name>
+                        <description>If 1, and SP is also set, PWM can be accessed from a Secure, Unprivileged context.</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>NSP</name>
+                        <description>If 1, PWM can be accessed from a Non-secure, Privileged context.</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>NSU</name>
+                        <description>If 1, and NSP is also set, PWM can be accessed from a Non-secure, Unprivileged context.
+
+                            This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set.</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SPI0</name>
+                <addressOffset>0x00000090</addressOffset>
+                <description>Control whether debugger, DMA, core 0 and core 1 can access SPI0, and at what security/privilege levels they can do so.
+
+                    Defaults to Secure access from any master.
+
+                    This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set.</description>
+                <resetValue>0x000000fc</resetValue>
+                <fields>
+                    <field>
+                        <name>DBG</name>
+                        <description>If 1, SPI0 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DMA</name>
+                        <description>If 1, SPI0 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CORE1</name>
+                        <description>If 1, SPI0 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CORE0</name>
+                        <description>If 1, SPI0 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SP</name>
+                        <description>If 1, SPI0 can be accessed from a Secure, Privileged context.</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SU</name>
+                        <description>If 1, and SP is also set, SPI0 can be accessed from a Secure, Unprivileged context.</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>NSP</name>
+                        <description>If 1, SPI0 can be accessed from a Non-secure, Privileged context.</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>NSU</name>
+                        <description>If 1, and NSP is also set, SPI0 can be accessed from a Non-secure, Unprivileged context.
+
+                            This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set.</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SPI1</name>
+                <addressOffset>0x00000094</addressOffset>
+                <description>Control whether debugger, DMA, core 0 and core 1 can access SPI1, and at what security/privilege levels they can do so.
+
+                    Defaults to Secure access from any master.
+
+                    This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set.</description>
+                <resetValue>0x000000fc</resetValue>
+                <fields>
+                    <field>
+                        <name>DBG</name>
+                        <description>If 1, SPI1 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DMA</name>
+                        <description>If 1, SPI1 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CORE1</name>
+                        <description>If 1, SPI1 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CORE0</name>
+                        <description>If 1, SPI1 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SP</name>
+                        <description>If 1, SPI1 can be accessed from a Secure, Privileged context.</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SU</name>
+                        <description>If 1, and SP is also set, SPI1 can be accessed from a Secure, Unprivileged context.</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>NSP</name>
+                        <description>If 1, SPI1 can be accessed from a Non-secure, Privileged context.</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>NSU</name>
+                        <description>If 1, and NSP is also set, SPI1 can be accessed from a Non-secure, Unprivileged context.
+
+                            This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set.</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>TIMER0</name>
+                <addressOffset>0x00000098</addressOffset>
+                <description>Control whether debugger, DMA, core 0 and core 1 can access TIMER0, and at what security/privilege levels they can do so.
+
+                    Defaults to Secure access from any master.
+
+                    This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set.</description>
+                <resetValue>0x000000fc</resetValue>
+                <fields>
+                    <field>
+                        <name>DBG</name>
+                        <description>If 1, TIMER0 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DMA</name>
+                        <description>If 1, TIMER0 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CORE1</name>
+                        <description>If 1, TIMER0 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CORE0</name>
+                        <description>If 1, TIMER0 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SP</name>
+                        <description>If 1, TIMER0 can be accessed from a Secure, Privileged context.</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SU</name>
+                        <description>If 1, and SP is also set, TIMER0 can be accessed from a Secure, Unprivileged context.</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>NSP</name>
+                        <description>If 1, TIMER0 can be accessed from a Non-secure, Privileged context.</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>NSU</name>
+                        <description>If 1, and NSP is also set, TIMER0 can be accessed from a Non-secure, Unprivileged context.
+
+                            This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set.</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>TIMER1</name>
+                <addressOffset>0x0000009c</addressOffset>
+                <description>Control whether debugger, DMA, core 0 and core 1 can access TIMER1, and at what security/privilege levels they can do so.
+
+                    Defaults to Secure access from any master.
+
+                    This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set.</description>
+                <resetValue>0x000000fc</resetValue>
+                <fields>
+                    <field>
+                        <name>DBG</name>
+                        <description>If 1, TIMER1 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DMA</name>
+                        <description>If 1, TIMER1 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CORE1</name>
+                        <description>If 1, TIMER1 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CORE0</name>
+                        <description>If 1, TIMER1 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SP</name>
+                        <description>If 1, TIMER1 can be accessed from a Secure, Privileged context.</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SU</name>
+                        <description>If 1, and SP is also set, TIMER1 can be accessed from a Secure, Unprivileged context.</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>NSP</name>
+                        <description>If 1, TIMER1 can be accessed from a Non-secure, Privileged context.</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>NSU</name>
+                        <description>If 1, and NSP is also set, TIMER1 can be accessed from a Non-secure, Unprivileged context.
+
+                            This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set.</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>UART0</name>
+                <addressOffset>0x000000a0</addressOffset>
+                <description>Control whether debugger, DMA, core 0 and core 1 can access UART0, and at what security/privilege levels they can do so.
+
+                    Defaults to Secure access from any master.
+
+                    This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set.</description>
+                <resetValue>0x000000fc</resetValue>
+                <fields>
+                    <field>
+                        <name>DBG</name>
+                        <description>If 1, UART0 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DMA</name>
+                        <description>If 1, UART0 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CORE1</name>
+                        <description>If 1, UART0 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CORE0</name>
+                        <description>If 1, UART0 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SP</name>
+                        <description>If 1, UART0 can be accessed from a Secure, Privileged context.</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SU</name>
+                        <description>If 1, and SP is also set, UART0 can be accessed from a Secure, Unprivileged context.</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>NSP</name>
+                        <description>If 1, UART0 can be accessed from a Non-secure, Privileged context.</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>NSU</name>
+                        <description>If 1, and NSP is also set, UART0 can be accessed from a Non-secure, Unprivileged context.
+
+                            This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set.</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>UART1</name>
+                <addressOffset>0x000000a4</addressOffset>
+                <description>Control whether debugger, DMA, core 0 and core 1 can access UART1, and at what security/privilege levels they can do so.
+
+                    Defaults to Secure access from any master.
+
+                    This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set.</description>
+                <resetValue>0x000000fc</resetValue>
+                <fields>
+                    <field>
+                        <name>DBG</name>
+                        <description>If 1, UART1 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DMA</name>
+                        <description>If 1, UART1 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CORE1</name>
+                        <description>If 1, UART1 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CORE0</name>
+                        <description>If 1, UART1 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SP</name>
+                        <description>If 1, UART1 can be accessed from a Secure, Privileged context.</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SU</name>
+                        <description>If 1, and SP is also set, UART1 can be accessed from a Secure, Unprivileged context.</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>NSP</name>
+                        <description>If 1, UART1 can be accessed from a Non-secure, Privileged context.</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>NSU</name>
+                        <description>If 1, and NSP is also set, UART1 can be accessed from a Non-secure, Unprivileged context.
+
+                            This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set.</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>OTP</name>
+                <addressOffset>0x000000a8</addressOffset>
+                <description>Control whether debugger, DMA, core 0 and core 1 can access OTP, and at what security/privilege levels they can do so.
+
+                    Defaults to Secure access from any master.
+
+                    This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set.</description>
+                <resetValue>0x000000fc</resetValue>
+                <fields>
+                    <field>
+                        <name>DBG</name>
+                        <description>If 1, OTP can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DMA</name>
+                        <description>If 1, OTP can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CORE1</name>
+                        <description>If 1, OTP can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CORE0</name>
+                        <description>If 1, OTP can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SP</name>
+                        <description>If 1, OTP can be accessed from a Secure, Privileged context.</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SU</name>
+                        <description>If 1, and SP is also set, OTP can be accessed from a Secure, Unprivileged context.</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>NSP</name>
+                        <description>If 1, OTP can be accessed from a Non-secure, Privileged context.</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>NSU</name>
+                        <description>If 1, and NSP is also set, OTP can be accessed from a Non-secure, Unprivileged context.
+
+                            This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set.</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>TBMAN</name>
+                <addressOffset>0x000000ac</addressOffset>
+                <description>Control whether debugger, DMA, core 0 and core 1 can access TBMAN, and at what security/privilege levels they can do so.
+
+                    Defaults to Secure access from any master.
+
+                    This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set.</description>
+                <resetValue>0x000000fc</resetValue>
+                <fields>
+                    <field>
+                        <name>DBG</name>
+                        <description>If 1, TBMAN can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DMA</name>
+                        <description>If 1, TBMAN can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CORE1</name>
+                        <description>If 1, TBMAN can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CORE0</name>
+                        <description>If 1, TBMAN can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SP</name>
+                        <description>If 1, TBMAN can be accessed from a Secure, Privileged context.</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SU</name>
+                        <description>If 1, and SP is also set, TBMAN can be accessed from a Secure, Unprivileged context.</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>NSP</name>
+                        <description>If 1, TBMAN can be accessed from a Non-secure, Privileged context.</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>NSU</name>
+                        <description>If 1, and NSP is also set, TBMAN can be accessed from a Non-secure, Unprivileged context.
+
+                            This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set.</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>POWMAN</name>
+                <addressOffset>0x000000b0</addressOffset>
+                <description>Control whether debugger, DMA, core 0 and core 1 can access POWMAN, and at what security/privilege levels they can do so.
+
+                    Defaults to Secure, Privileged processor or debug access only.
+
+                    This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set.</description>
+                <resetValue>0x000000b8</resetValue>
+                <fields>
+                    <field>
+                        <name>DBG</name>
+                        <description>If 1, POWMAN can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DMA</name>
+                        <description>If 1, POWMAN can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CORE1</name>
+                        <description>If 1, POWMAN can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CORE0</name>
+                        <description>If 1, POWMAN can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SP</name>
+                        <description>If 1, POWMAN can be accessed from a Secure, Privileged context.</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SU</name>
+                        <description>If 1, and SP is also set, POWMAN can be accessed from a Secure, Unprivileged context.</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>NSP</name>
+                        <description>If 1, POWMAN can be accessed from a Non-secure, Privileged context.</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>NSU</name>
+                        <description>If 1, and NSP is also set, POWMAN can be accessed from a Non-secure, Unprivileged context.
+
+                            This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set.</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>TRNG</name>
+                <addressOffset>0x000000b4</addressOffset>
+                <description>Control whether debugger, DMA, core 0 and core 1 can access TRNG, and at what security/privilege levels they can do so.
+
+                    Defaults to Secure, Privileged processor or debug access only.
+
+                    This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set.</description>
+                <resetValue>0x000000b8</resetValue>
+                <fields>
+                    <field>
+                        <name>DBG</name>
+                        <description>If 1, TRNG can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DMA</name>
+                        <description>If 1, TRNG can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CORE1</name>
+                        <description>If 1, TRNG can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CORE0</name>
+                        <description>If 1, TRNG can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SP</name>
+                        <description>If 1, TRNG can be accessed from a Secure, Privileged context.</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SU</name>
+                        <description>If 1, and SP is also set, TRNG can be accessed from a Secure, Unprivileged context.</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>NSP</name>
+                        <description>If 1, TRNG can be accessed from a Non-secure, Privileged context.</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>NSU</name>
+                        <description>If 1, and NSP is also set, TRNG can be accessed from a Non-secure, Unprivileged context.
+
+                            This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set.</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SHA256</name>
+                <addressOffset>0x000000b8</addressOffset>
+                <description>Control whether debugger, DMA, core 0 and core 1 can access SHA256, and at what security/privilege levels they can do so.
+
+                    Defaults to Secure, Privileged access only.
+
+                    This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set.</description>
+                <resetValue>0x000000f8</resetValue>
+                <fields>
+                    <field>
+                        <name>DBG</name>
+                        <description>If 1, SHA256 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DMA</name>
+                        <description>If 1, SHA256 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CORE1</name>
+                        <description>If 1, SHA256 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CORE0</name>
+                        <description>If 1, SHA256 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SP</name>
+                        <description>If 1, SHA256 can be accessed from a Secure, Privileged context.</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SU</name>
+                        <description>If 1, and SP is also set, SHA256 can be accessed from a Secure, Unprivileged context.</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>NSP</name>
+                        <description>If 1, SHA256 can be accessed from a Non-secure, Privileged context.</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>NSU</name>
+                        <description>If 1, and NSP is also set, SHA256 can be accessed from a Non-secure, Unprivileged context.
+
+                            This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set.</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SYSCFG</name>
+                <addressOffset>0x000000bc</addressOffset>
+                <description>Control whether debugger, DMA, core 0 and core 1 can access SYSCFG, and at what security/privilege levels they can do so.
+
+                    Defaults to Secure, Privileged processor or debug access only.
+
+                    This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set.</description>
+                <resetValue>0x000000b8</resetValue>
+                <fields>
+                    <field>
+                        <name>DBG</name>
+                        <description>If 1, SYSCFG can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DMA</name>
+                        <description>If 1, SYSCFG can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CORE1</name>
+                        <description>If 1, SYSCFG can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CORE0</name>
+                        <description>If 1, SYSCFG can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SP</name>
+                        <description>If 1, SYSCFG can be accessed from a Secure, Privileged context.</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SU</name>
+                        <description>If 1, and SP is also set, SYSCFG can be accessed from a Secure, Unprivileged context.</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>NSP</name>
+                        <description>If 1, SYSCFG can be accessed from a Non-secure, Privileged context.</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>NSU</name>
+                        <description>If 1, and NSP is also set, SYSCFG can be accessed from a Non-secure, Unprivileged context.
+
+                            This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set.</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CLOCKS</name>
+                <addressOffset>0x000000c0</addressOffset>
+                <description>Control whether debugger, DMA, core 0 and core 1 can access CLOCKS, and at what security/privilege levels they can do so.
+
+                    Defaults to Secure, Privileged processor or debug access only.
+
+                    This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set.</description>
+                <resetValue>0x000000b8</resetValue>
+                <fields>
+                    <field>
+                        <name>DBG</name>
+                        <description>If 1, CLOCKS can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DMA</name>
+                        <description>If 1, CLOCKS can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CORE1</name>
+                        <description>If 1, CLOCKS can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CORE0</name>
+                        <description>If 1, CLOCKS can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SP</name>
+                        <description>If 1, CLOCKS can be accessed from a Secure, Privileged context.</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SU</name>
+                        <description>If 1, and SP is also set, CLOCKS can be accessed from a Secure, Unprivileged context.</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>NSP</name>
+                        <description>If 1, CLOCKS can be accessed from a Non-secure, Privileged context.</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>NSU</name>
+                        <description>If 1, and NSP is also set, CLOCKS can be accessed from a Non-secure, Unprivileged context.
+
+                            This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set.</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>XOSC</name>
+                <addressOffset>0x000000c4</addressOffset>
+                <description>Control whether debugger, DMA, core 0 and core 1 can access XOSC, and at what security/privilege levels they can do so.
+
+                    Defaults to Secure, Privileged processor or debug access only.
+
+                    This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set.</description>
+                <resetValue>0x000000b8</resetValue>
+                <fields>
+                    <field>
+                        <name>DBG</name>
+                        <description>If 1, XOSC can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DMA</name>
+                        <description>If 1, XOSC can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CORE1</name>
+                        <description>If 1, XOSC can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CORE0</name>
+                        <description>If 1, XOSC can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SP</name>
+                        <description>If 1, XOSC can be accessed from a Secure, Privileged context.</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SU</name>
+                        <description>If 1, and SP is also set, XOSC can be accessed from a Secure, Unprivileged context.</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>NSP</name>
+                        <description>If 1, XOSC can be accessed from a Non-secure, Privileged context.</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>NSU</name>
+                        <description>If 1, and NSP is also set, XOSC can be accessed from a Non-secure, Unprivileged context.
+
+                            This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set.</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>ROSC</name>
+                <addressOffset>0x000000c8</addressOffset>
+                <description>Control whether debugger, DMA, core 0 and core 1 can access ROSC, and at what security/privilege levels they can do so.
+
+                    Defaults to Secure, Privileged processor or debug access only.
+
+                    This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set.</description>
+                <resetValue>0x000000b8</resetValue>
+                <fields>
+                    <field>
+                        <name>DBG</name>
+                        <description>If 1, ROSC can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DMA</name>
+                        <description>If 1, ROSC can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CORE1</name>
+                        <description>If 1, ROSC can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CORE0</name>
+                        <description>If 1, ROSC can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SP</name>
+                        <description>If 1, ROSC can be accessed from a Secure, Privileged context.</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SU</name>
+                        <description>If 1, and SP is also set, ROSC can be accessed from a Secure, Unprivileged context.</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>NSP</name>
+                        <description>If 1, ROSC can be accessed from a Non-secure, Privileged context.</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>NSU</name>
+                        <description>If 1, and NSP is also set, ROSC can be accessed from a Non-secure, Unprivileged context.
+
+                            This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set.</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PLL_SYS</name>
+                <addressOffset>0x000000cc</addressOffset>
+                <description>Control whether debugger, DMA, core 0 and core 1 can access PLL_SYS, and at what security/privilege levels they can do so.
+
+                    Defaults to Secure, Privileged processor or debug access only.
+
+                    This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set.</description>
+                <resetValue>0x000000b8</resetValue>
+                <fields>
+                    <field>
+                        <name>DBG</name>
+                        <description>If 1, PLL_SYS can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DMA</name>
+                        <description>If 1, PLL_SYS can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CORE1</name>
+                        <description>If 1, PLL_SYS can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CORE0</name>
+                        <description>If 1, PLL_SYS can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SP</name>
+                        <description>If 1, PLL_SYS can be accessed from a Secure, Privileged context.</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SU</name>
+                        <description>If 1, and SP is also set, PLL_SYS can be accessed from a Secure, Unprivileged context.</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>NSP</name>
+                        <description>If 1, PLL_SYS can be accessed from a Non-secure, Privileged context.</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>NSU</name>
+                        <description>If 1, and NSP is also set, PLL_SYS can be accessed from a Non-secure, Unprivileged context.
+
+                            This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set.</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PLL_USB</name>
+                <addressOffset>0x000000d0</addressOffset>
+                <description>Control whether debugger, DMA, core 0 and core 1 can access PLL_USB, and at what security/privilege levels they can do so.
+
+                    Defaults to Secure, Privileged processor or debug access only.
+
+                    This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set.</description>
+                <resetValue>0x000000b8</resetValue>
+                <fields>
+                    <field>
+                        <name>DBG</name>
+                        <description>If 1, PLL_USB can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DMA</name>
+                        <description>If 1, PLL_USB can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CORE1</name>
+                        <description>If 1, PLL_USB can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CORE0</name>
+                        <description>If 1, PLL_USB can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SP</name>
+                        <description>If 1, PLL_USB can be accessed from a Secure, Privileged context.</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SU</name>
+                        <description>If 1, and SP is also set, PLL_USB can be accessed from a Secure, Unprivileged context.</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>NSP</name>
+                        <description>If 1, PLL_USB can be accessed from a Non-secure, Privileged context.</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>NSU</name>
+                        <description>If 1, and NSP is also set, PLL_USB can be accessed from a Non-secure, Unprivileged context.
+
+                            This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set.</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>TICKS</name>
+                <addressOffset>0x000000d4</addressOffset>
+                <description>Control whether debugger, DMA, core 0 and core 1 can access TICKS, and at what security/privilege levels they can do so.
+
+                    Defaults to Secure, Privileged processor or debug access only.
+
+                    This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set.</description>
+                <resetValue>0x000000b8</resetValue>
+                <fields>
+                    <field>
+                        <name>DBG</name>
+                        <description>If 1, TICKS can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DMA</name>
+                        <description>If 1, TICKS can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CORE1</name>
+                        <description>If 1, TICKS can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CORE0</name>
+                        <description>If 1, TICKS can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SP</name>
+                        <description>If 1, TICKS can be accessed from a Secure, Privileged context.</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SU</name>
+                        <description>If 1, and SP is also set, TICKS can be accessed from a Secure, Unprivileged context.</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>NSP</name>
+                        <description>If 1, TICKS can be accessed from a Non-secure, Privileged context.</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>NSU</name>
+                        <description>If 1, and NSP is also set, TICKS can be accessed from a Non-secure, Unprivileged context.
+
+                            This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set.</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>WATCHDOG</name>
+                <addressOffset>0x000000d8</addressOffset>
+                <description>Control whether debugger, DMA, core 0 and core 1 can access WATCHDOG, and at what security/privilege levels they can do so.
+
+                    Defaults to Secure, Privileged processor or debug access only.
+
+                    This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set.</description>
+                <resetValue>0x000000b8</resetValue>
+                <fields>
+                    <field>
+                        <name>DBG</name>
+                        <description>If 1, WATCHDOG can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DMA</name>
+                        <description>If 1, WATCHDOG can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CORE1</name>
+                        <description>If 1, WATCHDOG can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CORE0</name>
+                        <description>If 1, WATCHDOG can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SP</name>
+                        <description>If 1, WATCHDOG can be accessed from a Secure, Privileged context.</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SU</name>
+                        <description>If 1, and SP is also set, WATCHDOG can be accessed from a Secure, Unprivileged context.</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>NSP</name>
+                        <description>If 1, WATCHDOG can be accessed from a Non-secure, Privileged context.</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>NSU</name>
+                        <description>If 1, and NSP is also set, WATCHDOG can be accessed from a Non-secure, Unprivileged context.
+
+                            This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set.</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>RSM</name>
+                <addressOffset>0x000000dc</addressOffset>
+                <description>Control whether debugger, DMA, core 0 and core 1 can access RSM, and at what security/privilege levels they can do so.
+
+                    Defaults to Secure, Privileged processor or debug access only.
+
+                    This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set.</description>
+                <resetValue>0x000000b8</resetValue>
+                <fields>
+                    <field>
+                        <name>DBG</name>
+                        <description>If 1, RSM can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DMA</name>
+                        <description>If 1, RSM can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CORE1</name>
+                        <description>If 1, RSM can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CORE0</name>
+                        <description>If 1, RSM can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SP</name>
+                        <description>If 1, RSM can be accessed from a Secure, Privileged context.</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SU</name>
+                        <description>If 1, and SP is also set, RSM can be accessed from a Secure, Unprivileged context.</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>NSP</name>
+                        <description>If 1, RSM can be accessed from a Non-secure, Privileged context.</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>NSU</name>
+                        <description>If 1, and NSP is also set, RSM can be accessed from a Non-secure, Unprivileged context.
+
+                            This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set.</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>XIP_CTRL</name>
+                <addressOffset>0x000000e0</addressOffset>
+                <description>Control whether debugger, DMA, core 0 and core 1 can access XIP_CTRL, and at what security/privilege levels they can do so.
+
+                    Defaults to Secure, Privileged processor or debug access only.
+
+                    This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set.</description>
+                <resetValue>0x000000b8</resetValue>
+                <fields>
+                    <field>
+                        <name>DBG</name>
+                        <description>If 1, XIP_CTRL can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DMA</name>
+                        <description>If 1, XIP_CTRL can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CORE1</name>
+                        <description>If 1, XIP_CTRL can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CORE0</name>
+                        <description>If 1, XIP_CTRL can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SP</name>
+                        <description>If 1, XIP_CTRL can be accessed from a Secure, Privileged context.</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SU</name>
+                        <description>If 1, and SP is also set, XIP_CTRL can be accessed from a Secure, Unprivileged context.</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>NSP</name>
+                        <description>If 1, XIP_CTRL can be accessed from a Non-secure, Privileged context.</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>NSU</name>
+                        <description>If 1, and NSP is also set, XIP_CTRL can be accessed from a Non-secure, Unprivileged context.
+
+                            This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set.</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>XIP_QMI</name>
+                <addressOffset>0x000000e4</addressOffset>
+                <description>Control whether debugger, DMA, core 0 and core 1 can access XIP_QMI, and at what security/privilege levels they can do so.
+
+                    Defaults to Secure, Privileged processor or debug access only.
+
+                    This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set.</description>
+                <resetValue>0x000000b8</resetValue>
+                <fields>
+                    <field>
+                        <name>DBG</name>
+                        <description>If 1, XIP_QMI can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DMA</name>
+                        <description>If 1, XIP_QMI can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CORE1</name>
+                        <description>If 1, XIP_QMI can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CORE0</name>
+                        <description>If 1, XIP_QMI can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SP</name>
+                        <description>If 1, XIP_QMI can be accessed from a Secure, Privileged context.</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SU</name>
+                        <description>If 1, and SP is also set, XIP_QMI can be accessed from a Secure, Unprivileged context.</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>NSP</name>
+                        <description>If 1, XIP_QMI can be accessed from a Non-secure, Privileged context.</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>NSU</name>
+                        <description>If 1, and NSP is also set, XIP_QMI can be accessed from a Non-secure, Unprivileged context.
+
+                            This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set.</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>XIP_AUX</name>
+                <addressOffset>0x000000e8</addressOffset>
+                <description>Control whether debugger, DMA, core 0 and core 1 can access XIP_AUX, and at what security/privilege levels they can do so.
+
+                    Defaults to Secure, Privileged access only.
+
+                    This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set.</description>
+                <resetValue>0x000000f8</resetValue>
+                <fields>
+                    <field>
+                        <name>DBG</name>
+                        <description>If 1, XIP_AUX can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DMA</name>
+                        <description>If 1, XIP_AUX can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CORE1</name>
+                        <description>If 1, XIP_AUX can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CORE0</name>
+                        <description>If 1, XIP_AUX can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SP</name>
+                        <description>If 1, XIP_AUX can be accessed from a Secure, Privileged context.</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SU</name>
+                        <description>If 1, and SP is also set, XIP_AUX can be accessed from a Secure, Unprivileged context.</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>NSP</name>
+                        <description>If 1, XIP_AUX can be accessed from a Non-secure, Privileged context.</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>NSU</name>
+                        <description>If 1, and NSP is also set, XIP_AUX can be accessed from a Non-secure, Unprivileged context.
+
+                            This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set.</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+        </registers>
+    </peripheral>
+    <peripheral>
+        <name>UART0</name>
+        <baseAddress>0x40070000</baseAddress>
+        <addressBlock>
+            <offset>0</offset>
+            <size>4096</size>
+            <usage>registers</usage>
+        </addressBlock>
+        <interrupt>
+            <name>UART0_IRQ</name>
+            <value>33</value>
+        </interrupt>
+        <registers>
+            <register>
+                <name>UARTDR</name>
+                <addressOffset>0x00000000</addressOffset>
+                <description>Data Register, UARTDR</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>OE</name>
+                        <description>Overrun error. This bit is set to 1 if data is received and the receive FIFO is already full. This is cleared to 0 once there is an empty space in the FIFO and a new character can be written to it.</description>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>BE</name>
+                        <description>Break error. This bit is set to 1 if a break condition was detected, indicating that the received data input was held LOW for longer than a full-word transmission time (defined as start, data, parity and stop bits). In FIFO mode, this error is associated with the character at the top of the FIFO. When a break occurs, only one 0 character is loaded into the FIFO. The next character is only enabled after the receive data input goes to a 1 (marking state), and the next valid start bit is received.</description>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>PE</name>
+                        <description>Parity error. When set to 1, it indicates that the parity of the received data character does not match the parity that the EPS and SPS bits in the Line Control Register, UARTLCR_H. In FIFO mode, this error is associated with the character at the top of the FIFO.</description>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>FE</name>
+                        <description>Framing error. When set to 1, it indicates that the received character did not have a valid stop bit (a valid stop bit is 1). In FIFO mode, this error is associated with the character at the top of the FIFO.</description>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>DATA</name>
+                        <description>Receive (read) data character. Transmit (write) data character.</description>
+                        <bitRange>[7:0]</bitRange>
+                        <access>read-write</access>
+                        <readAction>modify</readAction>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>UARTRSR</name>
+                <addressOffset>0x00000004</addressOffset>
+                <description>Receive Status Register/Error Clear Register, UARTRSR/UARTECR</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>OE</name>
+                        <description>Overrun error. This bit is set to 1 if data is received and the FIFO is already full. This bit is cleared to 0 by a write to UARTECR. The FIFO contents remain valid because no more data is written when the FIFO is full, only the contents of the shift register are overwritten. The CPU must now read the data, to empty the FIFO.</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>BE</name>
+                        <description>Break error. This bit is set to 1 if a break condition was detected, indicating that the received data input was held LOW for longer than a full-word transmission time (defined as start, data, parity, and stop bits). This bit is cleared to 0 after a write to UARTECR. In FIFO mode, this error is associated with the character at the top of the FIFO. When a break occurs, only one 0 character is loaded into the FIFO. The next character is only enabled after the receive data input goes to a 1 (marking state) and the next valid start bit is received.</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>PE</name>
+                        <description>Parity error. When set to 1, it indicates that the parity of the received data character does not match the parity that the EPS and SPS bits in the Line Control Register, UARTLCR_H. This bit is cleared to 0 by a write to UARTECR. In FIFO mode, this error is associated with the character at the top of the FIFO.</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>FE</name>
+                        <description>Framing error. When set to 1, it indicates that the received character did not have a valid stop bit (a valid stop bit is 1). This bit is cleared to 0 by a write to UARTECR. In FIFO mode, this error is associated with the character at the top of the FIFO.</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>UARTFR</name>
+                <addressOffset>0x00000018</addressOffset>
+                <description>Flag Register, UARTFR</description>
+                <resetValue>0x00000090</resetValue>
+                <fields>
+                    <field>
+                        <name>RI</name>
+                        <description>Ring indicator. This bit is the complement of the UART ring indicator, nUARTRI, modem status input. That is, the bit is 1 when nUARTRI is LOW.</description>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>TXFE</name>
+                        <description>Transmit FIFO empty. The meaning of this bit depends on the state of the FEN bit in the Line Control Register, UARTLCR_H. If the FIFO is disabled, this bit is set when the transmit holding register is empty. If the FIFO is enabled, the TXFE bit is set when the transmit FIFO is empty. This bit does not indicate if there is data in the transmit shift register.</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>RXFF</name>
+                        <description>Receive FIFO full. The meaning of this bit depends on the state of the FEN bit in the UARTLCR_H Register. If the FIFO is disabled, this bit is set when the receive holding register is full. If the FIFO is enabled, the RXFF bit is set when the receive FIFO is full.</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>TXFF</name>
+                        <description>Transmit FIFO full. The meaning of this bit depends on the state of the FEN bit in the UARTLCR_H Register. If the FIFO is disabled, this bit is set when the transmit holding register is full. If the FIFO is enabled, the TXFF bit is set when the transmit FIFO is full.</description>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>RXFE</name>
+                        <description>Receive FIFO empty. The meaning of this bit depends on the state of the FEN bit in the UARTLCR_H Register. If the FIFO is disabled, this bit is set when the receive holding register is empty. If the FIFO is enabled, the RXFE bit is set when the receive FIFO is empty.</description>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>BUSY</name>
+                        <description>UART busy. If this bit is set to 1, the UART is busy transmitting data. This bit remains set until the complete byte, including all the stop bits, has been sent from the shift register. This bit is set as soon as the transmit FIFO becomes non-empty, regardless of whether the UART is enabled or not.</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>DCD</name>
+                        <description>Data carrier detect. This bit is the complement of the UART data carrier detect, nUARTDCD, modem status input. That is, the bit is 1 when nUARTDCD is LOW.</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>DSR</name>
+                        <description>Data set ready. This bit is the complement of the UART data set ready, nUARTDSR, modem status input. That is, the bit is 1 when nUARTDSR is LOW.</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CTS</name>
+                        <description>Clear to send. This bit is the complement of the UART clear to send, nUARTCTS, modem status input. That is, the bit is 1 when nUARTCTS is LOW.</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>UARTILPR</name>
+                <addressOffset>0x00000020</addressOffset>
+                <description>IrDA Low-Power Counter Register, UARTILPR</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>ILPDVSR</name>
+                        <description>8-bit low-power divisor value. These bits are cleared to 0 at reset.</description>
+                        <bitRange>[7:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>UARTIBRD</name>
+                <addressOffset>0x00000024</addressOffset>
+                <description>Integer Baud Rate Register, UARTIBRD</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>BAUD_DIVINT</name>
+                        <description>The integer baud rate divisor. These bits are cleared to 0 on reset.</description>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>UARTFBRD</name>
+                <addressOffset>0x00000028</addressOffset>
+                <description>Fractional Baud Rate Register, UARTFBRD</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>BAUD_DIVFRAC</name>
+                        <description>The fractional baud rate divisor. These bits are cleared to 0 on reset.</description>
+                        <bitRange>[5:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>UARTLCR_H</name>
+                <addressOffset>0x0000002c</addressOffset>
+                <description>Line Control Register, UARTLCR_H</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>SPS</name>
+                        <description>Stick parity select. 0 = stick parity is disabled 1 = either: * if the EPS bit is 0 then the parity bit is transmitted and checked as a 1 * if the EPS bit is 1 then the parity bit is transmitted and checked as a 0. This bit has no effect when the PEN bit disables parity checking and generation.</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>WLEN</name>
+                        <description>Word length. These bits indicate the number of data bits transmitted or received in a frame as follows: b11 = 8 bits b10 = 7 bits b01 = 6 bits b00 = 5 bits.</description>
+                        <bitRange>[6:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>FEN</name>
+                        <description>Enable FIFOs: 0 = FIFOs are disabled (character mode) that is, the FIFOs become 1-byte-deep holding registers 1 = transmit and receive FIFO buffers are enabled (FIFO mode).</description>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>STP2</name>
+                        <description>Two stop bits select. If this bit is set to 1, two stop bits are transmitted at the end of the frame. The receive logic does not check for two stop bits being received.</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>EPS</name>
+                        <description>Even parity select. Controls the type of parity the UART uses during transmission and reception: 0 = odd parity. The UART generates or checks for an odd number of 1s in the data and parity bits. 1 = even parity. The UART generates or checks for an even number of 1s in the data and parity bits. This bit has no effect when the PEN bit disables parity checking and generation.</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PEN</name>
+                        <description>Parity enable: 0 = parity is disabled and no parity bit added to the data frame 1 = parity checking and generation is enabled.</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>BRK</name>
+                        <description>Send break. If this bit is set to 1, a low-level is continually output on the UARTTXD output, after completing transmission of the current character. For the proper execution of the break command, the software must set this bit for at least two complete frames. For normal use, this bit must be cleared to 0.</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>UARTCR</name>
+                <addressOffset>0x00000030</addressOffset>
+                <description>Control Register, UARTCR</description>
+                <resetValue>0x00000300</resetValue>
+                <fields>
+                    <field>
+                        <name>CTSEN</name>
+                        <description>CTS hardware flow control enable. If this bit is set to 1, CTS hardware flow control is enabled. Data is only transmitted when the nUARTCTS signal is asserted.</description>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>RTSEN</name>
+                        <description>RTS hardware flow control enable. If this bit is set to 1, RTS hardware flow control is enabled. Data is only requested when there is space in the receive FIFO for it to be received.</description>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>OUT2</name>
+                        <description>This bit is the complement of the UART Out2 (nUARTOut2) modem status output. That is, when the bit is programmed to a 1, the output is 0. For DTE this can be used as Ring Indicator (RI).</description>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>OUT1</name>
+                        <description>This bit is the complement of the UART Out1 (nUARTOut1) modem status output. That is, when the bit is programmed to a 1 the output is 0. For DTE this can be used as Data Carrier Detect (DCD).</description>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>RTS</name>
+                        <description>Request to send. This bit is the complement of the UART request to send, nUARTRTS, modem status output. That is, when the bit is programmed to a 1 then nUARTRTS is LOW.</description>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DTR</name>
+                        <description>Data transmit ready. This bit is the complement of the UART data transmit ready, nUARTDTR, modem status output. That is, when the bit is programmed to a 1 then nUARTDTR is LOW.</description>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>RXE</name>
+                        <description>Receive enable. If this bit is set to 1, the receive section of the UART is enabled. Data reception occurs for either UART signals or SIR signals depending on the setting of the SIREN bit. When the UART is disabled in the middle of reception, it completes the current character before stopping.</description>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>TXE</name>
+                        <description>Transmit enable. If this bit is set to 1, the transmit section of the UART is enabled. Data transmission occurs for either UART signals, or SIR signals depending on the setting of the SIREN bit. When the UART is disabled in the middle of transmission, it completes the current character before stopping.</description>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LBE</name>
+                        <description>Loopback enable. If this bit is set to 1 and the SIREN bit is set to 1 and the SIRTEST bit in the Test Control Register, UARTTCR is set to 1, then the nSIROUT path is inverted, and fed through to the SIRIN path. The SIRTEST bit in the test register must be set to 1 to override the normal half-duplex SIR operation. This must be the requirement for accessing the test registers during normal operation, and SIRTEST must be cleared to 0 when loopback testing is finished. This feature reduces the amount of external coupling required during system test. If this bit is set to 1, and the SIRTEST bit is set to 0, the UARTTXD path is fed through to the UARTRXD path. In either SIR mode or UART mode, when this bit is set, the modem outputs are also fed through to the modem inputs. This bit is cleared to 0 on reset, to disable loopback.</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SIRLP</name>
+                        <description>SIR low-power IrDA mode. This bit selects the IrDA encoding mode. If this bit is cleared to 0, low-level bits are transmitted as an active high pulse with a width of 3 / 16th of the bit period. If this bit is set to 1, low-level bits are transmitted with a pulse width that is 3 times the period of the IrLPBaud16 input signal, regardless of the selected bit rate. Setting this bit uses less power, but might reduce transmission distances.</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SIREN</name>
+                        <description>SIR enable: 0 = IrDA SIR ENDEC is disabled. nSIROUT remains LOW (no light pulse generated), and signal transitions on SIRIN have no effect. 1 = IrDA SIR ENDEC is enabled. Data is transmitted and received on nSIROUT and SIRIN. UARTTXD remains HIGH, in the marking state. Signal transitions on UARTRXD or modem status inputs have no effect. This bit has no effect if the UARTEN bit disables the UART.</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>UARTEN</name>
+                        <description>UART enable: 0 = UART is disabled. If the UART is disabled in the middle of transmission or reception, it completes the current character before stopping. 1 = the UART is enabled. Data transmission and reception occurs for either UART signals or SIR signals depending on the setting of the SIREN bit.</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>UARTIFLS</name>
+                <addressOffset>0x00000034</addressOffset>
+                <description>Interrupt FIFO Level Select Register, UARTIFLS</description>
+                <resetValue>0x00000012</resetValue>
+                <fields>
+                    <field>
+                        <name>RXIFLSEL</name>
+                        <description>Receive interrupt FIFO level select. The trigger points for the receive interrupt are as follows: b000 = Receive FIFO becomes &gt;= 1 / 8 full b001 = Receive FIFO becomes &gt;= 1 / 4 full b010 = Receive FIFO becomes &gt;= 1 / 2 full b011 = Receive FIFO becomes &gt;= 3 / 4 full b100 = Receive FIFO becomes &gt;= 7 / 8 full b101-b111 = reserved.</description>
+                        <bitRange>[5:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>TXIFLSEL</name>
+                        <description>Transmit interrupt FIFO level select. The trigger points for the transmit interrupt are as follows: b000 = Transmit FIFO becomes &lt;= 1 / 8 full b001 = Transmit FIFO becomes &lt;= 1 / 4 full b010 = Transmit FIFO becomes &lt;= 1 / 2 full b011 = Transmit FIFO becomes &lt;= 3 / 4 full b100 = Transmit FIFO becomes &lt;= 7 / 8 full b101-b111 = reserved.</description>
+                        <bitRange>[2:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>UARTIMSC</name>
+                <addressOffset>0x00000038</addressOffset>
+                <description>Interrupt Mask Set/Clear Register, UARTIMSC</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>OEIM</name>
+                        <description>Overrun error interrupt mask. A read returns the current mask for the UARTOEINTR interrupt. On a write of 1, the mask of the UARTOEINTR interrupt is set. A write of 0 clears the mask.</description>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>BEIM</name>
+                        <description>Break error interrupt mask. A read returns the current mask for the UARTBEINTR interrupt. On a write of 1, the mask of the UARTBEINTR interrupt is set. A write of 0 clears the mask.</description>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PEIM</name>
+                        <description>Parity error interrupt mask. A read returns the current mask for the UARTPEINTR interrupt. On a write of 1, the mask of the UARTPEINTR interrupt is set. A write of 0 clears the mask.</description>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>FEIM</name>
+                        <description>Framing error interrupt mask. A read returns the current mask for the UARTFEINTR interrupt. On a write of 1, the mask of the UARTFEINTR interrupt is set. A write of 0 clears the mask.</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>RTIM</name>
+                        <description>Receive timeout interrupt mask. A read returns the current mask for the UARTRTINTR interrupt. On a write of 1, the mask of the UARTRTINTR interrupt is set. A write of 0 clears the mask.</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>TXIM</name>
+                        <description>Transmit interrupt mask. A read returns the current mask for the UARTTXINTR interrupt. On a write of 1, the mask of the UARTTXINTR interrupt is set. A write of 0 clears the mask.</description>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>RXIM</name>
+                        <description>Receive interrupt mask. A read returns the current mask for the UARTRXINTR interrupt. On a write of 1, the mask of the UARTRXINTR interrupt is set. A write of 0 clears the mask.</description>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DSRMIM</name>
+                        <description>nUARTDSR modem interrupt mask. A read returns the current mask for the UARTDSRINTR interrupt. On a write of 1, the mask of the UARTDSRINTR interrupt is set. A write of 0 clears the mask.</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DCDMIM</name>
+                        <description>nUARTDCD modem interrupt mask. A read returns the current mask for the UARTDCDINTR interrupt. On a write of 1, the mask of the UARTDCDINTR interrupt is set. A write of 0 clears the mask.</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CTSMIM</name>
+                        <description>nUARTCTS modem interrupt mask. A read returns the current mask for the UARTCTSINTR interrupt. On a write of 1, the mask of the UARTCTSINTR interrupt is set. A write of 0 clears the mask.</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>RIMIM</name>
+                        <description>nUARTRI modem interrupt mask. A read returns the current mask for the UARTRIINTR interrupt. On a write of 1, the mask of the UARTRIINTR interrupt is set. A write of 0 clears the mask.</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>UARTRIS</name>
+                <addressOffset>0x0000003c</addressOffset>
+                <description>Raw Interrupt Status Register, UARTRIS</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>OERIS</name>
+                        <description>Overrun error interrupt status. Returns the raw interrupt state of the UARTOEINTR interrupt.</description>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>BERIS</name>
+                        <description>Break error interrupt status. Returns the raw interrupt state of the UARTBEINTR interrupt.</description>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>PERIS</name>
+                        <description>Parity error interrupt status. Returns the raw interrupt state of the UARTPEINTR interrupt.</description>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>FERIS</name>
+                        <description>Framing error interrupt status. Returns the raw interrupt state of the UARTFEINTR interrupt.</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>RTRIS</name>
+                        <description>Receive timeout interrupt status. Returns the raw interrupt state of the UARTRTINTR interrupt. a</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>TXRIS</name>
+                        <description>Transmit interrupt status. Returns the raw interrupt state of the UARTTXINTR interrupt.</description>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>RXRIS</name>
+                        <description>Receive interrupt status. Returns the raw interrupt state of the UARTRXINTR interrupt.</description>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>DSRRMIS</name>
+                        <description>nUARTDSR modem interrupt status. Returns the raw interrupt state of the UARTDSRINTR interrupt.</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>DCDRMIS</name>
+                        <description>nUARTDCD modem interrupt status. Returns the raw interrupt state of the UARTDCDINTR interrupt.</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CTSRMIS</name>
+                        <description>nUARTCTS modem interrupt status. Returns the raw interrupt state of the UARTCTSINTR interrupt.</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>RIRMIS</name>
+                        <description>nUARTRI modem interrupt status. Returns the raw interrupt state of the UARTRIINTR interrupt.</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>UARTMIS</name>
+                <addressOffset>0x00000040</addressOffset>
+                <description>Masked Interrupt Status Register, UARTMIS</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>OEMIS</name>
+                        <description>Overrun error masked interrupt status. Returns the masked interrupt state of the UARTOEINTR interrupt.</description>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>BEMIS</name>
+                        <description>Break error masked interrupt status. Returns the masked interrupt state of the UARTBEINTR interrupt.</description>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>PEMIS</name>
+                        <description>Parity error masked interrupt status. Returns the masked interrupt state of the UARTPEINTR interrupt.</description>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>FEMIS</name>
+                        <description>Framing error masked interrupt status. Returns the masked interrupt state of the UARTFEINTR interrupt.</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>RTMIS</name>
+                        <description>Receive timeout masked interrupt status. Returns the masked interrupt state of the UARTRTINTR interrupt.</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>TXMIS</name>
+                        <description>Transmit masked interrupt status. Returns the masked interrupt state of the UARTTXINTR interrupt.</description>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>RXMIS</name>
+                        <description>Receive masked interrupt status. Returns the masked interrupt state of the UARTRXINTR interrupt.</description>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>DSRMMIS</name>
+                        <description>nUARTDSR modem masked interrupt status. Returns the masked interrupt state of the UARTDSRINTR interrupt.</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>DCDMMIS</name>
+                        <description>nUARTDCD modem masked interrupt status. Returns the masked interrupt state of the UARTDCDINTR interrupt.</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CTSMMIS</name>
+                        <description>nUARTCTS modem masked interrupt status. Returns the masked interrupt state of the UARTCTSINTR interrupt.</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>RIMMIS</name>
+                        <description>nUARTRI modem masked interrupt status. Returns the masked interrupt state of the UARTRIINTR interrupt.</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>UARTICR</name>
+                <addressOffset>0x00000044</addressOffset>
+                <description>Interrupt Clear Register, UARTICR</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>OEIC</name>
+                        <description>Overrun error interrupt clear. Clears the UARTOEINTR interrupt.</description>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>BEIC</name>
+                        <description>Break error interrupt clear. Clears the UARTBEINTR interrupt.</description>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>PEIC</name>
+                        <description>Parity error interrupt clear. Clears the UARTPEINTR interrupt.</description>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>FEIC</name>
+                        <description>Framing error interrupt clear. Clears the UARTFEINTR interrupt.</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>RTIC</name>
+                        <description>Receive timeout interrupt clear. Clears the UARTRTINTR interrupt.</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>TXIC</name>
+                        <description>Transmit interrupt clear. Clears the UARTTXINTR interrupt.</description>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>RXIC</name>
+                        <description>Receive interrupt clear. Clears the UARTRXINTR interrupt.</description>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>DSRMIC</name>
+                        <description>nUARTDSR modem interrupt clear. Clears the UARTDSRINTR interrupt.</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>DCDMIC</name>
+                        <description>nUARTDCD modem interrupt clear. Clears the UARTDCDINTR interrupt.</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>CTSMIC</name>
+                        <description>nUARTCTS modem interrupt clear. Clears the UARTCTSINTR interrupt.</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>RIMIC</name>
+                        <description>nUARTRI modem interrupt clear. Clears the UARTRIINTR interrupt.</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>UARTDMACR</name>
+                <addressOffset>0x00000048</addressOffset>
+                <description>DMA Control Register, UARTDMACR</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>DMAONERR</name>
+                        <description>DMA on error. If this bit is set to 1, the DMA receive request outputs, UARTRXDMASREQ or UARTRXDMABREQ, are disabled when the UART error interrupt is asserted.</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>TXDMAE</name>
+                        <description>Transmit DMA enable. If this bit is set to 1, DMA for the transmit FIFO is enabled.</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>RXDMAE</name>
+                        <description>Receive DMA enable. If this bit is set to 1, DMA for the receive FIFO is enabled.</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>UARTPERIPHID0</name>
+                <addressOffset>0x00000fe0</addressOffset>
+                <description>UARTPeriphID0 Register</description>
+                <resetValue>0x00000011</resetValue>
+                <fields>
+                    <field>
+                        <name>PARTNUMBER0</name>
+                        <description>These bits read back as 0x11</description>
+                        <bitRange>[7:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>UARTPERIPHID1</name>
+                <addressOffset>0x00000fe4</addressOffset>
+                <description>UARTPeriphID1 Register</description>
+                <resetValue>0x00000010</resetValue>
+                <fields>
+                    <field>
+                        <name>DESIGNER0</name>
+                        <description>These bits read back as 0x1</description>
+                        <bitRange>[7:4]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>PARTNUMBER1</name>
+                        <description>These bits read back as 0x0</description>
+                        <bitRange>[3:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>UARTPERIPHID2</name>
+                <addressOffset>0x00000fe8</addressOffset>
+                <description>UARTPeriphID2 Register</description>
+                <resetValue>0x00000034</resetValue>
+                <fields>
+                    <field>
+                        <name>REVISION</name>
+                        <description>This field depends on the revision of the UART: r1p0 0x0 r1p1 0x1 r1p3 0x2 r1p4 0x2 r1p5 0x3</description>
+                        <bitRange>[7:4]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>DESIGNER1</name>
+                        <description>These bits read back as 0x4</description>
+                        <bitRange>[3:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>UARTPERIPHID3</name>
+                <addressOffset>0x00000fec</addressOffset>
+                <description>UARTPeriphID3 Register</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CONFIGURATION</name>
+                        <description>These bits read back as 0x00</description>
+                        <bitRange>[7:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>UARTPCELLID0</name>
+                <addressOffset>0x00000ff0</addressOffset>
+                <description>UARTPCellID0 Register</description>
+                <resetValue>0x0000000d</resetValue>
+                <fields>
+                    <field>
+                        <name>UARTPCELLID0</name>
+                        <description>These bits read back as 0x0D</description>
+                        <bitRange>[7:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>UARTPCELLID1</name>
+                <addressOffset>0x00000ff4</addressOffset>
+                <description>UARTPCellID1 Register</description>
+                <resetValue>0x000000f0</resetValue>
+                <fields>
+                    <field>
+                        <name>UARTPCELLID1</name>
+                        <description>These bits read back as 0xF0</description>
+                        <bitRange>[7:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>UARTPCELLID2</name>
+                <addressOffset>0x00000ff8</addressOffset>
+                <description>UARTPCellID2 Register</description>
+                <resetValue>0x00000005</resetValue>
+                <fields>
+                    <field>
+                        <name>UARTPCELLID2</name>
+                        <description>These bits read back as 0x05</description>
+                        <bitRange>[7:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>UARTPCELLID3</name>
+                <addressOffset>0x00000ffc</addressOffset>
+                <description>UARTPCellID3 Register</description>
+                <resetValue>0x000000b1</resetValue>
+                <fields>
+                    <field>
+                        <name>UARTPCELLID3</name>
+                        <description>These bits read back as 0xB1</description>
+                        <bitRange>[7:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+        </registers>
+    </peripheral>
+    <peripheral derivedFrom="UART0">
+        <name>UART1</name>
+        <baseAddress>0x40078000</baseAddress>
+        <interrupt>
+        <name>UART1_IRQ</name>
+        <value>34</value>
+    </interrupt>
+    </peripheral>
+    <peripheral>
+        <name>ROSC</name>
+        <baseAddress>0x400e8000</baseAddress>
+        <addressBlock>
+            <offset>0</offset>
+            <size>40</size>
+            <usage>registers</usage>
+        </addressBlock>
+        <registers>
+            <register>
+                <name>CTRL</name>
+                <addressOffset>0x00000000</addressOffset>
+                <description>Ring Oscillator control</description>
+                <resetValue>0x00000aa0</resetValue>
+                <fields>
+                    <field>
+                        <name>ENABLE</name>
+                        <description>On power-up this field is initialised to ENABLE 
+                            The system clock must be switched to another source before setting this field to DISABLE otherwise the chip will lock up 
+                            The 12-bit code is intended to give some protection against accidental writes. An invalid setting will enable the oscillator.</description>
+                        <bitRange>[23:12]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>DISABLE</name>
+                                <value>3358</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ENABLE</name>
+                                <value>4011</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>FREQ_RANGE</name>
+                        <description>Controls the number of delay stages in the ROSC ring 
+                            LOW uses stages 0 to 7 
+                            MEDIUM uses stages 2 to 7 
+                            HIGH uses stages 4 to 7 
+                            TOOHIGH uses stages 6 to 7 and should not be used because its frequency exceeds design specifications 
+                            The clock output will not glitch when changing the range up one step at a time 
+                            The clock output will glitch when changing the range down 
+                            Note: the values here are gray coded which is why HIGH comes before TOOHIGH</description>
+                        <bitRange>[11:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>LOW</name>
+                                <value>4004</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>MEDIUM</name>
+                                <value>4005</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>4007</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TOOHIGH</name>
+                                <value>4006</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>FREQA</name>
+                <addressOffset>0x00000004</addressOffset>
+                <description>The FREQA &amp; FREQB registers control the frequency by controlling the drive strength of each stage 
+                    The drive strength has 4 levels determined by the number of bits set 
+                    Increasing the number of bits set increases the drive strength and increases the oscillation frequency 
+                    0 bits set is the default drive strength 
+                    1 bit set doubles the drive strength 
+                    2 bits set triples drive strength 
+                    3 bits set quadruples drive strength 
+                    For frequency randomisation set both DS0_RANDOM=1 &amp; DS1_RANDOM=1</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>PASSWD</name>
+                        <description>Set to 0x9696 to apply the settings 
+                            Any other value in this field will set all drive strengths to 0</description>
+                        <bitRange>[31:16]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>PASS</name>
+                                <value>38550</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>DS3</name>
+                        <description>Stage 3 drive strength</description>
+                        <bitRange>[14:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DS2</name>
+                        <description>Stage 2 drive strength</description>
+                        <bitRange>[10:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DS1_RANDOM</name>
+                        <description>Randomises the stage 1 drive strength</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DS1</name>
+                        <description>Stage 1 drive strength</description>
+                        <bitRange>[6:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DS0_RANDOM</name>
+                        <description>Randomises the stage 0 drive strength</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DS0</name>
+                        <description>Stage 0 drive strength</description>
+                        <bitRange>[2:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>FREQB</name>
+                <addressOffset>0x00000008</addressOffset>
+                <description>For a detailed description see freqa register</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>PASSWD</name>
+                        <description>Set to 0x9696 to apply the settings 
+                            Any other value in this field will set all drive strengths to 0</description>
+                        <bitRange>[31:16]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>PASS</name>
+                                <value>38550</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>DS7</name>
+                        <description>Stage 7 drive strength</description>
+                        <bitRange>[14:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DS6</name>
+                        <description>Stage 6 drive strength</description>
+                        <bitRange>[10:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DS5</name>
+                        <description>Stage 5 drive strength</description>
+                        <bitRange>[6:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DS4</name>
+                        <description>Stage 4 drive strength</description>
+                        <bitRange>[2:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>RANDOM</name>
+                <addressOffset>0x0000000c</addressOffset>
+                <description>Loads a value to the LFSR randomiser</description>
+                <resetValue>0x3f04b16d</resetValue>
+                <fields>
+                    <field>
+                        <name>SEED</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>DORMANT</name>
+                <addressOffset>0x00000010</addressOffset>
+                <description>Ring Oscillator pause control</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>DORMANT</name>
+                        <description>This is used to save power by pausing the ROSC 
+                            On power-up this field is initialised to WAKE 
+                            An invalid write will also select WAKE 
+                            Warning: setup the irq before selecting dormant mode</description>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>dormant</name>
+                                <value>1668246881</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>WAKE</name>
+                                <value>2002873189</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>DIV</name>
+                <addressOffset>0x00000014</addressOffset>
+                <description>Controls the output divider</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>DIV</name>
+                        <description>set to 0xaa00 + div where 
+                            div = 0 divides by 128 
+                            div = 1-127 divides by div 
+                            any other value sets div=128 
+                            this register resets to div=32</description>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>PASS</name>
+                                <value>43520</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PHASE</name>
+                <addressOffset>0x00000018</addressOffset>
+                <description>Controls the phase shifted output</description>
+                <resetValue>0x00000008</resetValue>
+                <fields>
+                    <field>
+                        <name>PASSWD</name>
+                        <description>set to 0xaa 
+                            any other value enables the output with shift=0</description>
+                        <bitRange>[11:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ENABLE</name>
+                        <description>enable the phase-shifted output 
+                            this can be changed on-the-fly</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>FLIP</name>
+                        <description>invert the phase-shifted output 
+                            this is ignored when div=1</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SHIFT</name>
+                        <description>phase shift the phase-shifted output by SHIFT input clocks 
+                            this can be changed on-the-fly 
+                            must be set to 0 before setting div=1</description>
+                        <bitRange>[1:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>STATUS</name>
+                <addressOffset>0x0000001c</addressOffset>
+                <description>Ring Oscillator Status</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>STABLE</name>
+                        <description>Oscillator is running and stable</description>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>BADWRITE</name>
+                        <description>An invalid value has been written to CTRL_ENABLE or CTRL_FREQ_RANGE or FREQA or FREQB or DIV or PHASE or DORMANT</description>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>DIV_RUNNING</name>
+                        <description>post-divider is running 
+                            this resets to 0 but transitions to 1 during chip startup</description>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>ENABLED</name>
+                        <description>Oscillator is enabled but not necessarily running and stable 
+                            this resets to 0 but transitions to 1 during chip startup</description>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>RANDOMBIT</name>
+                <addressOffset>0x00000020</addressOffset>
+                <description>This just reads the state of the oscillator output so randomness is compromised if the ring oscillator is stopped or run at a harmonic of the bus frequency</description>
+                <resetValue>0x00000001</resetValue>
+                <fields>
+                    <field>
+                        <name>RANDOMBIT</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>COUNT</name>
+                <addressOffset>0x00000024</addressOffset>
+                <description>A down counter running at the ROSC frequency which counts to zero and stops. 
+                    To start the counter write a non-zero value. 
+                    Can be used for short software pauses when setting up time sensitive hardware.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>COUNT</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+        </registers>
+    </peripheral>
+    <peripheral>
+        <name>POWMAN</name>
+        <description>Controls vreg, bor, lposc, chip resets &amp; xosc startup, powman and provides scratch register for general use and for bootcode use</description>
+        <baseAddress>0x40100000</baseAddress>
+        <addressBlock>
+            <offset>0</offset>
+            <size>240</size>
+            <usage>registers</usage>
+        </addressBlock>
+        <interrupt>
+            <name>POWMAN_IRQ_POW</name>
+            <value>44</value>
+        </interrupt>
+        <interrupt>
+            <name>POWMAN_IRQ_TIMER</name>
+            <value>45</value>
+        </interrupt>
+        <registers>
+            <register>
+                <name>BADPASSWD</name>
+                <addressOffset>0x00000000</addressOffset>
+                <description>Indicates a bad password has been used</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>BADPASSWD</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>VREG_CTRL</name>
+                <addressOffset>0x00000004</addressOffset>
+                <description>Voltage Regulator Control</description>
+                <resetValue>0x00008050</resetValue>
+                <fields>
+                    <field>
+                        <name>RST_N</name>
+                        <description>returns the regulator to its startup settings 
+                            0 - reset 
+                            1 - not reset (default)</description>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>UNLOCK</name>
+                        <description>unlocks the VREG control interface after power up 
+                            0 - Locked (default) 
+                            1 - Unlocked 
+                            It cannot be relocked when it is unlocked.</description>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ISOLATE</name>
+                        <description>isolates the VREG control interface 
+                            0 - not isolated (default) 
+                            1 - isolated</description>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DISABLE_VOLTAGE_LIMIT</name>
+                        <description>0=not disabled, 1=enabled</description>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>HT_TH</name>
+                        <description>high temperature protection threshold 
+                            regulator power transistors are disabled when junction temperature exceeds threshold 
+                            000 - 100C 
+                            001 - 105C 
+                            010 - 110C 
+                            011 - 115C 
+                            100 - 120C 
+                            101 - 125C 
+                            110 - 135C 
+                            111 - 150C</description>
+                        <bitRange>[6:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>VREG_STS</name>
+                <addressOffset>0x00000008</addressOffset>
+                <description>Voltage Regulator Status</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>VOUT_OK</name>
+                        <description>output regulation status 
+                            0=not in regulation, 1=in regulation</description>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>STARTUP</name>
+                        <description>startup status 
+                            0=startup complete, 1=starting up</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>VREG</name>
+                <addressOffset>0x0000000c</addressOffset>
+                <description>Voltage Regulator Settings</description>
+                <resetValue>0x000000b0</resetValue>
+                <fields>
+                    <field>
+                        <name>UPDATE_IN_PROGRESS</name>
+                        <description>regulator state is being updated 
+                            writes to the vreg register will be ignored when this field is set</description>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>VSEL</name>
+                        <description>output voltage select 
+                            the regulator output voltage is limited to 1.3V unless the voltage limit 
+                            is disabled using the disable_voltage_limit field in the vreg_ctrl register 
+                            00000 - 0.55V 
+                            00001 - 0.60V 
+                            00010 - 0.65V 
+                            00011 - 0.70V 
+                            00100 - 0.75V 
+                            00101 - 0.80V 
+                            00110 - 0.85V 
+                            00111 - 0.90V 
+                            01000 - 0.95V 
+                            01001 - 1.00V 
+                            01010 - 1.05V 
+                            01011 - 1.10V (default) 
+                            01100 - 1.15V 
+                            01101 - 1.20V 
+                            01110 - 1.25V 
+                            01111 - 1.30V 
+                            10000 - 1.35V 
+                            10001 - 1.40V 
+                            10010 - 1.50V 
+                            10011 - 1.60V 
+                            10100 - 1.65V 
+                            10101 - 1.70V 
+                            10110 - 1.80V 
+                            10111 - 1.90V 
+                            11000 - 2.00V 
+                            11001 - 2.35V 
+                            11010 - 2.50V 
+                            11011 - 2.65V 
+                            11100 - 2.80V 
+                            11101 - 3.00V 
+                            11110 - 3.15V 
+                            11111 - 3.30V</description>
+                        <bitRange>[8:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>HIZ</name>
+                        <description>high impedance mode select 
+                            0=not in high impedance mode, 1=in high impedance mode</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>VREG_LP_ENTRY</name>
+                <addressOffset>0x00000010</addressOffset>
+                <description>Voltage Regulator Low Power Entry Settings</description>
+                <resetValue>0x000000b4</resetValue>
+                <fields>
+                    <field>
+                        <name>VSEL</name>
+                        <description>output voltage select 
+                            the regulator output voltage is limited to 1.3V unless the voltage limit 
+                            is disabled using the disable_voltage_limit field in the vreg_ctrl register 
+                            00000 - 0.55V 
+                            00001 - 0.60V 
+                            00010 - 0.65V 
+                            00011 - 0.70V 
+                            00100 - 0.75V 
+                            00101 - 0.80V 
+                            00110 - 0.85V 
+                            00111 - 0.90V 
+                            01000 - 0.95V 
+                            01001 - 1.00V 
+                            01010 - 1.05V 
+                            01011 - 1.10V (default) 
+                            01100 - 1.15V 
+                            01101 - 1.20V 
+                            01110 - 1.25V 
+                            01111 - 1.30V 
+                            10000 - 1.35V 
+                            10001 - 1.40V 
+                            10010 - 1.50V 
+                            10011 - 1.60V 
+                            10100 - 1.65V 
+                            10101 - 1.70V 
+                            10110 - 1.80V 
+                            10111 - 1.90V 
+                            11000 - 2.00V 
+                            11001 - 2.35V 
+                            11010 - 2.50V 
+                            11011 - 2.65V 
+                            11100 - 2.80V 
+                            11101 - 3.00V 
+                            11110 - 3.15V 
+                            11111 - 3.30V</description>
+                        <bitRange>[8:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>MODE</name>
+                        <description>selects either normal (switching) mode or low power (linear) mode 
+                            low power mode can only be selected for output voltages up to 1.3V 
+                            0 = normal mode (switching) 
+                            1 = low power mode (linear)</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>HIZ</name>
+                        <description>high impedance mode select 
+                            0=not in high impedance mode, 1=in high impedance mode</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>VREG_LP_EXIT</name>
+                <addressOffset>0x00000014</addressOffset>
+                <description>Voltage Regulator Low Power Exit Settings</description>
+                <resetValue>0x000000b0</resetValue>
+                <fields>
+                    <field>
+                        <name>VSEL</name>
+                        <description>output voltage select 
+                            the regulator output voltage is limited to 1.3V unless the voltage limit 
+                            is disabled using the disable_voltage_limit field in the vreg_ctrl register 
+                            00000 - 0.55V 
+                            00001 - 0.60V 
+                            00010 - 0.65V 
+                            00011 - 0.70V 
+                            00100 - 0.75V 
+                            00101 - 0.80V 
+                            00110 - 0.85V 
+                            00111 - 0.90V 
+                            01000 - 0.95V 
+                            01001 - 1.00V 
+                            01010 - 1.05V 
+                            01011 - 1.10V (default) 
+                            01100 - 1.15V 
+                            01101 - 1.20V 
+                            01110 - 1.25V 
+                            01111 - 1.30V 
+                            10000 - 1.35V 
+                            10001 - 1.40V 
+                            10010 - 1.50V 
+                            10011 - 1.60V 
+                            10100 - 1.65V 
+                            10101 - 1.70V 
+                            10110 - 1.80V 
+                            10111 - 1.90V 
+                            11000 - 2.00V 
+                            11001 - 2.35V 
+                            11010 - 2.50V 
+                            11011 - 2.65V 
+                            11100 - 2.80V 
+                            11101 - 3.00V 
+                            11110 - 3.15V 
+                            11111 - 3.30V</description>
+                        <bitRange>[8:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>MODE</name>
+                        <description>selects either normal (switching) mode or low power (linear) mode 
+                            low power mode can only be selected for output voltages up to 1.3V 
+                            0 = normal mode (switching) 
+                            1 = low power mode (linear)</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>HIZ</name>
+                        <description>high impedance mode select 
+                            0=not in high impedance mode, 1=in high impedance mode</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>BOD_CTRL</name>
+                <addressOffset>0x00000018</addressOffset>
+                <description>Brown-out Detection Control</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>ISOLATE</name>
+                        <description>isolates the brown-out detection control interface 
+                            0 - not isolated (default) 
+                            1 - isolated</description>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>BOD</name>
+                <addressOffset>0x0000001c</addressOffset>
+                <description>Brown-out Detection Settings</description>
+                <resetValue>0x000000b1</resetValue>
+                <fields>
+                    <field>
+                        <name>VSEL</name>
+                        <description>threshold select 
+                            00000 - 0.473V 
+                            00001 - 0.516V 
+                            00010 - 0.559V 
+                            00011 - 0.602V 
+                            00100 - 0.645VS 
+                            00101 - 0.688V 
+                            00110 - 0.731V 
+                            00111 - 0.774V 
+                            01000 - 0.817V 
+                            01001 - 0.860V (default) 
+                            01010 - 0.903V 
+                            01011 - 0.946V 
+                            01100 - 0.989V 
+                            01101 - 1.032V 
+                            01110 - 1.075V 
+                            01111 - 1.118V 
+                            10000 - 1.161 
+                            10001 - 1.204V</description>
+                        <bitRange>[8:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>EN</name>
+                        <description>enable brown-out detection 
+                            0=not enabled, 1=enabled</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>BOD_LP_ENTRY</name>
+                <addressOffset>0x00000020</addressOffset>
+                <description>Brown-out Detection Low Power Entry Settings</description>
+                <resetValue>0x000000b0</resetValue>
+                <fields>
+                    <field>
+                        <name>VSEL</name>
+                        <description>threshold select 
+                            00000 - 0.473V 
+                            00001 - 0.516V 
+                            00010 - 0.559V 
+                            00011 - 0.602V 
+                            00100 - 0.645VS 
+                            00101 - 0.688V 
+                            00110 - 0.731V 
+                            00111 - 0.774V 
+                            01000 - 0.817V 
+                            01001 - 0.860V (default) 
+                            01010 - 0.903V 
+                            01011 - 0.946V 
+                            01100 - 0.989V 
+                            01101 - 1.032V 
+                            01110 - 1.075V 
+                            01111 - 1.118V 
+                            10000 - 1.161 
+                            10001 - 1.204V</description>
+                        <bitRange>[8:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>EN</name>
+                        <description>enable brown-out detection 
+                            0=not enabled, 1=enabled</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>BOD_LP_EXIT</name>
+                <addressOffset>0x00000024</addressOffset>
+                <description>Brown-out Detection Low Power Exit Settings</description>
+                <resetValue>0x000000b1</resetValue>
+                <fields>
+                    <field>
+                        <name>VSEL</name>
+                        <description>threshold select 
+                            00000 - 0.473V 
+                            00001 - 0.516V 
+                            00010 - 0.559V 
+                            00011 - 0.602V 
+                            00100 - 0.645VS 
+                            00101 - 0.688V 
+                            00110 - 0.731V 
+                            00111 - 0.774V 
+                            01000 - 0.817V 
+                            01001 - 0.860V (default) 
+                            01010 - 0.903V 
+                            01011 - 0.946V 
+                            01100 - 0.989V 
+                            01101 - 1.032V 
+                            01110 - 1.075V 
+                            01111 - 1.118V 
+                            10000 - 1.161 
+                            10001 - 1.204V</description>
+                        <bitRange>[8:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>EN</name>
+                        <description>enable brown-out detection 
+                            0=not enabled, 1=enabled</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>LPOSC</name>
+                <addressOffset>0x00000028</addressOffset>
+                <description>Low power oscillator control register.</description>
+                <resetValue>0x00000203</resetValue>
+                <fields>
+                    <field>
+                        <name>TRIM</name>
+                        <description>Frequency trim - the trim step is typically 1% of the reset frequency, but can be up to 3%</description>
+                        <bitRange>[9:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>MODE</name>
+                        <description>This feature has been removed</description>
+                        <bitRange>[1:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CHIP_RESET</name>
+                <addressOffset>0x0000002c</addressOffset>
+                <description>Chip reset control and status</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>HAD_WATCHDOG_RESET_RSM</name>
+                        <description>Last reset was a watchdog timeout which was configured to reset the power-on state machine 
+                            This resets: 
+                            double_tap flag    no 
+                            DP                 no 
+                            RPAP               no 
+                            rescue_flag        no 
+                            timer              no 
+                            powman             no 
+                            swcore             no 
+                            psm                yes 
+                            and does not change the power state</description>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>HAD_HZD_SYS_RESET_REQ</name>
+                        <description>Last reset was a system reset from the hazard debugger 
+                            This resets: 
+                            double_tap flag    no 
+                            DP                 no 
+                            RPAP               no 
+                            rescue_flag        no 
+                            timer              no 
+                            powman             no 
+                            swcore             no 
+                            psm                yes 
+                            and does not change the power state</description>
+                        <bitRange>[27:27]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>HAD_GLITCH_DETECT</name>
+                        <description>Last reset was due to a power supply glitch 
+                            This resets: 
+                            double_tap flag    no 
+                            DP                 no 
+                            RPAP               no 
+                            rescue_flag        no 
+                            timer              no 
+                            powman             no 
+                            swcore             no 
+                            psm                yes 
+                            and does not change the power state</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>HAD_SWCORE_PD</name>
+                        <description>Last reset was a switched core powerdown 
+                            This resets: 
+                            double_tap flag    no 
+                            DP                 no 
+                            RPAP               no 
+                            rescue_flag        no 
+                            timer              no 
+                            powman             no 
+                            swcore             yes 
+                            psm                yes 
+                            then starts the power sequencer</description>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>HAD_WATCHDOG_RESET_SWCORE</name>
+                        <description>Last reset was a watchdog timeout which was configured to reset the switched-core 
+                            This resets: 
+                            double_tap flag    no 
+                            DP                 no 
+                            RPAP               no 
+                            rescue_flag        no 
+                            timer              no 
+                            powman             no 
+                            swcore             yes 
+                            psm                yes 
+                            then starts the power sequencer</description>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>HAD_WATCHDOG_RESET_POWMAN</name>
+                        <description>Last reset was a watchdog timeout which was configured to reset the power manager 
+                            This resets: 
+                            double_tap flag    no 
+                            DP                 no 
+                            RPAP               no 
+                            rescue_flag        no 
+                            timer              yes 
+                            powman             yes 
+                            swcore             yes 
+                            psm                yes 
+                            then starts the power sequencer</description>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>HAD_WATCHDOG_RESET_POWMAN_ASYNC</name>
+                        <description>Last reset was a watchdog timeout which was configured to reset the power manager asynchronously 
+                            This resets: 
+                            double_tap flag    no 
+                            DP                 no 
+                            RPAP               no 
+                            rescue_flag        no 
+                            timer              yes 
+                            powman             yes 
+                            swcore             yes 
+                            psm                yes 
+                            then starts the power sequencer</description>
+                        <bitRange>[22:22]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>HAD_RESCUE</name>
+                        <description>Last reset was a rescue reset from the debugger 
+                            This resets: 
+                            double_tap flag    no 
+                            DP                 no 
+                            RPAP               no 
+                            rescue_flag        no, it sets this flag 
+                            timer              yes 
+                            powman             yes 
+                            swcore             yes 
+                            psm                yes 
+                            then starts the power sequencer</description>
+                        <bitRange>[21:21]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>HAD_DP_RESET_REQ</name>
+                        <description>Last reset was an reset request from the arm debugger 
+                            This resets: 
+                            double_tap flag    no 
+                            DP                 no 
+                            RPAP               no 
+                            rescue_flag        yes 
+                            timer              yes 
+                            powman             yes 
+                            swcore             yes 
+                            psm                yes 
+                            then starts the power sequencer</description>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>HAD_RUN_LOW</name>
+                        <description>Last reset was from the RUN pin 
+                            This resets: 
+                            double_tap flag    no 
+                            DP                 yes 
+                            RPAP               yes 
+                            rescue_flag        yes 
+                            timer              yes 
+                            powman             yes 
+                            swcore             yes 
+                            psm                yes 
+                            then starts the power sequencer</description>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>HAD_BOR</name>
+                        <description>Last reset was from the brown-out detection block 
+                            This resets: 
+                            double_tap flag    yes 
+                            DP                 yes 
+                            RPAP               yes 
+                            rescue_flag        yes 
+                            timer              yes 
+                            powman             yes 
+                            swcore             yes 
+                            psm                yes 
+                            then starts the power sequencer</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>HAD_POR</name>
+                        <description>Last reset was from the power-on reset 
+                            This resets: 
+                            double_tap flag    yes 
+                            DP                 yes 
+                            RPAP               yes 
+                            rescue_flag        yes 
+                            timer              yes 
+                            powman             yes 
+                            swcore             yes 
+                            psm                yes 
+                            then starts the power sequencer</description>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>RESCUE_FLAG</name>
+                        <description>This is set by a rescue reset from the RP-AP. 
+                            Its purpose is to halt before the bootrom before booting from flash in order to recover from a boot lock-up. 
+                            The debugger can then attach once the bootrom has been halted and flash some working code that does not lock up.</description>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>DOUBLE_TAP</name>
+                        <description>This flag is set by double-tapping RUN. It tells bootcode to go into the bootloader.</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>WDSEL</name>
+                <addressOffset>0x00000030</addressOffset>
+                <description>Allows a watchdog reset to reset the internal state of powman in addition to the power-on state machine (PSM). 
+                    Note that powman ignores watchdog resets that do not select at least the CLOCKS stage or earlier stages in the PSM. If using these bits, it&#39;s recommended to set PSM_WDSEL to all-ones in addition to the desired bits in this register. Failing to select CLOCKS or earlier will result in the POWMAN_WDSEL register having no effect.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>RESET_RSM</name>
+                        <description>If set to 1, a watchdog reset will run the full power-on state machine (PSM) sequence 
+                            From a user perspective it is the same as setting RSM_WDSEL_PROC_COLD 
+                            From a hardware debug perspective it has the same effect as a reset from a glitch detector</description>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>RESET_SWCORE</name>
+                        <description>If set to 1, a watchdog reset will reset the switched core power domain and run the full power-on state machine (PSM) sequence 
+                            From a user perspective it is the same as setting RSM_WDSEL_PROC_COLD 
+                            From a hardware debug perspective it has the same effect as a power-on reset for the switched core power domain</description>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>RESET_POWMAN</name>
+                        <description>If set to 1, a watchdog reset will restore powman defaults, reset the timer, reset the switched core power domain 
+                            and run the full power-on state machine (PSM) sequence 
+                            This relies on clk_ref running. Use reset_powman_async if that may not be true</description>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>RESET_POWMAN_ASYNC</name>
+                        <description>If set to 1, a watchdog reset will restore powman defaults, reset the timer, 
+                            reset the switched core domain and run the full power-on state machine (PSM) sequence 
+                            This does not rely on clk_ref running</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SEQ_CFG</name>
+                <addressOffset>0x00000034</addressOffset>
+                <description>For configuration of the power sequencer 
+                    Writes are ignored while POWMAN_STATE_CHANGING=1</description>
+                <resetValue>0x001011f0</resetValue>
+                <fields>
+                    <field>
+                        <name>USING_FAST_POWCK</name>
+                        <description>0 indicates the POWMAN clock is running from the low power oscillator (32kHz) 
+                            1 indicates the POWMAN clock is running from the reference clock (2-50MHz)</description>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>USING_BOD_LP</name>
+                        <description>Indicates the brown-out detector (BOD) mode 
+                            0 = BOD high power mode which is the default 
+                            1 = BOD low power mode</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>USING_VREG_LP</name>
+                        <description>Indicates the voltage regulator (VREG) mode 
+                            0 = VREG high power mode which is the default 
+                            1 = VREG low power mode</description>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>USE_FAST_POWCK</name>
+                        <description>selects the reference clock (clk_ref) as the source of the POWMAN clock when switched-core is powered. The POWMAN clock always switches to the slow clock (lposc) when switched-core is powered down because the fast clock stops running. 
+                            0 always run the POWMAN clock from the slow clock (lposc) 
+                            1 run the POWMAN clock from the fast clock when available 
+                            This setting takes effect when a power up sequence is next run</description>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>RUN_LPOSC_IN_LP</name>
+                        <description>Set to 0 to stop the low power osc when the switched-core is powered down, which is unwise if using it to clock the timer 
+                            This setting takes effect when the swcore is next powered down</description>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>USE_BOD_HP</name>
+                        <description>Set to 0 to prevent automatic switching to bod high power mode when switched-core is powered up 
+                            This setting takes effect when the swcore is next powered up</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>USE_BOD_LP</name>
+                        <description>Set to 0 to prevent automatic switching to bod low power mode when switched-core is powered down 
+                            This setting takes effect when the swcore is next powered down</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>USE_VREG_HP</name>
+                        <description>Set to 0 to prevent automatic switching to vreg high power mode when switched-core is powered up 
+                            This setting takes effect when the swcore is next powered up</description>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>USE_VREG_LP</name>
+                        <description>Set to 0 to prevent automatic switching to vreg low power mode when switched-core is powered down 
+                            This setting takes effect when the swcore is next powered down</description>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>HW_PWRUP_SRAM0</name>
+                        <description>Specifies the power state of SRAM0 when powering up swcore from a low power state (P1.xxx) to a high power state (P0.0xx). 
+                            0=power-up 
+                            1=no change</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>HW_PWRUP_SRAM1</name>
+                        <description>Specifies the power state of SRAM1 when powering up swcore from a low power state (P1.xxx) to a high power state (P0.0xx). 
+                            0=power-up 
+                            1=no change</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>STATE</name>
+                <addressOffset>0x00000038</addressOffset>
+                <description>This register controls the power state of the 4 power domains. 
+                    The current power state is indicated in POWMAN_STATE_CURRENT which is read-only. 
+                    To change the state, write to POWMAN_STATE_REQ. 
+                    The coding of POWMAN_STATE_CURRENT &amp; POWMAN_STATE_REQ corresponds to the power states 
+                    defined in the datasheet: 
+                    bit 3 = SWCORE 
+                    bit 2 = XIP cache 
+                    bit 1 = SRAM0 
+                    bit 0 = SRAM1 
+                    0 = powered up 
+                    1 = powered down 
+                    When POWMAN_STATE_REQ is written, the POWMAN_STATE_WAITING flag is set while the Power Manager determines what is required. If an invalid transition is requested the Power Manager will still register the request in POWMAN_STATE_REQ but will also set the POWMAN_BAD_REQ flag. It will then implement the power-up requests and ignore the power down requests. To do nothing would risk entering an unrecoverable lock-up state. Invalid requests are: any combination of power up and power down requests any request that results in swcore boing powered and xip unpowered If the request is to power down the switched-core domain then POWMAN_STATE_WAITING stays active until the processors halt. During this time the POWMAN_STATE_REQ field can be re-written to change or cancel the request. When the power state transition begins the POWMAN_STATE_WAITING_flag is cleared, the POWMAN_STATE_CHANGING flag is set and POWMAN register writes are ignored until the transition completes.</description>
+                <resetValue>0x0000000f</resetValue>
+                <fields>
+                    <field>
+                        <name>CHANGING</name>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>WAITING</name>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>BAD_HW_REQ</name>
+                        <description>Bad hardware initiated state request. Went back to state 0 (i.e. everything powered up)</description>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>BAD_SW_REQ</name>
+                        <description>Bad software initiated state request. No action taken.</description>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>PWRUP_WHILE_WAITING</name>
+                        <description>Request ignored because of a pending pwrup request. See current_pwrup_req. Note this blocks powering up AND powering down.</description>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>REQ_IGNORED</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>REQ</name>
+                        <bitRange>[7:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CURRENT</name>
+                        <bitRange>[3:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>POW_FASTDIV</name>
+                <addressOffset>0x0000003c</addressOffset>
+                <resetValue>0x00000040</resetValue>
+                <fields>
+                    <field>
+                        <name>POW_FASTDIV</name>
+                        <description>divides the POWMAN clock to provide a tick for the delay module and state machines 
+                            when clk_pow is running from the slow clock it is not divided 
+                            when clk_pow is running from the fast clock it is divided by tick_div</description>
+                        <bitRange>[10:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>POW_DELAY</name>
+                <addressOffset>0x00000040</addressOffset>
+                <description>power state machine delays</description>
+                <resetValue>0x00002011</resetValue>
+                <fields>
+                    <field>
+                        <name>SRAM_STEP</name>
+                        <description>timing between the sram0 and sram1 power state machine steps 
+                            measured in units of the powman tick period (&gt;=1us), 0 gives a delay of 1 unit</description>
+                        <bitRange>[15:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>XIP_STEP</name>
+                        <description>timing between the xip power state machine steps 
+                            measured in units of the lposc period, 0 gives a delay of 1 unit</description>
+                        <bitRange>[7:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SWCORE_STEP</name>
+                        <description>timing between the swcore power state machine steps 
+                            measured in units of the lposc period, 0 gives a delay of 1 unit</description>
+                        <bitRange>[3:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>EXT_CTRL0</name>
+                <addressOffset>0x00000044</addressOffset>
+                <description>Configures a gpio as a power mode aware control output</description>
+                <resetValue>0x0000003f</resetValue>
+                <fields>
+                    <field>
+                        <name>LP_EXIT_STATE</name>
+                        <description>output level when exiting the low power state</description>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LP_ENTRY_STATE</name>
+                        <description>output level when entering the low power state</description>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INIT_STATE</name>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INIT</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_SELECT</name>
+                        <description>selects from gpio 0-&gt;30 
+                            set to 31 to disable this feature</description>
+                        <bitRange>[5:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>EXT_CTRL1</name>
+                <addressOffset>0x00000048</addressOffset>
+                <description>Configures a gpio as a power mode aware control output</description>
+                <resetValue>0x0000003f</resetValue>
+                <fields>
+                    <field>
+                        <name>LP_EXIT_STATE</name>
+                        <description>output level when exiting the low power state</description>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LP_ENTRY_STATE</name>
+                        <description>output level when entering the low power state</description>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INIT_STATE</name>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INIT</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO_SELECT</name>
+                        <description>selects from gpio 0-&gt;30 
+                            set to 31 to disable this feature</description>
+                        <bitRange>[5:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>EXT_TIME_REF</name>
+                <addressOffset>0x0000004c</addressOffset>
+                <description>Select a GPIO to use as a time reference, the source can be used to drive the low power clock at 32kHz, or to provide a 1ms tick to the timer, or provide a 1Hz tick to the timer. The tick selection is controlled by the POWMAN_TIMER register.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>DRIVE_LPCK</name>
+                        <description>Use the selected GPIO to drive the 32kHz low power clock, in place of LPOSC. This field must only be written when POWMAN_TIMER_RUN=0</description>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SOURCE_SEL</name>
+                        <description>0 -&gt;  gpio12 
+                            1 -&gt;  gpio20 
+                            2 -&gt;  gpio14 
+                            3 -&gt;  gpio22</description>
+                        <bitRange>[1:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>LPOSC_FREQ_KHZ_INT</name>
+                <addressOffset>0x00000050</addressOffset>
+                <description>Informs the AON Timer of the integer component of the clock frequency when running off the LPOSC.</description>
+                <resetValue>0x00000020</resetValue>
+                <fields>
+                    <field>
+                        <name>LPOSC_FREQ_KHZ_INT</name>
+                        <description>Integer component of the LPOSC or GPIO clock source frequency in kHz. Default = 32 This field must only be written when POWMAN_TIMER_RUN=0 or POWMAN_TIMER_USING_XOSC=1</description>
+                        <bitRange>[5:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>LPOSC_FREQ_KHZ_FRAC</name>
+                <addressOffset>0x00000054</addressOffset>
+                <description>Informs the AON Timer of the fractional component of the clock frequency when running off the LPOSC.</description>
+                <resetValue>0x0000c49c</resetValue>
+                <fields>
+                    <field>
+                        <name>LPOSC_FREQ_KHZ_FRAC</name>
+                        <description>Fractional component of the LPOSC or GPIO clock source frequency in kHz. Default = 0.768 This field must only be written when POWMAN_TIMER_RUN=0 or POWMAN_TIMER_USING_XOSC=1</description>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>XOSC_FREQ_KHZ_INT</name>
+                <addressOffset>0x00000058</addressOffset>
+                <description>Informs the AON Timer of the integer component of the clock frequency when running off the XOSC.</description>
+                <resetValue>0x00002ee0</resetValue>
+                <fields>
+                    <field>
+                        <name>XOSC_FREQ_KHZ_INT</name>
+                        <description>Integer component of the XOSC frequency in kHz. Default = 12000 Must be &gt;1 This field must only be written when POWMAN_TIMER_RUN=0 or POWMAN_TIMER_USING_XOSC=0</description>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>XOSC_FREQ_KHZ_FRAC</name>
+                <addressOffset>0x0000005c</addressOffset>
+                <description>Informs the AON Timer of the fractional component of the clock frequency when running off the XOSC.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>XOSC_FREQ_KHZ_FRAC</name>
+                        <description>Fractional component of the XOSC frequency in kHz. This field must only be written when POWMAN_TIMER_RUN=0 or POWMAN_TIMER_USING_XOSC=0</description>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SET_TIME_63TO48</name>
+                <addressOffset>0x00000060</addressOffset>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>SET_TIME_63TO48</name>
+                        <description>For setting the time, do not use for reading the time, use POWMAN_READ_TIME_UPPER and POWMAN_READ_TIME_LOWER. This field must only be written when POWMAN_TIMER_RUN=0</description>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SET_TIME_47TO32</name>
+                <addressOffset>0x00000064</addressOffset>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>SET_TIME_47TO32</name>
+                        <description>For setting the time, do not use for reading the time, use POWMAN_READ_TIME_UPPER and POWMAN_READ_TIME_LOWER. This field must only be written when POWMAN_TIMER_RUN=0</description>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SET_TIME_31TO16</name>
+                <addressOffset>0x00000068</addressOffset>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>SET_TIME_31TO16</name>
+                        <description>For setting the time, do not use for reading the time, use POWMAN_READ_TIME_UPPER and POWMAN_READ_TIME_LOWER. This field must only be written when POWMAN_TIMER_RUN=0</description>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SET_TIME_15TO0</name>
+                <addressOffset>0x0000006c</addressOffset>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>SET_TIME_15TO0</name>
+                        <description>For setting the time, do not use for reading the time, use POWMAN_READ_TIME_UPPER and POWMAN_READ_TIME_LOWER. This field must only be written when POWMAN_TIMER_RUN=0</description>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>READ_TIME_UPPER</name>
+                <addressOffset>0x00000070</addressOffset>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>READ_TIME_UPPER</name>
+                        <description>For reading bits 63:32 of the timer. When reading all 64 bits it is possible for the LOWER count to rollover during the read. It is recommended to read UPPER, then LOWER, then re-read UPPER and, if it has changed, re-read LOWER.</description>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>READ_TIME_LOWER</name>
+                <addressOffset>0x00000074</addressOffset>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>READ_TIME_LOWER</name>
+                        <description>For reading bits 31:0 of the timer.</description>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>ALARM_TIME_63TO48</name>
+                <addressOffset>0x00000078</addressOffset>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>ALARM_TIME_63TO48</name>
+                        <description>This field must only be written when POWMAN_ALARM_ENAB=0</description>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>ALARM_TIME_47TO32</name>
+                <addressOffset>0x0000007c</addressOffset>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>ALARM_TIME_47TO32</name>
+                        <description>This field must only be written when POWMAN_ALARM_ENAB=0</description>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>ALARM_TIME_31TO16</name>
+                <addressOffset>0x00000080</addressOffset>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>ALARM_TIME_31TO16</name>
+                        <description>This field must only be written when POWMAN_ALARM_ENAB=0</description>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>ALARM_TIME_15TO0</name>
+                <addressOffset>0x00000084</addressOffset>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>ALARM_TIME_15TO0</name>
+                        <description>This field must only be written when POWMAN_ALARM_ENAB=0</description>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>TIMER</name>
+                <addressOffset>0x00000088</addressOffset>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>USING_GPIO_1HZ</name>
+                        <description>Timer is synchronised to a 1hz gpio source</description>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>USING_GPIO_1KHZ</name>
+                        <description>Timer is running from a 1khz gpio source</description>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>USING_LPOSC</name>
+                        <description>Timer is running from lposc</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>USING_XOSC</name>
+                        <description>Timer is running from xosc</description>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>USE_GPIO_1HZ</name>
+                        <description>Selects the gpio source as the reference for the sec counter. The msec counter will continue to use the lposc or xosc reference.</description>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>USE_GPIO_1KHZ</name>
+                        <description>switch to gpio as the source of the 1kHz timer tick</description>
+                        <bitRange>[10:10]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>USE_XOSC</name>
+                        <description>switch to xosc as the source of the 1kHz timer tick</description>
+                        <bitRange>[9:9]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>USE_LPOSC</name>
+                        <description>Switch to lposc as the source of the 1kHz timer tick</description>
+                        <bitRange>[8:8]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>ALARM</name>
+                        <description>Alarm has fired. Write to 1 to clear the alarm.</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>PWRUP_ON_ALARM</name>
+                        <description>Alarm wakes the chip from low power mode</description>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ALARM_ENAB</name>
+                        <description>Enables the alarm. The alarm must be disabled while writing the alarm time.</description>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CLEAR</name>
+                        <description>Clears the timer, does not disable the timer and does not affect the alarm. This control can be written at any time.</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>RUN</name>
+                        <description>Timer enable. Setting this bit causes the timer to begin counting up from its current value. Clearing this bit stops the timer from counting.
+
+                            Before enabling the timer, set the POWMAN_LPOSC_FREQ* and POWMAN_XOSC_FREQ* registers to configure the count rate, and initialise the current time by writing to SET_TIME_63TO48 through SET_TIME_15TO0. You must not write to the SET_TIME_x registers when the timer is running.
+
+                            Once configured, start the timer by setting POWMAN_TIMER_RUN=1. This will start the timer running from the LPOSC. When the XOSC is available switch the reference clock to XOSC then select it as the timer clock by setting POWMAN_TIMER_USE_XOSC=1</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>NONSEC_WRITE</name>
+                        <description>Control whether Non-secure software can write to the timer registers. All other registers are hardwired to be inaccessible to Non-secure.</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PWRUP0</name>
+                <addressOffset>0x0000008c</addressOffset>
+                <description>4 GPIO powerup events can be configured to wake the chip up from a low power state. 
+                    The pwrups are level/edge sensitive and can be set to trigger on a high/rising or low/falling event 
+                    The number of gpios available depends on the package option. An invalid selection will be ignored 
+                    source = 0 selects gpio0 
+                    . 
+                    . 
+                    source = 47 selects gpio47 
+                    source = 48 selects qspi_ss 
+                    source = 49 selects qspi_sd0 
+                    source = 50 selects qspi_sd1 
+                    source = 51 selects qspi_sd2 
+                    source = 52 selects qspi_sd3 
+                    source = 53 selects qspi_sclk 
+                    level  = 0 triggers the pwrup when the source is low 
+                    level  = 1 triggers the pwrup when the source is high</description>
+                <resetValue>0x0000003f</resetValue>
+                <fields>
+                    <field>
+                        <name>RAW_STATUS</name>
+                        <description>Value of selected gpio pin (only if enable == 1)</description>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>STATUS</name>
+                        <description>Status of gpio wakeup. Write to 1 to clear a latched edge detect.</description>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>MODE</name>
+                        <description>Edge or level detect. Edge will detect a 0 to 1 transition (or 1 to 0 transition). Level will detect a 1 or 0. Both types of event get latched into the current_pwrup_req register.</description>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>level</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>edge</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>DIRECTION</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>low_falling</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>high_rising</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>ENABLE</name>
+                        <description>Set to 1 to enable the wakeup source. Set to 0 to disable the wakeup source and clear a pending wakeup event. 
+                            If using edge detect a latched edge needs to be cleared by writing 1 to the status register also.</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SOURCE</name>
+                        <bitRange>[5:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PWRUP1</name>
+                <addressOffset>0x00000090</addressOffset>
+                <description>4 GPIO powerup events can be configured to wake the chip up from a low power state. 
+                    The pwrups are level/edge sensitive and can be set to trigger on a high/rising or low/falling event 
+                    The number of gpios available depends on the package option. An invalid selection will be ignored 
+                    source = 0 selects gpio0 
+                    . 
+                    . 
+                    source = 47 selects gpio47 
+                    source = 48 selects qspi_ss 
+                    source = 49 selects qspi_sd0 
+                    source = 50 selects qspi_sd1 
+                    source = 51 selects qspi_sd2 
+                    source = 52 selects qspi_sd3 
+                    source = 53 selects qspi_sclk 
+                    level  = 0 triggers the pwrup when the source is low 
+                    level  = 1 triggers the pwrup when the source is high</description>
+                <resetValue>0x0000003f</resetValue>
+                <fields>
+                    <field>
+                        <name>RAW_STATUS</name>
+                        <description>Value of selected gpio pin (only if enable == 1)</description>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>STATUS</name>
+                        <description>Status of gpio wakeup. Write to 1 to clear a latched edge detect.</description>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>MODE</name>
+                        <description>Edge or level detect. Edge will detect a 0 to 1 transition (or 1 to 0 transition). Level will detect a 1 or 0. Both types of event get latched into the current_pwrup_req register.</description>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>level</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>edge</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>DIRECTION</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>low_falling</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>high_rising</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>ENABLE</name>
+                        <description>Set to 1 to enable the wakeup source. Set to 0 to disable the wakeup source and clear a pending wakeup event. 
+                            If using edge detect a latched edge needs to be cleared by writing 1 to the status register also.</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SOURCE</name>
+                        <bitRange>[5:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PWRUP2</name>
+                <addressOffset>0x00000094</addressOffset>
+                <description>4 GPIO powerup events can be configured to wake the chip up from a low power state. 
+                    The pwrups are level/edge sensitive and can be set to trigger on a high/rising or low/falling event 
+                    The number of gpios available depends on the package option. An invalid selection will be ignored 
+                    source = 0 selects gpio0 
+                    . 
+                    . 
+                    source = 47 selects gpio47 
+                    source = 48 selects qspi_ss 
+                    source = 49 selects qspi_sd0 
+                    source = 50 selects qspi_sd1 
+                    source = 51 selects qspi_sd2 
+                    source = 52 selects qspi_sd3 
+                    source = 53 selects qspi_sclk 
+                    level  = 0 triggers the pwrup when the source is low 
+                    level  = 1 triggers the pwrup when the source is high</description>
+                <resetValue>0x0000003f</resetValue>
+                <fields>
+                    <field>
+                        <name>RAW_STATUS</name>
+                        <description>Value of selected gpio pin (only if enable == 1)</description>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>STATUS</name>
+                        <description>Status of gpio wakeup. Write to 1 to clear a latched edge detect.</description>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>MODE</name>
+                        <description>Edge or level detect. Edge will detect a 0 to 1 transition (or 1 to 0 transition). Level will detect a 1 or 0. Both types of event get latched into the current_pwrup_req register.</description>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>level</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>edge</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>DIRECTION</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>low_falling</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>high_rising</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>ENABLE</name>
+                        <description>Set to 1 to enable the wakeup source. Set to 0 to disable the wakeup source and clear a pending wakeup event. 
+                            If using edge detect a latched edge needs to be cleared by writing 1 to the status register also.</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SOURCE</name>
+                        <bitRange>[5:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PWRUP3</name>
+                <addressOffset>0x00000098</addressOffset>
+                <description>4 GPIO powerup events can be configured to wake the chip up from a low power state. 
+                    The pwrups are level/edge sensitive and can be set to trigger on a high/rising or low/falling event 
+                    The number of gpios available depends on the package option. An invalid selection will be ignored 
+                    source = 0 selects gpio0 
+                    . 
+                    . 
+                    source = 47 selects gpio47 
+                    source = 48 selects qspi_ss 
+                    source = 49 selects qspi_sd0 
+                    source = 50 selects qspi_sd1 
+                    source = 51 selects qspi_sd2 
+                    source = 52 selects qspi_sd3 
+                    source = 53 selects qspi_sclk 
+                    level  = 0 triggers the pwrup when the source is low 
+                    level  = 1 triggers the pwrup when the source is high</description>
+                <resetValue>0x0000003f</resetValue>
+                <fields>
+                    <field>
+                        <name>RAW_STATUS</name>
+                        <description>Value of selected gpio pin (only if enable == 1)</description>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>STATUS</name>
+                        <description>Status of gpio wakeup. Write to 1 to clear a latched edge detect.</description>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>MODE</name>
+                        <description>Edge or level detect. Edge will detect a 0 to 1 transition (or 1 to 0 transition). Level will detect a 1 or 0. Both types of event get latched into the current_pwrup_req register.</description>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>level</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>edge</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>DIRECTION</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>low_falling</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>high_rising</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>ENABLE</name>
+                        <description>Set to 1 to enable the wakeup source. Set to 0 to disable the wakeup source and clear a pending wakeup event. 
+                            If using edge detect a latched edge needs to be cleared by writing 1 to the status register also.</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SOURCE</name>
+                        <bitRange>[5:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CURRENT_PWRUP_REQ</name>
+                <addressOffset>0x0000009c</addressOffset>
+                <description>Indicates current powerup request state 
+                    pwrup events can be cleared by removing the enable from the pwrup register. The alarm pwrup req can be cleared by clearing timer.alarm_enab 
+                    0 = chip reset, for the source of the last reset see POWMAN_CHIP_RESET 
+                    1 = pwrup0 
+                    2 = pwrup1 
+                    3 = pwrup2 
+                    4 = pwrup3 
+                    5 = coresight_pwrup 
+                    6 = alarm_pwrup</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CURRENT_PWRUP_REQ</name>
+                        <bitRange>[6:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>LAST_SWCORE_PWRUP</name>
+                <addressOffset>0x000000a0</addressOffset>
+                <description>Indicates which pwrup source triggered the last switched-core power up 
+                    0 = chip reset, for the source of the last reset see POWMAN_CHIP_RESET 
+                    1 = pwrup0 
+                    2 = pwrup1 
+                    3 = pwrup2 
+                    4 = pwrup3 
+                    5 = coresight_pwrup 
+                    6 = alarm_pwrup</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>LAST_SWCORE_PWRUP</name>
+                        <bitRange>[6:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>DBG_PWRCFG</name>
+                <addressOffset>0x000000a4</addressOffset>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>IGNORE</name>
+                        <description>Ignore pwrup req from debugger. If pwrup req is asserted then this will prevent power down and set powerdown blocked. Set ignore to stop paying attention to pwrup_req</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>BOOTDIS</name>
+                <addressOffset>0x000000a8</addressOffset>
+                <description>Tell the bootrom to ignore the BOOT0..3 registers following the next RSM reset (e.g. the next core power down/up).
+
+                    If an early boot stage has soft-locked some OTP pages in order to protect their contents from later stages, there is a risk that Secure code running at a later stage can unlock the pages by powering the core up and down.
+
+                    This register can be used to ensure that the bootloader runs as normal on the next power up, preventing Secure code at a later stage from accessing OTP in its unlocked state.
+
+                    Should be used in conjunction with the OTP BOOTDIS register.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>NEXT</name>
+                        <description>This flag always ORs writes into its current contents. It can be set but not cleared by software.
+
+                            The BOOTDIS_NEXT bit is OR&#39;d into the BOOTDIS_NOW bit when the core is powered down. Simultaneously, the BOOTDIS_NEXT bit is cleared. Setting this bit means that the BOOT0..3 registers will be ignored following the next reset of the RSM by powman.
+
+                            This flag should be set by an early boot stage that has soft-locked OTP pages, to prevent later stages from unlocking it by power cycling.</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>NOW</name>
+                        <description>When powman resets the RSM, the current value of BOOTDIS_NEXT is OR&#39;d into BOOTDIS_NOW, and BOOTDIS_NEXT is cleared.
+
+                            The bootrom checks this flag before reading the BOOT0..3 registers. If it is set, the bootrom clears it, and ignores the BOOT registers. This prevents Secure software from diverting the boot path before a bootloader has had the chance to soft lock OTP pages containing sensitive data.</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>DBGCONFIG</name>
+                <addressOffset>0x000000ac</addressOffset>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>DP_INSTID</name>
+                        <description>Configure DP instance ID for SWD multidrop selection. 
+                            Recommend that this is NOT changed until you require debug access in multi-chip environment</description>
+                        <bitRange>[3:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SCRATCH0</name>
+                <addressOffset>0x000000b0</addressOffset>
+                <description>Scratch register. Information persists in low power mode</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>SCRATCH0</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SCRATCH1</name>
+                <addressOffset>0x000000b4</addressOffset>
+                <description>Scratch register. Information persists in low power mode</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>SCRATCH1</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SCRATCH2</name>
+                <addressOffset>0x000000b8</addressOffset>
+                <description>Scratch register. Information persists in low power mode</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>SCRATCH2</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SCRATCH3</name>
+                <addressOffset>0x000000bc</addressOffset>
+                <description>Scratch register. Information persists in low power mode</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>SCRATCH3</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SCRATCH4</name>
+                <addressOffset>0x000000c0</addressOffset>
+                <description>Scratch register. Information persists in low power mode</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>SCRATCH4</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SCRATCH5</name>
+                <addressOffset>0x000000c4</addressOffset>
+                <description>Scratch register. Information persists in low power mode</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>SCRATCH5</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SCRATCH6</name>
+                <addressOffset>0x000000c8</addressOffset>
+                <description>Scratch register. Information persists in low power mode</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>SCRATCH6</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SCRATCH7</name>
+                <addressOffset>0x000000cc</addressOffset>
+                <description>Scratch register. Information persists in low power mode</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>SCRATCH7</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>BOOT0</name>
+                <addressOffset>0x000000d0</addressOffset>
+                <description>Scratch register. Information persists in low power mode</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>BOOT0</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>BOOT1</name>
+                <addressOffset>0x000000d4</addressOffset>
+                <description>Scratch register. Information persists in low power mode</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>BOOT1</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>BOOT2</name>
+                <addressOffset>0x000000d8</addressOffset>
+                <description>Scratch register. Information persists in low power mode</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>BOOT2</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>BOOT3</name>
+                <addressOffset>0x000000dc</addressOffset>
+                <description>Scratch register. Information persists in low power mode</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>BOOT3</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INTR</name>
+                <addressOffset>0x000000e0</addressOffset>
+                <description>Raw Interrupts</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>PWRUP_WHILE_WAITING</name>
+                        <description>Source is state.pwrup_while_waiting</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>STATE_REQ_IGNORED</name>
+                        <description>Source is state.req_ignored</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>TIMER</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>VREG_OUTPUT_LOW</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INTE</name>
+                <addressOffset>0x000000e4</addressOffset>
+                <description>Interrupt Enable</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>PWRUP_WHILE_WAITING</name>
+                        <description>Source is state.pwrup_while_waiting</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>STATE_REQ_IGNORED</name>
+                        <description>Source is state.req_ignored</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>TIMER</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>VREG_OUTPUT_LOW</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INTF</name>
+                <addressOffset>0x000000e8</addressOffset>
+                <description>Interrupt Force</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>PWRUP_WHILE_WAITING</name>
+                        <description>Source is state.pwrup_while_waiting</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>STATE_REQ_IGNORED</name>
+                        <description>Source is state.req_ignored</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>TIMER</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>VREG_OUTPUT_LOW</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INTS</name>
+                <addressOffset>0x000000ec</addressOffset>
+                <description>Interrupt status after masking &amp; forcing</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>PWRUP_WHILE_WAITING</name>
+                        <description>Source is state.pwrup_while_waiting</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>STATE_REQ_IGNORED</name>
+                        <description>Source is state.req_ignored</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>TIMER</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>VREG_OUTPUT_LOW</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+        </registers>
+    </peripheral>
+    <peripheral>
+        <name>WATCHDOG</name>
+        <baseAddress>0x400d8000</baseAddress>
+        <addressBlock>
+            <offset>0</offset>
+            <size>44</size>
+            <usage>registers</usage>
+        </addressBlock>
+        <registers>
+            <register>
+                <name>CTRL</name>
+                <addressOffset>0x00000000</addressOffset>
+                <description>Watchdog control 
+                    The rst_wdsel register determines which subsystems are reset when the watchdog is triggered. 
+                    The watchdog can be triggered in software.</description>
+                <resetValue>0x07000000</resetValue>
+                <fields>
+                    <field>
+                        <name>TRIGGER</name>
+                        <description>Trigger a watchdog reset</description>
+                        <bitRange>[31:31]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>ENABLE</name>
+                        <description>When not enabled the watchdog timer is paused</description>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PAUSE_DBG1</name>
+                        <description>Pause the watchdog timer when processor 1 is in debug mode</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PAUSE_DBG0</name>
+                        <description>Pause the watchdog timer when processor 0 is in debug mode</description>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PAUSE_JTAG</name>
+                        <description>Pause the watchdog timer when JTAG is accessing the bus fabric</description>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>TIME</name>
+                        <description>Indicates the time in usec before a watchdog reset will be triggered</description>
+                        <bitRange>[23:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>LOAD</name>
+                <addressOffset>0x00000004</addressOffset>
+                <description>Load the watchdog timer. The maximum setting is 0xffffff which corresponds to approximately 16 seconds.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>LOAD</name>
+                        <bitRange>[23:0]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>REASON</name>
+                <addressOffset>0x00000008</addressOffset>
+                <description>Logs the reason for the last reset. Both bits are zero for the case of a hardware reset.
+
+                    Additionally, as of RP2350, a debugger warm reset of either core (SYSRESETREQ or hartreset) will also clear the watchdog reason register, so that software loaded under the debugger following a watchdog timeout will not continue to see the timeout condition.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>FORCE</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>TIMER</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SCRATCH0</name>
+                <addressOffset>0x0000000c</addressOffset>
+                <description>Scratch register. Information persists through soft reset of the chip.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>SCRATCH0</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SCRATCH1</name>
+                <addressOffset>0x00000010</addressOffset>
+                <description>Scratch register. Information persists through soft reset of the chip.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>SCRATCH1</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SCRATCH2</name>
+                <addressOffset>0x00000014</addressOffset>
+                <description>Scratch register. Information persists through soft reset of the chip.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>SCRATCH2</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SCRATCH3</name>
+                <addressOffset>0x00000018</addressOffset>
+                <description>Scratch register. Information persists through soft reset of the chip.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>SCRATCH3</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SCRATCH4</name>
+                <addressOffset>0x0000001c</addressOffset>
+                <description>Scratch register. Information persists through soft reset of the chip.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>SCRATCH4</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SCRATCH5</name>
+                <addressOffset>0x00000020</addressOffset>
+                <description>Scratch register. Information persists through soft reset of the chip.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>SCRATCH5</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SCRATCH6</name>
+                <addressOffset>0x00000024</addressOffset>
+                <description>Scratch register. Information persists through soft reset of the chip.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>SCRATCH6</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SCRATCH7</name>
+                <addressOffset>0x00000028</addressOffset>
+                <description>Scratch register. Information persists through soft reset of the chip.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>SCRATCH7</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+        </registers>
+    </peripheral>
+    <peripheral>
+        <name>DMA</name>
+        <description>DMA with separate read and write masters</description>
+        <baseAddress>0x50000000</baseAddress>
+        <addressBlock>
+            <offset>0</offset>
+            <size>3016</size>
+            <usage>registers</usage>
+        </addressBlock>
+        <interrupt>
+            <name>DMA_IRQ_0</name>
+            <value>10</value>
+        </interrupt>
+        <interrupt>
+            <name>DMA_IRQ_1</name>
+            <value>11</value>
+        </interrupt>
+        <interrupt>
+            <name>DMA_IRQ_2</name>
+            <value>12</value>
+        </interrupt>
+        <interrupt>
+            <name>DMA_IRQ_3</name>
+            <value>13</value>
+        </interrupt>
+        <registers>
+            <register>
+                <name>CH0_READ_ADDR</name>
+                <addressOffset>0x00000000</addressOffset>
+                <description>DMA Channel 0 Read Address pointer</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CH0_READ_ADDR</name>
+                        <description>This register updates automatically each time a read completes. The current value is the next address to be read by this channel.</description>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH0_WRITE_ADDR</name>
+                <addressOffset>0x00000004</addressOffset>
+                <description>DMA Channel 0 Write Address pointer</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CH0_WRITE_ADDR</name>
+                        <description>This register updates automatically each time a write completes. The current value is the next address to be written by this channel.</description>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH0_TRANS_COUNT</name>
+                <addressOffset>0x00000008</addressOffset>
+                <description>DMA Channel 0 Transfer Count</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>MODE</name>
+                        <description>When MODE is 0x0, the transfer count decrements with each transfer until 0, and then the channel triggers the next channel indicated by CTRL_CHAIN_TO.
+
+                            When MODE is 0x1, the transfer count decrements with each transfer until 0, and then the channel re-triggers itself, in addition to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an endless ring-buffer DMA with periodic interrupts.
+
+                            When MODE is 0xf, the transfer count does not decrement. The DMA channel performs an endless sequence of transfers, never triggering other channels or raising interrupts, until an ABORT is raised.
+
+                            All other values are reserved.</description>
+                        <bitRange>[31:28]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TRIGGER_SELF</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ENDLESS</name>
+                                <value>15</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>COUNT</name>
+                        <description>28-bit transfer count (256 million transfers maximum).
+
+                            Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).
+
+                            When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.
+
+                            Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.
+
+                            The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD.</description>
+                        <bitRange>[27:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH0_CTRL_TRIG</name>
+                <addressOffset>0x0000000c</addressOffset>
+                <description>DMA Channel 0 Control and Status</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>AHB_ERROR</name>
+                        <description>Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag.</description>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>READ_ERROR</name>
+                        <description>If 1, the channel received a read bus error. Write one to clear. 
+                            READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)</description>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>WRITE_ERROR</name>
+                        <description>If 1, the channel received a write bus error. Write one to clear. 
+                            WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)</description>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>BUSY</name>
+                        <description>This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.
+
+                            To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT.</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SNIFF_EN</name>
+                        <description>If 1, this channel&#39;s data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.
+
+                            This allows checksum to be enabled or disabled on a per-control- block basis.</description>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>BSWAP</name>
+                        <description>Apply byte-swap transformation to DMA data. 
+                            For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.</description>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>IRQ_QUIET</name>
+                        <description>In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.
+
+                            This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.</description>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>TREQ_SEL</name>
+                        <description>Select a Transfer Request signal. 
+                            The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). 
+                            0x0 to 0x3a -&gt; select DREQ n as TREQ</description>
+                        <bitRange>[22:17]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>PIO0_TX0</name>
+                                <value>0</value>
+                                <description>Select PIO0&#39;s TX FIFO 0 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO0_TX1</name>
+                                <value>1</value>
+                                <description>Select PIO0&#39;s TX FIFO 1 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO0_TX2</name>
+                                <value>2</value>
+                                <description>Select PIO0&#39;s TX FIFO 2 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO0_TX3</name>
+                                <value>3</value>
+                                <description>Select PIO0&#39;s TX FIFO 3 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO0_RX0</name>
+                                <value>4</value>
+                                <description>Select PIO0&#39;s RX FIFO 0 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO0_RX1</name>
+                                <value>5</value>
+                                <description>Select PIO0&#39;s RX FIFO 1 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO0_RX2</name>
+                                <value>6</value>
+                                <description>Select PIO0&#39;s RX FIFO 2 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO0_RX3</name>
+                                <value>7</value>
+                                <description>Select PIO0&#39;s RX FIFO 3 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_TX0</name>
+                                <value>8</value>
+                                <description>Select PIO1&#39;s TX FIFO 0 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_TX1</name>
+                                <value>9</value>
+                                <description>Select PIO1&#39;s TX FIFO 1 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_TX2</name>
+                                <value>10</value>
+                                <description>Select PIO1&#39;s TX FIFO 2 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_TX3</name>
+                                <value>11</value>
+                                <description>Select PIO1&#39;s TX FIFO 3 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_RX0</name>
+                                <value>12</value>
+                                <description>Select PIO1&#39;s RX FIFO 0 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_RX1</name>
+                                <value>13</value>
+                                <description>Select PIO1&#39;s RX FIFO 1 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_RX2</name>
+                                <value>14</value>
+                                <description>Select PIO1&#39;s RX FIFO 2 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_RX3</name>
+                                <value>15</value>
+                                <description>Select PIO1&#39;s RX FIFO 3 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO2_TX0</name>
+                                <value>16</value>
+                                <description>Select PIO2&#39;s TX FIFO 0 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO2_TX1</name>
+                                <value>17</value>
+                                <description>Select PIO2&#39;s TX FIFO 1 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO2_TX2</name>
+                                <value>18</value>
+                                <description>Select PIO2&#39;s TX FIFO 2 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO2_TX3</name>
+                                <value>19</value>
+                                <description>Select PIO2&#39;s TX FIFO 3 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO2_RX0</name>
+                                <value>20</value>
+                                <description>Select PIO2&#39;s RX FIFO 0 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO2_RX1</name>
+                                <value>21</value>
+                                <description>Select PIO2&#39;s RX FIFO 1 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO2_RX2</name>
+                                <value>22</value>
+                                <description>Select PIO2&#39;s RX FIFO 2 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO2_RX3</name>
+                                <value>23</value>
+                                <description>Select PIO2&#39;s RX FIFO 3 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SPI0_TX</name>
+                                <value>24</value>
+                                <description>Select SPI0&#39;s TX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SPI0_RX</name>
+                                <value>25</value>
+                                <description>Select SPI0&#39;s RX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SPI1_TX</name>
+                                <value>26</value>
+                                <description>Select SPI1&#39;s TX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SPI1_RX</name>
+                                <value>27</value>
+                                <description>Select SPI1&#39;s RX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UART0_TX</name>
+                                <value>28</value>
+                                <description>Select UART0&#39;s TX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UART0_RX</name>
+                                <value>29</value>
+                                <description>Select UART0&#39;s RX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UART1_TX</name>
+                                <value>30</value>
+                                <description>Select UART1&#39;s TX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UART1_RX</name>
+                                <value>31</value>
+                                <description>Select UART1&#39;s RX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP0</name>
+                                <value>32</value>
+                                <description>Select PWM Counter 0&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP1</name>
+                                <value>33</value>
+                                <description>Select PWM Counter 1&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP2</name>
+                                <value>34</value>
+                                <description>Select PWM Counter 2&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP3</name>
+                                <value>35</value>
+                                <description>Select PWM Counter 3&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP4</name>
+                                <value>36</value>
+                                <description>Select PWM Counter 4&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP5</name>
+                                <value>37</value>
+                                <description>Select PWM Counter 5&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP6</name>
+                                <value>38</value>
+                                <description>Select PWM Counter 6&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP7</name>
+                                <value>39</value>
+                                <description>Select PWM Counter 7&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP8</name>
+                                <value>40</value>
+                                <description>Select PWM Counter 8&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP9</name>
+                                <value>41</value>
+                                <description>Select PWM Counter 9&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP10</name>
+                                <value>42</value>
+                                <description>Select PWM Counter 0&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP11</name>
+                                <value>43</value>
+                                <description>Select PWM Counter 1&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>I2C0_TX</name>
+                                <value>44</value>
+                                <description>Select I2C0&#39;s TX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>I2C0_RX</name>
+                                <value>45</value>
+                                <description>Select I2C0&#39;s RX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>I2C1_TX</name>
+                                <value>46</value>
+                                <description>Select I2C1&#39;s TX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>I2C1_RX</name>
+                                <value>47</value>
+                                <description>Select I2C1&#39;s RX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC</name>
+                                <value>48</value>
+                                <description>Select the ADC as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>XIP_STREAM</name>
+                                <value>49</value>
+                                <description>Select the XIP Streaming FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>XIP_QMITX</name>
+                                <value>50</value>
+                                <description>Select XIP_QMITX as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>XIP_QMIRX</name>
+                                <value>51</value>
+                                <description>Select XIP_QMIRX as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HSTX</name>
+                                <value>52</value>
+                                <description>Select HSTX as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CORESIGHT</name>
+                                <value>53</value>
+                                <description>Select CORESIGHT as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SHA256</name>
+                                <value>54</value>
+                                <description>Select SHA256 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TIMER0</name>
+                                <value>59</value>
+                                <description>Select Timer 0 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TIMER1</name>
+                                <value>60</value>
+                                <description>Select Timer 1 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TIMER2</name>
+                                <value>61</value>
+                                <description>Select Timer 2 as TREQ (Optional)</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TIMER3</name>
+                                <value>62</value>
+                                <description>Select Timer 3 as TREQ (Optional)</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PERMANENT</name>
+                                <value>63</value>
+                                <description>Permanent request, for unpaced transfers.</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>CHAIN_TO</name>
+                        <description>When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.
+
+                            Note this field resets to 0, so channels 1 and above will chain to channel 0 by default. Set this field to avoid this behaviour.</description>
+                        <bitRange>[16:13]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>RING_SEL</name>
+                        <description>Select whether RING_SIZE applies to read or write addresses. 
+                            If 0, read addresses are wrapped on a (1 &lt;&lt; RING_SIZE) boundary. If 1, write addresses are wrapped.</description>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>RING_SIZE</name>
+                        <description>Size of address wrap region. If 0, don&#39;t wrap. For values n &gt; 0, only the lower n bits of the address will change. This wraps the address on a (1 &lt;&lt; n) byte boundary, facilitating access to naturally-aligned ring buffers.
+
+                            Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.</description>
+                        <bitRange>[11:8]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>RING_NONE</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>INCR_WRITE_REV</name>
+                        <description>If 1, and INCR_WRITE is 1, the write address is decremented rather than incremented with each transfer.
+
+                            If 1, and INCR_WRITE is 0, this otherwise-unused combination causes the write address to be incremented by twice the transfer size, i.e. skipping over alternate addresses.</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INCR_WRITE</name>
+                        <description>If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.
+
+                            Generally this should be disabled for memory-to-peripheral transfers.</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INCR_READ_REV</name>
+                        <description>If 1, and INCR_READ is 1, the read address is decremented rather than incremented with each transfer.
+
+                            If 1, and INCR_READ is 0, this otherwise-unused combination causes the read address to be incremented by twice the transfer size, i.e. skipping over alternate addresses.</description>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INCR_READ</name>
+                        <description>If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.
+
+                            Generally this should be disabled for peripheral-to-memory transfers.</description>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DATA_SIZE</name>
+                        <description>Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.</description>
+                        <bitRange>[3:2]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>SIZE_BYTE</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SIZE_HALFWORD</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SIZE_WORD</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>HIGH_PRIORITY</name>
+                        <description>HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.
+
+                            This only affects the order in which the DMA schedules channels. The DMA&#39;s bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>EN</name>
+                        <description>DMA Channel Enable. 
+                            When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH0_AL1_CTRL</name>
+                <addressOffset>0x00000010</addressOffset>
+                <description>Alias for channel 0 CTRL register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH0_AL1_CTRL</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH0_AL1_READ_ADDR</name>
+                <addressOffset>0x00000014</addressOffset>
+                <description>Alias for channel 0 READ_ADDR register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH0_AL1_READ_ADDR</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH0_AL1_WRITE_ADDR</name>
+                <addressOffset>0x00000018</addressOffset>
+                <description>Alias for channel 0 WRITE_ADDR register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH0_AL1_WRITE_ADDR</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH0_AL1_TRANS_COUNT_TRIG</name>
+                <addressOffset>0x0000001c</addressOffset>
+                <description>Alias for channel 0 TRANS_COUNT register 
+                    This is a trigger register (0xc). Writing a nonzero value will 
+                    reload the channel counter and start the channel.</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH0_AL1_TRANS_COUNT_TRIG</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH0_AL2_CTRL</name>
+                <addressOffset>0x00000020</addressOffset>
+                <description>Alias for channel 0 CTRL register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH0_AL2_CTRL</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH0_AL2_TRANS_COUNT</name>
+                <addressOffset>0x00000024</addressOffset>
+                <description>Alias for channel 0 TRANS_COUNT register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH0_AL2_TRANS_COUNT</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH0_AL2_READ_ADDR</name>
+                <addressOffset>0x00000028</addressOffset>
+                <description>Alias for channel 0 READ_ADDR register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH0_AL2_READ_ADDR</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH0_AL2_WRITE_ADDR_TRIG</name>
+                <addressOffset>0x0000002c</addressOffset>
+                <description>Alias for channel 0 WRITE_ADDR register 
+                    This is a trigger register (0xc). Writing a nonzero value will 
+                    reload the channel counter and start the channel.</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH0_AL2_WRITE_ADDR_TRIG</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH0_AL3_CTRL</name>
+                <addressOffset>0x00000030</addressOffset>
+                <description>Alias for channel 0 CTRL register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH0_AL3_CTRL</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH0_AL3_WRITE_ADDR</name>
+                <addressOffset>0x00000034</addressOffset>
+                <description>Alias for channel 0 WRITE_ADDR register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH0_AL3_WRITE_ADDR</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH0_AL3_TRANS_COUNT</name>
+                <addressOffset>0x00000038</addressOffset>
+                <description>Alias for channel 0 TRANS_COUNT register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH0_AL3_TRANS_COUNT</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH0_AL3_READ_ADDR_TRIG</name>
+                <addressOffset>0x0000003c</addressOffset>
+                <description>Alias for channel 0 READ_ADDR register 
+                    This is a trigger register (0xc). Writing a nonzero value will 
+                    reload the channel counter and start the channel.</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH0_AL3_READ_ADDR_TRIG</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH1_READ_ADDR</name>
+                <addressOffset>0x00000040</addressOffset>
+                <description>DMA Channel 1 Read Address pointer</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CH1_READ_ADDR</name>
+                        <description>This register updates automatically each time a read completes. The current value is the next address to be read by this channel.</description>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH1_WRITE_ADDR</name>
+                <addressOffset>0x00000044</addressOffset>
+                <description>DMA Channel 1 Write Address pointer</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CH1_WRITE_ADDR</name>
+                        <description>This register updates automatically each time a write completes. The current value is the next address to be written by this channel.</description>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH1_TRANS_COUNT</name>
+                <addressOffset>0x00000048</addressOffset>
+                <description>DMA Channel 1 Transfer Count</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>MODE</name>
+                        <description>When MODE is 0x0, the transfer count decrements with each transfer until 0, and then the channel triggers the next channel indicated by CTRL_CHAIN_TO.
+
+                            When MODE is 0x1, the transfer count decrements with each transfer until 0, and then the channel re-triggers itself, in addition to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an endless ring-buffer DMA with periodic interrupts.
+
+                            When MODE is 0xf, the transfer count does not decrement. The DMA channel performs an endless sequence of transfers, never triggering other channels or raising interrupts, until an ABORT is raised.
+
+                            All other values are reserved.</description>
+                        <bitRange>[31:28]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TRIGGER_SELF</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ENDLESS</name>
+                                <value>15</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>COUNT</name>
+                        <description>28-bit transfer count (256 million transfers maximum).
+
+                            Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).
+
+                            When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.
+
+                            Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.
+
+                            The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD.</description>
+                        <bitRange>[27:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH1_CTRL_TRIG</name>
+                <addressOffset>0x0000004c</addressOffset>
+                <description>DMA Channel 1 Control and Status</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>AHB_ERROR</name>
+                        <description>Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag.</description>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>READ_ERROR</name>
+                        <description>If 1, the channel received a read bus error. Write one to clear. 
+                            READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)</description>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>WRITE_ERROR</name>
+                        <description>If 1, the channel received a write bus error. Write one to clear. 
+                            WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)</description>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>BUSY</name>
+                        <description>This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.
+
+                            To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT.</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SNIFF_EN</name>
+                        <description>If 1, this channel&#39;s data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.
+
+                            This allows checksum to be enabled or disabled on a per-control- block basis.</description>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>BSWAP</name>
+                        <description>Apply byte-swap transformation to DMA data. 
+                            For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.</description>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>IRQ_QUIET</name>
+                        <description>In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.
+
+                            This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.</description>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>TREQ_SEL</name>
+                        <description>Select a Transfer Request signal. 
+                            The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). 
+                            0x0 to 0x3a -&gt; select DREQ n as TREQ</description>
+                        <bitRange>[22:17]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>PIO0_TX0</name>
+                                <value>0</value>
+                                <description>Select PIO0&#39;s TX FIFO 0 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO0_TX1</name>
+                                <value>1</value>
+                                <description>Select PIO0&#39;s TX FIFO 1 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO0_TX2</name>
+                                <value>2</value>
+                                <description>Select PIO0&#39;s TX FIFO 2 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO0_TX3</name>
+                                <value>3</value>
+                                <description>Select PIO0&#39;s TX FIFO 3 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO0_RX0</name>
+                                <value>4</value>
+                                <description>Select PIO0&#39;s RX FIFO 0 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO0_RX1</name>
+                                <value>5</value>
+                                <description>Select PIO0&#39;s RX FIFO 1 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO0_RX2</name>
+                                <value>6</value>
+                                <description>Select PIO0&#39;s RX FIFO 2 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO0_RX3</name>
+                                <value>7</value>
+                                <description>Select PIO0&#39;s RX FIFO 3 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_TX0</name>
+                                <value>8</value>
+                                <description>Select PIO1&#39;s TX FIFO 0 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_TX1</name>
+                                <value>9</value>
+                                <description>Select PIO1&#39;s TX FIFO 1 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_TX2</name>
+                                <value>10</value>
+                                <description>Select PIO1&#39;s TX FIFO 2 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_TX3</name>
+                                <value>11</value>
+                                <description>Select PIO1&#39;s TX FIFO 3 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_RX0</name>
+                                <value>12</value>
+                                <description>Select PIO1&#39;s RX FIFO 0 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_RX1</name>
+                                <value>13</value>
+                                <description>Select PIO1&#39;s RX FIFO 1 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_RX2</name>
+                                <value>14</value>
+                                <description>Select PIO1&#39;s RX FIFO 2 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_RX3</name>
+                                <value>15</value>
+                                <description>Select PIO1&#39;s RX FIFO 3 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO2_TX0</name>
+                                <value>16</value>
+                                <description>Select PIO2&#39;s TX FIFO 0 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO2_TX1</name>
+                                <value>17</value>
+                                <description>Select PIO2&#39;s TX FIFO 1 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO2_TX2</name>
+                                <value>18</value>
+                                <description>Select PIO2&#39;s TX FIFO 2 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO2_TX3</name>
+                                <value>19</value>
+                                <description>Select PIO2&#39;s TX FIFO 3 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO2_RX0</name>
+                                <value>20</value>
+                                <description>Select PIO2&#39;s RX FIFO 0 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO2_RX1</name>
+                                <value>21</value>
+                                <description>Select PIO2&#39;s RX FIFO 1 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO2_RX2</name>
+                                <value>22</value>
+                                <description>Select PIO2&#39;s RX FIFO 2 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO2_RX3</name>
+                                <value>23</value>
+                                <description>Select PIO2&#39;s RX FIFO 3 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SPI0_TX</name>
+                                <value>24</value>
+                                <description>Select SPI0&#39;s TX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SPI0_RX</name>
+                                <value>25</value>
+                                <description>Select SPI0&#39;s RX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SPI1_TX</name>
+                                <value>26</value>
+                                <description>Select SPI1&#39;s TX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SPI1_RX</name>
+                                <value>27</value>
+                                <description>Select SPI1&#39;s RX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UART0_TX</name>
+                                <value>28</value>
+                                <description>Select UART0&#39;s TX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UART0_RX</name>
+                                <value>29</value>
+                                <description>Select UART0&#39;s RX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UART1_TX</name>
+                                <value>30</value>
+                                <description>Select UART1&#39;s TX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UART1_RX</name>
+                                <value>31</value>
+                                <description>Select UART1&#39;s RX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP0</name>
+                                <value>32</value>
+                                <description>Select PWM Counter 0&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP1</name>
+                                <value>33</value>
+                                <description>Select PWM Counter 1&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP2</name>
+                                <value>34</value>
+                                <description>Select PWM Counter 2&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP3</name>
+                                <value>35</value>
+                                <description>Select PWM Counter 3&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP4</name>
+                                <value>36</value>
+                                <description>Select PWM Counter 4&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP5</name>
+                                <value>37</value>
+                                <description>Select PWM Counter 5&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP6</name>
+                                <value>38</value>
+                                <description>Select PWM Counter 6&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP7</name>
+                                <value>39</value>
+                                <description>Select PWM Counter 7&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP8</name>
+                                <value>40</value>
+                                <description>Select PWM Counter 8&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP9</name>
+                                <value>41</value>
+                                <description>Select PWM Counter 9&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP10</name>
+                                <value>42</value>
+                                <description>Select PWM Counter 0&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP11</name>
+                                <value>43</value>
+                                <description>Select PWM Counter 1&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>I2C0_TX</name>
+                                <value>44</value>
+                                <description>Select I2C0&#39;s TX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>I2C0_RX</name>
+                                <value>45</value>
+                                <description>Select I2C0&#39;s RX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>I2C1_TX</name>
+                                <value>46</value>
+                                <description>Select I2C1&#39;s TX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>I2C1_RX</name>
+                                <value>47</value>
+                                <description>Select I2C1&#39;s RX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC</name>
+                                <value>48</value>
+                                <description>Select the ADC as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>XIP_STREAM</name>
+                                <value>49</value>
+                                <description>Select the XIP Streaming FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>XIP_QMITX</name>
+                                <value>50</value>
+                                <description>Select XIP_QMITX as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>XIP_QMIRX</name>
+                                <value>51</value>
+                                <description>Select XIP_QMIRX as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HSTX</name>
+                                <value>52</value>
+                                <description>Select HSTX as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CORESIGHT</name>
+                                <value>53</value>
+                                <description>Select CORESIGHT as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SHA256</name>
+                                <value>54</value>
+                                <description>Select SHA256 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TIMER0</name>
+                                <value>59</value>
+                                <description>Select Timer 0 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TIMER1</name>
+                                <value>60</value>
+                                <description>Select Timer 1 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TIMER2</name>
+                                <value>61</value>
+                                <description>Select Timer 2 as TREQ (Optional)</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TIMER3</name>
+                                <value>62</value>
+                                <description>Select Timer 3 as TREQ (Optional)</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PERMANENT</name>
+                                <value>63</value>
+                                <description>Permanent request, for unpaced transfers.</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>CHAIN_TO</name>
+                        <description>When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.
+
+                            Note this field resets to 0, so channels 1 and above will chain to channel 0 by default. Set this field to avoid this behaviour.</description>
+                        <bitRange>[16:13]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>RING_SEL</name>
+                        <description>Select whether RING_SIZE applies to read or write addresses. 
+                            If 0, read addresses are wrapped on a (1 &lt;&lt; RING_SIZE) boundary. If 1, write addresses are wrapped.</description>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>RING_SIZE</name>
+                        <description>Size of address wrap region. If 0, don&#39;t wrap. For values n &gt; 0, only the lower n bits of the address will change. This wraps the address on a (1 &lt;&lt; n) byte boundary, facilitating access to naturally-aligned ring buffers.
+
+                            Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.</description>
+                        <bitRange>[11:8]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>RING_NONE</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>INCR_WRITE_REV</name>
+                        <description>If 1, and INCR_WRITE is 1, the write address is decremented rather than incremented with each transfer.
+
+                            If 1, and INCR_WRITE is 0, this otherwise-unused combination causes the write address to be incremented by twice the transfer size, i.e. skipping over alternate addresses.</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INCR_WRITE</name>
+                        <description>If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.
+
+                            Generally this should be disabled for memory-to-peripheral transfers.</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INCR_READ_REV</name>
+                        <description>If 1, and INCR_READ is 1, the read address is decremented rather than incremented with each transfer.
+
+                            If 1, and INCR_READ is 0, this otherwise-unused combination causes the read address to be incremented by twice the transfer size, i.e. skipping over alternate addresses.</description>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INCR_READ</name>
+                        <description>If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.
+
+                            Generally this should be disabled for peripheral-to-memory transfers.</description>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DATA_SIZE</name>
+                        <description>Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.</description>
+                        <bitRange>[3:2]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>SIZE_BYTE</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SIZE_HALFWORD</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SIZE_WORD</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>HIGH_PRIORITY</name>
+                        <description>HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.
+
+                            This only affects the order in which the DMA schedules channels. The DMA&#39;s bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>EN</name>
+                        <description>DMA Channel Enable. 
+                            When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH1_AL1_CTRL</name>
+                <addressOffset>0x00000050</addressOffset>
+                <description>Alias for channel 1 CTRL register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH1_AL1_CTRL</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH1_AL1_READ_ADDR</name>
+                <addressOffset>0x00000054</addressOffset>
+                <description>Alias for channel 1 READ_ADDR register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH1_AL1_READ_ADDR</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH1_AL1_WRITE_ADDR</name>
+                <addressOffset>0x00000058</addressOffset>
+                <description>Alias for channel 1 WRITE_ADDR register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH1_AL1_WRITE_ADDR</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH1_AL1_TRANS_COUNT_TRIG</name>
+                <addressOffset>0x0000005c</addressOffset>
+                <description>Alias for channel 1 TRANS_COUNT register 
+                    This is a trigger register (0xc). Writing a nonzero value will 
+                    reload the channel counter and start the channel.</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH1_AL1_TRANS_COUNT_TRIG</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH1_AL2_CTRL</name>
+                <addressOffset>0x00000060</addressOffset>
+                <description>Alias for channel 1 CTRL register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH1_AL2_CTRL</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH1_AL2_TRANS_COUNT</name>
+                <addressOffset>0x00000064</addressOffset>
+                <description>Alias for channel 1 TRANS_COUNT register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH1_AL2_TRANS_COUNT</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH1_AL2_READ_ADDR</name>
+                <addressOffset>0x00000068</addressOffset>
+                <description>Alias for channel 1 READ_ADDR register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH1_AL2_READ_ADDR</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH1_AL2_WRITE_ADDR_TRIG</name>
+                <addressOffset>0x0000006c</addressOffset>
+                <description>Alias for channel 1 WRITE_ADDR register 
+                    This is a trigger register (0xc). Writing a nonzero value will 
+                    reload the channel counter and start the channel.</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH1_AL2_WRITE_ADDR_TRIG</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH1_AL3_CTRL</name>
+                <addressOffset>0x00000070</addressOffset>
+                <description>Alias for channel 1 CTRL register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH1_AL3_CTRL</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH1_AL3_WRITE_ADDR</name>
+                <addressOffset>0x00000074</addressOffset>
+                <description>Alias for channel 1 WRITE_ADDR register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH1_AL3_WRITE_ADDR</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH1_AL3_TRANS_COUNT</name>
+                <addressOffset>0x00000078</addressOffset>
+                <description>Alias for channel 1 TRANS_COUNT register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH1_AL3_TRANS_COUNT</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH1_AL3_READ_ADDR_TRIG</name>
+                <addressOffset>0x0000007c</addressOffset>
+                <description>Alias for channel 1 READ_ADDR register 
+                    This is a trigger register (0xc). Writing a nonzero value will 
+                    reload the channel counter and start the channel.</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH1_AL3_READ_ADDR_TRIG</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH2_READ_ADDR</name>
+                <addressOffset>0x00000080</addressOffset>
+                <description>DMA Channel 2 Read Address pointer</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CH2_READ_ADDR</name>
+                        <description>This register updates automatically each time a read completes. The current value is the next address to be read by this channel.</description>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH2_WRITE_ADDR</name>
+                <addressOffset>0x00000084</addressOffset>
+                <description>DMA Channel 2 Write Address pointer</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CH2_WRITE_ADDR</name>
+                        <description>This register updates automatically each time a write completes. The current value is the next address to be written by this channel.</description>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH2_TRANS_COUNT</name>
+                <addressOffset>0x00000088</addressOffset>
+                <description>DMA Channel 2 Transfer Count</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>MODE</name>
+                        <description>When MODE is 0x0, the transfer count decrements with each transfer until 0, and then the channel triggers the next channel indicated by CTRL_CHAIN_TO.
+
+                            When MODE is 0x1, the transfer count decrements with each transfer until 0, and then the channel re-triggers itself, in addition to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an endless ring-buffer DMA with periodic interrupts.
+
+                            When MODE is 0xf, the transfer count does not decrement. The DMA channel performs an endless sequence of transfers, never triggering other channels or raising interrupts, until an ABORT is raised.
+
+                            All other values are reserved.</description>
+                        <bitRange>[31:28]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TRIGGER_SELF</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ENDLESS</name>
+                                <value>15</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>COUNT</name>
+                        <description>28-bit transfer count (256 million transfers maximum).
+
+                            Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).
+
+                            When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.
+
+                            Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.
+
+                            The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD.</description>
+                        <bitRange>[27:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH2_CTRL_TRIG</name>
+                <addressOffset>0x0000008c</addressOffset>
+                <description>DMA Channel 2 Control and Status</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>AHB_ERROR</name>
+                        <description>Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag.</description>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>READ_ERROR</name>
+                        <description>If 1, the channel received a read bus error. Write one to clear. 
+                            READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)</description>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>WRITE_ERROR</name>
+                        <description>If 1, the channel received a write bus error. Write one to clear. 
+                            WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)</description>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>BUSY</name>
+                        <description>This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.
+
+                            To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT.</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SNIFF_EN</name>
+                        <description>If 1, this channel&#39;s data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.
+
+                            This allows checksum to be enabled or disabled on a per-control- block basis.</description>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>BSWAP</name>
+                        <description>Apply byte-swap transformation to DMA data. 
+                            For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.</description>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>IRQ_QUIET</name>
+                        <description>In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.
+
+                            This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.</description>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>TREQ_SEL</name>
+                        <description>Select a Transfer Request signal. 
+                            The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). 
+                            0x0 to 0x3a -&gt; select DREQ n as TREQ</description>
+                        <bitRange>[22:17]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>PIO0_TX0</name>
+                                <value>0</value>
+                                <description>Select PIO0&#39;s TX FIFO 0 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO0_TX1</name>
+                                <value>1</value>
+                                <description>Select PIO0&#39;s TX FIFO 1 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO0_TX2</name>
+                                <value>2</value>
+                                <description>Select PIO0&#39;s TX FIFO 2 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO0_TX3</name>
+                                <value>3</value>
+                                <description>Select PIO0&#39;s TX FIFO 3 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO0_RX0</name>
+                                <value>4</value>
+                                <description>Select PIO0&#39;s RX FIFO 0 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO0_RX1</name>
+                                <value>5</value>
+                                <description>Select PIO0&#39;s RX FIFO 1 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO0_RX2</name>
+                                <value>6</value>
+                                <description>Select PIO0&#39;s RX FIFO 2 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO0_RX3</name>
+                                <value>7</value>
+                                <description>Select PIO0&#39;s RX FIFO 3 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_TX0</name>
+                                <value>8</value>
+                                <description>Select PIO1&#39;s TX FIFO 0 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_TX1</name>
+                                <value>9</value>
+                                <description>Select PIO1&#39;s TX FIFO 1 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_TX2</name>
+                                <value>10</value>
+                                <description>Select PIO1&#39;s TX FIFO 2 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_TX3</name>
+                                <value>11</value>
+                                <description>Select PIO1&#39;s TX FIFO 3 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_RX0</name>
+                                <value>12</value>
+                                <description>Select PIO1&#39;s RX FIFO 0 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_RX1</name>
+                                <value>13</value>
+                                <description>Select PIO1&#39;s RX FIFO 1 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_RX2</name>
+                                <value>14</value>
+                                <description>Select PIO1&#39;s RX FIFO 2 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_RX3</name>
+                                <value>15</value>
+                                <description>Select PIO1&#39;s RX FIFO 3 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO2_TX0</name>
+                                <value>16</value>
+                                <description>Select PIO2&#39;s TX FIFO 0 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO2_TX1</name>
+                                <value>17</value>
+                                <description>Select PIO2&#39;s TX FIFO 1 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO2_TX2</name>
+                                <value>18</value>
+                                <description>Select PIO2&#39;s TX FIFO 2 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO2_TX3</name>
+                                <value>19</value>
+                                <description>Select PIO2&#39;s TX FIFO 3 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO2_RX0</name>
+                                <value>20</value>
+                                <description>Select PIO2&#39;s RX FIFO 0 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO2_RX1</name>
+                                <value>21</value>
+                                <description>Select PIO2&#39;s RX FIFO 1 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO2_RX2</name>
+                                <value>22</value>
+                                <description>Select PIO2&#39;s RX FIFO 2 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO2_RX3</name>
+                                <value>23</value>
+                                <description>Select PIO2&#39;s RX FIFO 3 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SPI0_TX</name>
+                                <value>24</value>
+                                <description>Select SPI0&#39;s TX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SPI0_RX</name>
+                                <value>25</value>
+                                <description>Select SPI0&#39;s RX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SPI1_TX</name>
+                                <value>26</value>
+                                <description>Select SPI1&#39;s TX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SPI1_RX</name>
+                                <value>27</value>
+                                <description>Select SPI1&#39;s RX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UART0_TX</name>
+                                <value>28</value>
+                                <description>Select UART0&#39;s TX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UART0_RX</name>
+                                <value>29</value>
+                                <description>Select UART0&#39;s RX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UART1_TX</name>
+                                <value>30</value>
+                                <description>Select UART1&#39;s TX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UART1_RX</name>
+                                <value>31</value>
+                                <description>Select UART1&#39;s RX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP0</name>
+                                <value>32</value>
+                                <description>Select PWM Counter 0&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP1</name>
+                                <value>33</value>
+                                <description>Select PWM Counter 1&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP2</name>
+                                <value>34</value>
+                                <description>Select PWM Counter 2&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP3</name>
+                                <value>35</value>
+                                <description>Select PWM Counter 3&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP4</name>
+                                <value>36</value>
+                                <description>Select PWM Counter 4&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP5</name>
+                                <value>37</value>
+                                <description>Select PWM Counter 5&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP6</name>
+                                <value>38</value>
+                                <description>Select PWM Counter 6&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP7</name>
+                                <value>39</value>
+                                <description>Select PWM Counter 7&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP8</name>
+                                <value>40</value>
+                                <description>Select PWM Counter 8&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP9</name>
+                                <value>41</value>
+                                <description>Select PWM Counter 9&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP10</name>
+                                <value>42</value>
+                                <description>Select PWM Counter 0&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP11</name>
+                                <value>43</value>
+                                <description>Select PWM Counter 1&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>I2C0_TX</name>
+                                <value>44</value>
+                                <description>Select I2C0&#39;s TX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>I2C0_RX</name>
+                                <value>45</value>
+                                <description>Select I2C0&#39;s RX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>I2C1_TX</name>
+                                <value>46</value>
+                                <description>Select I2C1&#39;s TX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>I2C1_RX</name>
+                                <value>47</value>
+                                <description>Select I2C1&#39;s RX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC</name>
+                                <value>48</value>
+                                <description>Select the ADC as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>XIP_STREAM</name>
+                                <value>49</value>
+                                <description>Select the XIP Streaming FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>XIP_QMITX</name>
+                                <value>50</value>
+                                <description>Select XIP_QMITX as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>XIP_QMIRX</name>
+                                <value>51</value>
+                                <description>Select XIP_QMIRX as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HSTX</name>
+                                <value>52</value>
+                                <description>Select HSTX as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CORESIGHT</name>
+                                <value>53</value>
+                                <description>Select CORESIGHT as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SHA256</name>
+                                <value>54</value>
+                                <description>Select SHA256 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TIMER0</name>
+                                <value>59</value>
+                                <description>Select Timer 0 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TIMER1</name>
+                                <value>60</value>
+                                <description>Select Timer 1 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TIMER2</name>
+                                <value>61</value>
+                                <description>Select Timer 2 as TREQ (Optional)</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TIMER3</name>
+                                <value>62</value>
+                                <description>Select Timer 3 as TREQ (Optional)</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PERMANENT</name>
+                                <value>63</value>
+                                <description>Permanent request, for unpaced transfers.</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>CHAIN_TO</name>
+                        <description>When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.
+
+                            Note this field resets to 0, so channels 1 and above will chain to channel 0 by default. Set this field to avoid this behaviour.</description>
+                        <bitRange>[16:13]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>RING_SEL</name>
+                        <description>Select whether RING_SIZE applies to read or write addresses. 
+                            If 0, read addresses are wrapped on a (1 &lt;&lt; RING_SIZE) boundary. If 1, write addresses are wrapped.</description>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>RING_SIZE</name>
+                        <description>Size of address wrap region. If 0, don&#39;t wrap. For values n &gt; 0, only the lower n bits of the address will change. This wraps the address on a (1 &lt;&lt; n) byte boundary, facilitating access to naturally-aligned ring buffers.
+
+                            Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.</description>
+                        <bitRange>[11:8]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>RING_NONE</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>INCR_WRITE_REV</name>
+                        <description>If 1, and INCR_WRITE is 1, the write address is decremented rather than incremented with each transfer.
+
+                            If 1, and INCR_WRITE is 0, this otherwise-unused combination causes the write address to be incremented by twice the transfer size, i.e. skipping over alternate addresses.</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INCR_WRITE</name>
+                        <description>If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.
+
+                            Generally this should be disabled for memory-to-peripheral transfers.</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INCR_READ_REV</name>
+                        <description>If 1, and INCR_READ is 1, the read address is decremented rather than incremented with each transfer.
+
+                            If 1, and INCR_READ is 0, this otherwise-unused combination causes the read address to be incremented by twice the transfer size, i.e. skipping over alternate addresses.</description>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INCR_READ</name>
+                        <description>If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.
+
+                            Generally this should be disabled for peripheral-to-memory transfers.</description>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DATA_SIZE</name>
+                        <description>Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.</description>
+                        <bitRange>[3:2]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>SIZE_BYTE</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SIZE_HALFWORD</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SIZE_WORD</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>HIGH_PRIORITY</name>
+                        <description>HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.
+
+                            This only affects the order in which the DMA schedules channels. The DMA&#39;s bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>EN</name>
+                        <description>DMA Channel Enable. 
+                            When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH2_AL1_CTRL</name>
+                <addressOffset>0x00000090</addressOffset>
+                <description>Alias for channel 2 CTRL register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH2_AL1_CTRL</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH2_AL1_READ_ADDR</name>
+                <addressOffset>0x00000094</addressOffset>
+                <description>Alias for channel 2 READ_ADDR register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH2_AL1_READ_ADDR</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH2_AL1_WRITE_ADDR</name>
+                <addressOffset>0x00000098</addressOffset>
+                <description>Alias for channel 2 WRITE_ADDR register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH2_AL1_WRITE_ADDR</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH2_AL1_TRANS_COUNT_TRIG</name>
+                <addressOffset>0x0000009c</addressOffset>
+                <description>Alias for channel 2 TRANS_COUNT register 
+                    This is a trigger register (0xc). Writing a nonzero value will 
+                    reload the channel counter and start the channel.</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH2_AL1_TRANS_COUNT_TRIG</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH2_AL2_CTRL</name>
+                <addressOffset>0x000000a0</addressOffset>
+                <description>Alias for channel 2 CTRL register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH2_AL2_CTRL</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH2_AL2_TRANS_COUNT</name>
+                <addressOffset>0x000000a4</addressOffset>
+                <description>Alias for channel 2 TRANS_COUNT register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH2_AL2_TRANS_COUNT</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH2_AL2_READ_ADDR</name>
+                <addressOffset>0x000000a8</addressOffset>
+                <description>Alias for channel 2 READ_ADDR register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH2_AL2_READ_ADDR</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH2_AL2_WRITE_ADDR_TRIG</name>
+                <addressOffset>0x000000ac</addressOffset>
+                <description>Alias for channel 2 WRITE_ADDR register 
+                    This is a trigger register (0xc). Writing a nonzero value will 
+                    reload the channel counter and start the channel.</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH2_AL2_WRITE_ADDR_TRIG</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH2_AL3_CTRL</name>
+                <addressOffset>0x000000b0</addressOffset>
+                <description>Alias for channel 2 CTRL register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH2_AL3_CTRL</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH2_AL3_WRITE_ADDR</name>
+                <addressOffset>0x000000b4</addressOffset>
+                <description>Alias for channel 2 WRITE_ADDR register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH2_AL3_WRITE_ADDR</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH2_AL3_TRANS_COUNT</name>
+                <addressOffset>0x000000b8</addressOffset>
+                <description>Alias for channel 2 TRANS_COUNT register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH2_AL3_TRANS_COUNT</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH2_AL3_READ_ADDR_TRIG</name>
+                <addressOffset>0x000000bc</addressOffset>
+                <description>Alias for channel 2 READ_ADDR register 
+                    This is a trigger register (0xc). Writing a nonzero value will 
+                    reload the channel counter and start the channel.</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH2_AL3_READ_ADDR_TRIG</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH3_READ_ADDR</name>
+                <addressOffset>0x000000c0</addressOffset>
+                <description>DMA Channel 3 Read Address pointer</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CH3_READ_ADDR</name>
+                        <description>This register updates automatically each time a read completes. The current value is the next address to be read by this channel.</description>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH3_WRITE_ADDR</name>
+                <addressOffset>0x000000c4</addressOffset>
+                <description>DMA Channel 3 Write Address pointer</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CH3_WRITE_ADDR</name>
+                        <description>This register updates automatically each time a write completes. The current value is the next address to be written by this channel.</description>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH3_TRANS_COUNT</name>
+                <addressOffset>0x000000c8</addressOffset>
+                <description>DMA Channel 3 Transfer Count</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>MODE</name>
+                        <description>When MODE is 0x0, the transfer count decrements with each transfer until 0, and then the channel triggers the next channel indicated by CTRL_CHAIN_TO.
+
+                            When MODE is 0x1, the transfer count decrements with each transfer until 0, and then the channel re-triggers itself, in addition to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an endless ring-buffer DMA with periodic interrupts.
+
+                            When MODE is 0xf, the transfer count does not decrement. The DMA channel performs an endless sequence of transfers, never triggering other channels or raising interrupts, until an ABORT is raised.
+
+                            All other values are reserved.</description>
+                        <bitRange>[31:28]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TRIGGER_SELF</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ENDLESS</name>
+                                <value>15</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>COUNT</name>
+                        <description>28-bit transfer count (256 million transfers maximum).
+
+                            Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).
+
+                            When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.
+
+                            Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.
+
+                            The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD.</description>
+                        <bitRange>[27:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH3_CTRL_TRIG</name>
+                <addressOffset>0x000000cc</addressOffset>
+                <description>DMA Channel 3 Control and Status</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>AHB_ERROR</name>
+                        <description>Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag.</description>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>READ_ERROR</name>
+                        <description>If 1, the channel received a read bus error. Write one to clear. 
+                            READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)</description>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>WRITE_ERROR</name>
+                        <description>If 1, the channel received a write bus error. Write one to clear. 
+                            WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)</description>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>BUSY</name>
+                        <description>This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.
+
+                            To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT.</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SNIFF_EN</name>
+                        <description>If 1, this channel&#39;s data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.
+
+                            This allows checksum to be enabled or disabled on a per-control- block basis.</description>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>BSWAP</name>
+                        <description>Apply byte-swap transformation to DMA data. 
+                            For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.</description>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>IRQ_QUIET</name>
+                        <description>In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.
+
+                            This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.</description>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>TREQ_SEL</name>
+                        <description>Select a Transfer Request signal. 
+                            The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). 
+                            0x0 to 0x3a -&gt; select DREQ n as TREQ</description>
+                        <bitRange>[22:17]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>PIO0_TX0</name>
+                                <value>0</value>
+                                <description>Select PIO0&#39;s TX FIFO 0 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO0_TX1</name>
+                                <value>1</value>
+                                <description>Select PIO0&#39;s TX FIFO 1 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO0_TX2</name>
+                                <value>2</value>
+                                <description>Select PIO0&#39;s TX FIFO 2 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO0_TX3</name>
+                                <value>3</value>
+                                <description>Select PIO0&#39;s TX FIFO 3 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO0_RX0</name>
+                                <value>4</value>
+                                <description>Select PIO0&#39;s RX FIFO 0 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO0_RX1</name>
+                                <value>5</value>
+                                <description>Select PIO0&#39;s RX FIFO 1 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO0_RX2</name>
+                                <value>6</value>
+                                <description>Select PIO0&#39;s RX FIFO 2 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO0_RX3</name>
+                                <value>7</value>
+                                <description>Select PIO0&#39;s RX FIFO 3 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_TX0</name>
+                                <value>8</value>
+                                <description>Select PIO1&#39;s TX FIFO 0 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_TX1</name>
+                                <value>9</value>
+                                <description>Select PIO1&#39;s TX FIFO 1 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_TX2</name>
+                                <value>10</value>
+                                <description>Select PIO1&#39;s TX FIFO 2 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_TX3</name>
+                                <value>11</value>
+                                <description>Select PIO1&#39;s TX FIFO 3 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_RX0</name>
+                                <value>12</value>
+                                <description>Select PIO1&#39;s RX FIFO 0 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_RX1</name>
+                                <value>13</value>
+                                <description>Select PIO1&#39;s RX FIFO 1 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_RX2</name>
+                                <value>14</value>
+                                <description>Select PIO1&#39;s RX FIFO 2 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_RX3</name>
+                                <value>15</value>
+                                <description>Select PIO1&#39;s RX FIFO 3 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO2_TX0</name>
+                                <value>16</value>
+                                <description>Select PIO2&#39;s TX FIFO 0 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO2_TX1</name>
+                                <value>17</value>
+                                <description>Select PIO2&#39;s TX FIFO 1 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO2_TX2</name>
+                                <value>18</value>
+                                <description>Select PIO2&#39;s TX FIFO 2 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO2_TX3</name>
+                                <value>19</value>
+                                <description>Select PIO2&#39;s TX FIFO 3 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO2_RX0</name>
+                                <value>20</value>
+                                <description>Select PIO2&#39;s RX FIFO 0 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO2_RX1</name>
+                                <value>21</value>
+                                <description>Select PIO2&#39;s RX FIFO 1 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO2_RX2</name>
+                                <value>22</value>
+                                <description>Select PIO2&#39;s RX FIFO 2 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO2_RX3</name>
+                                <value>23</value>
+                                <description>Select PIO2&#39;s RX FIFO 3 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SPI0_TX</name>
+                                <value>24</value>
+                                <description>Select SPI0&#39;s TX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SPI0_RX</name>
+                                <value>25</value>
+                                <description>Select SPI0&#39;s RX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SPI1_TX</name>
+                                <value>26</value>
+                                <description>Select SPI1&#39;s TX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SPI1_RX</name>
+                                <value>27</value>
+                                <description>Select SPI1&#39;s RX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UART0_TX</name>
+                                <value>28</value>
+                                <description>Select UART0&#39;s TX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UART0_RX</name>
+                                <value>29</value>
+                                <description>Select UART0&#39;s RX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UART1_TX</name>
+                                <value>30</value>
+                                <description>Select UART1&#39;s TX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UART1_RX</name>
+                                <value>31</value>
+                                <description>Select UART1&#39;s RX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP0</name>
+                                <value>32</value>
+                                <description>Select PWM Counter 0&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP1</name>
+                                <value>33</value>
+                                <description>Select PWM Counter 1&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP2</name>
+                                <value>34</value>
+                                <description>Select PWM Counter 2&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP3</name>
+                                <value>35</value>
+                                <description>Select PWM Counter 3&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP4</name>
+                                <value>36</value>
+                                <description>Select PWM Counter 4&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP5</name>
+                                <value>37</value>
+                                <description>Select PWM Counter 5&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP6</name>
+                                <value>38</value>
+                                <description>Select PWM Counter 6&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP7</name>
+                                <value>39</value>
+                                <description>Select PWM Counter 7&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP8</name>
+                                <value>40</value>
+                                <description>Select PWM Counter 8&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP9</name>
+                                <value>41</value>
+                                <description>Select PWM Counter 9&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP10</name>
+                                <value>42</value>
+                                <description>Select PWM Counter 0&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP11</name>
+                                <value>43</value>
+                                <description>Select PWM Counter 1&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>I2C0_TX</name>
+                                <value>44</value>
+                                <description>Select I2C0&#39;s TX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>I2C0_RX</name>
+                                <value>45</value>
+                                <description>Select I2C0&#39;s RX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>I2C1_TX</name>
+                                <value>46</value>
+                                <description>Select I2C1&#39;s TX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>I2C1_RX</name>
+                                <value>47</value>
+                                <description>Select I2C1&#39;s RX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC</name>
+                                <value>48</value>
+                                <description>Select the ADC as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>XIP_STREAM</name>
+                                <value>49</value>
+                                <description>Select the XIP Streaming FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>XIP_QMITX</name>
+                                <value>50</value>
+                                <description>Select XIP_QMITX as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>XIP_QMIRX</name>
+                                <value>51</value>
+                                <description>Select XIP_QMIRX as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HSTX</name>
+                                <value>52</value>
+                                <description>Select HSTX as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CORESIGHT</name>
+                                <value>53</value>
+                                <description>Select CORESIGHT as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SHA256</name>
+                                <value>54</value>
+                                <description>Select SHA256 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TIMER0</name>
+                                <value>59</value>
+                                <description>Select Timer 0 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TIMER1</name>
+                                <value>60</value>
+                                <description>Select Timer 1 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TIMER2</name>
+                                <value>61</value>
+                                <description>Select Timer 2 as TREQ (Optional)</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TIMER3</name>
+                                <value>62</value>
+                                <description>Select Timer 3 as TREQ (Optional)</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PERMANENT</name>
+                                <value>63</value>
+                                <description>Permanent request, for unpaced transfers.</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>CHAIN_TO</name>
+                        <description>When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.
+
+                            Note this field resets to 0, so channels 1 and above will chain to channel 0 by default. Set this field to avoid this behaviour.</description>
+                        <bitRange>[16:13]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>RING_SEL</name>
+                        <description>Select whether RING_SIZE applies to read or write addresses. 
+                            If 0, read addresses are wrapped on a (1 &lt;&lt; RING_SIZE) boundary. If 1, write addresses are wrapped.</description>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>RING_SIZE</name>
+                        <description>Size of address wrap region. If 0, don&#39;t wrap. For values n &gt; 0, only the lower n bits of the address will change. This wraps the address on a (1 &lt;&lt; n) byte boundary, facilitating access to naturally-aligned ring buffers.
+
+                            Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.</description>
+                        <bitRange>[11:8]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>RING_NONE</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>INCR_WRITE_REV</name>
+                        <description>If 1, and INCR_WRITE is 1, the write address is decremented rather than incremented with each transfer.
+
+                            If 1, and INCR_WRITE is 0, this otherwise-unused combination causes the write address to be incremented by twice the transfer size, i.e. skipping over alternate addresses.</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INCR_WRITE</name>
+                        <description>If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.
+
+                            Generally this should be disabled for memory-to-peripheral transfers.</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INCR_READ_REV</name>
+                        <description>If 1, and INCR_READ is 1, the read address is decremented rather than incremented with each transfer.
+
+                            If 1, and INCR_READ is 0, this otherwise-unused combination causes the read address to be incremented by twice the transfer size, i.e. skipping over alternate addresses.</description>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INCR_READ</name>
+                        <description>If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.
+
+                            Generally this should be disabled for peripheral-to-memory transfers.</description>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DATA_SIZE</name>
+                        <description>Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.</description>
+                        <bitRange>[3:2]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>SIZE_BYTE</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SIZE_HALFWORD</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SIZE_WORD</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>HIGH_PRIORITY</name>
+                        <description>HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.
+
+                            This only affects the order in which the DMA schedules channels. The DMA&#39;s bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>EN</name>
+                        <description>DMA Channel Enable. 
+                            When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH3_AL1_CTRL</name>
+                <addressOffset>0x000000d0</addressOffset>
+                <description>Alias for channel 3 CTRL register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH3_AL1_CTRL</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH3_AL1_READ_ADDR</name>
+                <addressOffset>0x000000d4</addressOffset>
+                <description>Alias for channel 3 READ_ADDR register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH3_AL1_READ_ADDR</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH3_AL1_WRITE_ADDR</name>
+                <addressOffset>0x000000d8</addressOffset>
+                <description>Alias for channel 3 WRITE_ADDR register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH3_AL1_WRITE_ADDR</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH3_AL1_TRANS_COUNT_TRIG</name>
+                <addressOffset>0x000000dc</addressOffset>
+                <description>Alias for channel 3 TRANS_COUNT register 
+                    This is a trigger register (0xc). Writing a nonzero value will 
+                    reload the channel counter and start the channel.</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH3_AL1_TRANS_COUNT_TRIG</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH3_AL2_CTRL</name>
+                <addressOffset>0x000000e0</addressOffset>
+                <description>Alias for channel 3 CTRL register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH3_AL2_CTRL</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH3_AL2_TRANS_COUNT</name>
+                <addressOffset>0x000000e4</addressOffset>
+                <description>Alias for channel 3 TRANS_COUNT register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH3_AL2_TRANS_COUNT</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH3_AL2_READ_ADDR</name>
+                <addressOffset>0x000000e8</addressOffset>
+                <description>Alias for channel 3 READ_ADDR register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH3_AL2_READ_ADDR</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH3_AL2_WRITE_ADDR_TRIG</name>
+                <addressOffset>0x000000ec</addressOffset>
+                <description>Alias for channel 3 WRITE_ADDR register 
+                    This is a trigger register (0xc). Writing a nonzero value will 
+                    reload the channel counter and start the channel.</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH3_AL2_WRITE_ADDR_TRIG</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH3_AL3_CTRL</name>
+                <addressOffset>0x000000f0</addressOffset>
+                <description>Alias for channel 3 CTRL register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH3_AL3_CTRL</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH3_AL3_WRITE_ADDR</name>
+                <addressOffset>0x000000f4</addressOffset>
+                <description>Alias for channel 3 WRITE_ADDR register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH3_AL3_WRITE_ADDR</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH3_AL3_TRANS_COUNT</name>
+                <addressOffset>0x000000f8</addressOffset>
+                <description>Alias for channel 3 TRANS_COUNT register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH3_AL3_TRANS_COUNT</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH3_AL3_READ_ADDR_TRIG</name>
+                <addressOffset>0x000000fc</addressOffset>
+                <description>Alias for channel 3 READ_ADDR register 
+                    This is a trigger register (0xc). Writing a nonzero value will 
+                    reload the channel counter and start the channel.</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH3_AL3_READ_ADDR_TRIG</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH4_READ_ADDR</name>
+                <addressOffset>0x00000100</addressOffset>
+                <description>DMA Channel 4 Read Address pointer</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CH4_READ_ADDR</name>
+                        <description>This register updates automatically each time a read completes. The current value is the next address to be read by this channel.</description>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH4_WRITE_ADDR</name>
+                <addressOffset>0x00000104</addressOffset>
+                <description>DMA Channel 4 Write Address pointer</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CH4_WRITE_ADDR</name>
+                        <description>This register updates automatically each time a write completes. The current value is the next address to be written by this channel.</description>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH4_TRANS_COUNT</name>
+                <addressOffset>0x00000108</addressOffset>
+                <description>DMA Channel 4 Transfer Count</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>MODE</name>
+                        <description>When MODE is 0x0, the transfer count decrements with each transfer until 0, and then the channel triggers the next channel indicated by CTRL_CHAIN_TO.
+
+                            When MODE is 0x1, the transfer count decrements with each transfer until 0, and then the channel re-triggers itself, in addition to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an endless ring-buffer DMA with periodic interrupts.
+
+                            When MODE is 0xf, the transfer count does not decrement. The DMA channel performs an endless sequence of transfers, never triggering other channels or raising interrupts, until an ABORT is raised.
+
+                            All other values are reserved.</description>
+                        <bitRange>[31:28]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TRIGGER_SELF</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ENDLESS</name>
+                                <value>15</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>COUNT</name>
+                        <description>28-bit transfer count (256 million transfers maximum).
+
+                            Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).
+
+                            When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.
+
+                            Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.
+
+                            The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD.</description>
+                        <bitRange>[27:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH4_CTRL_TRIG</name>
+                <addressOffset>0x0000010c</addressOffset>
+                <description>DMA Channel 4 Control and Status</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>AHB_ERROR</name>
+                        <description>Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag.</description>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>READ_ERROR</name>
+                        <description>If 1, the channel received a read bus error. Write one to clear. 
+                            READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)</description>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>WRITE_ERROR</name>
+                        <description>If 1, the channel received a write bus error. Write one to clear. 
+                            WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)</description>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>BUSY</name>
+                        <description>This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.
+
+                            To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT.</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SNIFF_EN</name>
+                        <description>If 1, this channel&#39;s data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.
+
+                            This allows checksum to be enabled or disabled on a per-control- block basis.</description>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>BSWAP</name>
+                        <description>Apply byte-swap transformation to DMA data. 
+                            For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.</description>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>IRQ_QUIET</name>
+                        <description>In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.
+
+                            This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.</description>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>TREQ_SEL</name>
+                        <description>Select a Transfer Request signal. 
+                            The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). 
+                            0x0 to 0x3a -&gt; select DREQ n as TREQ</description>
+                        <bitRange>[22:17]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>PIO0_TX0</name>
+                                <value>0</value>
+                                <description>Select PIO0&#39;s TX FIFO 0 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO0_TX1</name>
+                                <value>1</value>
+                                <description>Select PIO0&#39;s TX FIFO 1 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO0_TX2</name>
+                                <value>2</value>
+                                <description>Select PIO0&#39;s TX FIFO 2 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO0_TX3</name>
+                                <value>3</value>
+                                <description>Select PIO0&#39;s TX FIFO 3 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO0_RX0</name>
+                                <value>4</value>
+                                <description>Select PIO0&#39;s RX FIFO 0 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO0_RX1</name>
+                                <value>5</value>
+                                <description>Select PIO0&#39;s RX FIFO 1 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO0_RX2</name>
+                                <value>6</value>
+                                <description>Select PIO0&#39;s RX FIFO 2 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO0_RX3</name>
+                                <value>7</value>
+                                <description>Select PIO0&#39;s RX FIFO 3 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_TX0</name>
+                                <value>8</value>
+                                <description>Select PIO1&#39;s TX FIFO 0 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_TX1</name>
+                                <value>9</value>
+                                <description>Select PIO1&#39;s TX FIFO 1 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_TX2</name>
+                                <value>10</value>
+                                <description>Select PIO1&#39;s TX FIFO 2 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_TX3</name>
+                                <value>11</value>
+                                <description>Select PIO1&#39;s TX FIFO 3 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_RX0</name>
+                                <value>12</value>
+                                <description>Select PIO1&#39;s RX FIFO 0 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_RX1</name>
+                                <value>13</value>
+                                <description>Select PIO1&#39;s RX FIFO 1 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_RX2</name>
+                                <value>14</value>
+                                <description>Select PIO1&#39;s RX FIFO 2 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_RX3</name>
+                                <value>15</value>
+                                <description>Select PIO1&#39;s RX FIFO 3 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO2_TX0</name>
+                                <value>16</value>
+                                <description>Select PIO2&#39;s TX FIFO 0 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO2_TX1</name>
+                                <value>17</value>
+                                <description>Select PIO2&#39;s TX FIFO 1 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO2_TX2</name>
+                                <value>18</value>
+                                <description>Select PIO2&#39;s TX FIFO 2 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO2_TX3</name>
+                                <value>19</value>
+                                <description>Select PIO2&#39;s TX FIFO 3 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO2_RX0</name>
+                                <value>20</value>
+                                <description>Select PIO2&#39;s RX FIFO 0 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO2_RX1</name>
+                                <value>21</value>
+                                <description>Select PIO2&#39;s RX FIFO 1 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO2_RX2</name>
+                                <value>22</value>
+                                <description>Select PIO2&#39;s RX FIFO 2 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO2_RX3</name>
+                                <value>23</value>
+                                <description>Select PIO2&#39;s RX FIFO 3 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SPI0_TX</name>
+                                <value>24</value>
+                                <description>Select SPI0&#39;s TX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SPI0_RX</name>
+                                <value>25</value>
+                                <description>Select SPI0&#39;s RX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SPI1_TX</name>
+                                <value>26</value>
+                                <description>Select SPI1&#39;s TX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SPI1_RX</name>
+                                <value>27</value>
+                                <description>Select SPI1&#39;s RX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UART0_TX</name>
+                                <value>28</value>
+                                <description>Select UART0&#39;s TX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UART0_RX</name>
+                                <value>29</value>
+                                <description>Select UART0&#39;s RX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UART1_TX</name>
+                                <value>30</value>
+                                <description>Select UART1&#39;s TX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UART1_RX</name>
+                                <value>31</value>
+                                <description>Select UART1&#39;s RX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP0</name>
+                                <value>32</value>
+                                <description>Select PWM Counter 0&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP1</name>
+                                <value>33</value>
+                                <description>Select PWM Counter 1&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP2</name>
+                                <value>34</value>
+                                <description>Select PWM Counter 2&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP3</name>
+                                <value>35</value>
+                                <description>Select PWM Counter 3&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP4</name>
+                                <value>36</value>
+                                <description>Select PWM Counter 4&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP5</name>
+                                <value>37</value>
+                                <description>Select PWM Counter 5&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP6</name>
+                                <value>38</value>
+                                <description>Select PWM Counter 6&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP7</name>
+                                <value>39</value>
+                                <description>Select PWM Counter 7&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP8</name>
+                                <value>40</value>
+                                <description>Select PWM Counter 8&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP9</name>
+                                <value>41</value>
+                                <description>Select PWM Counter 9&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP10</name>
+                                <value>42</value>
+                                <description>Select PWM Counter 0&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP11</name>
+                                <value>43</value>
+                                <description>Select PWM Counter 1&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>I2C0_TX</name>
+                                <value>44</value>
+                                <description>Select I2C0&#39;s TX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>I2C0_RX</name>
+                                <value>45</value>
+                                <description>Select I2C0&#39;s RX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>I2C1_TX</name>
+                                <value>46</value>
+                                <description>Select I2C1&#39;s TX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>I2C1_RX</name>
+                                <value>47</value>
+                                <description>Select I2C1&#39;s RX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC</name>
+                                <value>48</value>
+                                <description>Select the ADC as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>XIP_STREAM</name>
+                                <value>49</value>
+                                <description>Select the XIP Streaming FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>XIP_QMITX</name>
+                                <value>50</value>
+                                <description>Select XIP_QMITX as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>XIP_QMIRX</name>
+                                <value>51</value>
+                                <description>Select XIP_QMIRX as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HSTX</name>
+                                <value>52</value>
+                                <description>Select HSTX as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CORESIGHT</name>
+                                <value>53</value>
+                                <description>Select CORESIGHT as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SHA256</name>
+                                <value>54</value>
+                                <description>Select SHA256 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TIMER0</name>
+                                <value>59</value>
+                                <description>Select Timer 0 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TIMER1</name>
+                                <value>60</value>
+                                <description>Select Timer 1 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TIMER2</name>
+                                <value>61</value>
+                                <description>Select Timer 2 as TREQ (Optional)</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TIMER3</name>
+                                <value>62</value>
+                                <description>Select Timer 3 as TREQ (Optional)</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PERMANENT</name>
+                                <value>63</value>
+                                <description>Permanent request, for unpaced transfers.</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>CHAIN_TO</name>
+                        <description>When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.
+
+                            Note this field resets to 0, so channels 1 and above will chain to channel 0 by default. Set this field to avoid this behaviour.</description>
+                        <bitRange>[16:13]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>RING_SEL</name>
+                        <description>Select whether RING_SIZE applies to read or write addresses. 
+                            If 0, read addresses are wrapped on a (1 &lt;&lt; RING_SIZE) boundary. If 1, write addresses are wrapped.</description>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>RING_SIZE</name>
+                        <description>Size of address wrap region. If 0, don&#39;t wrap. For values n &gt; 0, only the lower n bits of the address will change. This wraps the address on a (1 &lt;&lt; n) byte boundary, facilitating access to naturally-aligned ring buffers.
+
+                            Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.</description>
+                        <bitRange>[11:8]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>RING_NONE</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>INCR_WRITE_REV</name>
+                        <description>If 1, and INCR_WRITE is 1, the write address is decremented rather than incremented with each transfer.
+
+                            If 1, and INCR_WRITE is 0, this otherwise-unused combination causes the write address to be incremented by twice the transfer size, i.e. skipping over alternate addresses.</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INCR_WRITE</name>
+                        <description>If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.
+
+                            Generally this should be disabled for memory-to-peripheral transfers.</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INCR_READ_REV</name>
+                        <description>If 1, and INCR_READ is 1, the read address is decremented rather than incremented with each transfer.
+
+                            If 1, and INCR_READ is 0, this otherwise-unused combination causes the read address to be incremented by twice the transfer size, i.e. skipping over alternate addresses.</description>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INCR_READ</name>
+                        <description>If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.
+
+                            Generally this should be disabled for peripheral-to-memory transfers.</description>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DATA_SIZE</name>
+                        <description>Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.</description>
+                        <bitRange>[3:2]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>SIZE_BYTE</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SIZE_HALFWORD</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SIZE_WORD</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>HIGH_PRIORITY</name>
+                        <description>HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.
+
+                            This only affects the order in which the DMA schedules channels. The DMA&#39;s bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>EN</name>
+                        <description>DMA Channel Enable. 
+                            When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH4_AL1_CTRL</name>
+                <addressOffset>0x00000110</addressOffset>
+                <description>Alias for channel 4 CTRL register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH4_AL1_CTRL</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH4_AL1_READ_ADDR</name>
+                <addressOffset>0x00000114</addressOffset>
+                <description>Alias for channel 4 READ_ADDR register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH4_AL1_READ_ADDR</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH4_AL1_WRITE_ADDR</name>
+                <addressOffset>0x00000118</addressOffset>
+                <description>Alias for channel 4 WRITE_ADDR register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH4_AL1_WRITE_ADDR</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH4_AL1_TRANS_COUNT_TRIG</name>
+                <addressOffset>0x0000011c</addressOffset>
+                <description>Alias for channel 4 TRANS_COUNT register 
+                    This is a trigger register (0xc). Writing a nonzero value will 
+                    reload the channel counter and start the channel.</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH4_AL1_TRANS_COUNT_TRIG</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH4_AL2_CTRL</name>
+                <addressOffset>0x00000120</addressOffset>
+                <description>Alias for channel 4 CTRL register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH4_AL2_CTRL</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH4_AL2_TRANS_COUNT</name>
+                <addressOffset>0x00000124</addressOffset>
+                <description>Alias for channel 4 TRANS_COUNT register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH4_AL2_TRANS_COUNT</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH4_AL2_READ_ADDR</name>
+                <addressOffset>0x00000128</addressOffset>
+                <description>Alias for channel 4 READ_ADDR register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH4_AL2_READ_ADDR</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH4_AL2_WRITE_ADDR_TRIG</name>
+                <addressOffset>0x0000012c</addressOffset>
+                <description>Alias for channel 4 WRITE_ADDR register 
+                    This is a trigger register (0xc). Writing a nonzero value will 
+                    reload the channel counter and start the channel.</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH4_AL2_WRITE_ADDR_TRIG</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH4_AL3_CTRL</name>
+                <addressOffset>0x00000130</addressOffset>
+                <description>Alias for channel 4 CTRL register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH4_AL3_CTRL</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH4_AL3_WRITE_ADDR</name>
+                <addressOffset>0x00000134</addressOffset>
+                <description>Alias for channel 4 WRITE_ADDR register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH4_AL3_WRITE_ADDR</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH4_AL3_TRANS_COUNT</name>
+                <addressOffset>0x00000138</addressOffset>
+                <description>Alias for channel 4 TRANS_COUNT register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH4_AL3_TRANS_COUNT</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH4_AL3_READ_ADDR_TRIG</name>
+                <addressOffset>0x0000013c</addressOffset>
+                <description>Alias for channel 4 READ_ADDR register 
+                    This is a trigger register (0xc). Writing a nonzero value will 
+                    reload the channel counter and start the channel.</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH4_AL3_READ_ADDR_TRIG</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH5_READ_ADDR</name>
+                <addressOffset>0x00000140</addressOffset>
+                <description>DMA Channel 5 Read Address pointer</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CH5_READ_ADDR</name>
+                        <description>This register updates automatically each time a read completes. The current value is the next address to be read by this channel.</description>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH5_WRITE_ADDR</name>
+                <addressOffset>0x00000144</addressOffset>
+                <description>DMA Channel 5 Write Address pointer</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CH5_WRITE_ADDR</name>
+                        <description>This register updates automatically each time a write completes. The current value is the next address to be written by this channel.</description>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH5_TRANS_COUNT</name>
+                <addressOffset>0x00000148</addressOffset>
+                <description>DMA Channel 5 Transfer Count</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>MODE</name>
+                        <description>When MODE is 0x0, the transfer count decrements with each transfer until 0, and then the channel triggers the next channel indicated by CTRL_CHAIN_TO.
+
+                            When MODE is 0x1, the transfer count decrements with each transfer until 0, and then the channel re-triggers itself, in addition to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an endless ring-buffer DMA with periodic interrupts.
+
+                            When MODE is 0xf, the transfer count does not decrement. The DMA channel performs an endless sequence of transfers, never triggering other channels or raising interrupts, until an ABORT is raised.
+
+                            All other values are reserved.</description>
+                        <bitRange>[31:28]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TRIGGER_SELF</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ENDLESS</name>
+                                <value>15</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>COUNT</name>
+                        <description>28-bit transfer count (256 million transfers maximum).
+
+                            Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).
+
+                            When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.
+
+                            Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.
+
+                            The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD.</description>
+                        <bitRange>[27:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH5_CTRL_TRIG</name>
+                <addressOffset>0x0000014c</addressOffset>
+                <description>DMA Channel 5 Control and Status</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>AHB_ERROR</name>
+                        <description>Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag.</description>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>READ_ERROR</name>
+                        <description>If 1, the channel received a read bus error. Write one to clear. 
+                            READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)</description>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>WRITE_ERROR</name>
+                        <description>If 1, the channel received a write bus error. Write one to clear. 
+                            WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)</description>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>BUSY</name>
+                        <description>This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.
+
+                            To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT.</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SNIFF_EN</name>
+                        <description>If 1, this channel&#39;s data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.
+
+                            This allows checksum to be enabled or disabled on a per-control- block basis.</description>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>BSWAP</name>
+                        <description>Apply byte-swap transformation to DMA data. 
+                            For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.</description>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>IRQ_QUIET</name>
+                        <description>In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.
+
+                            This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.</description>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>TREQ_SEL</name>
+                        <description>Select a Transfer Request signal. 
+                            The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). 
+                            0x0 to 0x3a -&gt; select DREQ n as TREQ</description>
+                        <bitRange>[22:17]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>PIO0_TX0</name>
+                                <value>0</value>
+                                <description>Select PIO0&#39;s TX FIFO 0 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO0_TX1</name>
+                                <value>1</value>
+                                <description>Select PIO0&#39;s TX FIFO 1 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO0_TX2</name>
+                                <value>2</value>
+                                <description>Select PIO0&#39;s TX FIFO 2 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO0_TX3</name>
+                                <value>3</value>
+                                <description>Select PIO0&#39;s TX FIFO 3 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO0_RX0</name>
+                                <value>4</value>
+                                <description>Select PIO0&#39;s RX FIFO 0 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO0_RX1</name>
+                                <value>5</value>
+                                <description>Select PIO0&#39;s RX FIFO 1 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO0_RX2</name>
+                                <value>6</value>
+                                <description>Select PIO0&#39;s RX FIFO 2 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO0_RX3</name>
+                                <value>7</value>
+                                <description>Select PIO0&#39;s RX FIFO 3 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_TX0</name>
+                                <value>8</value>
+                                <description>Select PIO1&#39;s TX FIFO 0 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_TX1</name>
+                                <value>9</value>
+                                <description>Select PIO1&#39;s TX FIFO 1 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_TX2</name>
+                                <value>10</value>
+                                <description>Select PIO1&#39;s TX FIFO 2 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_TX3</name>
+                                <value>11</value>
+                                <description>Select PIO1&#39;s TX FIFO 3 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_RX0</name>
+                                <value>12</value>
+                                <description>Select PIO1&#39;s RX FIFO 0 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_RX1</name>
+                                <value>13</value>
+                                <description>Select PIO1&#39;s RX FIFO 1 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_RX2</name>
+                                <value>14</value>
+                                <description>Select PIO1&#39;s RX FIFO 2 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_RX3</name>
+                                <value>15</value>
+                                <description>Select PIO1&#39;s RX FIFO 3 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO2_TX0</name>
+                                <value>16</value>
+                                <description>Select PIO2&#39;s TX FIFO 0 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO2_TX1</name>
+                                <value>17</value>
+                                <description>Select PIO2&#39;s TX FIFO 1 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO2_TX2</name>
+                                <value>18</value>
+                                <description>Select PIO2&#39;s TX FIFO 2 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO2_TX3</name>
+                                <value>19</value>
+                                <description>Select PIO2&#39;s TX FIFO 3 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO2_RX0</name>
+                                <value>20</value>
+                                <description>Select PIO2&#39;s RX FIFO 0 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO2_RX1</name>
+                                <value>21</value>
+                                <description>Select PIO2&#39;s RX FIFO 1 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO2_RX2</name>
+                                <value>22</value>
+                                <description>Select PIO2&#39;s RX FIFO 2 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO2_RX3</name>
+                                <value>23</value>
+                                <description>Select PIO2&#39;s RX FIFO 3 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SPI0_TX</name>
+                                <value>24</value>
+                                <description>Select SPI0&#39;s TX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SPI0_RX</name>
+                                <value>25</value>
+                                <description>Select SPI0&#39;s RX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SPI1_TX</name>
+                                <value>26</value>
+                                <description>Select SPI1&#39;s TX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SPI1_RX</name>
+                                <value>27</value>
+                                <description>Select SPI1&#39;s RX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UART0_TX</name>
+                                <value>28</value>
+                                <description>Select UART0&#39;s TX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UART0_RX</name>
+                                <value>29</value>
+                                <description>Select UART0&#39;s RX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UART1_TX</name>
+                                <value>30</value>
+                                <description>Select UART1&#39;s TX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UART1_RX</name>
+                                <value>31</value>
+                                <description>Select UART1&#39;s RX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP0</name>
+                                <value>32</value>
+                                <description>Select PWM Counter 0&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP1</name>
+                                <value>33</value>
+                                <description>Select PWM Counter 1&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP2</name>
+                                <value>34</value>
+                                <description>Select PWM Counter 2&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP3</name>
+                                <value>35</value>
+                                <description>Select PWM Counter 3&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP4</name>
+                                <value>36</value>
+                                <description>Select PWM Counter 4&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP5</name>
+                                <value>37</value>
+                                <description>Select PWM Counter 5&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP6</name>
+                                <value>38</value>
+                                <description>Select PWM Counter 6&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP7</name>
+                                <value>39</value>
+                                <description>Select PWM Counter 7&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP8</name>
+                                <value>40</value>
+                                <description>Select PWM Counter 8&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP9</name>
+                                <value>41</value>
+                                <description>Select PWM Counter 9&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP10</name>
+                                <value>42</value>
+                                <description>Select PWM Counter 0&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP11</name>
+                                <value>43</value>
+                                <description>Select PWM Counter 1&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>I2C0_TX</name>
+                                <value>44</value>
+                                <description>Select I2C0&#39;s TX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>I2C0_RX</name>
+                                <value>45</value>
+                                <description>Select I2C0&#39;s RX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>I2C1_TX</name>
+                                <value>46</value>
+                                <description>Select I2C1&#39;s TX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>I2C1_RX</name>
+                                <value>47</value>
+                                <description>Select I2C1&#39;s RX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC</name>
+                                <value>48</value>
+                                <description>Select the ADC as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>XIP_STREAM</name>
+                                <value>49</value>
+                                <description>Select the XIP Streaming FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>XIP_QMITX</name>
+                                <value>50</value>
+                                <description>Select XIP_QMITX as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>XIP_QMIRX</name>
+                                <value>51</value>
+                                <description>Select XIP_QMIRX as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HSTX</name>
+                                <value>52</value>
+                                <description>Select HSTX as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CORESIGHT</name>
+                                <value>53</value>
+                                <description>Select CORESIGHT as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SHA256</name>
+                                <value>54</value>
+                                <description>Select SHA256 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TIMER0</name>
+                                <value>59</value>
+                                <description>Select Timer 0 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TIMER1</name>
+                                <value>60</value>
+                                <description>Select Timer 1 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TIMER2</name>
+                                <value>61</value>
+                                <description>Select Timer 2 as TREQ (Optional)</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TIMER3</name>
+                                <value>62</value>
+                                <description>Select Timer 3 as TREQ (Optional)</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PERMANENT</name>
+                                <value>63</value>
+                                <description>Permanent request, for unpaced transfers.</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>CHAIN_TO</name>
+                        <description>When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.
+
+                            Note this field resets to 0, so channels 1 and above will chain to channel 0 by default. Set this field to avoid this behaviour.</description>
+                        <bitRange>[16:13]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>RING_SEL</name>
+                        <description>Select whether RING_SIZE applies to read or write addresses. 
+                            If 0, read addresses are wrapped on a (1 &lt;&lt; RING_SIZE) boundary. If 1, write addresses are wrapped.</description>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>RING_SIZE</name>
+                        <description>Size of address wrap region. If 0, don&#39;t wrap. For values n &gt; 0, only the lower n bits of the address will change. This wraps the address on a (1 &lt;&lt; n) byte boundary, facilitating access to naturally-aligned ring buffers.
+
+                            Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.</description>
+                        <bitRange>[11:8]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>RING_NONE</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>INCR_WRITE_REV</name>
+                        <description>If 1, and INCR_WRITE is 1, the write address is decremented rather than incremented with each transfer.
+
+                            If 1, and INCR_WRITE is 0, this otherwise-unused combination causes the write address to be incremented by twice the transfer size, i.e. skipping over alternate addresses.</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INCR_WRITE</name>
+                        <description>If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.
+
+                            Generally this should be disabled for memory-to-peripheral transfers.</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INCR_READ_REV</name>
+                        <description>If 1, and INCR_READ is 1, the read address is decremented rather than incremented with each transfer.
+
+                            If 1, and INCR_READ is 0, this otherwise-unused combination causes the read address to be incremented by twice the transfer size, i.e. skipping over alternate addresses.</description>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INCR_READ</name>
+                        <description>If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.
+
+                            Generally this should be disabled for peripheral-to-memory transfers.</description>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DATA_SIZE</name>
+                        <description>Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.</description>
+                        <bitRange>[3:2]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>SIZE_BYTE</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SIZE_HALFWORD</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SIZE_WORD</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>HIGH_PRIORITY</name>
+                        <description>HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.
+
+                            This only affects the order in which the DMA schedules channels. The DMA&#39;s bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>EN</name>
+                        <description>DMA Channel Enable. 
+                            When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH5_AL1_CTRL</name>
+                <addressOffset>0x00000150</addressOffset>
+                <description>Alias for channel 5 CTRL register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH5_AL1_CTRL</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH5_AL1_READ_ADDR</name>
+                <addressOffset>0x00000154</addressOffset>
+                <description>Alias for channel 5 READ_ADDR register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH5_AL1_READ_ADDR</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH5_AL1_WRITE_ADDR</name>
+                <addressOffset>0x00000158</addressOffset>
+                <description>Alias for channel 5 WRITE_ADDR register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH5_AL1_WRITE_ADDR</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH5_AL1_TRANS_COUNT_TRIG</name>
+                <addressOffset>0x0000015c</addressOffset>
+                <description>Alias for channel 5 TRANS_COUNT register 
+                    This is a trigger register (0xc). Writing a nonzero value will 
+                    reload the channel counter and start the channel.</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH5_AL1_TRANS_COUNT_TRIG</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH5_AL2_CTRL</name>
+                <addressOffset>0x00000160</addressOffset>
+                <description>Alias for channel 5 CTRL register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH5_AL2_CTRL</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH5_AL2_TRANS_COUNT</name>
+                <addressOffset>0x00000164</addressOffset>
+                <description>Alias for channel 5 TRANS_COUNT register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH5_AL2_TRANS_COUNT</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH5_AL2_READ_ADDR</name>
+                <addressOffset>0x00000168</addressOffset>
+                <description>Alias for channel 5 READ_ADDR register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH5_AL2_READ_ADDR</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH5_AL2_WRITE_ADDR_TRIG</name>
+                <addressOffset>0x0000016c</addressOffset>
+                <description>Alias for channel 5 WRITE_ADDR register 
+                    This is a trigger register (0xc). Writing a nonzero value will 
+                    reload the channel counter and start the channel.</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH5_AL2_WRITE_ADDR_TRIG</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH5_AL3_CTRL</name>
+                <addressOffset>0x00000170</addressOffset>
+                <description>Alias for channel 5 CTRL register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH5_AL3_CTRL</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH5_AL3_WRITE_ADDR</name>
+                <addressOffset>0x00000174</addressOffset>
+                <description>Alias for channel 5 WRITE_ADDR register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH5_AL3_WRITE_ADDR</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH5_AL3_TRANS_COUNT</name>
+                <addressOffset>0x00000178</addressOffset>
+                <description>Alias for channel 5 TRANS_COUNT register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH5_AL3_TRANS_COUNT</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH5_AL3_READ_ADDR_TRIG</name>
+                <addressOffset>0x0000017c</addressOffset>
+                <description>Alias for channel 5 READ_ADDR register 
+                    This is a trigger register (0xc). Writing a nonzero value will 
+                    reload the channel counter and start the channel.</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH5_AL3_READ_ADDR_TRIG</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH6_READ_ADDR</name>
+                <addressOffset>0x00000180</addressOffset>
+                <description>DMA Channel 6 Read Address pointer</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CH6_READ_ADDR</name>
+                        <description>This register updates automatically each time a read completes. The current value is the next address to be read by this channel.</description>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH6_WRITE_ADDR</name>
+                <addressOffset>0x00000184</addressOffset>
+                <description>DMA Channel 6 Write Address pointer</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CH6_WRITE_ADDR</name>
+                        <description>This register updates automatically each time a write completes. The current value is the next address to be written by this channel.</description>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH6_TRANS_COUNT</name>
+                <addressOffset>0x00000188</addressOffset>
+                <description>DMA Channel 6 Transfer Count</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>MODE</name>
+                        <description>When MODE is 0x0, the transfer count decrements with each transfer until 0, and then the channel triggers the next channel indicated by CTRL_CHAIN_TO.
+
+                            When MODE is 0x1, the transfer count decrements with each transfer until 0, and then the channel re-triggers itself, in addition to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an endless ring-buffer DMA with periodic interrupts.
+
+                            When MODE is 0xf, the transfer count does not decrement. The DMA channel performs an endless sequence of transfers, never triggering other channels or raising interrupts, until an ABORT is raised.
+
+                            All other values are reserved.</description>
+                        <bitRange>[31:28]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TRIGGER_SELF</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ENDLESS</name>
+                                <value>15</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>COUNT</name>
+                        <description>28-bit transfer count (256 million transfers maximum).
+
+                            Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).
+
+                            When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.
+
+                            Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.
+
+                            The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD.</description>
+                        <bitRange>[27:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH6_CTRL_TRIG</name>
+                <addressOffset>0x0000018c</addressOffset>
+                <description>DMA Channel 6 Control and Status</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>AHB_ERROR</name>
+                        <description>Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag.</description>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>READ_ERROR</name>
+                        <description>If 1, the channel received a read bus error. Write one to clear. 
+                            READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)</description>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>WRITE_ERROR</name>
+                        <description>If 1, the channel received a write bus error. Write one to clear. 
+                            WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)</description>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>BUSY</name>
+                        <description>This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.
+
+                            To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT.</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SNIFF_EN</name>
+                        <description>If 1, this channel&#39;s data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.
+
+                            This allows checksum to be enabled or disabled on a per-control- block basis.</description>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>BSWAP</name>
+                        <description>Apply byte-swap transformation to DMA data. 
+                            For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.</description>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>IRQ_QUIET</name>
+                        <description>In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.
+
+                            This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.</description>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>TREQ_SEL</name>
+                        <description>Select a Transfer Request signal. 
+                            The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). 
+                            0x0 to 0x3a -&gt; select DREQ n as TREQ</description>
+                        <bitRange>[22:17]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>PIO0_TX0</name>
+                                <value>0</value>
+                                <description>Select PIO0&#39;s TX FIFO 0 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO0_TX1</name>
+                                <value>1</value>
+                                <description>Select PIO0&#39;s TX FIFO 1 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO0_TX2</name>
+                                <value>2</value>
+                                <description>Select PIO0&#39;s TX FIFO 2 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO0_TX3</name>
+                                <value>3</value>
+                                <description>Select PIO0&#39;s TX FIFO 3 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO0_RX0</name>
+                                <value>4</value>
+                                <description>Select PIO0&#39;s RX FIFO 0 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO0_RX1</name>
+                                <value>5</value>
+                                <description>Select PIO0&#39;s RX FIFO 1 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO0_RX2</name>
+                                <value>6</value>
+                                <description>Select PIO0&#39;s RX FIFO 2 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO0_RX3</name>
+                                <value>7</value>
+                                <description>Select PIO0&#39;s RX FIFO 3 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_TX0</name>
+                                <value>8</value>
+                                <description>Select PIO1&#39;s TX FIFO 0 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_TX1</name>
+                                <value>9</value>
+                                <description>Select PIO1&#39;s TX FIFO 1 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_TX2</name>
+                                <value>10</value>
+                                <description>Select PIO1&#39;s TX FIFO 2 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_TX3</name>
+                                <value>11</value>
+                                <description>Select PIO1&#39;s TX FIFO 3 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_RX0</name>
+                                <value>12</value>
+                                <description>Select PIO1&#39;s RX FIFO 0 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_RX1</name>
+                                <value>13</value>
+                                <description>Select PIO1&#39;s RX FIFO 1 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_RX2</name>
+                                <value>14</value>
+                                <description>Select PIO1&#39;s RX FIFO 2 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_RX3</name>
+                                <value>15</value>
+                                <description>Select PIO1&#39;s RX FIFO 3 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO2_TX0</name>
+                                <value>16</value>
+                                <description>Select PIO2&#39;s TX FIFO 0 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO2_TX1</name>
+                                <value>17</value>
+                                <description>Select PIO2&#39;s TX FIFO 1 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO2_TX2</name>
+                                <value>18</value>
+                                <description>Select PIO2&#39;s TX FIFO 2 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO2_TX3</name>
+                                <value>19</value>
+                                <description>Select PIO2&#39;s TX FIFO 3 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO2_RX0</name>
+                                <value>20</value>
+                                <description>Select PIO2&#39;s RX FIFO 0 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO2_RX1</name>
+                                <value>21</value>
+                                <description>Select PIO2&#39;s RX FIFO 1 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO2_RX2</name>
+                                <value>22</value>
+                                <description>Select PIO2&#39;s RX FIFO 2 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO2_RX3</name>
+                                <value>23</value>
+                                <description>Select PIO2&#39;s RX FIFO 3 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SPI0_TX</name>
+                                <value>24</value>
+                                <description>Select SPI0&#39;s TX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SPI0_RX</name>
+                                <value>25</value>
+                                <description>Select SPI0&#39;s RX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SPI1_TX</name>
+                                <value>26</value>
+                                <description>Select SPI1&#39;s TX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SPI1_RX</name>
+                                <value>27</value>
+                                <description>Select SPI1&#39;s RX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UART0_TX</name>
+                                <value>28</value>
+                                <description>Select UART0&#39;s TX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UART0_RX</name>
+                                <value>29</value>
+                                <description>Select UART0&#39;s RX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UART1_TX</name>
+                                <value>30</value>
+                                <description>Select UART1&#39;s TX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UART1_RX</name>
+                                <value>31</value>
+                                <description>Select UART1&#39;s RX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP0</name>
+                                <value>32</value>
+                                <description>Select PWM Counter 0&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP1</name>
+                                <value>33</value>
+                                <description>Select PWM Counter 1&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP2</name>
+                                <value>34</value>
+                                <description>Select PWM Counter 2&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP3</name>
+                                <value>35</value>
+                                <description>Select PWM Counter 3&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP4</name>
+                                <value>36</value>
+                                <description>Select PWM Counter 4&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP5</name>
+                                <value>37</value>
+                                <description>Select PWM Counter 5&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP6</name>
+                                <value>38</value>
+                                <description>Select PWM Counter 6&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP7</name>
+                                <value>39</value>
+                                <description>Select PWM Counter 7&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP8</name>
+                                <value>40</value>
+                                <description>Select PWM Counter 8&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP9</name>
+                                <value>41</value>
+                                <description>Select PWM Counter 9&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP10</name>
+                                <value>42</value>
+                                <description>Select PWM Counter 0&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP11</name>
+                                <value>43</value>
+                                <description>Select PWM Counter 1&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>I2C0_TX</name>
+                                <value>44</value>
+                                <description>Select I2C0&#39;s TX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>I2C0_RX</name>
+                                <value>45</value>
+                                <description>Select I2C0&#39;s RX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>I2C1_TX</name>
+                                <value>46</value>
+                                <description>Select I2C1&#39;s TX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>I2C1_RX</name>
+                                <value>47</value>
+                                <description>Select I2C1&#39;s RX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC</name>
+                                <value>48</value>
+                                <description>Select the ADC as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>XIP_STREAM</name>
+                                <value>49</value>
+                                <description>Select the XIP Streaming FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>XIP_QMITX</name>
+                                <value>50</value>
+                                <description>Select XIP_QMITX as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>XIP_QMIRX</name>
+                                <value>51</value>
+                                <description>Select XIP_QMIRX as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HSTX</name>
+                                <value>52</value>
+                                <description>Select HSTX as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CORESIGHT</name>
+                                <value>53</value>
+                                <description>Select CORESIGHT as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SHA256</name>
+                                <value>54</value>
+                                <description>Select SHA256 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TIMER0</name>
+                                <value>59</value>
+                                <description>Select Timer 0 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TIMER1</name>
+                                <value>60</value>
+                                <description>Select Timer 1 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TIMER2</name>
+                                <value>61</value>
+                                <description>Select Timer 2 as TREQ (Optional)</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TIMER3</name>
+                                <value>62</value>
+                                <description>Select Timer 3 as TREQ (Optional)</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PERMANENT</name>
+                                <value>63</value>
+                                <description>Permanent request, for unpaced transfers.</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>CHAIN_TO</name>
+                        <description>When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.
+
+                            Note this field resets to 0, so channels 1 and above will chain to channel 0 by default. Set this field to avoid this behaviour.</description>
+                        <bitRange>[16:13]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>RING_SEL</name>
+                        <description>Select whether RING_SIZE applies to read or write addresses. 
+                            If 0, read addresses are wrapped on a (1 &lt;&lt; RING_SIZE) boundary. If 1, write addresses are wrapped.</description>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>RING_SIZE</name>
+                        <description>Size of address wrap region. If 0, don&#39;t wrap. For values n &gt; 0, only the lower n bits of the address will change. This wraps the address on a (1 &lt;&lt; n) byte boundary, facilitating access to naturally-aligned ring buffers.
+
+                            Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.</description>
+                        <bitRange>[11:8]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>RING_NONE</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>INCR_WRITE_REV</name>
+                        <description>If 1, and INCR_WRITE is 1, the write address is decremented rather than incremented with each transfer.
+
+                            If 1, and INCR_WRITE is 0, this otherwise-unused combination causes the write address to be incremented by twice the transfer size, i.e. skipping over alternate addresses.</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INCR_WRITE</name>
+                        <description>If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.
+
+                            Generally this should be disabled for memory-to-peripheral transfers.</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INCR_READ_REV</name>
+                        <description>If 1, and INCR_READ is 1, the read address is decremented rather than incremented with each transfer.
+
+                            If 1, and INCR_READ is 0, this otherwise-unused combination causes the read address to be incremented by twice the transfer size, i.e. skipping over alternate addresses.</description>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INCR_READ</name>
+                        <description>If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.
+
+                            Generally this should be disabled for peripheral-to-memory transfers.</description>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DATA_SIZE</name>
+                        <description>Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.</description>
+                        <bitRange>[3:2]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>SIZE_BYTE</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SIZE_HALFWORD</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SIZE_WORD</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>HIGH_PRIORITY</name>
+                        <description>HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.
+
+                            This only affects the order in which the DMA schedules channels. The DMA&#39;s bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>EN</name>
+                        <description>DMA Channel Enable. 
+                            When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH6_AL1_CTRL</name>
+                <addressOffset>0x00000190</addressOffset>
+                <description>Alias for channel 6 CTRL register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH6_AL1_CTRL</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH6_AL1_READ_ADDR</name>
+                <addressOffset>0x00000194</addressOffset>
+                <description>Alias for channel 6 READ_ADDR register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH6_AL1_READ_ADDR</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH6_AL1_WRITE_ADDR</name>
+                <addressOffset>0x00000198</addressOffset>
+                <description>Alias for channel 6 WRITE_ADDR register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH6_AL1_WRITE_ADDR</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH6_AL1_TRANS_COUNT_TRIG</name>
+                <addressOffset>0x0000019c</addressOffset>
+                <description>Alias for channel 6 TRANS_COUNT register 
+                    This is a trigger register (0xc). Writing a nonzero value will 
+                    reload the channel counter and start the channel.</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH6_AL1_TRANS_COUNT_TRIG</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH6_AL2_CTRL</name>
+                <addressOffset>0x000001a0</addressOffset>
+                <description>Alias for channel 6 CTRL register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH6_AL2_CTRL</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH6_AL2_TRANS_COUNT</name>
+                <addressOffset>0x000001a4</addressOffset>
+                <description>Alias for channel 6 TRANS_COUNT register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH6_AL2_TRANS_COUNT</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH6_AL2_READ_ADDR</name>
+                <addressOffset>0x000001a8</addressOffset>
+                <description>Alias for channel 6 READ_ADDR register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH6_AL2_READ_ADDR</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH6_AL2_WRITE_ADDR_TRIG</name>
+                <addressOffset>0x000001ac</addressOffset>
+                <description>Alias for channel 6 WRITE_ADDR register 
+                    This is a trigger register (0xc). Writing a nonzero value will 
+                    reload the channel counter and start the channel.</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH6_AL2_WRITE_ADDR_TRIG</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH6_AL3_CTRL</name>
+                <addressOffset>0x000001b0</addressOffset>
+                <description>Alias for channel 6 CTRL register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH6_AL3_CTRL</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH6_AL3_WRITE_ADDR</name>
+                <addressOffset>0x000001b4</addressOffset>
+                <description>Alias for channel 6 WRITE_ADDR register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH6_AL3_WRITE_ADDR</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH6_AL3_TRANS_COUNT</name>
+                <addressOffset>0x000001b8</addressOffset>
+                <description>Alias for channel 6 TRANS_COUNT register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH6_AL3_TRANS_COUNT</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH6_AL3_READ_ADDR_TRIG</name>
+                <addressOffset>0x000001bc</addressOffset>
+                <description>Alias for channel 6 READ_ADDR register 
+                    This is a trigger register (0xc). Writing a nonzero value will 
+                    reload the channel counter and start the channel.</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH6_AL3_READ_ADDR_TRIG</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH7_READ_ADDR</name>
+                <addressOffset>0x000001c0</addressOffset>
+                <description>DMA Channel 7 Read Address pointer</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CH7_READ_ADDR</name>
+                        <description>This register updates automatically each time a read completes. The current value is the next address to be read by this channel.</description>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH7_WRITE_ADDR</name>
+                <addressOffset>0x000001c4</addressOffset>
+                <description>DMA Channel 7 Write Address pointer</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CH7_WRITE_ADDR</name>
+                        <description>This register updates automatically each time a write completes. The current value is the next address to be written by this channel.</description>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH7_TRANS_COUNT</name>
+                <addressOffset>0x000001c8</addressOffset>
+                <description>DMA Channel 7 Transfer Count</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>MODE</name>
+                        <description>When MODE is 0x0, the transfer count decrements with each transfer until 0, and then the channel triggers the next channel indicated by CTRL_CHAIN_TO.
+
+                            When MODE is 0x1, the transfer count decrements with each transfer until 0, and then the channel re-triggers itself, in addition to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an endless ring-buffer DMA with periodic interrupts.
+
+                            When MODE is 0xf, the transfer count does not decrement. The DMA channel performs an endless sequence of transfers, never triggering other channels or raising interrupts, until an ABORT is raised.
+
+                            All other values are reserved.</description>
+                        <bitRange>[31:28]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TRIGGER_SELF</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ENDLESS</name>
+                                <value>15</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>COUNT</name>
+                        <description>28-bit transfer count (256 million transfers maximum).
+
+                            Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).
+
+                            When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.
+
+                            Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.
+
+                            The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD.</description>
+                        <bitRange>[27:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH7_CTRL_TRIG</name>
+                <addressOffset>0x000001cc</addressOffset>
+                <description>DMA Channel 7 Control and Status</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>AHB_ERROR</name>
+                        <description>Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag.</description>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>READ_ERROR</name>
+                        <description>If 1, the channel received a read bus error. Write one to clear. 
+                            READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)</description>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>WRITE_ERROR</name>
+                        <description>If 1, the channel received a write bus error. Write one to clear. 
+                            WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)</description>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>BUSY</name>
+                        <description>This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.
+
+                            To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT.</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SNIFF_EN</name>
+                        <description>If 1, this channel&#39;s data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.
+
+                            This allows checksum to be enabled or disabled on a per-control- block basis.</description>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>BSWAP</name>
+                        <description>Apply byte-swap transformation to DMA data. 
+                            For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.</description>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>IRQ_QUIET</name>
+                        <description>In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.
+
+                            This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.</description>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>TREQ_SEL</name>
+                        <description>Select a Transfer Request signal. 
+                            The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). 
+                            0x0 to 0x3a -&gt; select DREQ n as TREQ</description>
+                        <bitRange>[22:17]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>PIO0_TX0</name>
+                                <value>0</value>
+                                <description>Select PIO0&#39;s TX FIFO 0 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO0_TX1</name>
+                                <value>1</value>
+                                <description>Select PIO0&#39;s TX FIFO 1 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO0_TX2</name>
+                                <value>2</value>
+                                <description>Select PIO0&#39;s TX FIFO 2 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO0_TX3</name>
+                                <value>3</value>
+                                <description>Select PIO0&#39;s TX FIFO 3 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO0_RX0</name>
+                                <value>4</value>
+                                <description>Select PIO0&#39;s RX FIFO 0 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO0_RX1</name>
+                                <value>5</value>
+                                <description>Select PIO0&#39;s RX FIFO 1 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO0_RX2</name>
+                                <value>6</value>
+                                <description>Select PIO0&#39;s RX FIFO 2 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO0_RX3</name>
+                                <value>7</value>
+                                <description>Select PIO0&#39;s RX FIFO 3 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_TX0</name>
+                                <value>8</value>
+                                <description>Select PIO1&#39;s TX FIFO 0 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_TX1</name>
+                                <value>9</value>
+                                <description>Select PIO1&#39;s TX FIFO 1 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_TX2</name>
+                                <value>10</value>
+                                <description>Select PIO1&#39;s TX FIFO 2 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_TX3</name>
+                                <value>11</value>
+                                <description>Select PIO1&#39;s TX FIFO 3 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_RX0</name>
+                                <value>12</value>
+                                <description>Select PIO1&#39;s RX FIFO 0 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_RX1</name>
+                                <value>13</value>
+                                <description>Select PIO1&#39;s RX FIFO 1 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_RX2</name>
+                                <value>14</value>
+                                <description>Select PIO1&#39;s RX FIFO 2 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_RX3</name>
+                                <value>15</value>
+                                <description>Select PIO1&#39;s RX FIFO 3 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO2_TX0</name>
+                                <value>16</value>
+                                <description>Select PIO2&#39;s TX FIFO 0 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO2_TX1</name>
+                                <value>17</value>
+                                <description>Select PIO2&#39;s TX FIFO 1 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO2_TX2</name>
+                                <value>18</value>
+                                <description>Select PIO2&#39;s TX FIFO 2 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO2_TX3</name>
+                                <value>19</value>
+                                <description>Select PIO2&#39;s TX FIFO 3 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO2_RX0</name>
+                                <value>20</value>
+                                <description>Select PIO2&#39;s RX FIFO 0 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO2_RX1</name>
+                                <value>21</value>
+                                <description>Select PIO2&#39;s RX FIFO 1 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO2_RX2</name>
+                                <value>22</value>
+                                <description>Select PIO2&#39;s RX FIFO 2 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO2_RX3</name>
+                                <value>23</value>
+                                <description>Select PIO2&#39;s RX FIFO 3 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SPI0_TX</name>
+                                <value>24</value>
+                                <description>Select SPI0&#39;s TX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SPI0_RX</name>
+                                <value>25</value>
+                                <description>Select SPI0&#39;s RX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SPI1_TX</name>
+                                <value>26</value>
+                                <description>Select SPI1&#39;s TX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SPI1_RX</name>
+                                <value>27</value>
+                                <description>Select SPI1&#39;s RX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UART0_TX</name>
+                                <value>28</value>
+                                <description>Select UART0&#39;s TX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UART0_RX</name>
+                                <value>29</value>
+                                <description>Select UART0&#39;s RX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UART1_TX</name>
+                                <value>30</value>
+                                <description>Select UART1&#39;s TX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UART1_RX</name>
+                                <value>31</value>
+                                <description>Select UART1&#39;s RX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP0</name>
+                                <value>32</value>
+                                <description>Select PWM Counter 0&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP1</name>
+                                <value>33</value>
+                                <description>Select PWM Counter 1&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP2</name>
+                                <value>34</value>
+                                <description>Select PWM Counter 2&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP3</name>
+                                <value>35</value>
+                                <description>Select PWM Counter 3&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP4</name>
+                                <value>36</value>
+                                <description>Select PWM Counter 4&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP5</name>
+                                <value>37</value>
+                                <description>Select PWM Counter 5&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP6</name>
+                                <value>38</value>
+                                <description>Select PWM Counter 6&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP7</name>
+                                <value>39</value>
+                                <description>Select PWM Counter 7&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP8</name>
+                                <value>40</value>
+                                <description>Select PWM Counter 8&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP9</name>
+                                <value>41</value>
+                                <description>Select PWM Counter 9&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP10</name>
+                                <value>42</value>
+                                <description>Select PWM Counter 0&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP11</name>
+                                <value>43</value>
+                                <description>Select PWM Counter 1&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>I2C0_TX</name>
+                                <value>44</value>
+                                <description>Select I2C0&#39;s TX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>I2C0_RX</name>
+                                <value>45</value>
+                                <description>Select I2C0&#39;s RX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>I2C1_TX</name>
+                                <value>46</value>
+                                <description>Select I2C1&#39;s TX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>I2C1_RX</name>
+                                <value>47</value>
+                                <description>Select I2C1&#39;s RX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC</name>
+                                <value>48</value>
+                                <description>Select the ADC as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>XIP_STREAM</name>
+                                <value>49</value>
+                                <description>Select the XIP Streaming FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>XIP_QMITX</name>
+                                <value>50</value>
+                                <description>Select XIP_QMITX as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>XIP_QMIRX</name>
+                                <value>51</value>
+                                <description>Select XIP_QMIRX as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HSTX</name>
+                                <value>52</value>
+                                <description>Select HSTX as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CORESIGHT</name>
+                                <value>53</value>
+                                <description>Select CORESIGHT as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SHA256</name>
+                                <value>54</value>
+                                <description>Select SHA256 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TIMER0</name>
+                                <value>59</value>
+                                <description>Select Timer 0 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TIMER1</name>
+                                <value>60</value>
+                                <description>Select Timer 1 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TIMER2</name>
+                                <value>61</value>
+                                <description>Select Timer 2 as TREQ (Optional)</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TIMER3</name>
+                                <value>62</value>
+                                <description>Select Timer 3 as TREQ (Optional)</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PERMANENT</name>
+                                <value>63</value>
+                                <description>Permanent request, for unpaced transfers.</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>CHAIN_TO</name>
+                        <description>When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.
+
+                            Note this field resets to 0, so channels 1 and above will chain to channel 0 by default. Set this field to avoid this behaviour.</description>
+                        <bitRange>[16:13]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>RING_SEL</name>
+                        <description>Select whether RING_SIZE applies to read or write addresses. 
+                            If 0, read addresses are wrapped on a (1 &lt;&lt; RING_SIZE) boundary. If 1, write addresses are wrapped.</description>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>RING_SIZE</name>
+                        <description>Size of address wrap region. If 0, don&#39;t wrap. For values n &gt; 0, only the lower n bits of the address will change. This wraps the address on a (1 &lt;&lt; n) byte boundary, facilitating access to naturally-aligned ring buffers.
+
+                            Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.</description>
+                        <bitRange>[11:8]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>RING_NONE</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>INCR_WRITE_REV</name>
+                        <description>If 1, and INCR_WRITE is 1, the write address is decremented rather than incremented with each transfer.
+
+                            If 1, and INCR_WRITE is 0, this otherwise-unused combination causes the write address to be incremented by twice the transfer size, i.e. skipping over alternate addresses.</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INCR_WRITE</name>
+                        <description>If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.
+
+                            Generally this should be disabled for memory-to-peripheral transfers.</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INCR_READ_REV</name>
+                        <description>If 1, and INCR_READ is 1, the read address is decremented rather than incremented with each transfer.
+
+                            If 1, and INCR_READ is 0, this otherwise-unused combination causes the read address to be incremented by twice the transfer size, i.e. skipping over alternate addresses.</description>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INCR_READ</name>
+                        <description>If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.
+
+                            Generally this should be disabled for peripheral-to-memory transfers.</description>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DATA_SIZE</name>
+                        <description>Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.</description>
+                        <bitRange>[3:2]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>SIZE_BYTE</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SIZE_HALFWORD</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SIZE_WORD</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>HIGH_PRIORITY</name>
+                        <description>HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.
+
+                            This only affects the order in which the DMA schedules channels. The DMA&#39;s bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>EN</name>
+                        <description>DMA Channel Enable. 
+                            When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH7_AL1_CTRL</name>
+                <addressOffset>0x000001d0</addressOffset>
+                <description>Alias for channel 7 CTRL register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH7_AL1_CTRL</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH7_AL1_READ_ADDR</name>
+                <addressOffset>0x000001d4</addressOffset>
+                <description>Alias for channel 7 READ_ADDR register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH7_AL1_READ_ADDR</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH7_AL1_WRITE_ADDR</name>
+                <addressOffset>0x000001d8</addressOffset>
+                <description>Alias for channel 7 WRITE_ADDR register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH7_AL1_WRITE_ADDR</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH7_AL1_TRANS_COUNT_TRIG</name>
+                <addressOffset>0x000001dc</addressOffset>
+                <description>Alias for channel 7 TRANS_COUNT register 
+                    This is a trigger register (0xc). Writing a nonzero value will 
+                    reload the channel counter and start the channel.</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH7_AL1_TRANS_COUNT_TRIG</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH7_AL2_CTRL</name>
+                <addressOffset>0x000001e0</addressOffset>
+                <description>Alias for channel 7 CTRL register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH7_AL2_CTRL</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH7_AL2_TRANS_COUNT</name>
+                <addressOffset>0x000001e4</addressOffset>
+                <description>Alias for channel 7 TRANS_COUNT register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH7_AL2_TRANS_COUNT</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH7_AL2_READ_ADDR</name>
+                <addressOffset>0x000001e8</addressOffset>
+                <description>Alias for channel 7 READ_ADDR register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH7_AL2_READ_ADDR</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH7_AL2_WRITE_ADDR_TRIG</name>
+                <addressOffset>0x000001ec</addressOffset>
+                <description>Alias for channel 7 WRITE_ADDR register 
+                    This is a trigger register (0xc). Writing a nonzero value will 
+                    reload the channel counter and start the channel.</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH7_AL2_WRITE_ADDR_TRIG</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH7_AL3_CTRL</name>
+                <addressOffset>0x000001f0</addressOffset>
+                <description>Alias for channel 7 CTRL register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH7_AL3_CTRL</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH7_AL3_WRITE_ADDR</name>
+                <addressOffset>0x000001f4</addressOffset>
+                <description>Alias for channel 7 WRITE_ADDR register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH7_AL3_WRITE_ADDR</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH7_AL3_TRANS_COUNT</name>
+                <addressOffset>0x000001f8</addressOffset>
+                <description>Alias for channel 7 TRANS_COUNT register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH7_AL3_TRANS_COUNT</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH7_AL3_READ_ADDR_TRIG</name>
+                <addressOffset>0x000001fc</addressOffset>
+                <description>Alias for channel 7 READ_ADDR register 
+                    This is a trigger register (0xc). Writing a nonzero value will 
+                    reload the channel counter and start the channel.</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH7_AL3_READ_ADDR_TRIG</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH8_READ_ADDR</name>
+                <addressOffset>0x00000200</addressOffset>
+                <description>DMA Channel 8 Read Address pointer</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CH8_READ_ADDR</name>
+                        <description>This register updates automatically each time a read completes. The current value is the next address to be read by this channel.</description>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH8_WRITE_ADDR</name>
+                <addressOffset>0x00000204</addressOffset>
+                <description>DMA Channel 8 Write Address pointer</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CH8_WRITE_ADDR</name>
+                        <description>This register updates automatically each time a write completes. The current value is the next address to be written by this channel.</description>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH8_TRANS_COUNT</name>
+                <addressOffset>0x00000208</addressOffset>
+                <description>DMA Channel 8 Transfer Count</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>MODE</name>
+                        <description>When MODE is 0x0, the transfer count decrements with each transfer until 0, and then the channel triggers the next channel indicated by CTRL_CHAIN_TO.
+
+                            When MODE is 0x1, the transfer count decrements with each transfer until 0, and then the channel re-triggers itself, in addition to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an endless ring-buffer DMA with periodic interrupts.
+
+                            When MODE is 0xf, the transfer count does not decrement. The DMA channel performs an endless sequence of transfers, never triggering other channels or raising interrupts, until an ABORT is raised.
+
+                            All other values are reserved.</description>
+                        <bitRange>[31:28]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TRIGGER_SELF</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ENDLESS</name>
+                                <value>15</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>COUNT</name>
+                        <description>28-bit transfer count (256 million transfers maximum).
+
+                            Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).
+
+                            When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.
+
+                            Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.
+
+                            The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD.</description>
+                        <bitRange>[27:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH8_CTRL_TRIG</name>
+                <addressOffset>0x0000020c</addressOffset>
+                <description>DMA Channel 8 Control and Status</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>AHB_ERROR</name>
+                        <description>Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag.</description>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>READ_ERROR</name>
+                        <description>If 1, the channel received a read bus error. Write one to clear. 
+                            READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)</description>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>WRITE_ERROR</name>
+                        <description>If 1, the channel received a write bus error. Write one to clear. 
+                            WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)</description>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>BUSY</name>
+                        <description>This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.
+
+                            To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT.</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SNIFF_EN</name>
+                        <description>If 1, this channel&#39;s data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.
+
+                            This allows checksum to be enabled or disabled on a per-control- block basis.</description>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>BSWAP</name>
+                        <description>Apply byte-swap transformation to DMA data. 
+                            For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.</description>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>IRQ_QUIET</name>
+                        <description>In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.
+
+                            This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.</description>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>TREQ_SEL</name>
+                        <description>Select a Transfer Request signal. 
+                            The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). 
+                            0x0 to 0x3a -&gt; select DREQ n as TREQ</description>
+                        <bitRange>[22:17]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>PIO0_TX0</name>
+                                <value>0</value>
+                                <description>Select PIO0&#39;s TX FIFO 0 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO0_TX1</name>
+                                <value>1</value>
+                                <description>Select PIO0&#39;s TX FIFO 1 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO0_TX2</name>
+                                <value>2</value>
+                                <description>Select PIO0&#39;s TX FIFO 2 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO0_TX3</name>
+                                <value>3</value>
+                                <description>Select PIO0&#39;s TX FIFO 3 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO0_RX0</name>
+                                <value>4</value>
+                                <description>Select PIO0&#39;s RX FIFO 0 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO0_RX1</name>
+                                <value>5</value>
+                                <description>Select PIO0&#39;s RX FIFO 1 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO0_RX2</name>
+                                <value>6</value>
+                                <description>Select PIO0&#39;s RX FIFO 2 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO0_RX3</name>
+                                <value>7</value>
+                                <description>Select PIO0&#39;s RX FIFO 3 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_TX0</name>
+                                <value>8</value>
+                                <description>Select PIO1&#39;s TX FIFO 0 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_TX1</name>
+                                <value>9</value>
+                                <description>Select PIO1&#39;s TX FIFO 1 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_TX2</name>
+                                <value>10</value>
+                                <description>Select PIO1&#39;s TX FIFO 2 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_TX3</name>
+                                <value>11</value>
+                                <description>Select PIO1&#39;s TX FIFO 3 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_RX0</name>
+                                <value>12</value>
+                                <description>Select PIO1&#39;s RX FIFO 0 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_RX1</name>
+                                <value>13</value>
+                                <description>Select PIO1&#39;s RX FIFO 1 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_RX2</name>
+                                <value>14</value>
+                                <description>Select PIO1&#39;s RX FIFO 2 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_RX3</name>
+                                <value>15</value>
+                                <description>Select PIO1&#39;s RX FIFO 3 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO2_TX0</name>
+                                <value>16</value>
+                                <description>Select PIO2&#39;s TX FIFO 0 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO2_TX1</name>
+                                <value>17</value>
+                                <description>Select PIO2&#39;s TX FIFO 1 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO2_TX2</name>
+                                <value>18</value>
+                                <description>Select PIO2&#39;s TX FIFO 2 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO2_TX3</name>
+                                <value>19</value>
+                                <description>Select PIO2&#39;s TX FIFO 3 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO2_RX0</name>
+                                <value>20</value>
+                                <description>Select PIO2&#39;s RX FIFO 0 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO2_RX1</name>
+                                <value>21</value>
+                                <description>Select PIO2&#39;s RX FIFO 1 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO2_RX2</name>
+                                <value>22</value>
+                                <description>Select PIO2&#39;s RX FIFO 2 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO2_RX3</name>
+                                <value>23</value>
+                                <description>Select PIO2&#39;s RX FIFO 3 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SPI0_TX</name>
+                                <value>24</value>
+                                <description>Select SPI0&#39;s TX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SPI0_RX</name>
+                                <value>25</value>
+                                <description>Select SPI0&#39;s RX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SPI1_TX</name>
+                                <value>26</value>
+                                <description>Select SPI1&#39;s TX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SPI1_RX</name>
+                                <value>27</value>
+                                <description>Select SPI1&#39;s RX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UART0_TX</name>
+                                <value>28</value>
+                                <description>Select UART0&#39;s TX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UART0_RX</name>
+                                <value>29</value>
+                                <description>Select UART0&#39;s RX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UART1_TX</name>
+                                <value>30</value>
+                                <description>Select UART1&#39;s TX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UART1_RX</name>
+                                <value>31</value>
+                                <description>Select UART1&#39;s RX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP0</name>
+                                <value>32</value>
+                                <description>Select PWM Counter 0&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP1</name>
+                                <value>33</value>
+                                <description>Select PWM Counter 1&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP2</name>
+                                <value>34</value>
+                                <description>Select PWM Counter 2&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP3</name>
+                                <value>35</value>
+                                <description>Select PWM Counter 3&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP4</name>
+                                <value>36</value>
+                                <description>Select PWM Counter 4&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP5</name>
+                                <value>37</value>
+                                <description>Select PWM Counter 5&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP6</name>
+                                <value>38</value>
+                                <description>Select PWM Counter 6&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP7</name>
+                                <value>39</value>
+                                <description>Select PWM Counter 7&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP8</name>
+                                <value>40</value>
+                                <description>Select PWM Counter 8&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP9</name>
+                                <value>41</value>
+                                <description>Select PWM Counter 9&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP10</name>
+                                <value>42</value>
+                                <description>Select PWM Counter 0&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP11</name>
+                                <value>43</value>
+                                <description>Select PWM Counter 1&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>I2C0_TX</name>
+                                <value>44</value>
+                                <description>Select I2C0&#39;s TX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>I2C0_RX</name>
+                                <value>45</value>
+                                <description>Select I2C0&#39;s RX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>I2C1_TX</name>
+                                <value>46</value>
+                                <description>Select I2C1&#39;s TX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>I2C1_RX</name>
+                                <value>47</value>
+                                <description>Select I2C1&#39;s RX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC</name>
+                                <value>48</value>
+                                <description>Select the ADC as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>XIP_STREAM</name>
+                                <value>49</value>
+                                <description>Select the XIP Streaming FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>XIP_QMITX</name>
+                                <value>50</value>
+                                <description>Select XIP_QMITX as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>XIP_QMIRX</name>
+                                <value>51</value>
+                                <description>Select XIP_QMIRX as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HSTX</name>
+                                <value>52</value>
+                                <description>Select HSTX as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CORESIGHT</name>
+                                <value>53</value>
+                                <description>Select CORESIGHT as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SHA256</name>
+                                <value>54</value>
+                                <description>Select SHA256 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TIMER0</name>
+                                <value>59</value>
+                                <description>Select Timer 0 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TIMER1</name>
+                                <value>60</value>
+                                <description>Select Timer 1 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TIMER2</name>
+                                <value>61</value>
+                                <description>Select Timer 2 as TREQ (Optional)</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TIMER3</name>
+                                <value>62</value>
+                                <description>Select Timer 3 as TREQ (Optional)</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PERMANENT</name>
+                                <value>63</value>
+                                <description>Permanent request, for unpaced transfers.</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>CHAIN_TO</name>
+                        <description>When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.
+
+                            Note this field resets to 0, so channels 1 and above will chain to channel 0 by default. Set this field to avoid this behaviour.</description>
+                        <bitRange>[16:13]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>RING_SEL</name>
+                        <description>Select whether RING_SIZE applies to read or write addresses. 
+                            If 0, read addresses are wrapped on a (1 &lt;&lt; RING_SIZE) boundary. If 1, write addresses are wrapped.</description>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>RING_SIZE</name>
+                        <description>Size of address wrap region. If 0, don&#39;t wrap. For values n &gt; 0, only the lower n bits of the address will change. This wraps the address on a (1 &lt;&lt; n) byte boundary, facilitating access to naturally-aligned ring buffers.
+
+                            Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.</description>
+                        <bitRange>[11:8]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>RING_NONE</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>INCR_WRITE_REV</name>
+                        <description>If 1, and INCR_WRITE is 1, the write address is decremented rather than incremented with each transfer.
+
+                            If 1, and INCR_WRITE is 0, this otherwise-unused combination causes the write address to be incremented by twice the transfer size, i.e. skipping over alternate addresses.</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INCR_WRITE</name>
+                        <description>If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.
+
+                            Generally this should be disabled for memory-to-peripheral transfers.</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INCR_READ_REV</name>
+                        <description>If 1, and INCR_READ is 1, the read address is decremented rather than incremented with each transfer.
+
+                            If 1, and INCR_READ is 0, this otherwise-unused combination causes the read address to be incremented by twice the transfer size, i.e. skipping over alternate addresses.</description>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INCR_READ</name>
+                        <description>If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.
+
+                            Generally this should be disabled for peripheral-to-memory transfers.</description>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DATA_SIZE</name>
+                        <description>Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.</description>
+                        <bitRange>[3:2]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>SIZE_BYTE</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SIZE_HALFWORD</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SIZE_WORD</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>HIGH_PRIORITY</name>
+                        <description>HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.
+
+                            This only affects the order in which the DMA schedules channels. The DMA&#39;s bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>EN</name>
+                        <description>DMA Channel Enable. 
+                            When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH8_AL1_CTRL</name>
+                <addressOffset>0x00000210</addressOffset>
+                <description>Alias for channel 8 CTRL register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH8_AL1_CTRL</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH8_AL1_READ_ADDR</name>
+                <addressOffset>0x00000214</addressOffset>
+                <description>Alias for channel 8 READ_ADDR register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH8_AL1_READ_ADDR</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH8_AL1_WRITE_ADDR</name>
+                <addressOffset>0x00000218</addressOffset>
+                <description>Alias for channel 8 WRITE_ADDR register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH8_AL1_WRITE_ADDR</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH8_AL1_TRANS_COUNT_TRIG</name>
+                <addressOffset>0x0000021c</addressOffset>
+                <description>Alias for channel 8 TRANS_COUNT register 
+                    This is a trigger register (0xc). Writing a nonzero value will 
+                    reload the channel counter and start the channel.</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH8_AL1_TRANS_COUNT_TRIG</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH8_AL2_CTRL</name>
+                <addressOffset>0x00000220</addressOffset>
+                <description>Alias for channel 8 CTRL register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH8_AL2_CTRL</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH8_AL2_TRANS_COUNT</name>
+                <addressOffset>0x00000224</addressOffset>
+                <description>Alias for channel 8 TRANS_COUNT register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH8_AL2_TRANS_COUNT</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH8_AL2_READ_ADDR</name>
+                <addressOffset>0x00000228</addressOffset>
+                <description>Alias for channel 8 READ_ADDR register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH8_AL2_READ_ADDR</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH8_AL2_WRITE_ADDR_TRIG</name>
+                <addressOffset>0x0000022c</addressOffset>
+                <description>Alias for channel 8 WRITE_ADDR register 
+                    This is a trigger register (0xc). Writing a nonzero value will 
+                    reload the channel counter and start the channel.</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH8_AL2_WRITE_ADDR_TRIG</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH8_AL3_CTRL</name>
+                <addressOffset>0x00000230</addressOffset>
+                <description>Alias for channel 8 CTRL register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH8_AL3_CTRL</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH8_AL3_WRITE_ADDR</name>
+                <addressOffset>0x00000234</addressOffset>
+                <description>Alias for channel 8 WRITE_ADDR register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH8_AL3_WRITE_ADDR</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH8_AL3_TRANS_COUNT</name>
+                <addressOffset>0x00000238</addressOffset>
+                <description>Alias for channel 8 TRANS_COUNT register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH8_AL3_TRANS_COUNT</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH8_AL3_READ_ADDR_TRIG</name>
+                <addressOffset>0x0000023c</addressOffset>
+                <description>Alias for channel 8 READ_ADDR register 
+                    This is a trigger register (0xc). Writing a nonzero value will 
+                    reload the channel counter and start the channel.</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH8_AL3_READ_ADDR_TRIG</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH9_READ_ADDR</name>
+                <addressOffset>0x00000240</addressOffset>
+                <description>DMA Channel 9 Read Address pointer</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CH9_READ_ADDR</name>
+                        <description>This register updates automatically each time a read completes. The current value is the next address to be read by this channel.</description>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH9_WRITE_ADDR</name>
+                <addressOffset>0x00000244</addressOffset>
+                <description>DMA Channel 9 Write Address pointer</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CH9_WRITE_ADDR</name>
+                        <description>This register updates automatically each time a write completes. The current value is the next address to be written by this channel.</description>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH9_TRANS_COUNT</name>
+                <addressOffset>0x00000248</addressOffset>
+                <description>DMA Channel 9 Transfer Count</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>MODE</name>
+                        <description>When MODE is 0x0, the transfer count decrements with each transfer until 0, and then the channel triggers the next channel indicated by CTRL_CHAIN_TO.
+
+                            When MODE is 0x1, the transfer count decrements with each transfer until 0, and then the channel re-triggers itself, in addition to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an endless ring-buffer DMA with periodic interrupts.
+
+                            When MODE is 0xf, the transfer count does not decrement. The DMA channel performs an endless sequence of transfers, never triggering other channels or raising interrupts, until an ABORT is raised.
+
+                            All other values are reserved.</description>
+                        <bitRange>[31:28]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TRIGGER_SELF</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ENDLESS</name>
+                                <value>15</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>COUNT</name>
+                        <description>28-bit transfer count (256 million transfers maximum).
+
+                            Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).
+
+                            When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.
+
+                            Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.
+
+                            The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD.</description>
+                        <bitRange>[27:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH9_CTRL_TRIG</name>
+                <addressOffset>0x0000024c</addressOffset>
+                <description>DMA Channel 9 Control and Status</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>AHB_ERROR</name>
+                        <description>Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag.</description>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>READ_ERROR</name>
+                        <description>If 1, the channel received a read bus error. Write one to clear. 
+                            READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)</description>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>WRITE_ERROR</name>
+                        <description>If 1, the channel received a write bus error. Write one to clear. 
+                            WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)</description>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>BUSY</name>
+                        <description>This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.
+
+                            To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT.</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SNIFF_EN</name>
+                        <description>If 1, this channel&#39;s data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.
+
+                            This allows checksum to be enabled or disabled on a per-control- block basis.</description>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>BSWAP</name>
+                        <description>Apply byte-swap transformation to DMA data. 
+                            For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.</description>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>IRQ_QUIET</name>
+                        <description>In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.
+
+                            This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.</description>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>TREQ_SEL</name>
+                        <description>Select a Transfer Request signal. 
+                            The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). 
+                            0x0 to 0x3a -&gt; select DREQ n as TREQ</description>
+                        <bitRange>[22:17]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>PIO0_TX0</name>
+                                <value>0</value>
+                                <description>Select PIO0&#39;s TX FIFO 0 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO0_TX1</name>
+                                <value>1</value>
+                                <description>Select PIO0&#39;s TX FIFO 1 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO0_TX2</name>
+                                <value>2</value>
+                                <description>Select PIO0&#39;s TX FIFO 2 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO0_TX3</name>
+                                <value>3</value>
+                                <description>Select PIO0&#39;s TX FIFO 3 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO0_RX0</name>
+                                <value>4</value>
+                                <description>Select PIO0&#39;s RX FIFO 0 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO0_RX1</name>
+                                <value>5</value>
+                                <description>Select PIO0&#39;s RX FIFO 1 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO0_RX2</name>
+                                <value>6</value>
+                                <description>Select PIO0&#39;s RX FIFO 2 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO0_RX3</name>
+                                <value>7</value>
+                                <description>Select PIO0&#39;s RX FIFO 3 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_TX0</name>
+                                <value>8</value>
+                                <description>Select PIO1&#39;s TX FIFO 0 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_TX1</name>
+                                <value>9</value>
+                                <description>Select PIO1&#39;s TX FIFO 1 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_TX2</name>
+                                <value>10</value>
+                                <description>Select PIO1&#39;s TX FIFO 2 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_TX3</name>
+                                <value>11</value>
+                                <description>Select PIO1&#39;s TX FIFO 3 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_RX0</name>
+                                <value>12</value>
+                                <description>Select PIO1&#39;s RX FIFO 0 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_RX1</name>
+                                <value>13</value>
+                                <description>Select PIO1&#39;s RX FIFO 1 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_RX2</name>
+                                <value>14</value>
+                                <description>Select PIO1&#39;s RX FIFO 2 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_RX3</name>
+                                <value>15</value>
+                                <description>Select PIO1&#39;s RX FIFO 3 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO2_TX0</name>
+                                <value>16</value>
+                                <description>Select PIO2&#39;s TX FIFO 0 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO2_TX1</name>
+                                <value>17</value>
+                                <description>Select PIO2&#39;s TX FIFO 1 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO2_TX2</name>
+                                <value>18</value>
+                                <description>Select PIO2&#39;s TX FIFO 2 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO2_TX3</name>
+                                <value>19</value>
+                                <description>Select PIO2&#39;s TX FIFO 3 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO2_RX0</name>
+                                <value>20</value>
+                                <description>Select PIO2&#39;s RX FIFO 0 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO2_RX1</name>
+                                <value>21</value>
+                                <description>Select PIO2&#39;s RX FIFO 1 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO2_RX2</name>
+                                <value>22</value>
+                                <description>Select PIO2&#39;s RX FIFO 2 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO2_RX3</name>
+                                <value>23</value>
+                                <description>Select PIO2&#39;s RX FIFO 3 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SPI0_TX</name>
+                                <value>24</value>
+                                <description>Select SPI0&#39;s TX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SPI0_RX</name>
+                                <value>25</value>
+                                <description>Select SPI0&#39;s RX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SPI1_TX</name>
+                                <value>26</value>
+                                <description>Select SPI1&#39;s TX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SPI1_RX</name>
+                                <value>27</value>
+                                <description>Select SPI1&#39;s RX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UART0_TX</name>
+                                <value>28</value>
+                                <description>Select UART0&#39;s TX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UART0_RX</name>
+                                <value>29</value>
+                                <description>Select UART0&#39;s RX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UART1_TX</name>
+                                <value>30</value>
+                                <description>Select UART1&#39;s TX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UART1_RX</name>
+                                <value>31</value>
+                                <description>Select UART1&#39;s RX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP0</name>
+                                <value>32</value>
+                                <description>Select PWM Counter 0&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP1</name>
+                                <value>33</value>
+                                <description>Select PWM Counter 1&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP2</name>
+                                <value>34</value>
+                                <description>Select PWM Counter 2&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP3</name>
+                                <value>35</value>
+                                <description>Select PWM Counter 3&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP4</name>
+                                <value>36</value>
+                                <description>Select PWM Counter 4&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP5</name>
+                                <value>37</value>
+                                <description>Select PWM Counter 5&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP6</name>
+                                <value>38</value>
+                                <description>Select PWM Counter 6&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP7</name>
+                                <value>39</value>
+                                <description>Select PWM Counter 7&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP8</name>
+                                <value>40</value>
+                                <description>Select PWM Counter 8&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP9</name>
+                                <value>41</value>
+                                <description>Select PWM Counter 9&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP10</name>
+                                <value>42</value>
+                                <description>Select PWM Counter 0&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP11</name>
+                                <value>43</value>
+                                <description>Select PWM Counter 1&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>I2C0_TX</name>
+                                <value>44</value>
+                                <description>Select I2C0&#39;s TX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>I2C0_RX</name>
+                                <value>45</value>
+                                <description>Select I2C0&#39;s RX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>I2C1_TX</name>
+                                <value>46</value>
+                                <description>Select I2C1&#39;s TX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>I2C1_RX</name>
+                                <value>47</value>
+                                <description>Select I2C1&#39;s RX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC</name>
+                                <value>48</value>
+                                <description>Select the ADC as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>XIP_STREAM</name>
+                                <value>49</value>
+                                <description>Select the XIP Streaming FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>XIP_QMITX</name>
+                                <value>50</value>
+                                <description>Select XIP_QMITX as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>XIP_QMIRX</name>
+                                <value>51</value>
+                                <description>Select XIP_QMIRX as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HSTX</name>
+                                <value>52</value>
+                                <description>Select HSTX as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CORESIGHT</name>
+                                <value>53</value>
+                                <description>Select CORESIGHT as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SHA256</name>
+                                <value>54</value>
+                                <description>Select SHA256 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TIMER0</name>
+                                <value>59</value>
+                                <description>Select Timer 0 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TIMER1</name>
+                                <value>60</value>
+                                <description>Select Timer 1 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TIMER2</name>
+                                <value>61</value>
+                                <description>Select Timer 2 as TREQ (Optional)</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TIMER3</name>
+                                <value>62</value>
+                                <description>Select Timer 3 as TREQ (Optional)</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PERMANENT</name>
+                                <value>63</value>
+                                <description>Permanent request, for unpaced transfers.</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>CHAIN_TO</name>
+                        <description>When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.
+
+                            Note this field resets to 0, so channels 1 and above will chain to channel 0 by default. Set this field to avoid this behaviour.</description>
+                        <bitRange>[16:13]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>RING_SEL</name>
+                        <description>Select whether RING_SIZE applies to read or write addresses. 
+                            If 0, read addresses are wrapped on a (1 &lt;&lt; RING_SIZE) boundary. If 1, write addresses are wrapped.</description>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>RING_SIZE</name>
+                        <description>Size of address wrap region. If 0, don&#39;t wrap. For values n &gt; 0, only the lower n bits of the address will change. This wraps the address on a (1 &lt;&lt; n) byte boundary, facilitating access to naturally-aligned ring buffers.
+
+                            Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.</description>
+                        <bitRange>[11:8]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>RING_NONE</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>INCR_WRITE_REV</name>
+                        <description>If 1, and INCR_WRITE is 1, the write address is decremented rather than incremented with each transfer.
+
+                            If 1, and INCR_WRITE is 0, this otherwise-unused combination causes the write address to be incremented by twice the transfer size, i.e. skipping over alternate addresses.</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INCR_WRITE</name>
+                        <description>If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.
+
+                            Generally this should be disabled for memory-to-peripheral transfers.</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INCR_READ_REV</name>
+                        <description>If 1, and INCR_READ is 1, the read address is decremented rather than incremented with each transfer.
+
+                            If 1, and INCR_READ is 0, this otherwise-unused combination causes the read address to be incremented by twice the transfer size, i.e. skipping over alternate addresses.</description>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INCR_READ</name>
+                        <description>If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.
+
+                            Generally this should be disabled for peripheral-to-memory transfers.</description>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DATA_SIZE</name>
+                        <description>Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.</description>
+                        <bitRange>[3:2]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>SIZE_BYTE</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SIZE_HALFWORD</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SIZE_WORD</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>HIGH_PRIORITY</name>
+                        <description>HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.
+
+                            This only affects the order in which the DMA schedules channels. The DMA&#39;s bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>EN</name>
+                        <description>DMA Channel Enable. 
+                            When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH9_AL1_CTRL</name>
+                <addressOffset>0x00000250</addressOffset>
+                <description>Alias for channel 9 CTRL register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH9_AL1_CTRL</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH9_AL1_READ_ADDR</name>
+                <addressOffset>0x00000254</addressOffset>
+                <description>Alias for channel 9 READ_ADDR register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH9_AL1_READ_ADDR</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH9_AL1_WRITE_ADDR</name>
+                <addressOffset>0x00000258</addressOffset>
+                <description>Alias for channel 9 WRITE_ADDR register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH9_AL1_WRITE_ADDR</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH9_AL1_TRANS_COUNT_TRIG</name>
+                <addressOffset>0x0000025c</addressOffset>
+                <description>Alias for channel 9 TRANS_COUNT register 
+                    This is a trigger register (0xc). Writing a nonzero value will 
+                    reload the channel counter and start the channel.</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH9_AL1_TRANS_COUNT_TRIG</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH9_AL2_CTRL</name>
+                <addressOffset>0x00000260</addressOffset>
+                <description>Alias for channel 9 CTRL register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH9_AL2_CTRL</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH9_AL2_TRANS_COUNT</name>
+                <addressOffset>0x00000264</addressOffset>
+                <description>Alias for channel 9 TRANS_COUNT register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH9_AL2_TRANS_COUNT</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH9_AL2_READ_ADDR</name>
+                <addressOffset>0x00000268</addressOffset>
+                <description>Alias for channel 9 READ_ADDR register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH9_AL2_READ_ADDR</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH9_AL2_WRITE_ADDR_TRIG</name>
+                <addressOffset>0x0000026c</addressOffset>
+                <description>Alias for channel 9 WRITE_ADDR register 
+                    This is a trigger register (0xc). Writing a nonzero value will 
+                    reload the channel counter and start the channel.</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH9_AL2_WRITE_ADDR_TRIG</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH9_AL3_CTRL</name>
+                <addressOffset>0x00000270</addressOffset>
+                <description>Alias for channel 9 CTRL register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH9_AL3_CTRL</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH9_AL3_WRITE_ADDR</name>
+                <addressOffset>0x00000274</addressOffset>
+                <description>Alias for channel 9 WRITE_ADDR register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH9_AL3_WRITE_ADDR</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH9_AL3_TRANS_COUNT</name>
+                <addressOffset>0x00000278</addressOffset>
+                <description>Alias for channel 9 TRANS_COUNT register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH9_AL3_TRANS_COUNT</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH9_AL3_READ_ADDR_TRIG</name>
+                <addressOffset>0x0000027c</addressOffset>
+                <description>Alias for channel 9 READ_ADDR register 
+                    This is a trigger register (0xc). Writing a nonzero value will 
+                    reload the channel counter and start the channel.</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH9_AL3_READ_ADDR_TRIG</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH10_READ_ADDR</name>
+                <addressOffset>0x00000280</addressOffset>
+                <description>DMA Channel 10 Read Address pointer</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CH10_READ_ADDR</name>
+                        <description>This register updates automatically each time a read completes. The current value is the next address to be read by this channel.</description>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH10_WRITE_ADDR</name>
+                <addressOffset>0x00000284</addressOffset>
+                <description>DMA Channel 10 Write Address pointer</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CH10_WRITE_ADDR</name>
+                        <description>This register updates automatically each time a write completes. The current value is the next address to be written by this channel.</description>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH10_TRANS_COUNT</name>
+                <addressOffset>0x00000288</addressOffset>
+                <description>DMA Channel 10 Transfer Count</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>MODE</name>
+                        <description>When MODE is 0x0, the transfer count decrements with each transfer until 0, and then the channel triggers the next channel indicated by CTRL_CHAIN_TO.
+
+                            When MODE is 0x1, the transfer count decrements with each transfer until 0, and then the channel re-triggers itself, in addition to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an endless ring-buffer DMA with periodic interrupts.
+
+                            When MODE is 0xf, the transfer count does not decrement. The DMA channel performs an endless sequence of transfers, never triggering other channels or raising interrupts, until an ABORT is raised.
+
+                            All other values are reserved.</description>
+                        <bitRange>[31:28]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TRIGGER_SELF</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ENDLESS</name>
+                                <value>15</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>COUNT</name>
+                        <description>28-bit transfer count (256 million transfers maximum).
+
+                            Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).
+
+                            When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.
+
+                            Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.
+
+                            The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD.</description>
+                        <bitRange>[27:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH10_CTRL_TRIG</name>
+                <addressOffset>0x0000028c</addressOffset>
+                <description>DMA Channel 10 Control and Status</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>AHB_ERROR</name>
+                        <description>Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag.</description>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>READ_ERROR</name>
+                        <description>If 1, the channel received a read bus error. Write one to clear. 
+                            READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)</description>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>WRITE_ERROR</name>
+                        <description>If 1, the channel received a write bus error. Write one to clear. 
+                            WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)</description>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>BUSY</name>
+                        <description>This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.
+
+                            To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT.</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SNIFF_EN</name>
+                        <description>If 1, this channel&#39;s data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.
+
+                            This allows checksum to be enabled or disabled on a per-control- block basis.</description>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>BSWAP</name>
+                        <description>Apply byte-swap transformation to DMA data. 
+                            For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.</description>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>IRQ_QUIET</name>
+                        <description>In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.
+
+                            This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.</description>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>TREQ_SEL</name>
+                        <description>Select a Transfer Request signal. 
+                            The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). 
+                            0x0 to 0x3a -&gt; select DREQ n as TREQ</description>
+                        <bitRange>[22:17]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>PIO0_TX0</name>
+                                <value>0</value>
+                                <description>Select PIO0&#39;s TX FIFO 0 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO0_TX1</name>
+                                <value>1</value>
+                                <description>Select PIO0&#39;s TX FIFO 1 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO0_TX2</name>
+                                <value>2</value>
+                                <description>Select PIO0&#39;s TX FIFO 2 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO0_TX3</name>
+                                <value>3</value>
+                                <description>Select PIO0&#39;s TX FIFO 3 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO0_RX0</name>
+                                <value>4</value>
+                                <description>Select PIO0&#39;s RX FIFO 0 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO0_RX1</name>
+                                <value>5</value>
+                                <description>Select PIO0&#39;s RX FIFO 1 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO0_RX2</name>
+                                <value>6</value>
+                                <description>Select PIO0&#39;s RX FIFO 2 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO0_RX3</name>
+                                <value>7</value>
+                                <description>Select PIO0&#39;s RX FIFO 3 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_TX0</name>
+                                <value>8</value>
+                                <description>Select PIO1&#39;s TX FIFO 0 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_TX1</name>
+                                <value>9</value>
+                                <description>Select PIO1&#39;s TX FIFO 1 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_TX2</name>
+                                <value>10</value>
+                                <description>Select PIO1&#39;s TX FIFO 2 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_TX3</name>
+                                <value>11</value>
+                                <description>Select PIO1&#39;s TX FIFO 3 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_RX0</name>
+                                <value>12</value>
+                                <description>Select PIO1&#39;s RX FIFO 0 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_RX1</name>
+                                <value>13</value>
+                                <description>Select PIO1&#39;s RX FIFO 1 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_RX2</name>
+                                <value>14</value>
+                                <description>Select PIO1&#39;s RX FIFO 2 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_RX3</name>
+                                <value>15</value>
+                                <description>Select PIO1&#39;s RX FIFO 3 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO2_TX0</name>
+                                <value>16</value>
+                                <description>Select PIO2&#39;s TX FIFO 0 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO2_TX1</name>
+                                <value>17</value>
+                                <description>Select PIO2&#39;s TX FIFO 1 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO2_TX2</name>
+                                <value>18</value>
+                                <description>Select PIO2&#39;s TX FIFO 2 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO2_TX3</name>
+                                <value>19</value>
+                                <description>Select PIO2&#39;s TX FIFO 3 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO2_RX0</name>
+                                <value>20</value>
+                                <description>Select PIO2&#39;s RX FIFO 0 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO2_RX1</name>
+                                <value>21</value>
+                                <description>Select PIO2&#39;s RX FIFO 1 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO2_RX2</name>
+                                <value>22</value>
+                                <description>Select PIO2&#39;s RX FIFO 2 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO2_RX3</name>
+                                <value>23</value>
+                                <description>Select PIO2&#39;s RX FIFO 3 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SPI0_TX</name>
+                                <value>24</value>
+                                <description>Select SPI0&#39;s TX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SPI0_RX</name>
+                                <value>25</value>
+                                <description>Select SPI0&#39;s RX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SPI1_TX</name>
+                                <value>26</value>
+                                <description>Select SPI1&#39;s TX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SPI1_RX</name>
+                                <value>27</value>
+                                <description>Select SPI1&#39;s RX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UART0_TX</name>
+                                <value>28</value>
+                                <description>Select UART0&#39;s TX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UART0_RX</name>
+                                <value>29</value>
+                                <description>Select UART0&#39;s RX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UART1_TX</name>
+                                <value>30</value>
+                                <description>Select UART1&#39;s TX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UART1_RX</name>
+                                <value>31</value>
+                                <description>Select UART1&#39;s RX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP0</name>
+                                <value>32</value>
+                                <description>Select PWM Counter 0&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP1</name>
+                                <value>33</value>
+                                <description>Select PWM Counter 1&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP2</name>
+                                <value>34</value>
+                                <description>Select PWM Counter 2&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP3</name>
+                                <value>35</value>
+                                <description>Select PWM Counter 3&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP4</name>
+                                <value>36</value>
+                                <description>Select PWM Counter 4&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP5</name>
+                                <value>37</value>
+                                <description>Select PWM Counter 5&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP6</name>
+                                <value>38</value>
+                                <description>Select PWM Counter 6&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP7</name>
+                                <value>39</value>
+                                <description>Select PWM Counter 7&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP8</name>
+                                <value>40</value>
+                                <description>Select PWM Counter 8&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP9</name>
+                                <value>41</value>
+                                <description>Select PWM Counter 9&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP10</name>
+                                <value>42</value>
+                                <description>Select PWM Counter 0&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP11</name>
+                                <value>43</value>
+                                <description>Select PWM Counter 1&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>I2C0_TX</name>
+                                <value>44</value>
+                                <description>Select I2C0&#39;s TX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>I2C0_RX</name>
+                                <value>45</value>
+                                <description>Select I2C0&#39;s RX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>I2C1_TX</name>
+                                <value>46</value>
+                                <description>Select I2C1&#39;s TX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>I2C1_RX</name>
+                                <value>47</value>
+                                <description>Select I2C1&#39;s RX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC</name>
+                                <value>48</value>
+                                <description>Select the ADC as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>XIP_STREAM</name>
+                                <value>49</value>
+                                <description>Select the XIP Streaming FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>XIP_QMITX</name>
+                                <value>50</value>
+                                <description>Select XIP_QMITX as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>XIP_QMIRX</name>
+                                <value>51</value>
+                                <description>Select XIP_QMIRX as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HSTX</name>
+                                <value>52</value>
+                                <description>Select HSTX as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CORESIGHT</name>
+                                <value>53</value>
+                                <description>Select CORESIGHT as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SHA256</name>
+                                <value>54</value>
+                                <description>Select SHA256 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TIMER0</name>
+                                <value>59</value>
+                                <description>Select Timer 0 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TIMER1</name>
+                                <value>60</value>
+                                <description>Select Timer 1 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TIMER2</name>
+                                <value>61</value>
+                                <description>Select Timer 2 as TREQ (Optional)</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TIMER3</name>
+                                <value>62</value>
+                                <description>Select Timer 3 as TREQ (Optional)</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PERMANENT</name>
+                                <value>63</value>
+                                <description>Permanent request, for unpaced transfers.</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>CHAIN_TO</name>
+                        <description>When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.
+
+                            Note this field resets to 0, so channels 1 and above will chain to channel 0 by default. Set this field to avoid this behaviour.</description>
+                        <bitRange>[16:13]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>RING_SEL</name>
+                        <description>Select whether RING_SIZE applies to read or write addresses. 
+                            If 0, read addresses are wrapped on a (1 &lt;&lt; RING_SIZE) boundary. If 1, write addresses are wrapped.</description>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>RING_SIZE</name>
+                        <description>Size of address wrap region. If 0, don&#39;t wrap. For values n &gt; 0, only the lower n bits of the address will change. This wraps the address on a (1 &lt;&lt; n) byte boundary, facilitating access to naturally-aligned ring buffers.
+
+                            Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.</description>
+                        <bitRange>[11:8]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>RING_NONE</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>INCR_WRITE_REV</name>
+                        <description>If 1, and INCR_WRITE is 1, the write address is decremented rather than incremented with each transfer.
+
+                            If 1, and INCR_WRITE is 0, this otherwise-unused combination causes the write address to be incremented by twice the transfer size, i.e. skipping over alternate addresses.</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INCR_WRITE</name>
+                        <description>If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.
+
+                            Generally this should be disabled for memory-to-peripheral transfers.</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INCR_READ_REV</name>
+                        <description>If 1, and INCR_READ is 1, the read address is decremented rather than incremented with each transfer.
+
+                            If 1, and INCR_READ is 0, this otherwise-unused combination causes the read address to be incremented by twice the transfer size, i.e. skipping over alternate addresses.</description>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INCR_READ</name>
+                        <description>If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.
+
+                            Generally this should be disabled for peripheral-to-memory transfers.</description>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DATA_SIZE</name>
+                        <description>Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.</description>
+                        <bitRange>[3:2]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>SIZE_BYTE</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SIZE_HALFWORD</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SIZE_WORD</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>HIGH_PRIORITY</name>
+                        <description>HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.
+
+                            This only affects the order in which the DMA schedules channels. The DMA&#39;s bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>EN</name>
+                        <description>DMA Channel Enable. 
+                            When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH10_AL1_CTRL</name>
+                <addressOffset>0x00000290</addressOffset>
+                <description>Alias for channel 10 CTRL register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH10_AL1_CTRL</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH10_AL1_READ_ADDR</name>
+                <addressOffset>0x00000294</addressOffset>
+                <description>Alias for channel 10 READ_ADDR register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH10_AL1_READ_ADDR</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH10_AL1_WRITE_ADDR</name>
+                <addressOffset>0x00000298</addressOffset>
+                <description>Alias for channel 10 WRITE_ADDR register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH10_AL1_WRITE_ADDR</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH10_AL1_TRANS_COUNT_TRIG</name>
+                <addressOffset>0x0000029c</addressOffset>
+                <description>Alias for channel 10 TRANS_COUNT register 
+                    This is a trigger register (0xc). Writing a nonzero value will 
+                    reload the channel counter and start the channel.</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH10_AL1_TRANS_COUNT_TRIG</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH10_AL2_CTRL</name>
+                <addressOffset>0x000002a0</addressOffset>
+                <description>Alias for channel 10 CTRL register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH10_AL2_CTRL</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH10_AL2_TRANS_COUNT</name>
+                <addressOffset>0x000002a4</addressOffset>
+                <description>Alias for channel 10 TRANS_COUNT register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH10_AL2_TRANS_COUNT</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH10_AL2_READ_ADDR</name>
+                <addressOffset>0x000002a8</addressOffset>
+                <description>Alias for channel 10 READ_ADDR register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH10_AL2_READ_ADDR</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH10_AL2_WRITE_ADDR_TRIG</name>
+                <addressOffset>0x000002ac</addressOffset>
+                <description>Alias for channel 10 WRITE_ADDR register 
+                    This is a trigger register (0xc). Writing a nonzero value will 
+                    reload the channel counter and start the channel.</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH10_AL2_WRITE_ADDR_TRIG</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH10_AL3_CTRL</name>
+                <addressOffset>0x000002b0</addressOffset>
+                <description>Alias for channel 10 CTRL register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH10_AL3_CTRL</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH10_AL3_WRITE_ADDR</name>
+                <addressOffset>0x000002b4</addressOffset>
+                <description>Alias for channel 10 WRITE_ADDR register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH10_AL3_WRITE_ADDR</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH10_AL3_TRANS_COUNT</name>
+                <addressOffset>0x000002b8</addressOffset>
+                <description>Alias for channel 10 TRANS_COUNT register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH10_AL3_TRANS_COUNT</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH10_AL3_READ_ADDR_TRIG</name>
+                <addressOffset>0x000002bc</addressOffset>
+                <description>Alias for channel 10 READ_ADDR register 
+                    This is a trigger register (0xc). Writing a nonzero value will 
+                    reload the channel counter and start the channel.</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH10_AL3_READ_ADDR_TRIG</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH11_READ_ADDR</name>
+                <addressOffset>0x000002c0</addressOffset>
+                <description>DMA Channel 11 Read Address pointer</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CH11_READ_ADDR</name>
+                        <description>This register updates automatically each time a read completes. The current value is the next address to be read by this channel.</description>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH11_WRITE_ADDR</name>
+                <addressOffset>0x000002c4</addressOffset>
+                <description>DMA Channel 11 Write Address pointer</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CH11_WRITE_ADDR</name>
+                        <description>This register updates automatically each time a write completes. The current value is the next address to be written by this channel.</description>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH11_TRANS_COUNT</name>
+                <addressOffset>0x000002c8</addressOffset>
+                <description>DMA Channel 11 Transfer Count</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>MODE</name>
+                        <description>When MODE is 0x0, the transfer count decrements with each transfer until 0, and then the channel triggers the next channel indicated by CTRL_CHAIN_TO.
+
+                            When MODE is 0x1, the transfer count decrements with each transfer until 0, and then the channel re-triggers itself, in addition to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an endless ring-buffer DMA with periodic interrupts.
+
+                            When MODE is 0xf, the transfer count does not decrement. The DMA channel performs an endless sequence of transfers, never triggering other channels or raising interrupts, until an ABORT is raised.
+
+                            All other values are reserved.</description>
+                        <bitRange>[31:28]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TRIGGER_SELF</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ENDLESS</name>
+                                <value>15</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>COUNT</name>
+                        <description>28-bit transfer count (256 million transfers maximum).
+
+                            Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).
+
+                            When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.
+
+                            Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.
+
+                            The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD.</description>
+                        <bitRange>[27:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH11_CTRL_TRIG</name>
+                <addressOffset>0x000002cc</addressOffset>
+                <description>DMA Channel 11 Control and Status</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>AHB_ERROR</name>
+                        <description>Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag.</description>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>READ_ERROR</name>
+                        <description>If 1, the channel received a read bus error. Write one to clear. 
+                            READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)</description>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>WRITE_ERROR</name>
+                        <description>If 1, the channel received a write bus error. Write one to clear. 
+                            WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)</description>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>BUSY</name>
+                        <description>This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.
+
+                            To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT.</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SNIFF_EN</name>
+                        <description>If 1, this channel&#39;s data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.
+
+                            This allows checksum to be enabled or disabled on a per-control- block basis.</description>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>BSWAP</name>
+                        <description>Apply byte-swap transformation to DMA data. 
+                            For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.</description>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>IRQ_QUIET</name>
+                        <description>In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.
+
+                            This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.</description>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>TREQ_SEL</name>
+                        <description>Select a Transfer Request signal. 
+                            The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). 
+                            0x0 to 0x3a -&gt; select DREQ n as TREQ</description>
+                        <bitRange>[22:17]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>PIO0_TX0</name>
+                                <value>0</value>
+                                <description>Select PIO0&#39;s TX FIFO 0 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO0_TX1</name>
+                                <value>1</value>
+                                <description>Select PIO0&#39;s TX FIFO 1 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO0_TX2</name>
+                                <value>2</value>
+                                <description>Select PIO0&#39;s TX FIFO 2 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO0_TX3</name>
+                                <value>3</value>
+                                <description>Select PIO0&#39;s TX FIFO 3 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO0_RX0</name>
+                                <value>4</value>
+                                <description>Select PIO0&#39;s RX FIFO 0 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO0_RX1</name>
+                                <value>5</value>
+                                <description>Select PIO0&#39;s RX FIFO 1 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO0_RX2</name>
+                                <value>6</value>
+                                <description>Select PIO0&#39;s RX FIFO 2 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO0_RX3</name>
+                                <value>7</value>
+                                <description>Select PIO0&#39;s RX FIFO 3 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_TX0</name>
+                                <value>8</value>
+                                <description>Select PIO1&#39;s TX FIFO 0 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_TX1</name>
+                                <value>9</value>
+                                <description>Select PIO1&#39;s TX FIFO 1 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_TX2</name>
+                                <value>10</value>
+                                <description>Select PIO1&#39;s TX FIFO 2 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_TX3</name>
+                                <value>11</value>
+                                <description>Select PIO1&#39;s TX FIFO 3 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_RX0</name>
+                                <value>12</value>
+                                <description>Select PIO1&#39;s RX FIFO 0 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_RX1</name>
+                                <value>13</value>
+                                <description>Select PIO1&#39;s RX FIFO 1 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_RX2</name>
+                                <value>14</value>
+                                <description>Select PIO1&#39;s RX FIFO 2 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_RX3</name>
+                                <value>15</value>
+                                <description>Select PIO1&#39;s RX FIFO 3 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO2_TX0</name>
+                                <value>16</value>
+                                <description>Select PIO2&#39;s TX FIFO 0 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO2_TX1</name>
+                                <value>17</value>
+                                <description>Select PIO2&#39;s TX FIFO 1 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO2_TX2</name>
+                                <value>18</value>
+                                <description>Select PIO2&#39;s TX FIFO 2 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO2_TX3</name>
+                                <value>19</value>
+                                <description>Select PIO2&#39;s TX FIFO 3 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO2_RX0</name>
+                                <value>20</value>
+                                <description>Select PIO2&#39;s RX FIFO 0 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO2_RX1</name>
+                                <value>21</value>
+                                <description>Select PIO2&#39;s RX FIFO 1 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO2_RX2</name>
+                                <value>22</value>
+                                <description>Select PIO2&#39;s RX FIFO 2 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO2_RX3</name>
+                                <value>23</value>
+                                <description>Select PIO2&#39;s RX FIFO 3 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SPI0_TX</name>
+                                <value>24</value>
+                                <description>Select SPI0&#39;s TX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SPI0_RX</name>
+                                <value>25</value>
+                                <description>Select SPI0&#39;s RX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SPI1_TX</name>
+                                <value>26</value>
+                                <description>Select SPI1&#39;s TX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SPI1_RX</name>
+                                <value>27</value>
+                                <description>Select SPI1&#39;s RX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UART0_TX</name>
+                                <value>28</value>
+                                <description>Select UART0&#39;s TX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UART0_RX</name>
+                                <value>29</value>
+                                <description>Select UART0&#39;s RX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UART1_TX</name>
+                                <value>30</value>
+                                <description>Select UART1&#39;s TX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UART1_RX</name>
+                                <value>31</value>
+                                <description>Select UART1&#39;s RX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP0</name>
+                                <value>32</value>
+                                <description>Select PWM Counter 0&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP1</name>
+                                <value>33</value>
+                                <description>Select PWM Counter 1&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP2</name>
+                                <value>34</value>
+                                <description>Select PWM Counter 2&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP3</name>
+                                <value>35</value>
+                                <description>Select PWM Counter 3&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP4</name>
+                                <value>36</value>
+                                <description>Select PWM Counter 4&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP5</name>
+                                <value>37</value>
+                                <description>Select PWM Counter 5&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP6</name>
+                                <value>38</value>
+                                <description>Select PWM Counter 6&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP7</name>
+                                <value>39</value>
+                                <description>Select PWM Counter 7&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP8</name>
+                                <value>40</value>
+                                <description>Select PWM Counter 8&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP9</name>
+                                <value>41</value>
+                                <description>Select PWM Counter 9&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP10</name>
+                                <value>42</value>
+                                <description>Select PWM Counter 0&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP11</name>
+                                <value>43</value>
+                                <description>Select PWM Counter 1&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>I2C0_TX</name>
+                                <value>44</value>
+                                <description>Select I2C0&#39;s TX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>I2C0_RX</name>
+                                <value>45</value>
+                                <description>Select I2C0&#39;s RX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>I2C1_TX</name>
+                                <value>46</value>
+                                <description>Select I2C1&#39;s TX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>I2C1_RX</name>
+                                <value>47</value>
+                                <description>Select I2C1&#39;s RX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC</name>
+                                <value>48</value>
+                                <description>Select the ADC as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>XIP_STREAM</name>
+                                <value>49</value>
+                                <description>Select the XIP Streaming FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>XIP_QMITX</name>
+                                <value>50</value>
+                                <description>Select XIP_QMITX as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>XIP_QMIRX</name>
+                                <value>51</value>
+                                <description>Select XIP_QMIRX as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HSTX</name>
+                                <value>52</value>
+                                <description>Select HSTX as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CORESIGHT</name>
+                                <value>53</value>
+                                <description>Select CORESIGHT as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SHA256</name>
+                                <value>54</value>
+                                <description>Select SHA256 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TIMER0</name>
+                                <value>59</value>
+                                <description>Select Timer 0 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TIMER1</name>
+                                <value>60</value>
+                                <description>Select Timer 1 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TIMER2</name>
+                                <value>61</value>
+                                <description>Select Timer 2 as TREQ (Optional)</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TIMER3</name>
+                                <value>62</value>
+                                <description>Select Timer 3 as TREQ (Optional)</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PERMANENT</name>
+                                <value>63</value>
+                                <description>Permanent request, for unpaced transfers.</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>CHAIN_TO</name>
+                        <description>When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.
+
+                            Note this field resets to 0, so channels 1 and above will chain to channel 0 by default. Set this field to avoid this behaviour.</description>
+                        <bitRange>[16:13]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>RING_SEL</name>
+                        <description>Select whether RING_SIZE applies to read or write addresses. 
+                            If 0, read addresses are wrapped on a (1 &lt;&lt; RING_SIZE) boundary. If 1, write addresses are wrapped.</description>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>RING_SIZE</name>
+                        <description>Size of address wrap region. If 0, don&#39;t wrap. For values n &gt; 0, only the lower n bits of the address will change. This wraps the address on a (1 &lt;&lt; n) byte boundary, facilitating access to naturally-aligned ring buffers.
+
+                            Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.</description>
+                        <bitRange>[11:8]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>RING_NONE</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>INCR_WRITE_REV</name>
+                        <description>If 1, and INCR_WRITE is 1, the write address is decremented rather than incremented with each transfer.
+
+                            If 1, and INCR_WRITE is 0, this otherwise-unused combination causes the write address to be incremented by twice the transfer size, i.e. skipping over alternate addresses.</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INCR_WRITE</name>
+                        <description>If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.
+
+                            Generally this should be disabled for memory-to-peripheral transfers.</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INCR_READ_REV</name>
+                        <description>If 1, and INCR_READ is 1, the read address is decremented rather than incremented with each transfer.
+
+                            If 1, and INCR_READ is 0, this otherwise-unused combination causes the read address to be incremented by twice the transfer size, i.e. skipping over alternate addresses.</description>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INCR_READ</name>
+                        <description>If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.
+
+                            Generally this should be disabled for peripheral-to-memory transfers.</description>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DATA_SIZE</name>
+                        <description>Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.</description>
+                        <bitRange>[3:2]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>SIZE_BYTE</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SIZE_HALFWORD</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SIZE_WORD</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>HIGH_PRIORITY</name>
+                        <description>HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.
+
+                            This only affects the order in which the DMA schedules channels. The DMA&#39;s bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>EN</name>
+                        <description>DMA Channel Enable. 
+                            When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH11_AL1_CTRL</name>
+                <addressOffset>0x000002d0</addressOffset>
+                <description>Alias for channel 11 CTRL register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH11_AL1_CTRL</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH11_AL1_READ_ADDR</name>
+                <addressOffset>0x000002d4</addressOffset>
+                <description>Alias for channel 11 READ_ADDR register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH11_AL1_READ_ADDR</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH11_AL1_WRITE_ADDR</name>
+                <addressOffset>0x000002d8</addressOffset>
+                <description>Alias for channel 11 WRITE_ADDR register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH11_AL1_WRITE_ADDR</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH11_AL1_TRANS_COUNT_TRIG</name>
+                <addressOffset>0x000002dc</addressOffset>
+                <description>Alias for channel 11 TRANS_COUNT register 
+                    This is a trigger register (0xc). Writing a nonzero value will 
+                    reload the channel counter and start the channel.</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH11_AL1_TRANS_COUNT_TRIG</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH11_AL2_CTRL</name>
+                <addressOffset>0x000002e0</addressOffset>
+                <description>Alias for channel 11 CTRL register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH11_AL2_CTRL</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH11_AL2_TRANS_COUNT</name>
+                <addressOffset>0x000002e4</addressOffset>
+                <description>Alias for channel 11 TRANS_COUNT register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH11_AL2_TRANS_COUNT</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH11_AL2_READ_ADDR</name>
+                <addressOffset>0x000002e8</addressOffset>
+                <description>Alias for channel 11 READ_ADDR register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH11_AL2_READ_ADDR</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH11_AL2_WRITE_ADDR_TRIG</name>
+                <addressOffset>0x000002ec</addressOffset>
+                <description>Alias for channel 11 WRITE_ADDR register 
+                    This is a trigger register (0xc). Writing a nonzero value will 
+                    reload the channel counter and start the channel.</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH11_AL2_WRITE_ADDR_TRIG</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH11_AL3_CTRL</name>
+                <addressOffset>0x000002f0</addressOffset>
+                <description>Alias for channel 11 CTRL register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH11_AL3_CTRL</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH11_AL3_WRITE_ADDR</name>
+                <addressOffset>0x000002f4</addressOffset>
+                <description>Alias for channel 11 WRITE_ADDR register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH11_AL3_WRITE_ADDR</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH11_AL3_TRANS_COUNT</name>
+                <addressOffset>0x000002f8</addressOffset>
+                <description>Alias for channel 11 TRANS_COUNT register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH11_AL3_TRANS_COUNT</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH11_AL3_READ_ADDR_TRIG</name>
+                <addressOffset>0x000002fc</addressOffset>
+                <description>Alias for channel 11 READ_ADDR register 
+                    This is a trigger register (0xc). Writing a nonzero value will 
+                    reload the channel counter and start the channel.</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH11_AL3_READ_ADDR_TRIG</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH12_READ_ADDR</name>
+                <addressOffset>0x00000300</addressOffset>
+                <description>DMA Channel 12 Read Address pointer</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CH12_READ_ADDR</name>
+                        <description>This register updates automatically each time a read completes. The current value is the next address to be read by this channel.</description>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH12_WRITE_ADDR</name>
+                <addressOffset>0x00000304</addressOffset>
+                <description>DMA Channel 12 Write Address pointer</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CH12_WRITE_ADDR</name>
+                        <description>This register updates automatically each time a write completes. The current value is the next address to be written by this channel.</description>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH12_TRANS_COUNT</name>
+                <addressOffset>0x00000308</addressOffset>
+                <description>DMA Channel 12 Transfer Count</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>MODE</name>
+                        <description>When MODE is 0x0, the transfer count decrements with each transfer until 0, and then the channel triggers the next channel indicated by CTRL_CHAIN_TO.
+
+                            When MODE is 0x1, the transfer count decrements with each transfer until 0, and then the channel re-triggers itself, in addition to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an endless ring-buffer DMA with periodic interrupts.
+
+                            When MODE is 0xf, the transfer count does not decrement. The DMA channel performs an endless sequence of transfers, never triggering other channels or raising interrupts, until an ABORT is raised.
+
+                            All other values are reserved.</description>
+                        <bitRange>[31:28]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TRIGGER_SELF</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ENDLESS</name>
+                                <value>15</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>COUNT</name>
+                        <description>28-bit transfer count (256 million transfers maximum).
+
+                            Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).
+
+                            When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.
+
+                            Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.
+
+                            The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD.</description>
+                        <bitRange>[27:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH12_CTRL_TRIG</name>
+                <addressOffset>0x0000030c</addressOffset>
+                <description>DMA Channel 12 Control and Status</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>AHB_ERROR</name>
+                        <description>Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag.</description>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>READ_ERROR</name>
+                        <description>If 1, the channel received a read bus error. Write one to clear. 
+                            READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)</description>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>WRITE_ERROR</name>
+                        <description>If 1, the channel received a write bus error. Write one to clear. 
+                            WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)</description>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>BUSY</name>
+                        <description>This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.
+
+                            To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT.</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SNIFF_EN</name>
+                        <description>If 1, this channel&#39;s data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.
+
+                            This allows checksum to be enabled or disabled on a per-control- block basis.</description>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>BSWAP</name>
+                        <description>Apply byte-swap transformation to DMA data. 
+                            For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.</description>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>IRQ_QUIET</name>
+                        <description>In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.
+
+                            This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.</description>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>TREQ_SEL</name>
+                        <description>Select a Transfer Request signal. 
+                            The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). 
+                            0x0 to 0x3a -&gt; select DREQ n as TREQ</description>
+                        <bitRange>[22:17]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>PIO0_TX0</name>
+                                <value>0</value>
+                                <description>Select PIO0&#39;s TX FIFO 0 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO0_TX1</name>
+                                <value>1</value>
+                                <description>Select PIO0&#39;s TX FIFO 1 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO0_TX2</name>
+                                <value>2</value>
+                                <description>Select PIO0&#39;s TX FIFO 2 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO0_TX3</name>
+                                <value>3</value>
+                                <description>Select PIO0&#39;s TX FIFO 3 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO0_RX0</name>
+                                <value>4</value>
+                                <description>Select PIO0&#39;s RX FIFO 0 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO0_RX1</name>
+                                <value>5</value>
+                                <description>Select PIO0&#39;s RX FIFO 1 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO0_RX2</name>
+                                <value>6</value>
+                                <description>Select PIO0&#39;s RX FIFO 2 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO0_RX3</name>
+                                <value>7</value>
+                                <description>Select PIO0&#39;s RX FIFO 3 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_TX0</name>
+                                <value>8</value>
+                                <description>Select PIO1&#39;s TX FIFO 0 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_TX1</name>
+                                <value>9</value>
+                                <description>Select PIO1&#39;s TX FIFO 1 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_TX2</name>
+                                <value>10</value>
+                                <description>Select PIO1&#39;s TX FIFO 2 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_TX3</name>
+                                <value>11</value>
+                                <description>Select PIO1&#39;s TX FIFO 3 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_RX0</name>
+                                <value>12</value>
+                                <description>Select PIO1&#39;s RX FIFO 0 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_RX1</name>
+                                <value>13</value>
+                                <description>Select PIO1&#39;s RX FIFO 1 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_RX2</name>
+                                <value>14</value>
+                                <description>Select PIO1&#39;s RX FIFO 2 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_RX3</name>
+                                <value>15</value>
+                                <description>Select PIO1&#39;s RX FIFO 3 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO2_TX0</name>
+                                <value>16</value>
+                                <description>Select PIO2&#39;s TX FIFO 0 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO2_TX1</name>
+                                <value>17</value>
+                                <description>Select PIO2&#39;s TX FIFO 1 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO2_TX2</name>
+                                <value>18</value>
+                                <description>Select PIO2&#39;s TX FIFO 2 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO2_TX3</name>
+                                <value>19</value>
+                                <description>Select PIO2&#39;s TX FIFO 3 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO2_RX0</name>
+                                <value>20</value>
+                                <description>Select PIO2&#39;s RX FIFO 0 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO2_RX1</name>
+                                <value>21</value>
+                                <description>Select PIO2&#39;s RX FIFO 1 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO2_RX2</name>
+                                <value>22</value>
+                                <description>Select PIO2&#39;s RX FIFO 2 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO2_RX3</name>
+                                <value>23</value>
+                                <description>Select PIO2&#39;s RX FIFO 3 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SPI0_TX</name>
+                                <value>24</value>
+                                <description>Select SPI0&#39;s TX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SPI0_RX</name>
+                                <value>25</value>
+                                <description>Select SPI0&#39;s RX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SPI1_TX</name>
+                                <value>26</value>
+                                <description>Select SPI1&#39;s TX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SPI1_RX</name>
+                                <value>27</value>
+                                <description>Select SPI1&#39;s RX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UART0_TX</name>
+                                <value>28</value>
+                                <description>Select UART0&#39;s TX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UART0_RX</name>
+                                <value>29</value>
+                                <description>Select UART0&#39;s RX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UART1_TX</name>
+                                <value>30</value>
+                                <description>Select UART1&#39;s TX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UART1_RX</name>
+                                <value>31</value>
+                                <description>Select UART1&#39;s RX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP0</name>
+                                <value>32</value>
+                                <description>Select PWM Counter 0&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP1</name>
+                                <value>33</value>
+                                <description>Select PWM Counter 1&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP2</name>
+                                <value>34</value>
+                                <description>Select PWM Counter 2&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP3</name>
+                                <value>35</value>
+                                <description>Select PWM Counter 3&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP4</name>
+                                <value>36</value>
+                                <description>Select PWM Counter 4&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP5</name>
+                                <value>37</value>
+                                <description>Select PWM Counter 5&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP6</name>
+                                <value>38</value>
+                                <description>Select PWM Counter 6&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP7</name>
+                                <value>39</value>
+                                <description>Select PWM Counter 7&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP8</name>
+                                <value>40</value>
+                                <description>Select PWM Counter 8&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP9</name>
+                                <value>41</value>
+                                <description>Select PWM Counter 9&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP10</name>
+                                <value>42</value>
+                                <description>Select PWM Counter 0&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP11</name>
+                                <value>43</value>
+                                <description>Select PWM Counter 1&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>I2C0_TX</name>
+                                <value>44</value>
+                                <description>Select I2C0&#39;s TX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>I2C0_RX</name>
+                                <value>45</value>
+                                <description>Select I2C0&#39;s RX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>I2C1_TX</name>
+                                <value>46</value>
+                                <description>Select I2C1&#39;s TX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>I2C1_RX</name>
+                                <value>47</value>
+                                <description>Select I2C1&#39;s RX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC</name>
+                                <value>48</value>
+                                <description>Select the ADC as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>XIP_STREAM</name>
+                                <value>49</value>
+                                <description>Select the XIP Streaming FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>XIP_QMITX</name>
+                                <value>50</value>
+                                <description>Select XIP_QMITX as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>XIP_QMIRX</name>
+                                <value>51</value>
+                                <description>Select XIP_QMIRX as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HSTX</name>
+                                <value>52</value>
+                                <description>Select HSTX as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CORESIGHT</name>
+                                <value>53</value>
+                                <description>Select CORESIGHT as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SHA256</name>
+                                <value>54</value>
+                                <description>Select SHA256 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TIMER0</name>
+                                <value>59</value>
+                                <description>Select Timer 0 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TIMER1</name>
+                                <value>60</value>
+                                <description>Select Timer 1 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TIMER2</name>
+                                <value>61</value>
+                                <description>Select Timer 2 as TREQ (Optional)</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TIMER3</name>
+                                <value>62</value>
+                                <description>Select Timer 3 as TREQ (Optional)</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PERMANENT</name>
+                                <value>63</value>
+                                <description>Permanent request, for unpaced transfers.</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>CHAIN_TO</name>
+                        <description>When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.
+
+                            Note this field resets to 0, so channels 1 and above will chain to channel 0 by default. Set this field to avoid this behaviour.</description>
+                        <bitRange>[16:13]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>RING_SEL</name>
+                        <description>Select whether RING_SIZE applies to read or write addresses. 
+                            If 0, read addresses are wrapped on a (1 &lt;&lt; RING_SIZE) boundary. If 1, write addresses are wrapped.</description>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>RING_SIZE</name>
+                        <description>Size of address wrap region. If 0, don&#39;t wrap. For values n &gt; 0, only the lower n bits of the address will change. This wraps the address on a (1 &lt;&lt; n) byte boundary, facilitating access to naturally-aligned ring buffers.
+
+                            Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.</description>
+                        <bitRange>[11:8]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>RING_NONE</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>INCR_WRITE_REV</name>
+                        <description>If 1, and INCR_WRITE is 1, the write address is decremented rather than incremented with each transfer.
+
+                            If 1, and INCR_WRITE is 0, this otherwise-unused combination causes the write address to be incremented by twice the transfer size, i.e. skipping over alternate addresses.</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INCR_WRITE</name>
+                        <description>If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.
+
+                            Generally this should be disabled for memory-to-peripheral transfers.</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INCR_READ_REV</name>
+                        <description>If 1, and INCR_READ is 1, the read address is decremented rather than incremented with each transfer.
+
+                            If 1, and INCR_READ is 0, this otherwise-unused combination causes the read address to be incremented by twice the transfer size, i.e. skipping over alternate addresses.</description>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INCR_READ</name>
+                        <description>If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.
+
+                            Generally this should be disabled for peripheral-to-memory transfers.</description>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DATA_SIZE</name>
+                        <description>Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.</description>
+                        <bitRange>[3:2]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>SIZE_BYTE</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SIZE_HALFWORD</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SIZE_WORD</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>HIGH_PRIORITY</name>
+                        <description>HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.
+
+                            This only affects the order in which the DMA schedules channels. The DMA&#39;s bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>EN</name>
+                        <description>DMA Channel Enable. 
+                            When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH12_AL1_CTRL</name>
+                <addressOffset>0x00000310</addressOffset>
+                <description>Alias for channel 12 CTRL register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH12_AL1_CTRL</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH12_AL1_READ_ADDR</name>
+                <addressOffset>0x00000314</addressOffset>
+                <description>Alias for channel 12 READ_ADDR register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH12_AL1_READ_ADDR</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH12_AL1_WRITE_ADDR</name>
+                <addressOffset>0x00000318</addressOffset>
+                <description>Alias for channel 12 WRITE_ADDR register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH12_AL1_WRITE_ADDR</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH12_AL1_TRANS_COUNT_TRIG</name>
+                <addressOffset>0x0000031c</addressOffset>
+                <description>Alias for channel 12 TRANS_COUNT register 
+                    This is a trigger register (0xc). Writing a nonzero value will 
+                    reload the channel counter and start the channel.</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH12_AL1_TRANS_COUNT_TRIG</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH12_AL2_CTRL</name>
+                <addressOffset>0x00000320</addressOffset>
+                <description>Alias for channel 12 CTRL register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH12_AL2_CTRL</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH12_AL2_TRANS_COUNT</name>
+                <addressOffset>0x00000324</addressOffset>
+                <description>Alias for channel 12 TRANS_COUNT register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH12_AL2_TRANS_COUNT</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH12_AL2_READ_ADDR</name>
+                <addressOffset>0x00000328</addressOffset>
+                <description>Alias for channel 12 READ_ADDR register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH12_AL2_READ_ADDR</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH12_AL2_WRITE_ADDR_TRIG</name>
+                <addressOffset>0x0000032c</addressOffset>
+                <description>Alias for channel 12 WRITE_ADDR register 
+                    This is a trigger register (0xc). Writing a nonzero value will 
+                    reload the channel counter and start the channel.</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH12_AL2_WRITE_ADDR_TRIG</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH12_AL3_CTRL</name>
+                <addressOffset>0x00000330</addressOffset>
+                <description>Alias for channel 12 CTRL register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH12_AL3_CTRL</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH12_AL3_WRITE_ADDR</name>
+                <addressOffset>0x00000334</addressOffset>
+                <description>Alias for channel 12 WRITE_ADDR register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH12_AL3_WRITE_ADDR</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH12_AL3_TRANS_COUNT</name>
+                <addressOffset>0x00000338</addressOffset>
+                <description>Alias for channel 12 TRANS_COUNT register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH12_AL3_TRANS_COUNT</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH12_AL3_READ_ADDR_TRIG</name>
+                <addressOffset>0x0000033c</addressOffset>
+                <description>Alias for channel 12 READ_ADDR register 
+                    This is a trigger register (0xc). Writing a nonzero value will 
+                    reload the channel counter and start the channel.</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH12_AL3_READ_ADDR_TRIG</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH13_READ_ADDR</name>
+                <addressOffset>0x00000340</addressOffset>
+                <description>DMA Channel 13 Read Address pointer</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CH13_READ_ADDR</name>
+                        <description>This register updates automatically each time a read completes. The current value is the next address to be read by this channel.</description>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH13_WRITE_ADDR</name>
+                <addressOffset>0x00000344</addressOffset>
+                <description>DMA Channel 13 Write Address pointer</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CH13_WRITE_ADDR</name>
+                        <description>This register updates automatically each time a write completes. The current value is the next address to be written by this channel.</description>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH13_TRANS_COUNT</name>
+                <addressOffset>0x00000348</addressOffset>
+                <description>DMA Channel 13 Transfer Count</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>MODE</name>
+                        <description>When MODE is 0x0, the transfer count decrements with each transfer until 0, and then the channel triggers the next channel indicated by CTRL_CHAIN_TO.
+
+                            When MODE is 0x1, the transfer count decrements with each transfer until 0, and then the channel re-triggers itself, in addition to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an endless ring-buffer DMA with periodic interrupts.
+
+                            When MODE is 0xf, the transfer count does not decrement. The DMA channel performs an endless sequence of transfers, never triggering other channels or raising interrupts, until an ABORT is raised.
+
+                            All other values are reserved.</description>
+                        <bitRange>[31:28]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TRIGGER_SELF</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ENDLESS</name>
+                                <value>15</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>COUNT</name>
+                        <description>28-bit transfer count (256 million transfers maximum).
+
+                            Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).
+
+                            When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.
+
+                            Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.
+
+                            The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD.</description>
+                        <bitRange>[27:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH13_CTRL_TRIG</name>
+                <addressOffset>0x0000034c</addressOffset>
+                <description>DMA Channel 13 Control and Status</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>AHB_ERROR</name>
+                        <description>Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag.</description>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>READ_ERROR</name>
+                        <description>If 1, the channel received a read bus error. Write one to clear. 
+                            READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)</description>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>WRITE_ERROR</name>
+                        <description>If 1, the channel received a write bus error. Write one to clear. 
+                            WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)</description>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>BUSY</name>
+                        <description>This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.
+
+                            To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT.</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SNIFF_EN</name>
+                        <description>If 1, this channel&#39;s data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.
+
+                            This allows checksum to be enabled or disabled on a per-control- block basis.</description>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>BSWAP</name>
+                        <description>Apply byte-swap transformation to DMA data. 
+                            For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.</description>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>IRQ_QUIET</name>
+                        <description>In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.
+
+                            This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.</description>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>TREQ_SEL</name>
+                        <description>Select a Transfer Request signal. 
+                            The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). 
+                            0x0 to 0x3a -&gt; select DREQ n as TREQ</description>
+                        <bitRange>[22:17]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>PIO0_TX0</name>
+                                <value>0</value>
+                                <description>Select PIO0&#39;s TX FIFO 0 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO0_TX1</name>
+                                <value>1</value>
+                                <description>Select PIO0&#39;s TX FIFO 1 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO0_TX2</name>
+                                <value>2</value>
+                                <description>Select PIO0&#39;s TX FIFO 2 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO0_TX3</name>
+                                <value>3</value>
+                                <description>Select PIO0&#39;s TX FIFO 3 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO0_RX0</name>
+                                <value>4</value>
+                                <description>Select PIO0&#39;s RX FIFO 0 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO0_RX1</name>
+                                <value>5</value>
+                                <description>Select PIO0&#39;s RX FIFO 1 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO0_RX2</name>
+                                <value>6</value>
+                                <description>Select PIO0&#39;s RX FIFO 2 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO0_RX3</name>
+                                <value>7</value>
+                                <description>Select PIO0&#39;s RX FIFO 3 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_TX0</name>
+                                <value>8</value>
+                                <description>Select PIO1&#39;s TX FIFO 0 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_TX1</name>
+                                <value>9</value>
+                                <description>Select PIO1&#39;s TX FIFO 1 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_TX2</name>
+                                <value>10</value>
+                                <description>Select PIO1&#39;s TX FIFO 2 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_TX3</name>
+                                <value>11</value>
+                                <description>Select PIO1&#39;s TX FIFO 3 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_RX0</name>
+                                <value>12</value>
+                                <description>Select PIO1&#39;s RX FIFO 0 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_RX1</name>
+                                <value>13</value>
+                                <description>Select PIO1&#39;s RX FIFO 1 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_RX2</name>
+                                <value>14</value>
+                                <description>Select PIO1&#39;s RX FIFO 2 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_RX3</name>
+                                <value>15</value>
+                                <description>Select PIO1&#39;s RX FIFO 3 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO2_TX0</name>
+                                <value>16</value>
+                                <description>Select PIO2&#39;s TX FIFO 0 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO2_TX1</name>
+                                <value>17</value>
+                                <description>Select PIO2&#39;s TX FIFO 1 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO2_TX2</name>
+                                <value>18</value>
+                                <description>Select PIO2&#39;s TX FIFO 2 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO2_TX3</name>
+                                <value>19</value>
+                                <description>Select PIO2&#39;s TX FIFO 3 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO2_RX0</name>
+                                <value>20</value>
+                                <description>Select PIO2&#39;s RX FIFO 0 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO2_RX1</name>
+                                <value>21</value>
+                                <description>Select PIO2&#39;s RX FIFO 1 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO2_RX2</name>
+                                <value>22</value>
+                                <description>Select PIO2&#39;s RX FIFO 2 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO2_RX3</name>
+                                <value>23</value>
+                                <description>Select PIO2&#39;s RX FIFO 3 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SPI0_TX</name>
+                                <value>24</value>
+                                <description>Select SPI0&#39;s TX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SPI0_RX</name>
+                                <value>25</value>
+                                <description>Select SPI0&#39;s RX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SPI1_TX</name>
+                                <value>26</value>
+                                <description>Select SPI1&#39;s TX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SPI1_RX</name>
+                                <value>27</value>
+                                <description>Select SPI1&#39;s RX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UART0_TX</name>
+                                <value>28</value>
+                                <description>Select UART0&#39;s TX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UART0_RX</name>
+                                <value>29</value>
+                                <description>Select UART0&#39;s RX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UART1_TX</name>
+                                <value>30</value>
+                                <description>Select UART1&#39;s TX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UART1_RX</name>
+                                <value>31</value>
+                                <description>Select UART1&#39;s RX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP0</name>
+                                <value>32</value>
+                                <description>Select PWM Counter 0&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP1</name>
+                                <value>33</value>
+                                <description>Select PWM Counter 1&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP2</name>
+                                <value>34</value>
+                                <description>Select PWM Counter 2&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP3</name>
+                                <value>35</value>
+                                <description>Select PWM Counter 3&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP4</name>
+                                <value>36</value>
+                                <description>Select PWM Counter 4&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP5</name>
+                                <value>37</value>
+                                <description>Select PWM Counter 5&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP6</name>
+                                <value>38</value>
+                                <description>Select PWM Counter 6&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP7</name>
+                                <value>39</value>
+                                <description>Select PWM Counter 7&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP8</name>
+                                <value>40</value>
+                                <description>Select PWM Counter 8&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP9</name>
+                                <value>41</value>
+                                <description>Select PWM Counter 9&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP10</name>
+                                <value>42</value>
+                                <description>Select PWM Counter 0&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP11</name>
+                                <value>43</value>
+                                <description>Select PWM Counter 1&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>I2C0_TX</name>
+                                <value>44</value>
+                                <description>Select I2C0&#39;s TX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>I2C0_RX</name>
+                                <value>45</value>
+                                <description>Select I2C0&#39;s RX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>I2C1_TX</name>
+                                <value>46</value>
+                                <description>Select I2C1&#39;s TX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>I2C1_RX</name>
+                                <value>47</value>
+                                <description>Select I2C1&#39;s RX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC</name>
+                                <value>48</value>
+                                <description>Select the ADC as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>XIP_STREAM</name>
+                                <value>49</value>
+                                <description>Select the XIP Streaming FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>XIP_QMITX</name>
+                                <value>50</value>
+                                <description>Select XIP_QMITX as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>XIP_QMIRX</name>
+                                <value>51</value>
+                                <description>Select XIP_QMIRX as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HSTX</name>
+                                <value>52</value>
+                                <description>Select HSTX as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CORESIGHT</name>
+                                <value>53</value>
+                                <description>Select CORESIGHT as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SHA256</name>
+                                <value>54</value>
+                                <description>Select SHA256 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TIMER0</name>
+                                <value>59</value>
+                                <description>Select Timer 0 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TIMER1</name>
+                                <value>60</value>
+                                <description>Select Timer 1 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TIMER2</name>
+                                <value>61</value>
+                                <description>Select Timer 2 as TREQ (Optional)</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TIMER3</name>
+                                <value>62</value>
+                                <description>Select Timer 3 as TREQ (Optional)</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PERMANENT</name>
+                                <value>63</value>
+                                <description>Permanent request, for unpaced transfers.</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>CHAIN_TO</name>
+                        <description>When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.
+
+                            Note this field resets to 0, so channels 1 and above will chain to channel 0 by default. Set this field to avoid this behaviour.</description>
+                        <bitRange>[16:13]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>RING_SEL</name>
+                        <description>Select whether RING_SIZE applies to read or write addresses. 
+                            If 0, read addresses are wrapped on a (1 &lt;&lt; RING_SIZE) boundary. If 1, write addresses are wrapped.</description>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>RING_SIZE</name>
+                        <description>Size of address wrap region. If 0, don&#39;t wrap. For values n &gt; 0, only the lower n bits of the address will change. This wraps the address on a (1 &lt;&lt; n) byte boundary, facilitating access to naturally-aligned ring buffers.
+
+                            Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.</description>
+                        <bitRange>[11:8]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>RING_NONE</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>INCR_WRITE_REV</name>
+                        <description>If 1, and INCR_WRITE is 1, the write address is decremented rather than incremented with each transfer.
+
+                            If 1, and INCR_WRITE is 0, this otherwise-unused combination causes the write address to be incremented by twice the transfer size, i.e. skipping over alternate addresses.</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INCR_WRITE</name>
+                        <description>If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.
+
+                            Generally this should be disabled for memory-to-peripheral transfers.</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INCR_READ_REV</name>
+                        <description>If 1, and INCR_READ is 1, the read address is decremented rather than incremented with each transfer.
+
+                            If 1, and INCR_READ is 0, this otherwise-unused combination causes the read address to be incremented by twice the transfer size, i.e. skipping over alternate addresses.</description>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INCR_READ</name>
+                        <description>If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.
+
+                            Generally this should be disabled for peripheral-to-memory transfers.</description>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DATA_SIZE</name>
+                        <description>Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.</description>
+                        <bitRange>[3:2]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>SIZE_BYTE</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SIZE_HALFWORD</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SIZE_WORD</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>HIGH_PRIORITY</name>
+                        <description>HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.
+
+                            This only affects the order in which the DMA schedules channels. The DMA&#39;s bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>EN</name>
+                        <description>DMA Channel Enable. 
+                            When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH13_AL1_CTRL</name>
+                <addressOffset>0x00000350</addressOffset>
+                <description>Alias for channel 13 CTRL register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH13_AL1_CTRL</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH13_AL1_READ_ADDR</name>
+                <addressOffset>0x00000354</addressOffset>
+                <description>Alias for channel 13 READ_ADDR register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH13_AL1_READ_ADDR</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH13_AL1_WRITE_ADDR</name>
+                <addressOffset>0x00000358</addressOffset>
+                <description>Alias for channel 13 WRITE_ADDR register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH13_AL1_WRITE_ADDR</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH13_AL1_TRANS_COUNT_TRIG</name>
+                <addressOffset>0x0000035c</addressOffset>
+                <description>Alias for channel 13 TRANS_COUNT register 
+                    This is a trigger register (0xc). Writing a nonzero value will 
+                    reload the channel counter and start the channel.</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH13_AL1_TRANS_COUNT_TRIG</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH13_AL2_CTRL</name>
+                <addressOffset>0x00000360</addressOffset>
+                <description>Alias for channel 13 CTRL register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH13_AL2_CTRL</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH13_AL2_TRANS_COUNT</name>
+                <addressOffset>0x00000364</addressOffset>
+                <description>Alias for channel 13 TRANS_COUNT register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH13_AL2_TRANS_COUNT</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH13_AL2_READ_ADDR</name>
+                <addressOffset>0x00000368</addressOffset>
+                <description>Alias for channel 13 READ_ADDR register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH13_AL2_READ_ADDR</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH13_AL2_WRITE_ADDR_TRIG</name>
+                <addressOffset>0x0000036c</addressOffset>
+                <description>Alias for channel 13 WRITE_ADDR register 
+                    This is a trigger register (0xc). Writing a nonzero value will 
+                    reload the channel counter and start the channel.</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH13_AL2_WRITE_ADDR_TRIG</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH13_AL3_CTRL</name>
+                <addressOffset>0x00000370</addressOffset>
+                <description>Alias for channel 13 CTRL register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH13_AL3_CTRL</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH13_AL3_WRITE_ADDR</name>
+                <addressOffset>0x00000374</addressOffset>
+                <description>Alias for channel 13 WRITE_ADDR register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH13_AL3_WRITE_ADDR</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH13_AL3_TRANS_COUNT</name>
+                <addressOffset>0x00000378</addressOffset>
+                <description>Alias for channel 13 TRANS_COUNT register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH13_AL3_TRANS_COUNT</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH13_AL3_READ_ADDR_TRIG</name>
+                <addressOffset>0x0000037c</addressOffset>
+                <description>Alias for channel 13 READ_ADDR register 
+                    This is a trigger register (0xc). Writing a nonzero value will 
+                    reload the channel counter and start the channel.</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH13_AL3_READ_ADDR_TRIG</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH14_READ_ADDR</name>
+                <addressOffset>0x00000380</addressOffset>
+                <description>DMA Channel 14 Read Address pointer</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CH14_READ_ADDR</name>
+                        <description>This register updates automatically each time a read completes. The current value is the next address to be read by this channel.</description>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH14_WRITE_ADDR</name>
+                <addressOffset>0x00000384</addressOffset>
+                <description>DMA Channel 14 Write Address pointer</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CH14_WRITE_ADDR</name>
+                        <description>This register updates automatically each time a write completes. The current value is the next address to be written by this channel.</description>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH14_TRANS_COUNT</name>
+                <addressOffset>0x00000388</addressOffset>
+                <description>DMA Channel 14 Transfer Count</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>MODE</name>
+                        <description>When MODE is 0x0, the transfer count decrements with each transfer until 0, and then the channel triggers the next channel indicated by CTRL_CHAIN_TO.
+
+                            When MODE is 0x1, the transfer count decrements with each transfer until 0, and then the channel re-triggers itself, in addition to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an endless ring-buffer DMA with periodic interrupts.
+
+                            When MODE is 0xf, the transfer count does not decrement. The DMA channel performs an endless sequence of transfers, never triggering other channels or raising interrupts, until an ABORT is raised.
+
+                            All other values are reserved.</description>
+                        <bitRange>[31:28]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TRIGGER_SELF</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ENDLESS</name>
+                                <value>15</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>COUNT</name>
+                        <description>28-bit transfer count (256 million transfers maximum).
+
+                            Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).
+
+                            When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.
+
+                            Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.
+
+                            The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD.</description>
+                        <bitRange>[27:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH14_CTRL_TRIG</name>
+                <addressOffset>0x0000038c</addressOffset>
+                <description>DMA Channel 14 Control and Status</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>AHB_ERROR</name>
+                        <description>Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag.</description>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>READ_ERROR</name>
+                        <description>If 1, the channel received a read bus error. Write one to clear. 
+                            READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)</description>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>WRITE_ERROR</name>
+                        <description>If 1, the channel received a write bus error. Write one to clear. 
+                            WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)</description>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>BUSY</name>
+                        <description>This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.
+
+                            To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT.</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SNIFF_EN</name>
+                        <description>If 1, this channel&#39;s data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.
+
+                            This allows checksum to be enabled or disabled on a per-control- block basis.</description>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>BSWAP</name>
+                        <description>Apply byte-swap transformation to DMA data. 
+                            For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.</description>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>IRQ_QUIET</name>
+                        <description>In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.
+
+                            This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.</description>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>TREQ_SEL</name>
+                        <description>Select a Transfer Request signal. 
+                            The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). 
+                            0x0 to 0x3a -&gt; select DREQ n as TREQ</description>
+                        <bitRange>[22:17]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>PIO0_TX0</name>
+                                <value>0</value>
+                                <description>Select PIO0&#39;s TX FIFO 0 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO0_TX1</name>
+                                <value>1</value>
+                                <description>Select PIO0&#39;s TX FIFO 1 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO0_TX2</name>
+                                <value>2</value>
+                                <description>Select PIO0&#39;s TX FIFO 2 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO0_TX3</name>
+                                <value>3</value>
+                                <description>Select PIO0&#39;s TX FIFO 3 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO0_RX0</name>
+                                <value>4</value>
+                                <description>Select PIO0&#39;s RX FIFO 0 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO0_RX1</name>
+                                <value>5</value>
+                                <description>Select PIO0&#39;s RX FIFO 1 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO0_RX2</name>
+                                <value>6</value>
+                                <description>Select PIO0&#39;s RX FIFO 2 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO0_RX3</name>
+                                <value>7</value>
+                                <description>Select PIO0&#39;s RX FIFO 3 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_TX0</name>
+                                <value>8</value>
+                                <description>Select PIO1&#39;s TX FIFO 0 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_TX1</name>
+                                <value>9</value>
+                                <description>Select PIO1&#39;s TX FIFO 1 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_TX2</name>
+                                <value>10</value>
+                                <description>Select PIO1&#39;s TX FIFO 2 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_TX3</name>
+                                <value>11</value>
+                                <description>Select PIO1&#39;s TX FIFO 3 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_RX0</name>
+                                <value>12</value>
+                                <description>Select PIO1&#39;s RX FIFO 0 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_RX1</name>
+                                <value>13</value>
+                                <description>Select PIO1&#39;s RX FIFO 1 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_RX2</name>
+                                <value>14</value>
+                                <description>Select PIO1&#39;s RX FIFO 2 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_RX3</name>
+                                <value>15</value>
+                                <description>Select PIO1&#39;s RX FIFO 3 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO2_TX0</name>
+                                <value>16</value>
+                                <description>Select PIO2&#39;s TX FIFO 0 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO2_TX1</name>
+                                <value>17</value>
+                                <description>Select PIO2&#39;s TX FIFO 1 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO2_TX2</name>
+                                <value>18</value>
+                                <description>Select PIO2&#39;s TX FIFO 2 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO2_TX3</name>
+                                <value>19</value>
+                                <description>Select PIO2&#39;s TX FIFO 3 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO2_RX0</name>
+                                <value>20</value>
+                                <description>Select PIO2&#39;s RX FIFO 0 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO2_RX1</name>
+                                <value>21</value>
+                                <description>Select PIO2&#39;s RX FIFO 1 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO2_RX2</name>
+                                <value>22</value>
+                                <description>Select PIO2&#39;s RX FIFO 2 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO2_RX3</name>
+                                <value>23</value>
+                                <description>Select PIO2&#39;s RX FIFO 3 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SPI0_TX</name>
+                                <value>24</value>
+                                <description>Select SPI0&#39;s TX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SPI0_RX</name>
+                                <value>25</value>
+                                <description>Select SPI0&#39;s RX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SPI1_TX</name>
+                                <value>26</value>
+                                <description>Select SPI1&#39;s TX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SPI1_RX</name>
+                                <value>27</value>
+                                <description>Select SPI1&#39;s RX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UART0_TX</name>
+                                <value>28</value>
+                                <description>Select UART0&#39;s TX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UART0_RX</name>
+                                <value>29</value>
+                                <description>Select UART0&#39;s RX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UART1_TX</name>
+                                <value>30</value>
+                                <description>Select UART1&#39;s TX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UART1_RX</name>
+                                <value>31</value>
+                                <description>Select UART1&#39;s RX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP0</name>
+                                <value>32</value>
+                                <description>Select PWM Counter 0&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP1</name>
+                                <value>33</value>
+                                <description>Select PWM Counter 1&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP2</name>
+                                <value>34</value>
+                                <description>Select PWM Counter 2&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP3</name>
+                                <value>35</value>
+                                <description>Select PWM Counter 3&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP4</name>
+                                <value>36</value>
+                                <description>Select PWM Counter 4&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP5</name>
+                                <value>37</value>
+                                <description>Select PWM Counter 5&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP6</name>
+                                <value>38</value>
+                                <description>Select PWM Counter 6&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP7</name>
+                                <value>39</value>
+                                <description>Select PWM Counter 7&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP8</name>
+                                <value>40</value>
+                                <description>Select PWM Counter 8&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP9</name>
+                                <value>41</value>
+                                <description>Select PWM Counter 9&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP10</name>
+                                <value>42</value>
+                                <description>Select PWM Counter 0&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP11</name>
+                                <value>43</value>
+                                <description>Select PWM Counter 1&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>I2C0_TX</name>
+                                <value>44</value>
+                                <description>Select I2C0&#39;s TX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>I2C0_RX</name>
+                                <value>45</value>
+                                <description>Select I2C0&#39;s RX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>I2C1_TX</name>
+                                <value>46</value>
+                                <description>Select I2C1&#39;s TX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>I2C1_RX</name>
+                                <value>47</value>
+                                <description>Select I2C1&#39;s RX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC</name>
+                                <value>48</value>
+                                <description>Select the ADC as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>XIP_STREAM</name>
+                                <value>49</value>
+                                <description>Select the XIP Streaming FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>XIP_QMITX</name>
+                                <value>50</value>
+                                <description>Select XIP_QMITX as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>XIP_QMIRX</name>
+                                <value>51</value>
+                                <description>Select XIP_QMIRX as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HSTX</name>
+                                <value>52</value>
+                                <description>Select HSTX as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CORESIGHT</name>
+                                <value>53</value>
+                                <description>Select CORESIGHT as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SHA256</name>
+                                <value>54</value>
+                                <description>Select SHA256 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TIMER0</name>
+                                <value>59</value>
+                                <description>Select Timer 0 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TIMER1</name>
+                                <value>60</value>
+                                <description>Select Timer 1 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TIMER2</name>
+                                <value>61</value>
+                                <description>Select Timer 2 as TREQ (Optional)</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TIMER3</name>
+                                <value>62</value>
+                                <description>Select Timer 3 as TREQ (Optional)</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PERMANENT</name>
+                                <value>63</value>
+                                <description>Permanent request, for unpaced transfers.</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>CHAIN_TO</name>
+                        <description>When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.
+
+                            Note this field resets to 0, so channels 1 and above will chain to channel 0 by default. Set this field to avoid this behaviour.</description>
+                        <bitRange>[16:13]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>RING_SEL</name>
+                        <description>Select whether RING_SIZE applies to read or write addresses. 
+                            If 0, read addresses are wrapped on a (1 &lt;&lt; RING_SIZE) boundary. If 1, write addresses are wrapped.</description>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>RING_SIZE</name>
+                        <description>Size of address wrap region. If 0, don&#39;t wrap. For values n &gt; 0, only the lower n bits of the address will change. This wraps the address on a (1 &lt;&lt; n) byte boundary, facilitating access to naturally-aligned ring buffers.
+
+                            Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.</description>
+                        <bitRange>[11:8]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>RING_NONE</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>INCR_WRITE_REV</name>
+                        <description>If 1, and INCR_WRITE is 1, the write address is decremented rather than incremented with each transfer.
+
+                            If 1, and INCR_WRITE is 0, this otherwise-unused combination causes the write address to be incremented by twice the transfer size, i.e. skipping over alternate addresses.</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INCR_WRITE</name>
+                        <description>If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.
+
+                            Generally this should be disabled for memory-to-peripheral transfers.</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INCR_READ_REV</name>
+                        <description>If 1, and INCR_READ is 1, the read address is decremented rather than incremented with each transfer.
+
+                            If 1, and INCR_READ is 0, this otherwise-unused combination causes the read address to be incremented by twice the transfer size, i.e. skipping over alternate addresses.</description>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INCR_READ</name>
+                        <description>If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.
+
+                            Generally this should be disabled for peripheral-to-memory transfers.</description>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DATA_SIZE</name>
+                        <description>Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.</description>
+                        <bitRange>[3:2]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>SIZE_BYTE</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SIZE_HALFWORD</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SIZE_WORD</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>HIGH_PRIORITY</name>
+                        <description>HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.
+
+                            This only affects the order in which the DMA schedules channels. The DMA&#39;s bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>EN</name>
+                        <description>DMA Channel Enable. 
+                            When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH14_AL1_CTRL</name>
+                <addressOffset>0x00000390</addressOffset>
+                <description>Alias for channel 14 CTRL register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH14_AL1_CTRL</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH14_AL1_READ_ADDR</name>
+                <addressOffset>0x00000394</addressOffset>
+                <description>Alias for channel 14 READ_ADDR register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH14_AL1_READ_ADDR</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH14_AL1_WRITE_ADDR</name>
+                <addressOffset>0x00000398</addressOffset>
+                <description>Alias for channel 14 WRITE_ADDR register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH14_AL1_WRITE_ADDR</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH14_AL1_TRANS_COUNT_TRIG</name>
+                <addressOffset>0x0000039c</addressOffset>
+                <description>Alias for channel 14 TRANS_COUNT register 
+                    This is a trigger register (0xc). Writing a nonzero value will 
+                    reload the channel counter and start the channel.</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH14_AL1_TRANS_COUNT_TRIG</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH14_AL2_CTRL</name>
+                <addressOffset>0x000003a0</addressOffset>
+                <description>Alias for channel 14 CTRL register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH14_AL2_CTRL</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH14_AL2_TRANS_COUNT</name>
+                <addressOffset>0x000003a4</addressOffset>
+                <description>Alias for channel 14 TRANS_COUNT register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH14_AL2_TRANS_COUNT</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH14_AL2_READ_ADDR</name>
+                <addressOffset>0x000003a8</addressOffset>
+                <description>Alias for channel 14 READ_ADDR register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH14_AL2_READ_ADDR</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH14_AL2_WRITE_ADDR_TRIG</name>
+                <addressOffset>0x000003ac</addressOffset>
+                <description>Alias for channel 14 WRITE_ADDR register 
+                    This is a trigger register (0xc). Writing a nonzero value will 
+                    reload the channel counter and start the channel.</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH14_AL2_WRITE_ADDR_TRIG</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH14_AL3_CTRL</name>
+                <addressOffset>0x000003b0</addressOffset>
+                <description>Alias for channel 14 CTRL register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH14_AL3_CTRL</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH14_AL3_WRITE_ADDR</name>
+                <addressOffset>0x000003b4</addressOffset>
+                <description>Alias for channel 14 WRITE_ADDR register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH14_AL3_WRITE_ADDR</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH14_AL3_TRANS_COUNT</name>
+                <addressOffset>0x000003b8</addressOffset>
+                <description>Alias for channel 14 TRANS_COUNT register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH14_AL3_TRANS_COUNT</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH14_AL3_READ_ADDR_TRIG</name>
+                <addressOffset>0x000003bc</addressOffset>
+                <description>Alias for channel 14 READ_ADDR register 
+                    This is a trigger register (0xc). Writing a nonzero value will 
+                    reload the channel counter and start the channel.</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH14_AL3_READ_ADDR_TRIG</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH15_READ_ADDR</name>
+                <addressOffset>0x000003c0</addressOffset>
+                <description>DMA Channel 15 Read Address pointer</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CH15_READ_ADDR</name>
+                        <description>This register updates automatically each time a read completes. The current value is the next address to be read by this channel.</description>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH15_WRITE_ADDR</name>
+                <addressOffset>0x000003c4</addressOffset>
+                <description>DMA Channel 15 Write Address pointer</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CH15_WRITE_ADDR</name>
+                        <description>This register updates automatically each time a write completes. The current value is the next address to be written by this channel.</description>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH15_TRANS_COUNT</name>
+                <addressOffset>0x000003c8</addressOffset>
+                <description>DMA Channel 15 Transfer Count</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>MODE</name>
+                        <description>When MODE is 0x0, the transfer count decrements with each transfer until 0, and then the channel triggers the next channel indicated by CTRL_CHAIN_TO.
+
+                            When MODE is 0x1, the transfer count decrements with each transfer until 0, and then the channel re-triggers itself, in addition to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an endless ring-buffer DMA with periodic interrupts.
+
+                            When MODE is 0xf, the transfer count does not decrement. The DMA channel performs an endless sequence of transfers, never triggering other channels or raising interrupts, until an ABORT is raised.
+
+                            All other values are reserved.</description>
+                        <bitRange>[31:28]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NORMAL</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TRIGGER_SELF</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ENDLESS</name>
+                                <value>15</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>COUNT</name>
+                        <description>28-bit transfer count (256 million transfers maximum).
+
+                            Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).
+
+                            When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.
+
+                            Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.
+
+                            The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD.</description>
+                        <bitRange>[27:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH15_CTRL_TRIG</name>
+                <addressOffset>0x000003cc</addressOffset>
+                <description>DMA Channel 15 Control and Status</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>AHB_ERROR</name>
+                        <description>Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag.</description>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>READ_ERROR</name>
+                        <description>If 1, the channel received a read bus error. Write one to clear. 
+                            READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)</description>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>WRITE_ERROR</name>
+                        <description>If 1, the channel received a write bus error. Write one to clear. 
+                            WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)</description>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>BUSY</name>
+                        <description>This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.
+
+                            To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT.</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SNIFF_EN</name>
+                        <description>If 1, this channel&#39;s data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.
+
+                            This allows checksum to be enabled or disabled on a per-control- block basis.</description>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>BSWAP</name>
+                        <description>Apply byte-swap transformation to DMA data. 
+                            For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.</description>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>IRQ_QUIET</name>
+                        <description>In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.
+
+                            This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.</description>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>TREQ_SEL</name>
+                        <description>Select a Transfer Request signal. 
+                            The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). 
+                            0x0 to 0x3a -&gt; select DREQ n as TREQ</description>
+                        <bitRange>[22:17]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>PIO0_TX0</name>
+                                <value>0</value>
+                                <description>Select PIO0&#39;s TX FIFO 0 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO0_TX1</name>
+                                <value>1</value>
+                                <description>Select PIO0&#39;s TX FIFO 1 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO0_TX2</name>
+                                <value>2</value>
+                                <description>Select PIO0&#39;s TX FIFO 2 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO0_TX3</name>
+                                <value>3</value>
+                                <description>Select PIO0&#39;s TX FIFO 3 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO0_RX0</name>
+                                <value>4</value>
+                                <description>Select PIO0&#39;s RX FIFO 0 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO0_RX1</name>
+                                <value>5</value>
+                                <description>Select PIO0&#39;s RX FIFO 1 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO0_RX2</name>
+                                <value>6</value>
+                                <description>Select PIO0&#39;s RX FIFO 2 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO0_RX3</name>
+                                <value>7</value>
+                                <description>Select PIO0&#39;s RX FIFO 3 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_TX0</name>
+                                <value>8</value>
+                                <description>Select PIO1&#39;s TX FIFO 0 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_TX1</name>
+                                <value>9</value>
+                                <description>Select PIO1&#39;s TX FIFO 1 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_TX2</name>
+                                <value>10</value>
+                                <description>Select PIO1&#39;s TX FIFO 2 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_TX3</name>
+                                <value>11</value>
+                                <description>Select PIO1&#39;s TX FIFO 3 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_RX0</name>
+                                <value>12</value>
+                                <description>Select PIO1&#39;s RX FIFO 0 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_RX1</name>
+                                <value>13</value>
+                                <description>Select PIO1&#39;s RX FIFO 1 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_RX2</name>
+                                <value>14</value>
+                                <description>Select PIO1&#39;s RX FIFO 2 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO1_RX3</name>
+                                <value>15</value>
+                                <description>Select PIO1&#39;s RX FIFO 3 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO2_TX0</name>
+                                <value>16</value>
+                                <description>Select PIO2&#39;s TX FIFO 0 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO2_TX1</name>
+                                <value>17</value>
+                                <description>Select PIO2&#39;s TX FIFO 1 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO2_TX2</name>
+                                <value>18</value>
+                                <description>Select PIO2&#39;s TX FIFO 2 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO2_TX3</name>
+                                <value>19</value>
+                                <description>Select PIO2&#39;s TX FIFO 3 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO2_RX0</name>
+                                <value>20</value>
+                                <description>Select PIO2&#39;s RX FIFO 0 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO2_RX1</name>
+                                <value>21</value>
+                                <description>Select PIO2&#39;s RX FIFO 1 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO2_RX2</name>
+                                <value>22</value>
+                                <description>Select PIO2&#39;s RX FIFO 2 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PIO2_RX3</name>
+                                <value>23</value>
+                                <description>Select PIO2&#39;s RX FIFO 3 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SPI0_TX</name>
+                                <value>24</value>
+                                <description>Select SPI0&#39;s TX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SPI0_RX</name>
+                                <value>25</value>
+                                <description>Select SPI0&#39;s RX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SPI1_TX</name>
+                                <value>26</value>
+                                <description>Select SPI1&#39;s TX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SPI1_RX</name>
+                                <value>27</value>
+                                <description>Select SPI1&#39;s RX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UART0_TX</name>
+                                <value>28</value>
+                                <description>Select UART0&#39;s TX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UART0_RX</name>
+                                <value>29</value>
+                                <description>Select UART0&#39;s RX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UART1_TX</name>
+                                <value>30</value>
+                                <description>Select UART1&#39;s TX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>UART1_RX</name>
+                                <value>31</value>
+                                <description>Select UART1&#39;s RX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP0</name>
+                                <value>32</value>
+                                <description>Select PWM Counter 0&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP1</name>
+                                <value>33</value>
+                                <description>Select PWM Counter 1&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP2</name>
+                                <value>34</value>
+                                <description>Select PWM Counter 2&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP3</name>
+                                <value>35</value>
+                                <description>Select PWM Counter 3&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP4</name>
+                                <value>36</value>
+                                <description>Select PWM Counter 4&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP5</name>
+                                <value>37</value>
+                                <description>Select PWM Counter 5&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP6</name>
+                                <value>38</value>
+                                <description>Select PWM Counter 6&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP7</name>
+                                <value>39</value>
+                                <description>Select PWM Counter 7&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP8</name>
+                                <value>40</value>
+                                <description>Select PWM Counter 8&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP9</name>
+                                <value>41</value>
+                                <description>Select PWM Counter 9&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP10</name>
+                                <value>42</value>
+                                <description>Select PWM Counter 0&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PWM_WRAP11</name>
+                                <value>43</value>
+                                <description>Select PWM Counter 1&#39;s Wrap Value as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>I2C0_TX</name>
+                                <value>44</value>
+                                <description>Select I2C0&#39;s TX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>I2C0_RX</name>
+                                <value>45</value>
+                                <description>Select I2C0&#39;s RX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>I2C1_TX</name>
+                                <value>46</value>
+                                <description>Select I2C1&#39;s TX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>I2C1_RX</name>
+                                <value>47</value>
+                                <description>Select I2C1&#39;s RX FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADC</name>
+                                <value>48</value>
+                                <description>Select the ADC as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>XIP_STREAM</name>
+                                <value>49</value>
+                                <description>Select the XIP Streaming FIFO as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>XIP_QMITX</name>
+                                <value>50</value>
+                                <description>Select XIP_QMITX as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>XIP_QMIRX</name>
+                                <value>51</value>
+                                <description>Select XIP_QMIRX as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HSTX</name>
+                                <value>52</value>
+                                <description>Select HSTX as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CORESIGHT</name>
+                                <value>53</value>
+                                <description>Select CORESIGHT as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SHA256</name>
+                                <value>54</value>
+                                <description>Select SHA256 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TIMER0</name>
+                                <value>59</value>
+                                <description>Select Timer 0 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TIMER1</name>
+                                <value>60</value>
+                                <description>Select Timer 1 as TREQ</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TIMER2</name>
+                                <value>61</value>
+                                <description>Select Timer 2 as TREQ (Optional)</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>TIMER3</name>
+                                <value>62</value>
+                                <description>Select Timer 3 as TREQ (Optional)</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>PERMANENT</name>
+                                <value>63</value>
+                                <description>Permanent request, for unpaced transfers.</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>CHAIN_TO</name>
+                        <description>When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.
+
+                            Note this field resets to 0, so channels 1 and above will chain to channel 0 by default. Set this field to avoid this behaviour.</description>
+                        <bitRange>[16:13]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>RING_SEL</name>
+                        <description>Select whether RING_SIZE applies to read or write addresses. 
+                            If 0, read addresses are wrapped on a (1 &lt;&lt; RING_SIZE) boundary. If 1, write addresses are wrapped.</description>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>RING_SIZE</name>
+                        <description>Size of address wrap region. If 0, don&#39;t wrap. For values n &gt; 0, only the lower n bits of the address will change. This wraps the address on a (1 &lt;&lt; n) byte boundary, facilitating access to naturally-aligned ring buffers.
+
+                            Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.</description>
+                        <bitRange>[11:8]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>RING_NONE</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>INCR_WRITE_REV</name>
+                        <description>If 1, and INCR_WRITE is 1, the write address is decremented rather than incremented with each transfer.
+
+                            If 1, and INCR_WRITE is 0, this otherwise-unused combination causes the write address to be incremented by twice the transfer size, i.e. skipping over alternate addresses.</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INCR_WRITE</name>
+                        <description>If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.
+
+                            Generally this should be disabled for memory-to-peripheral transfers.</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INCR_READ_REV</name>
+                        <description>If 1, and INCR_READ is 1, the read address is decremented rather than incremented with each transfer.
+
+                            If 1, and INCR_READ is 0, this otherwise-unused combination causes the read address to be incremented by twice the transfer size, i.e. skipping over alternate addresses.</description>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INCR_READ</name>
+                        <description>If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.
+
+                            Generally this should be disabled for peripheral-to-memory transfers.</description>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DATA_SIZE</name>
+                        <description>Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.</description>
+                        <bitRange>[3:2]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>SIZE_BYTE</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SIZE_HALFWORD</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SIZE_WORD</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>HIGH_PRIORITY</name>
+                        <description>HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.
+
+                            This only affects the order in which the DMA schedules channels. The DMA&#39;s bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>EN</name>
+                        <description>DMA Channel Enable. 
+                            When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH15_AL1_CTRL</name>
+                <addressOffset>0x000003d0</addressOffset>
+                <description>Alias for channel 15 CTRL register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH15_AL1_CTRL</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH15_AL1_READ_ADDR</name>
+                <addressOffset>0x000003d4</addressOffset>
+                <description>Alias for channel 15 READ_ADDR register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH15_AL1_READ_ADDR</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH15_AL1_WRITE_ADDR</name>
+                <addressOffset>0x000003d8</addressOffset>
+                <description>Alias for channel 15 WRITE_ADDR register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH15_AL1_WRITE_ADDR</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH15_AL1_TRANS_COUNT_TRIG</name>
+                <addressOffset>0x000003dc</addressOffset>
+                <description>Alias for channel 15 TRANS_COUNT register 
+                    This is a trigger register (0xc). Writing a nonzero value will 
+                    reload the channel counter and start the channel.</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH15_AL1_TRANS_COUNT_TRIG</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH15_AL2_CTRL</name>
+                <addressOffset>0x000003e0</addressOffset>
+                <description>Alias for channel 15 CTRL register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH15_AL2_CTRL</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH15_AL2_TRANS_COUNT</name>
+                <addressOffset>0x000003e4</addressOffset>
+                <description>Alias for channel 15 TRANS_COUNT register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH15_AL2_TRANS_COUNT</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH15_AL2_READ_ADDR</name>
+                <addressOffset>0x000003e8</addressOffset>
+                <description>Alias for channel 15 READ_ADDR register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH15_AL2_READ_ADDR</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH15_AL2_WRITE_ADDR_TRIG</name>
+                <addressOffset>0x000003ec</addressOffset>
+                <description>Alias for channel 15 WRITE_ADDR register 
+                    This is a trigger register (0xc). Writing a nonzero value will 
+                    reload the channel counter and start the channel.</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH15_AL2_WRITE_ADDR_TRIG</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH15_AL3_CTRL</name>
+                <addressOffset>0x000003f0</addressOffset>
+                <description>Alias for channel 15 CTRL register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH15_AL3_CTRL</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH15_AL3_WRITE_ADDR</name>
+                <addressOffset>0x000003f4</addressOffset>
+                <description>Alias for channel 15 WRITE_ADDR register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH15_AL3_WRITE_ADDR</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH15_AL3_TRANS_COUNT</name>
+                <addressOffset>0x000003f8</addressOffset>
+                <description>Alias for channel 15 TRANS_COUNT register</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH15_AL3_TRANS_COUNT</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH15_AL3_READ_ADDR_TRIG</name>
+                <addressOffset>0x000003fc</addressOffset>
+                <description>Alias for channel 15 READ_ADDR register 
+                    This is a trigger register (0xc). Writing a nonzero value will 
+                    reload the channel counter and start the channel.</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CH15_AL3_READ_ADDR_TRIG</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INTR</name>
+                <addressOffset>0x00000400</addressOffset>
+                <description>Interrupt Status (raw)</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>INTR</name>
+                        <description>Raw interrupt status for DMA Channels 0..15. Bit n corresponds to channel n. Ignores any masking or forcing. Channel interrupts can be cleared by writing a bit mask to INTR or INTS0/1/2/3.
+
+                            Channel interrupts can be routed to either of four system-level IRQs based on INTE0, INTE1, INTE2 and INTE3.
+
+                            The multiple system-level interrupts might be used to allow NVIC IRQ preemption for more time-critical channels, to spread IRQ load across different cores, or to target IRQs to different security domains.
+
+                            It is also valid to ignore the multiple IRQs, and just use INTE0/INTS0/IRQ 0.
+
+                            If this register is accessed at a security/privilege level less than that of a given channel (as defined by that channel&#39;s SECCFG_CHx register), then that channel&#39;s interrupt status will read as 0, ignore writes.</description>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INTE0</name>
+                <addressOffset>0x00000404</addressOffset>
+                <description>Interrupt Enables for IRQ 0</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>INTE0</name>
+                        <description>Set bit n to pass interrupts from channel n to DMA IRQ 0.
+
+                            Note this bit has no effect if the channel security/privilege level, defined by SECCFG_CHx, is greater than the IRQ security/privilege defined by SECCFG_IRQ0.</description>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INTF0</name>
+                <addressOffset>0x00000408</addressOffset>
+                <description>Force Interrupts</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>INTF0</name>
+                        <description>Write 1s to force the corresponding bits in INTS0. The interrupt remains asserted until INTF0 is cleared.</description>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INTS0</name>
+                <addressOffset>0x0000040c</addressOffset>
+                <description>Interrupt Status for IRQ 0</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>INTS0</name>
+                        <description>Indicates active channel interrupt requests which are currently causing IRQ 0 to be asserted. 
+                            Channel interrupts can be cleared by writing a bit mask here.
+
+                            Channels with a security/privilege (SECCFG_CHx) greater SECCFG_IRQ0) read as 0 in this register, and ignore writes.</description>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INTR1</name>
+                <addressOffset>0x00000410</addressOffset>
+                <description>Interrupt Status (raw)</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>INTR1</name>
+                        <description>Raw interrupt status for DMA Channels 0..15. Bit n corresponds to channel n. Ignores any masking or forcing. Channel interrupts can be cleared by writing a bit mask to INTR or INTS0/1/2/3.
+
+                            Channel interrupts can be routed to either of four system-level IRQs based on INTE0, INTE1, INTE2 and INTE3.
+
+                            The multiple system-level interrupts might be used to allow NVIC IRQ preemption for more time-critical channels, to spread IRQ load across different cores, or to target IRQs to different security domains.
+
+                            It is also valid to ignore the multiple IRQs, and just use INTE0/INTS0/IRQ 0.
+
+                            If this register is accessed at a security/privilege level less than that of a given channel (as defined by that channel&#39;s SECCFG_CHx register), then that channel&#39;s interrupt status will read as 0, ignore writes.</description>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INTE1</name>
+                <addressOffset>0x00000414</addressOffset>
+                <description>Interrupt Enables for IRQ 1</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>INTE1</name>
+                        <description>Set bit n to pass interrupts from channel n to DMA IRQ 1.
+
+                            Note this bit has no effect if the channel security/privilege level, defined by SECCFG_CHx, is greater than the IRQ security/privilege defined by SECCFG_IRQ1.</description>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INTF1</name>
+                <addressOffset>0x00000418</addressOffset>
+                <description>Force Interrupts</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>INTF1</name>
+                        <description>Write 1s to force the corresponding bits in INTS1. The interrupt remains asserted until INTF1 is cleared.</description>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INTS1</name>
+                <addressOffset>0x0000041c</addressOffset>
+                <description>Interrupt Status for IRQ 1</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>INTS1</name>
+                        <description>Indicates active channel interrupt requests which are currently causing IRQ 1 to be asserted. 
+                            Channel interrupts can be cleared by writing a bit mask here.
+
+                            Channels with a security/privilege (SECCFG_CHx) greater SECCFG_IRQ1) read as 0 in this register, and ignore writes.</description>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INTR2</name>
+                <addressOffset>0x00000420</addressOffset>
+                <description>Interrupt Status (raw)</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>INTR2</name>
+                        <description>Raw interrupt status for DMA Channels 0..15. Bit n corresponds to channel n. Ignores any masking or forcing. Channel interrupts can be cleared by writing a bit mask to INTR or INTS0/1/2/3.
+
+                            Channel interrupts can be routed to either of four system-level IRQs based on INTE0, INTE1, INTE2 and INTE3.
+
+                            The multiple system-level interrupts might be used to allow NVIC IRQ preemption for more time-critical channels, to spread IRQ load across different cores, or to target IRQs to different security domains.
+
+                            It is also valid to ignore the multiple IRQs, and just use INTE0/INTS0/IRQ 0.
+
+                            If this register is accessed at a security/privilege level less than that of a given channel (as defined by that channel&#39;s SECCFG_CHx register), then that channel&#39;s interrupt status will read as 0, ignore writes.</description>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INTE2</name>
+                <addressOffset>0x00000424</addressOffset>
+                <description>Interrupt Enables for IRQ 2</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>INTE2</name>
+                        <description>Set bit n to pass interrupts from channel n to DMA IRQ 2.
+
+                            Note this bit has no effect if the channel security/privilege level, defined by SECCFG_CHx, is greater than the IRQ security/privilege defined by SECCFG_IRQ2.</description>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INTF2</name>
+                <addressOffset>0x00000428</addressOffset>
+                <description>Force Interrupts</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>INTF2</name>
+                        <description>Write 1s to force the corresponding bits in INTS2. The interrupt remains asserted until INTF2 is cleared.</description>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INTS2</name>
+                <addressOffset>0x0000042c</addressOffset>
+                <description>Interrupt Status for IRQ 2</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>INTS2</name>
+                        <description>Indicates active channel interrupt requests which are currently causing IRQ 2 to be asserted. 
+                            Channel interrupts can be cleared by writing a bit mask here.
+
+                            Channels with a security/privilege (SECCFG_CHx) greater SECCFG_IRQ2) read as 0 in this register, and ignore writes.</description>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INTR3</name>
+                <addressOffset>0x00000430</addressOffset>
+                <description>Interrupt Status (raw)</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>INTR3</name>
+                        <description>Raw interrupt status for DMA Channels 0..15. Bit n corresponds to channel n. Ignores any masking or forcing. Channel interrupts can be cleared by writing a bit mask to INTR or INTS0/1/2/3.
+
+                            Channel interrupts can be routed to either of four system-level IRQs based on INTE0, INTE1, INTE2 and INTE3.
+
+                            The multiple system-level interrupts might be used to allow NVIC IRQ preemption for more time-critical channels, to spread IRQ load across different cores, or to target IRQs to different security domains.
+
+                            It is also valid to ignore the multiple IRQs, and just use INTE0/INTS0/IRQ 0.
+
+                            If this register is accessed at a security/privilege level less than that of a given channel (as defined by that channel&#39;s SECCFG_CHx register), then that channel&#39;s interrupt status will read as 0, ignore writes.</description>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INTE3</name>
+                <addressOffset>0x00000434</addressOffset>
+                <description>Interrupt Enables for IRQ 3</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>INTE3</name>
+                        <description>Set bit n to pass interrupts from channel n to DMA IRQ 3.
+
+                            Note this bit has no effect if the channel security/privilege level, defined by SECCFG_CHx, is greater than the IRQ security/privilege defined by SECCFG_IRQ3.</description>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INTF3</name>
+                <addressOffset>0x00000438</addressOffset>
+                <description>Force Interrupts</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>INTF3</name>
+                        <description>Write 1s to force the corresponding bits in INTS3. The interrupt remains asserted until INTF3 is cleared.</description>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INTS3</name>
+                <addressOffset>0x0000043c</addressOffset>
+                <description>Interrupt Status for IRQ 3</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>INTS3</name>
+                        <description>Indicates active channel interrupt requests which are currently causing IRQ 3 to be asserted. 
+                            Channel interrupts can be cleared by writing a bit mask here.
+
+                            Channels with a security/privilege (SECCFG_CHx) greater SECCFG_IRQ3) read as 0 in this register, and ignore writes.</description>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>TIMER0</name>
+                <addressOffset>0x00000440</addressOffset>
+                <description>Pacing (X/Y) fractional timer 
+                    The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>X</name>
+                        <description>Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer.</description>
+                        <bitRange>[31:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>Y</name>
+                        <description>Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer.</description>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>TIMER1</name>
+                <addressOffset>0x00000444</addressOffset>
+                <description>Pacing (X/Y) fractional timer 
+                    The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>X</name>
+                        <description>Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer.</description>
+                        <bitRange>[31:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>Y</name>
+                        <description>Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer.</description>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>TIMER2</name>
+                <addressOffset>0x00000448</addressOffset>
+                <description>Pacing (X/Y) fractional timer 
+                    The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>X</name>
+                        <description>Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer.</description>
+                        <bitRange>[31:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>Y</name>
+                        <description>Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer.</description>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>TIMER3</name>
+                <addressOffset>0x0000044c</addressOffset>
+                <description>Pacing (X/Y) fractional timer 
+                    The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>X</name>
+                        <description>Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer.</description>
+                        <bitRange>[31:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>Y</name>
+                        <description>Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer.</description>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>MULTI_CHAN_TRIGGER</name>
+                <addressOffset>0x00000450</addressOffset>
+                <description>Trigger one or more channels simultaneously</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>MULTI_CHAN_TRIGGER</name>
+                        <description>Each bit in this register corresponds to a DMA channel. Writing a 1 to the relevant bit is the same as writing to that channel&#39;s trigger register; the channel will start if it is currently enabled and not already busy.</description>
+                        <bitRange>[15:0]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SNIFF_CTRL</name>
+                <addressOffset>0x00000454</addressOffset>
+                <description>Sniffer Control</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>OUT_INV</name>
+                        <description>If set, the result appears inverted (bitwise complement) when read. This does not affect the way the checksum is calculated; the result is transformed on-the-fly between the result register and the bus.</description>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>OUT_REV</name>
+                        <description>If set, the result appears bit-reversed when read. This does not affect the way the checksum is calculated; the result is transformed on-the-fly between the result register and the bus.</description>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>BSWAP</name>
+                        <description>Locally perform a byte reverse on the sniffed data, before feeding into checksum.
+
+                            Note that the sniff hardware is downstream of the DMA channel byteswap performed in the read master: if channel CTRL_BSWAP and SNIFF_CTRL_BSWAP are both enabled, their effects cancel from the sniffer&#39;s point of view.</description>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CALC</name>
+                        <bitRange>[8:5]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>CRC32</name>
+                                <value>0</value>
+                                <description>Calculate a CRC-32 (IEEE802.3 polynomial)</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CRC32R</name>
+                                <value>1</value>
+                                <description>Calculate a CRC-32 (IEEE802.3 polynomial) with bit reversed data</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CRC16</name>
+                                <value>2</value>
+                                <description>Calculate a CRC-16-CCITT</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CRC16R</name>
+                                <value>3</value>
+                                <description>Calculate a CRC-16-CCITT with bit reversed data</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>EVEN</name>
+                                <value>14</value>
+                                <description>XOR reduction over all data. == 1 if the total 1 population count is odd.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SUM</name>
+                                <value>15</value>
+                                <description>Calculate a simple 32-bit checksum (addition with a 32 bit accumulator)</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>DMACH</name>
+                        <description>DMA channel for Sniffer to observe</description>
+                        <bitRange>[4:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>EN</name>
+                        <description>Enable sniffer</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SNIFF_DATA</name>
+                <addressOffset>0x00000458</addressOffset>
+                <description>Data accumulator for sniff hardware</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>SNIFF_DATA</name>
+                        <description>Write an initial seed value here before starting a DMA transfer on the channel indicated by SNIFF_CTRL_DMACH. The hardware will update this register each time it observes a read from the indicated channel. Once the channel completes, the final result can be read from this register.</description>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>FIFO_LEVELS</name>
+                <addressOffset>0x00000460</addressOffset>
+                <description>Debug RAF, WAF, TDF levels</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>RAF_LVL</name>
+                        <description>Current Read-Address-FIFO fill level</description>
+                        <bitRange>[23:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>WAF_LVL</name>
+                        <description>Current Write-Address-FIFO fill level</description>
+                        <bitRange>[15:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>TDF_LVL</name>
+                        <description>Current Transfer-Data-FIFO fill level</description>
+                        <bitRange>[7:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CHAN_ABORT</name>
+                <addressOffset>0x00000464</addressOffset>
+                <description>Abort an in-progress transfer sequence on one or more channels</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CHAN_ABORT</name>
+                        <description>Each bit corresponds to a channel. Writing a 1 aborts whatever transfer sequence is in progress on that channel. The bit will remain high until any in-flight transfers have been flushed through the address and data FIFOs.
+
+                            After writing, this register must be polled until it returns all-zero. Until this point, it is unsafe to restart the channel.</description>
+                        <bitRange>[15:0]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>N_CHANNELS</name>
+                <addressOffset>0x00000468</addressOffset>
+                <description>The number of channels this DMA instance is equipped with. This DMA supports up to 16 hardware channels, but can be configured with as few as one, to minimise silicon area.</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>N_CHANNELS</name>
+                        <bitRange>[4:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SECCFG_CH0</name>
+                <addressOffset>0x00000480</addressOffset>
+                <description>Security configuration for channel 0. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses.
+
+                    If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P &gt; S+U &gt; NS+P &gt; NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel.
+
+                    This register automatically locks down (becomes read-only) once software starts to configure the channel.
+
+                    This register is world-readable, but is writable only from a Secure, Privileged context.</description>
+                <resetValue>0x00000003</resetValue>
+                <fields>
+                    <field>
+                        <name>LOCK</name>
+                        <description>LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel&#39;s control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases.
+
+                            Once its LOCK bit is set, this register becomes read-only.
+
+                            A failed write, for example due to the write&#39;s privilege being lower than that specified in the channel&#39;s SECCFG register, will not set the LOCK bit.</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>S</name>
+                        <description>Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses.
+
+                            If 1, this channel is controllable only from a Secure context.</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>P</name>
+                        <description>Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses.
+
+                            If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level.</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SECCFG_CH1</name>
+                <addressOffset>0x00000484</addressOffset>
+                <description>Security configuration for channel 1. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses.
+
+                    If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P &gt; S+U &gt; NS+P &gt; NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel.
+
+                    This register automatically locks down (becomes read-only) once software starts to configure the channel.
+
+                    This register is world-readable, but is writable only from a Secure, Privileged context.</description>
+                <resetValue>0x00000003</resetValue>
+                <fields>
+                    <field>
+                        <name>LOCK</name>
+                        <description>LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel&#39;s control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases.
+
+                            Once its LOCK bit is set, this register becomes read-only.
+
+                            A failed write, for example due to the write&#39;s privilege being lower than that specified in the channel&#39;s SECCFG register, will not set the LOCK bit.</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>S</name>
+                        <description>Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses.
+
+                            If 1, this channel is controllable only from a Secure context.</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>P</name>
+                        <description>Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses.
+
+                            If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level.</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SECCFG_CH2</name>
+                <addressOffset>0x00000488</addressOffset>
+                <description>Security configuration for channel 2. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses.
+
+                    If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P &gt; S+U &gt; NS+P &gt; NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel.
+
+                    This register automatically locks down (becomes read-only) once software starts to configure the channel.
+
+                    This register is world-readable, but is writable only from a Secure, Privileged context.</description>
+                <resetValue>0x00000003</resetValue>
+                <fields>
+                    <field>
+                        <name>LOCK</name>
+                        <description>LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel&#39;s control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases.
+
+                            Once its LOCK bit is set, this register becomes read-only.
+
+                            A failed write, for example due to the write&#39;s privilege being lower than that specified in the channel&#39;s SECCFG register, will not set the LOCK bit.</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>S</name>
+                        <description>Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses.
+
+                            If 1, this channel is controllable only from a Secure context.</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>P</name>
+                        <description>Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses.
+
+                            If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level.</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SECCFG_CH3</name>
+                <addressOffset>0x0000048c</addressOffset>
+                <description>Security configuration for channel 3. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses.
+
+                    If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P &gt; S+U &gt; NS+P &gt; NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel.
+
+                    This register automatically locks down (becomes read-only) once software starts to configure the channel.
+
+                    This register is world-readable, but is writable only from a Secure, Privileged context.</description>
+                <resetValue>0x00000003</resetValue>
+                <fields>
+                    <field>
+                        <name>LOCK</name>
+                        <description>LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel&#39;s control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases.
+
+                            Once its LOCK bit is set, this register becomes read-only.
+
+                            A failed write, for example due to the write&#39;s privilege being lower than that specified in the channel&#39;s SECCFG register, will not set the LOCK bit.</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>S</name>
+                        <description>Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses.
+
+                            If 1, this channel is controllable only from a Secure context.</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>P</name>
+                        <description>Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses.
+
+                            If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level.</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SECCFG_CH4</name>
+                <addressOffset>0x00000490</addressOffset>
+                <description>Security configuration for channel 4. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses.
+
+                    If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P &gt; S+U &gt; NS+P &gt; NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel.
+
+                    This register automatically locks down (becomes read-only) once software starts to configure the channel.
+
+                    This register is world-readable, but is writable only from a Secure, Privileged context.</description>
+                <resetValue>0x00000003</resetValue>
+                <fields>
+                    <field>
+                        <name>LOCK</name>
+                        <description>LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel&#39;s control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases.
+
+                            Once its LOCK bit is set, this register becomes read-only.
+
+                            A failed write, for example due to the write&#39;s privilege being lower than that specified in the channel&#39;s SECCFG register, will not set the LOCK bit.</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>S</name>
+                        <description>Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses.
+
+                            If 1, this channel is controllable only from a Secure context.</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>P</name>
+                        <description>Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses.
+
+                            If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level.</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SECCFG_CH5</name>
+                <addressOffset>0x00000494</addressOffset>
+                <description>Security configuration for channel 5. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses.
+
+                    If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P &gt; S+U &gt; NS+P &gt; NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel.
+
+                    This register automatically locks down (becomes read-only) once software starts to configure the channel.
+
+                    This register is world-readable, but is writable only from a Secure, Privileged context.</description>
+                <resetValue>0x00000003</resetValue>
+                <fields>
+                    <field>
+                        <name>LOCK</name>
+                        <description>LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel&#39;s control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases.
+
+                            Once its LOCK bit is set, this register becomes read-only.
+
+                            A failed write, for example due to the write&#39;s privilege being lower than that specified in the channel&#39;s SECCFG register, will not set the LOCK bit.</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>S</name>
+                        <description>Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses.
+
+                            If 1, this channel is controllable only from a Secure context.</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>P</name>
+                        <description>Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses.
+
+                            If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level.</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SECCFG_CH6</name>
+                <addressOffset>0x00000498</addressOffset>
+                <description>Security configuration for channel 6. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses.
+
+                    If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P &gt; S+U &gt; NS+P &gt; NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel.
+
+                    This register automatically locks down (becomes read-only) once software starts to configure the channel.
+
+                    This register is world-readable, but is writable only from a Secure, Privileged context.</description>
+                <resetValue>0x00000003</resetValue>
+                <fields>
+                    <field>
+                        <name>LOCK</name>
+                        <description>LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel&#39;s control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases.
+
+                            Once its LOCK bit is set, this register becomes read-only.
+
+                            A failed write, for example due to the write&#39;s privilege being lower than that specified in the channel&#39;s SECCFG register, will not set the LOCK bit.</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>S</name>
+                        <description>Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses.
+
+                            If 1, this channel is controllable only from a Secure context.</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>P</name>
+                        <description>Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses.
+
+                            If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level.</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SECCFG_CH7</name>
+                <addressOffset>0x0000049c</addressOffset>
+                <description>Security configuration for channel 7. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses.
+
+                    If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P &gt; S+U &gt; NS+P &gt; NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel.
+
+                    This register automatically locks down (becomes read-only) once software starts to configure the channel.
+
+                    This register is world-readable, but is writable only from a Secure, Privileged context.</description>
+                <resetValue>0x00000003</resetValue>
+                <fields>
+                    <field>
+                        <name>LOCK</name>
+                        <description>LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel&#39;s control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases.
+
+                            Once its LOCK bit is set, this register becomes read-only.
+
+                            A failed write, for example due to the write&#39;s privilege being lower than that specified in the channel&#39;s SECCFG register, will not set the LOCK bit.</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>S</name>
+                        <description>Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses.
+
+                            If 1, this channel is controllable only from a Secure context.</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>P</name>
+                        <description>Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses.
+
+                            If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level.</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SECCFG_CH8</name>
+                <addressOffset>0x000004a0</addressOffset>
+                <description>Security configuration for channel 8. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses.
+
+                    If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P &gt; S+U &gt; NS+P &gt; NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel.
+
+                    This register automatically locks down (becomes read-only) once software starts to configure the channel.
+
+                    This register is world-readable, but is writable only from a Secure, Privileged context.</description>
+                <resetValue>0x00000003</resetValue>
+                <fields>
+                    <field>
+                        <name>LOCK</name>
+                        <description>LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel&#39;s control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases.
+
+                            Once its LOCK bit is set, this register becomes read-only.
+
+                            A failed write, for example due to the write&#39;s privilege being lower than that specified in the channel&#39;s SECCFG register, will not set the LOCK bit.</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>S</name>
+                        <description>Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses.
+
+                            If 1, this channel is controllable only from a Secure context.</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>P</name>
+                        <description>Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses.
+
+                            If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level.</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SECCFG_CH9</name>
+                <addressOffset>0x000004a4</addressOffset>
+                <description>Security configuration for channel 9. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses.
+
+                    If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P &gt; S+U &gt; NS+P &gt; NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel.
+
+                    This register automatically locks down (becomes read-only) once software starts to configure the channel.
+
+                    This register is world-readable, but is writable only from a Secure, Privileged context.</description>
+                <resetValue>0x00000003</resetValue>
+                <fields>
+                    <field>
+                        <name>LOCK</name>
+                        <description>LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel&#39;s control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases.
+
+                            Once its LOCK bit is set, this register becomes read-only.
+
+                            A failed write, for example due to the write&#39;s privilege being lower than that specified in the channel&#39;s SECCFG register, will not set the LOCK bit.</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>S</name>
+                        <description>Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses.
+
+                            If 1, this channel is controllable only from a Secure context.</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>P</name>
+                        <description>Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses.
+
+                            If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level.</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SECCFG_CH10</name>
+                <addressOffset>0x000004a8</addressOffset>
+                <description>Security configuration for channel 10. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses.
+
+                    If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P &gt; S+U &gt; NS+P &gt; NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel.
+
+                    This register automatically locks down (becomes read-only) once software starts to configure the channel.
+
+                    This register is world-readable, but is writable only from a Secure, Privileged context.</description>
+                <resetValue>0x00000003</resetValue>
+                <fields>
+                    <field>
+                        <name>LOCK</name>
+                        <description>LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel&#39;s control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases.
+
+                            Once its LOCK bit is set, this register becomes read-only.
+
+                            A failed write, for example due to the write&#39;s privilege being lower than that specified in the channel&#39;s SECCFG register, will not set the LOCK bit.</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>S</name>
+                        <description>Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses.
+
+                            If 1, this channel is controllable only from a Secure context.</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>P</name>
+                        <description>Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses.
+
+                            If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level.</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SECCFG_CH11</name>
+                <addressOffset>0x000004ac</addressOffset>
+                <description>Security configuration for channel 11. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses.
+
+                    If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P &gt; S+U &gt; NS+P &gt; NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel.
+
+                    This register automatically locks down (becomes read-only) once software starts to configure the channel.
+
+                    This register is world-readable, but is writable only from a Secure, Privileged context.</description>
+                <resetValue>0x00000003</resetValue>
+                <fields>
+                    <field>
+                        <name>LOCK</name>
+                        <description>LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel&#39;s control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases.
+
+                            Once its LOCK bit is set, this register becomes read-only.
+
+                            A failed write, for example due to the write&#39;s privilege being lower than that specified in the channel&#39;s SECCFG register, will not set the LOCK bit.</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>S</name>
+                        <description>Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses.
+
+                            If 1, this channel is controllable only from a Secure context.</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>P</name>
+                        <description>Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses.
+
+                            If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level.</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SECCFG_CH12</name>
+                <addressOffset>0x000004b0</addressOffset>
+                <description>Security configuration for channel 12. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses.
+
+                    If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P &gt; S+U &gt; NS+P &gt; NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel.
+
+                    This register automatically locks down (becomes read-only) once software starts to configure the channel.
+
+                    This register is world-readable, but is writable only from a Secure, Privileged context.</description>
+                <resetValue>0x00000003</resetValue>
+                <fields>
+                    <field>
+                        <name>LOCK</name>
+                        <description>LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel&#39;s control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases.
+
+                            Once its LOCK bit is set, this register becomes read-only.
+
+                            A failed write, for example due to the write&#39;s privilege being lower than that specified in the channel&#39;s SECCFG register, will not set the LOCK bit.</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>S</name>
+                        <description>Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses.
+
+                            If 1, this channel is controllable only from a Secure context.</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>P</name>
+                        <description>Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses.
+
+                            If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level.</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SECCFG_CH13</name>
+                <addressOffset>0x000004b4</addressOffset>
+                <description>Security configuration for channel 13. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses.
+
+                    If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P &gt; S+U &gt; NS+P &gt; NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel.
+
+                    This register automatically locks down (becomes read-only) once software starts to configure the channel.
+
+                    This register is world-readable, but is writable only from a Secure, Privileged context.</description>
+                <resetValue>0x00000003</resetValue>
+                <fields>
+                    <field>
+                        <name>LOCK</name>
+                        <description>LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel&#39;s control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases.
+
+                            Once its LOCK bit is set, this register becomes read-only.
+
+                            A failed write, for example due to the write&#39;s privilege being lower than that specified in the channel&#39;s SECCFG register, will not set the LOCK bit.</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>S</name>
+                        <description>Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses.
+
+                            If 1, this channel is controllable only from a Secure context.</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>P</name>
+                        <description>Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses.
+
+                            If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level.</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SECCFG_CH14</name>
+                <addressOffset>0x000004b8</addressOffset>
+                <description>Security configuration for channel 14. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses.
+
+                    If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P &gt; S+U &gt; NS+P &gt; NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel.
+
+                    This register automatically locks down (becomes read-only) once software starts to configure the channel.
+
+                    This register is world-readable, but is writable only from a Secure, Privileged context.</description>
+                <resetValue>0x00000003</resetValue>
+                <fields>
+                    <field>
+                        <name>LOCK</name>
+                        <description>LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel&#39;s control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases.
+
+                            Once its LOCK bit is set, this register becomes read-only.
+
+                            A failed write, for example due to the write&#39;s privilege being lower than that specified in the channel&#39;s SECCFG register, will not set the LOCK bit.</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>S</name>
+                        <description>Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses.
+
+                            If 1, this channel is controllable only from a Secure context.</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>P</name>
+                        <description>Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses.
+
+                            If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level.</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SECCFG_CH15</name>
+                <addressOffset>0x000004bc</addressOffset>
+                <description>Security configuration for channel 15. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses.
+
+                    If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P &gt; S+U &gt; NS+P &gt; NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel.
+
+                    This register automatically locks down (becomes read-only) once software starts to configure the channel.
+
+                    This register is world-readable, but is writable only from a Secure, Privileged context.</description>
+                <resetValue>0x00000003</resetValue>
+                <fields>
+                    <field>
+                        <name>LOCK</name>
+                        <description>LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel&#39;s control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases.
+
+                            Once its LOCK bit is set, this register becomes read-only.
+
+                            A failed write, for example due to the write&#39;s privilege being lower than that specified in the channel&#39;s SECCFG register, will not set the LOCK bit.</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>S</name>
+                        <description>Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses.
+
+                            If 1, this channel is controllable only from a Secure context.</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>P</name>
+                        <description>Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses.
+
+                            If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level.</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SECCFG_IRQ0</name>
+                <addressOffset>0x000004c0</addressOffset>
+                <description>Security configuration for IRQ 0. Control whether the IRQ permits configuration by Non-secure/Unprivileged contexts, and whether it can observe Secure/Privileged channel interrupt flags.</description>
+                <resetValue>0x00000003</resetValue>
+                <fields>
+                    <field>
+                        <name>S</name>
+                        <description>Secure IRQ. If 1, this IRQ&#39;s control registers can only be accessed from a Secure context.
+
+                            If 0, this IRQ&#39;s control registers can be accessed from a Non-secure context, but Secure channels (as per SECCFG_CHx) are masked from the IRQ status, and this IRQ&#39;s registers can not be used to acknowledge the channel interrupts of Secure channels.</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>P</name>
+                        <description>Privileged IRQ. If 1, this IRQ&#39;s control registers can only be accessed from a Privileged context.
+
+                            If 0, this IRQ&#39;s control registers can be accessed from an Unprivileged context, but Privileged channels (as per SECCFG_CHx) are masked from the IRQ status, and this IRQ&#39;s registers can not be used to acknowledge the channel interrupts of Privileged channels.</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SECCFG_IRQ1</name>
+                <addressOffset>0x000004c4</addressOffset>
+                <description>Security configuration for IRQ 1. Control whether the IRQ permits configuration by Non-secure/Unprivileged contexts, and whether it can observe Secure/Privileged channel interrupt flags.</description>
+                <resetValue>0x00000003</resetValue>
+                <fields>
+                    <field>
+                        <name>S</name>
+                        <description>Secure IRQ. If 1, this IRQ&#39;s control registers can only be accessed from a Secure context.
+
+                            If 0, this IRQ&#39;s control registers can be accessed from a Non-secure context, but Secure channels (as per SECCFG_CHx) are masked from the IRQ status, and this IRQ&#39;s registers can not be used to acknowledge the channel interrupts of Secure channels.</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>P</name>
+                        <description>Privileged IRQ. If 1, this IRQ&#39;s control registers can only be accessed from a Privileged context.
+
+                            If 0, this IRQ&#39;s control registers can be accessed from an Unprivileged context, but Privileged channels (as per SECCFG_CHx) are masked from the IRQ status, and this IRQ&#39;s registers can not be used to acknowledge the channel interrupts of Privileged channels.</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SECCFG_IRQ2</name>
+                <addressOffset>0x000004c8</addressOffset>
+                <description>Security configuration for IRQ 2. Control whether the IRQ permits configuration by Non-secure/Unprivileged contexts, and whether it can observe Secure/Privileged channel interrupt flags.</description>
+                <resetValue>0x00000003</resetValue>
+                <fields>
+                    <field>
+                        <name>S</name>
+                        <description>Secure IRQ. If 1, this IRQ&#39;s control registers can only be accessed from a Secure context.
+
+                            If 0, this IRQ&#39;s control registers can be accessed from a Non-secure context, but Secure channels (as per SECCFG_CHx) are masked from the IRQ status, and this IRQ&#39;s registers can not be used to acknowledge the channel interrupts of Secure channels.</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>P</name>
+                        <description>Privileged IRQ. If 1, this IRQ&#39;s control registers can only be accessed from a Privileged context.
+
+                            If 0, this IRQ&#39;s control registers can be accessed from an Unprivileged context, but Privileged channels (as per SECCFG_CHx) are masked from the IRQ status, and this IRQ&#39;s registers can not be used to acknowledge the channel interrupts of Privileged channels.</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SECCFG_IRQ3</name>
+                <addressOffset>0x000004cc</addressOffset>
+                <description>Security configuration for IRQ 3. Control whether the IRQ permits configuration by Non-secure/Unprivileged contexts, and whether it can observe Secure/Privileged channel interrupt flags.</description>
+                <resetValue>0x00000003</resetValue>
+                <fields>
+                    <field>
+                        <name>S</name>
+                        <description>Secure IRQ. If 1, this IRQ&#39;s control registers can only be accessed from a Secure context.
+
+                            If 0, this IRQ&#39;s control registers can be accessed from a Non-secure context, but Secure channels (as per SECCFG_CHx) are masked from the IRQ status, and this IRQ&#39;s registers can not be used to acknowledge the channel interrupts of Secure channels.</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>P</name>
+                        <description>Privileged IRQ. If 1, this IRQ&#39;s control registers can only be accessed from a Privileged context.
+
+                            If 0, this IRQ&#39;s control registers can be accessed from an Unprivileged context, but Privileged channels (as per SECCFG_CHx) are masked from the IRQ status, and this IRQ&#39;s registers can not be used to acknowledge the channel interrupts of Privileged channels.</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SECCFG_MISC</name>
+                <addressOffset>0x000004d0</addressOffset>
+                <description>Miscellaneous security configuration</description>
+                <resetValue>0x000003ff</resetValue>
+                <fields>
+                    <field>
+                        <name>TIMER3_S</name>
+                        <description>If 1, the TIMER3 register is only accessible from a Secure context, and timer DREQ 3 is only visible to Secure channels.</description>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>TIMER3_P</name>
+                        <description>If 1, the TIMER3 register is only accessible from a Privileged (or more Secure) context, and timer DREQ 3 is only visible to Privileged (or more Secure) channels.</description>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>TIMER2_S</name>
+                        <description>If 1, the TIMER2 register is only accessible from a Secure context, and timer DREQ 2 is only visible to Secure channels.</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>TIMER2_P</name>
+                        <description>If 1, the TIMER2 register is only accessible from a Privileged (or more Secure) context, and timer DREQ 2 is only visible to Privileged (or more Secure) channels.</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>TIMER1_S</name>
+                        <description>If 1, the TIMER1 register is only accessible from a Secure context, and timer DREQ 1 is only visible to Secure channels.</description>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>TIMER1_P</name>
+                        <description>If 1, the TIMER1 register is only accessible from a Privileged (or more Secure) context, and timer DREQ 1 is only visible to Privileged (or more Secure) channels.</description>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>TIMER0_S</name>
+                        <description>If 1, the TIMER0 register is only accessible from a Secure context, and timer DREQ 0 is only visible to Secure channels.</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>TIMER0_P</name>
+                        <description>If 1, the TIMER0 register is only accessible from a Privileged (or more Secure) context, and timer DREQ 0 is only visible to Privileged (or more Secure) channels.</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SNIFF_S</name>
+                        <description>If 1, the sniffer can see data transfers from Secure channels, and can itself only be accessed from a Secure context.
+
+                            If 0, the sniffer can be accessed from either a Secure or Non-secure context, but can not see data transfers of Secure channels.</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SNIFF_P</name>
+                        <description>If 1, the sniffer can see data transfers from Privileged channels, and can itself only be accessed from a privileged context, or from a Secure context when SNIFF_S is 0.
+
+                            If 0, the sniffer can be accessed from either a Privileged or Unprivileged context (with sufficient security level) but can not see transfers from Privileged channels.</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>MPU_CTRL</name>
+                <addressOffset>0x00000500</addressOffset>
+                <description>Control register for DMA MPU. Accessible only from a Privileged context.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>NS_HIDE_ADDR</name>
+                        <description>By default, when a region&#39;s S bit is clear, Non-secure-Privileged reads can see the region&#39;s base address and limit address. Set this bit to make the addresses appear as 0 to Non-secure reads, even when the region is Non-secure, to avoid leaking information about the processor SAU map.</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>S</name>
+                        <description>Determine whether an address not covered by an active MPU region is Secure (1) or Non-secure (0)</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>P</name>
+                        <description>Determine whether an address not covered by an active MPU region is Privileged (1) or Unprivileged (0)</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>MPU_BAR0</name>
+                <addressOffset>0x00000504</addressOffset>
+                <description>Base address register for MPU region 0. Writable only from a Secure, Privileged context.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>ADDR</name>
+                        <description>This MPU region matches addresses where addr[31:5] (the 27 most significant bits) are greater than or equal to BAR_ADDR, and less than or equal to LAR_ADDR.
+
+                            Readable from any Privileged context, if and only if this region&#39;s S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context.</description>
+                        <bitRange>[31:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>MPU_LAR0</name>
+                <addressOffset>0x00000508</addressOffset>
+                <description>Limit address register for MPU region 0. Writable only from a Secure, Privileged context, with the exception of the P bit.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>ADDR</name>
+                        <description>Limit address bits 31:5. Readable from any Privileged context, if and only if this region&#39;s S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context.</description>
+                        <bitRange>[31:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>S</name>
+                        <description>Determines the Secure/Non-secure (=1/0) status of addresses matching this region, if this region is enabled.</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>P</name>
+                        <description>Determines the Privileged/Unprivileged (=1/0) status of addresses matching this region, if this region is enabled. Writable from any Privileged context, if and only if the S bit is clear. Otherwise, writable only from a Secure, Privileged context.</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>EN</name>
+                        <description>Region enable. If 1, any address within range specified by the base address (BAR_ADDR) and limit address (LAR_ADDR) has the attributes specified by S and P.</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>MPU_BAR1</name>
+                <addressOffset>0x0000050c</addressOffset>
+                <description>Base address register for MPU region 1. Writable only from a Secure, Privileged context.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>ADDR</name>
+                        <description>This MPU region matches addresses where addr[31:5] (the 27 most significant bits) are greater than or equal to BAR_ADDR, and less than or equal to LAR_ADDR.
+
+                            Readable from any Privileged context, if and only if this region&#39;s S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context.</description>
+                        <bitRange>[31:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>MPU_LAR1</name>
+                <addressOffset>0x00000510</addressOffset>
+                <description>Limit address register for MPU region 1. Writable only from a Secure, Privileged context, with the exception of the P bit.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>ADDR</name>
+                        <description>Limit address bits 31:5. Readable from any Privileged context, if and only if this region&#39;s S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context.</description>
+                        <bitRange>[31:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>S</name>
+                        <description>Determines the Secure/Non-secure (=1/0) status of addresses matching this region, if this region is enabled.</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>P</name>
+                        <description>Determines the Privileged/Unprivileged (=1/0) status of addresses matching this region, if this region is enabled. Writable from any Privileged context, if and only if the S bit is clear. Otherwise, writable only from a Secure, Privileged context.</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>EN</name>
+                        <description>Region enable. If 1, any address within range specified by the base address (BAR_ADDR) and limit address (LAR_ADDR) has the attributes specified by S and P.</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>MPU_BAR2</name>
+                <addressOffset>0x00000514</addressOffset>
+                <description>Base address register for MPU region 2. Writable only from a Secure, Privileged context.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>ADDR</name>
+                        <description>This MPU region matches addresses where addr[31:5] (the 27 most significant bits) are greater than or equal to BAR_ADDR, and less than or equal to LAR_ADDR.
+
+                            Readable from any Privileged context, if and only if this region&#39;s S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context.</description>
+                        <bitRange>[31:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>MPU_LAR2</name>
+                <addressOffset>0x00000518</addressOffset>
+                <description>Limit address register for MPU region 2. Writable only from a Secure, Privileged context, with the exception of the P bit.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>ADDR</name>
+                        <description>Limit address bits 31:5. Readable from any Privileged context, if and only if this region&#39;s S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context.</description>
+                        <bitRange>[31:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>S</name>
+                        <description>Determines the Secure/Non-secure (=1/0) status of addresses matching this region, if this region is enabled.</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>P</name>
+                        <description>Determines the Privileged/Unprivileged (=1/0) status of addresses matching this region, if this region is enabled. Writable from any Privileged context, if and only if the S bit is clear. Otherwise, writable only from a Secure, Privileged context.</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>EN</name>
+                        <description>Region enable. If 1, any address within range specified by the base address (BAR_ADDR) and limit address (LAR_ADDR) has the attributes specified by S and P.</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>MPU_BAR3</name>
+                <addressOffset>0x0000051c</addressOffset>
+                <description>Base address register for MPU region 3. Writable only from a Secure, Privileged context.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>ADDR</name>
+                        <description>This MPU region matches addresses where addr[31:5] (the 27 most significant bits) are greater than or equal to BAR_ADDR, and less than or equal to LAR_ADDR.
+
+                            Readable from any Privileged context, if and only if this region&#39;s S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context.</description>
+                        <bitRange>[31:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>MPU_LAR3</name>
+                <addressOffset>0x00000520</addressOffset>
+                <description>Limit address register for MPU region 3. Writable only from a Secure, Privileged context, with the exception of the P bit.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>ADDR</name>
+                        <description>Limit address bits 31:5. Readable from any Privileged context, if and only if this region&#39;s S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context.</description>
+                        <bitRange>[31:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>S</name>
+                        <description>Determines the Secure/Non-secure (=1/0) status of addresses matching this region, if this region is enabled.</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>P</name>
+                        <description>Determines the Privileged/Unprivileged (=1/0) status of addresses matching this region, if this region is enabled. Writable from any Privileged context, if and only if the S bit is clear. Otherwise, writable only from a Secure, Privileged context.</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>EN</name>
+                        <description>Region enable. If 1, any address within range specified by the base address (BAR_ADDR) and limit address (LAR_ADDR) has the attributes specified by S and P.</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>MPU_BAR4</name>
+                <addressOffset>0x00000524</addressOffset>
+                <description>Base address register for MPU region 4. Writable only from a Secure, Privileged context.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>ADDR</name>
+                        <description>This MPU region matches addresses where addr[31:5] (the 27 most significant bits) are greater than or equal to BAR_ADDR, and less than or equal to LAR_ADDR.
+
+                            Readable from any Privileged context, if and only if this region&#39;s S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context.</description>
+                        <bitRange>[31:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>MPU_LAR4</name>
+                <addressOffset>0x00000528</addressOffset>
+                <description>Limit address register for MPU region 4. Writable only from a Secure, Privileged context, with the exception of the P bit.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>ADDR</name>
+                        <description>Limit address bits 31:5. Readable from any Privileged context, if and only if this region&#39;s S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context.</description>
+                        <bitRange>[31:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>S</name>
+                        <description>Determines the Secure/Non-secure (=1/0) status of addresses matching this region, if this region is enabled.</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>P</name>
+                        <description>Determines the Privileged/Unprivileged (=1/0) status of addresses matching this region, if this region is enabled. Writable from any Privileged context, if and only if the S bit is clear. Otherwise, writable only from a Secure, Privileged context.</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>EN</name>
+                        <description>Region enable. If 1, any address within range specified by the base address (BAR_ADDR) and limit address (LAR_ADDR) has the attributes specified by S and P.</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>MPU_BAR5</name>
+                <addressOffset>0x0000052c</addressOffset>
+                <description>Base address register for MPU region 5. Writable only from a Secure, Privileged context.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>ADDR</name>
+                        <description>This MPU region matches addresses where addr[31:5] (the 27 most significant bits) are greater than or equal to BAR_ADDR, and less than or equal to LAR_ADDR.
+
+                            Readable from any Privileged context, if and only if this region&#39;s S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context.</description>
+                        <bitRange>[31:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>MPU_LAR5</name>
+                <addressOffset>0x00000530</addressOffset>
+                <description>Limit address register for MPU region 5. Writable only from a Secure, Privileged context, with the exception of the P bit.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>ADDR</name>
+                        <description>Limit address bits 31:5. Readable from any Privileged context, if and only if this region&#39;s S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context.</description>
+                        <bitRange>[31:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>S</name>
+                        <description>Determines the Secure/Non-secure (=1/0) status of addresses matching this region, if this region is enabled.</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>P</name>
+                        <description>Determines the Privileged/Unprivileged (=1/0) status of addresses matching this region, if this region is enabled. Writable from any Privileged context, if and only if the S bit is clear. Otherwise, writable only from a Secure, Privileged context.</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>EN</name>
+                        <description>Region enable. If 1, any address within range specified by the base address (BAR_ADDR) and limit address (LAR_ADDR) has the attributes specified by S and P.</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>MPU_BAR6</name>
+                <addressOffset>0x00000534</addressOffset>
+                <description>Base address register for MPU region 6. Writable only from a Secure, Privileged context.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>ADDR</name>
+                        <description>This MPU region matches addresses where addr[31:5] (the 27 most significant bits) are greater than or equal to BAR_ADDR, and less than or equal to LAR_ADDR.
+
+                            Readable from any Privileged context, if and only if this region&#39;s S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context.</description>
+                        <bitRange>[31:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>MPU_LAR6</name>
+                <addressOffset>0x00000538</addressOffset>
+                <description>Limit address register for MPU region 6. Writable only from a Secure, Privileged context, with the exception of the P bit.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>ADDR</name>
+                        <description>Limit address bits 31:5. Readable from any Privileged context, if and only if this region&#39;s S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context.</description>
+                        <bitRange>[31:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>S</name>
+                        <description>Determines the Secure/Non-secure (=1/0) status of addresses matching this region, if this region is enabled.</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>P</name>
+                        <description>Determines the Privileged/Unprivileged (=1/0) status of addresses matching this region, if this region is enabled. Writable from any Privileged context, if and only if the S bit is clear. Otherwise, writable only from a Secure, Privileged context.</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>EN</name>
+                        <description>Region enable. If 1, any address within range specified by the base address (BAR_ADDR) and limit address (LAR_ADDR) has the attributes specified by S and P.</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>MPU_BAR7</name>
+                <addressOffset>0x0000053c</addressOffset>
+                <description>Base address register for MPU region 7. Writable only from a Secure, Privileged context.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>ADDR</name>
+                        <description>This MPU region matches addresses where addr[31:5] (the 27 most significant bits) are greater than or equal to BAR_ADDR, and less than or equal to LAR_ADDR.
+
+                            Readable from any Privileged context, if and only if this region&#39;s S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context.</description>
+                        <bitRange>[31:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>MPU_LAR7</name>
+                <addressOffset>0x00000540</addressOffset>
+                <description>Limit address register for MPU region 7. Writable only from a Secure, Privileged context, with the exception of the P bit.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>ADDR</name>
+                        <description>Limit address bits 31:5. Readable from any Privileged context, if and only if this region&#39;s S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context.</description>
+                        <bitRange>[31:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>S</name>
+                        <description>Determines the Secure/Non-secure (=1/0) status of addresses matching this region, if this region is enabled.</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>P</name>
+                        <description>Determines the Privileged/Unprivileged (=1/0) status of addresses matching this region, if this region is enabled. Writable from any Privileged context, if and only if the S bit is clear. Otherwise, writable only from a Secure, Privileged context.</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>EN</name>
+                        <description>Region enable. If 1, any address within range specified by the base address (BAR_ADDR) and limit address (LAR_ADDR) has the attributes specified by S and P.</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH0_DBG_CTDREQ</name>
+                <addressOffset>0x00000800</addressOffset>
+                <description>Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CH0_DBG_CTDREQ</name>
+                        <bitRange>[5:0]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH0_DBG_TCR</name>
+                <addressOffset>0x00000804</addressOffset>
+                <description>Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CH0_DBG_TCR</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH1_DBG_CTDREQ</name>
+                <addressOffset>0x00000840</addressOffset>
+                <description>Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CH1_DBG_CTDREQ</name>
+                        <bitRange>[5:0]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH1_DBG_TCR</name>
+                <addressOffset>0x00000844</addressOffset>
+                <description>Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CH1_DBG_TCR</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH2_DBG_CTDREQ</name>
+                <addressOffset>0x00000880</addressOffset>
+                <description>Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CH2_DBG_CTDREQ</name>
+                        <bitRange>[5:0]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH2_DBG_TCR</name>
+                <addressOffset>0x00000884</addressOffset>
+                <description>Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CH2_DBG_TCR</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH3_DBG_CTDREQ</name>
+                <addressOffset>0x000008c0</addressOffset>
+                <description>Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CH3_DBG_CTDREQ</name>
+                        <bitRange>[5:0]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH3_DBG_TCR</name>
+                <addressOffset>0x000008c4</addressOffset>
+                <description>Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CH3_DBG_TCR</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH4_DBG_CTDREQ</name>
+                <addressOffset>0x00000900</addressOffset>
+                <description>Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CH4_DBG_CTDREQ</name>
+                        <bitRange>[5:0]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH4_DBG_TCR</name>
+                <addressOffset>0x00000904</addressOffset>
+                <description>Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CH4_DBG_TCR</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH5_DBG_CTDREQ</name>
+                <addressOffset>0x00000940</addressOffset>
+                <description>Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CH5_DBG_CTDREQ</name>
+                        <bitRange>[5:0]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH5_DBG_TCR</name>
+                <addressOffset>0x00000944</addressOffset>
+                <description>Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CH5_DBG_TCR</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH6_DBG_CTDREQ</name>
+                <addressOffset>0x00000980</addressOffset>
+                <description>Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CH6_DBG_CTDREQ</name>
+                        <bitRange>[5:0]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH6_DBG_TCR</name>
+                <addressOffset>0x00000984</addressOffset>
+                <description>Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CH6_DBG_TCR</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH7_DBG_CTDREQ</name>
+                <addressOffset>0x000009c0</addressOffset>
+                <description>Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CH7_DBG_CTDREQ</name>
+                        <bitRange>[5:0]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH7_DBG_TCR</name>
+                <addressOffset>0x000009c4</addressOffset>
+                <description>Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CH7_DBG_TCR</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH8_DBG_CTDREQ</name>
+                <addressOffset>0x00000a00</addressOffset>
+                <description>Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CH8_DBG_CTDREQ</name>
+                        <bitRange>[5:0]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH8_DBG_TCR</name>
+                <addressOffset>0x00000a04</addressOffset>
+                <description>Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CH8_DBG_TCR</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH9_DBG_CTDREQ</name>
+                <addressOffset>0x00000a40</addressOffset>
+                <description>Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CH9_DBG_CTDREQ</name>
+                        <bitRange>[5:0]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH9_DBG_TCR</name>
+                <addressOffset>0x00000a44</addressOffset>
+                <description>Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CH9_DBG_TCR</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH10_DBG_CTDREQ</name>
+                <addressOffset>0x00000a80</addressOffset>
+                <description>Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CH10_DBG_CTDREQ</name>
+                        <bitRange>[5:0]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH10_DBG_TCR</name>
+                <addressOffset>0x00000a84</addressOffset>
+                <description>Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CH10_DBG_TCR</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH11_DBG_CTDREQ</name>
+                <addressOffset>0x00000ac0</addressOffset>
+                <description>Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CH11_DBG_CTDREQ</name>
+                        <bitRange>[5:0]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH11_DBG_TCR</name>
+                <addressOffset>0x00000ac4</addressOffset>
+                <description>Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CH11_DBG_TCR</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH12_DBG_CTDREQ</name>
+                <addressOffset>0x00000b00</addressOffset>
+                <description>Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CH12_DBG_CTDREQ</name>
+                        <bitRange>[5:0]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH12_DBG_TCR</name>
+                <addressOffset>0x00000b04</addressOffset>
+                <description>Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CH12_DBG_TCR</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH13_DBG_CTDREQ</name>
+                <addressOffset>0x00000b40</addressOffset>
+                <description>Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CH13_DBG_CTDREQ</name>
+                        <bitRange>[5:0]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH13_DBG_TCR</name>
+                <addressOffset>0x00000b44</addressOffset>
+                <description>Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CH13_DBG_TCR</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH14_DBG_CTDREQ</name>
+                <addressOffset>0x00000b80</addressOffset>
+                <description>Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CH14_DBG_CTDREQ</name>
+                        <bitRange>[5:0]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH14_DBG_TCR</name>
+                <addressOffset>0x00000b84</addressOffset>
+                <description>Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CH14_DBG_TCR</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH15_DBG_CTDREQ</name>
+                <addressOffset>0x00000bc0</addressOffset>
+                <description>Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CH15_DBG_CTDREQ</name>
+                        <bitRange>[5:0]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH15_DBG_TCR</name>
+                <addressOffset>0x00000bc4</addressOffset>
+                <description>Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CH15_DBG_TCR</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+        </registers>
+    </peripheral>
+    <peripheral>
+        <name>TIMER0</name>
+        <description>Controls time and alarms
+
+            time is a 64 bit value indicating the time since power-on
+
+            timeh is the top 32 bits of time &amp; timel is the bottom 32 bits to change time write to timelw before timehw to read time read from timelr before timehr
+
+            An alarm is set by setting alarm_enable and writing to the corresponding alarm register When an alarm is pending, the corresponding alarm_running signal will be high An alarm can be cancelled before it has finished by clearing the alarm_enable When an alarm fires, the corresponding alarm_irq is set and alarm_running is cleared To clear the interrupt write a 1 to the corresponding alarm_irq The timer can be locked to prevent writing</description>
+        <baseAddress>0x400b0000</baseAddress>
+        <addressBlock>
+            <offset>0</offset>
+            <size>76</size>
+            <usage>registers</usage>
+        </addressBlock>
+        <interrupt>
+            <name>TIMER0_IRQ_0</name>
+            <value>0</value>
+        </interrupt>
+        <interrupt>
+            <name>TIMER0_IRQ_1</name>
+            <value>1</value>
+        </interrupt>
+        <interrupt>
+            <name>TIMER0_IRQ_2</name>
+            <value>2</value>
+        </interrupt>
+        <interrupt>
+            <name>TIMER0_IRQ_3</name>
+            <value>3</value>
+        </interrupt>
+        <registers>
+            <register>
+                <name>TIMEHW</name>
+                <addressOffset>0x00000000</addressOffset>
+                <description>Write to bits 63:32 of time always write timelw before timehw</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>TIMEHW</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>TIMELW</name>
+                <addressOffset>0x00000004</addressOffset>
+                <description>Write to bits 31:0 of time writes do not get copied to time until timehw is written</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>TIMELW</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>TIMEHR</name>
+                <addressOffset>0x00000008</addressOffset>
+                <description>Read from bits 63:32 of time always read timelr before timehr</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>TIMEHR</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>TIMELR</name>
+                <addressOffset>0x0000000c</addressOffset>
+                <description>Read from bits 31:0 of time</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>TIMELR</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-only</access>
+                        <readAction>modify</readAction>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>ALARM0</name>
+                <addressOffset>0x00000010</addressOffset>
+                <description>Arm alarm 0, and configure the time it will fire. Once armed, the alarm fires when TIMER_ALARM0 == TIMELR. The alarm will disarm itself once it fires, and can be disarmed early using the ARMED status register.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>ALARM0</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>ALARM1</name>
+                <addressOffset>0x00000014</addressOffset>
+                <description>Arm alarm 1, and configure the time it will fire. Once armed, the alarm fires when TIMER_ALARM1 == TIMELR. The alarm will disarm itself once it fires, and can be disarmed early using the ARMED status register.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>ALARM1</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>ALARM2</name>
+                <addressOffset>0x00000018</addressOffset>
+                <description>Arm alarm 2, and configure the time it will fire. Once armed, the alarm fires when TIMER_ALARM2 == TIMELR. The alarm will disarm itself once it fires, and can be disarmed early using the ARMED status register.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>ALARM2</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>ALARM3</name>
+                <addressOffset>0x0000001c</addressOffset>
+                <description>Arm alarm 3, and configure the time it will fire. Once armed, the alarm fires when TIMER_ALARM3 == TIMELR. The alarm will disarm itself once it fires, and can be disarmed early using the ARMED status register.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>ALARM3</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>ARMED</name>
+                <addressOffset>0x00000020</addressOffset>
+                <description>Indicates the armed/disarmed status of each alarm. A write to the corresponding ALARMx register arms the alarm. Alarms automatically disarm upon firing, but writing ones here will disarm immediately without waiting to fire.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>ARMED</name>
+                        <bitRange>[3:0]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>TIMERAWH</name>
+                <addressOffset>0x00000024</addressOffset>
+                <description>Raw read from bits 63:32 of time (no side effects)</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>TIMERAWH</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>TIMERAWL</name>
+                <addressOffset>0x00000028</addressOffset>
+                <description>Raw read from bits 31:0 of time (no side effects)</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>TIMERAWL</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>DBGPAUSE</name>
+                <addressOffset>0x0000002c</addressOffset>
+                <description>Set bits high to enable pause when the corresponding debug ports are active</description>
+                <resetValue>0x00000007</resetValue>
+                <fields>
+                    <field>
+                        <name>DBG1</name>
+                        <description>Pause when processor 1 is in debug mode</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DBG0</name>
+                        <description>Pause when processor 0 is in debug mode</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PAUSE</name>
+                <addressOffset>0x00000030</addressOffset>
+                <description>Set high to pause the timer</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>PAUSE</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>LOCKED</name>
+                <addressOffset>0x00000034</addressOffset>
+                <description>Set locked bit to disable write access to timer Once set, cannot be cleared (without a reset)</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>LOCKED</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SOURCE</name>
+                <addressOffset>0x00000038</addressOffset>
+                <description>Selects the source for the timer. Defaults to the normal tick configured in the ticks block (typically configured to 1 microsecond). Writing to 1 will ignore the tick and count clk_sys cycles instead.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CLK_SYS</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>TICK</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>CLK_SYS</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INTR</name>
+                <addressOffset>0x0000003c</addressOffset>
+                <description>Raw Interrupts</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>ALARM_3</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>ALARM_2</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>ALARM_1</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>ALARM_0</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INTE</name>
+                <addressOffset>0x00000040</addressOffset>
+                <description>Interrupt Enable</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>ALARM_3</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ALARM_2</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ALARM_1</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ALARM_0</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INTF</name>
+                <addressOffset>0x00000044</addressOffset>
+                <description>Interrupt Force</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>ALARM_3</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ALARM_2</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ALARM_1</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ALARM_0</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INTS</name>
+                <addressOffset>0x00000048</addressOffset>
+                <description>Interrupt status after masking &amp; forcing</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>ALARM_3</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>ALARM_2</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>ALARM_1</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>ALARM_0</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+        </registers>
+    </peripheral>
+    <peripheral derivedFrom="TIMER0">
+        <name>TIMER1</name>
+        <baseAddress>0x400b8000</baseAddress>
+        <interrupt>
+        <name>TIMER1_IRQ_0</name>
+        <value>4</value>
+    </interrupt>
+        <interrupt>
+        <name>TIMER1_IRQ_1</name>
+        <value>5</value>
+    </interrupt>
+        <interrupt>
+        <name>TIMER1_IRQ_2</name>
+        <value>6</value>
+    </interrupt>
+        <interrupt>
+        <name>TIMER1_IRQ_3</name>
+        <value>7</value>
+    </interrupt>
+    </peripheral>
+    <peripheral>
+        <name>PWM</name>
+        <description>Simple PWM</description>
+        <baseAddress>0x400a8000</baseAddress>
+        <addressBlock>
+            <offset>0</offset>
+            <size>272</size>
+            <usage>registers</usage>
+        </addressBlock>
+        <interrupt>
+            <name>PWM_IRQ_WRAP_0</name>
+            <value>8</value>
+        </interrupt>
+        <interrupt>
+            <name>PWM_IRQ_WRAP_1</name>
+            <value>9</value>
+        </interrupt>
+        <registers>
+            <register>
+                <name>CH0_CSR</name>
+                <addressOffset>0x00000000</addressOffset>
+                <description>Control and status register</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>PH_ADV</name>
+                        <description>Advance the phase of the counter by 1 count, while it is running. 
+                            Self-clearing. Write a 1, and poll until low. Counter must be running 
+                            at less than full speed (div_int + div_frac / 16 &gt; 1)</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>PH_RET</name>
+                        <description>Retard the phase of the counter by 1 count, while it is running. 
+                            Self-clearing. Write a 1, and poll until low. Counter must be running.</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>DIVMODE</name>
+                        <bitRange>[5:4]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>div</name>
+                                <value>0</value>
+                                <description>Free-running counting at rate dictated by fractional divider</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>level</name>
+                                <value>1</value>
+                                <description>Fractional divider operation is gated by the PWM B pin.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>rise</name>
+                                <value>2</value>
+                                <description>Counter advances with each rising edge of the PWM B pin.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>fall</name>
+                                <value>3</value>
+                                <description>Counter advances with each falling edge of the PWM B pin.</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>B_INV</name>
+                        <description>Invert output B</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>A_INV</name>
+                        <description>Invert output A</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PH_CORRECT</name>
+                        <description>1: Enable phase-correct modulation. 0: Trailing-edge</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>EN</name>
+                        <description>Enable the PWM channel.</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH0_DIV</name>
+                <addressOffset>0x00000004</addressOffset>
+                <description>INT and FRAC form a fixed-point fractional number. 
+                    Counting rate is system clock frequency divided by this number. 
+                    Fractional division uses simple 1st-order sigma-delta.</description>
+                <resetValue>0x00000010</resetValue>
+                <fields>
+                    <field>
+                        <name>INT</name>
+                        <bitRange>[11:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>FRAC</name>
+                        <bitRange>[3:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH0_CTR</name>
+                <addressOffset>0x00000008</addressOffset>
+                <description>Direct access to the PWM counter</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CH0_CTR</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH0_CC</name>
+                <addressOffset>0x0000000c</addressOffset>
+                <description>Counter compare values</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>B</name>
+                        <bitRange>[31:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>A</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH0_TOP</name>
+                <addressOffset>0x00000010</addressOffset>
+                <description>Counter wrap value</description>
+                <resetValue>0x0000ffff</resetValue>
+                <fields>
+                    <field>
+                        <name>CH0_TOP</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH1_CSR</name>
+                <addressOffset>0x00000014</addressOffset>
+                <description>Control and status register</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>PH_ADV</name>
+                        <description>Advance the phase of the counter by 1 count, while it is running. 
+                            Self-clearing. Write a 1, and poll until low. Counter must be running 
+                            at less than full speed (div_int + div_frac / 16 &gt; 1)</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>PH_RET</name>
+                        <description>Retard the phase of the counter by 1 count, while it is running. 
+                            Self-clearing. Write a 1, and poll until low. Counter must be running.</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>DIVMODE</name>
+                        <bitRange>[5:4]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>div</name>
+                                <value>0</value>
+                                <description>Free-running counting at rate dictated by fractional divider</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>level</name>
+                                <value>1</value>
+                                <description>Fractional divider operation is gated by the PWM B pin.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>rise</name>
+                                <value>2</value>
+                                <description>Counter advances with each rising edge of the PWM B pin.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>fall</name>
+                                <value>3</value>
+                                <description>Counter advances with each falling edge of the PWM B pin.</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>B_INV</name>
+                        <description>Invert output B</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>A_INV</name>
+                        <description>Invert output A</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PH_CORRECT</name>
+                        <description>1: Enable phase-correct modulation. 0: Trailing-edge</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>EN</name>
+                        <description>Enable the PWM channel.</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH1_DIV</name>
+                <addressOffset>0x00000018</addressOffset>
+                <description>INT and FRAC form a fixed-point fractional number. 
+                    Counting rate is system clock frequency divided by this number. 
+                    Fractional division uses simple 1st-order sigma-delta.</description>
+                <resetValue>0x00000010</resetValue>
+                <fields>
+                    <field>
+                        <name>INT</name>
+                        <bitRange>[11:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>FRAC</name>
+                        <bitRange>[3:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH1_CTR</name>
+                <addressOffset>0x0000001c</addressOffset>
+                <description>Direct access to the PWM counter</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CH1_CTR</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH1_CC</name>
+                <addressOffset>0x00000020</addressOffset>
+                <description>Counter compare values</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>B</name>
+                        <bitRange>[31:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>A</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH1_TOP</name>
+                <addressOffset>0x00000024</addressOffset>
+                <description>Counter wrap value</description>
+                <resetValue>0x0000ffff</resetValue>
+                <fields>
+                    <field>
+                        <name>CH1_TOP</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH2_CSR</name>
+                <addressOffset>0x00000028</addressOffset>
+                <description>Control and status register</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>PH_ADV</name>
+                        <description>Advance the phase of the counter by 1 count, while it is running. 
+                            Self-clearing. Write a 1, and poll until low. Counter must be running 
+                            at less than full speed (div_int + div_frac / 16 &gt; 1)</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>PH_RET</name>
+                        <description>Retard the phase of the counter by 1 count, while it is running. 
+                            Self-clearing. Write a 1, and poll until low. Counter must be running.</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>DIVMODE</name>
+                        <bitRange>[5:4]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>div</name>
+                                <value>0</value>
+                                <description>Free-running counting at rate dictated by fractional divider</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>level</name>
+                                <value>1</value>
+                                <description>Fractional divider operation is gated by the PWM B pin.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>rise</name>
+                                <value>2</value>
+                                <description>Counter advances with each rising edge of the PWM B pin.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>fall</name>
+                                <value>3</value>
+                                <description>Counter advances with each falling edge of the PWM B pin.</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>B_INV</name>
+                        <description>Invert output B</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>A_INV</name>
+                        <description>Invert output A</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PH_CORRECT</name>
+                        <description>1: Enable phase-correct modulation. 0: Trailing-edge</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>EN</name>
+                        <description>Enable the PWM channel.</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH2_DIV</name>
+                <addressOffset>0x0000002c</addressOffset>
+                <description>INT and FRAC form a fixed-point fractional number. 
+                    Counting rate is system clock frequency divided by this number. 
+                    Fractional division uses simple 1st-order sigma-delta.</description>
+                <resetValue>0x00000010</resetValue>
+                <fields>
+                    <field>
+                        <name>INT</name>
+                        <bitRange>[11:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>FRAC</name>
+                        <bitRange>[3:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH2_CTR</name>
+                <addressOffset>0x00000030</addressOffset>
+                <description>Direct access to the PWM counter</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CH2_CTR</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH2_CC</name>
+                <addressOffset>0x00000034</addressOffset>
+                <description>Counter compare values</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>B</name>
+                        <bitRange>[31:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>A</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH2_TOP</name>
+                <addressOffset>0x00000038</addressOffset>
+                <description>Counter wrap value</description>
+                <resetValue>0x0000ffff</resetValue>
+                <fields>
+                    <field>
+                        <name>CH2_TOP</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH3_CSR</name>
+                <addressOffset>0x0000003c</addressOffset>
+                <description>Control and status register</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>PH_ADV</name>
+                        <description>Advance the phase of the counter by 1 count, while it is running. 
+                            Self-clearing. Write a 1, and poll until low. Counter must be running 
+                            at less than full speed (div_int + div_frac / 16 &gt; 1)</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>PH_RET</name>
+                        <description>Retard the phase of the counter by 1 count, while it is running. 
+                            Self-clearing. Write a 1, and poll until low. Counter must be running.</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>DIVMODE</name>
+                        <bitRange>[5:4]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>div</name>
+                                <value>0</value>
+                                <description>Free-running counting at rate dictated by fractional divider</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>level</name>
+                                <value>1</value>
+                                <description>Fractional divider operation is gated by the PWM B pin.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>rise</name>
+                                <value>2</value>
+                                <description>Counter advances with each rising edge of the PWM B pin.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>fall</name>
+                                <value>3</value>
+                                <description>Counter advances with each falling edge of the PWM B pin.</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>B_INV</name>
+                        <description>Invert output B</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>A_INV</name>
+                        <description>Invert output A</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PH_CORRECT</name>
+                        <description>1: Enable phase-correct modulation. 0: Trailing-edge</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>EN</name>
+                        <description>Enable the PWM channel.</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH3_DIV</name>
+                <addressOffset>0x00000040</addressOffset>
+                <description>INT and FRAC form a fixed-point fractional number. 
+                    Counting rate is system clock frequency divided by this number. 
+                    Fractional division uses simple 1st-order sigma-delta.</description>
+                <resetValue>0x00000010</resetValue>
+                <fields>
+                    <field>
+                        <name>INT</name>
+                        <bitRange>[11:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>FRAC</name>
+                        <bitRange>[3:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH3_CTR</name>
+                <addressOffset>0x00000044</addressOffset>
+                <description>Direct access to the PWM counter</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CH3_CTR</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH3_CC</name>
+                <addressOffset>0x00000048</addressOffset>
+                <description>Counter compare values</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>B</name>
+                        <bitRange>[31:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>A</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH3_TOP</name>
+                <addressOffset>0x0000004c</addressOffset>
+                <description>Counter wrap value</description>
+                <resetValue>0x0000ffff</resetValue>
+                <fields>
+                    <field>
+                        <name>CH3_TOP</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH4_CSR</name>
+                <addressOffset>0x00000050</addressOffset>
+                <description>Control and status register</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>PH_ADV</name>
+                        <description>Advance the phase of the counter by 1 count, while it is running. 
+                            Self-clearing. Write a 1, and poll until low. Counter must be running 
+                            at less than full speed (div_int + div_frac / 16 &gt; 1)</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>PH_RET</name>
+                        <description>Retard the phase of the counter by 1 count, while it is running. 
+                            Self-clearing. Write a 1, and poll until low. Counter must be running.</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>DIVMODE</name>
+                        <bitRange>[5:4]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>div</name>
+                                <value>0</value>
+                                <description>Free-running counting at rate dictated by fractional divider</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>level</name>
+                                <value>1</value>
+                                <description>Fractional divider operation is gated by the PWM B pin.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>rise</name>
+                                <value>2</value>
+                                <description>Counter advances with each rising edge of the PWM B pin.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>fall</name>
+                                <value>3</value>
+                                <description>Counter advances with each falling edge of the PWM B pin.</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>B_INV</name>
+                        <description>Invert output B</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>A_INV</name>
+                        <description>Invert output A</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PH_CORRECT</name>
+                        <description>1: Enable phase-correct modulation. 0: Trailing-edge</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>EN</name>
+                        <description>Enable the PWM channel.</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH4_DIV</name>
+                <addressOffset>0x00000054</addressOffset>
+                <description>INT and FRAC form a fixed-point fractional number. 
+                    Counting rate is system clock frequency divided by this number. 
+                    Fractional division uses simple 1st-order sigma-delta.</description>
+                <resetValue>0x00000010</resetValue>
+                <fields>
+                    <field>
+                        <name>INT</name>
+                        <bitRange>[11:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>FRAC</name>
+                        <bitRange>[3:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH4_CTR</name>
+                <addressOffset>0x00000058</addressOffset>
+                <description>Direct access to the PWM counter</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CH4_CTR</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH4_CC</name>
+                <addressOffset>0x0000005c</addressOffset>
+                <description>Counter compare values</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>B</name>
+                        <bitRange>[31:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>A</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH4_TOP</name>
+                <addressOffset>0x00000060</addressOffset>
+                <description>Counter wrap value</description>
+                <resetValue>0x0000ffff</resetValue>
+                <fields>
+                    <field>
+                        <name>CH4_TOP</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH5_CSR</name>
+                <addressOffset>0x00000064</addressOffset>
+                <description>Control and status register</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>PH_ADV</name>
+                        <description>Advance the phase of the counter by 1 count, while it is running. 
+                            Self-clearing. Write a 1, and poll until low. Counter must be running 
+                            at less than full speed (div_int + div_frac / 16 &gt; 1)</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>PH_RET</name>
+                        <description>Retard the phase of the counter by 1 count, while it is running. 
+                            Self-clearing. Write a 1, and poll until low. Counter must be running.</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>DIVMODE</name>
+                        <bitRange>[5:4]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>div</name>
+                                <value>0</value>
+                                <description>Free-running counting at rate dictated by fractional divider</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>level</name>
+                                <value>1</value>
+                                <description>Fractional divider operation is gated by the PWM B pin.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>rise</name>
+                                <value>2</value>
+                                <description>Counter advances with each rising edge of the PWM B pin.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>fall</name>
+                                <value>3</value>
+                                <description>Counter advances with each falling edge of the PWM B pin.</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>B_INV</name>
+                        <description>Invert output B</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>A_INV</name>
+                        <description>Invert output A</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PH_CORRECT</name>
+                        <description>1: Enable phase-correct modulation. 0: Trailing-edge</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>EN</name>
+                        <description>Enable the PWM channel.</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH5_DIV</name>
+                <addressOffset>0x00000068</addressOffset>
+                <description>INT and FRAC form a fixed-point fractional number. 
+                    Counting rate is system clock frequency divided by this number. 
+                    Fractional division uses simple 1st-order sigma-delta.</description>
+                <resetValue>0x00000010</resetValue>
+                <fields>
+                    <field>
+                        <name>INT</name>
+                        <bitRange>[11:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>FRAC</name>
+                        <bitRange>[3:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH5_CTR</name>
+                <addressOffset>0x0000006c</addressOffset>
+                <description>Direct access to the PWM counter</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CH5_CTR</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH5_CC</name>
+                <addressOffset>0x00000070</addressOffset>
+                <description>Counter compare values</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>B</name>
+                        <bitRange>[31:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>A</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH5_TOP</name>
+                <addressOffset>0x00000074</addressOffset>
+                <description>Counter wrap value</description>
+                <resetValue>0x0000ffff</resetValue>
+                <fields>
+                    <field>
+                        <name>CH5_TOP</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH6_CSR</name>
+                <addressOffset>0x00000078</addressOffset>
+                <description>Control and status register</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>PH_ADV</name>
+                        <description>Advance the phase of the counter by 1 count, while it is running. 
+                            Self-clearing. Write a 1, and poll until low. Counter must be running 
+                            at less than full speed (div_int + div_frac / 16 &gt; 1)</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>PH_RET</name>
+                        <description>Retard the phase of the counter by 1 count, while it is running. 
+                            Self-clearing. Write a 1, and poll until low. Counter must be running.</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>DIVMODE</name>
+                        <bitRange>[5:4]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>div</name>
+                                <value>0</value>
+                                <description>Free-running counting at rate dictated by fractional divider</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>level</name>
+                                <value>1</value>
+                                <description>Fractional divider operation is gated by the PWM B pin.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>rise</name>
+                                <value>2</value>
+                                <description>Counter advances with each rising edge of the PWM B pin.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>fall</name>
+                                <value>3</value>
+                                <description>Counter advances with each falling edge of the PWM B pin.</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>B_INV</name>
+                        <description>Invert output B</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>A_INV</name>
+                        <description>Invert output A</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PH_CORRECT</name>
+                        <description>1: Enable phase-correct modulation. 0: Trailing-edge</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>EN</name>
+                        <description>Enable the PWM channel.</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH6_DIV</name>
+                <addressOffset>0x0000007c</addressOffset>
+                <description>INT and FRAC form a fixed-point fractional number. 
+                    Counting rate is system clock frequency divided by this number. 
+                    Fractional division uses simple 1st-order sigma-delta.</description>
+                <resetValue>0x00000010</resetValue>
+                <fields>
+                    <field>
+                        <name>INT</name>
+                        <bitRange>[11:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>FRAC</name>
+                        <bitRange>[3:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH6_CTR</name>
+                <addressOffset>0x00000080</addressOffset>
+                <description>Direct access to the PWM counter</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CH6_CTR</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH6_CC</name>
+                <addressOffset>0x00000084</addressOffset>
+                <description>Counter compare values</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>B</name>
+                        <bitRange>[31:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>A</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH6_TOP</name>
+                <addressOffset>0x00000088</addressOffset>
+                <description>Counter wrap value</description>
+                <resetValue>0x0000ffff</resetValue>
+                <fields>
+                    <field>
+                        <name>CH6_TOP</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH7_CSR</name>
+                <addressOffset>0x0000008c</addressOffset>
+                <description>Control and status register</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>PH_ADV</name>
+                        <description>Advance the phase of the counter by 1 count, while it is running. 
+                            Self-clearing. Write a 1, and poll until low. Counter must be running 
+                            at less than full speed (div_int + div_frac / 16 &gt; 1)</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>PH_RET</name>
+                        <description>Retard the phase of the counter by 1 count, while it is running. 
+                            Self-clearing. Write a 1, and poll until low. Counter must be running.</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>DIVMODE</name>
+                        <bitRange>[5:4]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>div</name>
+                                <value>0</value>
+                                <description>Free-running counting at rate dictated by fractional divider</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>level</name>
+                                <value>1</value>
+                                <description>Fractional divider operation is gated by the PWM B pin.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>rise</name>
+                                <value>2</value>
+                                <description>Counter advances with each rising edge of the PWM B pin.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>fall</name>
+                                <value>3</value>
+                                <description>Counter advances with each falling edge of the PWM B pin.</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>B_INV</name>
+                        <description>Invert output B</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>A_INV</name>
+                        <description>Invert output A</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PH_CORRECT</name>
+                        <description>1: Enable phase-correct modulation. 0: Trailing-edge</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>EN</name>
+                        <description>Enable the PWM channel.</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH7_DIV</name>
+                <addressOffset>0x00000090</addressOffset>
+                <description>INT and FRAC form a fixed-point fractional number. 
+                    Counting rate is system clock frequency divided by this number. 
+                    Fractional division uses simple 1st-order sigma-delta.</description>
+                <resetValue>0x00000010</resetValue>
+                <fields>
+                    <field>
+                        <name>INT</name>
+                        <bitRange>[11:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>FRAC</name>
+                        <bitRange>[3:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH7_CTR</name>
+                <addressOffset>0x00000094</addressOffset>
+                <description>Direct access to the PWM counter</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CH7_CTR</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH7_CC</name>
+                <addressOffset>0x00000098</addressOffset>
+                <description>Counter compare values</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>B</name>
+                        <bitRange>[31:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>A</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH7_TOP</name>
+                <addressOffset>0x0000009c</addressOffset>
+                <description>Counter wrap value</description>
+                <resetValue>0x0000ffff</resetValue>
+                <fields>
+                    <field>
+                        <name>CH7_TOP</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH8_CSR</name>
+                <addressOffset>0x000000a0</addressOffset>
+                <description>Control and status register</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>PH_ADV</name>
+                        <description>Advance the phase of the counter by 1 count, while it is running. 
+                            Self-clearing. Write a 1, and poll until low. Counter must be running 
+                            at less than full speed (div_int + div_frac / 16 &gt; 1)</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>PH_RET</name>
+                        <description>Retard the phase of the counter by 1 count, while it is running. 
+                            Self-clearing. Write a 1, and poll until low. Counter must be running.</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>DIVMODE</name>
+                        <bitRange>[5:4]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>div</name>
+                                <value>0</value>
+                                <description>Free-running counting at rate dictated by fractional divider</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>level</name>
+                                <value>1</value>
+                                <description>Fractional divider operation is gated by the PWM B pin.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>rise</name>
+                                <value>2</value>
+                                <description>Counter advances with each rising edge of the PWM B pin.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>fall</name>
+                                <value>3</value>
+                                <description>Counter advances with each falling edge of the PWM B pin.</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>B_INV</name>
+                        <description>Invert output B</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>A_INV</name>
+                        <description>Invert output A</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PH_CORRECT</name>
+                        <description>1: Enable phase-correct modulation. 0: Trailing-edge</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>EN</name>
+                        <description>Enable the PWM channel.</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH8_DIV</name>
+                <addressOffset>0x000000a4</addressOffset>
+                <description>INT and FRAC form a fixed-point fractional number. 
+                    Counting rate is system clock frequency divided by this number. 
+                    Fractional division uses simple 1st-order sigma-delta.</description>
+                <resetValue>0x00000010</resetValue>
+                <fields>
+                    <field>
+                        <name>INT</name>
+                        <bitRange>[11:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>FRAC</name>
+                        <bitRange>[3:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH8_CTR</name>
+                <addressOffset>0x000000a8</addressOffset>
+                <description>Direct access to the PWM counter</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CH8_CTR</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH8_CC</name>
+                <addressOffset>0x000000ac</addressOffset>
+                <description>Counter compare values</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>B</name>
+                        <bitRange>[31:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>A</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH8_TOP</name>
+                <addressOffset>0x000000b0</addressOffset>
+                <description>Counter wrap value</description>
+                <resetValue>0x0000ffff</resetValue>
+                <fields>
+                    <field>
+                        <name>CH8_TOP</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH9_CSR</name>
+                <addressOffset>0x000000b4</addressOffset>
+                <description>Control and status register</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>PH_ADV</name>
+                        <description>Advance the phase of the counter by 1 count, while it is running. 
+                            Self-clearing. Write a 1, and poll until low. Counter must be running 
+                            at less than full speed (div_int + div_frac / 16 &gt; 1)</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>PH_RET</name>
+                        <description>Retard the phase of the counter by 1 count, while it is running. 
+                            Self-clearing. Write a 1, and poll until low. Counter must be running.</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>DIVMODE</name>
+                        <bitRange>[5:4]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>div</name>
+                                <value>0</value>
+                                <description>Free-running counting at rate dictated by fractional divider</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>level</name>
+                                <value>1</value>
+                                <description>Fractional divider operation is gated by the PWM B pin.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>rise</name>
+                                <value>2</value>
+                                <description>Counter advances with each rising edge of the PWM B pin.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>fall</name>
+                                <value>3</value>
+                                <description>Counter advances with each falling edge of the PWM B pin.</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>B_INV</name>
+                        <description>Invert output B</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>A_INV</name>
+                        <description>Invert output A</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PH_CORRECT</name>
+                        <description>1: Enable phase-correct modulation. 0: Trailing-edge</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>EN</name>
+                        <description>Enable the PWM channel.</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH9_DIV</name>
+                <addressOffset>0x000000b8</addressOffset>
+                <description>INT and FRAC form a fixed-point fractional number. 
+                    Counting rate is system clock frequency divided by this number. 
+                    Fractional division uses simple 1st-order sigma-delta.</description>
+                <resetValue>0x00000010</resetValue>
+                <fields>
+                    <field>
+                        <name>INT</name>
+                        <bitRange>[11:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>FRAC</name>
+                        <bitRange>[3:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH9_CTR</name>
+                <addressOffset>0x000000bc</addressOffset>
+                <description>Direct access to the PWM counter</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CH9_CTR</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH9_CC</name>
+                <addressOffset>0x000000c0</addressOffset>
+                <description>Counter compare values</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>B</name>
+                        <bitRange>[31:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>A</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH9_TOP</name>
+                <addressOffset>0x000000c4</addressOffset>
+                <description>Counter wrap value</description>
+                <resetValue>0x0000ffff</resetValue>
+                <fields>
+                    <field>
+                        <name>CH9_TOP</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH10_CSR</name>
+                <addressOffset>0x000000c8</addressOffset>
+                <description>Control and status register</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>PH_ADV</name>
+                        <description>Advance the phase of the counter by 1 count, while it is running. 
+                            Self-clearing. Write a 1, and poll until low. Counter must be running 
+                            at less than full speed (div_int + div_frac / 16 &gt; 1)</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>PH_RET</name>
+                        <description>Retard the phase of the counter by 1 count, while it is running. 
+                            Self-clearing. Write a 1, and poll until low. Counter must be running.</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>DIVMODE</name>
+                        <bitRange>[5:4]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>div</name>
+                                <value>0</value>
+                                <description>Free-running counting at rate dictated by fractional divider</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>level</name>
+                                <value>1</value>
+                                <description>Fractional divider operation is gated by the PWM B pin.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>rise</name>
+                                <value>2</value>
+                                <description>Counter advances with each rising edge of the PWM B pin.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>fall</name>
+                                <value>3</value>
+                                <description>Counter advances with each falling edge of the PWM B pin.</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>B_INV</name>
+                        <description>Invert output B</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>A_INV</name>
+                        <description>Invert output A</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PH_CORRECT</name>
+                        <description>1: Enable phase-correct modulation. 0: Trailing-edge</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>EN</name>
+                        <description>Enable the PWM channel.</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH10_DIV</name>
+                <addressOffset>0x000000cc</addressOffset>
+                <description>INT and FRAC form a fixed-point fractional number. 
+                    Counting rate is system clock frequency divided by this number. 
+                    Fractional division uses simple 1st-order sigma-delta.</description>
+                <resetValue>0x00000010</resetValue>
+                <fields>
+                    <field>
+                        <name>INT</name>
+                        <bitRange>[11:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>FRAC</name>
+                        <bitRange>[3:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH10_CTR</name>
+                <addressOffset>0x000000d0</addressOffset>
+                <description>Direct access to the PWM counter</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CH10_CTR</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH10_CC</name>
+                <addressOffset>0x000000d4</addressOffset>
+                <description>Counter compare values</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>B</name>
+                        <bitRange>[31:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>A</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH10_TOP</name>
+                <addressOffset>0x000000d8</addressOffset>
+                <description>Counter wrap value</description>
+                <resetValue>0x0000ffff</resetValue>
+                <fields>
+                    <field>
+                        <name>CH10_TOP</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH11_CSR</name>
+                <addressOffset>0x000000dc</addressOffset>
+                <description>Control and status register</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>PH_ADV</name>
+                        <description>Advance the phase of the counter by 1 count, while it is running. 
+                            Self-clearing. Write a 1, and poll until low. Counter must be running 
+                            at less than full speed (div_int + div_frac / 16 &gt; 1)</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>PH_RET</name>
+                        <description>Retard the phase of the counter by 1 count, while it is running. 
+                            Self-clearing. Write a 1, and poll until low. Counter must be running.</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>DIVMODE</name>
+                        <bitRange>[5:4]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>div</name>
+                                <value>0</value>
+                                <description>Free-running counting at rate dictated by fractional divider</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>level</name>
+                                <value>1</value>
+                                <description>Fractional divider operation is gated by the PWM B pin.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>rise</name>
+                                <value>2</value>
+                                <description>Counter advances with each rising edge of the PWM B pin.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>fall</name>
+                                <value>3</value>
+                                <description>Counter advances with each falling edge of the PWM B pin.</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>B_INV</name>
+                        <description>Invert output B</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>A_INV</name>
+                        <description>Invert output A</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PH_CORRECT</name>
+                        <description>1: Enable phase-correct modulation. 0: Trailing-edge</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>EN</name>
+                        <description>Enable the PWM channel.</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH11_DIV</name>
+                <addressOffset>0x000000e0</addressOffset>
+                <description>INT and FRAC form a fixed-point fractional number. 
+                    Counting rate is system clock frequency divided by this number. 
+                    Fractional division uses simple 1st-order sigma-delta.</description>
+                <resetValue>0x00000010</resetValue>
+                <fields>
+                    <field>
+                        <name>INT</name>
+                        <bitRange>[11:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>FRAC</name>
+                        <bitRange>[3:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH11_CTR</name>
+                <addressOffset>0x000000e4</addressOffset>
+                <description>Direct access to the PWM counter</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CH11_CTR</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH11_CC</name>
+                <addressOffset>0x000000e8</addressOffset>
+                <description>Counter compare values</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>B</name>
+                        <bitRange>[31:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>A</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CH11_TOP</name>
+                <addressOffset>0x000000ec</addressOffset>
+                <description>Counter wrap value</description>
+                <resetValue>0x0000ffff</resetValue>
+                <fields>
+                    <field>
+                        <name>CH11_TOP</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>EN</name>
+                <addressOffset>0x000000f0</addressOffset>
+                <description>This register aliases the CSR_EN bits for all channels. 
+                    Writing to this register allows multiple channels to be enabled 
+                    or disabled simultaneously, so they can run in perfect sync. 
+                    For each channel, there is only one physical EN register bit, 
+                    which can be accessed through here or CHx_CSR.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CH11</name>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CH10</name>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CH9</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CH8</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CH7</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CH6</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CH5</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CH4</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CH3</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CH2</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CH1</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CH0</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INTR</name>
+                <addressOffset>0x000000f4</addressOffset>
+                <description>Raw Interrupts</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CH11</name>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>CH10</name>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>CH9</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>CH8</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>CH7</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>CH6</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>CH5</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>CH4</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>CH3</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>CH2</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>CH1</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>CH0</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>IRQ0_INTE</name>
+                <addressOffset>0x000000f8</addressOffset>
+                <description>Interrupt Enable for irq0</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CH11</name>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CH10</name>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CH9</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CH8</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CH7</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CH6</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CH5</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CH4</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CH3</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CH2</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CH1</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CH0</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>IRQ0_INTF</name>
+                <addressOffset>0x000000fc</addressOffset>
+                <description>Interrupt Force for irq0</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CH11</name>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CH10</name>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CH9</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CH8</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CH7</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CH6</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CH5</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CH4</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CH3</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CH2</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CH1</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CH0</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>IRQ0_INTS</name>
+                <addressOffset>0x00000100</addressOffset>
+                <description>Interrupt status after masking &amp; forcing for irq0</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CH11</name>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CH10</name>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CH9</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CH8</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CH7</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CH6</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CH5</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CH4</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CH3</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CH2</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CH1</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CH0</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>IRQ1_INTE</name>
+                <addressOffset>0x00000104</addressOffset>
+                <description>Interrupt Enable for irq1</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CH11</name>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CH10</name>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CH9</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CH8</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CH7</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CH6</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CH5</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CH4</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CH3</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CH2</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CH1</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CH0</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>IRQ1_INTF</name>
+                <addressOffset>0x00000108</addressOffset>
+                <description>Interrupt Force for irq1</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CH11</name>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CH10</name>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CH9</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CH8</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CH7</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CH6</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CH5</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CH4</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CH3</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CH2</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CH1</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CH0</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>IRQ1_INTS</name>
+                <addressOffset>0x0000010c</addressOffset>
+                <description>Interrupt status after masking &amp; forcing for irq1</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CH11</name>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CH10</name>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CH9</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CH8</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CH7</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CH6</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CH5</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CH4</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CH3</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CH2</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CH1</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CH0</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+        </registers>
+    </peripheral>
+    <peripheral>
+        <name>ADC</name>
+        <description>Control and data interface to SAR ADC</description>
+        <baseAddress>0x400a0000</baseAddress>
+        <addressBlock>
+            <offset>0</offset>
+            <size>36</size>
+            <usage>registers</usage>
+        </addressBlock>
+        <interrupt>
+            <name>ADC_IRQ_FIFO</name>
+            <value>35</value>
+        </interrupt>
+        <registers>
+            <register>
+                <name>CS</name>
+                <addressOffset>0x00000000</addressOffset>
+                <description>ADC Control and Status</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>RROBIN</name>
+                        <description>Round-robin sampling. 1 bit per channel. Set all bits to 0 to disable. 
+                            Otherwise, the ADC will cycle through each enabled channel in a round-robin fashion. 
+                            The first channel to be sampled will be the one currently indicated by AINSEL. 
+                            AINSEL will be updated after each conversion with the newly-selected channel.</description>
+                        <bitRange>[24:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>AINSEL</name>
+                        <description>Select analog mux input. Updated automatically in round-robin mode. 
+                            This is corrected for the package option so only ADC channels which are bonded are available, and in the correct order</description>
+                        <bitRange>[15:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ERR_STICKY</name>
+                        <description>Some past ADC conversion encountered an error. Write 1 to clear.</description>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>ERR</name>
+                        <description>The most recent ADC conversion encountered an error; result is undefined or noisy.</description>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>READY</name>
+                        <description>1 if the ADC is ready to start a new conversion. Implies any previous conversion has completed. 
+                            0 whilst conversion in progress.</description>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>START_MANY</name>
+                        <description>Continuously perform conversions whilst this bit is 1. A new conversion will start immediately after the previous finishes.</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>START_ONCE</name>
+                        <description>Start a single conversion. Self-clearing. Ignored if start_many is asserted.</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>TS_EN</name>
+                        <description>Power on temperature sensor. 1 - enabled. 0 - disabled.</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>EN</name>
+                        <description>Power on ADC and enable its clock. 
+                            1 - enabled. 0 - disabled.</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>RESULT</name>
+                <addressOffset>0x00000004</addressOffset>
+                <description>Result of most recent ADC conversion</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>RESULT</name>
+                        <bitRange>[11:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>FCS</name>
+                <addressOffset>0x00000008</addressOffset>
+                <description>FIFO control and status</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>THRESH</name>
+                        <description>DREQ/IRQ asserted when level &gt;= threshold</description>
+                        <bitRange>[27:24]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LEVEL</name>
+                        <description>The number of conversion results currently waiting in the FIFO</description>
+                        <bitRange>[19:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OVER</name>
+                        <description>1 if the FIFO has been overflowed. Write 1 to clear.</description>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>UNDER</name>
+                        <description>1 if the FIFO has been underflowed. Write 1 to clear.</description>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>FULL</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>EMPTY</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>DREQ_EN</name>
+                        <description>If 1: assert DMA requests when FIFO contains data</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ERR</name>
+                        <description>If 1: conversion error bit appears in the FIFO alongside the result</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SHIFT</name>
+                        <description>If 1: FIFO results are right-shifted to be one byte in size. Enables DMA to byte buffers.</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>EN</name>
+                        <description>If 1: write result to the FIFO after each conversion.</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>FIFO</name>
+                <addressOffset>0x0000000c</addressOffset>
+                <description>Conversion result FIFO</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>ERR</name>
+                        <description>1 if this particular sample experienced a conversion error. Remains in the same location if the sample is shifted.</description>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-only</access>
+                        <readAction>modify</readAction>
+                    </field>
+                    <field>
+                        <name>VAL</name>
+                        <bitRange>[11:0]</bitRange>
+                        <access>read-only</access>
+                        <readAction>modify</readAction>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>DIV</name>
+                <addressOffset>0x00000010</addressOffset>
+                <description>Clock divider. If non-zero, CS_START_MANY will start conversions 
+                    at regular intervals rather than back-to-back. 
+                    The divider is reset when either of these fields are written. 
+                    Total period is 1 + INT + FRAC / 256</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>INT</name>
+                        <description>Integer part of clock divisor.</description>
+                        <bitRange>[23:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>FRAC</name>
+                        <description>Fractional part of clock divisor. First-order delta-sigma.</description>
+                        <bitRange>[7:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INTR</name>
+                <addressOffset>0x00000014</addressOffset>
+                <description>Raw Interrupts</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>FIFO</name>
+                        <description>Triggered when the sample FIFO reaches a certain level. 
+                            This level can be programmed via the FCS_THRESH field.</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INTE</name>
+                <addressOffset>0x00000018</addressOffset>
+                <description>Interrupt Enable</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>FIFO</name>
+                        <description>Triggered when the sample FIFO reaches a certain level. 
+                            This level can be programmed via the FCS_THRESH field.</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INTF</name>
+                <addressOffset>0x0000001c</addressOffset>
+                <description>Interrupt Force</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>FIFO</name>
+                        <description>Triggered when the sample FIFO reaches a certain level. 
+                            This level can be programmed via the FCS_THRESH field.</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INTS</name>
+                <addressOffset>0x00000020</addressOffset>
+                <description>Interrupt status after masking &amp; forcing</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>FIFO</name>
+                        <description>Triggered when the sample FIFO reaches a certain level. 
+                            This level can be programmed via the FCS_THRESH field.</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+        </registers>
+    </peripheral>
+    <peripheral>
+        <name>I2C0</name>
+        <description>DW_apb_i2c address block
+
+            List of configuration constants for the Synopsys I2C hardware (you may see references to these in I2C register header; these are *fixed* values, set at hardware design time):
+
+            IC_ULTRA_FAST_MODE ................ 0x0 
+            IC_UFM_TBUF_CNT_DEFAULT ........... 0x8 
+            IC_UFM_SCL_LOW_COUNT .............. 0x0008 
+            IC_UFM_SCL_HIGH_COUNT ............. 0x0006 
+            IC_TX_TL .......................... 0x0 
+            IC_TX_CMD_BLOCK ................... 0x1 
+            IC_HAS_DMA ........................ 0x1 
+            IC_HAS_ASYNC_FIFO ................. 0x0 
+            IC_SMBUS_ARP ...................... 0x0 
+            IC_FIRST_DATA_BYTE_STATUS ......... 0x1 
+            IC_INTR_IO ........................ 0x1 
+            IC_MASTER_MODE .................... 0x1 
+            IC_DEFAULT_ACK_GENERAL_CALL ....... 0x1 
+            IC_INTR_POL ....................... 0x1 
+            IC_OPTIONAL_SAR ................... 0x0 
+            IC_DEFAULT_TAR_SLAVE_ADDR ......... 0x055 
+            IC_DEFAULT_SLAVE_ADDR ............. 0x055 
+            IC_DEFAULT_HS_SPKLEN .............. 0x1 
+            IC_FS_SCL_HIGH_COUNT .............. 0x0006 
+            IC_HS_SCL_LOW_COUNT ............... 0x0008 
+            IC_DEVICE_ID_VALUE ................ 0x0 
+            IC_10BITADDR_MASTER ............... 0x0 
+            IC_CLK_FREQ_OPTIMIZATION .......... 0x0 
+            IC_DEFAULT_FS_SPKLEN .............. 0x7 
+            IC_ADD_ENCODED_PARAMS ............. 0x0 
+            IC_DEFAULT_SDA_HOLD ............... 0x000001 
+            IC_DEFAULT_SDA_SETUP .............. 0x64 
+            IC_AVOID_RX_FIFO_FLUSH_ON_TX_ABRT . 0x0 
+            IC_CLOCK_PERIOD ................... 100 
+            IC_EMPTYFIFO_HOLD_MASTER_EN ....... 1 
+            IC_RESTART_EN ..................... 0x1 
+            IC_TX_CMD_BLOCK_DEFAULT ........... 0x0 
+            IC_BUS_CLEAR_FEATURE .............. 0x0 
+            IC_CAP_LOADING .................... 100 
+            IC_FS_SCL_LOW_COUNT ............... 0x000d 
+            APB_DATA_WIDTH .................... 32 
+            IC_SDA_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff 
+            IC_SLV_DATA_NACK_ONLY ............. 0x1 
+            IC_10BITADDR_SLAVE ................ 0x0 
+            IC_CLK_TYPE ....................... 0x0 
+            IC_SMBUS_UDID_MSB ................. 0x0 
+            IC_SMBUS_SUSPEND_ALERT ............ 0x0 
+            IC_HS_SCL_HIGH_COUNT .............. 0x0006 
+            IC_SLV_RESTART_DET_EN ............. 0x1 
+            IC_SMBUS .......................... 0x0 
+            IC_OPTIONAL_SAR_DEFAULT ........... 0x0 
+            IC_PERSISTANT_SLV_ADDR_DEFAULT .... 0x0 
+            IC_USE_COUNTS ..................... 0x0 
+            IC_RX_BUFFER_DEPTH ................ 16 
+            IC_SCL_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff 
+            IC_RX_FULL_HLD_BUS_EN ............. 0x1 
+            IC_SLAVE_DISABLE .................. 0x1 
+            IC_RX_TL .......................... 0x0 
+            IC_DEVICE_ID ...................... 0x0 
+            IC_HC_COUNT_VALUES ................ 0x0 
+            I2C_DYNAMIC_TAR_UPDATE ............ 0 
+            IC_SMBUS_CLK_LOW_MEXT_DEFAULT ..... 0xffffffff 
+            IC_SMBUS_CLK_LOW_SEXT_DEFAULT ..... 0xffffffff 
+            IC_HS_MASTER_CODE ................. 0x1 
+            IC_SMBUS_RST_IDLE_CNT_DEFAULT ..... 0xffff 
+            IC_SMBUS_UDID_LSB_DEFAULT ......... 0xffffffff 
+            IC_SS_SCL_HIGH_COUNT .............. 0x0028 
+            IC_SS_SCL_LOW_COUNT ............... 0x002f 
+            IC_MAX_SPEED_MODE ................. 0x2 
+            IC_STAT_FOR_CLK_STRETCH ........... 0x0 
+            IC_STOP_DET_IF_MASTER_ACTIVE ...... 0x0 
+            IC_DEFAULT_UFM_SPKLEN ............. 0x1 
+            IC_TX_BUFFER_DEPTH ................ 16</description>
+        <baseAddress>0x40090000</baseAddress>
+        <addressBlock>
+            <offset>0</offset>
+            <size>256</size>
+            <usage>registers</usage>
+        </addressBlock>
+        <interrupt>
+            <name>I2C0_IRQ</name>
+            <value>36</value>
+        </interrupt>
+        <registers>
+            <register>
+                <name>IC_CON</name>
+                <addressOffset>0x00000000</addressOffset>
+                <description>I2C Control Register. This register can be written only when the DW_apb_i2c is disabled, which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect.
+
+                    Read/Write Access: - bit 10 is read only. - bit 11 is read only - bit 16 is read only - bit 17 is read only - bits 18 and 19 are read only.</description>
+                <resetValue>0x00000065</resetValue>
+                <fields>
+                    <field>
+                        <name>STOP_DET_IF_MASTER_ACTIVE</name>
+                        <description>Master issues the STOP_DET interrupt irrespective of whether master is active or not</description>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>RX_FIFO_FULL_HLD_CTRL</name>
+                        <description>This bit controls whether DW_apb_i2c should hold the bus when the Rx FIFO is physically full to its RX_BUFFER_DEPTH, as described in the IC_RX_FULL_HLD_BUS_EN parameter.
+
+                            Reset value: 0x0.</description>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>DISABLED</name>
+                                <value>0</value>
+                                <description>Overflow when RX_FIFO is full</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ENABLED</name>
+                                <value>1</value>
+                                <description>Hold bus when RX_FIFO is full</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>TX_EMPTY_CTRL</name>
+                        <description>This bit controls the generation of the TX_EMPTY interrupt, as described in the IC_RAW_INTR_STAT register.
+
+                            Reset value: 0x0.</description>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>DISABLED</name>
+                                <value>0</value>
+                                <description>Default behaviour of TX_EMPTY interrupt</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ENABLED</name>
+                                <value>1</value>
+                                <description>Controlled generation of TX_EMPTY interrupt</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>STOP_DET_IFADDRESSED</name>
+                        <description>In slave mode: - 1&#39;b1:  issues the STOP_DET interrupt only when it is addressed. - 1&#39;b0:  issues the STOP_DET irrespective of whether it&#39;s addressed or not. Reset value: 0x0
+
+                            NOTE: During a general call address, this slave does not issue the STOP_DET interrupt if STOP_DET_IF_ADDRESSED = 1&#39;b1, even if the slave responds to the general call address by generating ACK. The STOP_DET interrupt is generated only when the transmitted address matches the slave address (SAR).</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>DISABLED</name>
+                                <value>0</value>
+                                <description>slave issues STOP_DET intr always</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ENABLED</name>
+                                <value>1</value>
+                                <description>slave issues STOP_DET intr only if addressed</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>IC_SLAVE_DISABLE</name>
+                        <description>This bit controls whether I2C has its slave disabled, which means once the presetn signal is applied, then this bit is set and the slave is disabled.
+
+                            If this bit is set (slave is disabled), DW_apb_i2c functions only as a master and does not perform any action that requires a slave.
+
+                            NOTE: Software should ensure that if this bit is written with 0, then bit 0 should also be written with a 0.</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>SLAVE_ENABLED</name>
+                                <value>0</value>
+                                <description>Slave mode is enabled</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>SLAVE_DISABLED</name>
+                                <value>1</value>
+                                <description>Slave mode is disabled</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>IC_RESTART_EN</name>
+                        <description>Determines whether RESTART conditions may be sent when acting as a master. Some older slaves do not support handling RESTART conditions; however, RESTART conditions are used in several DW_apb_i2c operations. When RESTART is disabled, the master is prohibited from performing the following functions: - Sending a START BYTE - Performing any high-speed mode operation - High-speed mode operation - Performing direction changes in combined format mode - Performing a read operation with a 10-bit address By replacing RESTART condition followed by a STOP and a subsequent START condition, split operations are broken down into multiple DW_apb_i2c transfers. If the above operations are performed, it will result in setting bit 6 (TX_ABRT) of the IC_RAW_INTR_STAT register.
+
+                            Reset value: ENABLED</description>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>DISABLED</name>
+                                <value>0</value>
+                                <description>Master restart disabled</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ENABLED</name>
+                                <value>1</value>
+                                <description>Master restart enabled</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>IC_10BITADDR_MASTER</name>
+                        <description>Controls whether the DW_apb_i2c starts its transfers in 7- or 10-bit addressing mode when acting as a master. - 0: 7-bit addressing - 1: 10-bit addressing</description>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>ADDR_7BITS</name>
+                                <value>0</value>
+                                <description>Master 7Bit addressing mode</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADDR_10BITS</name>
+                                <value>1</value>
+                                <description>Master 10Bit addressing mode</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>IC_10BITADDR_SLAVE</name>
+                        <description>When acting as a slave, this bit controls whether the DW_apb_i2c responds to 7- or 10-bit addresses. - 0: 7-bit addressing. The DW_apb_i2c ignores transactions that involve 10-bit addressing; for 7-bit addressing, only the lower 7 bits of the IC_SAR register are compared. - 1: 10-bit addressing. The DW_apb_i2c responds to only 10-bit addressing transfers that match the full 10 bits of the IC_SAR register.</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>ADDR_7BITS</name>
+                                <value>0</value>
+                                <description>Slave 7Bit addressing</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ADDR_10BITS</name>
+                                <value>1</value>
+                                <description>Slave 10Bit addressing</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>SPEED</name>
+                        <description>These bits control at which speed the DW_apb_i2c operates; its setting is relevant only if one is operating the DW_apb_i2c in master mode. Hardware protects against illegal values being programmed by software. These bits must be programmed appropriately for slave mode also, as it is used to capture correct value of spike filter as per the speed mode.
+
+                            This register should be programmed only with a value in the range of 1 to IC_MAX_SPEED_MODE; otherwise, hardware updates this register with the value of IC_MAX_SPEED_MODE.
+
+                            1: standard mode (100 kbit/s)
+
+                            2: fast mode (&lt;=400 kbit/s) or fast mode plus (&lt;=1000Kbit/s)
+
+                            3: high speed mode (3.4 Mbit/s)
+
+                            Note: This field is not applicable when IC_ULTRA_FAST_MODE=1</description>
+                        <bitRange>[2:1]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>STANDARD</name>
+                                <value>1</value>
+                                <description>Standard Speed mode of operation</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>FAST</name>
+                                <value>2</value>
+                                <description>Fast or Fast Plus mode of operation</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>HIGH</name>
+                                <value>3</value>
+                                <description>High Speed mode of operation</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>MASTER_MODE</name>
+                        <description>This bit controls whether the DW_apb_i2c master is enabled.
+
+                            NOTE: Software should ensure that if this bit is written with &#39;1&#39; then bit 6 should also be written with a &#39;1&#39;.</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>DISABLED</name>
+                                <value>0</value>
+                                <description>Master mode is disabled</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ENABLED</name>
+                                <value>1</value>
+                                <description>Master mode is enabled</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>IC_TAR</name>
+                <addressOffset>0x00000004</addressOffset>
+                <description>I2C Target Address Register
+
+                    This register is 12 bits wide, and bits 31:12 are reserved. This register can be written to only when IC_ENABLE[0] is set to 0.
+
+                    Note: If the software or application is aware that the DW_apb_i2c is not using the TAR address for the pending commands in the Tx FIFO, then it is possible to update the TAR address even while the Tx FIFO has entries (IC_STATUS[2]= 0). - It is not necessary to perform any write to this register if DW_apb_i2c is enabled as an I2C slave only.</description>
+                <resetValue>0x00000055</resetValue>
+                <fields>
+                    <field>
+                        <name>SPECIAL</name>
+                        <description>This bit indicates whether software performs a Device-ID or General Call or START BYTE command. - 0: ignore bit 10 GC_OR_START and use IC_TAR normally - 1: perform special I2C command as specified in Device_ID or GC_OR_START bit Reset value: 0x0</description>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>DISABLED</name>
+                                <value>0</value>
+                                <description>Disables programming of GENERAL_CALL or START_BYTE transmission</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ENABLED</name>
+                                <value>1</value>
+                                <description>Enables programming of GENERAL_CALL or START_BYTE transmission</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>GC_OR_START</name>
+                        <description>If bit 11 (SPECIAL) is set to 1 and bit 13(Device-ID) is set to 0, then this bit indicates whether a General Call or START byte command is to be performed by the DW_apb_i2c. - 0: General Call Address - after issuing a General Call, only writes may be performed. Attempting to issue a read command results in setting bit 6 (TX_ABRT) of the IC_RAW_INTR_STAT register. The DW_apb_i2c remains in General Call mode until the SPECIAL bit value (bit 11) is cleared. - 1: START BYTE Reset value: 0x0</description>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>GENERAL_CALL</name>
+                                <value>0</value>
+                                <description>GENERAL_CALL byte transmission</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>START_BYTE</name>
+                                <value>1</value>
+                                <description>START byte transmission</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>IC_TAR</name>
+                        <description>This is the target address for any master transaction. When transmitting a General Call, these bits are ignored. To generate a START BYTE, the CPU needs to write only once into these bits.
+
+                            If the IC_TAR and IC_SAR are the same, loopback exists but the FIFOs are shared between master and slave, so full loopback is not feasible. Only one direction loopback mode is supported (simplex), not duplex. A master cannot transmit to itself; it can transmit to only a slave.</description>
+                        <bitRange>[9:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>IC_SAR</name>
+                <addressOffset>0x00000008</addressOffset>
+                <description>I2C Slave Address Register</description>
+                <resetValue>0x00000055</resetValue>
+                <fields>
+                    <field>
+                        <name>IC_SAR</name>
+                        <description>The IC_SAR holds the slave address when the I2C is operating as a slave. For 7-bit addressing, only IC_SAR[6:0] is used.
+
+                            This register can be written only when the I2C interface is disabled, which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect.
+
+                            Note: The default values cannot be any of the reserved address locations: that is, 0x00 to 0x07, or 0x78 to 0x7f. The correct operation of the device is not guaranteed if you program the IC_SAR or IC_TAR to a reserved value. Refer to &lt;&lt;table_I2C_firstbyte_bit_defs&gt;&gt; for a complete list of these reserved values.</description>
+                        <bitRange>[9:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>IC_DATA_CMD</name>
+                <addressOffset>0x00000010</addressOffset>
+                <description>I2C Rx/Tx Data Buffer and Command Register; this is the register the CPU writes to when filling the TX FIFO and the CPU reads from when retrieving bytes from RX FIFO.
+
+                    The size of the register changes as follows:
+
+                    Write: - 11 bits when IC_EMPTYFIFO_HOLD_MASTER_EN=1 - 9 bits when IC_EMPTYFIFO_HOLD_MASTER_EN=0 Read: - 12 bits when IC_FIRST_DATA_BYTE_STATUS = 1 - 8 bits when IC_FIRST_DATA_BYTE_STATUS = 0 Note: In order for the DW_apb_i2c to continue acknowledging reads, a read command should be written for every byte that is to be received; otherwise the DW_apb_i2c will stop acknowledging.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>FIRST_DATA_BYTE</name>
+                        <description>Indicates the first data byte received after the address phase for receive transfer in Master receiver or Slave receiver mode.
+
+                            Reset value : 0x0
+
+                            NOTE:  In case of APB_DATA_WIDTH=8,
+
+                            1. The user has to perform two APB Reads to IC_DATA_CMD in order to get status on 11 bit.
+
+                            2. In order to read the 11 bit, the user has to perform the first data byte read [7:0] (offset 0x10) and then perform the second read [15:8] (offset 0x11) in order to know the status of 11 bit (whether the data received in previous read is a first data byte or not).
+
+                            3. The 11th bit is an optional read field, user can ignore 2nd byte read [15:8] (offset 0x11) if not interested in FIRST_DATA_BYTE status.</description>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>INACTIVE</name>
+                                <value>0</value>
+                                <description>Sequential data byte received</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ACTIVE</name>
+                                <value>1</value>
+                                <description>Non sequential data byte received</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>RESTART</name>
+                        <description>This bit controls whether a RESTART is issued before the byte is sent or received.
+
+                            1 - If IC_RESTART_EN is 1, a RESTART is issued before the data is sent/received (according to the value of CMD), regardless of whether or not the transfer direction is changing from the previous command; if IC_RESTART_EN is 0, a STOP followed by a START is issued instead.
+
+                            0 - If IC_RESTART_EN is 1, a RESTART is issued only if the transfer direction is changing from the previous command; if IC_RESTART_EN is 0, a STOP followed by a START is issued instead.
+
+                            Reset value: 0x0</description>
+                        <bitRange>[10:10]</bitRange>
+                        <access>write-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>DISABLE</name>
+                                <value>0</value>
+                                <description>Don&#39;t Issue RESTART before this command</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ENABLE</name>
+                                <value>1</value>
+                                <description>Issue RESTART before this command</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>STOP</name>
+                        <description>This bit controls whether a STOP is issued after the byte is sent or received.
+
+                            - 1 - STOP is issued after this byte, regardless of whether or not the Tx FIFO is empty. If the Tx FIFO is not empty, the master immediately tries to start a new transfer by issuing a START and arbitrating for the bus. - 0 - STOP is not issued after this byte, regardless of whether or not the Tx FIFO is empty. If the Tx FIFO is not empty, the master continues the current transfer by sending/receiving data bytes according to the value of the CMD bit. If the Tx FIFO is empty, the master holds the SCL line low and stalls the bus until a new command is available in the Tx FIFO. Reset value: 0x0</description>
+                        <bitRange>[9:9]</bitRange>
+                        <access>write-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>DISABLE</name>
+                                <value>0</value>
+                                <description>Don&#39;t Issue STOP after this command</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ENABLE</name>
+                                <value>1</value>
+                                <description>Issue STOP after this command</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>CMD</name>
+                        <description>This bit controls whether a read or a write is performed. This bit does not control the direction when the DW_apb_i2con acts as a slave. It controls only the direction when it acts as a master.
+
+                            When a command is entered in the TX FIFO, this bit distinguishes the write and read commands. In slave-receiver mode, this bit is a &#39;don&#39;t care&#39; because writes to this register are not required. In slave-transmitter mode, a &#39;0&#39; indicates that the data in IC_DATA_CMD is to be transmitted.
+
+                            When programming this bit, you should remember the following: attempting to perform a read operation after a General Call command has been sent results in a TX_ABRT interrupt (bit 6 of the IC_RAW_INTR_STAT register), unless bit 11 (SPECIAL) in the IC_TAR register has been cleared. If a &#39;1&#39; is written to this bit after receiving a RD_REQ interrupt, then a TX_ABRT interrupt occurs.
+
+                            Reset value: 0x0</description>
+                        <bitRange>[8:8]</bitRange>
+                        <access>write-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>WRITE</name>
+                                <value>0</value>
+                                <description>Master Write Command</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>READ</name>
+                                <value>1</value>
+                                <description>Master Read Command</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>DAT</name>
+                        <description>This register contains the data to be transmitted or received on the I2C bus. If you are writing to this register and want to perform a read, bits 7:0 (DAT) are ignored by the DW_apb_i2c. However, when you read this register, these bits return the value of data received on the DW_apb_i2c interface.
+
+                            Reset value: 0x0</description>
+                        <bitRange>[7:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>IC_SS_SCL_HCNT</name>
+                <addressOffset>0x00000014</addressOffset>
+                <description>Standard Speed I2C Clock SCL High Count Register</description>
+                <resetValue>0x00000028</resetValue>
+                <fields>
+                    <field>
+                        <name>IC_SS_SCL_HCNT</name>
+                        <description>This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock high-period count for standard speed. For more information, refer to &#39;IC_CLK Frequency Configuration&#39;.
+
+                            This register can be written only when the I2C interface is disabled which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect.
+
+                            The minimum valid value is 6; hardware prevents values less than this being written, and if attempted results in 6 being set. For designs with APB_DATA_WIDTH = 8, the order of programming is important to ensure the correct operation of the DW_apb_i2c. The lower byte must be programmed first. Then the upper byte is programmed.
+
+                            NOTE: This register must not be programmed to a value higher than 65525, because DW_apb_i2c uses a 16-bit counter to flag an I2C bus idle condition when this counter reaches a value of IC_SS_SCL_HCNT + 10.</description>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>IC_SS_SCL_LCNT</name>
+                <addressOffset>0x00000018</addressOffset>
+                <description>Standard Speed I2C Clock SCL Low Count Register</description>
+                <resetValue>0x0000002f</resetValue>
+                <fields>
+                    <field>
+                        <name>IC_SS_SCL_LCNT</name>
+                        <description>This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock low period count for standard speed. For more information, refer to &#39;IC_CLK Frequency Configuration&#39;
+
+                            This register can be written only when the I2C interface is disabled which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect.
+
+                            The minimum valid value is 8; hardware prevents values less than this being written, and if attempted, results in 8 being set. For designs with APB_DATA_WIDTH = 8, the order of programming is important to ensure the correct operation of DW_apb_i2c. The lower byte must be programmed first, and then the upper byte is programmed.</description>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>IC_FS_SCL_HCNT</name>
+                <addressOffset>0x0000001c</addressOffset>
+                <description>Fast Mode or Fast Mode Plus I2C Clock SCL High Count Register</description>
+                <resetValue>0x00000006</resetValue>
+                <fields>
+                    <field>
+                        <name>IC_FS_SCL_HCNT</name>
+                        <description>This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock high-period count for fast mode or fast mode plus. It is used in high-speed mode to send the Master Code and START BYTE or General CALL. For more information, refer to &#39;IC_CLK Frequency Configuration&#39;.
+
+                            This register goes away and becomes read-only returning 0s if IC_MAX_SPEED_MODE = standard. This register can be written only when the I2C interface is disabled, which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect.
+
+                            The minimum valid value is 6; hardware prevents values less than this being written, and if attempted results in 6 being set. For designs with APB_DATA_WIDTH == 8 the order of programming is important to ensure the correct operation of the DW_apb_i2c. The lower byte must be programmed first. Then the upper byte is programmed.</description>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>IC_FS_SCL_LCNT</name>
+                <addressOffset>0x00000020</addressOffset>
+                <description>Fast Mode or Fast Mode Plus I2C Clock SCL Low Count Register</description>
+                <resetValue>0x0000000d</resetValue>
+                <fields>
+                    <field>
+                        <name>IC_FS_SCL_LCNT</name>
+                        <description>This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock low period count for fast speed. It is used in high-speed mode to send the Master Code and START BYTE or General CALL. For more information, refer to &#39;IC_CLK Frequency Configuration&#39;.
+
+                            This register goes away and becomes read-only returning 0s if IC_MAX_SPEED_MODE = standard.
+
+                            This register can be written only when the I2C interface is disabled, which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect.
+
+                            The minimum valid value is 8; hardware prevents values less than this being written, and if attempted results in 8 being set. For designs with APB_DATA_WIDTH = 8 the order of programming is important to ensure the correct operation of the DW_apb_i2c. The lower byte must be programmed first. Then the upper byte is programmed. If the value is less than 8 then the count value gets changed to 8.</description>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>IC_INTR_STAT</name>
+                <addressOffset>0x0000002c</addressOffset>
+                <description>I2C Interrupt Status Register
+
+                    Each bit in this register has a corresponding mask bit in the IC_INTR_MASK register. These bits are cleared by reading the matching interrupt clear register. The unmasked raw versions of these bits are available in the IC_RAW_INTR_STAT register.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>R_RESTART_DET</name>
+                        <description>See IC_RAW_INTR_STAT for a detailed description of R_RESTART_DET bit.
+
+                            Reset value: 0x0</description>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>INACTIVE</name>
+                                <value>0</value>
+                                <description>R_RESTART_DET interrupt is inactive</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ACTIVE</name>
+                                <value>1</value>
+                                <description>R_RESTART_DET interrupt is active</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>R_GEN_CALL</name>
+                        <description>See IC_RAW_INTR_STAT for a detailed description of R_GEN_CALL bit.
+
+                            Reset value: 0x0</description>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>INACTIVE</name>
+                                <value>0</value>
+                                <description>R_GEN_CALL interrupt is inactive</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ACTIVE</name>
+                                <value>1</value>
+                                <description>R_GEN_CALL interrupt is active</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>R_START_DET</name>
+                        <description>See IC_RAW_INTR_STAT for a detailed description of R_START_DET bit.
+
+                            Reset value: 0x0</description>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>INACTIVE</name>
+                                <value>0</value>
+                                <description>R_START_DET interrupt is inactive</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ACTIVE</name>
+                                <value>1</value>
+                                <description>R_START_DET interrupt is active</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>R_STOP_DET</name>
+                        <description>See IC_RAW_INTR_STAT for a detailed description of R_STOP_DET bit.
+
+                            Reset value: 0x0</description>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>INACTIVE</name>
+                                <value>0</value>
+                                <description>R_STOP_DET interrupt is inactive</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ACTIVE</name>
+                                <value>1</value>
+                                <description>R_STOP_DET interrupt is active</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>R_ACTIVITY</name>
+                        <description>See IC_RAW_INTR_STAT for a detailed description of R_ACTIVITY bit.
+
+                            Reset value: 0x0</description>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>INACTIVE</name>
+                                <value>0</value>
+                                <description>R_ACTIVITY interrupt is inactive</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ACTIVE</name>
+                                <value>1</value>
+                                <description>R_ACTIVITY interrupt is active</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>R_RX_DONE</name>
+                        <description>See IC_RAW_INTR_STAT for a detailed description of R_RX_DONE bit.
+
+                            Reset value: 0x0</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>INACTIVE</name>
+                                <value>0</value>
+                                <description>R_RX_DONE interrupt is inactive</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ACTIVE</name>
+                                <value>1</value>
+                                <description>R_RX_DONE interrupt is active</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>R_TX_ABRT</name>
+                        <description>See IC_RAW_INTR_STAT for a detailed description of R_TX_ABRT bit.
+
+                            Reset value: 0x0</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>INACTIVE</name>
+                                <value>0</value>
+                                <description>R_TX_ABRT interrupt is inactive</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ACTIVE</name>
+                                <value>1</value>
+                                <description>R_TX_ABRT interrupt is active</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>R_RD_REQ</name>
+                        <description>See IC_RAW_INTR_STAT for a detailed description of R_RD_REQ bit.
+
+                            Reset value: 0x0</description>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>INACTIVE</name>
+                                <value>0</value>
+                                <description>R_RD_REQ interrupt is inactive</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ACTIVE</name>
+                                <value>1</value>
+                                <description>R_RD_REQ interrupt is active</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>R_TX_EMPTY</name>
+                        <description>See IC_RAW_INTR_STAT for a detailed description of R_TX_EMPTY bit.
+
+                            Reset value: 0x0</description>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>INACTIVE</name>
+                                <value>0</value>
+                                <description>R_TX_EMPTY interrupt is inactive</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ACTIVE</name>
+                                <value>1</value>
+                                <description>R_TX_EMPTY interrupt is active</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>R_TX_OVER</name>
+                        <description>See IC_RAW_INTR_STAT for a detailed description of R_TX_OVER bit.
+
+                            Reset value: 0x0</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>INACTIVE</name>
+                                <value>0</value>
+                                <description>R_TX_OVER interrupt is inactive</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ACTIVE</name>
+                                <value>1</value>
+                                <description>R_TX_OVER interrupt is active</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>R_RX_FULL</name>
+                        <description>See IC_RAW_INTR_STAT for a detailed description of R_RX_FULL bit.
+
+                            Reset value: 0x0</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>INACTIVE</name>
+                                <value>0</value>
+                                <description>R_RX_FULL interrupt is inactive</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ACTIVE</name>
+                                <value>1</value>
+                                <description>R_RX_FULL interrupt is active</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>R_RX_OVER</name>
+                        <description>See IC_RAW_INTR_STAT for a detailed description of R_RX_OVER bit.
+
+                            Reset value: 0x0</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>INACTIVE</name>
+                                <value>0</value>
+                                <description>R_RX_OVER interrupt is inactive</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ACTIVE</name>
+                                <value>1</value>
+                                <description>R_RX_OVER interrupt is active</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>R_RX_UNDER</name>
+                        <description>See IC_RAW_INTR_STAT for a detailed description of R_RX_UNDER bit.
+
+                            Reset value: 0x0</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>INACTIVE</name>
+                                <value>0</value>
+                                <description>RX_UNDER interrupt is inactive</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ACTIVE</name>
+                                <value>1</value>
+                                <description>RX_UNDER interrupt is active</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>IC_INTR_MASK</name>
+                <addressOffset>0x00000030</addressOffset>
+                <description>I2C Interrupt Mask Register.
+
+                    These bits mask their corresponding interrupt status bits. This register is active low; a value of 0 masks the interrupt, whereas a value of 1 unmasks the interrupt.</description>
+                <resetValue>0x000008ff</resetValue>
+                <fields>
+                    <field>
+                        <name>M_RESTART_DET</name>
+                        <description>This bit masks the R_RESTART_DET interrupt in IC_INTR_STAT register.
+
+                            Reset value: 0x0</description>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>ENABLED</name>
+                                <value>0</value>
+                                <description>RESTART_DET interrupt is masked</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>DISABLED</name>
+                                <value>1</value>
+                                <description>RESTART_DET interrupt is unmasked</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>M_GEN_CALL</name>
+                        <description>This bit masks the R_GEN_CALL interrupt in IC_INTR_STAT register.
+
+                            Reset value: 0x1</description>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>ENABLED</name>
+                                <value>0</value>
+                                <description>GEN_CALL interrupt is masked</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>DISABLED</name>
+                                <value>1</value>
+                                <description>GEN_CALL interrupt is unmasked</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>M_START_DET</name>
+                        <description>This bit masks the R_START_DET interrupt in IC_INTR_STAT register.
+
+                            Reset value: 0x0</description>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>ENABLED</name>
+                                <value>0</value>
+                                <description>START_DET interrupt is masked</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>DISABLED</name>
+                                <value>1</value>
+                                <description>START_DET interrupt is unmasked</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>M_STOP_DET</name>
+                        <description>This bit masks the R_STOP_DET interrupt in IC_INTR_STAT register.
+
+                            Reset value: 0x0</description>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>ENABLED</name>
+                                <value>0</value>
+                                <description>STOP_DET interrupt is masked</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>DISABLED</name>
+                                <value>1</value>
+                                <description>STOP_DET interrupt is unmasked</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>M_ACTIVITY</name>
+                        <description>This bit masks the R_ACTIVITY interrupt in IC_INTR_STAT register.
+
+                            Reset value: 0x0</description>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>ENABLED</name>
+                                <value>0</value>
+                                <description>ACTIVITY interrupt is masked</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>DISABLED</name>
+                                <value>1</value>
+                                <description>ACTIVITY interrupt is unmasked</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>M_RX_DONE</name>
+                        <description>This bit masks the R_RX_DONE interrupt in IC_INTR_STAT register.
+
+                            Reset value: 0x1</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>ENABLED</name>
+                                <value>0</value>
+                                <description>RX_DONE interrupt is masked</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>DISABLED</name>
+                                <value>1</value>
+                                <description>RX_DONE interrupt is unmasked</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>M_TX_ABRT</name>
+                        <description>This bit masks the R_TX_ABRT interrupt in IC_INTR_STAT register.
+
+                            Reset value: 0x1</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>ENABLED</name>
+                                <value>0</value>
+                                <description>TX_ABORT interrupt is masked</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>DISABLED</name>
+                                <value>1</value>
+                                <description>TX_ABORT interrupt is unmasked</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>M_RD_REQ</name>
+                        <description>This bit masks the R_RD_REQ interrupt in IC_INTR_STAT register.
+
+                            Reset value: 0x1</description>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>ENABLED</name>
+                                <value>0</value>
+                                <description>RD_REQ interrupt is masked</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>DISABLED</name>
+                                <value>1</value>
+                                <description>RD_REQ interrupt is unmasked</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>M_TX_EMPTY</name>
+                        <description>This bit masks the R_TX_EMPTY interrupt in IC_INTR_STAT register.
+
+                            Reset value: 0x1</description>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>ENABLED</name>
+                                <value>0</value>
+                                <description>TX_EMPTY interrupt is masked</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>DISABLED</name>
+                                <value>1</value>
+                                <description>TX_EMPTY interrupt is unmasked</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>M_TX_OVER</name>
+                        <description>This bit masks the R_TX_OVER interrupt in IC_INTR_STAT register.
+
+                            Reset value: 0x1</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>ENABLED</name>
+                                <value>0</value>
+                                <description>TX_OVER interrupt is masked</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>DISABLED</name>
+                                <value>1</value>
+                                <description>TX_OVER interrupt is unmasked</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>M_RX_FULL</name>
+                        <description>This bit masks the R_RX_FULL interrupt in IC_INTR_STAT register.
+
+                            Reset value: 0x1</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>ENABLED</name>
+                                <value>0</value>
+                                <description>RX_FULL interrupt is masked</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>DISABLED</name>
+                                <value>1</value>
+                                <description>RX_FULL interrupt is unmasked</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>M_RX_OVER</name>
+                        <description>This bit masks the R_RX_OVER interrupt in IC_INTR_STAT register.
+
+                            Reset value: 0x1</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>ENABLED</name>
+                                <value>0</value>
+                                <description>RX_OVER interrupt is masked</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>DISABLED</name>
+                                <value>1</value>
+                                <description>RX_OVER interrupt is unmasked</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>M_RX_UNDER</name>
+                        <description>This bit masks the R_RX_UNDER interrupt in IC_INTR_STAT register.
+
+                            Reset value: 0x1</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>ENABLED</name>
+                                <value>0</value>
+                                <description>RX_UNDER interrupt is masked</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>DISABLED</name>
+                                <value>1</value>
+                                <description>RX_UNDER interrupt is unmasked</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>IC_RAW_INTR_STAT</name>
+                <addressOffset>0x00000034</addressOffset>
+                <description>I2C Raw Interrupt Status Register
+
+                    Unlike the IC_INTR_STAT register, these bits are not masked so they always show the true status of the DW_apb_i2c.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>RESTART_DET</name>
+                        <description>Indicates whether a RESTART condition has occurred on the I2C interface when DW_apb_i2c is operating in Slave mode and the slave is being addressed. Enabled only when IC_SLV_RESTART_DET_EN=1.
+
+                            Note: However, in high-speed mode or during a START BYTE transfer, the RESTART comes before the address field as per the I2C protocol. In this case, the slave is not the addressed slave when the RESTART is issued, therefore DW_apb_i2c does not generate the RESTART_DET interrupt.
+
+                            Reset value: 0x0</description>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>INACTIVE</name>
+                                <value>0</value>
+                                <description>RESTART_DET interrupt is inactive</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ACTIVE</name>
+                                <value>1</value>
+                                <description>RESTART_DET interrupt is active</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>GEN_CALL</name>
+                        <description>Set only when a General Call address is received and it is acknowledged. It stays set until it is cleared either by disabling DW_apb_i2c or when the CPU reads bit 0 of the IC_CLR_GEN_CALL register. DW_apb_i2c stores the received data in the Rx buffer.
+
+                            Reset value: 0x0</description>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>INACTIVE</name>
+                                <value>0</value>
+                                <description>GEN_CALL interrupt is inactive</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ACTIVE</name>
+                                <value>1</value>
+                                <description>GEN_CALL interrupt is active</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>START_DET</name>
+                        <description>Indicates whether a START or RESTART condition has occurred on the I2C interface regardless of whether DW_apb_i2c is operating in slave or master mode.
+
+                            Reset value: 0x0</description>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>INACTIVE</name>
+                                <value>0</value>
+                                <description>START_DET interrupt is inactive</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ACTIVE</name>
+                                <value>1</value>
+                                <description>START_DET interrupt is active</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>STOP_DET</name>
+                        <description>Indicates whether a STOP condition has occurred on the I2C interface regardless of whether DW_apb_i2c is operating in slave or master mode.
+
+                            In Slave Mode: - If IC_CON[7]=1&#39;b1  (STOP_DET_IFADDRESSED), the STOP_DET interrupt will be issued only if slave is addressed. Note: During a general call address, this slave does not issue a STOP_DET interrupt if STOP_DET_IF_ADDRESSED=1&#39;b1, even if the slave responds to the general call address by generating ACK. The STOP_DET interrupt is generated only when the transmitted address matches the slave address (SAR). - If IC_CON[7]=1&#39;b0 (STOP_DET_IFADDRESSED), the STOP_DET interrupt is issued irrespective of whether it is being addressed. In Master Mode: - If IC_CON[10]=1&#39;b1  (STOP_DET_IF_MASTER_ACTIVE),the STOP_DET interrupt will be issued only if Master is active. - If IC_CON[10]=1&#39;b0  (STOP_DET_IFADDRESSED),the STOP_DET interrupt will be issued irrespective of whether master is active or not. Reset value: 0x0</description>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>INACTIVE</name>
+                                <value>0</value>
+                                <description>STOP_DET interrupt is inactive</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ACTIVE</name>
+                                <value>1</value>
+                                <description>STOP_DET interrupt is active</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>ACTIVITY</name>
+                        <description>This bit captures DW_apb_i2c activity and stays set until it is cleared. There are four ways to clear it: - Disabling the DW_apb_i2c - Reading the IC_CLR_ACTIVITY register - Reading the IC_CLR_INTR register - System reset Once this bit is set, it stays set unless one of the four methods is used to clear it. Even if the DW_apb_i2c module is idle, this bit remains set until cleared, indicating that there was activity on the bus.
+
+                            Reset value: 0x0</description>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>INACTIVE</name>
+                                <value>0</value>
+                                <description>RAW_INTR_ACTIVITY interrupt is inactive</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ACTIVE</name>
+                                <value>1</value>
+                                <description>RAW_INTR_ACTIVITY interrupt is active</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>RX_DONE</name>
+                        <description>When the DW_apb_i2c is acting as a slave-transmitter, this bit is set to 1 if the master does not acknowledge a transmitted byte. This occurs on the last byte of the transmission, indicating that the transmission is done.
+
+                            Reset value: 0x0</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>INACTIVE</name>
+                                <value>0</value>
+                                <description>RX_DONE interrupt is inactive</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ACTIVE</name>
+                                <value>1</value>
+                                <description>RX_DONE interrupt is active</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>TX_ABRT</name>
+                        <description>This bit indicates if DW_apb_i2c, as an I2C transmitter, is unable to complete the intended actions on the contents of the transmit FIFO. This situation can occur both as an I2C master or an I2C slave, and is referred to as a &#39;transmit abort&#39;. When this bit is set to 1, the IC_TX_ABRT_SOURCE register indicates the reason why the transmit abort takes places.
+
+                            Note:  The DW_apb_i2c flushes/resets/empties the TX_FIFO and RX_FIFO whenever there is a transmit abort caused by any of the events tracked by the IC_TX_ABRT_SOURCE register. The FIFOs remains in this flushed state until the register IC_CLR_TX_ABRT is read. Once this read is performed, the Tx FIFO is then ready to accept more data bytes from the APB interface.
+
+                            Reset value: 0x0</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>INACTIVE</name>
+                                <value>0</value>
+                                <description>TX_ABRT interrupt is inactive</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ACTIVE</name>
+                                <value>1</value>
+                                <description>TX_ABRT interrupt is active</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>RD_REQ</name>
+                        <description>This bit is set to 1 when DW_apb_i2c is acting as a slave and another I2C master is attempting to read data from DW_apb_i2c. The DW_apb_i2c holds the I2C bus in a wait state (SCL=0) until this interrupt is serviced, which means that the slave has been addressed by a remote master that is asking for data to be transferred. The processor must respond to this interrupt and then write the requested data to the IC_DATA_CMD register. This bit is set to 0 just after the processor reads the IC_CLR_RD_REQ register.
+
+                            Reset value: 0x0</description>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>INACTIVE</name>
+                                <value>0</value>
+                                <description>RD_REQ interrupt is inactive</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ACTIVE</name>
+                                <value>1</value>
+                                <description>RD_REQ interrupt is active</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>TX_EMPTY</name>
+                        <description>The behavior of the TX_EMPTY interrupt status differs based on the TX_EMPTY_CTRL selection in the IC_CON register. - When TX_EMPTY_CTRL = 0: This bit is set to 1 when the transmit buffer is at or below the threshold value set in the IC_TX_TL register. - When TX_EMPTY_CTRL = 1: This bit is set to 1 when the transmit buffer is at or below the threshold value set in the IC_TX_TL register and the transmission of the address/data from the internal shift register for the most recently popped command is completed. It is automatically cleared by hardware when the buffer level goes above the threshold. When IC_ENABLE[0] is set to 0, the TX FIFO is flushed and held in reset. There the TX FIFO looks like it has no data within it, so this bit is set to 1, provided there is activity in the master or slave state machines. When there is no longer any activity, then with ic_en=0, this bit is set to 0.
+
+                            Reset value: 0x0.</description>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>INACTIVE</name>
+                                <value>0</value>
+                                <description>TX_EMPTY interrupt is inactive</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ACTIVE</name>
+                                <value>1</value>
+                                <description>TX_EMPTY interrupt is active</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>TX_OVER</name>
+                        <description>Set during transmit if the transmit buffer is filled to IC_TX_BUFFER_DEPTH and the processor attempts to issue another I2C command by writing to the IC_DATA_CMD register. When the module is disabled, this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared.
+
+                            Reset value: 0x0</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>INACTIVE</name>
+                                <value>0</value>
+                                <description>TX_OVER interrupt is inactive</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ACTIVE</name>
+                                <value>1</value>
+                                <description>TX_OVER interrupt is active</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>RX_FULL</name>
+                        <description>Set when the receive buffer reaches or goes above the RX_TL threshold in the IC_RX_TL register. It is automatically cleared by hardware when buffer level goes below the threshold. If the module is disabled (IC_ENABLE[0]=0), the RX FIFO is flushed and held in reset; therefore the RX FIFO is not full. So this bit is cleared once the IC_ENABLE bit 0 is programmed with a 0, regardless of the activity that continues.
+
+                            Reset value: 0x0</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>INACTIVE</name>
+                                <value>0</value>
+                                <description>RX_FULL interrupt is inactive</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ACTIVE</name>
+                                <value>1</value>
+                                <description>RX_FULL interrupt is active</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>RX_OVER</name>
+                        <description>Set if the receive buffer is completely filled to IC_RX_BUFFER_DEPTH and an additional byte is received from an external I2C device. The DW_apb_i2c acknowledges this, but any data bytes received after the FIFO is full are lost. If the module is disabled (IC_ENABLE[0]=0), this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared.
+
+                            Note:  If bit 9 of the IC_CON register (RX_FIFO_FULL_HLD_CTRL) is programmed to HIGH, then the RX_OVER interrupt never occurs, because the Rx FIFO never overflows.
+
+                            Reset value: 0x0</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>INACTIVE</name>
+                                <value>0</value>
+                                <description>RX_OVER interrupt is inactive</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ACTIVE</name>
+                                <value>1</value>
+                                <description>RX_OVER interrupt is active</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>RX_UNDER</name>
+                        <description>Set if the processor attempts to read the receive buffer when it is empty by reading from the IC_DATA_CMD register. If the module is disabled (IC_ENABLE[0]=0), this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared.
+
+                            Reset value: 0x0</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>INACTIVE</name>
+                                <value>0</value>
+                                <description>RX_UNDER interrupt is inactive</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ACTIVE</name>
+                                <value>1</value>
+                                <description>RX_UNDER interrupt is active</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>IC_RX_TL</name>
+                <addressOffset>0x00000038</addressOffset>
+                <description>I2C Receive FIFO Threshold Register</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>RX_TL</name>
+                        <description>Receive FIFO Threshold Level.
+
+                            Controls the level of entries (or above) that triggers the RX_FULL interrupt (bit 2 in IC_RAW_INTR_STAT register). The valid range is 0-255, with the additional restriction that hardware does not allow this value to be set to a value larger than the depth of the buffer. If an attempt is made to do that, the actual value set will be the maximum depth of the buffer. A value of 0 sets the threshold for 1 entry, and a value of 255 sets the threshold for 256 entries.</description>
+                        <bitRange>[7:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>IC_TX_TL</name>
+                <addressOffset>0x0000003c</addressOffset>
+                <description>I2C Transmit FIFO Threshold Register</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>TX_TL</name>
+                        <description>Transmit FIFO Threshold Level.
+
+                            Controls the level of entries (or below) that trigger the TX_EMPTY interrupt (bit 4 in IC_RAW_INTR_STAT register). The valid range is 0-255, with the additional restriction that it may not be set to value larger than the depth of the buffer. If an attempt is made to do that, the actual value set will be the maximum depth of the buffer. A value of 0 sets the threshold for 0 entries, and a value of 255 sets the threshold for 255 entries.</description>
+                        <bitRange>[7:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>IC_CLR_INTR</name>
+                <addressOffset>0x00000040</addressOffset>
+                <description>Clear Combined and Individual Interrupt Register</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CLR_INTR</name>
+                        <description>Read this register to clear the combined interrupt, all individual interrupts, and the IC_TX_ABRT_SOURCE register. This bit does not clear hardware clearable interrupts but software clearable interrupts. Refer to Bit 9 of the IC_TX_ABRT_SOURCE register for an exception to clearing IC_TX_ABRT_SOURCE.
+
+                            Reset value: 0x0</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>IC_CLR_RX_UNDER</name>
+                <addressOffset>0x00000044</addressOffset>
+                <description>Clear RX_UNDER Interrupt Register</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CLR_RX_UNDER</name>
+                        <description>Read this register to clear the RX_UNDER interrupt (bit 0) of the IC_RAW_INTR_STAT register.
+
+                            Reset value: 0x0</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>IC_CLR_RX_OVER</name>
+                <addressOffset>0x00000048</addressOffset>
+                <description>Clear RX_OVER Interrupt Register</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CLR_RX_OVER</name>
+                        <description>Read this register to clear the RX_OVER interrupt (bit 1) of the IC_RAW_INTR_STAT register.
+
+                            Reset value: 0x0</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>IC_CLR_TX_OVER</name>
+                <addressOffset>0x0000004c</addressOffset>
+                <description>Clear TX_OVER Interrupt Register</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CLR_TX_OVER</name>
+                        <description>Read this register to clear the TX_OVER interrupt (bit 3) of the IC_RAW_INTR_STAT register.
+
+                            Reset value: 0x0</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>IC_CLR_RD_REQ</name>
+                <addressOffset>0x00000050</addressOffset>
+                <description>Clear RD_REQ Interrupt Register</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CLR_RD_REQ</name>
+                        <description>Read this register to clear the RD_REQ interrupt (bit 5) of the IC_RAW_INTR_STAT register.
+
+                            Reset value: 0x0</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>IC_CLR_TX_ABRT</name>
+                <addressOffset>0x00000054</addressOffset>
+                <description>Clear TX_ABRT Interrupt Register</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CLR_TX_ABRT</name>
+                        <description>Read this register to clear the TX_ABRT interrupt (bit 6) of the IC_RAW_INTR_STAT register, and the IC_TX_ABRT_SOURCE register. This also releases the TX FIFO from the flushed/reset state, allowing more writes to the TX FIFO. Refer to Bit 9 of the IC_TX_ABRT_SOURCE register for an exception to clearing IC_TX_ABRT_SOURCE.
+
+                            Reset value: 0x0</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>IC_CLR_RX_DONE</name>
+                <addressOffset>0x00000058</addressOffset>
+                <description>Clear RX_DONE Interrupt Register</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CLR_RX_DONE</name>
+                        <description>Read this register to clear the RX_DONE interrupt (bit 7) of the IC_RAW_INTR_STAT register.
+
+                            Reset value: 0x0</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>IC_CLR_ACTIVITY</name>
+                <addressOffset>0x0000005c</addressOffset>
+                <description>Clear ACTIVITY Interrupt Register</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CLR_ACTIVITY</name>
+                        <description>Reading this register clears the ACTIVITY interrupt if the I2C is not active anymore. If the I2C module is still active on the bus, the ACTIVITY interrupt bit continues to be set. It is automatically cleared by hardware if the module is disabled and if there is no further activity on the bus. The value read from this register to get status of the ACTIVITY interrupt (bit 8) of the IC_RAW_INTR_STAT register.
+
+                            Reset value: 0x0</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>IC_CLR_STOP_DET</name>
+                <addressOffset>0x00000060</addressOffset>
+                <description>Clear STOP_DET Interrupt Register</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CLR_STOP_DET</name>
+                        <description>Read this register to clear the STOP_DET interrupt (bit 9) of the IC_RAW_INTR_STAT register.
+
+                            Reset value: 0x0</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>IC_CLR_START_DET</name>
+                <addressOffset>0x00000064</addressOffset>
+                <description>Clear START_DET Interrupt Register</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CLR_START_DET</name>
+                        <description>Read this register to clear the START_DET interrupt (bit 10) of the IC_RAW_INTR_STAT register.
+
+                            Reset value: 0x0</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>IC_CLR_GEN_CALL</name>
+                <addressOffset>0x00000068</addressOffset>
+                <description>Clear GEN_CALL Interrupt Register</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CLR_GEN_CALL</name>
+                        <description>Read this register to clear the GEN_CALL interrupt (bit 11) of IC_RAW_INTR_STAT register.
+
+                            Reset value: 0x0</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>IC_ENABLE</name>
+                <addressOffset>0x0000006c</addressOffset>
+                <description>I2C Enable Register</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>TX_CMD_BLOCK</name>
+                        <description>In Master mode: - 1&#39;b1: Blocks the transmission of data on I2C bus even if Tx FIFO has data to transmit. - 1&#39;b0: The transmission of data starts on I2C bus automatically, as soon as the first data is available in the Tx FIFO. Note: To block the execution of Master commands, set the TX_CMD_BLOCK bit only when Tx FIFO is empty (IC_STATUS[2]==1) and Master is in Idle state (IC_STATUS[5] == 0). Any further commands put in the Tx FIFO are not executed until TX_CMD_BLOCK bit is unset. Reset value:  IC_TX_CMD_BLOCK_DEFAULT</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NOT_BLOCKED</name>
+                                <value>0</value>
+                                <description>Tx Command execution not blocked</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>BLOCKED</name>
+                                <value>1</value>
+                                <description>Tx Command execution blocked</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>ABORT</name>
+                        <description>When set, the controller initiates the transfer abort. - 0: ABORT not initiated or ABORT done - 1: ABORT operation in progress The software can abort the I2C transfer in master mode by setting this bit. The software can set this bit only when ENABLE is already set; otherwise, the controller ignores any write to ABORT bit. The software cannot clear the ABORT bit once set. In response to an ABORT, the controller issues a STOP and flushes the Tx FIFO after completing the current transfer, then sets the TX_ABORT interrupt after the abort operation. The ABORT bit is cleared automatically after the abort operation.
+
+                            For a detailed description on how to abort I2C transfers, refer to &#39;Aborting I2C Transfers&#39;.
+
+                            Reset value: 0x0</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>DISABLE</name>
+                                <value>0</value>
+                                <description>ABORT operation not in progress</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ENABLED</name>
+                                <value>1</value>
+                                <description>ABORT operation in progress</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>ENABLE</name>
+                        <description>Controls whether the DW_apb_i2c is enabled. - 0: Disables DW_apb_i2c (TX and RX FIFOs are held in an erased state) - 1: Enables DW_apb_i2c Software can disable DW_apb_i2c while it is active. However, it is important that care be taken to ensure that DW_apb_i2c is disabled properly. A recommended procedure is described in &#39;Disabling DW_apb_i2c&#39;.
+
+                            When DW_apb_i2c is disabled, the following occurs: - The TX FIFO and RX FIFO get flushed. - Status bits in the IC_INTR_STAT register are still active until DW_apb_i2c goes into IDLE state. If the module is transmitting, it stops as well as deletes the contents of the transmit buffer after the current transfer is complete. If the module is receiving, the DW_apb_i2c stops the current transfer at the end of the current byte and does not acknowledge the transfer.
+
+                            In systems with asynchronous pclk and ic_clk when IC_CLK_TYPE parameter set to asynchronous (1), there is a two ic_clk delay when enabling or disabling the DW_apb_i2c. For a detailed description on how to disable DW_apb_i2c, refer to &#39;Disabling DW_apb_i2c&#39;
+
+                            Reset value: 0x0</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>DISABLED</name>
+                                <value>0</value>
+                                <description>I2C is disabled</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ENABLED</name>
+                                <value>1</value>
+                                <description>I2C is enabled</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>IC_STATUS</name>
+                <addressOffset>0x00000070</addressOffset>
+                <description>I2C Status Register
+
+                    This is a read-only register used to indicate the current transfer status and FIFO status. The status register may be read at any time. None of the bits in this register request an interrupt.
+
+                    When the I2C is disabled by writing 0 in bit 0 of the IC_ENABLE register: - Bits 1 and 2 are set to 1 - Bits 3 and 10 are set to 0 When the master or slave state machines goes to idle and ic_en=0: - Bits 5 and 6 are set to 0</description>
+                <resetValue>0x00000006</resetValue>
+                <fields>
+                    <field>
+                        <name>SLV_ACTIVITY</name>
+                        <description>Slave FSM Activity Status. When the Slave Finite State Machine (FSM) is not in the IDLE state, this bit is set. - 0: Slave FSM is in IDLE state so the Slave part of DW_apb_i2c is not Active - 1: Slave FSM is not in IDLE state so the Slave part of DW_apb_i2c is Active Reset value: 0x0</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>IDLE</name>
+                                <value>0</value>
+                                <description>Slave is idle</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ACTIVE</name>
+                                <value>1</value>
+                                <description>Slave not idle</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>MST_ACTIVITY</name>
+                        <description>Master FSM Activity Status. When the Master Finite State Machine (FSM) is not in the IDLE state, this bit is set. - 0: Master FSM is in IDLE state so the Master part of DW_apb_i2c is not Active - 1: Master FSM is not in IDLE state so the Master part of DW_apb_i2c is Active Note: IC_STATUS[0]-that is, ACTIVITY bit-is the OR of SLV_ACTIVITY and MST_ACTIVITY bits.
+
+                            Reset value: 0x0</description>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>IDLE</name>
+                                <value>0</value>
+                                <description>Master is idle</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ACTIVE</name>
+                                <value>1</value>
+                                <description>Master not idle</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>RFF</name>
+                        <description>Receive FIFO Completely Full. When the receive FIFO is completely full, this bit is set. When the receive FIFO contains one or more empty location, this bit is cleared. - 0: Receive FIFO is not full - 1: Receive FIFO is full Reset value: 0x0</description>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NOT_FULL</name>
+                                <value>0</value>
+                                <description>Rx FIFO not full</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>FULL</name>
+                                <value>1</value>
+                                <description>Rx FIFO is full</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>RFNE</name>
+                        <description>Receive FIFO Not Empty. This bit is set when the receive FIFO contains one or more entries; it is cleared when the receive FIFO is empty. - 0: Receive FIFO is empty - 1: Receive FIFO is not empty Reset value: 0x0</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>EMPTY</name>
+                                <value>0</value>
+                                <description>Rx FIFO is empty</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>NOT_EMPTY</name>
+                                <value>1</value>
+                                <description>Rx FIFO not empty</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>TFE</name>
+                        <description>Transmit FIFO Completely Empty. When the transmit FIFO is completely empty, this bit is set. When it contains one or more valid entries, this bit is cleared. This bit field does not request an interrupt. - 0: Transmit FIFO is not empty - 1: Transmit FIFO is empty Reset value: 0x1</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NON_EMPTY</name>
+                                <value>0</value>
+                                <description>Tx FIFO not empty</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>EMPTY</name>
+                                <value>1</value>
+                                <description>Tx FIFO is empty</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>TFNF</name>
+                        <description>Transmit FIFO Not Full. Set when the transmit FIFO contains one or more empty locations, and is cleared when the FIFO is full. - 0: Transmit FIFO is full - 1: Transmit FIFO is not full Reset value: 0x1</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>FULL</name>
+                                <value>0</value>
+                                <description>Tx FIFO is full</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>NOT_FULL</name>
+                                <value>1</value>
+                                <description>Tx FIFO not full</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>ACTIVITY</name>
+                        <description>I2C Activity Status. Reset value: 0x0</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>INACTIVE</name>
+                                <value>0</value>
+                                <description>I2C is idle</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ACTIVE</name>
+                                <value>1</value>
+                                <description>I2C is active</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>IC_TXFLR</name>
+                <addressOffset>0x00000074</addressOffset>
+                <description>I2C Transmit FIFO Level Register This register contains the number of valid data entries in the transmit FIFO buffer. It is cleared whenever: - The I2C is disabled - There is a transmit abort - that is, TX_ABRT bit is set in the IC_RAW_INTR_STAT register - The slave bulk transmit mode is aborted The register increments whenever data is placed into the transmit FIFO and decrements when data is taken from the transmit FIFO.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>TXFLR</name>
+                        <description>Transmit FIFO Level. Contains the number of valid data entries in the transmit FIFO.
+
+                            Reset value: 0x0</description>
+                        <bitRange>[4:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>IC_RXFLR</name>
+                <addressOffset>0x00000078</addressOffset>
+                <description>I2C Receive FIFO Level Register This register contains the number of valid data entries in the receive FIFO buffer. It is cleared whenever: - The I2C is disabled - Whenever there is a transmit abort caused by any of the events tracked in IC_TX_ABRT_SOURCE The register increments whenever data is placed into the receive FIFO and decrements when data is taken from the receive FIFO.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>RXFLR</name>
+                        <description>Receive FIFO Level. Contains the number of valid data entries in the receive FIFO.
+
+                            Reset value: 0x0</description>
+                        <bitRange>[4:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>IC_SDA_HOLD</name>
+                <addressOffset>0x0000007c</addressOffset>
+                <description>I2C SDA Hold Time Length Register
+
+                    The bits [15:0] of this register are used to control the hold time of SDA during transmit in both slave and master mode (after SCL goes from HIGH to LOW).
+
+                    The bits [23:16] of this register are used to extend the SDA transition (if any) whenever SCL is HIGH in the receiver in either master or slave mode.
+
+                    Writes to this register succeed only when IC_ENABLE[0]=0.
+
+                    The values in this register are in units of ic_clk period. The value programmed in IC_SDA_TX_HOLD must be greater than the minimum hold time in each mode (one cycle in master mode, seven cycles in slave mode) for the value to be implemented.
+
+                    The programmed SDA hold time during transmit (IC_SDA_TX_HOLD) cannot exceed at any time the duration of the low part of scl. Therefore the programmed value cannot be larger than N_SCL_LOW-2, where N_SCL_LOW is the duration of the low part of the scl period measured in ic_clk cycles.</description>
+                <resetValue>0x00000001</resetValue>
+                <fields>
+                    <field>
+                        <name>IC_SDA_RX_HOLD</name>
+                        <description>Sets the required SDA hold time in units of ic_clk period, when DW_apb_i2c acts as a receiver.
+
+                            Reset value: IC_DEFAULT_SDA_HOLD[23:16].</description>
+                        <bitRange>[23:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>IC_SDA_TX_HOLD</name>
+                        <description>Sets the required SDA hold time in units of ic_clk period, when DW_apb_i2c acts as a transmitter.
+
+                            Reset value: IC_DEFAULT_SDA_HOLD[15:0].</description>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>IC_TX_ABRT_SOURCE</name>
+                <addressOffset>0x00000080</addressOffset>
+                <description>I2C Transmit Abort Source Register
+
+                    This register has 32 bits that indicate the source of the TX_ABRT bit. Except for Bit 9, this register is cleared whenever the IC_CLR_TX_ABRT register or the IC_CLR_INTR register is read. To clear Bit 9, the source of the ABRT_SBYTE_NORSTRT must be fixed first; RESTART must be enabled (IC_CON[5]=1), the SPECIAL bit must be cleared (IC_TAR[11]), or the GC_OR_START bit must be cleared (IC_TAR[10]).
+
+                    Once the source of the ABRT_SBYTE_NORSTRT is fixed, then this bit can be cleared in the same manner as other bits in this register. If the source of the ABRT_SBYTE_NORSTRT is not fixed before attempting to clear this bit, Bit 9 clears for one cycle and is then re-asserted.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>TX_FLUSH_CNT</name>
+                        <description>This field indicates the number of Tx FIFO Data Commands which are flushed due to TX_ABRT interrupt. It is cleared whenever I2C is disabled.
+
+                            Reset value: 0x0
+
+                            Role of DW_apb_i2c:  Master-Transmitter or Slave-Transmitter</description>
+                        <bitRange>[31:23]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>ABRT_USER_ABRT</name>
+                        <description>This is a master-mode-only bit. Master has detected the transfer abort (IC_ENABLE[1])
+
+                            Reset value: 0x0
+
+                            Role of DW_apb_i2c:  Master-Transmitter</description>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>ABRT_USER_ABRT_VOID</name>
+                                <value>0</value>
+                                <description>Transfer abort detected by master- scenario not present</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ABRT_USER_ABRT_GENERATED</name>
+                                <value>1</value>
+                                <description>Transfer abort detected by master</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>ABRT_SLVRD_INTX</name>
+                        <description>1: When the processor side responds to a slave mode request for data to be transmitted to a remote master and user writes a 1 in CMD (bit 8) of IC_DATA_CMD register.
+
+                            Reset value: 0x0
+
+                            Role of DW_apb_i2c:  Slave-Transmitter</description>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>ABRT_SLVRD_INTX_VOID</name>
+                                <value>0</value>
+                                <description>Slave trying to transmit to remote master in read mode- scenario not present</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ABRT_SLVRD_INTX_GENERATED</name>
+                                <value>1</value>
+                                <description>Slave trying to transmit to remote master in read mode</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>ABRT_SLV_ARBLOST</name>
+                        <description>This field indicates that a Slave has lost the bus while transmitting data to a remote master. IC_TX_ABRT_SOURCE[12] is set at the same time. Note:  Even though the slave never &#39;owns&#39; the bus, something could go wrong on the bus. This is a fail safe check. For instance, during a data transmission at the low-to-high transition of SCL, if what is on the data bus is not what is supposed to be transmitted, then DW_apb_i2c no longer own the bus.
+
+                            Reset value: 0x0
+
+                            Role of DW_apb_i2c:  Slave-Transmitter</description>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>ABRT_SLV_ARBLOST_VOID</name>
+                                <value>0</value>
+                                <description>Slave lost arbitration to remote master- scenario not present</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ABRT_SLV_ARBLOST_GENERATED</name>
+                                <value>1</value>
+                                <description>Slave lost arbitration to remote master</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>ABRT_SLVFLUSH_TXFIFO</name>
+                        <description>This field specifies that the Slave has received a read command and some data exists in the TX FIFO, so the slave issues a TX_ABRT interrupt to flush old data in TX FIFO.
+
+                            Reset value: 0x0
+
+                            Role of DW_apb_i2c:  Slave-Transmitter</description>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>ABRT_SLVFLUSH_TXFIFO_VOID</name>
+                                <value>0</value>
+                                <description>Slave flushes existing data in TX-FIFO upon getting read command- scenario not present</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ABRT_SLVFLUSH_TXFIFO_GENERATED</name>
+                                <value>1</value>
+                                <description>Slave flushes existing data in TX-FIFO upon getting read command</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>ARB_LOST</name>
+                        <description>This field specifies that the Master has lost arbitration, or if IC_TX_ABRT_SOURCE[14] is also set, then the slave transmitter has lost arbitration.
+
+                            Reset value: 0x0
+
+                            Role of DW_apb_i2c:  Master-Transmitter or Slave-Transmitter</description>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>ABRT_LOST_VOID</name>
+                                <value>0</value>
+                                <description>Master or Slave-Transmitter lost arbitration- scenario not present</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ABRT_LOST_GENERATED</name>
+                                <value>1</value>
+                                <description>Master or Slave-Transmitter lost arbitration</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>ABRT_MASTER_DIS</name>
+                        <description>This field indicates that the User tries to initiate a Master operation with the Master mode disabled.
+
+                            Reset value: 0x0
+
+                            Role of DW_apb_i2c:  Master-Transmitter or Master-Receiver</description>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>ABRT_MASTER_DIS_VOID</name>
+                                <value>0</value>
+                                <description>User initiating master operation when MASTER disabled- scenario not present</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ABRT_MASTER_DIS_GENERATED</name>
+                                <value>1</value>
+                                <description>User initiating master operation when MASTER disabled</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>ABRT_10B_RD_NORSTRT</name>
+                        <description>This field indicates that the restart is disabled (IC_RESTART_EN bit (IC_CON[5]) =0) and the master sends a read command in 10-bit addressing mode.
+
+                            Reset value: 0x0
+
+                            Role of DW_apb_i2c:  Master-Receiver</description>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>ABRT_10B_RD_VOID</name>
+                                <value>0</value>
+                                <description>Master not trying to read in 10Bit addressing mode when RESTART disabled</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ABRT_10B_RD_GENERATED</name>
+                                <value>1</value>
+                                <description>Master trying to read in 10Bit addressing mode when RESTART disabled</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>ABRT_SBYTE_NORSTRT</name>
+                        <description>To clear Bit 9, the source of the ABRT_SBYTE_NORSTRT must be fixed first; restart must be enabled (IC_CON[5]=1), the SPECIAL bit must be cleared (IC_TAR[11]), or the GC_OR_START bit must be cleared (IC_TAR[10]). Once the source of the ABRT_SBYTE_NORSTRT is fixed, then this bit can be cleared in the same manner as other bits in this register. If the source of the ABRT_SBYTE_NORSTRT is not fixed before attempting to clear this bit, bit 9 clears for one cycle and then gets reasserted. When this field is set to 1, the restart is disabled (IC_RESTART_EN bit (IC_CON[5]) =0) and the user is trying to send a START Byte.
+
+                            Reset value: 0x0
+
+                            Role of DW_apb_i2c:  Master</description>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>ABRT_SBYTE_NORSTRT_VOID</name>
+                                <value>0</value>
+                                <description>User trying to send START byte when RESTART disabled- scenario not present</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ABRT_SBYTE_NORSTRT_GENERATED</name>
+                                <value>1</value>
+                                <description>User trying to send START byte when RESTART disabled</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>ABRT_HS_NORSTRT</name>
+                        <description>This field indicates that the restart is disabled (IC_RESTART_EN bit (IC_CON[5]) =0) and the user is trying to use the master to transfer data in High Speed mode.
+
+                            Reset value: 0x0
+
+                            Role of DW_apb_i2c:  Master-Transmitter or Master-Receiver</description>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>ABRT_HS_NORSTRT_VOID</name>
+                                <value>0</value>
+                                <description>User trying to switch Master to HS mode when RESTART disabled- scenario not present</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ABRT_HS_NORSTRT_GENERATED</name>
+                                <value>1</value>
+                                <description>User trying to switch Master to HS mode when RESTART disabled</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>ABRT_SBYTE_ACKDET</name>
+                        <description>This field indicates that the Master has sent a START Byte and the START Byte was acknowledged (wrong behavior).
+
+                            Reset value: 0x0
+
+                            Role of DW_apb_i2c:  Master</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>ABRT_SBYTE_ACKDET_VOID</name>
+                                <value>0</value>
+                                <description>ACK detected for START byte- scenario not present</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ABRT_SBYTE_ACKDET_GENERATED</name>
+                                <value>1</value>
+                                <description>ACK detected for START byte</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>ABRT_HS_ACKDET</name>
+                        <description>This field indicates that the Master is in High Speed mode and the High Speed Master code was acknowledged (wrong behavior).
+
+                            Reset value: 0x0
+
+                            Role of DW_apb_i2c:  Master</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>ABRT_HS_ACK_VOID</name>
+                                <value>0</value>
+                                <description>HS Master code ACKed in HS Mode- scenario not present</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ABRT_HS_ACK_GENERATED</name>
+                                <value>1</value>
+                                <description>HS Master code ACKed in HS Mode</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>ABRT_GCALL_READ</name>
+                        <description>This field indicates that DW_apb_i2c in the master mode has sent a General Call but the user programmed the byte following the General Call to be a read from the bus (IC_DATA_CMD[9] is set to 1).
+
+                            Reset value: 0x0
+
+                            Role of DW_apb_i2c:  Master-Transmitter</description>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>ABRT_GCALL_READ_VOID</name>
+                                <value>0</value>
+                                <description>GCALL is followed by read from bus-scenario not present</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ABRT_GCALL_READ_GENERATED</name>
+                                <value>1</value>
+                                <description>GCALL is followed by read from bus</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>ABRT_GCALL_NOACK</name>
+                        <description>This field indicates that DW_apb_i2c in master mode has sent a General Call and no slave on the bus acknowledged the General Call.
+
+                            Reset value: 0x0
+
+                            Role of DW_apb_i2c:  Master-Transmitter</description>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>ABRT_GCALL_NOACK_VOID</name>
+                                <value>0</value>
+                                <description>GCALL not ACKed by any slave-scenario not present</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ABRT_GCALL_NOACK_GENERATED</name>
+                                <value>1</value>
+                                <description>GCALL not ACKed by any slave</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>ABRT_TXDATA_NOACK</name>
+                        <description>This field indicates the master-mode only bit. When the master receives an acknowledgement for the address, but when it sends data byte(s) following the address, it did not receive an acknowledge from the remote slave(s).
+
+                            Reset value: 0x0
+
+                            Role of DW_apb_i2c:  Master-Transmitter</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>ABRT_TXDATA_NOACK_VOID</name>
+                                <value>0</value>
+                                <description>Transmitted data non-ACKed by addressed slave-scenario not present</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ABRT_TXDATA_NOACK_GENERATED</name>
+                                <value>1</value>
+                                <description>Transmitted data not ACKed by addressed slave</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>ABRT_10ADDR2_NOACK</name>
+                        <description>This field indicates that the Master is in 10-bit address mode and that the second address byte of the 10-bit address was not acknowledged by any slave.
+
+                            Reset value: 0x0
+
+                            Role of DW_apb_i2c:  Master-Transmitter or Master-Receiver</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>INACTIVE</name>
+                                <value>0</value>
+                                <description>This abort is not generated</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ACTIVE</name>
+                                <value>1</value>
+                                <description>Byte 2 of 10Bit Address not ACKed by any slave</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>ABRT_10ADDR1_NOACK</name>
+                        <description>This field indicates that the Master is in 10-bit address mode and the first 10-bit address byte was not acknowledged by any slave.
+
+                            Reset value: 0x0
+
+                            Role of DW_apb_i2c:  Master-Transmitter or Master-Receiver</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>INACTIVE</name>
+                                <value>0</value>
+                                <description>This abort is not generated</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ACTIVE</name>
+                                <value>1</value>
+                                <description>Byte 1 of 10Bit Address not ACKed by any slave</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>ABRT_7B_ADDR_NOACK</name>
+                        <description>This field indicates that the Master is in 7-bit addressing mode and the address sent was not acknowledged by any slave.
+
+                            Reset value: 0x0
+
+                            Role of DW_apb_i2c:  Master-Transmitter or Master-Receiver</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>INACTIVE</name>
+                                <value>0</value>
+                                <description>This abort is not generated</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ACTIVE</name>
+                                <value>1</value>
+                                <description>This abort is generated because of NOACK for 7-bit address</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>IC_SLV_DATA_NACK_ONLY</name>
+                <addressOffset>0x00000084</addressOffset>
+                <description>Generate Slave Data NACK Register
+
+                    The register is used to generate a NACK for the data part of a transfer when DW_apb_i2c is acting as a slave-receiver. This register only exists when the IC_SLV_DATA_NACK_ONLY parameter is set to 1. When this parameter disabled, this register does not exist and writing to the register&#39;s address has no effect.
+
+                    A write can occur on this register if both of the following conditions are met: - DW_apb_i2c is disabled (IC_ENABLE[0] = 0) - Slave part is inactive (IC_STATUS[6] = 0) Note: The IC_STATUS[6] is a register read-back location for the internal slv_activity signal; the user should poll this before writing the ic_slv_data_nack_only bit.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>NACK</name>
+                        <description>Generate NACK. This NACK generation only occurs when DW_apb_i2c is a slave-receiver. If this register is set to a value of 1, it can only generate a NACK after a data byte is received; hence, the data transfer is aborted and the data received is not pushed to the receive buffer.
+
+                            When the register is set to a value of 0, it generates NACK/ACK, depending on normal criteria. - 1: generate NACK after data byte received - 0: generate NACK/ACK normally Reset value: 0x0</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>DISABLED</name>
+                                <value>0</value>
+                                <description>Slave receiver generates NACK normally</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ENABLED</name>
+                                <value>1</value>
+                                <description>Slave receiver generates NACK upon data reception only</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>IC_DMA_CR</name>
+                <addressOffset>0x00000088</addressOffset>
+                <description>DMA Control Register
+
+                    The register is used to enable the DMA Controller interface operation. There is a separate bit for transmit and receive. This can be programmed regardless of the state of IC_ENABLE.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>TDMAE</name>
+                        <description>Transmit DMA Enable. This bit enables/disables the transmit FIFO DMA channel. Reset value: 0x0</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>DISABLED</name>
+                                <value>0</value>
+                                <description>transmit FIFO DMA channel disabled</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ENABLED</name>
+                                <value>1</value>
+                                <description>Transmit FIFO DMA channel enabled</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>RDMAE</name>
+                        <description>Receive DMA Enable. This bit enables/disables the receive FIFO DMA channel. Reset value: 0x0</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>DISABLED</name>
+                                <value>0</value>
+                                <description>Receive FIFO DMA channel disabled</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ENABLED</name>
+                                <value>1</value>
+                                <description>Receive FIFO DMA channel enabled</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>IC_DMA_TDLR</name>
+                <addressOffset>0x0000008c</addressOffset>
+                <description>DMA Transmit Data Level Register</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>DMATDL</name>
+                        <description>Transmit Data Level. This bit field controls the level at which a DMA request is made by the transmit logic. It is equal to the watermark level; that is, the dma_tx_req signal is generated when the number of valid data entries in the transmit FIFO is equal to or below this field value, and TDMAE = 1.
+
+                            Reset value: 0x0</description>
+                        <bitRange>[3:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>IC_DMA_RDLR</name>
+                <addressOffset>0x00000090</addressOffset>
+                <description>I2C Receive Data Level Register</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>DMARDL</name>
+                        <description>Receive Data Level. This bit field controls the level at which a DMA request is made by the receive logic. The watermark level = DMARDL+1; that is, dma_rx_req is generated when the number of valid data entries in the receive FIFO is equal to or more than this field value + 1, and RDMAE =1. For instance, when DMARDL is 0, then dma_rx_req is asserted when 1 or more data entries are present in the receive FIFO.
+
+                            Reset value: 0x0</description>
+                        <bitRange>[3:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>IC_SDA_SETUP</name>
+                <addressOffset>0x00000094</addressOffset>
+                <description>I2C SDA Setup Register
+
+                    This register controls the amount of time delay (in terms of number of ic_clk clock periods) introduced in the rising edge of SCL - relative to SDA changing - when DW_apb_i2c services a read request in a slave-transmitter operation. The relevant I2C requirement is tSU:DAT (note 4) as detailed in the I2C Bus Specification. This register must be programmed with a value equal to or greater than 2.
+
+                    Writes to this register succeed only when IC_ENABLE[0] = 0.
+
+                    Note: The length of setup time is calculated using [(IC_SDA_SETUP - 1) * (ic_clk_period)], so if the user requires 10 ic_clk periods of setup time, they should program a value of 11. The IC_SDA_SETUP register is only used by the DW_apb_i2c when operating as a slave transmitter.</description>
+                <resetValue>0x00000064</resetValue>
+                <fields>
+                    <field>
+                        <name>SDA_SETUP</name>
+                        <description>SDA Setup. It is recommended that if the required delay is 1000ns, then for an ic_clk frequency of 10 MHz, IC_SDA_SETUP should be programmed to a value of 11. IC_SDA_SETUP must be programmed with a minimum value of 2.</description>
+                        <bitRange>[7:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>IC_ACK_GENERAL_CALL</name>
+                <addressOffset>0x00000098</addressOffset>
+                <description>I2C ACK General Call Register
+
+                    The register controls whether DW_apb_i2c responds with a ACK or NACK when it receives an I2C General Call address.
+
+                    This register is applicable only when the DW_apb_i2c is in slave mode.</description>
+                <resetValue>0x00000001</resetValue>
+                <fields>
+                    <field>
+                        <name>ACK_GEN_CALL</name>
+                        <description>ACK General Call. When set to 1, DW_apb_i2c responds with a ACK (by asserting ic_data_oe) when it receives a General Call. Otherwise, DW_apb_i2c responds with a NACK (by negating ic_data_oe).</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>DISABLED</name>
+                                <value>0</value>
+                                <description>Generate NACK for a General Call</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ENABLED</name>
+                                <value>1</value>
+                                <description>Generate ACK for a General Call</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>IC_ENABLE_STATUS</name>
+                <addressOffset>0x0000009c</addressOffset>
+                <description>I2C Enable Status Register
+
+                    The register is used to report the DW_apb_i2c hardware status when the IC_ENABLE[0] register is set from 1 to 0; that is, when DW_apb_i2c is disabled.
+
+                    If IC_ENABLE[0] has been set to 1, bits 2:1 are forced to 0, and bit 0 is forced to 1.
+
+                    If IC_ENABLE[0] has been set to 0, bits 2:1 is only be valid as soon as bit 0 is read as &#39;0&#39;.
+
+                    Note: When IC_ENABLE[0] has been set to 0, a delay occurs for bit 0 to be read as 0 because disabling the DW_apb_i2c depends on I2C bus activities.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>SLV_RX_DATA_LOST</name>
+                        <description>Slave Received Data Lost. This bit indicates if a Slave-Receiver operation has been aborted with at least one data byte received from an I2C transfer due to the setting bit 0 of IC_ENABLE from 1 to 0. When read as 1, DW_apb_i2c is deemed to have been actively engaged in an aborted I2C transfer (with matching address) and the data phase of the I2C transfer has been entered, even though a data byte has been responded with a NACK.
+
+                            Note:  If the remote I2C master terminates the transfer with a STOP condition before the DW_apb_i2c has a chance to NACK a transfer, and IC_ENABLE[0] has been set to 0, then this bit is also set to 1.
+
+                            When read as 0, DW_apb_i2c is deemed to have been disabled without being actively involved in the data phase of a Slave-Receiver transfer.
+
+                            Note:  The CPU can safely read this bit when IC_EN (bit 0) is read as 0.
+
+                            Reset value: 0x0</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>INACTIVE</name>
+                                <value>0</value>
+                                <description>Slave RX Data is not lost</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ACTIVE</name>
+                                <value>1</value>
+                                <description>Slave RX Data is lost</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>SLV_DISABLED_WHILE_BUSY</name>
+                        <description>Slave Disabled While Busy (Transmit, Receive). This bit indicates if a potential or active Slave operation has been aborted due to the setting bit 0 of the IC_ENABLE register from 1 to 0. This bit is set when the CPU writes a 0 to the IC_ENABLE register while:
+
+                            (a) DW_apb_i2c is receiving the address byte of the Slave-Transmitter operation from a remote master;
+
+                            OR,
+
+                            (b) address and data bytes of the Slave-Receiver operation from a remote master.
+
+                            When read as 1, DW_apb_i2c is deemed to have forced a NACK during any part of an I2C transfer, irrespective of whether the I2C address matches the slave address set in DW_apb_i2c (IC_SAR register) OR if the transfer is completed before IC_ENABLE is set to 0 but has not taken effect.
+
+                            Note:  If the remote I2C master terminates the transfer with a STOP condition before the DW_apb_i2c has a chance to NACK a transfer, and IC_ENABLE[0] has been set to 0, then this bit will also be set to 1.
+
+                            When read as 0, DW_apb_i2c is deemed to have been disabled when there is master activity, or when the I2C bus is idle.
+
+                            Note:  The CPU can safely read this bit when IC_EN (bit 0) is read as 0.
+
+                            Reset value: 0x0</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>INACTIVE</name>
+                                <value>0</value>
+                                <description>Slave is disabled when it is idle</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ACTIVE</name>
+                                <value>1</value>
+                                <description>Slave is disabled when it is active</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>IC_EN</name>
+                        <description>ic_en Status. This bit always reflects the value driven on the output port ic_en. - When read as 1, DW_apb_i2c is deemed to be in an enabled state. - When read as 0, DW_apb_i2c is deemed completely inactive. Note:  The CPU can safely read this bit anytime. When this bit is read as 0, the CPU can safely read SLV_RX_DATA_LOST (bit 2) and SLV_DISABLED_WHILE_BUSY (bit 1).
+
+                            Reset value: 0x0</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>DISABLED</name>
+                                <value>0</value>
+                                <description>I2C disabled</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>ENABLED</name>
+                                <value>1</value>
+                                <description>I2C enabled</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>IC_FS_SPKLEN</name>
+                <addressOffset>0x000000a0</addressOffset>
+                <description>I2C SS, FS or FM+ spike suppression limit
+
+                    This register is used to store the duration, measured in ic_clk cycles, of the longest spike that is filtered out by the spike suppression logic when the component is operating in SS, FS or FM+ modes. The relevant I2C requirement is tSP (table 4) as detailed in the I2C Bus Specification. This register must be programmed with a minimum value of 1.</description>
+                <resetValue>0x00000007</resetValue>
+                <fields>
+                    <field>
+                        <name>IC_FS_SPKLEN</name>
+                        <description>This register must be set before any I2C bus transaction can take place to ensure stable operation. This register sets the duration, measured in ic_clk cycles, of the longest spike in the SCL or SDA lines that will be filtered out by the spike suppression logic. This register can be written only when the I2C interface is disabled which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect. The minimum valid value is 1; hardware prevents values less than this being written, and if attempted results in 1 being set. or more information, refer to &#39;Spike Suppression&#39;.</description>
+                        <bitRange>[7:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>IC_CLR_RESTART_DET</name>
+                <addressOffset>0x000000a8</addressOffset>
+                <description>Clear RESTART_DET Interrupt Register</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CLR_RESTART_DET</name>
+                        <description>Read this register to clear the RESTART_DET interrupt (bit 12) of IC_RAW_INTR_STAT register.
+
+                            Reset value: 0x0</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>IC_COMP_PARAM_1</name>
+                <addressOffset>0x000000f4</addressOffset>
+                <description>Component Parameter Register 1
+
+                    Note This register is not implemented and therefore reads as 0. If it was implemented it would be a constant read-only register that contains encoded information about the component&#39;s parameter settings. Fields shown below are the settings for those parameters</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>TX_BUFFER_DEPTH</name>
+                        <description>TX Buffer Depth = 16</description>
+                        <bitRange>[23:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>RX_BUFFER_DEPTH</name>
+                        <description>RX Buffer Depth = 16</description>
+                        <bitRange>[15:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>ADD_ENCODED_PARAMS</name>
+                        <description>Encoded parameters not visible</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>HAS_DMA</name>
+                        <description>DMA handshaking signals are enabled</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>INTR_IO</name>
+                        <description>COMBINED Interrupt outputs</description>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>HC_COUNT_VALUES</name>
+                        <description>Programmable count values for each mode.</description>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>MAX_SPEED_MODE</name>
+                        <description>MAX SPEED MODE = FAST MODE</description>
+                        <bitRange>[3:2]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>APB_DATA_WIDTH</name>
+                        <description>APB data bus width is 32 bits</description>
+                        <bitRange>[1:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>IC_COMP_VERSION</name>
+                <addressOffset>0x000000f8</addressOffset>
+                <description>I2C Component Version Register</description>
+                <resetValue>0x3230312a</resetValue>
+                <fields>
+                    <field>
+                        <name>IC_COMP_VERSION</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>IC_COMP_TYPE</name>
+                <addressOffset>0x000000fc</addressOffset>
+                <description>I2C Component Type Register</description>
+                <resetValue>0x44570140</resetValue>
+                <fields>
+                    <field>
+                        <name>IC_COMP_TYPE</name>
+                        <description>Designware Component Type number = 0x44_57_01_40. This assigned unique hex value is constant and is derived from the two ASCII letters &#39;DW&#39; followed by a 16-bit unsigned number.</description>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+        </registers>
+    </peripheral>
+    <peripheral derivedFrom="I2C0">
+        <name>I2C1</name>
+        <baseAddress>0x40098000</baseAddress>
+        <interrupt>
+        <name>I2C1_IRQ</name>
+        <value>37</value>
+    </interrupt>
+    </peripheral>
+    <peripheral>
+        <name>SPI0</name>
+        <baseAddress>0x40080000</baseAddress>
+        <addressBlock>
+            <offset>0</offset>
+            <size>4096</size>
+            <usage>registers</usage>
+        </addressBlock>
+        <interrupt>
+            <name>SPI0_IRQ</name>
+            <value>31</value>
+        </interrupt>
+        <registers>
+            <register>
+                <name>SSPCR0</name>
+                <addressOffset>0x00000000</addressOffset>
+                <description>Control register 0, SSPCR0 on page 3-4</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>SCR</name>
+                        <description>Serial clock rate. The value SCR is used to generate the transmit and receive bit rate of the PrimeCell SSP. The bit rate is: F SSPCLK CPSDVSR x (1+SCR) where CPSDVSR is an even value from 2-254, programmed through the SSPCPSR register and SCR is a value from 0-255.</description>
+                        <bitRange>[15:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SPH</name>
+                        <description>SSPCLKOUT phase, applicable to Motorola SPI frame format only. See Motorola SPI frame format on page 2-10.</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SPO</name>
+                        <description>SSPCLKOUT polarity, applicable to Motorola SPI frame format only. See Motorola SPI frame format on page 2-10.</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>FRF</name>
+                        <description>Frame format: 00 Motorola SPI frame format. 01 TI synchronous serial frame format. 10 National Microwire frame format. 11 Reserved, undefined operation.</description>
+                        <bitRange>[5:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DSS</name>
+                        <description>Data Size Select: 0000 Reserved, undefined operation. 0001 Reserved, undefined operation. 0010 Reserved, undefined operation. 0011 4-bit data. 0100 5-bit data. 0101 6-bit data. 0110 7-bit data. 0111 8-bit data. 1000 9-bit data. 1001 10-bit data. 1010 11-bit data. 1011 12-bit data. 1100 13-bit data. 1101 14-bit data. 1110 15-bit data. 1111 16-bit data.</description>
+                        <bitRange>[3:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SSPCR1</name>
+                <addressOffset>0x00000004</addressOffset>
+                <description>Control register 1, SSPCR1 on page 3-5</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>SOD</name>
+                        <description>Slave-mode output disable. This bit is relevant only in the slave mode, MS=1. In multiple-slave systems, it is possible for an PrimeCell SSP master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto its serial output line. In such systems the RXD lines from multiple slaves could be tied together. To operate in such systems, the SOD bit can be set if the PrimeCell SSP slave is not supposed to drive the SSPTXD line: 0 SSP can drive the SSPTXD output in slave mode. 1 SSP must not drive the SSPTXD output in slave mode.</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>MS</name>
+                        <description>Master or slave mode select. This bit can be modified only when the PrimeCell SSP is disabled, SSE=0: 0 Device configured as master, default. 1 Device configured as slave.</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SSE</name>
+                        <description>Synchronous serial port enable: 0 SSP operation disabled. 1 SSP operation enabled.</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LBM</name>
+                        <description>Loop back mode: 0 Normal serial port operation enabled. 1 Output of transmit serial shifter is connected to input of receive serial shifter internally.</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SSPDR</name>
+                <addressOffset>0x00000008</addressOffset>
+                <description>Data register, SSPDR on page 3-6</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>DATA</name>
+                        <description>Transmit/Receive FIFO: Read Receive FIFO. Write Transmit FIFO. You must right-justify data when the PrimeCell SSP is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies.</description>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                        <readAction>modify</readAction>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SSPSR</name>
+                <addressOffset>0x0000000c</addressOffset>
+                <description>Status register, SSPSR on page 3-7</description>
+                <resetValue>0x00000003</resetValue>
+                <fields>
+                    <field>
+                        <name>BSY</name>
+                        <description>PrimeCell SSP busy flag, RO: 0 SSP is idle. 1 SSP is currently transmitting and/or receiving a frame or the transmit FIFO is not empty.</description>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>RFF</name>
+                        <description>Receive FIFO full, RO: 0 Receive FIFO is not full. 1 Receive FIFO is full.</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>RNE</name>
+                        <description>Receive FIFO not empty, RO: 0 Receive FIFO is empty. 1 Receive FIFO is not empty.</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>TNF</name>
+                        <description>Transmit FIFO not full, RO: 0 Transmit FIFO is full. 1 Transmit FIFO is not full.</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>TFE</name>
+                        <description>Transmit FIFO empty, RO: 0 Transmit FIFO is not empty. 1 Transmit FIFO is empty.</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SSPCPSR</name>
+                <addressOffset>0x00000010</addressOffset>
+                <description>Clock prescale register, SSPCPSR on page 3-8</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CPSDVSR</name>
+                        <description>Clock prescale divisor. Must be an even number from 2-254, depending on the frequency of SSPCLK. The least significant bit always returns zero on reads.</description>
+                        <bitRange>[7:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SSPIMSC</name>
+                <addressOffset>0x00000014</addressOffset>
+                <description>Interrupt mask set or clear register, SSPIMSC on page 3-9</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>TXIM</name>
+                        <description>Transmit FIFO interrupt mask: 0 Transmit FIFO half empty or less condition interrupt is masked. 1 Transmit FIFO half empty or less condition interrupt is not masked.</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>RXIM</name>
+                        <description>Receive FIFO interrupt mask: 0 Receive FIFO half full or less condition interrupt is masked. 1 Receive FIFO half full or less condition interrupt is not masked.</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>RTIM</name>
+                        <description>Receive timeout interrupt mask: 0 Receive FIFO not empty and no read prior to timeout period interrupt is masked. 1 Receive FIFO not empty and no read prior to timeout period interrupt is not masked.</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>RORIM</name>
+                        <description>Receive overrun interrupt mask: 0 Receive FIFO written to while full condition interrupt is masked. 1 Receive FIFO written to while full condition interrupt is not masked.</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SSPRIS</name>
+                <addressOffset>0x00000018</addressOffset>
+                <description>Raw interrupt status register, SSPRIS on page 3-10</description>
+                <resetValue>0x00000008</resetValue>
+                <fields>
+                    <field>
+                        <name>TXRIS</name>
+                        <description>Gives the raw interrupt state, prior to masking, of the SSPTXINTR interrupt</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>RXRIS</name>
+                        <description>Gives the raw interrupt state, prior to masking, of the SSPRXINTR interrupt</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>RTRIS</name>
+                        <description>Gives the raw interrupt state, prior to masking, of the SSPRTINTR interrupt</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>RORRIS</name>
+                        <description>Gives the raw interrupt state, prior to masking, of the SSPRORINTR interrupt</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SSPMIS</name>
+                <addressOffset>0x0000001c</addressOffset>
+                <description>Masked interrupt status register, SSPMIS on page 3-11</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>TXMIS</name>
+                        <description>Gives the transmit FIFO masked interrupt state, after masking, of the SSPTXINTR interrupt</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>RXMIS</name>
+                        <description>Gives the receive FIFO masked interrupt state, after masking, of the SSPRXINTR interrupt</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>RTMIS</name>
+                        <description>Gives the receive timeout masked interrupt state, after masking, of the SSPRTINTR interrupt</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>RORMIS</name>
+                        <description>Gives the receive over run masked interrupt status, after masking, of the SSPRORINTR interrupt</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SSPICR</name>
+                <addressOffset>0x00000020</addressOffset>
+                <description>Interrupt clear register, SSPICR on page 3-11</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>RTIC</name>
+                        <description>Clears the SSPRTINTR interrupt</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>RORIC</name>
+                        <description>Clears the SSPRORINTR interrupt</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SSPDMACR</name>
+                <addressOffset>0x00000024</addressOffset>
+                <description>DMA control register, SSPDMACR on page 3-12</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>TXDMAE</name>
+                        <description>Transmit DMA Enable. If this bit is set to 1, DMA for the transmit FIFO is enabled.</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>RXDMAE</name>
+                        <description>Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO is enabled.</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SSPPERIPHID0</name>
+                <addressOffset>0x00000fe0</addressOffset>
+                <description>Peripheral identification registers, SSPPeriphID0-3 on page 3-13</description>
+                <resetValue>0x00000022</resetValue>
+                <fields>
+                    <field>
+                        <name>PARTNUMBER0</name>
+                        <description>These bits read back as 0x22</description>
+                        <bitRange>[7:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SSPPERIPHID1</name>
+                <addressOffset>0x00000fe4</addressOffset>
+                <description>Peripheral identification registers, SSPPeriphID0-3 on page 3-13</description>
+                <resetValue>0x00000010</resetValue>
+                <fields>
+                    <field>
+                        <name>DESIGNER0</name>
+                        <description>These bits read back as 0x1</description>
+                        <bitRange>[7:4]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>PARTNUMBER1</name>
+                        <description>These bits read back as 0x0</description>
+                        <bitRange>[3:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SSPPERIPHID2</name>
+                <addressOffset>0x00000fe8</addressOffset>
+                <description>Peripheral identification registers, SSPPeriphID0-3 on page 3-13</description>
+                <resetValue>0x00000034</resetValue>
+                <fields>
+                    <field>
+                        <name>REVISION</name>
+                        <description>These bits return the peripheral revision</description>
+                        <bitRange>[7:4]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>DESIGNER1</name>
+                        <description>These bits read back as 0x4</description>
+                        <bitRange>[3:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SSPPERIPHID3</name>
+                <addressOffset>0x00000fec</addressOffset>
+                <description>Peripheral identification registers, SSPPeriphID0-3 on page 3-13</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CONFIGURATION</name>
+                        <description>These bits read back as 0x00</description>
+                        <bitRange>[7:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SSPPCELLID0</name>
+                <addressOffset>0x00000ff0</addressOffset>
+                <description>PrimeCell identification registers, SSPPCellID0-3 on page 3-16</description>
+                <resetValue>0x0000000d</resetValue>
+                <fields>
+                    <field>
+                        <name>SSPPCELLID0</name>
+                        <description>These bits read back as 0x0D</description>
+                        <bitRange>[7:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SSPPCELLID1</name>
+                <addressOffset>0x00000ff4</addressOffset>
+                <description>PrimeCell identification registers, SSPPCellID0-3 on page 3-16</description>
+                <resetValue>0x000000f0</resetValue>
+                <fields>
+                    <field>
+                        <name>SSPPCELLID1</name>
+                        <description>These bits read back as 0xF0</description>
+                        <bitRange>[7:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SSPPCELLID2</name>
+                <addressOffset>0x00000ff8</addressOffset>
+                <description>PrimeCell identification registers, SSPPCellID0-3 on page 3-16</description>
+                <resetValue>0x00000005</resetValue>
+                <fields>
+                    <field>
+                        <name>SSPPCELLID2</name>
+                        <description>These bits read back as 0x05</description>
+                        <bitRange>[7:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SSPPCELLID3</name>
+                <addressOffset>0x00000ffc</addressOffset>
+                <description>PrimeCell identification registers, SSPPCellID0-3 on page 3-16</description>
+                <resetValue>0x000000b1</resetValue>
+                <fields>
+                    <field>
+                        <name>SSPPCELLID3</name>
+                        <description>These bits read back as 0xB1</description>
+                        <bitRange>[7:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+        </registers>
+    </peripheral>
+    <peripheral derivedFrom="SPI0">
+        <name>SPI1</name>
+        <baseAddress>0x40088000</baseAddress>
+        <interrupt>
+        <name>SPI1_IRQ</name>
+        <value>32</value>
+    </interrupt>
+    </peripheral>
+    <peripheral>
+        <name>PIO0</name>
+        <description>Programmable IO block</description>
+        <baseAddress>0x50200000</baseAddress>
+        <addressBlock>
+            <offset>0</offset>
+            <size>392</size>
+            <usage>registers</usage>
+        </addressBlock>
+        <interrupt>
+            <name>PIO0_IRQ_0</name>
+            <value>15</value>
+        </interrupt>
+        <interrupt>
+            <name>PIO0_IRQ_1</name>
+            <value>16</value>
+        </interrupt>
+        <registers>
+            <register>
+                <name>CTRL</name>
+                <addressOffset>0x00000000</addressOffset>
+                <description>PIO control register</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>NEXTPREV_CLKDIV_RESTART</name>
+                        <description>Write 1 to restart the clock dividers of state machines in neighbouring PIO blocks, as specified by NEXT_PIO_MASK and PREV_PIO_MASK in the same write.
+
+                            This is equivalent to writing 1 to the corresponding CLKDIV_RESTART bits in those PIOs&#39; CTRL registers.</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>NEXTPREV_SM_DISABLE</name>
+                        <description>Write 1 to disable state machines in neighbouring PIO blocks, as specified by NEXT_PIO_MASK and PREV_PIO_MASK in the same write.
+
+                            This is equivalent to clearing the corresponding SM_ENABLE bits in those PIOs&#39; CTRL registers.</description>
+                        <bitRange>[25:25]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>NEXTPREV_SM_ENABLE</name>
+                        <description>Write 1 to enable state machines in neighbouring PIO blocks, as specified by NEXT_PIO_MASK and PREV_PIO_MASK in the same write.
+
+                            This is equivalent to setting the corresponding SM_ENABLE bits in those PIOs&#39; CTRL registers.
+
+                            If both OTHERS_SM_ENABLE and OTHERS_SM_DISABLE are set, the disable takes precedence.</description>
+                        <bitRange>[24:24]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>NEXT_PIO_MASK</name>
+                        <description>A mask of state machines in the neighbouring higher-numbered PIO block in the system (or PIO block 0 if this is the highest-numbered PIO block) to which to apply the operations specified by NEXTPREV_CLKDIV_RESTART, NEXTPREV_SM_ENABLE, and NEXTPREV_SM_DISABLE in the same write.
+
+                            This allows state machines in a neighbouring PIO block to be started/stopped/clock-synced exactly simultaneously with a write to this PIO block&#39;s CTRL register.
+
+                            Note that in a system with two PIOs, NEXT_PIO_MASK and PREV_PIO_MASK actually indicate the same PIO block. In this case the effects are applied cumulatively (as though the masks were OR&#39;d together).
+
+                            Neighbouring PIO blocks are disconnected (status signals tied to 0 and control signals ignored) if one block is accessible to NonSecure code, and one is not.</description>
+                        <bitRange>[23:20]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>PREV_PIO_MASK</name>
+                        <description>A mask of state machines in the neighbouring lower-numbered PIO block in the system (or the highest-numbered PIO block if this is PIO block 0) to which to apply the operations specified by OP_CLKDIV_RESTART, OP_ENABLE, OP_DISABLE in the same write.
+
+                            This allows state machines in a neighbouring PIO block to be started/stopped/clock-synced exactly simultaneously with a write to this PIO block&#39;s CTRL register.
+
+                            Neighbouring PIO blocks are disconnected (status signals tied to 0 and control signals ignored) if one block is accessible to NonSecure code, and one is not.</description>
+                        <bitRange>[19:16]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>CLKDIV_RESTART</name>
+                        <description>Restart a state machine&#39;s clock divider from an initial phase of 0. Clock dividers are free-running, so once started, their output (including fractional jitter) is completely determined by the integer/fractional divisor configured in SMx_CLKDIV. This means that, if multiple clock dividers with the same divisor are restarted simultaneously, by writing multiple 1 bits to this field, the execution clocks of those state machines will run in precise lockstep.
+
+                            Note that setting/clearing SM_ENABLE does not stop the clock divider from running, so once multiple state machines&#39; clocks are synchronised, it is safe to disable/reenable a state machine, whilst keeping the clock dividers in sync.
+
+                            Note also that CLKDIV_RESTART can be written to whilst the state machine is running, and this is useful to resynchronise clock dividers after the divisors (SMx_CLKDIV) have been changed on-the-fly.</description>
+                        <bitRange>[11:8]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>SM_RESTART</name>
+                        <description>Write 1 to instantly clear internal SM state which may be otherwise difficult to access and will affect future execution.
+
+                            Specifically, the following are cleared: input and output shift counters; the contents of the input shift register; the delay counter; the waiting-on-IRQ state; any stalled instruction written to SMx_INSTR or run by OUT/MOV EXEC; any pin write left asserted due to OUT_STICKY.
+
+                            The contents of the output shift register and the X/Y scratch registers are not affected.</description>
+                        <bitRange>[7:4]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>SM_ENABLE</name>
+                        <description>Enable/disable each of the four state machines by writing 1/0 to each of these four bits. When disabled, a state machine will cease executing instructions, except those written directly to SMx_INSTR by the system. Multiple bits can be set/cleared at once to run/halt multiple state machines simultaneously.</description>
+                        <bitRange>[3:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>FSTAT</name>
+                <addressOffset>0x00000004</addressOffset>
+                <description>FIFO status register</description>
+                <resetValue>0x0f000f00</resetValue>
+                <fields>
+                    <field>
+                        <name>TXEMPTY</name>
+                        <description>State machine TX FIFO is empty</description>
+                        <bitRange>[27:24]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>TXFULL</name>
+                        <description>State machine TX FIFO is full</description>
+                        <bitRange>[19:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>RXEMPTY</name>
+                        <description>State machine RX FIFO is empty</description>
+                        <bitRange>[11:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>RXFULL</name>
+                        <description>State machine RX FIFO is full</description>
+                        <bitRange>[3:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>FDEBUG</name>
+                <addressOffset>0x00000008</addressOffset>
+                <description>FIFO debug register</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>TXSTALL</name>
+                        <description>State machine has stalled on empty TX FIFO during a blocking PULL, or an OUT with autopull enabled. Write 1 to clear.</description>
+                        <bitRange>[27:24]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>TXOVER</name>
+                        <description>TX FIFO overflow (i.e. write-on-full by the system) has occurred. Write 1 to clear. Note that write-on-full does not alter the state or contents of the FIFO in any way, but the data that the system attempted to write is dropped, so if this flag is set, your software has quite likely dropped some data on the floor.</description>
+                        <bitRange>[19:16]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>RXUNDER</name>
+                        <description>RX FIFO underflow (i.e. read-on-empty by the system) has occurred. Write 1 to clear. Note that read-on-empty does not perturb the state of the FIFO in any way, but the data returned by reading from an empty FIFO is undefined, so this flag generally only becomes set due to some kind of software error.</description>
+                        <bitRange>[11:8]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>RXSTALL</name>
+                        <description>State machine has stalled on full RX FIFO during a blocking PUSH, or an IN with autopush enabled. This flag is also set when a nonblocking PUSH to a full FIFO took place, in which case the state machine has dropped data. Write 1 to clear.</description>
+                        <bitRange>[3:0]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>FLEVEL</name>
+                <addressOffset>0x0000000c</addressOffset>
+                <description>FIFO levels</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>RX3</name>
+                        <bitRange>[31:28]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>TX3</name>
+                        <bitRange>[27:24]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>RX2</name>
+                        <bitRange>[23:20]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>TX2</name>
+                        <bitRange>[19:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>RX1</name>
+                        <bitRange>[15:12]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>TX1</name>
+                        <bitRange>[11:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>RX0</name>
+                        <bitRange>[7:4]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>TX0</name>
+                        <bitRange>[3:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>TXF0</name>
+                <addressOffset>0x00000010</addressOffset>
+                <description>Direct write access to the TX FIFO for this state machine. Each write pushes one word to the FIFO. Attempting to write to a full FIFO has no effect on the FIFO state or contents, and sets the sticky FDEBUG_TXOVER error flag for this FIFO.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>TXF0</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>TXF1</name>
+                <addressOffset>0x00000014</addressOffset>
+                <description>Direct write access to the TX FIFO for this state machine. Each write pushes one word to the FIFO. Attempting to write to a full FIFO has no effect on the FIFO state or contents, and sets the sticky FDEBUG_TXOVER error flag for this FIFO.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>TXF1</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>TXF2</name>
+                <addressOffset>0x00000018</addressOffset>
+                <description>Direct write access to the TX FIFO for this state machine. Each write pushes one word to the FIFO. Attempting to write to a full FIFO has no effect on the FIFO state or contents, and sets the sticky FDEBUG_TXOVER error flag for this FIFO.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>TXF2</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>TXF3</name>
+                <addressOffset>0x0000001c</addressOffset>
+                <description>Direct write access to the TX FIFO for this state machine. Each write pushes one word to the FIFO. Attempting to write to a full FIFO has no effect on the FIFO state or contents, and sets the sticky FDEBUG_TXOVER error flag for this FIFO.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>TXF3</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>RXF0</name>
+                <addressOffset>0x00000020</addressOffset>
+                <description>Direct read access to the RX FIFO for this state machine. Each read pops one word from the FIFO. Attempting to read from an empty FIFO has no effect on the FIFO state, and sets the sticky FDEBUG_RXUNDER error flag for this FIFO. The data returned to the system on a read from an empty FIFO is undefined.</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>RXF0</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-only</access>
+                        <readAction>modify</readAction>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>RXF1</name>
+                <addressOffset>0x00000024</addressOffset>
+                <description>Direct read access to the RX FIFO for this state machine. Each read pops one word from the FIFO. Attempting to read from an empty FIFO has no effect on the FIFO state, and sets the sticky FDEBUG_RXUNDER error flag for this FIFO. The data returned to the system on a read from an empty FIFO is undefined.</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>RXF1</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-only</access>
+                        <readAction>modify</readAction>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>RXF2</name>
+                <addressOffset>0x00000028</addressOffset>
+                <description>Direct read access to the RX FIFO for this state machine. Each read pops one word from the FIFO. Attempting to read from an empty FIFO has no effect on the FIFO state, and sets the sticky FDEBUG_RXUNDER error flag for this FIFO. The data returned to the system on a read from an empty FIFO is undefined.</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>RXF2</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-only</access>
+                        <readAction>modify</readAction>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>RXF3</name>
+                <addressOffset>0x0000002c</addressOffset>
+                <description>Direct read access to the RX FIFO for this state machine. Each read pops one word from the FIFO. Attempting to read from an empty FIFO has no effect on the FIFO state, and sets the sticky FDEBUG_RXUNDER error flag for this FIFO. The data returned to the system on a read from an empty FIFO is undefined.</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>RXF3</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-only</access>
+                        <readAction>modify</readAction>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>IRQ</name>
+                <addressOffset>0x00000030</addressOffset>
+                <description>State machine IRQ flags register. Write 1 to clear. There are eight state machine IRQ flags, which can be set, cleared, and waited on by the state machines. There&#39;s no fixed association between flags and state machines -- any state machine can use any flag.
+
+                    Any of the eight flags can be used for timing synchronisation between state machines, using IRQ and WAIT instructions. Any combination of the eight flags can also routed out to either of the two system-level interrupt requests, alongside FIFO status interrupts -- see e.g. IRQ0_INTE.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>IRQ</name>
+                        <bitRange>[7:0]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>IRQ_FORCE</name>
+                <addressOffset>0x00000034</addressOffset>
+                <description>Writing a 1 to each of these bits will forcibly assert the corresponding IRQ. Note this is different to the INTF register: writing here affects PIO internal state. INTF just asserts the processor-facing IRQ signal for testing ISRs, and is not visible to the state machines.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>IRQ_FORCE</name>
+                        <bitRange>[7:0]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INPUT_SYNC_BYPASS</name>
+                <addressOffset>0x00000038</addressOffset>
+                <description>There is a 2-flipflop synchronizer on each GPIO input, which protects PIO logic from metastabilities. This increases input delay, and for fast synchronous IO (e.g. SPI) these synchronizers may need to be bypassed. Each bit in this register corresponds to one GPIO. 
+                    0 -&gt; input is synchronized (default) 
+                    1 -&gt; synchronizer is bypassed 
+                    If in doubt, leave this register as all zeroes.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>INPUT_SYNC_BYPASS</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>DBG_PADOUT</name>
+                <addressOffset>0x0000003c</addressOffset>
+                <description>Read to sample the pad output values PIO is currently driving to the GPIOs. On RP2040 there are 30 GPIOs, so the two most significant bits are hardwired to 0.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>DBG_PADOUT</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>DBG_PADOE</name>
+                <addressOffset>0x00000040</addressOffset>
+                <description>Read to sample the pad output enables (direction) PIO is currently driving to the GPIOs. On RP2040 there are 30 GPIOs, so the two most significant bits are hardwired to 0.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>DBG_PADOE</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>DBG_CFGINFO</name>
+                <addressOffset>0x00000044</addressOffset>
+                <description>The PIO hardware has some free parameters that may vary between chip products. 
+                    These should be provided in the chip datasheet, but are also exposed here.</description>
+                <resetValue>0x10000000</resetValue>
+                <fields>
+                    <field>
+                        <name>VERSION</name>
+                        <description>Version of the core PIO hardware.</description>
+                        <bitRange>[31:28]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>v0</name>
+                                <value>0</value>
+                                <description>Version 0 (RP2040)</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>v1</name>
+                                <value>1</value>
+                                <description>Version 1 (RP2350)</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>IMEM_SIZE</name>
+                        <description>The size of the instruction memory, measured in units of one instruction</description>
+                        <bitRange>[21:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SM_COUNT</name>
+                        <description>The number of state machines this PIO instance is equipped with.</description>
+                        <bitRange>[11:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>FIFO_DEPTH</name>
+                        <description>The depth of the state machine TX/RX FIFOs, measured in words. 
+                            Joining fifos via SHIFTCTRL_FJOIN gives one FIFO with double 
+                            this depth.</description>
+                        <bitRange>[5:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INSTR_MEM0</name>
+                <addressOffset>0x00000048</addressOffset>
+                <description>Write-only access to instruction memory location 0</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>INSTR_MEM0</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INSTR_MEM1</name>
+                <addressOffset>0x0000004c</addressOffset>
+                <description>Write-only access to instruction memory location 1</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>INSTR_MEM1</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INSTR_MEM2</name>
+                <addressOffset>0x00000050</addressOffset>
+                <description>Write-only access to instruction memory location 2</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>INSTR_MEM2</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INSTR_MEM3</name>
+                <addressOffset>0x00000054</addressOffset>
+                <description>Write-only access to instruction memory location 3</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>INSTR_MEM3</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INSTR_MEM4</name>
+                <addressOffset>0x00000058</addressOffset>
+                <description>Write-only access to instruction memory location 4</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>INSTR_MEM4</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INSTR_MEM5</name>
+                <addressOffset>0x0000005c</addressOffset>
+                <description>Write-only access to instruction memory location 5</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>INSTR_MEM5</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INSTR_MEM6</name>
+                <addressOffset>0x00000060</addressOffset>
+                <description>Write-only access to instruction memory location 6</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>INSTR_MEM6</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INSTR_MEM7</name>
+                <addressOffset>0x00000064</addressOffset>
+                <description>Write-only access to instruction memory location 7</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>INSTR_MEM7</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INSTR_MEM8</name>
+                <addressOffset>0x00000068</addressOffset>
+                <description>Write-only access to instruction memory location 8</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>INSTR_MEM8</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INSTR_MEM9</name>
+                <addressOffset>0x0000006c</addressOffset>
+                <description>Write-only access to instruction memory location 9</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>INSTR_MEM9</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INSTR_MEM10</name>
+                <addressOffset>0x00000070</addressOffset>
+                <description>Write-only access to instruction memory location 10</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>INSTR_MEM10</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INSTR_MEM11</name>
+                <addressOffset>0x00000074</addressOffset>
+                <description>Write-only access to instruction memory location 11</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>INSTR_MEM11</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INSTR_MEM12</name>
+                <addressOffset>0x00000078</addressOffset>
+                <description>Write-only access to instruction memory location 12</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>INSTR_MEM12</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INSTR_MEM13</name>
+                <addressOffset>0x0000007c</addressOffset>
+                <description>Write-only access to instruction memory location 13</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>INSTR_MEM13</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INSTR_MEM14</name>
+                <addressOffset>0x00000080</addressOffset>
+                <description>Write-only access to instruction memory location 14</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>INSTR_MEM14</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INSTR_MEM15</name>
+                <addressOffset>0x00000084</addressOffset>
+                <description>Write-only access to instruction memory location 15</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>INSTR_MEM15</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INSTR_MEM16</name>
+                <addressOffset>0x00000088</addressOffset>
+                <description>Write-only access to instruction memory location 16</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>INSTR_MEM16</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INSTR_MEM17</name>
+                <addressOffset>0x0000008c</addressOffset>
+                <description>Write-only access to instruction memory location 17</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>INSTR_MEM17</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INSTR_MEM18</name>
+                <addressOffset>0x00000090</addressOffset>
+                <description>Write-only access to instruction memory location 18</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>INSTR_MEM18</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INSTR_MEM19</name>
+                <addressOffset>0x00000094</addressOffset>
+                <description>Write-only access to instruction memory location 19</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>INSTR_MEM19</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INSTR_MEM20</name>
+                <addressOffset>0x00000098</addressOffset>
+                <description>Write-only access to instruction memory location 20</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>INSTR_MEM20</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INSTR_MEM21</name>
+                <addressOffset>0x0000009c</addressOffset>
+                <description>Write-only access to instruction memory location 21</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>INSTR_MEM21</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INSTR_MEM22</name>
+                <addressOffset>0x000000a0</addressOffset>
+                <description>Write-only access to instruction memory location 22</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>INSTR_MEM22</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INSTR_MEM23</name>
+                <addressOffset>0x000000a4</addressOffset>
+                <description>Write-only access to instruction memory location 23</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>INSTR_MEM23</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INSTR_MEM24</name>
+                <addressOffset>0x000000a8</addressOffset>
+                <description>Write-only access to instruction memory location 24</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>INSTR_MEM24</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INSTR_MEM25</name>
+                <addressOffset>0x000000ac</addressOffset>
+                <description>Write-only access to instruction memory location 25</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>INSTR_MEM25</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INSTR_MEM26</name>
+                <addressOffset>0x000000b0</addressOffset>
+                <description>Write-only access to instruction memory location 26</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>INSTR_MEM26</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INSTR_MEM27</name>
+                <addressOffset>0x000000b4</addressOffset>
+                <description>Write-only access to instruction memory location 27</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>INSTR_MEM27</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INSTR_MEM28</name>
+                <addressOffset>0x000000b8</addressOffset>
+                <description>Write-only access to instruction memory location 28</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>INSTR_MEM28</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INSTR_MEM29</name>
+                <addressOffset>0x000000bc</addressOffset>
+                <description>Write-only access to instruction memory location 29</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>INSTR_MEM29</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INSTR_MEM30</name>
+                <addressOffset>0x000000c0</addressOffset>
+                <description>Write-only access to instruction memory location 30</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>INSTR_MEM30</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INSTR_MEM31</name>
+                <addressOffset>0x000000c4</addressOffset>
+                <description>Write-only access to instruction memory location 31</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>INSTR_MEM31</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SM0_CLKDIV</name>
+                <addressOffset>0x000000c8</addressOffset>
+                <description>Clock divisor register for state machine 0 
+                    Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256)</description>
+                <resetValue>0x00010000</resetValue>
+                <fields>
+                    <field>
+                        <name>INT</name>
+                        <description>Effective frequency is sysclk/(int + frac/256). 
+                            Value of 0 is interpreted as 65536. If INT is 0, FRAC must also be 0.</description>
+                        <bitRange>[31:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>FRAC</name>
+                        <description>Fractional part of clock divisor</description>
+                        <bitRange>[15:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SM0_EXECCTRL</name>
+                <addressOffset>0x000000cc</addressOffset>
+                <description>Execution/behavioural settings for state machine 0</description>
+                <resetValue>0x0001f000</resetValue>
+                <fields>
+                    <field>
+                        <name>EXEC_STALLED</name>
+                        <description>If 1, an instruction written to SMx_INSTR is stalled, and latched by the state machine. Will clear to 0 once this instruction completes.</description>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SIDE_EN</name>
+                        <description>If 1, the MSB of the Delay/Side-set instruction field is used as side-set enable, rather than a side-set data bit. This allows instructions to perform side-set optionally, rather than on every instruction, but the maximum possible side-set width is reduced from 5 to 4. Note that the value of PINCTRL_SIDESET_COUNT is inclusive of this enable bit.</description>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SIDE_PINDIR</name>
+                        <description>If 1, side-set data is asserted to pin directions, instead of pin values</description>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>JMP_PIN</name>
+                        <description>The GPIO number to use as condition for JMP PIN. Unaffected by input mapping.</description>
+                        <bitRange>[28:24]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>OUT_EN_SEL</name>
+                        <description>Which data bit to use for inline OUT enable</description>
+                        <bitRange>[23:19]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INLINE_OUT_EN</name>
+                        <description>If 1, use a bit of OUT data as an auxiliary write enable 
+                            When used in conjunction with OUT_STICKY, writes with an enable of 0 will 
+                            deassert the latest pin write. This can create useful masking/override behaviour 
+                            due to the priority ordering of state machine pin writes (SM0 &lt; SM1 &lt; ...)</description>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>OUT_STICKY</name>
+                        <description>Continuously assert the most recent OUT/SET to the pins</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>WRAP_TOP</name>
+                        <description>After reaching this address, execution is wrapped to wrap_bottom. 
+                            If the instruction is a jump, and the jump condition is true, the jump takes priority.</description>
+                        <bitRange>[16:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>WRAP_BOTTOM</name>
+                        <description>After reaching wrap_top, execution is wrapped to this address.</description>
+                        <bitRange>[11:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>STATUS_SEL</name>
+                        <description>Comparison used for the MOV x, STATUS instruction.</description>
+                        <bitRange>[6:5]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>TXLEVEL</name>
+                                <value>0</value>
+                                <description>All-ones if TX FIFO level &lt; N, otherwise all-zeroes</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>RXLEVEL</name>
+                                <value>1</value>
+                                <description>All-ones if RX FIFO level &lt; N, otherwise all-zeroes</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>IRQ</name>
+                                <value>2</value>
+                                <description>All-ones if the indexed IRQ flag is raised, otherwise all-zeroes</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>STATUS_N</name>
+                        <description>Comparison level or IRQ index for the MOV x, STATUS instruction.
+
+                            If STATUS_SEL is TXLEVEL or RXLEVEL, then values of STATUS_N greater than the current FIFO depth are reserved, and have undefined behaviour.</description>
+                        <bitRange>[4:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>IRQ</name>
+                                <value>0</value>
+                                <description>Index 0-7 of an IRQ flag in this PIO block</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>IRQ_PREVPIO</name>
+                                <value>8</value>
+                                <description>Index 0-7 of an IRQ flag in the next lower-numbered PIO block</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>IRQ_NEXTPIO</name>
+                                <value>16</value>
+                                <description>Index 0-7 of an IRQ flag in the next higher-numbered PIO block</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SM0_SHIFTCTRL</name>
+                <addressOffset>0x000000d0</addressOffset>
+                <description>Control behaviour of the input/output shift registers for state machine 0</description>
+                <resetValue>0x000c0000</resetValue>
+                <fields>
+                    <field>
+                        <name>FJOIN_RX</name>
+                        <description>When 1, RX FIFO steals the TX FIFO&#39;s storage, and becomes twice as deep. 
+                            TX FIFO is disabled as a result (always reads as both full and empty). 
+                            FIFOs are flushed when this bit is changed.</description>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>FJOIN_TX</name>
+                        <description>When 1, TX FIFO steals the RX FIFO&#39;s storage, and becomes twice as deep. 
+                            RX FIFO is disabled as a result (always reads as both full and empty). 
+                            FIFOs are flushed when this bit is changed.</description>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PULL_THRESH</name>
+                        <description>Number of bits shifted out of OSR before autopull, or conditional pull (PULL IFEMPTY), will take place. 
+                            Write 0 for value of 32.</description>
+                        <bitRange>[29:25]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PUSH_THRESH</name>
+                        <description>Number of bits shifted into ISR before autopush, or conditional push (PUSH IFFULL), will take place. 
+                            Write 0 for value of 32.</description>
+                        <bitRange>[24:20]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>OUT_SHIFTDIR</name>
+                        <description>1 = shift out of output shift register to right. 0 = to left.</description>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>IN_SHIFTDIR</name>
+                        <description>1 = shift input shift register to right (data enters from left). 0 = to left.</description>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>AUTOPULL</name>
+                        <description>Pull automatically when the output shift register is emptied, i.e. on or following an OUT instruction which causes the output shift counter to reach or exceed PULL_THRESH.</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>AUTOPUSH</name>
+                        <description>Push automatically when the input shift register is filled, i.e. on an IN instruction which causes the input shift counter to reach or exceed PUSH_THRESH.</description>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>FJOIN_RX_PUT</name>
+                        <description>If 1, disable this state machine&#39;s RX FIFO, make its storage available for random write access by the state machine (using the `put` instruction) and, unless FJOIN_RX_GET is also set, random read access by the processor (through the RXFx_PUTGETy registers).
+
+                            If FJOIN_RX_PUT and FJOIN_RX_GET are both set, then the RX FIFO&#39;s registers can be randomly read/written by the state machine, but are completely inaccessible to the processor.
+
+                            Setting this bit will clear the FJOIN_TX and FJOIN_RX bits.</description>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>FJOIN_RX_GET</name>
+                        <description>If 1, disable this state machine&#39;s RX FIFO, make its storage available for random read access by the state machine (using the `get` instruction) and, unless FJOIN_RX_PUT is also set, random write access by the processor (through the RXFx_PUTGETy registers).
+
+                            If FJOIN_RX_PUT and FJOIN_RX_GET are both set, then the RX FIFO&#39;s registers can be randomly read/written by the state machine, but are completely inaccessible to the processor.
+
+                            Setting this bit will clear the FJOIN_TX and FJOIN_RX bits.</description>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>IN_COUNT</name>
+                        <description>Set the number of pins which are not masked to 0 when read by an IN PINS, WAIT PIN or MOV x, PINS instruction.
+
+                            For example, an IN_COUNT of 5 means that the 5 LSBs of the IN pin group are visible (bits 4:0), but the remaining 27 MSBs are masked to 0. A count of 32 is encoded with a field value of 0, so the default behaviour is to not perform any masking.
+
+                            Note this masking is applied in addition to the masking usually performed by the IN instruction. This is mainly useful for the MOV x, PINS instruction, which otherwise has no way of masking pins.</description>
+                        <bitRange>[4:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SM0_ADDR</name>
+                <addressOffset>0x000000d4</addressOffset>
+                <description>Current instruction address of state machine 0</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>SM0_ADDR</name>
+                        <bitRange>[4:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SM0_INSTR</name>
+                <addressOffset>0x000000d8</addressOffset>
+                <description>Read to see the instruction currently addressed by state machine 0&#39;s program counter 
+                    Write to execute an instruction immediately (including jumps) and then resume execution.</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>SM0_INSTR</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SM0_PINCTRL</name>
+                <addressOffset>0x000000dc</addressOffset>
+                <description>State machine pin control</description>
+                <resetValue>0x14000000</resetValue>
+                <fields>
+                    <field>
+                        <name>SIDESET_COUNT</name>
+                        <description>The number of MSBs of the Delay/Side-set instruction field which are used for side-set. Inclusive of the enable bit, if present. Minimum of 0 (all delay bits, no side-set) and maximum of 5 (all side-set, no delay).</description>
+                        <bitRange>[31:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SET_COUNT</name>
+                        <description>The number of pins asserted by a SET. In the range 0 to 5 inclusive.</description>
+                        <bitRange>[28:26]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>OUT_COUNT</name>
+                        <description>The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV PINS instruction. In the range 0 to 32 inclusive.</description>
+                        <bitRange>[25:20]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>IN_BASE</name>
+                        <description>The pin which is mapped to the least-significant bit of a state machine&#39;s IN data bus. Higher-numbered pins are mapped to consecutively more-significant data bits, with a modulo of 32 applied to pin number.</description>
+                        <bitRange>[19:15]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SIDESET_BASE</name>
+                        <description>The lowest-numbered pin that will be affected by a side-set operation. The MSBs of an instruction&#39;s side-set/delay field (up to 5, determined by SIDESET_COUNT) are used for side-set data, with the remaining LSBs used for delay. The least-significant bit of the side-set portion is the bit written to this pin, with more-significant bits written to higher-numbered pins.</description>
+                        <bitRange>[14:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SET_BASE</name>
+                        <description>The lowest-numbered pin that will be affected by a SET PINS or SET PINDIRS instruction. The data written to this pin is the least-significant bit of the SET data.</description>
+                        <bitRange>[9:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>OUT_BASE</name>
+                        <description>The lowest-numbered pin that will be affected by an OUT PINS, OUT PINDIRS or MOV PINS instruction. The data written to this pin will always be the least-significant bit of the OUT or MOV data.</description>
+                        <bitRange>[4:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SM1_CLKDIV</name>
+                <addressOffset>0x000000e0</addressOffset>
+                <description>Clock divisor register for state machine 1 
+                    Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256)</description>
+                <resetValue>0x00010000</resetValue>
+                <fields>
+                    <field>
+                        <name>INT</name>
+                        <description>Effective frequency is sysclk/(int + frac/256). 
+                            Value of 0 is interpreted as 65536. If INT is 0, FRAC must also be 0.</description>
+                        <bitRange>[31:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>FRAC</name>
+                        <description>Fractional part of clock divisor</description>
+                        <bitRange>[15:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SM1_EXECCTRL</name>
+                <addressOffset>0x000000e4</addressOffset>
+                <description>Execution/behavioural settings for state machine 1</description>
+                <resetValue>0x0001f000</resetValue>
+                <fields>
+                    <field>
+                        <name>EXEC_STALLED</name>
+                        <description>If 1, an instruction written to SMx_INSTR is stalled, and latched by the state machine. Will clear to 0 once this instruction completes.</description>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SIDE_EN</name>
+                        <description>If 1, the MSB of the Delay/Side-set instruction field is used as side-set enable, rather than a side-set data bit. This allows instructions to perform side-set optionally, rather than on every instruction, but the maximum possible side-set width is reduced from 5 to 4. Note that the value of PINCTRL_SIDESET_COUNT is inclusive of this enable bit.</description>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SIDE_PINDIR</name>
+                        <description>If 1, side-set data is asserted to pin directions, instead of pin values</description>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>JMP_PIN</name>
+                        <description>The GPIO number to use as condition for JMP PIN. Unaffected by input mapping.</description>
+                        <bitRange>[28:24]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>OUT_EN_SEL</name>
+                        <description>Which data bit to use for inline OUT enable</description>
+                        <bitRange>[23:19]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INLINE_OUT_EN</name>
+                        <description>If 1, use a bit of OUT data as an auxiliary write enable 
+                            When used in conjunction with OUT_STICKY, writes with an enable of 0 will 
+                            deassert the latest pin write. This can create useful masking/override behaviour 
+                            due to the priority ordering of state machine pin writes (SM0 &lt; SM1 &lt; ...)</description>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>OUT_STICKY</name>
+                        <description>Continuously assert the most recent OUT/SET to the pins</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>WRAP_TOP</name>
+                        <description>After reaching this address, execution is wrapped to wrap_bottom. 
+                            If the instruction is a jump, and the jump condition is true, the jump takes priority.</description>
+                        <bitRange>[16:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>WRAP_BOTTOM</name>
+                        <description>After reaching wrap_top, execution is wrapped to this address.</description>
+                        <bitRange>[11:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>STATUS_SEL</name>
+                        <description>Comparison used for the MOV x, STATUS instruction.</description>
+                        <bitRange>[6:5]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>TXLEVEL</name>
+                                <value>0</value>
+                                <description>All-ones if TX FIFO level &lt; N, otherwise all-zeroes</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>RXLEVEL</name>
+                                <value>1</value>
+                                <description>All-ones if RX FIFO level &lt; N, otherwise all-zeroes</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>IRQ</name>
+                                <value>2</value>
+                                <description>All-ones if the indexed IRQ flag is raised, otherwise all-zeroes</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>STATUS_N</name>
+                        <description>Comparison level or IRQ index for the MOV x, STATUS instruction.
+
+                            If STATUS_SEL is TXLEVEL or RXLEVEL, then values of STATUS_N greater than the current FIFO depth are reserved, and have undefined behaviour.</description>
+                        <bitRange>[4:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>IRQ</name>
+                                <value>0</value>
+                                <description>Index 0-7 of an IRQ flag in this PIO block</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>IRQ_PREVPIO</name>
+                                <value>8</value>
+                                <description>Index 0-7 of an IRQ flag in the next lower-numbered PIO block</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>IRQ_NEXTPIO</name>
+                                <value>16</value>
+                                <description>Index 0-7 of an IRQ flag in the next higher-numbered PIO block</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SM1_SHIFTCTRL</name>
+                <addressOffset>0x000000e8</addressOffset>
+                <description>Control behaviour of the input/output shift registers for state machine 1</description>
+                <resetValue>0x000c0000</resetValue>
+                <fields>
+                    <field>
+                        <name>FJOIN_RX</name>
+                        <description>When 1, RX FIFO steals the TX FIFO&#39;s storage, and becomes twice as deep. 
+                            TX FIFO is disabled as a result (always reads as both full and empty). 
+                            FIFOs are flushed when this bit is changed.</description>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>FJOIN_TX</name>
+                        <description>When 1, TX FIFO steals the RX FIFO&#39;s storage, and becomes twice as deep. 
+                            RX FIFO is disabled as a result (always reads as both full and empty). 
+                            FIFOs are flushed when this bit is changed.</description>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PULL_THRESH</name>
+                        <description>Number of bits shifted out of OSR before autopull, or conditional pull (PULL IFEMPTY), will take place. 
+                            Write 0 for value of 32.</description>
+                        <bitRange>[29:25]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PUSH_THRESH</name>
+                        <description>Number of bits shifted into ISR before autopush, or conditional push (PUSH IFFULL), will take place. 
+                            Write 0 for value of 32.</description>
+                        <bitRange>[24:20]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>OUT_SHIFTDIR</name>
+                        <description>1 = shift out of output shift register to right. 0 = to left.</description>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>IN_SHIFTDIR</name>
+                        <description>1 = shift input shift register to right (data enters from left). 0 = to left.</description>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>AUTOPULL</name>
+                        <description>Pull automatically when the output shift register is emptied, i.e. on or following an OUT instruction which causes the output shift counter to reach or exceed PULL_THRESH.</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>AUTOPUSH</name>
+                        <description>Push automatically when the input shift register is filled, i.e. on an IN instruction which causes the input shift counter to reach or exceed PUSH_THRESH.</description>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>FJOIN_RX_PUT</name>
+                        <description>If 1, disable this state machine&#39;s RX FIFO, make its storage available for random write access by the state machine (using the `put` instruction) and, unless FJOIN_RX_GET is also set, random read access by the processor (through the RXFx_PUTGETy registers).
+
+                            If FJOIN_RX_PUT and FJOIN_RX_GET are both set, then the RX FIFO&#39;s registers can be randomly read/written by the state machine, but are completely inaccessible to the processor.
+
+                            Setting this bit will clear the FJOIN_TX and FJOIN_RX bits.</description>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>FJOIN_RX_GET</name>
+                        <description>If 1, disable this state machine&#39;s RX FIFO, make its storage available for random read access by the state machine (using the `get` instruction) and, unless FJOIN_RX_PUT is also set, random write access by the processor (through the RXFx_PUTGETy registers).
+
+                            If FJOIN_RX_PUT and FJOIN_RX_GET are both set, then the RX FIFO&#39;s registers can be randomly read/written by the state machine, but are completely inaccessible to the processor.
+
+                            Setting this bit will clear the FJOIN_TX and FJOIN_RX bits.</description>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>IN_COUNT</name>
+                        <description>Set the number of pins which are not masked to 0 when read by an IN PINS, WAIT PIN or MOV x, PINS instruction.
+
+                            For example, an IN_COUNT of 5 means that the 5 LSBs of the IN pin group are visible (bits 4:0), but the remaining 27 MSBs are masked to 0. A count of 32 is encoded with a field value of 0, so the default behaviour is to not perform any masking.
+
+                            Note this masking is applied in addition to the masking usually performed by the IN instruction. This is mainly useful for the MOV x, PINS instruction, which otherwise has no way of masking pins.</description>
+                        <bitRange>[4:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SM1_ADDR</name>
+                <addressOffset>0x000000ec</addressOffset>
+                <description>Current instruction address of state machine 1</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>SM1_ADDR</name>
+                        <bitRange>[4:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SM1_INSTR</name>
+                <addressOffset>0x000000f0</addressOffset>
+                <description>Read to see the instruction currently addressed by state machine 1&#39;s program counter 
+                    Write to execute an instruction immediately (including jumps) and then resume execution.</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>SM1_INSTR</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SM1_PINCTRL</name>
+                <addressOffset>0x000000f4</addressOffset>
+                <description>State machine pin control</description>
+                <resetValue>0x14000000</resetValue>
+                <fields>
+                    <field>
+                        <name>SIDESET_COUNT</name>
+                        <description>The number of MSBs of the Delay/Side-set instruction field which are used for side-set. Inclusive of the enable bit, if present. Minimum of 0 (all delay bits, no side-set) and maximum of 5 (all side-set, no delay).</description>
+                        <bitRange>[31:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SET_COUNT</name>
+                        <description>The number of pins asserted by a SET. In the range 0 to 5 inclusive.</description>
+                        <bitRange>[28:26]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>OUT_COUNT</name>
+                        <description>The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV PINS instruction. In the range 0 to 32 inclusive.</description>
+                        <bitRange>[25:20]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>IN_BASE</name>
+                        <description>The pin which is mapped to the least-significant bit of a state machine&#39;s IN data bus. Higher-numbered pins are mapped to consecutively more-significant data bits, with a modulo of 32 applied to pin number.</description>
+                        <bitRange>[19:15]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SIDESET_BASE</name>
+                        <description>The lowest-numbered pin that will be affected by a side-set operation. The MSBs of an instruction&#39;s side-set/delay field (up to 5, determined by SIDESET_COUNT) are used for side-set data, with the remaining LSBs used for delay. The least-significant bit of the side-set portion is the bit written to this pin, with more-significant bits written to higher-numbered pins.</description>
+                        <bitRange>[14:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SET_BASE</name>
+                        <description>The lowest-numbered pin that will be affected by a SET PINS or SET PINDIRS instruction. The data written to this pin is the least-significant bit of the SET data.</description>
+                        <bitRange>[9:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>OUT_BASE</name>
+                        <description>The lowest-numbered pin that will be affected by an OUT PINS, OUT PINDIRS or MOV PINS instruction. The data written to this pin will always be the least-significant bit of the OUT or MOV data.</description>
+                        <bitRange>[4:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SM2_CLKDIV</name>
+                <addressOffset>0x000000f8</addressOffset>
+                <description>Clock divisor register for state machine 2 
+                    Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256)</description>
+                <resetValue>0x00010000</resetValue>
+                <fields>
+                    <field>
+                        <name>INT</name>
+                        <description>Effective frequency is sysclk/(int + frac/256). 
+                            Value of 0 is interpreted as 65536. If INT is 0, FRAC must also be 0.</description>
+                        <bitRange>[31:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>FRAC</name>
+                        <description>Fractional part of clock divisor</description>
+                        <bitRange>[15:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SM2_EXECCTRL</name>
+                <addressOffset>0x000000fc</addressOffset>
+                <description>Execution/behavioural settings for state machine 2</description>
+                <resetValue>0x0001f000</resetValue>
+                <fields>
+                    <field>
+                        <name>EXEC_STALLED</name>
+                        <description>If 1, an instruction written to SMx_INSTR is stalled, and latched by the state machine. Will clear to 0 once this instruction completes.</description>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SIDE_EN</name>
+                        <description>If 1, the MSB of the Delay/Side-set instruction field is used as side-set enable, rather than a side-set data bit. This allows instructions to perform side-set optionally, rather than on every instruction, but the maximum possible side-set width is reduced from 5 to 4. Note that the value of PINCTRL_SIDESET_COUNT is inclusive of this enable bit.</description>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SIDE_PINDIR</name>
+                        <description>If 1, side-set data is asserted to pin directions, instead of pin values</description>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>JMP_PIN</name>
+                        <description>The GPIO number to use as condition for JMP PIN. Unaffected by input mapping.</description>
+                        <bitRange>[28:24]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>OUT_EN_SEL</name>
+                        <description>Which data bit to use for inline OUT enable</description>
+                        <bitRange>[23:19]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INLINE_OUT_EN</name>
+                        <description>If 1, use a bit of OUT data as an auxiliary write enable 
+                            When used in conjunction with OUT_STICKY, writes with an enable of 0 will 
+                            deassert the latest pin write. This can create useful masking/override behaviour 
+                            due to the priority ordering of state machine pin writes (SM0 &lt; SM1 &lt; ...)</description>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>OUT_STICKY</name>
+                        <description>Continuously assert the most recent OUT/SET to the pins</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>WRAP_TOP</name>
+                        <description>After reaching this address, execution is wrapped to wrap_bottom. 
+                            If the instruction is a jump, and the jump condition is true, the jump takes priority.</description>
+                        <bitRange>[16:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>WRAP_BOTTOM</name>
+                        <description>After reaching wrap_top, execution is wrapped to this address.</description>
+                        <bitRange>[11:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>STATUS_SEL</name>
+                        <description>Comparison used for the MOV x, STATUS instruction.</description>
+                        <bitRange>[6:5]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>TXLEVEL</name>
+                                <value>0</value>
+                                <description>All-ones if TX FIFO level &lt; N, otherwise all-zeroes</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>RXLEVEL</name>
+                                <value>1</value>
+                                <description>All-ones if RX FIFO level &lt; N, otherwise all-zeroes</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>IRQ</name>
+                                <value>2</value>
+                                <description>All-ones if the indexed IRQ flag is raised, otherwise all-zeroes</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>STATUS_N</name>
+                        <description>Comparison level or IRQ index for the MOV x, STATUS instruction.
+
+                            If STATUS_SEL is TXLEVEL or RXLEVEL, then values of STATUS_N greater than the current FIFO depth are reserved, and have undefined behaviour.</description>
+                        <bitRange>[4:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>IRQ</name>
+                                <value>0</value>
+                                <description>Index 0-7 of an IRQ flag in this PIO block</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>IRQ_PREVPIO</name>
+                                <value>8</value>
+                                <description>Index 0-7 of an IRQ flag in the next lower-numbered PIO block</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>IRQ_NEXTPIO</name>
+                                <value>16</value>
+                                <description>Index 0-7 of an IRQ flag in the next higher-numbered PIO block</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SM2_SHIFTCTRL</name>
+                <addressOffset>0x00000100</addressOffset>
+                <description>Control behaviour of the input/output shift registers for state machine 2</description>
+                <resetValue>0x000c0000</resetValue>
+                <fields>
+                    <field>
+                        <name>FJOIN_RX</name>
+                        <description>When 1, RX FIFO steals the TX FIFO&#39;s storage, and becomes twice as deep. 
+                            TX FIFO is disabled as a result (always reads as both full and empty). 
+                            FIFOs are flushed when this bit is changed.</description>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>FJOIN_TX</name>
+                        <description>When 1, TX FIFO steals the RX FIFO&#39;s storage, and becomes twice as deep. 
+                            RX FIFO is disabled as a result (always reads as both full and empty). 
+                            FIFOs are flushed when this bit is changed.</description>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PULL_THRESH</name>
+                        <description>Number of bits shifted out of OSR before autopull, or conditional pull (PULL IFEMPTY), will take place. 
+                            Write 0 for value of 32.</description>
+                        <bitRange>[29:25]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PUSH_THRESH</name>
+                        <description>Number of bits shifted into ISR before autopush, or conditional push (PUSH IFFULL), will take place. 
+                            Write 0 for value of 32.</description>
+                        <bitRange>[24:20]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>OUT_SHIFTDIR</name>
+                        <description>1 = shift out of output shift register to right. 0 = to left.</description>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>IN_SHIFTDIR</name>
+                        <description>1 = shift input shift register to right (data enters from left). 0 = to left.</description>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>AUTOPULL</name>
+                        <description>Pull automatically when the output shift register is emptied, i.e. on or following an OUT instruction which causes the output shift counter to reach or exceed PULL_THRESH.</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>AUTOPUSH</name>
+                        <description>Push automatically when the input shift register is filled, i.e. on an IN instruction which causes the input shift counter to reach or exceed PUSH_THRESH.</description>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>FJOIN_RX_PUT</name>
+                        <description>If 1, disable this state machine&#39;s RX FIFO, make its storage available for random write access by the state machine (using the `put` instruction) and, unless FJOIN_RX_GET is also set, random read access by the processor (through the RXFx_PUTGETy registers).
+
+                            If FJOIN_RX_PUT and FJOIN_RX_GET are both set, then the RX FIFO&#39;s registers can be randomly read/written by the state machine, but are completely inaccessible to the processor.
+
+                            Setting this bit will clear the FJOIN_TX and FJOIN_RX bits.</description>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>FJOIN_RX_GET</name>
+                        <description>If 1, disable this state machine&#39;s RX FIFO, make its storage available for random read access by the state machine (using the `get` instruction) and, unless FJOIN_RX_PUT is also set, random write access by the processor (through the RXFx_PUTGETy registers).
+
+                            If FJOIN_RX_PUT and FJOIN_RX_GET are both set, then the RX FIFO&#39;s registers can be randomly read/written by the state machine, but are completely inaccessible to the processor.
+
+                            Setting this bit will clear the FJOIN_TX and FJOIN_RX bits.</description>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>IN_COUNT</name>
+                        <description>Set the number of pins which are not masked to 0 when read by an IN PINS, WAIT PIN or MOV x, PINS instruction.
+
+                            For example, an IN_COUNT of 5 means that the 5 LSBs of the IN pin group are visible (bits 4:0), but the remaining 27 MSBs are masked to 0. A count of 32 is encoded with a field value of 0, so the default behaviour is to not perform any masking.
+
+                            Note this masking is applied in addition to the masking usually performed by the IN instruction. This is mainly useful for the MOV x, PINS instruction, which otherwise has no way of masking pins.</description>
+                        <bitRange>[4:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SM2_ADDR</name>
+                <addressOffset>0x00000104</addressOffset>
+                <description>Current instruction address of state machine 2</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>SM2_ADDR</name>
+                        <bitRange>[4:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SM2_INSTR</name>
+                <addressOffset>0x00000108</addressOffset>
+                <description>Read to see the instruction currently addressed by state machine 2&#39;s program counter 
+                    Write to execute an instruction immediately (including jumps) and then resume execution.</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>SM2_INSTR</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SM2_PINCTRL</name>
+                <addressOffset>0x0000010c</addressOffset>
+                <description>State machine pin control</description>
+                <resetValue>0x14000000</resetValue>
+                <fields>
+                    <field>
+                        <name>SIDESET_COUNT</name>
+                        <description>The number of MSBs of the Delay/Side-set instruction field which are used for side-set. Inclusive of the enable bit, if present. Minimum of 0 (all delay bits, no side-set) and maximum of 5 (all side-set, no delay).</description>
+                        <bitRange>[31:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SET_COUNT</name>
+                        <description>The number of pins asserted by a SET. In the range 0 to 5 inclusive.</description>
+                        <bitRange>[28:26]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>OUT_COUNT</name>
+                        <description>The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV PINS instruction. In the range 0 to 32 inclusive.</description>
+                        <bitRange>[25:20]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>IN_BASE</name>
+                        <description>The pin which is mapped to the least-significant bit of a state machine&#39;s IN data bus. Higher-numbered pins are mapped to consecutively more-significant data bits, with a modulo of 32 applied to pin number.</description>
+                        <bitRange>[19:15]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SIDESET_BASE</name>
+                        <description>The lowest-numbered pin that will be affected by a side-set operation. The MSBs of an instruction&#39;s side-set/delay field (up to 5, determined by SIDESET_COUNT) are used for side-set data, with the remaining LSBs used for delay. The least-significant bit of the side-set portion is the bit written to this pin, with more-significant bits written to higher-numbered pins.</description>
+                        <bitRange>[14:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SET_BASE</name>
+                        <description>The lowest-numbered pin that will be affected by a SET PINS or SET PINDIRS instruction. The data written to this pin is the least-significant bit of the SET data.</description>
+                        <bitRange>[9:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>OUT_BASE</name>
+                        <description>The lowest-numbered pin that will be affected by an OUT PINS, OUT PINDIRS or MOV PINS instruction. The data written to this pin will always be the least-significant bit of the OUT or MOV data.</description>
+                        <bitRange>[4:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SM3_CLKDIV</name>
+                <addressOffset>0x00000110</addressOffset>
+                <description>Clock divisor register for state machine 3 
+                    Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256)</description>
+                <resetValue>0x00010000</resetValue>
+                <fields>
+                    <field>
+                        <name>INT</name>
+                        <description>Effective frequency is sysclk/(int + frac/256). 
+                            Value of 0 is interpreted as 65536. If INT is 0, FRAC must also be 0.</description>
+                        <bitRange>[31:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>FRAC</name>
+                        <description>Fractional part of clock divisor</description>
+                        <bitRange>[15:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SM3_EXECCTRL</name>
+                <addressOffset>0x00000114</addressOffset>
+                <description>Execution/behavioural settings for state machine 3</description>
+                <resetValue>0x0001f000</resetValue>
+                <fields>
+                    <field>
+                        <name>EXEC_STALLED</name>
+                        <description>If 1, an instruction written to SMx_INSTR is stalled, and latched by the state machine. Will clear to 0 once this instruction completes.</description>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SIDE_EN</name>
+                        <description>If 1, the MSB of the Delay/Side-set instruction field is used as side-set enable, rather than a side-set data bit. This allows instructions to perform side-set optionally, rather than on every instruction, but the maximum possible side-set width is reduced from 5 to 4. Note that the value of PINCTRL_SIDESET_COUNT is inclusive of this enable bit.</description>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SIDE_PINDIR</name>
+                        <description>If 1, side-set data is asserted to pin directions, instead of pin values</description>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>JMP_PIN</name>
+                        <description>The GPIO number to use as condition for JMP PIN. Unaffected by input mapping.</description>
+                        <bitRange>[28:24]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>OUT_EN_SEL</name>
+                        <description>Which data bit to use for inline OUT enable</description>
+                        <bitRange>[23:19]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INLINE_OUT_EN</name>
+                        <description>If 1, use a bit of OUT data as an auxiliary write enable 
+                            When used in conjunction with OUT_STICKY, writes with an enable of 0 will 
+                            deassert the latest pin write. This can create useful masking/override behaviour 
+                            due to the priority ordering of state machine pin writes (SM0 &lt; SM1 &lt; ...)</description>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>OUT_STICKY</name>
+                        <description>Continuously assert the most recent OUT/SET to the pins</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>WRAP_TOP</name>
+                        <description>After reaching this address, execution is wrapped to wrap_bottom. 
+                            If the instruction is a jump, and the jump condition is true, the jump takes priority.</description>
+                        <bitRange>[16:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>WRAP_BOTTOM</name>
+                        <description>After reaching wrap_top, execution is wrapped to this address.</description>
+                        <bitRange>[11:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>STATUS_SEL</name>
+                        <description>Comparison used for the MOV x, STATUS instruction.</description>
+                        <bitRange>[6:5]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>TXLEVEL</name>
+                                <value>0</value>
+                                <description>All-ones if TX FIFO level &lt; N, otherwise all-zeroes</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>RXLEVEL</name>
+                                <value>1</value>
+                                <description>All-ones if RX FIFO level &lt; N, otherwise all-zeroes</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>IRQ</name>
+                                <value>2</value>
+                                <description>All-ones if the indexed IRQ flag is raised, otherwise all-zeroes</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>STATUS_N</name>
+                        <description>Comparison level or IRQ index for the MOV x, STATUS instruction.
+
+                            If STATUS_SEL is TXLEVEL or RXLEVEL, then values of STATUS_N greater than the current FIFO depth are reserved, and have undefined behaviour.</description>
+                        <bitRange>[4:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>IRQ</name>
+                                <value>0</value>
+                                <description>Index 0-7 of an IRQ flag in this PIO block</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>IRQ_PREVPIO</name>
+                                <value>8</value>
+                                <description>Index 0-7 of an IRQ flag in the next lower-numbered PIO block</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>IRQ_NEXTPIO</name>
+                                <value>16</value>
+                                <description>Index 0-7 of an IRQ flag in the next higher-numbered PIO block</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SM3_SHIFTCTRL</name>
+                <addressOffset>0x00000118</addressOffset>
+                <description>Control behaviour of the input/output shift registers for state machine 3</description>
+                <resetValue>0x000c0000</resetValue>
+                <fields>
+                    <field>
+                        <name>FJOIN_RX</name>
+                        <description>When 1, RX FIFO steals the TX FIFO&#39;s storage, and becomes twice as deep. 
+                            TX FIFO is disabled as a result (always reads as both full and empty). 
+                            FIFOs are flushed when this bit is changed.</description>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>FJOIN_TX</name>
+                        <description>When 1, TX FIFO steals the RX FIFO&#39;s storage, and becomes twice as deep. 
+                            RX FIFO is disabled as a result (always reads as both full and empty). 
+                            FIFOs are flushed when this bit is changed.</description>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PULL_THRESH</name>
+                        <description>Number of bits shifted out of OSR before autopull, or conditional pull (PULL IFEMPTY), will take place. 
+                            Write 0 for value of 32.</description>
+                        <bitRange>[29:25]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PUSH_THRESH</name>
+                        <description>Number of bits shifted into ISR before autopush, or conditional push (PUSH IFFULL), will take place. 
+                            Write 0 for value of 32.</description>
+                        <bitRange>[24:20]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>OUT_SHIFTDIR</name>
+                        <description>1 = shift out of output shift register to right. 0 = to left.</description>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>IN_SHIFTDIR</name>
+                        <description>1 = shift input shift register to right (data enters from left). 0 = to left.</description>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>AUTOPULL</name>
+                        <description>Pull automatically when the output shift register is emptied, i.e. on or following an OUT instruction which causes the output shift counter to reach or exceed PULL_THRESH.</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>AUTOPUSH</name>
+                        <description>Push automatically when the input shift register is filled, i.e. on an IN instruction which causes the input shift counter to reach or exceed PUSH_THRESH.</description>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>FJOIN_RX_PUT</name>
+                        <description>If 1, disable this state machine&#39;s RX FIFO, make its storage available for random write access by the state machine (using the `put` instruction) and, unless FJOIN_RX_GET is also set, random read access by the processor (through the RXFx_PUTGETy registers).
+
+                            If FJOIN_RX_PUT and FJOIN_RX_GET are both set, then the RX FIFO&#39;s registers can be randomly read/written by the state machine, but are completely inaccessible to the processor.
+
+                            Setting this bit will clear the FJOIN_TX and FJOIN_RX bits.</description>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>FJOIN_RX_GET</name>
+                        <description>If 1, disable this state machine&#39;s RX FIFO, make its storage available for random read access by the state machine (using the `get` instruction) and, unless FJOIN_RX_PUT is also set, random write access by the processor (through the RXFx_PUTGETy registers).
+
+                            If FJOIN_RX_PUT and FJOIN_RX_GET are both set, then the RX FIFO&#39;s registers can be randomly read/written by the state machine, but are completely inaccessible to the processor.
+
+                            Setting this bit will clear the FJOIN_TX and FJOIN_RX bits.</description>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>IN_COUNT</name>
+                        <description>Set the number of pins which are not masked to 0 when read by an IN PINS, WAIT PIN or MOV x, PINS instruction.
+
+                            For example, an IN_COUNT of 5 means that the 5 LSBs of the IN pin group are visible (bits 4:0), but the remaining 27 MSBs are masked to 0. A count of 32 is encoded with a field value of 0, so the default behaviour is to not perform any masking.
+
+                            Note this masking is applied in addition to the masking usually performed by the IN instruction. This is mainly useful for the MOV x, PINS instruction, which otherwise has no way of masking pins.</description>
+                        <bitRange>[4:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SM3_ADDR</name>
+                <addressOffset>0x0000011c</addressOffset>
+                <description>Current instruction address of state machine 3</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>SM3_ADDR</name>
+                        <bitRange>[4:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SM3_INSTR</name>
+                <addressOffset>0x00000120</addressOffset>
+                <description>Read to see the instruction currently addressed by state machine 3&#39;s program counter 
+                    Write to execute an instruction immediately (including jumps) and then resume execution.</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>SM3_INSTR</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SM3_PINCTRL</name>
+                <addressOffset>0x00000124</addressOffset>
+                <description>State machine pin control</description>
+                <resetValue>0x14000000</resetValue>
+                <fields>
+                    <field>
+                        <name>SIDESET_COUNT</name>
+                        <description>The number of MSBs of the Delay/Side-set instruction field which are used for side-set. Inclusive of the enable bit, if present. Minimum of 0 (all delay bits, no side-set) and maximum of 5 (all side-set, no delay).</description>
+                        <bitRange>[31:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SET_COUNT</name>
+                        <description>The number of pins asserted by a SET. In the range 0 to 5 inclusive.</description>
+                        <bitRange>[28:26]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>OUT_COUNT</name>
+                        <description>The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV PINS instruction. In the range 0 to 32 inclusive.</description>
+                        <bitRange>[25:20]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>IN_BASE</name>
+                        <description>The pin which is mapped to the least-significant bit of a state machine&#39;s IN data bus. Higher-numbered pins are mapped to consecutively more-significant data bits, with a modulo of 32 applied to pin number.</description>
+                        <bitRange>[19:15]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SIDESET_BASE</name>
+                        <description>The lowest-numbered pin that will be affected by a side-set operation. The MSBs of an instruction&#39;s side-set/delay field (up to 5, determined by SIDESET_COUNT) are used for side-set data, with the remaining LSBs used for delay. The least-significant bit of the side-set portion is the bit written to this pin, with more-significant bits written to higher-numbered pins.</description>
+                        <bitRange>[14:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SET_BASE</name>
+                        <description>The lowest-numbered pin that will be affected by a SET PINS or SET PINDIRS instruction. The data written to this pin is the least-significant bit of the SET data.</description>
+                        <bitRange>[9:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>OUT_BASE</name>
+                        <description>The lowest-numbered pin that will be affected by an OUT PINS, OUT PINDIRS or MOV PINS instruction. The data written to this pin will always be the least-significant bit of the OUT or MOV data.</description>
+                        <bitRange>[4:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>RXF0_PUTGET0</name>
+                <addressOffset>0x00000128</addressOffset>
+                <description>Direct read/write access to entry 0 of SM0&#39;s RX FIFO, if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>RXF0_PUTGET0</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>RXF0_PUTGET1</name>
+                <addressOffset>0x0000012c</addressOffset>
+                <description>Direct read/write access to entry 1 of SM0&#39;s RX FIFO, if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>RXF0_PUTGET1</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>RXF0_PUTGET2</name>
+                <addressOffset>0x00000130</addressOffset>
+                <description>Direct read/write access to entry 2 of SM0&#39;s RX FIFO, if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>RXF0_PUTGET2</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>RXF0_PUTGET3</name>
+                <addressOffset>0x00000134</addressOffset>
+                <description>Direct read/write access to entry 3 of SM0&#39;s RX FIFO, if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>RXF0_PUTGET3</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>RXF1_PUTGET0</name>
+                <addressOffset>0x00000138</addressOffset>
+                <description>Direct read/write access to entry 0 of SM1&#39;s RX FIFO, if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>RXF1_PUTGET0</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>RXF1_PUTGET1</name>
+                <addressOffset>0x0000013c</addressOffset>
+                <description>Direct read/write access to entry 1 of SM1&#39;s RX FIFO, if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>RXF1_PUTGET1</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>RXF1_PUTGET2</name>
+                <addressOffset>0x00000140</addressOffset>
+                <description>Direct read/write access to entry 2 of SM1&#39;s RX FIFO, if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>RXF1_PUTGET2</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>RXF1_PUTGET3</name>
+                <addressOffset>0x00000144</addressOffset>
+                <description>Direct read/write access to entry 3 of SM1&#39;s RX FIFO, if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>RXF1_PUTGET3</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>RXF2_PUTGET0</name>
+                <addressOffset>0x00000148</addressOffset>
+                <description>Direct read/write access to entry 0 of SM2&#39;s RX FIFO, if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>RXF2_PUTGET0</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>RXF2_PUTGET1</name>
+                <addressOffset>0x0000014c</addressOffset>
+                <description>Direct read/write access to entry 1 of SM2&#39;s RX FIFO, if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>RXF2_PUTGET1</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>RXF2_PUTGET2</name>
+                <addressOffset>0x00000150</addressOffset>
+                <description>Direct read/write access to entry 2 of SM2&#39;s RX FIFO, if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>RXF2_PUTGET2</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>RXF2_PUTGET3</name>
+                <addressOffset>0x00000154</addressOffset>
+                <description>Direct read/write access to entry 3 of SM2&#39;s RX FIFO, if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>RXF2_PUTGET3</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>RXF3_PUTGET0</name>
+                <addressOffset>0x00000158</addressOffset>
+                <description>Direct read/write access to entry 0 of SM3&#39;s RX FIFO, if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>RXF3_PUTGET0</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>RXF3_PUTGET1</name>
+                <addressOffset>0x0000015c</addressOffset>
+                <description>Direct read/write access to entry 1 of SM3&#39;s RX FIFO, if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>RXF3_PUTGET1</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>RXF3_PUTGET2</name>
+                <addressOffset>0x00000160</addressOffset>
+                <description>Direct read/write access to entry 2 of SM3&#39;s RX FIFO, if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>RXF3_PUTGET2</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>RXF3_PUTGET3</name>
+                <addressOffset>0x00000164</addressOffset>
+                <description>Direct read/write access to entry 3 of SM3&#39;s RX FIFO, if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>RXF3_PUTGET3</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIOBASE</name>
+                <addressOffset>0x00000168</addressOffset>
+                <description>Relocate GPIO 0 (from PIO&#39;s point of view) in the system GPIO numbering, to access more than 32 GPIOs from PIO.
+
+                    Only the values 0 and 16 are supported (only bit 4 is writable).</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>GPIOBASE</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INTR</name>
+                <addressOffset>0x0000016c</addressOffset>
+                <description>Raw Interrupts</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>SM7</name>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SM6</name>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SM5</name>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SM4</name>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SM3</name>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SM2</name>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SM1</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SM0</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SM3_TXNFULL</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SM2_TXNFULL</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SM1_TXNFULL</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SM0_TXNFULL</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SM3_RXNEMPTY</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SM2_RXNEMPTY</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SM1_RXNEMPTY</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SM0_RXNEMPTY</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>IRQ0_INTE</name>
+                <addressOffset>0x00000170</addressOffset>
+                <description>Interrupt Enable for irq0</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>SM7</name>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SM6</name>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SM5</name>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SM4</name>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SM3</name>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SM2</name>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SM1</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SM0</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SM3_TXNFULL</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SM2_TXNFULL</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SM1_TXNFULL</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SM0_TXNFULL</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SM3_RXNEMPTY</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SM2_RXNEMPTY</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SM1_RXNEMPTY</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SM0_RXNEMPTY</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>IRQ0_INTF</name>
+                <addressOffset>0x00000174</addressOffset>
+                <description>Interrupt Force for irq0</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>SM7</name>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SM6</name>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SM5</name>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SM4</name>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SM3</name>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SM2</name>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SM1</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SM0</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SM3_TXNFULL</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SM2_TXNFULL</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SM1_TXNFULL</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SM0_TXNFULL</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SM3_RXNEMPTY</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SM2_RXNEMPTY</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SM1_RXNEMPTY</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SM0_RXNEMPTY</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>IRQ0_INTS</name>
+                <addressOffset>0x00000178</addressOffset>
+                <description>Interrupt status after masking &amp; forcing for irq0</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>SM7</name>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SM6</name>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SM5</name>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SM4</name>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SM3</name>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SM2</name>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SM1</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SM0</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SM3_TXNFULL</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SM2_TXNFULL</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SM1_TXNFULL</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SM0_TXNFULL</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SM3_RXNEMPTY</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SM2_RXNEMPTY</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SM1_RXNEMPTY</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SM0_RXNEMPTY</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>IRQ1_INTE</name>
+                <addressOffset>0x0000017c</addressOffset>
+                <description>Interrupt Enable for irq1</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>SM7</name>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SM6</name>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SM5</name>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SM4</name>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SM3</name>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SM2</name>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SM1</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SM0</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SM3_TXNFULL</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SM2_TXNFULL</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SM1_TXNFULL</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SM0_TXNFULL</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SM3_RXNEMPTY</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SM2_RXNEMPTY</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SM1_RXNEMPTY</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SM0_RXNEMPTY</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>IRQ1_INTF</name>
+                <addressOffset>0x00000180</addressOffset>
+                <description>Interrupt Force for irq1</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>SM7</name>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SM6</name>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SM5</name>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SM4</name>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SM3</name>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SM2</name>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SM1</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SM0</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SM3_TXNFULL</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SM2_TXNFULL</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SM1_TXNFULL</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SM0_TXNFULL</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SM3_RXNEMPTY</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SM2_RXNEMPTY</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SM1_RXNEMPTY</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SM0_RXNEMPTY</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>IRQ1_INTS</name>
+                <addressOffset>0x00000184</addressOffset>
+                <description>Interrupt status after masking &amp; forcing for irq1</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>SM7</name>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SM6</name>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SM5</name>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SM4</name>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SM3</name>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SM2</name>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SM1</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SM0</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SM3_TXNFULL</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SM2_TXNFULL</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SM1_TXNFULL</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SM0_TXNFULL</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SM3_RXNEMPTY</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SM2_RXNEMPTY</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SM1_RXNEMPTY</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SM0_RXNEMPTY</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+        </registers>
+    </peripheral>
+    <peripheral derivedFrom="PIO0">
+        <name>PIO1</name>
+        <baseAddress>0x50300000</baseAddress>
+        <interrupt>
+        <name>PIO1_IRQ_0</name>
+        <value>17</value>
+    </interrupt>
+        <interrupt>
+        <name>PIO1_IRQ_1</name>
+        <value>18</value>
+    </interrupt>
+    </peripheral>
+    <peripheral derivedFrom="PIO0">
+        <name>PIO2</name>
+        <baseAddress>0x50400000</baseAddress>
+        <interrupt>
+        <name>PIO2_IRQ_0</name>
+        <value>19</value>
+    </interrupt>
+        <interrupt>
+        <name>PIO2_IRQ_1</name>
+        <value>20</value>
+    </interrupt>
+    </peripheral>
+    <peripheral>
+        <name>BUSCTRL</name>
+        <description>Register block for busfabric control signals and performance counters</description>
+        <baseAddress>0x40068000</baseAddress>
+        <addressBlock>
+            <offset>0</offset>
+            <size>44</size>
+            <usage>registers</usage>
+        </addressBlock>
+        <registers>
+            <register>
+                <name>BUS_PRIORITY</name>
+                <addressOffset>0x00000000</addressOffset>
+                <description>Set the priority of each master for bus arbitration.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>DMA_W</name>
+                        <description>0 - low priority, 1 - high priority</description>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DMA_R</name>
+                        <description>0 - low priority, 1 - high priority</description>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PROC1</name>
+                        <description>0 - low priority, 1 - high priority</description>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PROC0</name>
+                        <description>0 - low priority, 1 - high priority</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>BUS_PRIORITY_ACK</name>
+                <addressOffset>0x00000004</addressOffset>
+                <description>Bus priority acknowledge</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>BUS_PRIORITY_ACK</name>
+                        <description>Goes to 1 once all arbiters have registered the new global priority levels. 
+                            Arbiters update their local priority when servicing a new nonsequential access. 
+                            In normal circumstances this will happen almost immediately.</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PERFCTR_EN</name>
+                <addressOffset>0x00000008</addressOffset>
+                <description>Enable the performance counters. If 0, the performance counters do not increment. This can be used to precisely start/stop event sampling around the profiled section of code.
+
+                    The performance counters are initially disabled, to save energy.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>PERFCTR_EN</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PERFCTR0</name>
+                <addressOffset>0x0000000c</addressOffset>
+                <description>Bus fabric performance counter 0</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>PERFCTR0</name>
+                        <description>Busfabric saturating performance counter 0 
+                            Count some event signal from the busfabric arbiters, if PERFCTR_EN is set. 
+                            Write any value to clear. Select an event to count using PERFSEL0</description>
+                        <bitRange>[23:0]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PERFSEL0</name>
+                <addressOffset>0x00000010</addressOffset>
+                <description>Bus fabric performance event select for PERFCTR0</description>
+                <resetValue>0x0000001f</resetValue>
+                <fields>
+                    <field>
+                        <name>PERFSEL0</name>
+                        <description>Select an event for PERFCTR0. For each downstream port of the main crossbar, four events are available: ACCESS, an access took place; ACCESS_CONTESTED, an access took place that previously stalled due to contention from other masters; STALL_DOWNSTREAM, count cycles where any master stalled due to a stall on the downstream bus; STALL_UPSTREAM, count cycles where any master stalled for any reason, including contention from other masters.</description>
+                        <bitRange>[6:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>siob_proc1_stall_upstream</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>siob_proc1_stall_downstream</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>siob_proc1_access_contested</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>siob_proc1_access</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>siob_proc0_stall_upstream</name>
+                                <value>4</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>siob_proc0_stall_downstream</name>
+                                <value>5</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>siob_proc0_access_contested</name>
+                                <value>6</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>siob_proc0_access</name>
+                                <value>7</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>apb_stall_upstream</name>
+                                <value>8</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>apb_stall_downstream</name>
+                                <value>9</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>apb_access_contested</name>
+                                <value>10</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>apb_access</name>
+                                <value>11</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>fastperi_stall_upstream</name>
+                                <value>12</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>fastperi_stall_downstream</name>
+                                <value>13</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>fastperi_access_contested</name>
+                                <value>14</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>fastperi_access</name>
+                                <value>15</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram9_stall_upstream</name>
+                                <value>16</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram9_stall_downstream</name>
+                                <value>17</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram9_access_contested</name>
+                                <value>18</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram9_access</name>
+                                <value>19</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram8_stall_upstream</name>
+                                <value>20</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram8_stall_downstream</name>
+                                <value>21</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram8_access_contested</name>
+                                <value>22</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram8_access</name>
+                                <value>23</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram7_stall_upstream</name>
+                                <value>24</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram7_stall_downstream</name>
+                                <value>25</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram7_access_contested</name>
+                                <value>26</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram7_access</name>
+                                <value>27</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram6_stall_upstream</name>
+                                <value>28</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram6_stall_downstream</name>
+                                <value>29</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram6_access_contested</name>
+                                <value>30</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram6_access</name>
+                                <value>31</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram5_stall_upstream</name>
+                                <value>32</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram5_stall_downstream</name>
+                                <value>33</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram5_access_contested</name>
+                                <value>34</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram5_access</name>
+                                <value>35</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram4_stall_upstream</name>
+                                <value>36</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram4_stall_downstream</name>
+                                <value>37</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram4_access_contested</name>
+                                <value>38</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram4_access</name>
+                                <value>39</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram3_stall_upstream</name>
+                                <value>40</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram3_stall_downstream</name>
+                                <value>41</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram3_access_contested</name>
+                                <value>42</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram3_access</name>
+                                <value>43</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram2_stall_upstream</name>
+                                <value>44</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram2_stall_downstream</name>
+                                <value>45</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram2_access_contested</name>
+                                <value>46</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram2_access</name>
+                                <value>47</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram1_stall_upstream</name>
+                                <value>48</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram1_stall_downstream</name>
+                                <value>49</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram1_access_contested</name>
+                                <value>50</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram1_access</name>
+                                <value>51</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram0_stall_upstream</name>
+                                <value>52</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram0_stall_downstream</name>
+                                <value>53</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram0_access_contested</name>
+                                <value>54</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram0_access</name>
+                                <value>55</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>xip_main1_stall_upstream</name>
+                                <value>56</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>xip_main1_stall_downstream</name>
+                                <value>57</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>xip_main1_access_contested</name>
+                                <value>58</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>xip_main1_access</name>
+                                <value>59</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>xip_main0_stall_upstream</name>
+                                <value>60</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>xip_main0_stall_downstream</name>
+                                <value>61</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>xip_main0_access_contested</name>
+                                <value>62</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>xip_main0_access</name>
+                                <value>63</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>rom_stall_upstream</name>
+                                <value>64</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>rom_stall_downstream</name>
+                                <value>65</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>rom_access_contested</name>
+                                <value>66</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>rom_access</name>
+                                <value>67</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PERFCTR1</name>
+                <addressOffset>0x00000014</addressOffset>
+                <description>Bus fabric performance counter 1</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>PERFCTR1</name>
+                        <description>Busfabric saturating performance counter 1 
+                            Count some event signal from the busfabric arbiters, if PERFCTR_EN is set. 
+                            Write any value to clear. Select an event to count using PERFSEL1</description>
+                        <bitRange>[23:0]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PERFSEL1</name>
+                <addressOffset>0x00000018</addressOffset>
+                <description>Bus fabric performance event select for PERFCTR1</description>
+                <resetValue>0x0000001f</resetValue>
+                <fields>
+                    <field>
+                        <name>PERFSEL1</name>
+                        <description>Select an event for PERFCTR1. For each downstream port of the main crossbar, four events are available: ACCESS, an access took place; ACCESS_CONTESTED, an access took place that previously stalled due to contention from other masters; STALL_DOWNSTREAM, count cycles where any master stalled due to a stall on the downstream bus; STALL_UPSTREAM, count cycles where any master stalled for any reason, including contention from other masters.</description>
+                        <bitRange>[6:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>siob_proc1_stall_upstream</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>siob_proc1_stall_downstream</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>siob_proc1_access_contested</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>siob_proc1_access</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>siob_proc0_stall_upstream</name>
+                                <value>4</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>siob_proc0_stall_downstream</name>
+                                <value>5</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>siob_proc0_access_contested</name>
+                                <value>6</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>siob_proc0_access</name>
+                                <value>7</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>apb_stall_upstream</name>
+                                <value>8</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>apb_stall_downstream</name>
+                                <value>9</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>apb_access_contested</name>
+                                <value>10</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>apb_access</name>
+                                <value>11</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>fastperi_stall_upstream</name>
+                                <value>12</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>fastperi_stall_downstream</name>
+                                <value>13</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>fastperi_access_contested</name>
+                                <value>14</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>fastperi_access</name>
+                                <value>15</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram9_stall_upstream</name>
+                                <value>16</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram9_stall_downstream</name>
+                                <value>17</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram9_access_contested</name>
+                                <value>18</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram9_access</name>
+                                <value>19</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram8_stall_upstream</name>
+                                <value>20</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram8_stall_downstream</name>
+                                <value>21</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram8_access_contested</name>
+                                <value>22</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram8_access</name>
+                                <value>23</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram7_stall_upstream</name>
+                                <value>24</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram7_stall_downstream</name>
+                                <value>25</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram7_access_contested</name>
+                                <value>26</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram7_access</name>
+                                <value>27</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram6_stall_upstream</name>
+                                <value>28</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram6_stall_downstream</name>
+                                <value>29</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram6_access_contested</name>
+                                <value>30</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram6_access</name>
+                                <value>31</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram5_stall_upstream</name>
+                                <value>32</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram5_stall_downstream</name>
+                                <value>33</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram5_access_contested</name>
+                                <value>34</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram5_access</name>
+                                <value>35</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram4_stall_upstream</name>
+                                <value>36</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram4_stall_downstream</name>
+                                <value>37</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram4_access_contested</name>
+                                <value>38</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram4_access</name>
+                                <value>39</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram3_stall_upstream</name>
+                                <value>40</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram3_stall_downstream</name>
+                                <value>41</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram3_access_contested</name>
+                                <value>42</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram3_access</name>
+                                <value>43</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram2_stall_upstream</name>
+                                <value>44</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram2_stall_downstream</name>
+                                <value>45</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram2_access_contested</name>
+                                <value>46</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram2_access</name>
+                                <value>47</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram1_stall_upstream</name>
+                                <value>48</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram1_stall_downstream</name>
+                                <value>49</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram1_access_contested</name>
+                                <value>50</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram1_access</name>
+                                <value>51</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram0_stall_upstream</name>
+                                <value>52</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram0_stall_downstream</name>
+                                <value>53</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram0_access_contested</name>
+                                <value>54</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram0_access</name>
+                                <value>55</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>xip_main1_stall_upstream</name>
+                                <value>56</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>xip_main1_stall_downstream</name>
+                                <value>57</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>xip_main1_access_contested</name>
+                                <value>58</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>xip_main1_access</name>
+                                <value>59</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>xip_main0_stall_upstream</name>
+                                <value>60</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>xip_main0_stall_downstream</name>
+                                <value>61</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>xip_main0_access_contested</name>
+                                <value>62</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>xip_main0_access</name>
+                                <value>63</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>rom_stall_upstream</name>
+                                <value>64</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>rom_stall_downstream</name>
+                                <value>65</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>rom_access_contested</name>
+                                <value>66</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>rom_access</name>
+                                <value>67</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PERFCTR2</name>
+                <addressOffset>0x0000001c</addressOffset>
+                <description>Bus fabric performance counter 2</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>PERFCTR2</name>
+                        <description>Busfabric saturating performance counter 2 
+                            Count some event signal from the busfabric arbiters, if PERFCTR_EN is set. 
+                            Write any value to clear. Select an event to count using PERFSEL2</description>
+                        <bitRange>[23:0]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PERFSEL2</name>
+                <addressOffset>0x00000020</addressOffset>
+                <description>Bus fabric performance event select for PERFCTR2</description>
+                <resetValue>0x0000001f</resetValue>
+                <fields>
+                    <field>
+                        <name>PERFSEL2</name>
+                        <description>Select an event for PERFCTR2. For each downstream port of the main crossbar, four events are available: ACCESS, an access took place; ACCESS_CONTESTED, an access took place that previously stalled due to contention from other masters; STALL_DOWNSTREAM, count cycles where any master stalled due to a stall on the downstream bus; STALL_UPSTREAM, count cycles where any master stalled for any reason, including contention from other masters.</description>
+                        <bitRange>[6:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>siob_proc1_stall_upstream</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>siob_proc1_stall_downstream</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>siob_proc1_access_contested</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>siob_proc1_access</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>siob_proc0_stall_upstream</name>
+                                <value>4</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>siob_proc0_stall_downstream</name>
+                                <value>5</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>siob_proc0_access_contested</name>
+                                <value>6</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>siob_proc0_access</name>
+                                <value>7</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>apb_stall_upstream</name>
+                                <value>8</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>apb_stall_downstream</name>
+                                <value>9</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>apb_access_contested</name>
+                                <value>10</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>apb_access</name>
+                                <value>11</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>fastperi_stall_upstream</name>
+                                <value>12</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>fastperi_stall_downstream</name>
+                                <value>13</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>fastperi_access_contested</name>
+                                <value>14</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>fastperi_access</name>
+                                <value>15</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram9_stall_upstream</name>
+                                <value>16</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram9_stall_downstream</name>
+                                <value>17</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram9_access_contested</name>
+                                <value>18</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram9_access</name>
+                                <value>19</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram8_stall_upstream</name>
+                                <value>20</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram8_stall_downstream</name>
+                                <value>21</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram8_access_contested</name>
+                                <value>22</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram8_access</name>
+                                <value>23</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram7_stall_upstream</name>
+                                <value>24</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram7_stall_downstream</name>
+                                <value>25</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram7_access_contested</name>
+                                <value>26</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram7_access</name>
+                                <value>27</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram6_stall_upstream</name>
+                                <value>28</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram6_stall_downstream</name>
+                                <value>29</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram6_access_contested</name>
+                                <value>30</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram6_access</name>
+                                <value>31</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram5_stall_upstream</name>
+                                <value>32</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram5_stall_downstream</name>
+                                <value>33</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram5_access_contested</name>
+                                <value>34</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram5_access</name>
+                                <value>35</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram4_stall_upstream</name>
+                                <value>36</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram4_stall_downstream</name>
+                                <value>37</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram4_access_contested</name>
+                                <value>38</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram4_access</name>
+                                <value>39</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram3_stall_upstream</name>
+                                <value>40</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram3_stall_downstream</name>
+                                <value>41</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram3_access_contested</name>
+                                <value>42</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram3_access</name>
+                                <value>43</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram2_stall_upstream</name>
+                                <value>44</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram2_stall_downstream</name>
+                                <value>45</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram2_access_contested</name>
+                                <value>46</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram2_access</name>
+                                <value>47</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram1_stall_upstream</name>
+                                <value>48</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram1_stall_downstream</name>
+                                <value>49</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram1_access_contested</name>
+                                <value>50</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram1_access</name>
+                                <value>51</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram0_stall_upstream</name>
+                                <value>52</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram0_stall_downstream</name>
+                                <value>53</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram0_access_contested</name>
+                                <value>54</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram0_access</name>
+                                <value>55</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>xip_main1_stall_upstream</name>
+                                <value>56</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>xip_main1_stall_downstream</name>
+                                <value>57</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>xip_main1_access_contested</name>
+                                <value>58</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>xip_main1_access</name>
+                                <value>59</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>xip_main0_stall_upstream</name>
+                                <value>60</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>xip_main0_stall_downstream</name>
+                                <value>61</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>xip_main0_access_contested</name>
+                                <value>62</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>xip_main0_access</name>
+                                <value>63</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>rom_stall_upstream</name>
+                                <value>64</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>rom_stall_downstream</name>
+                                <value>65</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>rom_access_contested</name>
+                                <value>66</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>rom_access</name>
+                                <value>67</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PERFCTR3</name>
+                <addressOffset>0x00000024</addressOffset>
+                <description>Bus fabric performance counter 3</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>PERFCTR3</name>
+                        <description>Busfabric saturating performance counter 3 
+                            Count some event signal from the busfabric arbiters, if PERFCTR_EN is set. 
+                            Write any value to clear. Select an event to count using PERFSEL3</description>
+                        <bitRange>[23:0]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PERFSEL3</name>
+                <addressOffset>0x00000028</addressOffset>
+                <description>Bus fabric performance event select for PERFCTR3</description>
+                <resetValue>0x0000001f</resetValue>
+                <fields>
+                    <field>
+                        <name>PERFSEL3</name>
+                        <description>Select an event for PERFCTR3. For each downstream port of the main crossbar, four events are available: ACCESS, an access took place; ACCESS_CONTESTED, an access took place that previously stalled due to contention from other masters; STALL_DOWNSTREAM, count cycles where any master stalled due to a stall on the downstream bus; STALL_UPSTREAM, count cycles where any master stalled for any reason, including contention from other masters.</description>
+                        <bitRange>[6:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>siob_proc1_stall_upstream</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>siob_proc1_stall_downstream</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>siob_proc1_access_contested</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>siob_proc1_access</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>siob_proc0_stall_upstream</name>
+                                <value>4</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>siob_proc0_stall_downstream</name>
+                                <value>5</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>siob_proc0_access_contested</name>
+                                <value>6</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>siob_proc0_access</name>
+                                <value>7</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>apb_stall_upstream</name>
+                                <value>8</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>apb_stall_downstream</name>
+                                <value>9</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>apb_access_contested</name>
+                                <value>10</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>apb_access</name>
+                                <value>11</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>fastperi_stall_upstream</name>
+                                <value>12</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>fastperi_stall_downstream</name>
+                                <value>13</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>fastperi_access_contested</name>
+                                <value>14</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>fastperi_access</name>
+                                <value>15</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram9_stall_upstream</name>
+                                <value>16</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram9_stall_downstream</name>
+                                <value>17</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram9_access_contested</name>
+                                <value>18</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram9_access</name>
+                                <value>19</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram8_stall_upstream</name>
+                                <value>20</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram8_stall_downstream</name>
+                                <value>21</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram8_access_contested</name>
+                                <value>22</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram8_access</name>
+                                <value>23</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram7_stall_upstream</name>
+                                <value>24</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram7_stall_downstream</name>
+                                <value>25</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram7_access_contested</name>
+                                <value>26</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram7_access</name>
+                                <value>27</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram6_stall_upstream</name>
+                                <value>28</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram6_stall_downstream</name>
+                                <value>29</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram6_access_contested</name>
+                                <value>30</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram6_access</name>
+                                <value>31</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram5_stall_upstream</name>
+                                <value>32</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram5_stall_downstream</name>
+                                <value>33</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram5_access_contested</name>
+                                <value>34</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram5_access</name>
+                                <value>35</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram4_stall_upstream</name>
+                                <value>36</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram4_stall_downstream</name>
+                                <value>37</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram4_access_contested</name>
+                                <value>38</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram4_access</name>
+                                <value>39</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram3_stall_upstream</name>
+                                <value>40</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram3_stall_downstream</name>
+                                <value>41</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram3_access_contested</name>
+                                <value>42</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram3_access</name>
+                                <value>43</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram2_stall_upstream</name>
+                                <value>44</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram2_stall_downstream</name>
+                                <value>45</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram2_access_contested</name>
+                                <value>46</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram2_access</name>
+                                <value>47</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram1_stall_upstream</name>
+                                <value>48</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram1_stall_downstream</name>
+                                <value>49</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram1_access_contested</name>
+                                <value>50</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram1_access</name>
+                                <value>51</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram0_stall_upstream</name>
+                                <value>52</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram0_stall_downstream</name>
+                                <value>53</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram0_access_contested</name>
+                                <value>54</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>sram0_access</name>
+                                <value>55</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>xip_main1_stall_upstream</name>
+                                <value>56</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>xip_main1_stall_downstream</name>
+                                <value>57</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>xip_main1_access_contested</name>
+                                <value>58</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>xip_main1_access</name>
+                                <value>59</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>xip_main0_stall_upstream</name>
+                                <value>60</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>xip_main0_stall_downstream</name>
+                                <value>61</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>xip_main0_access_contested</name>
+                                <value>62</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>xip_main0_access</name>
+                                <value>63</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>rom_stall_upstream</name>
+                                <value>64</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>rom_stall_downstream</name>
+                                <value>65</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>rom_access_contested</name>
+                                <value>66</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>rom_access</name>
+                                <value>67</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+        </registers>
+    </peripheral>
+    <peripheral>
+        <name>SIO</name>
+        <description>Single-cycle IO block 
+            Provides core-local and inter-core hardware for the two processors, with single-cycle access.</description>
+        <baseAddress>0xd0000000</baseAddress>
+        <addressBlock>
+            <offset>0</offset>
+            <size>488</size>
+            <usage>registers</usage>
+        </addressBlock>
+        <interrupt>
+            <name>SIO_IRQ_FIFO</name>
+            <value>25</value>
+        </interrupt>
+        <interrupt>
+            <name>SIO_IRQ_BELL</name>
+            <value>26</value>
+        </interrupt>
+        <interrupt>
+            <name>SIO_IRQ_FIFO_NS</name>
+            <value>27</value>
+        </interrupt>
+        <interrupt>
+            <name>SIO_IRQ_BELL_NS</name>
+            <value>28</value>
+        </interrupt>
+        <interrupt>
+            <name>SIO_IRQ_MTIMECMP</name>
+            <value>29</value>
+        </interrupt>
+        <registers>
+            <register>
+                <name>CPUID</name>
+                <addressOffset>0x00000000</addressOffset>
+                <description>Processor core identifier</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CPUID</name>
+                        <description>Value is 0 when read from processor core 0, and 1 when read from processor core 1.</description>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO_IN</name>
+                <addressOffset>0x00000004</addressOffset>
+                <description>Input value for GPIO0...31.
+
+                    In the Non-secure SIO, Secure-only GPIOs (as per ACCESSCTRL) appear as zero.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>GPIO_IN</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO_HI_IN</name>
+                <addressOffset>0x00000008</addressOffset>
+                <description>Input value on GPIO32...47, QSPI IOs and USB pins
+
+                    In the Non-secure SIO, Secure-only GPIOs (as per ACCESSCTRL) appear as zero.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>QSPI_SD</name>
+                        <description>Input value on QSPI SD0 (MOSI), SD1 (MISO), SD2 and SD3 pins</description>
+                        <bitRange>[31:28]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>QSPI_CSN</name>
+                        <description>Input value on QSPI CSn pin</description>
+                        <bitRange>[27:27]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>QSPI_SCK</name>
+                        <description>Input value on QSPI SCK pin</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>USB_DM</name>
+                        <description>Input value on USB D- pin</description>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>USB_DP</name>
+                        <description>Input value on USB D+ pin</description>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO</name>
+                        <description>Input value on GPIO32...47</description>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO_OUT</name>
+                <addressOffset>0x00000010</addressOffset>
+                <description>GPIO0...31 output value</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>GPIO_OUT</name>
+                        <description>Set output level (1/0 -&gt; high/low) for GPIO0...31. Reading back gives the last value written, NOT the input value from the pins.
+
+                            If core 0 and core 1 both write to GPIO_OUT simultaneously (or to a SET/CLR/XOR alias), the result is as though the write from core 0 took place first, and the write from core 1 was then applied to that intermediate result.
+
+                            In the Non-secure SIO, Secure-only GPIOs (as per ACCESSCTRL) ignore writes, and their output status reads back as zero. This is also true for SET/CLR/XOR aliases of this register.</description>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO_HI_OUT</name>
+                <addressOffset>0x00000014</addressOffset>
+                <description>Output value for GPIO32...47, QSPI IOs and USB pins.
+
+                    Write to set output level (1/0 -&gt; high/low). Reading back gives the last value written, NOT the input value from the pins. If core 0 and core 1 both write to GPIO_HI_OUT simultaneously (or to a SET/CLR/XOR alias), the result is as though the write from core 0 took place first, and the write from core 1 was then applied to that intermediate result.
+
+                    In the Non-secure SIO, Secure-only GPIOs (as per ACCESSCTRL) ignore writes, and their output status reads back as zero. This is also true for SET/CLR/XOR aliases of this register.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>QSPI_SD</name>
+                        <description>Output value for QSPI SD0 (MOSI), SD1 (MISO), SD2 and SD3 pins</description>
+                        <bitRange>[31:28]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>QSPI_CSN</name>
+                        <description>Output value for QSPI CSn pin</description>
+                        <bitRange>[27:27]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>QSPI_SCK</name>
+                        <description>Output value for QSPI SCK pin</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>USB_DM</name>
+                        <description>Output value for USB D- pin</description>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>USB_DP</name>
+                        <description>Output value for USB D+ pin</description>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO</name>
+                        <description>Output value for GPIO32...47</description>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO_OUT_SET</name>
+                <addressOffset>0x00000018</addressOffset>
+                <description>GPIO0...31 output value set</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>GPIO_OUT_SET</name>
+                        <description>Perform an atomic bit-set on GPIO_OUT, i.e. `GPIO_OUT |= wdata`</description>
+                        <bitRange>[31:0]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO_HI_OUT_SET</name>
+                <addressOffset>0x0000001c</addressOffset>
+                <description>Output value set for GPIO32..47, QSPI IOs and USB pins. 
+                    Perform an atomic bit-set on GPIO_HI_OUT, i.e. `GPIO_HI_OUT |= wdata`</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>QSPI_SD</name>
+                        <bitRange>[31:28]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>QSPI_CSN</name>
+                        <bitRange>[27:27]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>QSPI_SCK</name>
+                        <bitRange>[26:26]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>USB_DM</name>
+                        <bitRange>[25:25]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>USB_DP</name>
+                        <bitRange>[24:24]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO_OUT_CLR</name>
+                <addressOffset>0x00000020</addressOffset>
+                <description>GPIO0...31 output value clear</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>GPIO_OUT_CLR</name>
+                        <description>Perform an atomic bit-clear on GPIO_OUT, i.e. `GPIO_OUT &amp;= ~wdata`</description>
+                        <bitRange>[31:0]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO_HI_OUT_CLR</name>
+                <addressOffset>0x00000024</addressOffset>
+                <description>Output value clear for GPIO32..47, QSPI IOs and USB pins. 
+                    Perform an atomic bit-clear on GPIO_HI_OUT, i.e. `GPIO_HI_OUT &amp;= ~wdata`</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>QSPI_SD</name>
+                        <bitRange>[31:28]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>QSPI_CSN</name>
+                        <bitRange>[27:27]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>QSPI_SCK</name>
+                        <bitRange>[26:26]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>USB_DM</name>
+                        <bitRange>[25:25]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>USB_DP</name>
+                        <bitRange>[24:24]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO_OUT_XOR</name>
+                <addressOffset>0x00000028</addressOffset>
+                <description>GPIO0...31 output value XOR</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>GPIO_OUT_XOR</name>
+                        <description>Perform an atomic bitwise XOR on GPIO_OUT, i.e. `GPIO_OUT ^= wdata`</description>
+                        <bitRange>[31:0]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO_HI_OUT_XOR</name>
+                <addressOffset>0x0000002c</addressOffset>
+                <description>Output value XOR for GPIO32..47, QSPI IOs and USB pins. 
+                    Perform an atomic bitwise XOR on GPIO_HI_OUT, i.e. `GPIO_HI_OUT ^= wdata`</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>QSPI_SD</name>
+                        <bitRange>[31:28]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>QSPI_CSN</name>
+                        <bitRange>[27:27]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>QSPI_SCK</name>
+                        <bitRange>[26:26]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>USB_DM</name>
+                        <bitRange>[25:25]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>USB_DP</name>
+                        <bitRange>[24:24]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO_OE</name>
+                <addressOffset>0x00000030</addressOffset>
+                <description>GPIO0...31 output enable</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>GPIO_OE</name>
+                        <description>Set output enable (1/0 -&gt; output/input) for GPIO0...31. Reading back gives the last value written.
+
+                            If core 0 and core 1 both write to GPIO_OE simultaneously (or to a SET/CLR/XOR alias), the result is as though the write from core 0 took place first, and the write from core 1 was then applied to that intermediate result.
+
+                            In the Non-secure SIO, Secure-only GPIOs (as per ACCESSCTRL) ignore writes, and their output status reads back as zero. This is also true for SET/CLR/XOR aliases of this register.</description>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO_HI_OE</name>
+                <addressOffset>0x00000034</addressOffset>
+                <description>Output enable value for GPIO32...47, QSPI IOs and USB pins.
+
+                    Write output enable (1/0 -&gt; output/input). Reading back gives the last value written. If core 0 and core 1 both write to GPIO_HI_OE simultaneously (or to a SET/CLR/XOR alias), the result is as though the write from core 0 took place first, and the write from core 1 was then applied to that intermediate result.
+
+                    In the Non-secure SIO, Secure-only GPIOs (as per ACCESSCTRL) ignore writes, and their output status reads back as zero. This is also true for SET/CLR/XOR aliases of this register.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>QSPI_SD</name>
+                        <description>Output enable value for QSPI SD0 (MOSI), SD1 (MISO), SD2 and SD3 pins</description>
+                        <bitRange>[31:28]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>QSPI_CSN</name>
+                        <description>Output enable value for QSPI CSn pin</description>
+                        <bitRange>[27:27]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>QSPI_SCK</name>
+                        <description>Output enable value for QSPI SCK pin</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>USB_DM</name>
+                        <description>Output enable value for USB D- pin</description>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>USB_DP</name>
+                        <description>Output enable value for USB D+ pin</description>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>GPIO</name>
+                        <description>Output enable value for GPIO32...47</description>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO_OE_SET</name>
+                <addressOffset>0x00000038</addressOffset>
+                <description>GPIO0...31 output enable set</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>GPIO_OE_SET</name>
+                        <description>Perform an atomic bit-set on GPIO_OE, i.e. `GPIO_OE |= wdata`</description>
+                        <bitRange>[31:0]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO_HI_OE_SET</name>
+                <addressOffset>0x0000003c</addressOffset>
+                <description>Output enable set for GPIO32...47, QSPI IOs and USB pins. 
+                    Perform an atomic bit-set on GPIO_HI_OE, i.e. `GPIO_HI_OE |= wdata`</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>QSPI_SD</name>
+                        <bitRange>[31:28]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>QSPI_CSN</name>
+                        <bitRange>[27:27]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>QSPI_SCK</name>
+                        <bitRange>[26:26]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>USB_DM</name>
+                        <bitRange>[25:25]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>USB_DP</name>
+                        <bitRange>[24:24]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO_OE_CLR</name>
+                <addressOffset>0x00000040</addressOffset>
+                <description>GPIO0...31 output enable clear</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>GPIO_OE_CLR</name>
+                        <description>Perform an atomic bit-clear on GPIO_OE, i.e. `GPIO_OE &amp;= ~wdata`</description>
+                        <bitRange>[31:0]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO_HI_OE_CLR</name>
+                <addressOffset>0x00000044</addressOffset>
+                <description>Output enable clear for GPIO32...47, QSPI IOs and USB pins. 
+                    Perform an atomic bit-clear on GPIO_HI_OE, i.e. `GPIO_HI_OE &amp;= ~wdata`</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>QSPI_SD</name>
+                        <bitRange>[31:28]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>QSPI_CSN</name>
+                        <bitRange>[27:27]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>QSPI_SCK</name>
+                        <bitRange>[26:26]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>USB_DM</name>
+                        <bitRange>[25:25]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>USB_DP</name>
+                        <bitRange>[24:24]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO_OE_XOR</name>
+                <addressOffset>0x00000048</addressOffset>
+                <description>GPIO0...31 output enable XOR</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>GPIO_OE_XOR</name>
+                        <description>Perform an atomic bitwise XOR on GPIO_OE, i.e. `GPIO_OE ^= wdata`</description>
+                        <bitRange>[31:0]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>GPIO_HI_OE_XOR</name>
+                <addressOffset>0x0000004c</addressOffset>
+                <description>Output enable XOR for GPIO32...47, QSPI IOs and USB pins. 
+                    Perform an atomic bitwise XOR on GPIO_HI_OE, i.e. `GPIO_HI_OE ^= wdata`</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>QSPI_SD</name>
+                        <bitRange>[31:28]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>QSPI_CSN</name>
+                        <bitRange>[27:27]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>QSPI_SCK</name>
+                        <bitRange>[26:26]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>USB_DM</name>
+                        <bitRange>[25:25]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>USB_DP</name>
+                        <bitRange>[24:24]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>GPIO</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>FIFO_ST</name>
+                <addressOffset>0x00000050</addressOffset>
+                <description>Status register for inter-core FIFOs (mailboxes). 
+                    There is one FIFO in the core 0 -&gt; core 1 direction, and one core 1 -&gt; core 0. Both are 32 bits wide and 8 words deep. 
+                    Core 0 can see the read side of the 1-&gt;0 FIFO (RX), and the write side of 0-&gt;1 FIFO (TX). 
+                    Core 1 can see the read side of the 0-&gt;1 FIFO (RX), and the write side of 1-&gt;0 FIFO (TX). 
+                    The SIO IRQ for each core is the logical OR of the VLD, WOF and ROE fields of its FIFO_ST register.</description>
+                <resetValue>0x00000002</resetValue>
+                <fields>
+                    <field>
+                        <name>ROE</name>
+                        <description>Sticky flag indicating the RX FIFO was read when empty. This read was ignored by the FIFO.</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>WOF</name>
+                        <description>Sticky flag indicating the TX FIFO was written when full. This write was ignored by the FIFO.</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>RDY</name>
+                        <description>Value is 1 if this core&#39;s TX FIFO is not full (i.e. if FIFO_WR is ready for more data)</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>VLD</name>
+                        <description>Value is 1 if this core&#39;s RX FIFO is not empty (i.e. if FIFO_RD is valid)</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>FIFO_WR</name>
+                <addressOffset>0x00000054</addressOffset>
+                <description>Write access to this core&#39;s TX FIFO</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>FIFO_WR</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>FIFO_RD</name>
+                <addressOffset>0x00000058</addressOffset>
+                <description>Read access to this core&#39;s RX FIFO</description>
+                <resetMask>0x00000000</resetMask>
+                <fields>
+                    <field>
+                        <name>FIFO_RD</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-only</access>
+                        <readAction>modify</readAction>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SPINLOCK_ST</name>
+                <addressOffset>0x0000005c</addressOffset>
+                <description>Spinlock state 
+                    A bitmap containing the state of all 32 spinlocks (1=locked). 
+                    Mainly intended for debugging.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>SPINLOCK_ST</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INTERP0_ACCUM0</name>
+                <addressOffset>0x00000080</addressOffset>
+                <description>Read/write access to accumulator 0</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>INTERP0_ACCUM0</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INTERP0_ACCUM1</name>
+                <addressOffset>0x00000084</addressOffset>
+                <description>Read/write access to accumulator 1</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>INTERP0_ACCUM1</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INTERP0_BASE0</name>
+                <addressOffset>0x00000088</addressOffset>
+                <description>Read/write access to BASE0 register.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>INTERP0_BASE0</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INTERP0_BASE1</name>
+                <addressOffset>0x0000008c</addressOffset>
+                <description>Read/write access to BASE1 register.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>INTERP0_BASE1</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INTERP0_BASE2</name>
+                <addressOffset>0x00000090</addressOffset>
+                <description>Read/write access to BASE2 register.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>INTERP0_BASE2</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INTERP0_POP_LANE0</name>
+                <addressOffset>0x00000094</addressOffset>
+                <description>Read LANE0 result, and simultaneously write lane results to both accumulators (POP).</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>INTERP0_POP_LANE0</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INTERP0_POP_LANE1</name>
+                <addressOffset>0x00000098</addressOffset>
+                <description>Read LANE1 result, and simultaneously write lane results to both accumulators (POP).</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>INTERP0_POP_LANE1</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INTERP0_POP_FULL</name>
+                <addressOffset>0x0000009c</addressOffset>
+                <description>Read FULL result, and simultaneously write lane results to both accumulators (POP).</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>INTERP0_POP_FULL</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INTERP0_PEEK_LANE0</name>
+                <addressOffset>0x000000a0</addressOffset>
+                <description>Read LANE0 result, without altering any internal state (PEEK).</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>INTERP0_PEEK_LANE0</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INTERP0_PEEK_LANE1</name>
+                <addressOffset>0x000000a4</addressOffset>
+                <description>Read LANE1 result, without altering any internal state (PEEK).</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>INTERP0_PEEK_LANE1</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INTERP0_PEEK_FULL</name>
+                <addressOffset>0x000000a8</addressOffset>
+                <description>Read FULL result, without altering any internal state (PEEK).</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>INTERP0_PEEK_FULL</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INTERP0_CTRL_LANE0</name>
+                <addressOffset>0x000000ac</addressOffset>
+                <description>Control register for lane 0</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>OVERF</name>
+                        <description>Set if either OVERF0 or OVERF1 is set.</description>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OVERF1</name>
+                        <description>Indicates if any masked-off MSBs in ACCUM1 are set.</description>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OVERF0</name>
+                        <description>Indicates if any masked-off MSBs in ACCUM0 are set.</description>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>BLEND</name>
+                        <description>Only present on INTERP0 on each core. If BLEND mode is enabled: 
+                            - LANE1 result is a linear interpolation between BASE0 and BASE1, controlled 
+                            by the 8 LSBs of lane 1 shift and mask value (a fractional number between 
+                            0 and 255/256ths) 
+                            - LANE0 result does not have BASE0 added (yields only the 8 LSBs of lane 1 shift+mask value) 
+                            - FULL result does not have lane 1 shift+mask value added (BASE2 + lane 0 shift+mask) 
+                            LANE1 SIGNED flag controls whether the interpolation is signed or unsigned.</description>
+                        <bitRange>[21:21]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>FORCE_MSB</name>
+                        <description>ORed into bits 29:28 of the lane result presented to the processor on the bus. 
+                            No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence 
+                            of pointers into flash or SRAM.</description>
+                        <bitRange>[20:19]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ADD_RAW</name>
+                        <description>If 1, mask + shift is bypassed for LANE0 result. This does not affect FULL result.</description>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CROSS_RESULT</name>
+                        <description>If 1, feed the opposite lane&#39;s result into this lane&#39;s accumulator on POP.</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CROSS_INPUT</name>
+                        <description>If 1, feed the opposite lane&#39;s accumulator into this lane&#39;s shift + mask hardware. 
+                            Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass)</description>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SIGNED</name>
+                        <description>If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits 
+                            before adding to BASE0, and LANE0 PEEK/POP appear extended to 32 bits when read by processor.</description>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>MASK_MSB</name>
+                        <description>The most-significant bit allowed to pass by the mask (inclusive) 
+                            Setting MSB &lt; LSB may cause chip to turn inside-out</description>
+                        <bitRange>[14:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>MASK_LSB</name>
+                        <description>The least-significant bit allowed to pass by the mask (inclusive)</description>
+                        <bitRange>[9:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SHIFT</name>
+                        <description>Right-rotate applied to accumulator before masking. By appropriately configuring the masks, left and right shifts can be synthesised.</description>
+                        <bitRange>[4:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INTERP0_CTRL_LANE1</name>
+                <addressOffset>0x000000b0</addressOffset>
+                <description>Control register for lane 1</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>FORCE_MSB</name>
+                        <description>ORed into bits 29:28 of the lane result presented to the processor on the bus. 
+                            No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence 
+                            of pointers into flash or SRAM.</description>
+                        <bitRange>[20:19]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ADD_RAW</name>
+                        <description>If 1, mask + shift is bypassed for LANE1 result. This does not affect FULL result.</description>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CROSS_RESULT</name>
+                        <description>If 1, feed the opposite lane&#39;s result into this lane&#39;s accumulator on POP.</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CROSS_INPUT</name>
+                        <description>If 1, feed the opposite lane&#39;s accumulator into this lane&#39;s shift + mask hardware. 
+                            Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass)</description>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SIGNED</name>
+                        <description>If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits 
+                            before adding to BASE1, and LANE1 PEEK/POP appear extended to 32 bits when read by processor.</description>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>MASK_MSB</name>
+                        <description>The most-significant bit allowed to pass by the mask (inclusive) 
+                            Setting MSB &lt; LSB may cause chip to turn inside-out</description>
+                        <bitRange>[14:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>MASK_LSB</name>
+                        <description>The least-significant bit allowed to pass by the mask (inclusive)</description>
+                        <bitRange>[9:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SHIFT</name>
+                        <description>Right-rotate applied to accumulator before masking. By appropriately configuring the masks, left and right shifts can be synthesised.</description>
+                        <bitRange>[4:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INTERP0_ACCUM0_ADD</name>
+                <addressOffset>0x000000b4</addressOffset>
+                <description>Values written here are atomically added to ACCUM0 
+                    Reading yields lane 0&#39;s raw shift and mask value (BASE0 not added).</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>INTERP0_ACCUM0_ADD</name>
+                        <bitRange>[23:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INTERP0_ACCUM1_ADD</name>
+                <addressOffset>0x000000b8</addressOffset>
+                <description>Values written here are atomically added to ACCUM1 
+                    Reading yields lane 1&#39;s raw shift and mask value (BASE1 not added).</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>INTERP0_ACCUM1_ADD</name>
+                        <bitRange>[23:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INTERP0_BASE_1AND0</name>
+                <addressOffset>0x000000bc</addressOffset>
+                <description>On write, the lower 16 bits go to BASE0, upper bits to BASE1 simultaneously. 
+                    Each half is sign-extended to 32 bits if that lane&#39;s SIGNED flag is set.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>INTERP0_BASE_1AND0</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INTERP1_ACCUM0</name>
+                <addressOffset>0x000000c0</addressOffset>
+                <description>Read/write access to accumulator 0</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>INTERP1_ACCUM0</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INTERP1_ACCUM1</name>
+                <addressOffset>0x000000c4</addressOffset>
+                <description>Read/write access to accumulator 1</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>INTERP1_ACCUM1</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INTERP1_BASE0</name>
+                <addressOffset>0x000000c8</addressOffset>
+                <description>Read/write access to BASE0 register.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>INTERP1_BASE0</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INTERP1_BASE1</name>
+                <addressOffset>0x000000cc</addressOffset>
+                <description>Read/write access to BASE1 register.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>INTERP1_BASE1</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INTERP1_BASE2</name>
+                <addressOffset>0x000000d0</addressOffset>
+                <description>Read/write access to BASE2 register.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>INTERP1_BASE2</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INTERP1_POP_LANE0</name>
+                <addressOffset>0x000000d4</addressOffset>
+                <description>Read LANE0 result, and simultaneously write lane results to both accumulators (POP).</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>INTERP1_POP_LANE0</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INTERP1_POP_LANE1</name>
+                <addressOffset>0x000000d8</addressOffset>
+                <description>Read LANE1 result, and simultaneously write lane results to both accumulators (POP).</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>INTERP1_POP_LANE1</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INTERP1_POP_FULL</name>
+                <addressOffset>0x000000dc</addressOffset>
+                <description>Read FULL result, and simultaneously write lane results to both accumulators (POP).</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>INTERP1_POP_FULL</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INTERP1_PEEK_LANE0</name>
+                <addressOffset>0x000000e0</addressOffset>
+                <description>Read LANE0 result, without altering any internal state (PEEK).</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>INTERP1_PEEK_LANE0</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INTERP1_PEEK_LANE1</name>
+                <addressOffset>0x000000e4</addressOffset>
+                <description>Read LANE1 result, without altering any internal state (PEEK).</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>INTERP1_PEEK_LANE1</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INTERP1_PEEK_FULL</name>
+                <addressOffset>0x000000e8</addressOffset>
+                <description>Read FULL result, without altering any internal state (PEEK).</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>INTERP1_PEEK_FULL</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INTERP1_CTRL_LANE0</name>
+                <addressOffset>0x000000ec</addressOffset>
+                <description>Control register for lane 0</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>OVERF</name>
+                        <description>Set if either OVERF0 or OVERF1 is set.</description>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OVERF1</name>
+                        <description>Indicates if any masked-off MSBs in ACCUM1 are set.</description>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OVERF0</name>
+                        <description>Indicates if any masked-off MSBs in ACCUM0 are set.</description>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CLAMP</name>
+                        <description>Only present on INTERP1 on each core. If CLAMP mode is enabled: 
+                            - LANE0 result is shifted and masked ACCUM0, clamped by a lower bound of 
+                            BASE0 and an upper bound of BASE1. 
+                            - Signedness of these comparisons is determined by LANE0_CTRL_SIGNED</description>
+                        <bitRange>[22:22]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>FORCE_MSB</name>
+                        <description>ORed into bits 29:28 of the lane result presented to the processor on the bus. 
+                            No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence 
+                            of pointers into flash or SRAM.</description>
+                        <bitRange>[20:19]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ADD_RAW</name>
+                        <description>If 1, mask + shift is bypassed for LANE0 result. This does not affect FULL result.</description>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CROSS_RESULT</name>
+                        <description>If 1, feed the opposite lane&#39;s result into this lane&#39;s accumulator on POP.</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CROSS_INPUT</name>
+                        <description>If 1, feed the opposite lane&#39;s accumulator into this lane&#39;s shift + mask hardware. 
+                            Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass)</description>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SIGNED</name>
+                        <description>If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits 
+                            before adding to BASE0, and LANE0 PEEK/POP appear extended to 32 bits when read by processor.</description>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>MASK_MSB</name>
+                        <description>The most-significant bit allowed to pass by the mask (inclusive) 
+                            Setting MSB &lt; LSB may cause chip to turn inside-out</description>
+                        <bitRange>[14:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>MASK_LSB</name>
+                        <description>The least-significant bit allowed to pass by the mask (inclusive)</description>
+                        <bitRange>[9:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SHIFT</name>
+                        <description>Right-rotate applied to accumulator before masking. By appropriately configuring the masks, left and right shifts can be synthesised.</description>
+                        <bitRange>[4:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INTERP1_CTRL_LANE1</name>
+                <addressOffset>0x000000f0</addressOffset>
+                <description>Control register for lane 1</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>FORCE_MSB</name>
+                        <description>ORed into bits 29:28 of the lane result presented to the processor on the bus. 
+                            No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence 
+                            of pointers into flash or SRAM.</description>
+                        <bitRange>[20:19]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ADD_RAW</name>
+                        <description>If 1, mask + shift is bypassed for LANE1 result. This does not affect FULL result.</description>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CROSS_RESULT</name>
+                        <description>If 1, feed the opposite lane&#39;s result into this lane&#39;s accumulator on POP.</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CROSS_INPUT</name>
+                        <description>If 1, feed the opposite lane&#39;s accumulator into this lane&#39;s shift + mask hardware. 
+                            Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass)</description>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SIGNED</name>
+                        <description>If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits 
+                            before adding to BASE1, and LANE1 PEEK/POP appear extended to 32 bits when read by processor.</description>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>MASK_MSB</name>
+                        <description>The most-significant bit allowed to pass by the mask (inclusive) 
+                            Setting MSB &lt; LSB may cause chip to turn inside-out</description>
+                        <bitRange>[14:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>MASK_LSB</name>
+                        <description>The least-significant bit allowed to pass by the mask (inclusive)</description>
+                        <bitRange>[9:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SHIFT</name>
+                        <description>Right-rotate applied to accumulator before masking. By appropriately configuring the masks, left and right shifts can be synthesised.</description>
+                        <bitRange>[4:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INTERP1_ACCUM0_ADD</name>
+                <addressOffset>0x000000f4</addressOffset>
+                <description>Values written here are atomically added to ACCUM0 
+                    Reading yields lane 0&#39;s raw shift and mask value (BASE0 not added).</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>INTERP1_ACCUM0_ADD</name>
+                        <bitRange>[23:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INTERP1_ACCUM1_ADD</name>
+                <addressOffset>0x000000f8</addressOffset>
+                <description>Values written here are atomically added to ACCUM1 
+                    Reading yields lane 1&#39;s raw shift and mask value (BASE1 not added).</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>INTERP1_ACCUM1_ADD</name>
+                        <bitRange>[23:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INTERP1_BASE_1AND0</name>
+                <addressOffset>0x000000fc</addressOffset>
+                <description>On write, the lower 16 bits go to BASE0, upper bits to BASE1 simultaneously. 
+                    Each half is sign-extended to 32 bits if that lane&#39;s SIGNED flag is set.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>INTERP1_BASE_1AND0</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SPINLOCK0</name>
+                <addressOffset>0x00000100</addressOffset>
+                <description>Reading from a spinlock address will: 
+                    - Return 0 if lock is already locked 
+                    - Otherwise return nonzero, and simultaneously claim the lock
+
+                    Writing (any value) releases the lock. 
+                    If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. 
+                    The value returned on success is 0x1 &lt;&lt; lock number.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>SPINLOCK0</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                        <readAction>modify</readAction>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SPINLOCK1</name>
+                <addressOffset>0x00000104</addressOffset>
+                <description>Reading from a spinlock address will: 
+                    - Return 0 if lock is already locked 
+                    - Otherwise return nonzero, and simultaneously claim the lock
+
+                    Writing (any value) releases the lock. 
+                    If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. 
+                    The value returned on success is 0x1 &lt;&lt; lock number.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>SPINLOCK1</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                        <readAction>modify</readAction>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SPINLOCK2</name>
+                <addressOffset>0x00000108</addressOffset>
+                <description>Reading from a spinlock address will: 
+                    - Return 0 if lock is already locked 
+                    - Otherwise return nonzero, and simultaneously claim the lock
+
+                    Writing (any value) releases the lock. 
+                    If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. 
+                    The value returned on success is 0x1 &lt;&lt; lock number.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>SPINLOCK2</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                        <readAction>modify</readAction>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SPINLOCK3</name>
+                <addressOffset>0x0000010c</addressOffset>
+                <description>Reading from a spinlock address will: 
+                    - Return 0 if lock is already locked 
+                    - Otherwise return nonzero, and simultaneously claim the lock
+
+                    Writing (any value) releases the lock. 
+                    If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. 
+                    The value returned on success is 0x1 &lt;&lt; lock number.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>SPINLOCK3</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                        <readAction>modify</readAction>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SPINLOCK4</name>
+                <addressOffset>0x00000110</addressOffset>
+                <description>Reading from a spinlock address will: 
+                    - Return 0 if lock is already locked 
+                    - Otherwise return nonzero, and simultaneously claim the lock
+
+                    Writing (any value) releases the lock. 
+                    If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. 
+                    The value returned on success is 0x1 &lt;&lt; lock number.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>SPINLOCK4</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                        <readAction>modify</readAction>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SPINLOCK5</name>
+                <addressOffset>0x00000114</addressOffset>
+                <description>Reading from a spinlock address will: 
+                    - Return 0 if lock is already locked 
+                    - Otherwise return nonzero, and simultaneously claim the lock
+
+                    Writing (any value) releases the lock. 
+                    If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. 
+                    The value returned on success is 0x1 &lt;&lt; lock number.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>SPINLOCK5</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                        <readAction>modify</readAction>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SPINLOCK6</name>
+                <addressOffset>0x00000118</addressOffset>
+                <description>Reading from a spinlock address will: 
+                    - Return 0 if lock is already locked 
+                    - Otherwise return nonzero, and simultaneously claim the lock
+
+                    Writing (any value) releases the lock. 
+                    If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. 
+                    The value returned on success is 0x1 &lt;&lt; lock number.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>SPINLOCK6</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                        <readAction>modify</readAction>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SPINLOCK7</name>
+                <addressOffset>0x0000011c</addressOffset>
+                <description>Reading from a spinlock address will: 
+                    - Return 0 if lock is already locked 
+                    - Otherwise return nonzero, and simultaneously claim the lock
+
+                    Writing (any value) releases the lock. 
+                    If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. 
+                    The value returned on success is 0x1 &lt;&lt; lock number.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>SPINLOCK7</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                        <readAction>modify</readAction>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SPINLOCK8</name>
+                <addressOffset>0x00000120</addressOffset>
+                <description>Reading from a spinlock address will: 
+                    - Return 0 if lock is already locked 
+                    - Otherwise return nonzero, and simultaneously claim the lock
+
+                    Writing (any value) releases the lock. 
+                    If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. 
+                    The value returned on success is 0x1 &lt;&lt; lock number.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>SPINLOCK8</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                        <readAction>modify</readAction>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SPINLOCK9</name>
+                <addressOffset>0x00000124</addressOffset>
+                <description>Reading from a spinlock address will: 
+                    - Return 0 if lock is already locked 
+                    - Otherwise return nonzero, and simultaneously claim the lock
+
+                    Writing (any value) releases the lock. 
+                    If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. 
+                    The value returned on success is 0x1 &lt;&lt; lock number.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>SPINLOCK9</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                        <readAction>modify</readAction>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SPINLOCK10</name>
+                <addressOffset>0x00000128</addressOffset>
+                <description>Reading from a spinlock address will: 
+                    - Return 0 if lock is already locked 
+                    - Otherwise return nonzero, and simultaneously claim the lock
+
+                    Writing (any value) releases the lock. 
+                    If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. 
+                    The value returned on success is 0x1 &lt;&lt; lock number.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>SPINLOCK10</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                        <readAction>modify</readAction>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SPINLOCK11</name>
+                <addressOffset>0x0000012c</addressOffset>
+                <description>Reading from a spinlock address will: 
+                    - Return 0 if lock is already locked 
+                    - Otherwise return nonzero, and simultaneously claim the lock
+
+                    Writing (any value) releases the lock. 
+                    If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. 
+                    The value returned on success is 0x1 &lt;&lt; lock number.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>SPINLOCK11</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                        <readAction>modify</readAction>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SPINLOCK12</name>
+                <addressOffset>0x00000130</addressOffset>
+                <description>Reading from a spinlock address will: 
+                    - Return 0 if lock is already locked 
+                    - Otherwise return nonzero, and simultaneously claim the lock
+
+                    Writing (any value) releases the lock. 
+                    If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. 
+                    The value returned on success is 0x1 &lt;&lt; lock number.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>SPINLOCK12</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                        <readAction>modify</readAction>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SPINLOCK13</name>
+                <addressOffset>0x00000134</addressOffset>
+                <description>Reading from a spinlock address will: 
+                    - Return 0 if lock is already locked 
+                    - Otherwise return nonzero, and simultaneously claim the lock
+
+                    Writing (any value) releases the lock. 
+                    If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. 
+                    The value returned on success is 0x1 &lt;&lt; lock number.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>SPINLOCK13</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                        <readAction>modify</readAction>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SPINLOCK14</name>
+                <addressOffset>0x00000138</addressOffset>
+                <description>Reading from a spinlock address will: 
+                    - Return 0 if lock is already locked 
+                    - Otherwise return nonzero, and simultaneously claim the lock
+
+                    Writing (any value) releases the lock. 
+                    If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. 
+                    The value returned on success is 0x1 &lt;&lt; lock number.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>SPINLOCK14</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                        <readAction>modify</readAction>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SPINLOCK15</name>
+                <addressOffset>0x0000013c</addressOffset>
+                <description>Reading from a spinlock address will: 
+                    - Return 0 if lock is already locked 
+                    - Otherwise return nonzero, and simultaneously claim the lock
+
+                    Writing (any value) releases the lock. 
+                    If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. 
+                    The value returned on success is 0x1 &lt;&lt; lock number.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>SPINLOCK15</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                        <readAction>modify</readAction>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SPINLOCK16</name>
+                <addressOffset>0x00000140</addressOffset>
+                <description>Reading from a spinlock address will: 
+                    - Return 0 if lock is already locked 
+                    - Otherwise return nonzero, and simultaneously claim the lock
+
+                    Writing (any value) releases the lock. 
+                    If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. 
+                    The value returned on success is 0x1 &lt;&lt; lock number.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>SPINLOCK16</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                        <readAction>modify</readAction>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SPINLOCK17</name>
+                <addressOffset>0x00000144</addressOffset>
+                <description>Reading from a spinlock address will: 
+                    - Return 0 if lock is already locked 
+                    - Otherwise return nonzero, and simultaneously claim the lock
+
+                    Writing (any value) releases the lock. 
+                    If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. 
+                    The value returned on success is 0x1 &lt;&lt; lock number.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>SPINLOCK17</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                        <readAction>modify</readAction>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SPINLOCK18</name>
+                <addressOffset>0x00000148</addressOffset>
+                <description>Reading from a spinlock address will: 
+                    - Return 0 if lock is already locked 
+                    - Otherwise return nonzero, and simultaneously claim the lock
+
+                    Writing (any value) releases the lock. 
+                    If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. 
+                    The value returned on success is 0x1 &lt;&lt; lock number.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>SPINLOCK18</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                        <readAction>modify</readAction>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SPINLOCK19</name>
+                <addressOffset>0x0000014c</addressOffset>
+                <description>Reading from a spinlock address will: 
+                    - Return 0 if lock is already locked 
+                    - Otherwise return nonzero, and simultaneously claim the lock
+
+                    Writing (any value) releases the lock. 
+                    If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. 
+                    The value returned on success is 0x1 &lt;&lt; lock number.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>SPINLOCK19</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                        <readAction>modify</readAction>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SPINLOCK20</name>
+                <addressOffset>0x00000150</addressOffset>
+                <description>Reading from a spinlock address will: 
+                    - Return 0 if lock is already locked 
+                    - Otherwise return nonzero, and simultaneously claim the lock
+
+                    Writing (any value) releases the lock. 
+                    If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. 
+                    The value returned on success is 0x1 &lt;&lt; lock number.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>SPINLOCK20</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                        <readAction>modify</readAction>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SPINLOCK21</name>
+                <addressOffset>0x00000154</addressOffset>
+                <description>Reading from a spinlock address will: 
+                    - Return 0 if lock is already locked 
+                    - Otherwise return nonzero, and simultaneously claim the lock
+
+                    Writing (any value) releases the lock. 
+                    If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. 
+                    The value returned on success is 0x1 &lt;&lt; lock number.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>SPINLOCK21</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                        <readAction>modify</readAction>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SPINLOCK22</name>
+                <addressOffset>0x00000158</addressOffset>
+                <description>Reading from a spinlock address will: 
+                    - Return 0 if lock is already locked 
+                    - Otherwise return nonzero, and simultaneously claim the lock
+
+                    Writing (any value) releases the lock. 
+                    If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. 
+                    The value returned on success is 0x1 &lt;&lt; lock number.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>SPINLOCK22</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                        <readAction>modify</readAction>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SPINLOCK23</name>
+                <addressOffset>0x0000015c</addressOffset>
+                <description>Reading from a spinlock address will: 
+                    - Return 0 if lock is already locked 
+                    - Otherwise return nonzero, and simultaneously claim the lock
+
+                    Writing (any value) releases the lock. 
+                    If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. 
+                    The value returned on success is 0x1 &lt;&lt; lock number.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>SPINLOCK23</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                        <readAction>modify</readAction>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SPINLOCK24</name>
+                <addressOffset>0x00000160</addressOffset>
+                <description>Reading from a spinlock address will: 
+                    - Return 0 if lock is already locked 
+                    - Otherwise return nonzero, and simultaneously claim the lock
+
+                    Writing (any value) releases the lock. 
+                    If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. 
+                    The value returned on success is 0x1 &lt;&lt; lock number.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>SPINLOCK24</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                        <readAction>modify</readAction>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SPINLOCK25</name>
+                <addressOffset>0x00000164</addressOffset>
+                <description>Reading from a spinlock address will: 
+                    - Return 0 if lock is already locked 
+                    - Otherwise return nonzero, and simultaneously claim the lock
+
+                    Writing (any value) releases the lock. 
+                    If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. 
+                    The value returned on success is 0x1 &lt;&lt; lock number.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>SPINLOCK25</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                        <readAction>modify</readAction>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SPINLOCK26</name>
+                <addressOffset>0x00000168</addressOffset>
+                <description>Reading from a spinlock address will: 
+                    - Return 0 if lock is already locked 
+                    - Otherwise return nonzero, and simultaneously claim the lock
+
+                    Writing (any value) releases the lock. 
+                    If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. 
+                    The value returned on success is 0x1 &lt;&lt; lock number.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>SPINLOCK26</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                        <readAction>modify</readAction>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SPINLOCK27</name>
+                <addressOffset>0x0000016c</addressOffset>
+                <description>Reading from a spinlock address will: 
+                    - Return 0 if lock is already locked 
+                    - Otherwise return nonzero, and simultaneously claim the lock
+
+                    Writing (any value) releases the lock. 
+                    If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. 
+                    The value returned on success is 0x1 &lt;&lt; lock number.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>SPINLOCK27</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                        <readAction>modify</readAction>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SPINLOCK28</name>
+                <addressOffset>0x00000170</addressOffset>
+                <description>Reading from a spinlock address will: 
+                    - Return 0 if lock is already locked 
+                    - Otherwise return nonzero, and simultaneously claim the lock
+
+                    Writing (any value) releases the lock. 
+                    If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. 
+                    The value returned on success is 0x1 &lt;&lt; lock number.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>SPINLOCK28</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                        <readAction>modify</readAction>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SPINLOCK29</name>
+                <addressOffset>0x00000174</addressOffset>
+                <description>Reading from a spinlock address will: 
+                    - Return 0 if lock is already locked 
+                    - Otherwise return nonzero, and simultaneously claim the lock
+
+                    Writing (any value) releases the lock. 
+                    If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. 
+                    The value returned on success is 0x1 &lt;&lt; lock number.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>SPINLOCK29</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                        <readAction>modify</readAction>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SPINLOCK30</name>
+                <addressOffset>0x00000178</addressOffset>
+                <description>Reading from a spinlock address will: 
+                    - Return 0 if lock is already locked 
+                    - Otherwise return nonzero, and simultaneously claim the lock
+
+                    Writing (any value) releases the lock. 
+                    If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. 
+                    The value returned on success is 0x1 &lt;&lt; lock number.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>SPINLOCK30</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                        <readAction>modify</readAction>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SPINLOCK31</name>
+                <addressOffset>0x0000017c</addressOffset>
+                <description>Reading from a spinlock address will: 
+                    - Return 0 if lock is already locked 
+                    - Otherwise return nonzero, and simultaneously claim the lock
+
+                    Writing (any value) releases the lock. 
+                    If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. 
+                    The value returned on success is 0x1 &lt;&lt; lock number.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>SPINLOCK31</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                        <readAction>modify</readAction>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>DOORBELL_OUT_SET</name>
+                <addressOffset>0x00000180</addressOffset>
+                <description>Trigger a doorbell interrupt on the opposite core.
+
+                    Write 1 to a bit to set the corresponding bit in DOORBELL_IN on the opposite core. This raises the opposite core&#39;s doorbell interrupt.
+
+                    Read to get the status of the doorbells currently asserted on the opposite core. This is equivalent to that core reading its own DOORBELL_IN status.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>DOORBELL_OUT_SET</name>
+                        <bitRange>[7:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>DOORBELL_OUT_CLR</name>
+                <addressOffset>0x00000184</addressOffset>
+                <description>Clear doorbells which have been posted to the opposite core. This register is intended for debugging and initialisation purposes.
+
+                    Writing 1 to a bit in DOORBELL_OUT_CLR clears the corresponding bit in DOORBELL_IN on the opposite core. Clearing all bits will cause that core&#39;s doorbell interrupt to deassert. Since the usual order of events is for software to send events using DOORBELL_OUT_SET, and acknowledge incoming events by writing to DOORBELL_IN_CLR, this register should be used with caution to avoid race conditions.
+
+                    Reading returns the status of the doorbells currently asserted on the other core, i.e. is equivalent to that core reading its own DOORBELL_IN status.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>DOORBELL_OUT_CLR</name>
+                        <bitRange>[7:0]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>DOORBELL_IN_SET</name>
+                <addressOffset>0x00000188</addressOffset>
+                <description>Write 1s to trigger doorbell interrupts on this core. Read to get status of doorbells currently asserted on this core.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>DOORBELL_IN_SET</name>
+                        <bitRange>[7:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>DOORBELL_IN_CLR</name>
+                <addressOffset>0x0000018c</addressOffset>
+                <description>Check and acknowledge doorbells posted to this core. This core&#39;s doorbell interrupt is asserted when any bit in this register is 1.
+
+                    Write 1 to each bit to clear that bit. The doorbell interrupt deasserts once all bits are cleared. Read to get status of doorbells currently asserted on this core.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>DOORBELL_IN_CLR</name>
+                        <bitRange>[7:0]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PERI_NONSEC</name>
+                <addressOffset>0x00000190</addressOffset>
+                <description>Detach certain core-local peripherals from Secure SIO, and attach them to Non-secure SIO, so that Non-secure software can use them. Attempting to access one of these peripherals from the Secure SIO when it is attached to the Non-secure SIO, or vice versa, will generate a bus error.
+
+                    This register is per-core, and is only present on the Secure SIO.
+
+                    Most SIO hardware is duplicated across the Secure and Non-secure SIO, so is not listed in this register.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>TMDS</name>
+                        <description>IF 1, detach TMDS encoder (of this core) from the Secure SIO, and attach to the Non-secure SIO.</description>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTERP1</name>
+                        <description>If 1, detach interpolator 1 (of this core) from the Secure SIO, and attach to the Non-secure SIO.</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTERP0</name>
+                        <description>If 1, detach interpolator 0 (of this core) from the Secure SIO, and attach to the Non-secure SIO.</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>RISCV_SOFTIRQ</name>
+                <addressOffset>0x000001a0</addressOffset>
+                <description>Control the assertion of the standard software interrupt (MIP.MSIP) on the RISC-V cores.
+
+                    Unlike the RISC-V timer, this interrupt is not routed to a normal system-level interrupt line, so can not be used by the Arm cores.
+
+                    It is safe for both cores to write to this register on the same cycle. The set/clear effect is accumulated across both cores, and then applied. If a flag is both set and cleared on the same cycle, only the set takes effect.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CORE1_CLR</name>
+                        <description>Write 1 to atomically clear the core 1 software interrupt flag. Read to get the status of this flag.</description>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CORE0_CLR</name>
+                        <description>Write 1 to atomically clear the core 0 software interrupt flag. Read to get the status of this flag.</description>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CORE1_SET</name>
+                        <description>Write 1 to atomically set the core 1 software interrupt flag. Read to get the status of this flag.</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CORE0_SET</name>
+                        <description>Write 1 to atomically set the core 0 software interrupt flag. Read to get the status of this flag.</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>MTIME_CTRL</name>
+                <addressOffset>0x000001a4</addressOffset>
+                <description>Control register for the RISC-V 64-bit Machine-mode timer. This timer is only present in the Secure SIO, so is only accessible to an Arm core in Secure mode or a RISC-V core in Machine mode.
+
+                    Note whilst this timer follows the RISC-V privileged specification, it is equally usable by the Arm cores. The interrupts are routed to normal system-level interrupt lines as well as to the MIP.MTIP inputs on the RISC-V cores.</description>
+                <resetValue>0x0000000d</resetValue>
+                <fields>
+                    <field>
+                        <name>DBGPAUSE_CORE1</name>
+                        <description>If 1, the timer pauses when core 1 is in the debug halt state.</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DBGPAUSE_CORE0</name>
+                        <description>If 1, the timer pauses when core 0 is in the debug halt state.</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>FULLSPEED</name>
+                        <description>If 1, increment the timer every cycle (i.e. run directly from the system clock), rather than incrementing on the system-level timer tick input.</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>EN</name>
+                        <description>Timer enable bit. When 0, the timer will not increment automatically.</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>MTIME</name>
+                <addressOffset>0x000001b0</addressOffset>
+                <description>Read/write access to the high half of RISC-V Machine-mode timer. This register is shared between both cores. If both cores write on the same cycle, core 1 takes precedence.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>MTIME</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>MTIMEH</name>
+                <addressOffset>0x000001b4</addressOffset>
+                <description>Read/write access to the high half of RISC-V Machine-mode timer. This register is shared between both cores. If both cores write on the same cycle, core 1 takes precedence.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>MTIMEH</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>MTIMECMP</name>
+                <addressOffset>0x000001b8</addressOffset>
+                <description>Low half of RISC-V Machine-mode timer comparator. This register is core-local, i.e., each core gets a copy of this register, with the comparison result routed to its own interrupt line.
+
+                    The timer interrupt is asserted whenever MTIME is greater than or equal to MTIMECMP. This comparison is unsigned, and performed on the full 64-bit values.</description>
+                <resetValue>0xffffffff</resetValue>
+                <fields>
+                    <field>
+                        <name>MTIMECMP</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>MTIMECMPH</name>
+                <addressOffset>0x000001bc</addressOffset>
+                <description>High half of RISC-V Machine-mode timer comparator. This register is core-local.
+
+                    The timer interrupt is asserted whenever MTIME is greater than or equal to MTIMECMP. This comparison is unsigned, and performed on the full 64-bit values.</description>
+                <resetValue>0xffffffff</resetValue>
+                <fields>
+                    <field>
+                        <name>MTIMECMPH</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>TMDS_CTRL</name>
+                <addressOffset>0x000001c0</addressOffset>
+                <description>Control register for TMDS encoder.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CLEAR_BALANCE</name>
+                        <description>Clear the running DC balance state of the TMDS encoders. This bit should be written once at the beginning of each scanline.</description>
+                        <bitRange>[28:28]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>PIX2_NOSHIFT</name>
+                        <description>When encoding two pixels&#39;s worth of symbols in one cycle (a read of a PEEK/POP_DOUBLE register), the second encoder sees a shifted version of the colour data register.
+
+                            This control disables that shift, so that both encoder layers see the same pixel data. This is used for pixel doubling.</description>
+                        <bitRange>[27:27]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PIX_SHIFT</name>
+                        <description>Shift applied to the colour data register with each read of a POP alias register.
+
+                            Reading from the POP_SINGLE register, or reading from the POP_DOUBLE register with PIX2_NOSHIFT set (for pixel doubling), shifts by the indicated amount.
+
+                            Reading from a POP_DOUBLE register when PIX2_NOSHIFT is clear will shift by double the indicated amount. (Shift by 32 means no shift.)</description>
+                        <bitRange>[26:24]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>0</name>
+                                <value>0</value>
+                                <description>Do not shift the colour data register.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>1</name>
+                                <value>1</value>
+                                <description>Shift the colour data register by 1 bit</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>2</name>
+                                <value>2</value>
+                                <description>Shift the colour data register by 2 bits</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>4</name>
+                                <value>3</value>
+                                <description>Shift the colour data register by 4 bits</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>8</name>
+                                <value>4</value>
+                                <description>Shift the colour data register by 8 bits</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>16</name>
+                                <value>5</value>
+                                <description>Shift the colour data register by 16 bits</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>INTERLEAVE</name>
+                        <description>Enable lane interleaving for reads of PEEK_SINGLE/POP_SINGLE.
+
+                            When interleaving is disabled, each of the 3 symbols appears as a contiguous 10-bit field, with lane 0 being the least-significant and starting at bit 0 of the register.
+
+                            When interleaving is enabled, the symbols are packed into 5 chunks of 3 lanes times 2 bits (30 bits total). Each chunk contains two bits of a TMDS symbol per lane, with lane 0 being the least significant.</description>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>L2_NBITS</name>
+                        <description>Number of valid colour MSBs for lane 2 (1-8 bits, encoded as 0 through 7). Remaining LSBs are masked to 0 after the rotate.</description>
+                        <bitRange>[20:18]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>L1_NBITS</name>
+                        <description>Number of valid colour MSBs for lane 1 (1-8 bits, encoded as 0 through 7). Remaining LSBs are masked to 0 after the rotate.</description>
+                        <bitRange>[17:15]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>L0_NBITS</name>
+                        <description>Number of valid colour MSBs for lane 0 (1-8 bits, encoded as 0 through 7). Remaining LSBs are masked to 0 after the rotate.</description>
+                        <bitRange>[14:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>L2_ROT</name>
+                        <description>Right-rotate the 16 LSBs of the colour accumulator by 0-15 bits, in order to get the MSB of the lane 2 (red) colour data aligned with the MSB of the 8-bit encoder input.
+
+                            For example, for RGB565 (red most significant), red is bits 15:11, so should be right-rotated by 8 bits to align with bits 7:3 of the encoder input.</description>
+                        <bitRange>[11:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>L1_ROT</name>
+                        <description>Right-rotate the 16 LSBs of the colour accumulator by 0-15 bits, in order to get the MSB of the lane 1 (green) colour data aligned with the MSB of the 8-bit encoder input.
+
+                            For example, for RGB565, green is bits 10:5, so should be right-rotated by 3 bits to align with bits 7:2 of the encoder input.</description>
+                        <bitRange>[7:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>L0_ROT</name>
+                        <description>Right-rotate the 16 LSBs of the colour accumulator by 0-15 bits, in order to get the MSB of the lane 0 (blue) colour data aligned with the MSB of the 8-bit encoder input.
+
+                            For example, for RGB565 (red most significant), blue is bits 4:0, so should be right-rotated by 13 to align with bits 7:3 of the encoder input.</description>
+                        <bitRange>[3:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>TMDS_WDATA</name>
+                <addressOffset>0x000001c4</addressOffset>
+                <description>Write-only access to the TMDS colour data register.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>TMDS_WDATA</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>TMDS_PEEK_SINGLE</name>
+                <addressOffset>0x000001c8</addressOffset>
+                <description>Get the encoding of one pixel&#39;s worth of colour data, packed into a 32-bit value (3x10-bit symbols).
+
+                    The PEEK alias does not shift the colour register when read, but still advances the running DC balance state of each encoder. This is useful for pixel doubling.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>TMDS_PEEK_SINGLE</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-only</access>
+                        <readAction>modify</readAction>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>TMDS_POP_SINGLE</name>
+                <addressOffset>0x000001cc</addressOffset>
+                <description>Get the encoding of one pixel&#39;s worth of colour data, packed into a 32-bit value. The packing is 5 chunks of 3 lanes times 2 bits (30 bits total). Each chunk contains two bits of a TMDS symbol per lane. This format is intended for shifting out with the HSTX peripheral on RP2350.
+
+                    The POP alias shifts the colour register when read, as well as advancing the running DC balance state of each encoder.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>TMDS_POP_SINGLE</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-only</access>
+                        <readAction>modify</readAction>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>TMDS_PEEK_DOUBLE_L0</name>
+                <addressOffset>0x000001d0</addressOffset>
+                <description>Get lane 0 of the encoding of two pixels&#39; worth of colour data. Two 10-bit TMDS symbols are packed at the bottom of a 32-bit word.
+
+                    The PEEK alias does not shift the colour register when read, but still advances the lane 0 DC balance state. This is useful if all 3 lanes&#39; worth of encode are to be read at once, rather than processing the entire scanline for one lane before moving to the next lane.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>TMDS_PEEK_DOUBLE_L0</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-only</access>
+                        <readAction>modify</readAction>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>TMDS_POP_DOUBLE_L0</name>
+                <addressOffset>0x000001d4</addressOffset>
+                <description>Get lane 0 of the encoding of two pixels&#39; worth of colour data. Two 10-bit TMDS symbols are packed at the bottom of a 32-bit word.
+
+                    The POP alias shifts the colour register when read, according to the values of PIX_SHIFT and PIX2_NOSHIFT.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>TMDS_POP_DOUBLE_L0</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-only</access>
+                        <readAction>modify</readAction>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>TMDS_PEEK_DOUBLE_L1</name>
+                <addressOffset>0x000001d8</addressOffset>
+                <description>Get lane 1 of the encoding of two pixels&#39; worth of colour data. Two 10-bit TMDS symbols are packed at the bottom of a 32-bit word.
+
+                    The PEEK alias does not shift the colour register when read, but still advances the lane 1 DC balance state. This is useful if all 3 lanes&#39; worth of encode are to be read at once, rather than processing the entire scanline for one lane before moving to the next lane.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>TMDS_PEEK_DOUBLE_L1</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-only</access>
+                        <readAction>modify</readAction>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>TMDS_POP_DOUBLE_L1</name>
+                <addressOffset>0x000001dc</addressOffset>
+                <description>Get lane 1 of the encoding of two pixels&#39; worth of colour data. Two 10-bit TMDS symbols are packed at the bottom of a 32-bit word.
+
+                    The POP alias shifts the colour register when read, according to the values of PIX_SHIFT and PIX2_NOSHIFT.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>TMDS_POP_DOUBLE_L1</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-only</access>
+                        <readAction>modify</readAction>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>TMDS_PEEK_DOUBLE_L2</name>
+                <addressOffset>0x000001e0</addressOffset>
+                <description>Get lane 2 of the encoding of two pixels&#39; worth of colour data. Two 10-bit TMDS symbols are packed at the bottom of a 32-bit word.
+
+                    The PEEK alias does not shift the colour register when read, but still advances the lane 2 DC balance state. This is useful if all 3 lanes&#39; worth of encode are to be read at once, rather than processing the entire scanline for one lane before moving to the next lane.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>TMDS_PEEK_DOUBLE_L2</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-only</access>
+                        <readAction>modify</readAction>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>TMDS_POP_DOUBLE_L2</name>
+                <addressOffset>0x000001e4</addressOffset>
+                <description>Get lane 2 of the encoding of two pixels&#39; worth of colour data. Two 10-bit TMDS symbols are packed at the bottom of a 32-bit word.
+
+                    The POP alias shifts the colour register when read, according to the values of PIX_SHIFT and PIX2_NOSHIFT.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>TMDS_POP_DOUBLE_L2</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-only</access>
+                        <readAction>modify</readAction>
+                    </field>
+                </fields>
+            </register>
+        </registers>
+    </peripheral>
+    <peripheral derivedFrom="SIO">
+        <name>SIO_NS</name>
+        <baseAddress>0xd0020000</baseAddress>
+    </peripheral>
+    <peripheral>
+        <name>BOOTRAM</name>
+        <description>Additional registers mapped adjacent to the bootram, for use by the bootrom.</description>
+        <baseAddress>0x400e0000</baseAddress>
+        <addressBlock>
+            <offset>0</offset>
+            <size>2092</size>
+            <usage>registers</usage>
+        </addressBlock>
+        <registers>
+            <register>
+                <name>WRITE_ONCE0</name>
+                <addressOffset>0x00000800</addressOffset>
+                <description>This registers always ORs writes into its current contents. Once a bit is set, it can only be cleared by a reset.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>WRITE_ONCE0</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>WRITE_ONCE1</name>
+                <addressOffset>0x00000804</addressOffset>
+                <description>This registers always ORs writes into its current contents. Once a bit is set, it can only be cleared by a reset.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>WRITE_ONCE1</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>BOOTLOCK_STAT</name>
+                <addressOffset>0x00000808</addressOffset>
+                <description>Bootlock status register. 1=unclaimed, 0=claimed. These locks function identically to the SIO spinlocks, but are reserved for bootrom use.</description>
+                <resetValue>0x000000ff</resetValue>
+                <fields>
+                    <field>
+                        <name>BOOTLOCK_STAT</name>
+                        <bitRange>[7:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>BOOTLOCK0</name>
+                <addressOffset>0x0000080c</addressOffset>
+                <description>Read to claim and check. Write to unclaim. The value returned on successful claim is 1 &lt;&lt; n, and on failed claim is zero.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>BOOTLOCK0</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>BOOTLOCK1</name>
+                <addressOffset>0x00000810</addressOffset>
+                <description>Read to claim and check. Write to unclaim. The value returned on successful claim is 1 &lt;&lt; n, and on failed claim is zero.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>BOOTLOCK1</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>BOOTLOCK2</name>
+                <addressOffset>0x00000814</addressOffset>
+                <description>Read to claim and check. Write to unclaim. The value returned on successful claim is 1 &lt;&lt; n, and on failed claim is zero.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>BOOTLOCK2</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>BOOTLOCK3</name>
+                <addressOffset>0x00000818</addressOffset>
+                <description>Read to claim and check. Write to unclaim. The value returned on successful claim is 1 &lt;&lt; n, and on failed claim is zero.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>BOOTLOCK3</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>BOOTLOCK4</name>
+                <addressOffset>0x0000081c</addressOffset>
+                <description>Read to claim and check. Write to unclaim. The value returned on successful claim is 1 &lt;&lt; n, and on failed claim is zero.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>BOOTLOCK4</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>BOOTLOCK5</name>
+                <addressOffset>0x00000820</addressOffset>
+                <description>Read to claim and check. Write to unclaim. The value returned on successful claim is 1 &lt;&lt; n, and on failed claim is zero.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>BOOTLOCK5</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>BOOTLOCK6</name>
+                <addressOffset>0x00000824</addressOffset>
+                <description>Read to claim and check. Write to unclaim. The value returned on successful claim is 1 &lt;&lt; n, and on failed claim is zero.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>BOOTLOCK6</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>BOOTLOCK7</name>
+                <addressOffset>0x00000828</addressOffset>
+                <description>Read to claim and check. Write to unclaim. The value returned on successful claim is 1 &lt;&lt; n, and on failed claim is zero.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>BOOTLOCK7</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+        </registers>
+    </peripheral>
+    <peripheral>
+        <name>CORESIGHT_TRACE</name>
+        <description>Coresight block - RP specific registers</description>
+        <baseAddress>0x50700000</baseAddress>
+        <addressBlock>
+            <offset>0</offset>
+            <size>8</size>
+            <usage>registers</usage>
+        </addressBlock>
+        <registers>
+            <register>
+                <name>CTRL_STATUS</name>
+                <addressOffset>0x00000000</addressOffset>
+                <description>Control and status register</description>
+                <resetValue>0x00000001</resetValue>
+                <fields>
+                    <field>
+                        <name>TRACE_CAPTURE_FIFO_OVERFLOW</name>
+                        <description>This status flag is set high when trace data has been dropped due to the FIFO being full at the point trace data was sampled. Write 1 to acknowledge and clear the bit.</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>TRACE_CAPTURE_FIFO_FLUSH</name>
+                        <description>Set to 1 to continuously hold the trace FIFO in a flushed state and prevent overflow.
+
+                            Before clearing this flag, configure and start a DMA channel with the correct DREQ for the TRACE_CAPTURE_FIFO register.
+
+                            Clear this flag to begin sampling trace data, and set once again once the trace capture buffer is full. You must configure the TPIU in order to generate trace packets to be captured, as well as components like the ETM further upstream to generate the event stream propagated to the TPIU.</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>TRACE_CAPTURE_FIFO</name>
+                <addressOffset>0x00000004</addressOffset>
+                <description>FIFO for trace data captured from the TPIU</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>RDATA</name>
+                        <description>Read from an 8 x 32-bit FIFO containing trace data captured from the TPIU.
+
+                            Hardware pushes to the FIFO on rising edges of clk_sys, when either of the following is true:
+
+                            * TPIU TRACECTL output is low (normal trace data)
+
+                            * TPIU TRACETCL output is high, and TPIU TRACEDATA0 and TRACEDATA1 are both low (trigger packet)
+
+                            These conditions are in accordance with Arm Coresight Architecture Spec v3.0 section D3.3.3: Decoding requirements for Trace Capture Devices
+
+                            The data captured into the FIFO is the full 32-bit TRACEDATA bus output by the TPIU. Note that the TPIU is a DDR output at half of clk_sys, therefore this interface can capture the full 32-bit TPIU DDR output bandwidth as it samples once per active edge of the TPIU output clock.</description>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-only</access>
+                        <readAction>modify</readAction>
+                    </field>
+                </fields>
+            </register>
+        </registers>
+    </peripheral>
+    <peripheral>
+        <name>USB</name>
+        <description>USB FS/LS controller device registers</description>
+        <baseAddress>0x50110000</baseAddress>
+        <addressBlock>
+            <offset>0</offset>
+            <size>280</size>
+            <usage>registers</usage>
+        </addressBlock>
+        <interrupt>
+            <name>USBCTRL_IRQ</name>
+            <value>14</value>
+        </interrupt>
+        <registers>
+            <register>
+                <name>ADDR_ENDP</name>
+                <addressOffset>0x00000000</addressOffset>
+                <description>Device address and endpoint control</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>ENDPOINT</name>
+                        <description>Device endpoint to send data to. Only valid for HOST mode.</description>
+                        <bitRange>[19:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ADDRESS</name>
+                        <description>In device mode, the address that the device should respond to. Set in response to a SET_ADDR setup packet from the host. In host mode set to the address of the device to communicate with.</description>
+                        <bitRange>[6:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>ADDR_ENDP1</name>
+                <addressOffset>0x00000004</addressOffset>
+                <description>Interrupt endpoint 1. Only valid for HOST mode.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>INTEP_PREAMBLE</name>
+                        <description>Interrupt EP requires preamble (is a low speed device on a full speed hub)</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTEP_DIR</name>
+                        <description>Direction of the interrupt endpoint. In=0, Out=1</description>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ENDPOINT</name>
+                        <description>Endpoint number of the interrupt endpoint</description>
+                        <bitRange>[19:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ADDRESS</name>
+                        <description>Device address</description>
+                        <bitRange>[6:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>ADDR_ENDP2</name>
+                <addressOffset>0x00000008</addressOffset>
+                <description>Interrupt endpoint 2. Only valid for HOST mode.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>INTEP_PREAMBLE</name>
+                        <description>Interrupt EP requires preamble (is a low speed device on a full speed hub)</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTEP_DIR</name>
+                        <description>Direction of the interrupt endpoint. In=0, Out=1</description>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ENDPOINT</name>
+                        <description>Endpoint number of the interrupt endpoint</description>
+                        <bitRange>[19:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ADDRESS</name>
+                        <description>Device address</description>
+                        <bitRange>[6:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>ADDR_ENDP3</name>
+                <addressOffset>0x0000000c</addressOffset>
+                <description>Interrupt endpoint 3. Only valid for HOST mode.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>INTEP_PREAMBLE</name>
+                        <description>Interrupt EP requires preamble (is a low speed device on a full speed hub)</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTEP_DIR</name>
+                        <description>Direction of the interrupt endpoint. In=0, Out=1</description>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ENDPOINT</name>
+                        <description>Endpoint number of the interrupt endpoint</description>
+                        <bitRange>[19:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ADDRESS</name>
+                        <description>Device address</description>
+                        <bitRange>[6:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>ADDR_ENDP4</name>
+                <addressOffset>0x00000010</addressOffset>
+                <description>Interrupt endpoint 4. Only valid for HOST mode.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>INTEP_PREAMBLE</name>
+                        <description>Interrupt EP requires preamble (is a low speed device on a full speed hub)</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTEP_DIR</name>
+                        <description>Direction of the interrupt endpoint. In=0, Out=1</description>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ENDPOINT</name>
+                        <description>Endpoint number of the interrupt endpoint</description>
+                        <bitRange>[19:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ADDRESS</name>
+                        <description>Device address</description>
+                        <bitRange>[6:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>ADDR_ENDP5</name>
+                <addressOffset>0x00000014</addressOffset>
+                <description>Interrupt endpoint 5. Only valid for HOST mode.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>INTEP_PREAMBLE</name>
+                        <description>Interrupt EP requires preamble (is a low speed device on a full speed hub)</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTEP_DIR</name>
+                        <description>Direction of the interrupt endpoint. In=0, Out=1</description>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ENDPOINT</name>
+                        <description>Endpoint number of the interrupt endpoint</description>
+                        <bitRange>[19:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ADDRESS</name>
+                        <description>Device address</description>
+                        <bitRange>[6:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>ADDR_ENDP6</name>
+                <addressOffset>0x00000018</addressOffset>
+                <description>Interrupt endpoint 6. Only valid for HOST mode.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>INTEP_PREAMBLE</name>
+                        <description>Interrupt EP requires preamble (is a low speed device on a full speed hub)</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTEP_DIR</name>
+                        <description>Direction of the interrupt endpoint. In=0, Out=1</description>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ENDPOINT</name>
+                        <description>Endpoint number of the interrupt endpoint</description>
+                        <bitRange>[19:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ADDRESS</name>
+                        <description>Device address</description>
+                        <bitRange>[6:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>ADDR_ENDP7</name>
+                <addressOffset>0x0000001c</addressOffset>
+                <description>Interrupt endpoint 7. Only valid for HOST mode.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>INTEP_PREAMBLE</name>
+                        <description>Interrupt EP requires preamble (is a low speed device on a full speed hub)</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTEP_DIR</name>
+                        <description>Direction of the interrupt endpoint. In=0, Out=1</description>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ENDPOINT</name>
+                        <description>Endpoint number of the interrupt endpoint</description>
+                        <bitRange>[19:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ADDRESS</name>
+                        <description>Device address</description>
+                        <bitRange>[6:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>ADDR_ENDP8</name>
+                <addressOffset>0x00000020</addressOffset>
+                <description>Interrupt endpoint 8. Only valid for HOST mode.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>INTEP_PREAMBLE</name>
+                        <description>Interrupt EP requires preamble (is a low speed device on a full speed hub)</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTEP_DIR</name>
+                        <description>Direction of the interrupt endpoint. In=0, Out=1</description>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ENDPOINT</name>
+                        <description>Endpoint number of the interrupt endpoint</description>
+                        <bitRange>[19:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ADDRESS</name>
+                        <description>Device address</description>
+                        <bitRange>[6:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>ADDR_ENDP9</name>
+                <addressOffset>0x00000024</addressOffset>
+                <description>Interrupt endpoint 9. Only valid for HOST mode.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>INTEP_PREAMBLE</name>
+                        <description>Interrupt EP requires preamble (is a low speed device on a full speed hub)</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTEP_DIR</name>
+                        <description>Direction of the interrupt endpoint. In=0, Out=1</description>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ENDPOINT</name>
+                        <description>Endpoint number of the interrupt endpoint</description>
+                        <bitRange>[19:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ADDRESS</name>
+                        <description>Device address</description>
+                        <bitRange>[6:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>ADDR_ENDP10</name>
+                <addressOffset>0x00000028</addressOffset>
+                <description>Interrupt endpoint 10. Only valid for HOST mode.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>INTEP_PREAMBLE</name>
+                        <description>Interrupt EP requires preamble (is a low speed device on a full speed hub)</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTEP_DIR</name>
+                        <description>Direction of the interrupt endpoint. In=0, Out=1</description>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ENDPOINT</name>
+                        <description>Endpoint number of the interrupt endpoint</description>
+                        <bitRange>[19:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ADDRESS</name>
+                        <description>Device address</description>
+                        <bitRange>[6:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>ADDR_ENDP11</name>
+                <addressOffset>0x0000002c</addressOffset>
+                <description>Interrupt endpoint 11. Only valid for HOST mode.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>INTEP_PREAMBLE</name>
+                        <description>Interrupt EP requires preamble (is a low speed device on a full speed hub)</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTEP_DIR</name>
+                        <description>Direction of the interrupt endpoint. In=0, Out=1</description>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ENDPOINT</name>
+                        <description>Endpoint number of the interrupt endpoint</description>
+                        <bitRange>[19:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ADDRESS</name>
+                        <description>Device address</description>
+                        <bitRange>[6:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>ADDR_ENDP12</name>
+                <addressOffset>0x00000030</addressOffset>
+                <description>Interrupt endpoint 12. Only valid for HOST mode.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>INTEP_PREAMBLE</name>
+                        <description>Interrupt EP requires preamble (is a low speed device on a full speed hub)</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTEP_DIR</name>
+                        <description>Direction of the interrupt endpoint. In=0, Out=1</description>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ENDPOINT</name>
+                        <description>Endpoint number of the interrupt endpoint</description>
+                        <bitRange>[19:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ADDRESS</name>
+                        <description>Device address</description>
+                        <bitRange>[6:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>ADDR_ENDP13</name>
+                <addressOffset>0x00000034</addressOffset>
+                <description>Interrupt endpoint 13. Only valid for HOST mode.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>INTEP_PREAMBLE</name>
+                        <description>Interrupt EP requires preamble (is a low speed device on a full speed hub)</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTEP_DIR</name>
+                        <description>Direction of the interrupt endpoint. In=0, Out=1</description>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ENDPOINT</name>
+                        <description>Endpoint number of the interrupt endpoint</description>
+                        <bitRange>[19:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ADDRESS</name>
+                        <description>Device address</description>
+                        <bitRange>[6:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>ADDR_ENDP14</name>
+                <addressOffset>0x00000038</addressOffset>
+                <description>Interrupt endpoint 14. Only valid for HOST mode.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>INTEP_PREAMBLE</name>
+                        <description>Interrupt EP requires preamble (is a low speed device on a full speed hub)</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTEP_DIR</name>
+                        <description>Direction of the interrupt endpoint. In=0, Out=1</description>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ENDPOINT</name>
+                        <description>Endpoint number of the interrupt endpoint</description>
+                        <bitRange>[19:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ADDRESS</name>
+                        <description>Device address</description>
+                        <bitRange>[6:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>ADDR_ENDP15</name>
+                <addressOffset>0x0000003c</addressOffset>
+                <description>Interrupt endpoint 15. Only valid for HOST mode.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>INTEP_PREAMBLE</name>
+                        <description>Interrupt EP requires preamble (is a low speed device on a full speed hub)</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTEP_DIR</name>
+                        <description>Direction of the interrupt endpoint. In=0, Out=1</description>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ENDPOINT</name>
+                        <description>Endpoint number of the interrupt endpoint</description>
+                        <bitRange>[19:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ADDRESS</name>
+                        <description>Device address</description>
+                        <bitRange>[6:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>MAIN_CTRL</name>
+                <addressOffset>0x00000040</addressOffset>
+                <description>Main control register</description>
+                <resetValue>0x00000004</resetValue>
+                <fields>
+                    <field>
+                        <name>SIM_TIMING</name>
+                        <description>Reduced timings for simulation</description>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PHY_ISO</name>
+                        <description>Isolates USB phy after controller power-up 
+                            Remove isolation once software has configured the controller 
+                            Not isolated = 0, Isolated = 1</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>HOST_NDEVICE</name>
+                        <description>Device mode = 0, Host mode = 1</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CONTROLLER_EN</name>
+                        <description>Enable controller</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SOF_WR</name>
+                <addressOffset>0x00000044</addressOffset>
+                <description>Set the SOF (Start of Frame) frame number in the host controller. The SOF packet is sent every 1ms and the host will increment the frame number by 1 each time.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>COUNT</name>
+                        <bitRange>[10:0]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SOF_RD</name>
+                <addressOffset>0x00000048</addressOffset>
+                <description>Read the last SOF (Start of Frame) frame number seen. In device mode the last SOF received from the host. In host mode the last SOF sent by the host.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>COUNT</name>
+                        <bitRange>[10:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SIE_CTRL</name>
+                <addressOffset>0x0000004c</addressOffset>
+                <description>SIE control register</description>
+                <resetValue>0x00008000</resetValue>
+                <fields>
+                    <field>
+                        <name>EP0_INT_STALL</name>
+                        <description>Device: Set bit in EP_STATUS_STALL_NAK when EP0 sends a STALL</description>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>EP0_DOUBLE_BUF</name>
+                        <description>Device: EP0 single buffered = 0, double buffered = 1</description>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>EP0_INT_1BUF</name>
+                        <description>Device: Set bit in BUFF_STATUS for every buffer completed on EP0</description>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>EP0_INT_2BUF</name>
+                        <description>Device: Set bit in BUFF_STATUS for every 2 buffers completed on EP0</description>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>EP0_INT_NAK</name>
+                        <description>Device: Set bit in EP_STATUS_STALL_NAK when EP0 sends a NAK</description>
+                        <bitRange>[27:27]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DIRECT_EN</name>
+                        <description>Direct bus drive enable</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DIRECT_DP</name>
+                        <description>Direct control of DP</description>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DIRECT_DM</name>
+                        <description>Direct control of DM</description>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>EP0_STOP_ON_SHORT_PACKET</name>
+                        <description>Device: Stop EP0 on a short packet.</description>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>TRANSCEIVER_PD</name>
+                        <description>Power down bus transceiver</description>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>RPU_OPT</name>
+                        <description>Device: Pull-up strength (0=1K2, 1=2k3)</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PULLUP_EN</name>
+                        <description>Device: Enable pull up resistor</description>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PULLDOWN_EN</name>
+                        <description>Host: Enable pull down resistors</description>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>RESET_BUS</name>
+                        <description>Host: Reset bus</description>
+                        <bitRange>[13:13]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>RESUME</name>
+                        <description>Device: Remote wakeup. Device can initiate its own resume after suspend.</description>
+                        <bitRange>[12:12]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>VBUS_EN</name>
+                        <description>Host: Enable VBUS</description>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>KEEP_ALIVE_EN</name>
+                        <description>Host: Enable keep alive packet (for low speed bus)</description>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SOF_EN</name>
+                        <description>Host: Enable SOF generation (for full speed bus)</description>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SOF_SYNC</name>
+                        <description>Host: Delay packet(s) until after SOF</description>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PREAMBLE_EN</name>
+                        <description>Host: Preable enable for LS device on FS hub</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>STOP_TRANS</name>
+                        <description>Host: Stop transaction</description>
+                        <bitRange>[4:4]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>RECEIVE_DATA</name>
+                        <description>Host: Receive transaction (IN to host)</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SEND_DATA</name>
+                        <description>Host: Send transaction (OUT from host)</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SEND_SETUP</name>
+                        <description>Host: Send Setup packet</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>START_TRANS</name>
+                        <description>Host: Start transaction</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SIE_STATUS</name>
+                <addressOffset>0x00000050</addressOffset>
+                <description>SIE status register</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>DATA_SEQ_ERROR</name>
+                        <description>Data Sequence Error.
+
+                            The device can raise a sequence error in the following conditions:
+
+                            * A SETUP packet is received followed by a DATA1 packet (data phase should always be DATA0) * An OUT packet is received from the host but doesn&#39;t match the data pid in the buffer control register read from DPSRAM
+
+                            The host can raise a data sequence error in the following conditions:
+
+                            * An IN packet from the device has the wrong data PID</description>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>ACK_REC</name>
+                        <description>ACK received. Raised by both host and device.</description>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>STALL_REC</name>
+                        <description>Host: STALL received</description>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>NAK_REC</name>
+                        <description>Host: NAK received</description>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>RX_TIMEOUT</name>
+                        <description>RX timeout is raised by both the host and device if an ACK is not received in the maximum time specified by the USB spec.</description>
+                        <bitRange>[27:27]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>RX_OVERFLOW</name>
+                        <description>RX overflow is raised by the Serial RX engine if the incoming data is too fast.</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>BIT_STUFF_ERROR</name>
+                        <description>Bit Stuff Error. Raised by the Serial RX engine.</description>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>CRC_ERROR</name>
+                        <description>CRC Error. Raised by the Serial RX engine.</description>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>ENDPOINT_ERROR</name>
+                        <description>An endpoint has encountered an error. Read the ep_rx_error and ep_tx_error registers to find out which endpoint had an error.</description>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>BUS_RESET</name>
+                        <description>Device: bus reset received</description>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>TRANS_COMPLETE</name>
+                        <description>Transaction complete.
+
+                            Raised by device if:
+
+                            * An IN or OUT packet is sent with the `LAST_BUFF` bit set in the buffer control register
+
+                            Raised by host if:
+
+                            * A setup packet is sent when no data in or data out transaction follows * An IN packet is received and the `LAST_BUFF` bit is set in the buffer control register * An IN packet is received with zero length * An OUT packet is sent and the `LAST_BUFF` bit is set</description>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>SETUP_REC</name>
+                        <description>Device: Setup packet received</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>CONNECTED</name>
+                        <description>Device: connected</description>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>RX_SHORT_PACKET</name>
+                        <description>Device or Host has received a short packet. This is when the data received is less than configured in the buffer control register. Device: If using double buffered mode on device the buffer select will not be toggled after writing status back to the buffer control register. This is to prevent any further transactions on that endpoint until the user has reset the buffer control registers. Host: the current transfer will be stopped early.</description>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>RESUME</name>
+                        <description>Host: Device has initiated a remote resume. Device: host has initiated a resume.</description>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>VBUS_OVER_CURR</name>
+                        <description>VBUS over current detected</description>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SPEED</name>
+                        <description>Host: device speed. Disconnected = 00, LS = 01, FS = 10</description>
+                        <bitRange>[9:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SUSPENDED</name>
+                        <description>Bus in suspended state. Valid for device. Device will go into suspend if neither Keep Alive / SOF frames are enabled.</description>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>LINE_STATE</name>
+                        <description>USB bus line state</description>
+                        <bitRange>[3:2]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>VBUS_DETECTED</name>
+                        <description>Device: VBUS Detected</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INT_EP_CTRL</name>
+                <addressOffset>0x00000054</addressOffset>
+                <description>interrupt endpoint control register</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>INT_EP_ACTIVE</name>
+                        <description>Host: Enable interrupt endpoint 1 -&gt; 15</description>
+                        <bitRange>[15:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>BUFF_STATUS</name>
+                <addressOffset>0x00000058</addressOffset>
+                <description>Buffer status register. A bit set here indicates that a buffer has completed on the endpoint (if the buffer interrupt is enabled). It is possible for 2 buffers to be completed, so clearing the buffer status bit may instantly re set it on the next clock cycle.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>EP15_OUT</name>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP15_IN</name>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP14_OUT</name>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP14_IN</name>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP13_OUT</name>
+                        <bitRange>[27:27]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP13_IN</name>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP12_OUT</name>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP12_IN</name>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP11_OUT</name>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP11_IN</name>
+                        <bitRange>[22:22]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP10_OUT</name>
+                        <bitRange>[21:21]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP10_IN</name>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP9_OUT</name>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP9_IN</name>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP8_OUT</name>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP8_IN</name>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP7_OUT</name>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP7_IN</name>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP6_OUT</name>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP6_IN</name>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP5_OUT</name>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP5_IN</name>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP4_OUT</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP4_IN</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP3_OUT</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP3_IN</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP2_OUT</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP2_IN</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP1_OUT</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP1_IN</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP0_OUT</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP0_IN</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>BUFF_CPU_SHOULD_HANDLE</name>
+                <addressOffset>0x0000005c</addressOffset>
+                <description>Which of the double buffers should be handled. Only valid if using an interrupt per buffer (i.e. not per 2 buffers). Not valid for host interrupt endpoint polling because they are only single buffered.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>EP15_OUT</name>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>EP15_IN</name>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>EP14_OUT</name>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>EP14_IN</name>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>EP13_OUT</name>
+                        <bitRange>[27:27]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>EP13_IN</name>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>EP12_OUT</name>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>EP12_IN</name>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>EP11_OUT</name>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>EP11_IN</name>
+                        <bitRange>[22:22]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>EP10_OUT</name>
+                        <bitRange>[21:21]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>EP10_IN</name>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>EP9_OUT</name>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>EP9_IN</name>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>EP8_OUT</name>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>EP8_IN</name>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>EP7_OUT</name>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>EP7_IN</name>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>EP6_OUT</name>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>EP6_IN</name>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>EP5_OUT</name>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>EP5_IN</name>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>EP4_OUT</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>EP4_IN</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>EP3_OUT</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>EP3_IN</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>EP2_OUT</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>EP2_IN</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>EP1_OUT</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>EP1_IN</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>EP0_OUT</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>EP0_IN</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>EP_ABORT</name>
+                <addressOffset>0x00000060</addressOffset>
+                <description>Device only: Can be set to ignore the buffer control register for this endpoint in case you would like to revoke a buffer. A NAK will be sent for every access to the endpoint until this bit is cleared. A corresponding bit in `EP_ABORT_DONE` is set when it is safe to modify the buffer control register.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>EP15_OUT</name>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>EP15_IN</name>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>EP14_OUT</name>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>EP14_IN</name>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>EP13_OUT</name>
+                        <bitRange>[27:27]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>EP13_IN</name>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>EP12_OUT</name>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>EP12_IN</name>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>EP11_OUT</name>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>EP11_IN</name>
+                        <bitRange>[22:22]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>EP10_OUT</name>
+                        <bitRange>[21:21]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>EP10_IN</name>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>EP9_OUT</name>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>EP9_IN</name>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>EP8_OUT</name>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>EP8_IN</name>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>EP7_OUT</name>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>EP7_IN</name>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>EP6_OUT</name>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>EP6_IN</name>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>EP5_OUT</name>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>EP5_IN</name>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>EP4_OUT</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>EP4_IN</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>EP3_OUT</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>EP3_IN</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>EP2_OUT</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>EP2_IN</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>EP1_OUT</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>EP1_IN</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>EP0_OUT</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>EP0_IN</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>EP_ABORT_DONE</name>
+                <addressOffset>0x00000064</addressOffset>
+                <description>Device only: Used in conjunction with `EP_ABORT`. Set once an endpoint is idle so the programmer knows it is safe to modify the buffer control register.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>EP15_OUT</name>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP15_IN</name>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP14_OUT</name>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP14_IN</name>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP13_OUT</name>
+                        <bitRange>[27:27]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP13_IN</name>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP12_OUT</name>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP12_IN</name>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP11_OUT</name>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP11_IN</name>
+                        <bitRange>[22:22]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP10_OUT</name>
+                        <bitRange>[21:21]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP10_IN</name>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP9_OUT</name>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP9_IN</name>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP8_OUT</name>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP8_IN</name>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP7_OUT</name>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP7_IN</name>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP6_OUT</name>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP6_IN</name>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP5_OUT</name>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP5_IN</name>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP4_OUT</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP4_IN</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP3_OUT</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP3_IN</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP2_OUT</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP2_IN</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP1_OUT</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP1_IN</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP0_OUT</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP0_IN</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>EP_STALL_ARM</name>
+                <addressOffset>0x00000068</addressOffset>
+                <description>Device: this bit must be set in conjunction with the `STALL` bit in the buffer control register to send a STALL on EP0. The device controller clears these bits when a SETUP packet is received because the USB spec requires that a STALL condition is cleared when a SETUP packet is received.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>EP0_OUT</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>EP0_IN</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>NAK_POLL</name>
+                <addressOffset>0x0000006c</addressOffset>
+                <description>Used by the host controller. Sets the wait time in microseconds before trying again if the device replies with a NAK.</description>
+                <resetValue>0x00100010</resetValue>
+                <fields>
+                    <field>
+                        <name>RETRY_COUNT_HI</name>
+                        <description>Bits 9:6 of nak_retry count</description>
+                        <bitRange>[31:28]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>EPX_STOPPED_ON_NAK</name>
+                        <description>EPX polling has stopped because a nak was received</description>
+                        <bitRange>[27:27]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>STOP_EPX_ON_NAK</name>
+                        <description>Stop polling epx when a nak is received</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DELAY_FS</name>
+                        <description>NAK polling interval for a full speed device</description>
+                        <bitRange>[25:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>RETRY_COUNT_LO</name>
+                        <description>Bits 5:0 of nak_retry_count</description>
+                        <bitRange>[15:10]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>DELAY_LS</name>
+                        <description>NAK polling interval for a low speed device</description>
+                        <bitRange>[9:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>EP_STATUS_STALL_NAK</name>
+                <addressOffset>0x00000070</addressOffset>
+                <description>Device: bits are set when the `IRQ_ON_NAK` or `IRQ_ON_STALL` bits are set. For EP0 this comes from `SIE_CTRL`. For all other endpoints it comes from the endpoint control register.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>EP15_OUT</name>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP15_IN</name>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP14_OUT</name>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP14_IN</name>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP13_OUT</name>
+                        <bitRange>[27:27]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP13_IN</name>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP12_OUT</name>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP12_IN</name>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP11_OUT</name>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP11_IN</name>
+                        <bitRange>[22:22]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP10_OUT</name>
+                        <bitRange>[21:21]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP10_IN</name>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP9_OUT</name>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP9_IN</name>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP8_OUT</name>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP8_IN</name>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP7_OUT</name>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP7_IN</name>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP6_OUT</name>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP6_IN</name>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP5_OUT</name>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP5_IN</name>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP4_OUT</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP4_IN</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP3_OUT</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP3_IN</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP2_OUT</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP2_IN</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP1_OUT</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP1_IN</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP0_OUT</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP0_IN</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>USB_MUXING</name>
+                <addressOffset>0x00000074</addressOffset>
+                <description>Where to connect the USB controller. Should be to_phy by default.</description>
+                <resetValue>0x00000001</resetValue>
+                <fields>
+                    <field>
+                        <name>SWAP_DPDM</name>
+                        <description>Swap the USB PHY DP and DM pins and all related controls and flip receive differential data. Can be used to switch USB DP/DP on the PCB. 
+                            This is done at a low level so overrides all other controls.</description>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>USBPHY_AS_GPIO</name>
+                        <description>Use the usb DP and DM pins as GPIO pins instead of connecting them to the USB controller.</description>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SOFTCON</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>TO_DIGITAL_PAD</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>TO_EXTPHY</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>TO_PHY</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>USB_PWR</name>
+                <addressOffset>0x00000078</addressOffset>
+                <description>Overrides for the power signals in the event that the VBUS signals are not hooked up to GPIO. Set the value of the override and then the override enable to switch over to the override value.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>OVERCURR_DETECT_EN</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>OVERCURR_DETECT</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>VBUS_DETECT_OVERRIDE_EN</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>VBUS_DETECT</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>VBUS_EN_OVERRIDE_EN</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>VBUS_EN</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>USBPHY_DIRECT</name>
+                <addressOffset>0x0000007c</addressOffset>
+                <description>This register allows for direct control of the USB phy. Use in conjunction with usbphy_direct_override register to enable each override bit.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>RX_DM_OVERRIDE</name>
+                        <description>Override rx_dm value into controller</description>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>RX_DP_OVERRIDE</name>
+                        <description>Override rx_dp value into controller</description>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>RX_DD_OVERRIDE</name>
+                        <description>Override rx_dd value into controller</description>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DM_OVV</name>
+                        <description>DM over voltage</description>
+                        <bitRange>[22:22]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>DP_OVV</name>
+                        <description>DP over voltage</description>
+                        <bitRange>[21:21]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>DM_OVCN</name>
+                        <description>DM overcurrent</description>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>DP_OVCN</name>
+                        <description>DP overcurrent</description>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>RX_DM</name>
+                        <description>DPM pin state</description>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>RX_DP</name>
+                        <description>DPP pin state</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>RX_DD</name>
+                        <description>Differential RX</description>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>TX_DIFFMODE</name>
+                        <description>TX_DIFFMODE=0: Single ended mode 
+                            TX_DIFFMODE=1: Differential drive mode (TX_DM, TX_DM_OE ignored)</description>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>TX_FSSLEW</name>
+                        <description>TX_FSSLEW=0: Low speed slew rate 
+                            TX_FSSLEW=1: Full speed slew rate</description>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>TX_PD</name>
+                        <description>TX power down override (if override enable is set). 1 = powered down.</description>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>RX_PD</name>
+                        <description>RX power down override (if override enable is set). 1 = powered down.</description>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>TX_DM</name>
+                        <description>Output data. TX_DIFFMODE=1, Ignored 
+                            TX_DIFFMODE=0, Drives DPM only. TX_DM_OE=1 to enable drive. DPM=TX_DM</description>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>TX_DP</name>
+                        <description>Output data. If TX_DIFFMODE=1, Drives DPP/DPM diff pair. TX_DP_OE=1 to enable drive. DPP=TX_DP, DPM=~TX_DP 
+                            If TX_DIFFMODE=0, Drives DPP only. TX_DP_OE=1 to enable drive. DPP=TX_DP</description>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>TX_DM_OE</name>
+                        <description>Output enable. If TX_DIFFMODE=1, Ignored. 
+                            If TX_DIFFMODE=0, OE for DPM only. 0 - DPM in Hi-Z state; 1 - DPM driving</description>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>TX_DP_OE</name>
+                        <description>Output enable. If TX_DIFFMODE=1, OE for DPP/DPM diff pair. 0 - DPP/DPM in Hi-Z state; 1 - DPP/DPM driving 
+                            If TX_DIFFMODE=0, OE for DPP only. 0 - DPP in Hi-Z state; 1 - DPP driving</description>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DM_PULLDN_EN</name>
+                        <description>DM pull down enable</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DM_PULLUP_EN</name>
+                        <description>DM pull up enable</description>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DM_PULLUP_HISEL</name>
+                        <description>Enable the second DM pull up resistor. 0 - Pull = Rpu2; 1 - Pull = Rpu1 + Rpu2</description>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DP_PULLDN_EN</name>
+                        <description>DP pull down enable</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DP_PULLUP_EN</name>
+                        <description>DP pull up enable</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DP_PULLUP_HISEL</name>
+                        <description>Enable the second DP pull up resistor. 0 - Pull = Rpu2; 1 - Pull = Rpu1 + Rpu2</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>USBPHY_DIRECT_OVERRIDE</name>
+                <addressOffset>0x00000080</addressOffset>
+                <description>Override enable for each control in usbphy_direct</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>RX_DM_OVERRIDE_EN</name>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>RX_DP_OVERRIDE_EN</name>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>RX_DD_OVERRIDE_EN</name>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>TX_DIFFMODE_OVERRIDE_EN</name>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DM_PULLUP_OVERRIDE_EN</name>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>TX_FSSLEW_OVERRIDE_EN</name>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>TX_PD_OVERRIDE_EN</name>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>RX_PD_OVERRIDE_EN</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>TX_DM_OVERRIDE_EN</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>TX_DP_OVERRIDE_EN</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>TX_DM_OE_OVERRIDE_EN</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>TX_DP_OE_OVERRIDE_EN</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DM_PULLDN_EN_OVERRIDE_EN</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DP_PULLDN_EN_OVERRIDE_EN</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DP_PULLUP_EN_OVERRIDE_EN</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DM_PULLUP_HISEL_OVERRIDE_EN</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DP_PULLUP_HISEL_OVERRIDE_EN</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>USBPHY_TRIM</name>
+                <addressOffset>0x00000084</addressOffset>
+                <description>Used to adjust trim values of USB phy pull down resistors.</description>
+                <resetValue>0x00001f1f</resetValue>
+                <fields>
+                    <field>
+                        <name>DM_PULLDN_TRIM</name>
+                        <description>Value to drive to USB PHY 
+                            DM pulldown resistor trim control 
+                            Experimental data suggests that the reset value will work, but this register allows adjustment if required</description>
+                        <bitRange>[12:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DP_PULLDN_TRIM</name>
+                        <description>Value to drive to USB PHY 
+                            DP pulldown resistor trim control 
+                            Experimental data suggests that the reset value will work, but this register allows adjustment if required</description>
+                        <bitRange>[4:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>LINESTATE_TUNING</name>
+                <addressOffset>0x00000088</addressOffset>
+                <description>Used for debug only.</description>
+                <resetValue>0x000000f8</resetValue>
+                <fields>
+                    <field>
+                        <name>SPARE_FIX</name>
+                        <bitRange>[11:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DEV_LS_WAKE_FIX</name>
+                        <description>Device - exit suspend on any non-idle signalling, not qualified with a 1ms timer</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DEV_RX_ERR_QUIESCE</name>
+                        <description>Device - suppress repeated errors until the device FSM is next in the process of decoding an inbound packet.</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SIE_RX_CHATTER_SE0_FIX</name>
+                        <description>RX - when recovering from line chatter or bitstuff errors, treat SE0 as the end of chatter as well as 
+                            8 consecutive idle bits.</description>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SIE_RX_BITSTUFF_FIX</name>
+                        <description>RX - when a bitstuff error is signalled by rx_dasm, unconditionally terminate RX decode to 
+                            avoid a hang during certain packet phases.</description>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DEV_BUFF_CONTROL_DOUBLE_READ_FIX</name>
+                        <description>Device - the controller FSM performs two reads of the buffer status memory address to 
+                            avoid sampling metastable data. An enabled buffer is only used if both reads match.</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>MULTI_HUB_FIX</name>
+                        <description>Host - increase inter-packet and turnaround timeouts to accommodate worst-case hub delays.</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LINESTATE_DELAY</name>
+                        <description>Device/Host - add an extra 1-bit debounce of linestate sampling.</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>RCV_DELAY</name>
+                        <description>Device - register the received data to account for hub bit dribble before EOP. Only affects certain hubs.</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INTR</name>
+                <addressOffset>0x0000008c</addressOffset>
+                <description>Raw Interrupts</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>EPX_STOPPED_ON_NAK</name>
+                        <description>Source: NAK_POLL.EPX_STOPPED_ON_NAK</description>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>DEV_SM_WATCHDOG_FIRED</name>
+                        <description>Source: DEV_SM_WATCHDOG.FIRED</description>
+                        <bitRange>[22:22]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>ENDPOINT_ERROR</name>
+                        <description>Source: SIE_STATUS.ENDPOINT_ERROR</description>
+                        <bitRange>[21:21]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>RX_SHORT_PACKET</name>
+                        <description>Source: SIE_STATUS.RX_SHORT_PACKET</description>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>EP_STALL_NAK</name>
+                        <description>Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by clearing all bits in EP_STATUS_STALL_NAK.</description>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>ABORT_DONE</name>
+                        <description>Raised when any bit in ABORT_DONE is set. Clear by clearing all bits in ABORT_DONE.</description>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>DEV_SOF</name>
+                        <description>Set every time the device receives a SOF (Start of Frame) packet. Cleared by reading SOF_RD</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SETUP_REQ</name>
+                        <description>Device. Source: SIE_STATUS.SETUP_REC</description>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>DEV_RESUME_FROM_HOST</name>
+                        <description>Set when the device receives a resume from the host. Cleared by writing to SIE_STATUS.RESUME</description>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>DEV_SUSPEND</name>
+                        <description>Set when the device suspend state changes. Cleared by writing to SIE_STATUS.SUSPENDED</description>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>DEV_CONN_DIS</name>
+                        <description>Set when the device connection state changes. Cleared by writing to SIE_STATUS.CONNECTED</description>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>BUS_RESET</name>
+                        <description>Source: SIE_STATUS.BUS_RESET</description>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>VBUS_DETECT</name>
+                        <description>Source: SIE_STATUS.VBUS_DETECTED</description>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>STALL</name>
+                        <description>Source: SIE_STATUS.STALL_REC</description>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>ERROR_CRC</name>
+                        <description>Source: SIE_STATUS.CRC_ERROR</description>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>ERROR_BIT_STUFF</name>
+                        <description>Source: SIE_STATUS.BIT_STUFF_ERROR</description>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>ERROR_RX_OVERFLOW</name>
+                        <description>Source: SIE_STATUS.RX_OVERFLOW</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>ERROR_RX_TIMEOUT</name>
+                        <description>Source: SIE_STATUS.RX_TIMEOUT</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>ERROR_DATA_SEQ</name>
+                        <description>Source: SIE_STATUS.DATA_SEQ_ERROR</description>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>BUFF_STATUS</name>
+                        <description>Raised when any bit in BUFF_STATUS is set. Clear by clearing all bits in BUFF_STATUS.</description>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>TRANS_COMPLETE</name>
+                        <description>Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by writing to this bit.</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>HOST_SOF</name>
+                        <description>Host: raised every time the host sends a SOF (Start of Frame). Cleared by reading SOF_RD</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>HOST_RESUME</name>
+                        <description>Host: raised when a device wakes up the host. Cleared by writing to SIE_STATUS.RESUME</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>HOST_CONN_DIS</name>
+                        <description>Host: raised when a device is connected or disconnected (i.e. when SIE_STATUS.SPEED changes). Cleared by writing to SIE_STATUS.SPEED</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INTE</name>
+                <addressOffset>0x00000090</addressOffset>
+                <description>Interrupt Enable</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>EPX_STOPPED_ON_NAK</name>
+                        <description>Source: NAK_POLL.EPX_STOPPED_ON_NAK</description>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DEV_SM_WATCHDOG_FIRED</name>
+                        <description>Source: DEV_SM_WATCHDOG.FIRED</description>
+                        <bitRange>[22:22]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ENDPOINT_ERROR</name>
+                        <description>Source: SIE_STATUS.ENDPOINT_ERROR</description>
+                        <bitRange>[21:21]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>RX_SHORT_PACKET</name>
+                        <description>Source: SIE_STATUS.RX_SHORT_PACKET</description>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>EP_STALL_NAK</name>
+                        <description>Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by clearing all bits in EP_STATUS_STALL_NAK.</description>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ABORT_DONE</name>
+                        <description>Raised when any bit in ABORT_DONE is set. Clear by clearing all bits in ABORT_DONE.</description>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DEV_SOF</name>
+                        <description>Set every time the device receives a SOF (Start of Frame) packet. Cleared by reading SOF_RD</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SETUP_REQ</name>
+                        <description>Device. Source: SIE_STATUS.SETUP_REC</description>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DEV_RESUME_FROM_HOST</name>
+                        <description>Set when the device receives a resume from the host. Cleared by writing to SIE_STATUS.RESUME</description>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DEV_SUSPEND</name>
+                        <description>Set when the device suspend state changes. Cleared by writing to SIE_STATUS.SUSPENDED</description>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DEV_CONN_DIS</name>
+                        <description>Set when the device connection state changes. Cleared by writing to SIE_STATUS.CONNECTED</description>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>BUS_RESET</name>
+                        <description>Source: SIE_STATUS.BUS_RESET</description>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>VBUS_DETECT</name>
+                        <description>Source: SIE_STATUS.VBUS_DETECTED</description>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>STALL</name>
+                        <description>Source: SIE_STATUS.STALL_REC</description>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ERROR_CRC</name>
+                        <description>Source: SIE_STATUS.CRC_ERROR</description>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ERROR_BIT_STUFF</name>
+                        <description>Source: SIE_STATUS.BIT_STUFF_ERROR</description>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ERROR_RX_OVERFLOW</name>
+                        <description>Source: SIE_STATUS.RX_OVERFLOW</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ERROR_RX_TIMEOUT</name>
+                        <description>Source: SIE_STATUS.RX_TIMEOUT</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ERROR_DATA_SEQ</name>
+                        <description>Source: SIE_STATUS.DATA_SEQ_ERROR</description>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>BUFF_STATUS</name>
+                        <description>Raised when any bit in BUFF_STATUS is set. Clear by clearing all bits in BUFF_STATUS.</description>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>TRANS_COMPLETE</name>
+                        <description>Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by writing to this bit.</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>HOST_SOF</name>
+                        <description>Host: raised every time the host sends a SOF (Start of Frame). Cleared by reading SOF_RD</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>HOST_RESUME</name>
+                        <description>Host: raised when a device wakes up the host. Cleared by writing to SIE_STATUS.RESUME</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>HOST_CONN_DIS</name>
+                        <description>Host: raised when a device is connected or disconnected (i.e. when SIE_STATUS.SPEED changes). Cleared by writing to SIE_STATUS.SPEED</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INTF</name>
+                <addressOffset>0x00000094</addressOffset>
+                <description>Interrupt Force</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>EPX_STOPPED_ON_NAK</name>
+                        <description>Source: NAK_POLL.EPX_STOPPED_ON_NAK</description>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DEV_SM_WATCHDOG_FIRED</name>
+                        <description>Source: DEV_SM_WATCHDOG.FIRED</description>
+                        <bitRange>[22:22]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ENDPOINT_ERROR</name>
+                        <description>Source: SIE_STATUS.ENDPOINT_ERROR</description>
+                        <bitRange>[21:21]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>RX_SHORT_PACKET</name>
+                        <description>Source: SIE_STATUS.RX_SHORT_PACKET</description>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>EP_STALL_NAK</name>
+                        <description>Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by clearing all bits in EP_STATUS_STALL_NAK.</description>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ABORT_DONE</name>
+                        <description>Raised when any bit in ABORT_DONE is set. Clear by clearing all bits in ABORT_DONE.</description>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DEV_SOF</name>
+                        <description>Set every time the device receives a SOF (Start of Frame) packet. Cleared by reading SOF_RD</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SETUP_REQ</name>
+                        <description>Device. Source: SIE_STATUS.SETUP_REC</description>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DEV_RESUME_FROM_HOST</name>
+                        <description>Set when the device receives a resume from the host. Cleared by writing to SIE_STATUS.RESUME</description>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DEV_SUSPEND</name>
+                        <description>Set when the device suspend state changes. Cleared by writing to SIE_STATUS.SUSPENDED</description>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DEV_CONN_DIS</name>
+                        <description>Set when the device connection state changes. Cleared by writing to SIE_STATUS.CONNECTED</description>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>BUS_RESET</name>
+                        <description>Source: SIE_STATUS.BUS_RESET</description>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>VBUS_DETECT</name>
+                        <description>Source: SIE_STATUS.VBUS_DETECTED</description>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>STALL</name>
+                        <description>Source: SIE_STATUS.STALL_REC</description>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ERROR_CRC</name>
+                        <description>Source: SIE_STATUS.CRC_ERROR</description>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ERROR_BIT_STUFF</name>
+                        <description>Source: SIE_STATUS.BIT_STUFF_ERROR</description>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ERROR_RX_OVERFLOW</name>
+                        <description>Source: SIE_STATUS.RX_OVERFLOW</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ERROR_RX_TIMEOUT</name>
+                        <description>Source: SIE_STATUS.RX_TIMEOUT</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ERROR_DATA_SEQ</name>
+                        <description>Source: SIE_STATUS.DATA_SEQ_ERROR</description>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>BUFF_STATUS</name>
+                        <description>Raised when any bit in BUFF_STATUS is set. Clear by clearing all bits in BUFF_STATUS.</description>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>TRANS_COMPLETE</name>
+                        <description>Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by writing to this bit.</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>HOST_SOF</name>
+                        <description>Host: raised every time the host sends a SOF (Start of Frame). Cleared by reading SOF_RD</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>HOST_RESUME</name>
+                        <description>Host: raised when a device wakes up the host. Cleared by writing to SIE_STATUS.RESUME</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>HOST_CONN_DIS</name>
+                        <description>Host: raised when a device is connected or disconnected (i.e. when SIE_STATUS.SPEED changes). Cleared by writing to SIE_STATUS.SPEED</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INTS</name>
+                <addressOffset>0x00000098</addressOffset>
+                <description>Interrupt status after masking &amp; forcing</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>EPX_STOPPED_ON_NAK</name>
+                        <description>Source: NAK_POLL.EPX_STOPPED_ON_NAK</description>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>DEV_SM_WATCHDOG_FIRED</name>
+                        <description>Source: DEV_SM_WATCHDOG.FIRED</description>
+                        <bitRange>[22:22]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>ENDPOINT_ERROR</name>
+                        <description>Source: SIE_STATUS.ENDPOINT_ERROR</description>
+                        <bitRange>[21:21]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>RX_SHORT_PACKET</name>
+                        <description>Source: SIE_STATUS.RX_SHORT_PACKET</description>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>EP_STALL_NAK</name>
+                        <description>Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by clearing all bits in EP_STATUS_STALL_NAK.</description>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>ABORT_DONE</name>
+                        <description>Raised when any bit in ABORT_DONE is set. Clear by clearing all bits in ABORT_DONE.</description>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>DEV_SOF</name>
+                        <description>Set every time the device receives a SOF (Start of Frame) packet. Cleared by reading SOF_RD</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SETUP_REQ</name>
+                        <description>Device. Source: SIE_STATUS.SETUP_REC</description>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>DEV_RESUME_FROM_HOST</name>
+                        <description>Set when the device receives a resume from the host. Cleared by writing to SIE_STATUS.RESUME</description>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>DEV_SUSPEND</name>
+                        <description>Set when the device suspend state changes. Cleared by writing to SIE_STATUS.SUSPENDED</description>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>DEV_CONN_DIS</name>
+                        <description>Set when the device connection state changes. Cleared by writing to SIE_STATUS.CONNECTED</description>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>BUS_RESET</name>
+                        <description>Source: SIE_STATUS.BUS_RESET</description>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>VBUS_DETECT</name>
+                        <description>Source: SIE_STATUS.VBUS_DETECTED</description>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>STALL</name>
+                        <description>Source: SIE_STATUS.STALL_REC</description>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>ERROR_CRC</name>
+                        <description>Source: SIE_STATUS.CRC_ERROR</description>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>ERROR_BIT_STUFF</name>
+                        <description>Source: SIE_STATUS.BIT_STUFF_ERROR</description>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>ERROR_RX_OVERFLOW</name>
+                        <description>Source: SIE_STATUS.RX_OVERFLOW</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>ERROR_RX_TIMEOUT</name>
+                        <description>Source: SIE_STATUS.RX_TIMEOUT</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>ERROR_DATA_SEQ</name>
+                        <description>Source: SIE_STATUS.DATA_SEQ_ERROR</description>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>BUFF_STATUS</name>
+                        <description>Raised when any bit in BUFF_STATUS is set. Clear by clearing all bits in BUFF_STATUS.</description>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>TRANS_COMPLETE</name>
+                        <description>Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by writing to this bit.</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>HOST_SOF</name>
+                        <description>Host: raised every time the host sends a SOF (Start of Frame). Cleared by reading SOF_RD</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>HOST_RESUME</name>
+                        <description>Host: raised when a device wakes up the host. Cleared by writing to SIE_STATUS.RESUME</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>HOST_CONN_DIS</name>
+                        <description>Host: raised when a device is connected or disconnected (i.e. when SIE_STATUS.SPEED changes). Cleared by writing to SIE_STATUS.SPEED</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SOF_TIMESTAMP_RAW</name>
+                <addressOffset>0x00000100</addressOffset>
+                <description>Device only. Raw value of free-running PHY clock counter @48MHz. Used to calculate time between SOF events.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>SOF_TIMESTAMP_RAW</name>
+                        <bitRange>[20:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SOF_TIMESTAMP_LAST</name>
+                <addressOffset>0x00000104</addressOffset>
+                <description>Device only. Value of free-running PHY clock counter @48MHz when last SOF event occurred.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>SOF_TIMESTAMP_LAST</name>
+                        <bitRange>[20:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SM_STATE</name>
+                <addressOffset>0x00000108</addressOffset>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>RX_DASM</name>
+                        <bitRange>[11:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>BC_STATE</name>
+                        <bitRange>[7:5]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>STATE</name>
+                        <bitRange>[4:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>EP_TX_ERROR</name>
+                <addressOffset>0x0000010c</addressOffset>
+                <description>TX error count for each endpoint. Write to each field to reset the counter to 0.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>EP15</name>
+                        <bitRange>[31:30]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP14</name>
+                        <bitRange>[29:28]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP13</name>
+                        <bitRange>[27:26]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP12</name>
+                        <bitRange>[25:24]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP11</name>
+                        <bitRange>[23:22]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP10</name>
+                        <bitRange>[21:20]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP9</name>
+                        <bitRange>[19:18]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP8</name>
+                        <bitRange>[17:16]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP7</name>
+                        <bitRange>[15:14]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP6</name>
+                        <bitRange>[13:12]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP5</name>
+                        <bitRange>[11:10]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP4</name>
+                        <bitRange>[9:8]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP3</name>
+                        <bitRange>[7:6]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP2</name>
+                        <bitRange>[5:4]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP1</name>
+                        <bitRange>[3:2]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP0</name>
+                        <bitRange>[1:0]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>EP_RX_ERROR</name>
+                <addressOffset>0x00000110</addressOffset>
+                <description>RX error count for each endpoint. Write to each field to reset the counter to 0.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>EP15_SEQ</name>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP15_TRANSACTION</name>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP14_SEQ</name>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP14_TRANSACTION</name>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP13_SEQ</name>
+                        <bitRange>[27:27]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP13_TRANSACTION</name>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP12_SEQ</name>
+                        <bitRange>[25:25]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP12_TRANSACTION</name>
+                        <bitRange>[24:24]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP11_SEQ</name>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP11_TRANSACTION</name>
+                        <bitRange>[22:22]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP10_SEQ</name>
+                        <bitRange>[21:21]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP10_TRANSACTION</name>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP9_SEQ</name>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP9_TRANSACTION</name>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP8_SEQ</name>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP8_TRANSACTION</name>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP7_SEQ</name>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP7_TRANSACTION</name>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP6_SEQ</name>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP6_TRANSACTION</name>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP5_SEQ</name>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP5_TRANSACTION</name>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP4_SEQ</name>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP4_TRANSACTION</name>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP3_SEQ</name>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP3_TRANSACTION</name>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP2_SEQ</name>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP2_TRANSACTION</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP1_SEQ</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP1_TRANSACTION</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP0_SEQ</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>EP0_TRANSACTION</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>DEV_SM_WATCHDOG</name>
+                <addressOffset>0x00000114</addressOffset>
+                <description>Watchdog that forces the device state machine to idle and raises an interrupt if the device stays in a state that isn&#39;t idle for the configured limit. The counter is reset on every state transition. 
+                    Set limit while enable is low and then set the enable.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>FIRED</name>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>RESET</name>
+                        <description>Set to 1 to forcibly reset the device state machine on watchdog expiry</description>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ENABLE</name>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LIMIT</name>
+                        <bitRange>[17:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+        </registers>
+    </peripheral>
+    <peripheral>
+        <name>TRNG</name>
+        <description>ARM TrustZone RNG register block</description>
+        <baseAddress>0x400f0000</baseAddress>
+        <addressBlock>
+            <offset>0</offset>
+            <size>492</size>
+            <usage>registers</usage>
+        </addressBlock>
+        <interrupt>
+            <name>TRNG_IRQ</name>
+            <value>39</value>
+        </interrupt>
+        <registers>
+            <register>
+                <name>RNG_IMR</name>
+                <addressOffset>0x00000100</addressOffset>
+                <description>Interrupt masking.</description>
+                <resetValue>0x0000000f</resetValue>
+                <fields>
+                    <field>
+                        <name>RESERVED</name>
+                        <description>RESERVED</description>
+                        <bitRange>[31:4]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>VN_ERR_INT_MASK</name>
+                        <description>1&#39;b1-mask interrupt, no interrupt will be generated. See RNG_ISR for an explanation on this interrupt.</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CRNGT_ERR_INT_MASK</name>
+                        <description>1&#39;b1-mask interrupt, no interrupt will be generated. See RNG_ISR for an explanation on this interrupt.</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>AUTOCORR_ERR_INT_MASK</name>
+                        <description>1&#39;b1-mask interrupt, no interrupt will be generated. See RNG_ISR for an explanation on this interrupt.</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>EHR_VALID_INT_MASK</name>
+                        <description>1&#39;b1-mask interrupt, no interrupt will be generated. See RNG_ISR for an explanation on this interrupt.</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>RNG_ISR</name>
+                <addressOffset>0x00000104</addressOffset>
+                <description>RNG status register. If corresponding RNG_IMR bit is unmasked, an interrupt will be generated.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>RESERVED</name>
+                        <description>RESERVED</description>
+                        <bitRange>[31:4]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>VN_ERR</name>
+                        <description>1&#39;b1 indicates Von Neuman error. Error in von Neuman occurs if 32 consecutive collected bits are identical, ZERO or ONE.</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CRNGT_ERR</name>
+                        <description>1&#39;b1 indicates CRNGT in the RNG test failed. Failure occurs when two consecutive blocks of 16 collected bits are equal.</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>AUTOCORR_ERR</name>
+                        <description>1&#39;b1 indicates Autocorrelation test failed four times in a row. When set, RNG cease from functioning until next reset.</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>EHR_VALID</name>
+                        <description>1&#39;b1 indicates that 192 bits have been collected in the RNG, and are ready to be read.</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>RNG_ICR</name>
+                <addressOffset>0x00000108</addressOffset>
+                <description>Interrupt/status bit clear Register.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>RESERVED</name>
+                        <description>RESERVED</description>
+                        <bitRange>[31:4]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>VN_ERR</name>
+                        <description>Write 1&#39;b1 - clear corresponding bit in RNG_ISR.</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CRNGT_ERR</name>
+                        <description>Write 1&#39;b1 - clear corresponding bit in RNG_ISR.</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>AUTOCORR_ERR</name>
+                        <description>Cannot be cleared by SW! Only RNG reset clears this bit.</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>EHR_VALID</name>
+                        <description>Write 1&#39;b1 - clear corresponding bit in RNG_ISR.</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>TRNG_CONFIG</name>
+                <addressOffset>0x0000010c</addressOffset>
+                <description>Selecting the inverter-chain length.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>RESERVED</name>
+                        <description>RESERVED</description>
+                        <bitRange>[31:2]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>RND_SRC_SEL</name>
+                        <description>Selects the number of inverters (out of four possible selections) in the ring oscillator (the entropy source).</description>
+                        <bitRange>[1:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>TRNG_VALID</name>
+                <addressOffset>0x00000110</addressOffset>
+                <description>192 bit collection indication.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>RESERVED</name>
+                        <description>RESERVED</description>
+                        <bitRange>[31:1]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>EHR_VALID</name>
+                        <description>1&#39;b1 indicates that collection of bits in the RNG is completed, and data can be read from EHR_DATA register.</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>EHR_DATA0</name>
+                <addressOffset>0x00000114</addressOffset>
+                <description>RNG collected bits.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>EHR_DATA0</name>
+                        <description>Bits [31:0] of Entropy Holding Register (EHR) - RNG output register</description>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>EHR_DATA1</name>
+                <addressOffset>0x00000118</addressOffset>
+                <description>RNG collected bits.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>EHR_DATA1</name>
+                        <description>Bits [63:32] of Entropy Holding Register (EHR) - RNG output register</description>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>EHR_DATA2</name>
+                <addressOffset>0x0000011c</addressOffset>
+                <description>RNG collected bits.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>EHR_DATA2</name>
+                        <description>Bits [95:64] of Entropy Holding Register (EHR) - RNG output register</description>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>EHR_DATA3</name>
+                <addressOffset>0x00000120</addressOffset>
+                <description>RNG collected bits.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>EHR_DATA3</name>
+                        <description>Bits [127:96] of Entropy Holding Register (EHR) - RNG output register</description>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>EHR_DATA4</name>
+                <addressOffset>0x00000124</addressOffset>
+                <description>RNG collected bits.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>EHR_DATA4</name>
+                        <description>Bits [159:128] of Entropy Holding Register (EHR) - RNG output register</description>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>EHR_DATA5</name>
+                <addressOffset>0x00000128</addressOffset>
+                <description>RNG collected bits.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>EHR_DATA5</name>
+                        <description>Bits [191:160] of Entropy Holding Register (EHR) - RNG output register</description>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>RND_SOURCE_ENABLE</name>
+                <addressOffset>0x0000012c</addressOffset>
+                <description>Enable signal for the random source.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>RESERVED</name>
+                        <description>RESERVED</description>
+                        <bitRange>[31:1]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>RND_SRC_EN</name>
+                        <description>* 1&#39;b1 - entropy source is enabled. *1&#39;b0 - entropy source is disabled</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SAMPLE_CNT1</name>
+                <addressOffset>0x00000130</addressOffset>
+                <description>Counts clocks between sampling of random bit.</description>
+                <resetValue>0x0000ffff</resetValue>
+                <fields>
+                    <field>
+                        <name>SAMPLE_CNTR1</name>
+                        <description>Sets the number of rng_clk cycles between two consecutive ring oscillator samples. Note! If the Von-Neuman is bypassed, the minimum value for sample counter must not be less then decimal seventeen</description>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>AUTOCORR_STATISTIC</name>
+                <addressOffset>0x00000134</addressOffset>
+                <description>Statistic about Autocorrelation test activations.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>RESERVED</name>
+                        <description>RESERVED</description>
+                        <bitRange>[31:22]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>AUTOCORR_FAILS</name>
+                        <description>Count each time an autocorrelation test fails. Any write to the register reset the counter. Stop collecting statistic if one of the counters reached the limit.</description>
+                        <bitRange>[21:14]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>AUTOCORR_TRYS</name>
+                        <description>Count each time an autocorrelation test starts. Any write to the register reset the counter. Stop collecting statistic if one of the counters reached the limit.</description>
+                        <bitRange>[13:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>TRNG_DEBUG_CONTROL</name>
+                <addressOffset>0x00000138</addressOffset>
+                <description>Debug register.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>AUTO_CORRELATE_BYPASS</name>
+                        <description>When set, the autocorrelation test in the TRNG module is bypassed.</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>TRNG_CRNGT_BYPASS</name>
+                        <description>When set, the CRNGT test in the RNG is bypassed.</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>VNC_BYPASS</name>
+                        <description>When set, the Von-Neuman balancer is bypassed (including the 32 consecutive bits test).</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>RESERVED</name>
+                        <description>N/A</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>TRNG_SW_RESET</name>
+                <addressOffset>0x00000140</addressOffset>
+                <description>Generate internal SW reset within the RNG block.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>RESERVED</name>
+                        <description>RESERVED</description>
+                        <bitRange>[31:1]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>TRNG_SW_RESET</name>
+                        <description>Writing 1&#39;b1 to this register causes an internal RNG reset.</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>RNG_DEBUG_EN_INPUT</name>
+                <addressOffset>0x000001b4</addressOffset>
+                <description>Enable the RNG debug mode</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>RESERVED</name>
+                        <description>RESERVED</description>
+                        <bitRange>[31:1]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>RNG_DEBUG_EN</name>
+                        <description>* 1&#39;b1 - debug mode is enabled. *1&#39;b0 - debug mode is disabled</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>TRNG_BUSY</name>
+                <addressOffset>0x000001b8</addressOffset>
+                <description>RNG Busy indication.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>RESERVED</name>
+                        <description>RESERVED</description>
+                        <bitRange>[31:1]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>TRNG_BUSY</name>
+                        <description>Reflects rng_busy status.</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>RST_BITS_COUNTER</name>
+                <addressOffset>0x000001bc</addressOffset>
+                <description>Reset the counter of collected bits in the RNG.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>RESERVED</name>
+                        <description>RESERVED</description>
+                        <bitRange>[31:1]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>RST_BITS_COUNTER</name>
+                        <description>Writing any value to this address will reset the bits counter and RNG valid registers. RND_SORCE_ENABLE register must be unset in order for the reset to take place.</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>RNG_VERSION</name>
+                <addressOffset>0x000001c0</addressOffset>
+                <description>Displays the version settings of the TRNG.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>RESERVED</name>
+                        <description>RESERVED</description>
+                        <bitRange>[31:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>RNG_USE_5_SBOXES</name>
+                        <description>* 1&#39;b1 - 5 SBOX AES. *1&#39;b0 - 20 SBOX AES</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>RESEEDING_EXISTS</name>
+                        <description>* 1&#39;b1 - Exists. *1&#39;b0 - Does not exist</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>KAT_EXISTS</name>
+                        <description>* 1&#39;b1 - Exists. *1&#39;b0 - Does not exist</description>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>PRNG_EXISTS</name>
+                        <description>* 1&#39;b1 - Exists. *1&#39;b0 - Does not exist</description>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>TRNG_TESTS_BYPASS_EN</name>
+                        <description>* 1&#39;b1 - Exists. *1&#39;b0 - Does not exist</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>AUTOCORR_EXISTS</name>
+                        <description>* 1&#39;b1 - Exists. *1&#39;b0 - Does not exist</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CRNGT_EXISTS</name>
+                        <description>* 1&#39;b1 - Exists. *1&#39;b0 - Does not exist</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>EHR_WIDTH_192</name>
+                        <description>* 1&#39;b1 - 192-bit EHR. *1&#39;b0 - 128-bit EHR</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>RNG_BIST_CNTR_0</name>
+                <addressOffset>0x000001e0</addressOffset>
+                <description>Collected BIST results.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>RESERVED</name>
+                        <description>RESERVED</description>
+                        <bitRange>[31:22]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>ROSC_CNTR_VAL</name>
+                        <description>Reflects the results of RNG BIST counter.</description>
+                        <bitRange>[21:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>RNG_BIST_CNTR_1</name>
+                <addressOffset>0x000001e4</addressOffset>
+                <description>Collected BIST results.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>RESERVED</name>
+                        <description>RESERVED</description>
+                        <bitRange>[31:22]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>ROSC_CNTR_VAL</name>
+                        <description>Reflects the results of RNG BIST counter.</description>
+                        <bitRange>[21:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>RNG_BIST_CNTR_2</name>
+                <addressOffset>0x000001e8</addressOffset>
+                <description>Collected BIST results.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>RESERVED</name>
+                        <description>RESERVED</description>
+                        <bitRange>[31:22]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>ROSC_CNTR_VAL</name>
+                        <description>Reflects the results of RNG BIST counter.</description>
+                        <bitRange>[21:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+        </registers>
+    </peripheral>
+    <peripheral>
+        <name>GLITCH_DETECTOR</name>
+        <description>Glitch detector controls</description>
+        <baseAddress>0x40158000</baseAddress>
+        <addressBlock>
+            <offset>0</offset>
+            <size>24</size>
+            <usage>registers</usage>
+        </addressBlock>
+        <registers>
+            <register>
+                <name>ARM</name>
+                <addressOffset>0x00000000</addressOffset>
+                <description>Forcibly arm the glitch detectors, if they are not already armed by OTP. When armed, any individual detector trigger will cause a restart of the switched core power domain&#39;s power-on reset state machine.
+
+                    Glitch detector triggers are recorded accumulatively in TRIG_STATUS. If the system is reset by a glitch detector trigger, this is recorded in POWMAN_CHIP_RESET.
+
+                    This register is Secure read/write only.</description>
+                <resetValue>0x00005bad</resetValue>
+                <fields>
+                    <field>
+                        <name>ARM</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>no</name>
+                                <value>23469</value>
+                                <description>Do not force the glitch detectors to be armed</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>yes</name>
+                                <value>0</value>
+                                <description>Force the glitch detectors to be armed. (Any value other than ARM_NO counts as YES)</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>DISARM</name>
+                <addressOffset>0x00000004</addressOffset>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>DISARM</name>
+                        <description>Forcibly disarm the glitch detectors, if they are armed by OTP. Ignored if ARM is YES.
+
+                            This register is Secure read/write only.</description>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>no</name>
+                                <value>0</value>
+                                <description>Do not disarm the glitch detectors. (Any value other than DISARM_YES counts as NO)</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>yes</name>
+                                <value>56495</value>
+                                <description>Disarm the glitch detectors</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SENSITIVITY</name>
+                <addressOffset>0x00000008</addressOffset>
+                <description>Adjust the sensitivity of glitch detectors to values other than their OTP-provided defaults.
+
+                    This register is Secure read/write only.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>DEFAULT</name>
+                        <bitRange>[31:24]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>yes</name>
+                                <value>0</value>
+                                <description>Use the default sensitivity configured in OTP for all detectors. (Any value other than DEFAULT_NO counts as YES)</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>no</name>
+                                <value>222</value>
+                                <description>Do not use the default sensitivity configured in OTP. Instead use the value from this register.</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>DET3_INV</name>
+                        <description>Must be the inverse of DET3, else the default value is used.</description>
+                        <bitRange>[15:14]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DET2_INV</name>
+                        <description>Must be the inverse of DET2, else the default value is used.</description>
+                        <bitRange>[13:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DET1_INV</name>
+                        <description>Must be the inverse of DET1, else the default value is used.</description>
+                        <bitRange>[11:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DET0_INV</name>
+                        <description>Must be the inverse of DET0, else the default value is used.</description>
+                        <bitRange>[9:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DET3</name>
+                        <description>Set sensitivity for detector 3. Higher values are more sensitive.</description>
+                        <bitRange>[7:6]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DET2</name>
+                        <description>Set sensitivity for detector 2. Higher values are more sensitive.</description>
+                        <bitRange>[5:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DET1</name>
+                        <description>Set sensitivity for detector 1. Higher values are more sensitive.</description>
+                        <bitRange>[3:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DET0</name>
+                        <description>Set sensitivity for detector 0. Higher values are more sensitive.</description>
+                        <bitRange>[1:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>LOCK</name>
+                <addressOffset>0x0000000c</addressOffset>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>LOCK</name>
+                        <description>Write any nonzero value to disable writes to ARM, DISARM, SENSITIVITY and LOCK. This register is Secure read/write only.</description>
+                        <bitRange>[7:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>TRIG_STATUS</name>
+                <addressOffset>0x00000010</addressOffset>
+                <description>Set when a detector output triggers. Write-1-clear.
+
+                    (May immediately return high if the detector remains in a failed state. Detectors can only be cleared by a full reset of the switched core power domain.)
+
+                    This register is Secure read/write only.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>DET3</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>DET2</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>DET1</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>DET0</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>TRIG_FORCE</name>
+                <addressOffset>0x00000014</addressOffset>
+                <description>Simulate the firing of one or more detectors. Writing ones to this register will set the matching bits in STATUS_TRIG.
+
+                    If the glitch detectors are currently armed, writing ones will also immediately reset the switched core power domain, and set the reset reason latches in POWMAN_CHIP_RESET to indicate a glitch detector resets.
+
+                    This register is Secure read/write only.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>TRIG_FORCE</name>
+                        <bitRange>[3:0]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                </fields>
+            </register>
+        </registers>
+    </peripheral>
+    <peripheral>
+        <name>OTP</name>
+        <description>SNPS OTP control IF (SBPI and RPi wrapper control)</description>
+        <baseAddress>0x40120000</baseAddress>
+        <addressBlock>
+            <offset>0</offset>
+            <size>372</size>
+            <usage>registers</usage>
+        </addressBlock>
+        <interrupt>
+            <name>OTP_IRQ</name>
+            <value>38</value>
+        </interrupt>
+        <registers>
+            <register>
+                <name>SW_LOCK0</name>
+                <addressOffset>0x00000000</addressOffset>
+                <description>Software lock register for page 0.
+
+                    Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>NSEC</name>
+                        <description>Non-secure lock status. Writes are OR&#39;d with the current value.</description>
+                        <bitRange>[3:2]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>SEC</name>
+                        <description>Secure lock status. Writes are OR&#39;d with the current value. This field is read-only to Non-secure code.</description>
+                        <bitRange>[1:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SW_LOCK1</name>
+                <addressOffset>0x00000004</addressOffset>
+                <description>Software lock register for page 1.
+
+                    Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>NSEC</name>
+                        <description>Non-secure lock status. Writes are OR&#39;d with the current value.</description>
+                        <bitRange>[3:2]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>SEC</name>
+                        <description>Secure lock status. Writes are OR&#39;d with the current value. This field is read-only to Non-secure code.</description>
+                        <bitRange>[1:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SW_LOCK2</name>
+                <addressOffset>0x00000008</addressOffset>
+                <description>Software lock register for page 2.
+
+                    Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>NSEC</name>
+                        <description>Non-secure lock status. Writes are OR&#39;d with the current value.</description>
+                        <bitRange>[3:2]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>SEC</name>
+                        <description>Secure lock status. Writes are OR&#39;d with the current value. This field is read-only to Non-secure code.</description>
+                        <bitRange>[1:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SW_LOCK3</name>
+                <addressOffset>0x0000000c</addressOffset>
+                <description>Software lock register for page 3.
+
+                    Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>NSEC</name>
+                        <description>Non-secure lock status. Writes are OR&#39;d with the current value.</description>
+                        <bitRange>[3:2]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>SEC</name>
+                        <description>Secure lock status. Writes are OR&#39;d with the current value. This field is read-only to Non-secure code.</description>
+                        <bitRange>[1:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SW_LOCK4</name>
+                <addressOffset>0x00000010</addressOffset>
+                <description>Software lock register for page 4.
+
+                    Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>NSEC</name>
+                        <description>Non-secure lock status. Writes are OR&#39;d with the current value.</description>
+                        <bitRange>[3:2]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>SEC</name>
+                        <description>Secure lock status. Writes are OR&#39;d with the current value. This field is read-only to Non-secure code.</description>
+                        <bitRange>[1:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SW_LOCK5</name>
+                <addressOffset>0x00000014</addressOffset>
+                <description>Software lock register for page 5.
+
+                    Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>NSEC</name>
+                        <description>Non-secure lock status. Writes are OR&#39;d with the current value.</description>
+                        <bitRange>[3:2]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>SEC</name>
+                        <description>Secure lock status. Writes are OR&#39;d with the current value. This field is read-only to Non-secure code.</description>
+                        <bitRange>[1:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SW_LOCK6</name>
+                <addressOffset>0x00000018</addressOffset>
+                <description>Software lock register for page 6.
+
+                    Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>NSEC</name>
+                        <description>Non-secure lock status. Writes are OR&#39;d with the current value.</description>
+                        <bitRange>[3:2]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>SEC</name>
+                        <description>Secure lock status. Writes are OR&#39;d with the current value. This field is read-only to Non-secure code.</description>
+                        <bitRange>[1:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SW_LOCK7</name>
+                <addressOffset>0x0000001c</addressOffset>
+                <description>Software lock register for page 7.
+
+                    Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>NSEC</name>
+                        <description>Non-secure lock status. Writes are OR&#39;d with the current value.</description>
+                        <bitRange>[3:2]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>SEC</name>
+                        <description>Secure lock status. Writes are OR&#39;d with the current value. This field is read-only to Non-secure code.</description>
+                        <bitRange>[1:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SW_LOCK8</name>
+                <addressOffset>0x00000020</addressOffset>
+                <description>Software lock register for page 8.
+
+                    Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>NSEC</name>
+                        <description>Non-secure lock status. Writes are OR&#39;d with the current value.</description>
+                        <bitRange>[3:2]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>SEC</name>
+                        <description>Secure lock status. Writes are OR&#39;d with the current value. This field is read-only to Non-secure code.</description>
+                        <bitRange>[1:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SW_LOCK9</name>
+                <addressOffset>0x00000024</addressOffset>
+                <description>Software lock register for page 9.
+
+                    Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>NSEC</name>
+                        <description>Non-secure lock status. Writes are OR&#39;d with the current value.</description>
+                        <bitRange>[3:2]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>SEC</name>
+                        <description>Secure lock status. Writes are OR&#39;d with the current value. This field is read-only to Non-secure code.</description>
+                        <bitRange>[1:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SW_LOCK10</name>
+                <addressOffset>0x00000028</addressOffset>
+                <description>Software lock register for page 10.
+
+                    Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>NSEC</name>
+                        <description>Non-secure lock status. Writes are OR&#39;d with the current value.</description>
+                        <bitRange>[3:2]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>SEC</name>
+                        <description>Secure lock status. Writes are OR&#39;d with the current value. This field is read-only to Non-secure code.</description>
+                        <bitRange>[1:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SW_LOCK11</name>
+                <addressOffset>0x0000002c</addressOffset>
+                <description>Software lock register for page 11.
+
+                    Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>NSEC</name>
+                        <description>Non-secure lock status. Writes are OR&#39;d with the current value.</description>
+                        <bitRange>[3:2]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>SEC</name>
+                        <description>Secure lock status. Writes are OR&#39;d with the current value. This field is read-only to Non-secure code.</description>
+                        <bitRange>[1:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SW_LOCK12</name>
+                <addressOffset>0x00000030</addressOffset>
+                <description>Software lock register for page 12.
+
+                    Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>NSEC</name>
+                        <description>Non-secure lock status. Writes are OR&#39;d with the current value.</description>
+                        <bitRange>[3:2]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>SEC</name>
+                        <description>Secure lock status. Writes are OR&#39;d with the current value. This field is read-only to Non-secure code.</description>
+                        <bitRange>[1:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SW_LOCK13</name>
+                <addressOffset>0x00000034</addressOffset>
+                <description>Software lock register for page 13.
+
+                    Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>NSEC</name>
+                        <description>Non-secure lock status. Writes are OR&#39;d with the current value.</description>
+                        <bitRange>[3:2]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>SEC</name>
+                        <description>Secure lock status. Writes are OR&#39;d with the current value. This field is read-only to Non-secure code.</description>
+                        <bitRange>[1:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SW_LOCK14</name>
+                <addressOffset>0x00000038</addressOffset>
+                <description>Software lock register for page 14.
+
+                    Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>NSEC</name>
+                        <description>Non-secure lock status. Writes are OR&#39;d with the current value.</description>
+                        <bitRange>[3:2]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>SEC</name>
+                        <description>Secure lock status. Writes are OR&#39;d with the current value. This field is read-only to Non-secure code.</description>
+                        <bitRange>[1:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SW_LOCK15</name>
+                <addressOffset>0x0000003c</addressOffset>
+                <description>Software lock register for page 15.
+
+                    Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>NSEC</name>
+                        <description>Non-secure lock status. Writes are OR&#39;d with the current value.</description>
+                        <bitRange>[3:2]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>SEC</name>
+                        <description>Secure lock status. Writes are OR&#39;d with the current value. This field is read-only to Non-secure code.</description>
+                        <bitRange>[1:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SW_LOCK16</name>
+                <addressOffset>0x00000040</addressOffset>
+                <description>Software lock register for page 16.
+
+                    Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>NSEC</name>
+                        <description>Non-secure lock status. Writes are OR&#39;d with the current value.</description>
+                        <bitRange>[3:2]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>SEC</name>
+                        <description>Secure lock status. Writes are OR&#39;d with the current value. This field is read-only to Non-secure code.</description>
+                        <bitRange>[1:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SW_LOCK17</name>
+                <addressOffset>0x00000044</addressOffset>
+                <description>Software lock register for page 17.
+
+                    Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>NSEC</name>
+                        <description>Non-secure lock status. Writes are OR&#39;d with the current value.</description>
+                        <bitRange>[3:2]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>SEC</name>
+                        <description>Secure lock status. Writes are OR&#39;d with the current value. This field is read-only to Non-secure code.</description>
+                        <bitRange>[1:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SW_LOCK18</name>
+                <addressOffset>0x00000048</addressOffset>
+                <description>Software lock register for page 18.
+
+                    Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>NSEC</name>
+                        <description>Non-secure lock status. Writes are OR&#39;d with the current value.</description>
+                        <bitRange>[3:2]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>SEC</name>
+                        <description>Secure lock status. Writes are OR&#39;d with the current value. This field is read-only to Non-secure code.</description>
+                        <bitRange>[1:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SW_LOCK19</name>
+                <addressOffset>0x0000004c</addressOffset>
+                <description>Software lock register for page 19.
+
+                    Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>NSEC</name>
+                        <description>Non-secure lock status. Writes are OR&#39;d with the current value.</description>
+                        <bitRange>[3:2]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>SEC</name>
+                        <description>Secure lock status. Writes are OR&#39;d with the current value. This field is read-only to Non-secure code.</description>
+                        <bitRange>[1:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SW_LOCK20</name>
+                <addressOffset>0x00000050</addressOffset>
+                <description>Software lock register for page 20.
+
+                    Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>NSEC</name>
+                        <description>Non-secure lock status. Writes are OR&#39;d with the current value.</description>
+                        <bitRange>[3:2]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>SEC</name>
+                        <description>Secure lock status. Writes are OR&#39;d with the current value. This field is read-only to Non-secure code.</description>
+                        <bitRange>[1:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SW_LOCK21</name>
+                <addressOffset>0x00000054</addressOffset>
+                <description>Software lock register for page 21.
+
+                    Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>NSEC</name>
+                        <description>Non-secure lock status. Writes are OR&#39;d with the current value.</description>
+                        <bitRange>[3:2]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>SEC</name>
+                        <description>Secure lock status. Writes are OR&#39;d with the current value. This field is read-only to Non-secure code.</description>
+                        <bitRange>[1:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SW_LOCK22</name>
+                <addressOffset>0x00000058</addressOffset>
+                <description>Software lock register for page 22.
+
+                    Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>NSEC</name>
+                        <description>Non-secure lock status. Writes are OR&#39;d with the current value.</description>
+                        <bitRange>[3:2]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>SEC</name>
+                        <description>Secure lock status. Writes are OR&#39;d with the current value. This field is read-only to Non-secure code.</description>
+                        <bitRange>[1:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SW_LOCK23</name>
+                <addressOffset>0x0000005c</addressOffset>
+                <description>Software lock register for page 23.
+
+                    Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>NSEC</name>
+                        <description>Non-secure lock status. Writes are OR&#39;d with the current value.</description>
+                        <bitRange>[3:2]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>SEC</name>
+                        <description>Secure lock status. Writes are OR&#39;d with the current value. This field is read-only to Non-secure code.</description>
+                        <bitRange>[1:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SW_LOCK24</name>
+                <addressOffset>0x00000060</addressOffset>
+                <description>Software lock register for page 24.
+
+                    Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>NSEC</name>
+                        <description>Non-secure lock status. Writes are OR&#39;d with the current value.</description>
+                        <bitRange>[3:2]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>SEC</name>
+                        <description>Secure lock status. Writes are OR&#39;d with the current value. This field is read-only to Non-secure code.</description>
+                        <bitRange>[1:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SW_LOCK25</name>
+                <addressOffset>0x00000064</addressOffset>
+                <description>Software lock register for page 25.
+
+                    Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>NSEC</name>
+                        <description>Non-secure lock status. Writes are OR&#39;d with the current value.</description>
+                        <bitRange>[3:2]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>SEC</name>
+                        <description>Secure lock status. Writes are OR&#39;d with the current value. This field is read-only to Non-secure code.</description>
+                        <bitRange>[1:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SW_LOCK26</name>
+                <addressOffset>0x00000068</addressOffset>
+                <description>Software lock register for page 26.
+
+                    Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>NSEC</name>
+                        <description>Non-secure lock status. Writes are OR&#39;d with the current value.</description>
+                        <bitRange>[3:2]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>SEC</name>
+                        <description>Secure lock status. Writes are OR&#39;d with the current value. This field is read-only to Non-secure code.</description>
+                        <bitRange>[1:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SW_LOCK27</name>
+                <addressOffset>0x0000006c</addressOffset>
+                <description>Software lock register for page 27.
+
+                    Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>NSEC</name>
+                        <description>Non-secure lock status. Writes are OR&#39;d with the current value.</description>
+                        <bitRange>[3:2]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>SEC</name>
+                        <description>Secure lock status. Writes are OR&#39;d with the current value. This field is read-only to Non-secure code.</description>
+                        <bitRange>[1:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SW_LOCK28</name>
+                <addressOffset>0x00000070</addressOffset>
+                <description>Software lock register for page 28.
+
+                    Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>NSEC</name>
+                        <description>Non-secure lock status. Writes are OR&#39;d with the current value.</description>
+                        <bitRange>[3:2]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>SEC</name>
+                        <description>Secure lock status. Writes are OR&#39;d with the current value. This field is read-only to Non-secure code.</description>
+                        <bitRange>[1:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SW_LOCK29</name>
+                <addressOffset>0x00000074</addressOffset>
+                <description>Software lock register for page 29.
+
+                    Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>NSEC</name>
+                        <description>Non-secure lock status. Writes are OR&#39;d with the current value.</description>
+                        <bitRange>[3:2]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>SEC</name>
+                        <description>Secure lock status. Writes are OR&#39;d with the current value. This field is read-only to Non-secure code.</description>
+                        <bitRange>[1:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SW_LOCK30</name>
+                <addressOffset>0x00000078</addressOffset>
+                <description>Software lock register for page 30.
+
+                    Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>NSEC</name>
+                        <description>Non-secure lock status. Writes are OR&#39;d with the current value.</description>
+                        <bitRange>[3:2]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>SEC</name>
+                        <description>Secure lock status. Writes are OR&#39;d with the current value. This field is read-only to Non-secure code.</description>
+                        <bitRange>[1:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SW_LOCK31</name>
+                <addressOffset>0x0000007c</addressOffset>
+                <description>Software lock register for page 31.
+
+                    Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>NSEC</name>
+                        <description>Non-secure lock status. Writes are OR&#39;d with the current value.</description>
+                        <bitRange>[3:2]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>SEC</name>
+                        <description>Secure lock status. Writes are OR&#39;d with the current value. This field is read-only to Non-secure code.</description>
+                        <bitRange>[1:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SW_LOCK32</name>
+                <addressOffset>0x00000080</addressOffset>
+                <description>Software lock register for page 32.
+
+                    Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>NSEC</name>
+                        <description>Non-secure lock status. Writes are OR&#39;d with the current value.</description>
+                        <bitRange>[3:2]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>SEC</name>
+                        <description>Secure lock status. Writes are OR&#39;d with the current value. This field is read-only to Non-secure code.</description>
+                        <bitRange>[1:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SW_LOCK33</name>
+                <addressOffset>0x00000084</addressOffset>
+                <description>Software lock register for page 33.
+
+                    Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>NSEC</name>
+                        <description>Non-secure lock status. Writes are OR&#39;d with the current value.</description>
+                        <bitRange>[3:2]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>SEC</name>
+                        <description>Secure lock status. Writes are OR&#39;d with the current value. This field is read-only to Non-secure code.</description>
+                        <bitRange>[1:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SW_LOCK34</name>
+                <addressOffset>0x00000088</addressOffset>
+                <description>Software lock register for page 34.
+
+                    Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>NSEC</name>
+                        <description>Non-secure lock status. Writes are OR&#39;d with the current value.</description>
+                        <bitRange>[3:2]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>SEC</name>
+                        <description>Secure lock status. Writes are OR&#39;d with the current value. This field is read-only to Non-secure code.</description>
+                        <bitRange>[1:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SW_LOCK35</name>
+                <addressOffset>0x0000008c</addressOffset>
+                <description>Software lock register for page 35.
+
+                    Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>NSEC</name>
+                        <description>Non-secure lock status. Writes are OR&#39;d with the current value.</description>
+                        <bitRange>[3:2]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>SEC</name>
+                        <description>Secure lock status. Writes are OR&#39;d with the current value. This field is read-only to Non-secure code.</description>
+                        <bitRange>[1:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SW_LOCK36</name>
+                <addressOffset>0x00000090</addressOffset>
+                <description>Software lock register for page 36.
+
+                    Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>NSEC</name>
+                        <description>Non-secure lock status. Writes are OR&#39;d with the current value.</description>
+                        <bitRange>[3:2]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>SEC</name>
+                        <description>Secure lock status. Writes are OR&#39;d with the current value. This field is read-only to Non-secure code.</description>
+                        <bitRange>[1:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SW_LOCK37</name>
+                <addressOffset>0x00000094</addressOffset>
+                <description>Software lock register for page 37.
+
+                    Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>NSEC</name>
+                        <description>Non-secure lock status. Writes are OR&#39;d with the current value.</description>
+                        <bitRange>[3:2]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>SEC</name>
+                        <description>Secure lock status. Writes are OR&#39;d with the current value. This field is read-only to Non-secure code.</description>
+                        <bitRange>[1:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SW_LOCK38</name>
+                <addressOffset>0x00000098</addressOffset>
+                <description>Software lock register for page 38.
+
+                    Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>NSEC</name>
+                        <description>Non-secure lock status. Writes are OR&#39;d with the current value.</description>
+                        <bitRange>[3:2]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>SEC</name>
+                        <description>Secure lock status. Writes are OR&#39;d with the current value. This field is read-only to Non-secure code.</description>
+                        <bitRange>[1:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SW_LOCK39</name>
+                <addressOffset>0x0000009c</addressOffset>
+                <description>Software lock register for page 39.
+
+                    Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>NSEC</name>
+                        <description>Non-secure lock status. Writes are OR&#39;d with the current value.</description>
+                        <bitRange>[3:2]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>SEC</name>
+                        <description>Secure lock status. Writes are OR&#39;d with the current value. This field is read-only to Non-secure code.</description>
+                        <bitRange>[1:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SW_LOCK40</name>
+                <addressOffset>0x000000a0</addressOffset>
+                <description>Software lock register for page 40.
+
+                    Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>NSEC</name>
+                        <description>Non-secure lock status. Writes are OR&#39;d with the current value.</description>
+                        <bitRange>[3:2]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>SEC</name>
+                        <description>Secure lock status. Writes are OR&#39;d with the current value. This field is read-only to Non-secure code.</description>
+                        <bitRange>[1:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SW_LOCK41</name>
+                <addressOffset>0x000000a4</addressOffset>
+                <description>Software lock register for page 41.
+
+                    Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>NSEC</name>
+                        <description>Non-secure lock status. Writes are OR&#39;d with the current value.</description>
+                        <bitRange>[3:2]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>SEC</name>
+                        <description>Secure lock status. Writes are OR&#39;d with the current value. This field is read-only to Non-secure code.</description>
+                        <bitRange>[1:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SW_LOCK42</name>
+                <addressOffset>0x000000a8</addressOffset>
+                <description>Software lock register for page 42.
+
+                    Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>NSEC</name>
+                        <description>Non-secure lock status. Writes are OR&#39;d with the current value.</description>
+                        <bitRange>[3:2]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>SEC</name>
+                        <description>Secure lock status. Writes are OR&#39;d with the current value. This field is read-only to Non-secure code.</description>
+                        <bitRange>[1:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SW_LOCK43</name>
+                <addressOffset>0x000000ac</addressOffset>
+                <description>Software lock register for page 43.
+
+                    Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>NSEC</name>
+                        <description>Non-secure lock status. Writes are OR&#39;d with the current value.</description>
+                        <bitRange>[3:2]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>SEC</name>
+                        <description>Secure lock status. Writes are OR&#39;d with the current value. This field is read-only to Non-secure code.</description>
+                        <bitRange>[1:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SW_LOCK44</name>
+                <addressOffset>0x000000b0</addressOffset>
+                <description>Software lock register for page 44.
+
+                    Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>NSEC</name>
+                        <description>Non-secure lock status. Writes are OR&#39;d with the current value.</description>
+                        <bitRange>[3:2]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>SEC</name>
+                        <description>Secure lock status. Writes are OR&#39;d with the current value. This field is read-only to Non-secure code.</description>
+                        <bitRange>[1:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SW_LOCK45</name>
+                <addressOffset>0x000000b4</addressOffset>
+                <description>Software lock register for page 45.
+
+                    Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>NSEC</name>
+                        <description>Non-secure lock status. Writes are OR&#39;d with the current value.</description>
+                        <bitRange>[3:2]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>SEC</name>
+                        <description>Secure lock status. Writes are OR&#39;d with the current value. This field is read-only to Non-secure code.</description>
+                        <bitRange>[1:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SW_LOCK46</name>
+                <addressOffset>0x000000b8</addressOffset>
+                <description>Software lock register for page 46.
+
+                    Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>NSEC</name>
+                        <description>Non-secure lock status. Writes are OR&#39;d with the current value.</description>
+                        <bitRange>[3:2]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>SEC</name>
+                        <description>Secure lock status. Writes are OR&#39;d with the current value. This field is read-only to Non-secure code.</description>
+                        <bitRange>[1:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SW_LOCK47</name>
+                <addressOffset>0x000000bc</addressOffset>
+                <description>Software lock register for page 47.
+
+                    Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>NSEC</name>
+                        <description>Non-secure lock status. Writes are OR&#39;d with the current value.</description>
+                        <bitRange>[3:2]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>SEC</name>
+                        <description>Secure lock status. Writes are OR&#39;d with the current value. This field is read-only to Non-secure code.</description>
+                        <bitRange>[1:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SW_LOCK48</name>
+                <addressOffset>0x000000c0</addressOffset>
+                <description>Software lock register for page 48.
+
+                    Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>NSEC</name>
+                        <description>Non-secure lock status. Writes are OR&#39;d with the current value.</description>
+                        <bitRange>[3:2]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>SEC</name>
+                        <description>Secure lock status. Writes are OR&#39;d with the current value. This field is read-only to Non-secure code.</description>
+                        <bitRange>[1:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SW_LOCK49</name>
+                <addressOffset>0x000000c4</addressOffset>
+                <description>Software lock register for page 49.
+
+                    Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>NSEC</name>
+                        <description>Non-secure lock status. Writes are OR&#39;d with the current value.</description>
+                        <bitRange>[3:2]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>SEC</name>
+                        <description>Secure lock status. Writes are OR&#39;d with the current value. This field is read-only to Non-secure code.</description>
+                        <bitRange>[1:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SW_LOCK50</name>
+                <addressOffset>0x000000c8</addressOffset>
+                <description>Software lock register for page 50.
+
+                    Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>NSEC</name>
+                        <description>Non-secure lock status. Writes are OR&#39;d with the current value.</description>
+                        <bitRange>[3:2]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>SEC</name>
+                        <description>Secure lock status. Writes are OR&#39;d with the current value. This field is read-only to Non-secure code.</description>
+                        <bitRange>[1:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SW_LOCK51</name>
+                <addressOffset>0x000000cc</addressOffset>
+                <description>Software lock register for page 51.
+
+                    Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>NSEC</name>
+                        <description>Non-secure lock status. Writes are OR&#39;d with the current value.</description>
+                        <bitRange>[3:2]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>SEC</name>
+                        <description>Secure lock status. Writes are OR&#39;d with the current value. This field is read-only to Non-secure code.</description>
+                        <bitRange>[1:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SW_LOCK52</name>
+                <addressOffset>0x000000d0</addressOffset>
+                <description>Software lock register for page 52.
+
+                    Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>NSEC</name>
+                        <description>Non-secure lock status. Writes are OR&#39;d with the current value.</description>
+                        <bitRange>[3:2]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>SEC</name>
+                        <description>Secure lock status. Writes are OR&#39;d with the current value. This field is read-only to Non-secure code.</description>
+                        <bitRange>[1:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SW_LOCK53</name>
+                <addressOffset>0x000000d4</addressOffset>
+                <description>Software lock register for page 53.
+
+                    Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>NSEC</name>
+                        <description>Non-secure lock status. Writes are OR&#39;d with the current value.</description>
+                        <bitRange>[3:2]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>SEC</name>
+                        <description>Secure lock status. Writes are OR&#39;d with the current value. This field is read-only to Non-secure code.</description>
+                        <bitRange>[1:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SW_LOCK54</name>
+                <addressOffset>0x000000d8</addressOffset>
+                <description>Software lock register for page 54.
+
+                    Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>NSEC</name>
+                        <description>Non-secure lock status. Writes are OR&#39;d with the current value.</description>
+                        <bitRange>[3:2]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>SEC</name>
+                        <description>Secure lock status. Writes are OR&#39;d with the current value. This field is read-only to Non-secure code.</description>
+                        <bitRange>[1:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SW_LOCK55</name>
+                <addressOffset>0x000000dc</addressOffset>
+                <description>Software lock register for page 55.
+
+                    Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>NSEC</name>
+                        <description>Non-secure lock status. Writes are OR&#39;d with the current value.</description>
+                        <bitRange>[3:2]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>SEC</name>
+                        <description>Secure lock status. Writes are OR&#39;d with the current value. This field is read-only to Non-secure code.</description>
+                        <bitRange>[1:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SW_LOCK56</name>
+                <addressOffset>0x000000e0</addressOffset>
+                <description>Software lock register for page 56.
+
+                    Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>NSEC</name>
+                        <description>Non-secure lock status. Writes are OR&#39;d with the current value.</description>
+                        <bitRange>[3:2]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>SEC</name>
+                        <description>Secure lock status. Writes are OR&#39;d with the current value. This field is read-only to Non-secure code.</description>
+                        <bitRange>[1:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SW_LOCK57</name>
+                <addressOffset>0x000000e4</addressOffset>
+                <description>Software lock register for page 57.
+
+                    Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>NSEC</name>
+                        <description>Non-secure lock status. Writes are OR&#39;d with the current value.</description>
+                        <bitRange>[3:2]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>SEC</name>
+                        <description>Secure lock status. Writes are OR&#39;d with the current value. This field is read-only to Non-secure code.</description>
+                        <bitRange>[1:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SW_LOCK58</name>
+                <addressOffset>0x000000e8</addressOffset>
+                <description>Software lock register for page 58.
+
+                    Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>NSEC</name>
+                        <description>Non-secure lock status. Writes are OR&#39;d with the current value.</description>
+                        <bitRange>[3:2]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>SEC</name>
+                        <description>Secure lock status. Writes are OR&#39;d with the current value. This field is read-only to Non-secure code.</description>
+                        <bitRange>[1:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SW_LOCK59</name>
+                <addressOffset>0x000000ec</addressOffset>
+                <description>Software lock register for page 59.
+
+                    Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>NSEC</name>
+                        <description>Non-secure lock status. Writes are OR&#39;d with the current value.</description>
+                        <bitRange>[3:2]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>SEC</name>
+                        <description>Secure lock status. Writes are OR&#39;d with the current value. This field is read-only to Non-secure code.</description>
+                        <bitRange>[1:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SW_LOCK60</name>
+                <addressOffset>0x000000f0</addressOffset>
+                <description>Software lock register for page 60.
+
+                    Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>NSEC</name>
+                        <description>Non-secure lock status. Writes are OR&#39;d with the current value.</description>
+                        <bitRange>[3:2]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>SEC</name>
+                        <description>Secure lock status. Writes are OR&#39;d with the current value. This field is read-only to Non-secure code.</description>
+                        <bitRange>[1:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SW_LOCK61</name>
+                <addressOffset>0x000000f4</addressOffset>
+                <description>Software lock register for page 61.
+
+                    Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>NSEC</name>
+                        <description>Non-secure lock status. Writes are OR&#39;d with the current value.</description>
+                        <bitRange>[3:2]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>SEC</name>
+                        <description>Secure lock status. Writes are OR&#39;d with the current value. This field is read-only to Non-secure code.</description>
+                        <bitRange>[1:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SW_LOCK62</name>
+                <addressOffset>0x000000f8</addressOffset>
+                <description>Software lock register for page 62.
+
+                    Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>NSEC</name>
+                        <description>Non-secure lock status. Writes are OR&#39;d with the current value.</description>
+                        <bitRange>[3:2]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>SEC</name>
+                        <description>Secure lock status. Writes are OR&#39;d with the current value. This field is read-only to Non-secure code.</description>
+                        <bitRange>[1:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SW_LOCK63</name>
+                <addressOffset>0x000000fc</addressOffset>
+                <description>Software lock register for page 63.
+
+                    Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>NSEC</name>
+                        <description>Non-secure lock status. Writes are OR&#39;d with the current value.</description>
+                        <bitRange>[3:2]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>SEC</name>
+                        <description>Secure lock status. Writes are OR&#39;d with the current value. This field is read-only to Non-secure code.</description>
+                        <bitRange>[1:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SBPI_INSTR</name>
+                <addressOffset>0x00000100</addressOffset>
+                <description>Dispatch instructions to the SBPI interface, used for programming the OTP fuses.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>EXEC</name>
+                        <description>Execute instruction</description>
+                        <bitRange>[30:30]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>IS_WR</name>
+                        <description>Payload type is write</description>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>HAS_PAYLOAD</name>
+                        <description>Instruction has payload (data to be written or to be read)</description>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PAYLOAD_SIZE_M1</name>
+                        <description>Instruction payload size in bytes minus 1</description>
+                        <bitRange>[27:24]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>TARGET</name>
+                        <description>Instruction target, it can be PMC (0x3a) or DAP (0x02)</description>
+                        <bitRange>[23:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CMD</name>
+                        <bitRange>[15:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SHORT_WDATA</name>
+                        <description>wdata to be used only when payload_size_m1=0</description>
+                        <bitRange>[7:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SBPI_WDATA_0</name>
+                <addressOffset>0x00000104</addressOffset>
+                <description>SBPI write payload bytes 3..0</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>SBPI_WDATA_0</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SBPI_WDATA_1</name>
+                <addressOffset>0x00000108</addressOffset>
+                <description>SBPI write payload bytes 7..4</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>SBPI_WDATA_1</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SBPI_WDATA_2</name>
+                <addressOffset>0x0000010c</addressOffset>
+                <description>SBPI write payload bytes 11..8</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>SBPI_WDATA_2</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SBPI_WDATA_3</name>
+                <addressOffset>0x00000110</addressOffset>
+                <description>SBPI write payload bytes 15..12</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>SBPI_WDATA_3</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SBPI_RDATA_0</name>
+                <addressOffset>0x00000114</addressOffset>
+                <description>Read payload bytes 3..0. Once read, the data in the register will automatically clear to 0.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>SBPI_RDATA_0</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-only</access>
+                        <readAction>modify</readAction>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SBPI_RDATA_1</name>
+                <addressOffset>0x00000118</addressOffset>
+                <description>Read payload bytes 7..4. Once read, the data in the register will automatically clear to 0.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>SBPI_RDATA_1</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-only</access>
+                        <readAction>modify</readAction>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SBPI_RDATA_2</name>
+                <addressOffset>0x0000011c</addressOffset>
+                <description>Read payload bytes 11..8. Once read, the data in the register will automatically clear to 0.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>SBPI_RDATA_2</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-only</access>
+                        <readAction>modify</readAction>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SBPI_RDATA_3</name>
+                <addressOffset>0x00000120</addressOffset>
+                <description>Read payload bytes 15..12. Once read, the data in the register will automatically clear to 0.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>SBPI_RDATA_3</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>read-only</access>
+                        <readAction>modify</readAction>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SBPI_STATUS</name>
+                <addressOffset>0x00000124</addressOffset>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>MISO</name>
+                        <description>SBPI MISO (master in - slave out): response from SBPI</description>
+                        <bitRange>[23:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>FLAG</name>
+                        <description>SBPI flag</description>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>INSTR_MISS</name>
+                        <description>Last instruction missed (dropped), as the previous has not finished running</description>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>INSTR_DONE</name>
+                        <description>Last instruction done</description>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>RDATA_VLD</name>
+                        <description>Read command has returned data</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>USR</name>
+                <addressOffset>0x00000128</addressOffset>
+                <description>Controls for APB data read interface (USER interface)</description>
+                <resetValue>0x00000001</resetValue>
+                <fields>
+                    <field>
+                        <name>PD</name>
+                        <description>Power-down; 1 disables current reference. Must be 0 to read data from the OTP.</description>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DCTRL</name>
+                        <description>1 enables USER interface; 0 disables USER interface (enables SBPI).
+
+                            This bit must be cleared before performing any SBPI access, such as when programming the OTP. The APB data read interface (USER interface) will be inaccessible during this time, and will return a bus error if any read is attempted.</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>DBG</name>
+                <addressOffset>0x0000012c</addressOffset>
+                <description>Debug for OTP power-on state machine</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CUSTOMER_RMA_FLAG</name>
+                        <description>The chip is in RMA mode</description>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>PSM_STATE</name>
+                        <description>Monitor the PSM FSM&#39;s state</description>
+                        <bitRange>[7:4]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>ROSC_UP</name>
+                        <description>Ring oscillator is up and running</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>ROSC_UP_SEEN</name>
+                        <description>Ring oscillator was seen up and running</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>BOOT_DONE</name>
+                        <description>PSM boot done status flag</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>PSM_DONE</name>
+                        <description>PSM done status flag</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>BIST</name>
+                <addressOffset>0x00000134</addressOffset>
+                <description>During BIST, count address locations that have at least one leaky bit</description>
+                <resetValue>0x0fff0000</resetValue>
+                <fields>
+                    <field>
+                        <name>CNT_FAIL</name>
+                        <description>Flag if the count of address locations with at least one leaky bit exceeds cnt_max</description>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CNT_CLR</name>
+                        <description>Clear counter before use</description>
+                        <bitRange>[29:29]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                    <field>
+                        <name>CNT_ENA</name>
+                        <description>Enable the counter before the BIST function is initiated</description>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CNT_MAX</name>
+                        <description>The cnt_fail flag will be set if the number of leaky locations exceeds this number</description>
+                        <bitRange>[27:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>CNT</name>
+                        <description>Number of locations that have at least one leaky bit. Note: This count is true only if the BIST was initiated without the fix option.</description>
+                        <bitRange>[12:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CRT_KEY_W0</name>
+                <addressOffset>0x00000138</addressOffset>
+                <description>Word 0 (bits 31..0) of the key. Write only, read returns 0x0</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CRT_KEY_W0</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CRT_KEY_W1</name>
+                <addressOffset>0x0000013c</addressOffset>
+                <description>Word 1 (bits 63..32) of the key. Write only, read returns 0x0</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CRT_KEY_W1</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CRT_KEY_W2</name>
+                <addressOffset>0x00000140</addressOffset>
+                <description>Word 2 (bits 95..64) of the key. Write only, read returns 0x0</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CRT_KEY_W2</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CRT_KEY_W3</name>
+                <addressOffset>0x00000144</addressOffset>
+                <description>Word 3 (bits 127..96) of the key. Write only, read returns 0x0</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CRT_KEY_W3</name>
+                        <bitRange>[31:0]</bitRange>
+                        <access>write-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CRITICAL</name>
+                <addressOffset>0x00000148</addressOffset>
+                <description>Quickly check values of critical flags read during boot up</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>RISCV_DISABLE</name>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>ARM_DISABLE</name>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GLITCH_DETECTOR_SENS</name>
+                        <bitRange>[6:5]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GLITCH_DETECTOR_ENABLE</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>DEFAULT_ARCHSEL</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>DEBUG_DISABLE</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SECURE_DEBUG_DISABLE</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SECURE_BOOT_ENABLE</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>KEY_VALID</name>
+                <addressOffset>0x0000014c</addressOffset>
+                <description>Which keys were valid (enrolled) at boot time</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>KEY_VALID</name>
+                        <bitRange>[7:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>DEBUGEN</name>
+                <addressOffset>0x00000150</addressOffset>
+                <description>Enable a debug feature that has been disabled. Debug features are disabled if one of the relevant critical boot flags is set in OTP (DEBUG_DISABLE or SECURE_DEBUG_DISABLE), OR if a debug key is marked valid in OTP, and the matching key value has not been supplied over SWD.
+
+                    Specifically:
+
+                    - The DEBUG_DISABLE flag disables all debug features. This can be fully overridden by setting all bits of this register.
+
+                    - The SECURE_DEBUG_DISABLE flag disables secure processor debug. This can be fully overridden by setting the PROC0_SECURE and PROC1_SECURE bits of this register.
+
+                    - If a single debug key has been registered, and no matching key value has been supplied over SWD, then all debug features are disabled. This can be fully overridden by setting all bits of this register.
+
+                    - If both debug keys have been registered, and the Non-secure key&#39;s value (key 6) has been supplied over SWD, secure processor debug is disabled. This can be fully overridden by setting the PROC0_SECURE and PROC1_SECURE bits of this register.
+
+                    - If both debug keys have been registered, and the Secure key&#39;s value (key 5) has been supplied over SWD, then no debug features are disabled by the key mechanism. However, note that in this case debug features may still be disabled by the critical boot flags.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>MISC</name>
+                        <description>Enable other debug components. Specifically, the CTI, and the APB-AP used to access the RISC-V Debug Module.
+
+                            These components are disabled by default if either of the debug disable critical flags is set, or if at least one debug key has been enrolled and the least secure of these enrolled key values has not been provided over SWD.</description>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PROC1_SECURE</name>
+                        <description>Permit core 1&#39;s Mem-AP to generate Secure accesses, assuming it is enabled at all. Also enable secure debug of core 1 (SPIDEN and SPNIDEN).
+
+                            Secure debug of core 1 is disabled by default if the secure debug disable critical flag is set, or if at least one debug key has been enrolled and the most secure of these enrolled key values not yet provided over SWD.</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PROC1</name>
+                        <description>Enable core 1&#39;s Mem-AP if it is currently disabled.
+
+                            The Mem-AP is disabled by default if either of the debug disable critical flags is set, or if at least one debug key has been enrolled and the least secure of these enrolled key values has not been provided over SWD.</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PROC0_SECURE</name>
+                        <description>Permit core 0&#39;s Mem-AP to generate Secure accesses, assuming it is enabled at all. Also enable secure debug of core 0 (SPIDEN and SPNIDEN).
+
+                            Secure debug of core 0 is disabled by default if the secure debug disable critical flag is set, or if at least one debug key has been enrolled and the most secure of these enrolled key values not yet provided over SWD.
+
+                            Note also that core Mem-APs are unconditionally disabled when a core is switched to RISC-V mode (by setting the ARCHSEL bit and performing a warm reset of the core).</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PROC0</name>
+                        <description>Enable core 0&#39;s Mem-AP if it is currently disabled.
+
+                            The Mem-AP is disabled by default if either of the debug disable critical flags is set, or if at least one debug key has been enrolled and the least secure of these enrolled key values has not been provided over SWD.
+
+                            Note also that core Mem-APs are unconditionally disabled when a core is switched to RISC-V mode (by setting the ARCHSEL bit and performing a warm reset of the core).</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>DEBUGEN_LOCK</name>
+                <addressOffset>0x00000154</addressOffset>
+                <description>Write 1s to lock corresponding bits in DEBUGEN. This register is reset by the processor cold reset.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>MISC</name>
+                        <description>Write 1 to lock the MISC bit of DEBUGEN. Can&#39;t be cleared once set.</description>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PROC1_SECURE</name>
+                        <description>Write 1 to lock the PROC1_SECURE bit of DEBUGEN. Can&#39;t be cleared once set.</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PROC1</name>
+                        <description>Write 1 to lock the PROC1 bit of DEBUGEN. Can&#39;t be cleared once set.</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PROC0_SECURE</name>
+                        <description>Write 1 to lock the PROC0_SECURE bit of DEBUGEN. Can&#39;t be cleared once set.</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PROC0</name>
+                        <description>Write 1 to lock the PROC0 bit of DEBUGEN. Can&#39;t be cleared once set.</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>ARCHSEL</name>
+                <addressOffset>0x00000158</addressOffset>
+                <description>Architecture select (Arm/RISC-V). The default and allowable values of this register are constrained by the critical boot flags.
+
+                    This register is reset by the earliest reset in the switched core power domain (before a processor cold reset).
+
+                    Cores sample their architecture select signal on a warm reset. The source of the warm reset could be the system power-up state machine, the watchdog timer, Arm SYSRESETREQ or from RISC-V hartresetreq.
+
+                    Note that when an Arm core is deselected, its cold reset domain is also held in reset, since in particular the SYSRESETREQ bit becomes inaccessible once the core is deselected. Note also the RISC-V cores do not have a cold reset domain, since their corresponding controls are located in the Debug Module.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CORE1</name>
+                        <description>Select architecture for core 1.</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>arm</name>
+                                <value>0</value>
+                                <description>Switch core 1 to Arm (Cortex-M33)</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>riscv</name>
+                                <value>1</value>
+                                <description>Switch core 1 to RISC-V (Hazard3)</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>CORE0</name>
+                        <description>Select architecture for core 0.</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>arm</name>
+                                <value>0</value>
+                                <description>Switch core 0 to Arm (Cortex-M33)</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>riscv</name>
+                                <value>1</value>
+                                <description>Switch core 0 to RISC-V (Hazard3)</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>ARCHSEL_STATUS</name>
+                <addressOffset>0x0000015c</addressOffset>
+                <description>Get the current architecture select state of each core. Cores sample the current value of the ARCHSEL register when their warm reset is released, at which point the corresponding bit in this register will also update.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CORE1</name>
+                        <description>Current architecture for core 0. Updated on processor warm reset.</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>arm</name>
+                                <value>0</value>
+                                <description>Core 1 is currently Arm (Cortex-M33)</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>riscv</name>
+                                <value>1</value>
+                                <description>Core 1 is currently RISC-V (Hazard3)</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>CORE0</name>
+                        <description>Current architecture for core 0. Updated on processor warm reset.</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>arm</name>
+                                <value>0</value>
+                                <description>Core 0 is currently Arm (Cortex-M33)</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>riscv</name>
+                                <value>1</value>
+                                <description>Core 0 is currently RISC-V (Hazard3)</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>BOOTDIS</name>
+                <addressOffset>0x00000160</addressOffset>
+                <description>Tell the bootrom to ignore scratch register boot vectors (both power manager and watchdog) on the next power up.
+
+                    If an early boot stage has soft-locked some OTP pages in order to protect their contents from later stages, there is a risk that Secure code running at a later stage can unlock the pages by performing a watchdog reset that resets the OTP.
+
+                    This register can be used to ensure that the bootloader runs as normal on the next power up, preventing Secure code at a later stage from accessing OTP in its unlocked state.
+
+                    Should be used in conjunction with the power manager BOOTDIS register.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>NEXT</name>
+                        <description>This flag always ORs writes into its current contents. It can be set but not cleared by software.
+
+                            The BOOTDIS_NEXT bit is OR&#39;d into the BOOTDIS_NOW bit when the core is powered down. Simultaneously, the BOOTDIS_NEXT bit is cleared. Setting this bit means that the boot scratch registers will be ignored following the next core power down.
+
+                            This flag should be set by an early boot stage that has soft-locked OTP pages, to prevent later stages from unlocking it via watchdog reset.</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>NOW</name>
+                        <description>When the core is powered down, the current value of BOOTDIS_NEXT is OR&#39;d into BOOTDIS_NOW, and BOOTDIS_NEXT is cleared.
+
+                            The bootrom checks this flag before reading the boot scratch registers. If it is set, the bootrom clears it, and ignores the BOOT registers. This prevents Secure software from diverting the boot path before a bootloader has had the chance to soft lock OTP pages containing sensitive data.</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INTR</name>
+                <addressOffset>0x00000164</addressOffset>
+                <description>Raw Interrupts</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>APB_RD_NSEC_FAIL</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>APB_RD_SEC_FAIL</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>APB_DCTRL_FAIL</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>SBPI_WR_FAIL</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+                    </field>
+                    <field>
+                        <name>SBPI_FLAG_N</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INTE</name>
+                <addressOffset>0x00000168</addressOffset>
+                <description>Interrupt Enable</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>APB_RD_NSEC_FAIL</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>APB_RD_SEC_FAIL</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>APB_DCTRL_FAIL</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SBPI_WR_FAIL</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SBPI_FLAG_N</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INTF</name>
+                <addressOffset>0x0000016c</addressOffset>
+                <description>Interrupt Force</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>APB_RD_NSEC_FAIL</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>APB_RD_SEC_FAIL</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>APB_DCTRL_FAIL</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SBPI_WR_FAIL</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>SBPI_FLAG_N</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INTS</name>
+                <addressOffset>0x00000170</addressOffset>
+                <description>Interrupt status after masking &amp; forcing</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>APB_RD_NSEC_FAIL</name>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>APB_RD_SEC_FAIL</name>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>APB_DCTRL_FAIL</name>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SBPI_WR_FAIL</name>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SBPI_FLAG_N</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+        </registers>
+    </peripheral>
+    <peripheral>
+        <name>OTP_DATA</name>
+        <description>Predefined OTP data layout for RP2350</description>
+        <baseAddress>0x40130000</baseAddress>
+        <addressBlock>
+            <offset>0</offset>
+            <size>7920</size>
+            <usage>registers</usage>
+        </addressBlock>
+        <registers>
+            <register>
+                <name>CHIPID0</name>
+                <addressOffset>0x0000</addressOffset>
+                <description>Bits 15:0 of public device ID. (ECC)
+
+                    The CHIPID0..3 rows contain a 64-bit random identifier for this chip, which can be read from the USB bootloader PICOBOOT interface or from the get_sys_info ROM API.
+
+                    The number of random bits makes the occurrence of twins exceedingly unlikely: for example, a fleet of a hundred million devices has a 99.97% probability of no twinned IDs. This is estimated to be lower than the occurrence of process errors in the assignment of sequential random IDs, and for practical purposes CHIPID may be treated as unique.</description>
+                <size>16</size>
+                <resetMask>0x0000</resetMask>
+                <fields>
+                    <field>
+                        <name>CHIPID0</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CHIPID1</name>
+                <addressOffset>0x0002</addressOffset>
+                <description>Bits 31:16 of public device ID (ECC)</description>
+                <size>16</size>
+                <resetMask>0x0000</resetMask>
+                <fields>
+                    <field>
+                        <name>CHIPID1</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CHIPID2</name>
+                <addressOffset>0x0004</addressOffset>
+                <description>Bits 47:32 of public device ID (ECC)</description>
+                <size>16</size>
+                <resetMask>0x0000</resetMask>
+                <fields>
+                    <field>
+                        <name>CHIPID2</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CHIPID3</name>
+                <addressOffset>0x0006</addressOffset>
+                <description>Bits 63:48 of public device ID (ECC)</description>
+                <size>16</size>
+                <resetMask>0x0000</resetMask>
+                <fields>
+                    <field>
+                        <name>CHIPID3</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>RANDID0</name>
+                <addressOffset>0x0008</addressOffset>
+                <description>Bits 15:0 of private per-device random number (ECC)
+
+                    The RANDID0..7 rows form a 128-bit random number generated during device test.
+
+                    This ID is not exposed through the USB PICOBOOT GET_INFO command or the ROM `get_sys_info()` API. However note that the USB PICOBOOT OTP access point can read the entirety of page 0, so this value is not meaningfully private unless the USB PICOBOOT interface is disabled via the DISABLE_BOOTSEL_USB_PICOBOOT_IFC flag in BOOT_FLAGS0.</description>
+                <size>16</size>
+                <resetMask>0x0000</resetMask>
+                <fields>
+                    <field>
+                        <name>RANDID0</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>RANDID1</name>
+                <addressOffset>0x000a</addressOffset>
+                <description>Bits 31:16 of private per-device random number (ECC)</description>
+                <size>16</size>
+                <resetMask>0x0000</resetMask>
+                <fields>
+                    <field>
+                        <name>RANDID1</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>RANDID2</name>
+                <addressOffset>0x000c</addressOffset>
+                <description>Bits 47:32 of private per-device random number (ECC)</description>
+                <size>16</size>
+                <resetMask>0x0000</resetMask>
+                <fields>
+                    <field>
+                        <name>RANDID2</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>RANDID3</name>
+                <addressOffset>0x000e</addressOffset>
+                <description>Bits 63:48 of private per-device random number (ECC)</description>
+                <size>16</size>
+                <resetMask>0x0000</resetMask>
+                <fields>
+                    <field>
+                        <name>RANDID3</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>RANDID4</name>
+                <addressOffset>0x0010</addressOffset>
+                <description>Bits 79:64 of private per-device random number (ECC)</description>
+                <size>16</size>
+                <resetMask>0x0000</resetMask>
+                <fields>
+                    <field>
+                        <name>RANDID4</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>RANDID5</name>
+                <addressOffset>0x0012</addressOffset>
+                <description>Bits 95:80 of private per-device random number (ECC)</description>
+                <size>16</size>
+                <resetMask>0x0000</resetMask>
+                <fields>
+                    <field>
+                        <name>RANDID5</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>RANDID6</name>
+                <addressOffset>0x0014</addressOffset>
+                <description>Bits 111:96 of private per-device random number (ECC)</description>
+                <size>16</size>
+                <resetMask>0x0000</resetMask>
+                <fields>
+                    <field>
+                        <name>RANDID6</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>RANDID7</name>
+                <addressOffset>0x0016</addressOffset>
+                <description>Bits 127:112 of private per-device random number (ECC)</description>
+                <size>16</size>
+                <resetMask>0x0000</resetMask>
+                <fields>
+                    <field>
+                        <name>RANDID7</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>ROSC_CALIB</name>
+                <addressOffset>0x0020</addressOffset>
+                <description>Ring oscillator frequency in kHz, measured during manufacturing (ECC)
+
+                    This is measured at 1.1 V, at room temperature, with the ROSC configuration registers in their reset state.</description>
+                <size>16</size>
+                <resetMask>0x0000</resetMask>
+                <fields>
+                    <field>
+                        <name>ROSC_CALIB</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>LPOSC_CALIB</name>
+                <addressOffset>0x0022</addressOffset>
+                <description>Low-power oscillator frequency in Hz, measured during manufacturing (ECC)
+
+                    This is measured at 1.1V, at room temperature, with the LPOSC trim register in its reset state.</description>
+                <size>16</size>
+                <resetMask>0x0000</resetMask>
+                <fields>
+                    <field>
+                        <name>LPOSC_CALIB</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>NUM_GPIOS</name>
+                <addressOffset>0x0030</addressOffset>
+                <description>The number of main user GPIOs (bank 0). Should read 48 in the QFN80 package, and 30 in the QFN60 package. (ECC)</description>
+                <size>16</size>
+                <resetMask>0x0000</resetMask>
+                <fields>
+                    <field>
+                        <name>NUM_GPIOS</name>
+                        <bitRange>[7:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INFO_CRC0</name>
+                <addressOffset>0x006c</addressOffset>
+                <description>Lower 16 bits of CRC32 of OTP addresses 0x00 through 0x6b (polynomial 0x4c11db7, input reflected, output reflected, seed all-ones, final XOR all-ones) (ECC)</description>
+                <size>16</size>
+                <resetMask>0x0000</resetMask>
+                <fields>
+                    <field>
+                        <name>INFO_CRC0</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INFO_CRC1</name>
+                <addressOffset>0x006e</addressOffset>
+                <description>Upper 16 bits of CRC32 of OTP addresses 0x00 through 0x6b (ECC)</description>
+                <size>16</size>
+                <resetMask>0x0000</resetMask>
+                <fields>
+                    <field>
+                        <name>INFO_CRC1</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>FLASH_DEVINFO</name>
+                <addressOffset>0x00a8</addressOffset>
+                <description>Stores information about external flash device(s). (ECC)
+
+                    Assumed to be valid if BOOT_FLAGS0_FLASH_DEVINFO_ENABLE is set.</description>
+                <size>16</size>
+                <resetValue>0x0000</resetValue>
+                <fields>
+                    <field>
+                        <name>CS1_SIZE</name>
+                        <description>The size of the flash/PSRAM device on chip select 1 (addressable at 0x11000000 through 0x11ffffff).
+
+                            A value of zero is decoded as a size of zero (no device). Nonzero values are decoded as 4kiB &lt;&lt; CS1_SIZE. For example, four megabytes is encoded with a CS1_SIZE value of 10, and 16 megabytes is encoded with a CS1_SIZE value of 12.
+
+                            When BOOT_FLAGS0_FLASH_DEVINFO_ENABLE is not set, a default of zero is used.</description>
+                        <bitRange>[15:12]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NONE</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>8K</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>16K</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>32K</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>64k</name>
+                                <value>4</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>128K</name>
+                                <value>5</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>256K</name>
+                                <value>6</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>512K</name>
+                                <value>7</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>1M</name>
+                                <value>8</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>2M</name>
+                                <value>9</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>4M</name>
+                                <value>10</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>8M</name>
+                                <value>11</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>16M</name>
+                                <value>12</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>CS0_SIZE</name>
+                        <description>The size of the flash/PSRAM device on chip select 0 (addressable at 0x10000000 through 0x10ffffff).
+
+                            A value of zero is decoded as a size of zero (no device). Nonzero values are decoded as 4kiB &lt;&lt; CS0_SIZE. For example, four megabytes is encoded with a CS0_SIZE value of 10, and 16 megabytes is encoded with a CS0_SIZE value of 12.
+
+                            When BOOT_FLAGS0_FLASH_DEVINFO_ENABLE is not set, a default of 12 (16 MiB) is used.</description>
+                        <bitRange>[11:8]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NONE</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>8K</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>16K</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>32K</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>64k</name>
+                                <value>4</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>128K</name>
+                                <value>5</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>256K</name>
+                                <value>6</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>512K</name>
+                                <value>7</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>1M</name>
+                                <value>8</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>2M</name>
+                                <value>9</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>4M</name>
+                                <value>10</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>8M</name>
+                                <value>11</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>16M</name>
+                                <value>12</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>D8H_ERASE_SUPPORTED</name>
+                        <description>If true, all attached devices are assumed to support (or ignore, in the case of PSRAM) a block erase command with a command prefix of D8h, an erase size of 64 kiB, and a 24-bit address. Almost all 25-series flash devices support this command.
+
+                            If set, the bootrom will use the D8h erase command where it is able, to accelerate bulk erase operations. This makes flash programming faster.
+
+                            When BOOT_FLAGS0_FLASH_DEVINFO_ENABLE is not set, this field defaults to false.</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CS1_GPIO</name>
+                        <description>Indicate a GPIO number to be used for the secondary flash chip select (CS1), which selects the external QSPI device mapped at system addresses 0x11000000 through 0x11ffffff. There is no such configuration for CS0, as the primary chip select has a dedicated pin.
+
+                            On RP2350 the permissible GPIO numbers are 0, 8, 19 and 47.
+
+                            Ignored if CS1_size is zero. If CS1_SIZE is nonzero, the bootrom will automatically configure this GPIO as a second chip select upon entering the flash boot path, or entering any other path that may use the QSPI flash interface, such as BOOTSEL mode (nsboot).</description>
+                        <bitRange>[5:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>FLASH_PARTITION_SLOT_SIZE</name>
+                <addressOffset>0x00aa</addressOffset>
+                <description>Gap between partition table slot 0 and slot 1 at the start of flash (the default size is 4096 bytes) (ECC) Enabled by the OVERRIDE_FLASH_PARTITION_SLOT_SIZE bit in BOOT_FLAGS, the size is 4096 * (value + 1)</description>
+                <size>16</size>
+                <resetMask>0x0000</resetMask>
+                <fields>
+                    <field>
+                        <name>FLASH_PARTITION_SLOT_SIZE</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>BOOTSEL_LED_CFG</name>
+                <addressOffset>0x00ac</addressOffset>
+                <description>Pin configuration for LED status, used by USB bootloader. (ECC) 
+                    Must be valid if BOOT_FLAGS0_ENABLE_BOOTSEL_LED is set.</description>
+                <size>16</size>
+                <resetValue>0x0000</resetValue>
+                <fields>
+                    <field>
+                        <name>ACTIVELOW</name>
+                        <description>LED is active-low. (Default: active-high.)</description>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>PIN</name>
+                        <description>GPIO index to use for bootloader activity LED.</description>
+                        <bitRange>[5:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>BOOTSEL_PLL_CFG</name>
+                <addressOffset>0x00ae</addressOffset>
+                <description>Optional PLL configuration for BOOTSEL mode. (ECC)
+
+                    This should be configured to produce an exact 48 MHz based on the crystal oscillator frequency. User mode software may also use this value to calculate the expected crystal frequency based on an assumed 48 MHz PLL output.
+
+                    If no configuration is given, the crystal is assumed to be 12 MHz.
+
+                    The PLL frequency can be calculated as:
+
+                    PLL out = (XOSC frequency / (REFDIV+1)) x FBDIV / (POSTDIV1 x POSTDIV2)
+
+                    Conversely the crystal frequency can be calculated as:
+
+                    XOSC frequency = 48 MHz x (REFDIV+1) x (POSTDIV1 x POSTDIV2) / FBDIV
+
+                    (Note the  +1 on REFDIV is because the value stored in this OTP location is the actual divisor value minus one.)
+
+                    Used if and only if ENABLE_BOOTSEL_NON_DEFAULT_PLL_XOSC_CFG is set in BOOT_FLAGS0. That bit should be set only after this row and BOOTSEL_XOSC_CFG are both correctly programmed.</description>
+                <size>16</size>
+                <resetValue>0x0000</resetValue>
+                <fields>
+                    <field>
+                        <name>REFDIV</name>
+                        <description>PLL reference divisor, minus one.
+
+                            Programming a value of 0 means a reference divisor of 1. Programming a value of 1 means a reference divisor of 2 (for exceptionally fast XIN inputs)</description>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>POSTDIV2</name>
+                        <description>PLL post-divide 2 divisor, in the range 1..7 inclusive.</description>
+                        <bitRange>[14:12]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>POSTDIV1</name>
+                        <description>PLL post-divide 1 divisor, in the range 1..7 inclusive.</description>
+                        <bitRange>[11:9]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>FBDIV</name>
+                        <description>PLL feedback divisor, in the range 16..320 inclusive.</description>
+                        <bitRange>[8:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>BOOTSEL_XOSC_CFG</name>
+                <addressOffset>0x00b0</addressOffset>
+                <description>Non-default crystal oscillator configuration for the USB bootloader. (ECC)
+
+                    These values may also be used by user code configuring the crystal oscillator.
+
+                    Used if and only if ENABLE_BOOTSEL_NON_DEFAULT_PLL_XOSC_CFG is set in BOOT_FLAGS0. That bit should be set only after this row and BOOTSEL_PLL_CFG are both correctly programmed.</description>
+                <size>16</size>
+                <resetValue>0x0000</resetValue>
+                <fields>
+                    <field>
+                        <name>RANGE</name>
+                        <description>Value of the XOSC_CTRL_FREQ_RANGE register.</description>
+                        <bitRange>[15:14]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>1_15MHZ</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>10_30MHZ</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>25_60MHZ</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>40_100MHZ</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>STARTUP</name>
+                        <description>Value of the XOSC_STARTUP register</description>
+                        <bitRange>[13:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>USB_WHITE_LABEL_ADDR</name>
+                <addressOffset>0x00b8</addressOffset>
+                <description>Row index of the USB_WHITE_LABEL structure within OTP (ECC)
+
+                    The table has 16 rows, each of which are also ECC and marked valid by the corresponding valid bit in USB_BOOT_FLAGS (ECC).
+
+                    The entries are either _VALUEs where the 16 bit value is used as is, or _STRDEFs which acts as a pointers to a string value.
+
+                    The value stored in a _STRDEF is two separate bytes: The low seven bits of the first (LSB) byte indicates the number of characters in the string, and the top bit of the first (LSB) byte if set to indicate that each character in the string is two bytes (Unicode) versus one byte if unset. The second (MSB) byte represents the location of the string data, and is encoded as the number of rows from this USB_WHITE_LABEL_ADDR; i.e. the row of the start of the string is USB_WHITE_LABEL_ADDR value + msb_byte.
+
+                    In each case, the corresponding valid bit enables replacing the default value for the corresponding item provided by the boot rom.
+
+                    Note that Unicode _STRDEFs are only supported for USB_DEVICE_PRODUCT_STRDEF, USB_DEVICE_SERIAL_NUMBER_STRDEF and USB_DEVICE_MANUFACTURER_STRDEF. Unicode values will be ignored if specified for other fields, and non-unicode values for these three items will be converted to Unicode characters by setting the upper 8 bits to zero.
+
+                    Note that if the USB_WHITE_LABEL structure or the corresponding strings are not readable by BOOTSEL mode based on OTP permissions, or if alignment requirements are not met, then the corresponding default values are used.
+
+                    The index values indicate where each field is located (row USB_WHITE_LABEL_ADDR value + index):</description>
+                <size>16</size>
+                <resetMask>0x0000</resetMask>
+                <fields>
+                    <field>
+                        <name>USB_WHITE_LABEL_ADDR</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>INDEX_USB_DEVICE_VID_VALUE</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INDEX_USB_DEVICE_PID_VALUE</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INDEX_USB_DEVICE_BCD_DEVICE_VALUE</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INDEX_USB_DEVICE_LANG_ID_VALUE</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INDEX_USB_DEVICE_MANUFACTURER_STRDEF</name>
+                                <value>4</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INDEX_USB_DEVICE_PRODUCT_STRDEF</name>
+                                <value>5</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INDEX_USB_DEVICE_SERIAL_NUMBER_STRDEF</name>
+                                <value>6</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INDEX_USB_CONFIG_ATTRIBUTES_MAX_POWER_VALUES</name>
+                                <value>7</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INDEX_VOLUME_LABEL_STRDEF</name>
+                                <value>8</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INDEX_SCSI_INQUIRY_VENDOR_STRDEF</name>
+                                <value>9</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INDEX_SCSI_INQUIRY_PRODUCT_STRDEF</name>
+                                <value>10</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INDEX_SCSI_INQUIRY_VERSION_STRDEF</name>
+                                <value>11</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INDEX_INDEX_HTM_REDIRECT_URL_STRDEF</name>
+                                <value>12</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INDEX_INDEX_HTM_REDIRECT_NAME_STRDEF</name>
+                                <value>13</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INDEX_INFO_UF2_TXT_MODEL_STRDEF</name>
+                                <value>14</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INDEX_INFO_UF2_TXT_BOARD_ID_STRDEF</name>
+                                <value>15</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>OTPBOOT_SRC</name>
+                <addressOffset>0x00bc</addressOffset>
+                <description>OTP start row for the OTP boot image. (ECC)
+
+                    If OTP boot is enabled, the bootrom will load from this location into SRAM and then directly enter the loaded image. Note that the image must be signed if SECURE_BOOT_ENABLE is set. The image itself is assumed to be ECC-protected.
+
+                    This must be an even number. Equivalently, the OTP boot image must start at a word-aligned location in the ECC read data address window.</description>
+                <size>16</size>
+                <resetMask>0x0000</resetMask>
+                <fields>
+                    <field>
+                        <name>OTPBOOT_SRC</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>OTPBOOT_LEN</name>
+                <addressOffset>0x00be</addressOffset>
+                <description>Length in rows of the OTP boot image. (ECC)
+
+                    OTPBOOT_LEN must be even. The total image size must be a multiple of 4 bytes (32 bits).</description>
+                <size>16</size>
+                <resetMask>0x0000</resetMask>
+                <fields>
+                    <field>
+                        <name>OTPBOOT_LEN</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>OTPBOOT_DST0</name>
+                <addressOffset>0x00c0</addressOffset>
+                <description>Bits 15:0 of the OTP boot image load destination (and entry point). (ECC)
+
+                    This must be a location in main SRAM (main SRAM is addresses 0x20000000 through 0x20082000) and must be word-aligned.</description>
+                <size>16</size>
+                <resetMask>0x0000</resetMask>
+                <fields>
+                    <field>
+                        <name>OTPBOOT_DST0</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>OTPBOOT_DST1</name>
+                <addressOffset>0x00c2</addressOffset>
+                <description>Bits 31:16 of the OTP boot image load destination (and entry point). (ECC)
+
+                    This must be a location in main SRAM (main SRAM is addresses 0x20000000 through 0x20082000) and must be word-aligned.</description>
+                <size>16</size>
+                <resetMask>0x0000</resetMask>
+                <fields>
+                    <field>
+                        <name>OTPBOOT_DST1</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>BOOTKEY0_0</name>
+                <addressOffset>0x0100</addressOffset>
+                <description>Bits 15:0 of SHA-256 hash of boot key 0 (ECC)</description>
+                <size>16</size>
+                <resetMask>0x0000</resetMask>
+                <fields>
+                    <field>
+                        <name>BOOTKEY0_0</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>BOOTKEY0_1</name>
+                <addressOffset>0x0102</addressOffset>
+                <description>Bits 31:16 of SHA-256 hash of boot key 0 (ECC)</description>
+                <size>16</size>
+                <resetMask>0x0000</resetMask>
+                <fields>
+                    <field>
+                        <name>BOOTKEY0_1</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>BOOTKEY0_2</name>
+                <addressOffset>0x0104</addressOffset>
+                <description>Bits 47:32 of SHA-256 hash of boot key 0 (ECC)</description>
+                <size>16</size>
+                <resetMask>0x0000</resetMask>
+                <fields>
+                    <field>
+                        <name>BOOTKEY0_2</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>BOOTKEY0_3</name>
+                <addressOffset>0x0106</addressOffset>
+                <description>Bits 63:48 of SHA-256 hash of boot key 0 (ECC)</description>
+                <size>16</size>
+                <resetMask>0x0000</resetMask>
+                <fields>
+                    <field>
+                        <name>BOOTKEY0_3</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>BOOTKEY0_4</name>
+                <addressOffset>0x0108</addressOffset>
+                <description>Bits 79:64 of SHA-256 hash of boot key 0 (ECC)</description>
+                <size>16</size>
+                <resetMask>0x0000</resetMask>
+                <fields>
+                    <field>
+                        <name>BOOTKEY0_4</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>BOOTKEY0_5</name>
+                <addressOffset>0x010a</addressOffset>
+                <description>Bits 95:80 of SHA-256 hash of boot key 0 (ECC)</description>
+                <size>16</size>
+                <resetMask>0x0000</resetMask>
+                <fields>
+                    <field>
+                        <name>BOOTKEY0_5</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>BOOTKEY0_6</name>
+                <addressOffset>0x010c</addressOffset>
+                <description>Bits 111:96 of SHA-256 hash of boot key 0 (ECC)</description>
+                <size>16</size>
+                <resetMask>0x0000</resetMask>
+                <fields>
+                    <field>
+                        <name>BOOTKEY0_6</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>BOOTKEY0_7</name>
+                <addressOffset>0x010e</addressOffset>
+                <description>Bits 127:112 of SHA-256 hash of boot key 0 (ECC)</description>
+                <size>16</size>
+                <resetMask>0x0000</resetMask>
+                <fields>
+                    <field>
+                        <name>BOOTKEY0_7</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>BOOTKEY0_8</name>
+                <addressOffset>0x0110</addressOffset>
+                <description>Bits 143:128 of SHA-256 hash of boot key 0 (ECC)</description>
+                <size>16</size>
+                <resetMask>0x0000</resetMask>
+                <fields>
+                    <field>
+                        <name>BOOTKEY0_8</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>BOOTKEY0_9</name>
+                <addressOffset>0x0112</addressOffset>
+                <description>Bits 159:144 of SHA-256 hash of boot key 0 (ECC)</description>
+                <size>16</size>
+                <resetMask>0x0000</resetMask>
+                <fields>
+                    <field>
+                        <name>BOOTKEY0_9</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>BOOTKEY0_10</name>
+                <addressOffset>0x0114</addressOffset>
+                <description>Bits 175:160 of SHA-256 hash of boot key 0 (ECC)</description>
+                <size>16</size>
+                <resetMask>0x0000</resetMask>
+                <fields>
+                    <field>
+                        <name>BOOTKEY0_10</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>BOOTKEY0_11</name>
+                <addressOffset>0x0116</addressOffset>
+                <description>Bits 191:176 of SHA-256 hash of boot key 0 (ECC)</description>
+                <size>16</size>
+                <resetMask>0x0000</resetMask>
+                <fields>
+                    <field>
+                        <name>BOOTKEY0_11</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>BOOTKEY0_12</name>
+                <addressOffset>0x0118</addressOffset>
+                <description>Bits 207:192 of SHA-256 hash of boot key 0 (ECC)</description>
+                <size>16</size>
+                <resetMask>0x0000</resetMask>
+                <fields>
+                    <field>
+                        <name>BOOTKEY0_12</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>BOOTKEY0_13</name>
+                <addressOffset>0x011a</addressOffset>
+                <description>Bits 223:208 of SHA-256 hash of boot key 0 (ECC)</description>
+                <size>16</size>
+                <resetMask>0x0000</resetMask>
+                <fields>
+                    <field>
+                        <name>BOOTKEY0_13</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>BOOTKEY0_14</name>
+                <addressOffset>0x011c</addressOffset>
+                <description>Bits 239:224 of SHA-256 hash of boot key 0 (ECC)</description>
+                <size>16</size>
+                <resetMask>0x0000</resetMask>
+                <fields>
+                    <field>
+                        <name>BOOTKEY0_14</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>BOOTKEY0_15</name>
+                <addressOffset>0x011e</addressOffset>
+                <description>Bits 255:240 of SHA-256 hash of boot key 0 (ECC)</description>
+                <size>16</size>
+                <resetMask>0x0000</resetMask>
+                <fields>
+                    <field>
+                        <name>BOOTKEY0_15</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>BOOTKEY1_0</name>
+                <addressOffset>0x0120</addressOffset>
+                <description>Bits 15:0 of SHA-256 hash of boot key 1 (ECC)</description>
+                <size>16</size>
+                <resetMask>0x0000</resetMask>
+                <fields>
+                    <field>
+                        <name>BOOTKEY1_0</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>BOOTKEY1_1</name>
+                <addressOffset>0x0122</addressOffset>
+                <description>Bits 31:16 of SHA-256 hash of boot key 1 (ECC)</description>
+                <size>16</size>
+                <resetMask>0x0000</resetMask>
+                <fields>
+                    <field>
+                        <name>BOOTKEY1_1</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>BOOTKEY1_2</name>
+                <addressOffset>0x0124</addressOffset>
+                <description>Bits 47:32 of SHA-256 hash of boot key 1 (ECC)</description>
+                <size>16</size>
+                <resetMask>0x0000</resetMask>
+                <fields>
+                    <field>
+                        <name>BOOTKEY1_2</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>BOOTKEY1_3</name>
+                <addressOffset>0x0126</addressOffset>
+                <description>Bits 63:48 of SHA-256 hash of boot key 1 (ECC)</description>
+                <size>16</size>
+                <resetMask>0x0000</resetMask>
+                <fields>
+                    <field>
+                        <name>BOOTKEY1_3</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>BOOTKEY1_4</name>
+                <addressOffset>0x0128</addressOffset>
+                <description>Bits 79:64 of SHA-256 hash of boot key 1 (ECC)</description>
+                <size>16</size>
+                <resetMask>0x0000</resetMask>
+                <fields>
+                    <field>
+                        <name>BOOTKEY1_4</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>BOOTKEY1_5</name>
+                <addressOffset>0x012a</addressOffset>
+                <description>Bits 95:80 of SHA-256 hash of boot key 1 (ECC)</description>
+                <size>16</size>
+                <resetMask>0x0000</resetMask>
+                <fields>
+                    <field>
+                        <name>BOOTKEY1_5</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>BOOTKEY1_6</name>
+                <addressOffset>0x012c</addressOffset>
+                <description>Bits 111:96 of SHA-256 hash of boot key 1 (ECC)</description>
+                <size>16</size>
+                <resetMask>0x0000</resetMask>
+                <fields>
+                    <field>
+                        <name>BOOTKEY1_6</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>BOOTKEY1_7</name>
+                <addressOffset>0x012e</addressOffset>
+                <description>Bits 127:112 of SHA-256 hash of boot key 1 (ECC)</description>
+                <size>16</size>
+                <resetMask>0x0000</resetMask>
+                <fields>
+                    <field>
+                        <name>BOOTKEY1_7</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>BOOTKEY1_8</name>
+                <addressOffset>0x0130</addressOffset>
+                <description>Bits 143:128 of SHA-256 hash of boot key 1 (ECC)</description>
+                <size>16</size>
+                <resetMask>0x0000</resetMask>
+                <fields>
+                    <field>
+                        <name>BOOTKEY1_8</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>BOOTKEY1_9</name>
+                <addressOffset>0x0132</addressOffset>
+                <description>Bits 159:144 of SHA-256 hash of boot key 1 (ECC)</description>
+                <size>16</size>
+                <resetMask>0x0000</resetMask>
+                <fields>
+                    <field>
+                        <name>BOOTKEY1_9</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>BOOTKEY1_10</name>
+                <addressOffset>0x0134</addressOffset>
+                <description>Bits 175:160 of SHA-256 hash of boot key 1 (ECC)</description>
+                <size>16</size>
+                <resetMask>0x0000</resetMask>
+                <fields>
+                    <field>
+                        <name>BOOTKEY1_10</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>BOOTKEY1_11</name>
+                <addressOffset>0x0136</addressOffset>
+                <description>Bits 191:176 of SHA-256 hash of boot key 1 (ECC)</description>
+                <size>16</size>
+                <resetMask>0x0000</resetMask>
+                <fields>
+                    <field>
+                        <name>BOOTKEY1_11</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>BOOTKEY1_12</name>
+                <addressOffset>0x0138</addressOffset>
+                <description>Bits 207:192 of SHA-256 hash of boot key 1 (ECC)</description>
+                <size>16</size>
+                <resetMask>0x0000</resetMask>
+                <fields>
+                    <field>
+                        <name>BOOTKEY1_12</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>BOOTKEY1_13</name>
+                <addressOffset>0x013a</addressOffset>
+                <description>Bits 223:208 of SHA-256 hash of boot key 1 (ECC)</description>
+                <size>16</size>
+                <resetMask>0x0000</resetMask>
+                <fields>
+                    <field>
+                        <name>BOOTKEY1_13</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>BOOTKEY1_14</name>
+                <addressOffset>0x013c</addressOffset>
+                <description>Bits 239:224 of SHA-256 hash of boot key 1 (ECC)</description>
+                <size>16</size>
+                <resetMask>0x0000</resetMask>
+                <fields>
+                    <field>
+                        <name>BOOTKEY1_14</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>BOOTKEY1_15</name>
+                <addressOffset>0x013e</addressOffset>
+                <description>Bits 255:240 of SHA-256 hash of boot key 1 (ECC)</description>
+                <size>16</size>
+                <resetMask>0x0000</resetMask>
+                <fields>
+                    <field>
+                        <name>BOOTKEY1_15</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>BOOTKEY2_0</name>
+                <addressOffset>0x0140</addressOffset>
+                <description>Bits 15:0 of SHA-256 hash of boot key 2 (ECC)</description>
+                <size>16</size>
+                <resetMask>0x0000</resetMask>
+                <fields>
+                    <field>
+                        <name>BOOTKEY2_0</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>BOOTKEY2_1</name>
+                <addressOffset>0x0142</addressOffset>
+                <description>Bits 31:16 of SHA-256 hash of boot key 2 (ECC)</description>
+                <size>16</size>
+                <resetMask>0x0000</resetMask>
+                <fields>
+                    <field>
+                        <name>BOOTKEY2_1</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>BOOTKEY2_2</name>
+                <addressOffset>0x0144</addressOffset>
+                <description>Bits 47:32 of SHA-256 hash of boot key 2 (ECC)</description>
+                <size>16</size>
+                <resetMask>0x0000</resetMask>
+                <fields>
+                    <field>
+                        <name>BOOTKEY2_2</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>BOOTKEY2_3</name>
+                <addressOffset>0x0146</addressOffset>
+                <description>Bits 63:48 of SHA-256 hash of boot key 2 (ECC)</description>
+                <size>16</size>
+                <resetMask>0x0000</resetMask>
+                <fields>
+                    <field>
+                        <name>BOOTKEY2_3</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>BOOTKEY2_4</name>
+                <addressOffset>0x0148</addressOffset>
+                <description>Bits 79:64 of SHA-256 hash of boot key 2 (ECC)</description>
+                <size>16</size>
+                <resetMask>0x0000</resetMask>
+                <fields>
+                    <field>
+                        <name>BOOTKEY2_4</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>BOOTKEY2_5</name>
+                <addressOffset>0x014a</addressOffset>
+                <description>Bits 95:80 of SHA-256 hash of boot key 2 (ECC)</description>
+                <size>16</size>
+                <resetMask>0x0000</resetMask>
+                <fields>
+                    <field>
+                        <name>BOOTKEY2_5</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>BOOTKEY2_6</name>
+                <addressOffset>0x014c</addressOffset>
+                <description>Bits 111:96 of SHA-256 hash of boot key 2 (ECC)</description>
+                <size>16</size>
+                <resetMask>0x0000</resetMask>
+                <fields>
+                    <field>
+                        <name>BOOTKEY2_6</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>BOOTKEY2_7</name>
+                <addressOffset>0x014e</addressOffset>
+                <description>Bits 127:112 of SHA-256 hash of boot key 2 (ECC)</description>
+                <size>16</size>
+                <resetMask>0x0000</resetMask>
+                <fields>
+                    <field>
+                        <name>BOOTKEY2_7</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>BOOTKEY2_8</name>
+                <addressOffset>0x0150</addressOffset>
+                <description>Bits 143:128 of SHA-256 hash of boot key 2 (ECC)</description>
+                <size>16</size>
+                <resetMask>0x0000</resetMask>
+                <fields>
+                    <field>
+                        <name>BOOTKEY2_8</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>BOOTKEY2_9</name>
+                <addressOffset>0x0152</addressOffset>
+                <description>Bits 159:144 of SHA-256 hash of boot key 2 (ECC)</description>
+                <size>16</size>
+                <resetMask>0x0000</resetMask>
+                <fields>
+                    <field>
+                        <name>BOOTKEY2_9</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>BOOTKEY2_10</name>
+                <addressOffset>0x0154</addressOffset>
+                <description>Bits 175:160 of SHA-256 hash of boot key 2 (ECC)</description>
+                <size>16</size>
+                <resetMask>0x0000</resetMask>
+                <fields>
+                    <field>
+                        <name>BOOTKEY2_10</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>BOOTKEY2_11</name>
+                <addressOffset>0x0156</addressOffset>
+                <description>Bits 191:176 of SHA-256 hash of boot key 2 (ECC)</description>
+                <size>16</size>
+                <resetMask>0x0000</resetMask>
+                <fields>
+                    <field>
+                        <name>BOOTKEY2_11</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>BOOTKEY2_12</name>
+                <addressOffset>0x0158</addressOffset>
+                <description>Bits 207:192 of SHA-256 hash of boot key 2 (ECC)</description>
+                <size>16</size>
+                <resetMask>0x0000</resetMask>
+                <fields>
+                    <field>
+                        <name>BOOTKEY2_12</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>BOOTKEY2_13</name>
+                <addressOffset>0x015a</addressOffset>
+                <description>Bits 223:208 of SHA-256 hash of boot key 2 (ECC)</description>
+                <size>16</size>
+                <resetMask>0x0000</resetMask>
+                <fields>
+                    <field>
+                        <name>BOOTKEY2_13</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>BOOTKEY2_14</name>
+                <addressOffset>0x015c</addressOffset>
+                <description>Bits 239:224 of SHA-256 hash of boot key 2 (ECC)</description>
+                <size>16</size>
+                <resetMask>0x0000</resetMask>
+                <fields>
+                    <field>
+                        <name>BOOTKEY2_14</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>BOOTKEY2_15</name>
+                <addressOffset>0x015e</addressOffset>
+                <description>Bits 255:240 of SHA-256 hash of boot key 2 (ECC)</description>
+                <size>16</size>
+                <resetMask>0x0000</resetMask>
+                <fields>
+                    <field>
+                        <name>BOOTKEY2_15</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>BOOTKEY3_0</name>
+                <addressOffset>0x0160</addressOffset>
+                <description>Bits 15:0 of SHA-256 hash of boot key 3 (ECC)</description>
+                <size>16</size>
+                <resetMask>0x0000</resetMask>
+                <fields>
+                    <field>
+                        <name>BOOTKEY3_0</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>BOOTKEY3_1</name>
+                <addressOffset>0x0162</addressOffset>
+                <description>Bits 31:16 of SHA-256 hash of boot key 3 (ECC)</description>
+                <size>16</size>
+                <resetMask>0x0000</resetMask>
+                <fields>
+                    <field>
+                        <name>BOOTKEY3_1</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>BOOTKEY3_2</name>
+                <addressOffset>0x0164</addressOffset>
+                <description>Bits 47:32 of SHA-256 hash of boot key 3 (ECC)</description>
+                <size>16</size>
+                <resetMask>0x0000</resetMask>
+                <fields>
+                    <field>
+                        <name>BOOTKEY3_2</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>BOOTKEY3_3</name>
+                <addressOffset>0x0166</addressOffset>
+                <description>Bits 63:48 of SHA-256 hash of boot key 3 (ECC)</description>
+                <size>16</size>
+                <resetMask>0x0000</resetMask>
+                <fields>
+                    <field>
+                        <name>BOOTKEY3_3</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>BOOTKEY3_4</name>
+                <addressOffset>0x0168</addressOffset>
+                <description>Bits 79:64 of SHA-256 hash of boot key 3 (ECC)</description>
+                <size>16</size>
+                <resetMask>0x0000</resetMask>
+                <fields>
+                    <field>
+                        <name>BOOTKEY3_4</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>BOOTKEY3_5</name>
+                <addressOffset>0x016a</addressOffset>
+                <description>Bits 95:80 of SHA-256 hash of boot key 3 (ECC)</description>
+                <size>16</size>
+                <resetMask>0x0000</resetMask>
+                <fields>
+                    <field>
+                        <name>BOOTKEY3_5</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>BOOTKEY3_6</name>
+                <addressOffset>0x016c</addressOffset>
+                <description>Bits 111:96 of SHA-256 hash of boot key 3 (ECC)</description>
+                <size>16</size>
+                <resetMask>0x0000</resetMask>
+                <fields>
+                    <field>
+                        <name>BOOTKEY3_6</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>BOOTKEY3_7</name>
+                <addressOffset>0x016e</addressOffset>
+                <description>Bits 127:112 of SHA-256 hash of boot key 3 (ECC)</description>
+                <size>16</size>
+                <resetMask>0x0000</resetMask>
+                <fields>
+                    <field>
+                        <name>BOOTKEY3_7</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>BOOTKEY3_8</name>
+                <addressOffset>0x0170</addressOffset>
+                <description>Bits 143:128 of SHA-256 hash of boot key 3 (ECC)</description>
+                <size>16</size>
+                <resetMask>0x0000</resetMask>
+                <fields>
+                    <field>
+                        <name>BOOTKEY3_8</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>BOOTKEY3_9</name>
+                <addressOffset>0x0172</addressOffset>
+                <description>Bits 159:144 of SHA-256 hash of boot key 3 (ECC)</description>
+                <size>16</size>
+                <resetMask>0x0000</resetMask>
+                <fields>
+                    <field>
+                        <name>BOOTKEY3_9</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>BOOTKEY3_10</name>
+                <addressOffset>0x0174</addressOffset>
+                <description>Bits 175:160 of SHA-256 hash of boot key 3 (ECC)</description>
+                <size>16</size>
+                <resetMask>0x0000</resetMask>
+                <fields>
+                    <field>
+                        <name>BOOTKEY3_10</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>BOOTKEY3_11</name>
+                <addressOffset>0x0176</addressOffset>
+                <description>Bits 191:176 of SHA-256 hash of boot key 3 (ECC)</description>
+                <size>16</size>
+                <resetMask>0x0000</resetMask>
+                <fields>
+                    <field>
+                        <name>BOOTKEY3_11</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>BOOTKEY3_12</name>
+                <addressOffset>0x0178</addressOffset>
+                <description>Bits 207:192 of SHA-256 hash of boot key 3 (ECC)</description>
+                <size>16</size>
+                <resetMask>0x0000</resetMask>
+                <fields>
+                    <field>
+                        <name>BOOTKEY3_12</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>BOOTKEY3_13</name>
+                <addressOffset>0x017a</addressOffset>
+                <description>Bits 223:208 of SHA-256 hash of boot key 3 (ECC)</description>
+                <size>16</size>
+                <resetMask>0x0000</resetMask>
+                <fields>
+                    <field>
+                        <name>BOOTKEY3_13</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>BOOTKEY3_14</name>
+                <addressOffset>0x017c</addressOffset>
+                <description>Bits 239:224 of SHA-256 hash of boot key 3 (ECC)</description>
+                <size>16</size>
+                <resetMask>0x0000</resetMask>
+                <fields>
+                    <field>
+                        <name>BOOTKEY3_14</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>BOOTKEY3_15</name>
+                <addressOffset>0x017e</addressOffset>
+                <description>Bits 255:240 of SHA-256 hash of boot key 3 (ECC)</description>
+                <size>16</size>
+                <resetMask>0x0000</resetMask>
+                <fields>
+                    <field>
+                        <name>BOOTKEY3_15</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>KEY1_0</name>
+                <addressOffset>0x1e90</addressOffset>
+                <description>Bits 15:0 of OTP access key 1 (ECC)</description>
+                <size>16</size>
+                <resetMask>0x0000</resetMask>
+                <fields>
+                    <field>
+                        <name>KEY1_0</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>KEY1_1</name>
+                <addressOffset>0x1e92</addressOffset>
+                <description>Bits 31:16 of OTP access key 1 (ECC)</description>
+                <size>16</size>
+                <resetMask>0x0000</resetMask>
+                <fields>
+                    <field>
+                        <name>KEY1_1</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>KEY1_2</name>
+                <addressOffset>0x1e94</addressOffset>
+                <description>Bits 47:32 of OTP access key 1 (ECC)</description>
+                <size>16</size>
+                <resetMask>0x0000</resetMask>
+                <fields>
+                    <field>
+                        <name>KEY1_2</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>KEY1_3</name>
+                <addressOffset>0x1e96</addressOffset>
+                <description>Bits 63:48 of OTP access key 1 (ECC)</description>
+                <size>16</size>
+                <resetMask>0x0000</resetMask>
+                <fields>
+                    <field>
+                        <name>KEY1_3</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>KEY1_4</name>
+                <addressOffset>0x1e98</addressOffset>
+                <description>Bits 79:64 of OTP access key 1 (ECC)</description>
+                <size>16</size>
+                <resetMask>0x0000</resetMask>
+                <fields>
+                    <field>
+                        <name>KEY1_4</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>KEY1_5</name>
+                <addressOffset>0x1e9a</addressOffset>
+                <description>Bits 95:80 of OTP access key 1 (ECC)</description>
+                <size>16</size>
+                <resetMask>0x0000</resetMask>
+                <fields>
+                    <field>
+                        <name>KEY1_5</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>KEY1_6</name>
+                <addressOffset>0x1e9c</addressOffset>
+                <description>Bits 111:96 of OTP access key 1 (ECC)</description>
+                <size>16</size>
+                <resetMask>0x0000</resetMask>
+                <fields>
+                    <field>
+                        <name>KEY1_6</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>KEY1_7</name>
+                <addressOffset>0x1e9e</addressOffset>
+                <description>Bits 127:112 of OTP access key 1 (ECC)</description>
+                <size>16</size>
+                <resetMask>0x0000</resetMask>
+                <fields>
+                    <field>
+                        <name>KEY1_7</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>KEY2_0</name>
+                <addressOffset>0x1ea0</addressOffset>
+                <description>Bits 15:0 of OTP access key 2 (ECC)</description>
+                <size>16</size>
+                <resetMask>0x0000</resetMask>
+                <fields>
+                    <field>
+                        <name>KEY2_0</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>KEY2_1</name>
+                <addressOffset>0x1ea2</addressOffset>
+                <description>Bits 31:16 of OTP access key 2 (ECC)</description>
+                <size>16</size>
+                <resetMask>0x0000</resetMask>
+                <fields>
+                    <field>
+                        <name>KEY2_1</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>KEY2_2</name>
+                <addressOffset>0x1ea4</addressOffset>
+                <description>Bits 47:32 of OTP access key 2 (ECC)</description>
+                <size>16</size>
+                <resetMask>0x0000</resetMask>
+                <fields>
+                    <field>
+                        <name>KEY2_2</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>KEY2_3</name>
+                <addressOffset>0x1ea6</addressOffset>
+                <description>Bits 63:48 of OTP access key 2 (ECC)</description>
+                <size>16</size>
+                <resetMask>0x0000</resetMask>
+                <fields>
+                    <field>
+                        <name>KEY2_3</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>KEY2_4</name>
+                <addressOffset>0x1ea8</addressOffset>
+                <description>Bits 79:64 of OTP access key 2 (ECC)</description>
+                <size>16</size>
+                <resetMask>0x0000</resetMask>
+                <fields>
+                    <field>
+                        <name>KEY2_4</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>KEY2_5</name>
+                <addressOffset>0x1eaa</addressOffset>
+                <description>Bits 95:80 of OTP access key 2 (ECC)</description>
+                <size>16</size>
+                <resetMask>0x0000</resetMask>
+                <fields>
+                    <field>
+                        <name>KEY2_5</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>KEY2_6</name>
+                <addressOffset>0x1eac</addressOffset>
+                <description>Bits 111:96 of OTP access key 2 (ECC)</description>
+                <size>16</size>
+                <resetMask>0x0000</resetMask>
+                <fields>
+                    <field>
+                        <name>KEY2_6</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>KEY2_7</name>
+                <addressOffset>0x1eae</addressOffset>
+                <description>Bits 127:112 of OTP access key 2 (ECC)</description>
+                <size>16</size>
+                <resetMask>0x0000</resetMask>
+                <fields>
+                    <field>
+                        <name>KEY2_7</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>KEY3_0</name>
+                <addressOffset>0x1eb0</addressOffset>
+                <description>Bits 15:0 of OTP access key 3 (ECC)</description>
+                <size>16</size>
+                <resetMask>0x0000</resetMask>
+                <fields>
+                    <field>
+                        <name>KEY3_0</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>KEY3_1</name>
+                <addressOffset>0x1eb2</addressOffset>
+                <description>Bits 31:16 of OTP access key 3 (ECC)</description>
+                <size>16</size>
+                <resetMask>0x0000</resetMask>
+                <fields>
+                    <field>
+                        <name>KEY3_1</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>KEY3_2</name>
+                <addressOffset>0x1eb4</addressOffset>
+                <description>Bits 47:32 of OTP access key 3 (ECC)</description>
+                <size>16</size>
+                <resetMask>0x0000</resetMask>
+                <fields>
+                    <field>
+                        <name>KEY3_2</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>KEY3_3</name>
+                <addressOffset>0x1eb6</addressOffset>
+                <description>Bits 63:48 of OTP access key 3 (ECC)</description>
+                <size>16</size>
+                <resetMask>0x0000</resetMask>
+                <fields>
+                    <field>
+                        <name>KEY3_3</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>KEY3_4</name>
+                <addressOffset>0x1eb8</addressOffset>
+                <description>Bits 79:64 of OTP access key 3 (ECC)</description>
+                <size>16</size>
+                <resetMask>0x0000</resetMask>
+                <fields>
+                    <field>
+                        <name>KEY3_4</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>KEY3_5</name>
+                <addressOffset>0x1eba</addressOffset>
+                <description>Bits 95:80 of OTP access key 3 (ECC)</description>
+                <size>16</size>
+                <resetMask>0x0000</resetMask>
+                <fields>
+                    <field>
+                        <name>KEY3_5</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>KEY3_6</name>
+                <addressOffset>0x1ebc</addressOffset>
+                <description>Bits 111:96 of OTP access key 3 (ECC)</description>
+                <size>16</size>
+                <resetMask>0x0000</resetMask>
+                <fields>
+                    <field>
+                        <name>KEY3_6</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>KEY3_7</name>
+                <addressOffset>0x1ebe</addressOffset>
+                <description>Bits 127:112 of OTP access key 3 (ECC)</description>
+                <size>16</size>
+                <resetMask>0x0000</resetMask>
+                <fields>
+                    <field>
+                        <name>KEY3_7</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>KEY4_0</name>
+                <addressOffset>0x1ec0</addressOffset>
+                <description>Bits 15:0 of OTP access key 4 (ECC)</description>
+                <size>16</size>
+                <resetMask>0x0000</resetMask>
+                <fields>
+                    <field>
+                        <name>KEY4_0</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>KEY4_1</name>
+                <addressOffset>0x1ec2</addressOffset>
+                <description>Bits 31:16 of OTP access key 4 (ECC)</description>
+                <size>16</size>
+                <resetMask>0x0000</resetMask>
+                <fields>
+                    <field>
+                        <name>KEY4_1</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>KEY4_2</name>
+                <addressOffset>0x1ec4</addressOffset>
+                <description>Bits 47:32 of OTP access key 4 (ECC)</description>
+                <size>16</size>
+                <resetMask>0x0000</resetMask>
+                <fields>
+                    <field>
+                        <name>KEY4_2</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>KEY4_3</name>
+                <addressOffset>0x1ec6</addressOffset>
+                <description>Bits 63:48 of OTP access key 4 (ECC)</description>
+                <size>16</size>
+                <resetMask>0x0000</resetMask>
+                <fields>
+                    <field>
+                        <name>KEY4_3</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>KEY4_4</name>
+                <addressOffset>0x1ec8</addressOffset>
+                <description>Bits 79:64 of OTP access key 4 (ECC)</description>
+                <size>16</size>
+                <resetMask>0x0000</resetMask>
+                <fields>
+                    <field>
+                        <name>KEY4_4</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>KEY4_5</name>
+                <addressOffset>0x1eca</addressOffset>
+                <description>Bits 95:80 of OTP access key 4 (ECC)</description>
+                <size>16</size>
+                <resetMask>0x0000</resetMask>
+                <fields>
+                    <field>
+                        <name>KEY4_5</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>KEY4_6</name>
+                <addressOffset>0x1ecc</addressOffset>
+                <description>Bits 111:96 of OTP access key 4 (ECC)</description>
+                <size>16</size>
+                <resetMask>0x0000</resetMask>
+                <fields>
+                    <field>
+                        <name>KEY4_6</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>KEY4_7</name>
+                <addressOffset>0x1ece</addressOffset>
+                <description>Bits 127:112 of OTP access key 4 (ECC)</description>
+                <size>16</size>
+                <resetMask>0x0000</resetMask>
+                <fields>
+                    <field>
+                        <name>KEY4_7</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>KEY5_0</name>
+                <addressOffset>0x1ed0</addressOffset>
+                <description>Bits 15:0 of OTP access key 5 (ECC)</description>
+                <size>16</size>
+                <resetMask>0x0000</resetMask>
+                <fields>
+                    <field>
+                        <name>KEY5_0</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>KEY5_1</name>
+                <addressOffset>0x1ed2</addressOffset>
+                <description>Bits 31:16 of OTP access key 5 (ECC)</description>
+                <size>16</size>
+                <resetMask>0x0000</resetMask>
+                <fields>
+                    <field>
+                        <name>KEY5_1</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>KEY5_2</name>
+                <addressOffset>0x1ed4</addressOffset>
+                <description>Bits 47:32 of OTP access key 5 (ECC)</description>
+                <size>16</size>
+                <resetMask>0x0000</resetMask>
+                <fields>
+                    <field>
+                        <name>KEY5_2</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>KEY5_3</name>
+                <addressOffset>0x1ed6</addressOffset>
+                <description>Bits 63:48 of OTP access key 5 (ECC)</description>
+                <size>16</size>
+                <resetMask>0x0000</resetMask>
+                <fields>
+                    <field>
+                        <name>KEY5_3</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>KEY5_4</name>
+                <addressOffset>0x1ed8</addressOffset>
+                <description>Bits 79:64 of OTP access key 5 (ECC)</description>
+                <size>16</size>
+                <resetMask>0x0000</resetMask>
+                <fields>
+                    <field>
+                        <name>KEY5_4</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>KEY5_5</name>
+                <addressOffset>0x1eda</addressOffset>
+                <description>Bits 95:80 of OTP access key 5 (ECC)</description>
+                <size>16</size>
+                <resetMask>0x0000</resetMask>
+                <fields>
+                    <field>
+                        <name>KEY5_5</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>KEY5_6</name>
+                <addressOffset>0x1edc</addressOffset>
+                <description>Bits 111:96 of OTP access key 5 (ECC)</description>
+                <size>16</size>
+                <resetMask>0x0000</resetMask>
+                <fields>
+                    <field>
+                        <name>KEY5_6</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>KEY5_7</name>
+                <addressOffset>0x1ede</addressOffset>
+                <description>Bits 127:112 of OTP access key 5 (ECC)</description>
+                <size>16</size>
+                <resetMask>0x0000</resetMask>
+                <fields>
+                    <field>
+                        <name>KEY5_7</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>KEY6_0</name>
+                <addressOffset>0x1ee0</addressOffset>
+                <description>Bits 15:0 of OTP access key 6 (ECC)</description>
+                <size>16</size>
+                <resetMask>0x0000</resetMask>
+                <fields>
+                    <field>
+                        <name>KEY6_0</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>KEY6_1</name>
+                <addressOffset>0x1ee2</addressOffset>
+                <description>Bits 31:16 of OTP access key 6 (ECC)</description>
+                <size>16</size>
+                <resetMask>0x0000</resetMask>
+                <fields>
+                    <field>
+                        <name>KEY6_1</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>KEY6_2</name>
+                <addressOffset>0x1ee4</addressOffset>
+                <description>Bits 47:32 of OTP access key 6 (ECC)</description>
+                <size>16</size>
+                <resetMask>0x0000</resetMask>
+                <fields>
+                    <field>
+                        <name>KEY6_2</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>KEY6_3</name>
+                <addressOffset>0x1ee6</addressOffset>
+                <description>Bits 63:48 of OTP access key 6 (ECC)</description>
+                <size>16</size>
+                <resetMask>0x0000</resetMask>
+                <fields>
+                    <field>
+                        <name>KEY6_3</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>KEY6_4</name>
+                <addressOffset>0x1ee8</addressOffset>
+                <description>Bits 79:64 of OTP access key 6 (ECC)</description>
+                <size>16</size>
+                <resetMask>0x0000</resetMask>
+                <fields>
+                    <field>
+                        <name>KEY6_4</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>KEY6_5</name>
+                <addressOffset>0x1eea</addressOffset>
+                <description>Bits 95:80 of OTP access key 6 (ECC)</description>
+                <size>16</size>
+                <resetMask>0x0000</resetMask>
+                <fields>
+                    <field>
+                        <name>KEY6_5</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>KEY6_6</name>
+                <addressOffset>0x1eec</addressOffset>
+                <description>Bits 111:96 of OTP access key 6 (ECC)</description>
+                <size>16</size>
+                <resetMask>0x0000</resetMask>
+                <fields>
+                    <field>
+                        <name>KEY6_6</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>KEY6_7</name>
+                <addressOffset>0x1eee</addressOffset>
+                <description>Bits 127:112 of OTP access key 6 (ECC)</description>
+                <size>16</size>
+                <resetMask>0x0000</resetMask>
+                <fields>
+                    <field>
+                        <name>KEY6_7</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+        </registers>
+    </peripheral>
+    <peripheral>
+        <name>OTP_DATA_RAW</name>
+        <description>Predefined OTP data layout for RP2350</description>
+        <baseAddress>0x40134000</baseAddress>
+        <addressBlock>
+            <offset>0</offset>
+            <size>16383</size>
+            <usage>registers</usage>
+        </addressBlock>
+        <registers>
+            <register>
+                <name>CHIPID0</name>
+                <addressOffset>0x000000</addressOffset>
+                <description>Bits 15:0 of public device ID. (ECC)
+
+                    The CHIPID0..3 rows contain a 64-bit random identifier for this chip, which can be read from the USB bootloader PICOBOOT interface or from the get_sys_info ROM API.
+
+                    The number of random bits makes the occurrence of twins exceedingly unlikely: for example, a fleet of a hundred million devices has a 99.97% probability of no twinned IDs. This is estimated to be lower than the occurrence of process errors in the assignment of sequential random IDs, and for practical purposes CHIPID may be treated as unique.</description>
+                <size>24</size>
+                <resetMask>0x000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CHIPID0</name>
+                        <bitRange>[23:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CHIPID1</name>
+                <addressOffset>0x000004</addressOffset>
+                <description>Bits 31:16 of public device ID (ECC)</description>
+                <size>24</size>
+                <resetMask>0x000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CHIPID1</name>
+                        <bitRange>[23:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CHIPID2</name>
+                <addressOffset>0x000008</addressOffset>
+                <description>Bits 47:32 of public device ID (ECC)</description>
+                <size>24</size>
+                <resetMask>0x000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CHIPID2</name>
+                        <bitRange>[23:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CHIPID3</name>
+                <addressOffset>0x00000c</addressOffset>
+                <description>Bits 63:48 of public device ID (ECC)</description>
+                <size>24</size>
+                <resetMask>0x000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CHIPID3</name>
+                        <bitRange>[23:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>RANDID0</name>
+                <addressOffset>0x000010</addressOffset>
+                <description>Bits 15:0 of private per-device random number (ECC)
+
+                    The RANDID0..7 rows form a 128-bit random number generated during device test.
+
+                    This ID is not exposed through the USB PICOBOOT GET_INFO command or the ROM `get_sys_info()` API. However note that the USB PICOBOOT OTP access point can read the entirety of page 0, so this value is not meaningfully private unless the USB PICOBOOT interface is disabled via the DISABLE_BOOTSEL_USB_PICOBOOT_IFC flag in BOOT_FLAGS0.</description>
+                <size>24</size>
+                <resetMask>0x000000</resetMask>
+                <fields>
+                    <field>
+                        <name>RANDID0</name>
+                        <bitRange>[23:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>RANDID1</name>
+                <addressOffset>0x000014</addressOffset>
+                <description>Bits 31:16 of private per-device random number (ECC)</description>
+                <size>24</size>
+                <resetMask>0x000000</resetMask>
+                <fields>
+                    <field>
+                        <name>RANDID1</name>
+                        <bitRange>[23:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>RANDID2</name>
+                <addressOffset>0x000018</addressOffset>
+                <description>Bits 47:32 of private per-device random number (ECC)</description>
+                <size>24</size>
+                <resetMask>0x000000</resetMask>
+                <fields>
+                    <field>
+                        <name>RANDID2</name>
+                        <bitRange>[23:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>RANDID3</name>
+                <addressOffset>0x00001c</addressOffset>
+                <description>Bits 63:48 of private per-device random number (ECC)</description>
+                <size>24</size>
+                <resetMask>0x000000</resetMask>
+                <fields>
+                    <field>
+                        <name>RANDID3</name>
+                        <bitRange>[23:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>RANDID4</name>
+                <addressOffset>0x000020</addressOffset>
+                <description>Bits 79:64 of private per-device random number (ECC)</description>
+                <size>24</size>
+                <resetMask>0x000000</resetMask>
+                <fields>
+                    <field>
+                        <name>RANDID4</name>
+                        <bitRange>[23:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>RANDID5</name>
+                <addressOffset>0x000024</addressOffset>
+                <description>Bits 95:80 of private per-device random number (ECC)</description>
+                <size>24</size>
+                <resetMask>0x000000</resetMask>
+                <fields>
+                    <field>
+                        <name>RANDID5</name>
+                        <bitRange>[23:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>RANDID6</name>
+                <addressOffset>0x000028</addressOffset>
+                <description>Bits 111:96 of private per-device random number (ECC)</description>
+                <size>24</size>
+                <resetMask>0x000000</resetMask>
+                <fields>
+                    <field>
+                        <name>RANDID6</name>
+                        <bitRange>[23:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>RANDID7</name>
+                <addressOffset>0x00002c</addressOffset>
+                <description>Bits 127:112 of private per-device random number (ECC)</description>
+                <size>24</size>
+                <resetMask>0x000000</resetMask>
+                <fields>
+                    <field>
+                        <name>RANDID7</name>
+                        <bitRange>[23:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>ROSC_CALIB</name>
+                <addressOffset>0x000040</addressOffset>
+                <description>Ring oscillator frequency in kHz, measured during manufacturing (ECC)
+
+                    This is measured at 1.1 V, at room temperature, with the ROSC configuration registers in their reset state.</description>
+                <size>24</size>
+                <resetMask>0x000000</resetMask>
+                <fields>
+                    <field>
+                        <name>ROSC_CALIB</name>
+                        <bitRange>[23:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>LPOSC_CALIB</name>
+                <addressOffset>0x000044</addressOffset>
+                <description>Low-power oscillator frequency in Hz, measured during manufacturing (ECC)
+
+                    This is measured at 1.1V, at room temperature, with the LPOSC trim register in its reset state.</description>
+                <size>24</size>
+                <resetMask>0x000000</resetMask>
+                <fields>
+                    <field>
+                        <name>LPOSC_CALIB</name>
+                        <bitRange>[23:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>NUM_GPIOS</name>
+                <addressOffset>0x000060</addressOffset>
+                <description>The number of main user GPIOs (bank 0). Should read 48 in the QFN80 package, and 30 in the QFN60 package. (ECC)</description>
+                <size>24</size>
+                <resetMask>0x000000</resetMask>
+                <fields>
+                    <field>
+                        <name>NUM_GPIOS</name>
+                        <bitRange>[23:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INFO_CRC0</name>
+                <addressOffset>0x0000d8</addressOffset>
+                <description>Lower 16 bits of CRC32 of OTP addresses 0x00 through 0x6b (polynomial 0x4c11db7, input reflected, output reflected, seed all-ones, final XOR all-ones) (ECC)</description>
+                <size>24</size>
+                <resetMask>0x000000</resetMask>
+                <fields>
+                    <field>
+                        <name>INFO_CRC0</name>
+                        <bitRange>[23:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>INFO_CRC1</name>
+                <addressOffset>0x0000dc</addressOffset>
+                <description>Upper 16 bits of CRC32 of OTP addresses 0x00 through 0x6b (ECC)</description>
+                <size>24</size>
+                <resetMask>0x000000</resetMask>
+                <fields>
+                    <field>
+                        <name>INFO_CRC1</name>
+                        <bitRange>[23:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CRIT0</name>
+                <addressOffset>0x0000e0</addressOffset>
+                <description>Page 0 critical boot flags (RBIT-8)</description>
+                <size>24</size>
+                <resetValue>0x000000</resetValue>
+                <fields>
+                    <field>
+                        <name>RISCV_DISABLE</name>
+                        <description>Permanently disable RISC-V processors (Hazard3)</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>ARM_DISABLE</name>
+                        <description>Permanently disable ARM processors (Cortex-M33)</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CRIT0_R1</name>
+                <addressOffset>0x0000e4</addressOffset>
+                <description>Redundant copy of CRIT0</description>
+                <size>24</size>
+                <resetMask>0x000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CRIT0_R1</name>
+                        <bitRange>[23:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CRIT0_R2</name>
+                <addressOffset>0x0000e8</addressOffset>
+                <description>Redundant copy of CRIT0</description>
+                <size>24</size>
+                <resetMask>0x000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CRIT0_R2</name>
+                        <bitRange>[23:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CRIT0_R3</name>
+                <addressOffset>0x0000ec</addressOffset>
+                <description>Redundant copy of CRIT0</description>
+                <size>24</size>
+                <resetMask>0x000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CRIT0_R3</name>
+                        <bitRange>[23:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CRIT0_R4</name>
+                <addressOffset>0x0000f0</addressOffset>
+                <description>Redundant copy of CRIT0</description>
+                <size>24</size>
+                <resetMask>0x000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CRIT0_R4</name>
+                        <bitRange>[23:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CRIT0_R5</name>
+                <addressOffset>0x0000f4</addressOffset>
+                <description>Redundant copy of CRIT0</description>
+                <size>24</size>
+                <resetMask>0x000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CRIT0_R5</name>
+                        <bitRange>[23:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CRIT0_R6</name>
+                <addressOffset>0x0000f8</addressOffset>
+                <description>Redundant copy of CRIT0</description>
+                <size>24</size>
+                <resetMask>0x000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CRIT0_R6</name>
+                        <bitRange>[23:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CRIT0_R7</name>
+                <addressOffset>0x0000fc</addressOffset>
+                <description>Redundant copy of CRIT0</description>
+                <size>24</size>
+                <resetMask>0x000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CRIT0_R7</name>
+                        <bitRange>[23:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CRIT1</name>
+                <addressOffset>0x000100</addressOffset>
+                <description>Page 1 critical boot flags (RBIT-8)</description>
+                <size>24</size>
+                <resetValue>0x000000</resetValue>
+                <fields>
+                    <field>
+                        <name>GLITCH_DETECTOR_SENS</name>
+                        <description>Increase the sensitivity of the glitch detectors from their default.</description>
+                        <bitRange>[6:5]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>GLITCH_DETECTOR_ENABLE</name>
+                        <description>Arm the glitch detectors to reset the system if an abnormal clock/power event is observed.</description>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>BOOT_ARCH</name>
+                        <description>Set the default boot architecture, 0=ARM 1=RISC-V. Ignored if ARM_DISABLE, RISCV_DISABLE or SECURE_BOOT_ENABLE is set.</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>DEBUG_DISABLE</name>
+                        <description>Disable all debug access</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SECURE_DEBUG_DISABLE</name>
+                        <description>Disable Secure debug access</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SECURE_BOOT_ENABLE</name>
+                        <description>Enable boot signature enforcement, and permanently disable the RISC-V cores.</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CRIT1_R1</name>
+                <addressOffset>0x000104</addressOffset>
+                <description>Redundant copy of CRIT1</description>
+                <size>24</size>
+                <resetMask>0x000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CRIT1_R1</name>
+                        <bitRange>[23:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CRIT1_R2</name>
+                <addressOffset>0x000108</addressOffset>
+                <description>Redundant copy of CRIT1</description>
+                <size>24</size>
+                <resetMask>0x000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CRIT1_R2</name>
+                        <bitRange>[23:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CRIT1_R3</name>
+                <addressOffset>0x00010c</addressOffset>
+                <description>Redundant copy of CRIT1</description>
+                <size>24</size>
+                <resetMask>0x000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CRIT1_R3</name>
+                        <bitRange>[23:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CRIT1_R4</name>
+                <addressOffset>0x000110</addressOffset>
+                <description>Redundant copy of CRIT1</description>
+                <size>24</size>
+                <resetMask>0x000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CRIT1_R4</name>
+                        <bitRange>[23:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CRIT1_R5</name>
+                <addressOffset>0x000114</addressOffset>
+                <description>Redundant copy of CRIT1</description>
+                <size>24</size>
+                <resetMask>0x000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CRIT1_R5</name>
+                        <bitRange>[23:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CRIT1_R6</name>
+                <addressOffset>0x000118</addressOffset>
+                <description>Redundant copy of CRIT1</description>
+                <size>24</size>
+                <resetMask>0x000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CRIT1_R6</name>
+                        <bitRange>[23:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>CRIT1_R7</name>
+                <addressOffset>0x00011c</addressOffset>
+                <description>Redundant copy of CRIT1</description>
+                <size>24</size>
+                <resetMask>0x000000</resetMask>
+                <fields>
+                    <field>
+                        <name>CRIT1_R7</name>
+                        <bitRange>[23:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>BOOT_FLAGS0</name>
+                <addressOffset>0x000120</addressOffset>
+                <description>Disable/Enable boot paths/features in the RP2350 mask ROM. Disables always supersede enables. Enables are provided where there are other configurations in OTP that must be valid. (RBIT-3)</description>
+                <size>24</size>
+                <resetValue>0x000000</resetValue>
+                <fields>
+                    <field>
+                        <name>DISABLE_SRAM_WINDOW_BOOT</name>
+                        <bitRange>[21:21]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>DISABLE_XIP_ACCESS_ON_SRAM_ENTRY</name>
+                        <description>Disable all access to XIP after entering an SRAM binary.
+
+                            Note that this will cause bootrom APIs that access XIP to fail, including APIs that interact with the partition table.</description>
+                        <bitRange>[20:20]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>DISABLE_BOOTSEL_UART_BOOT</name>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>DISABLE_BOOTSEL_USB_PICOBOOT_IFC</name>
+                        <bitRange>[18:18]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>DISABLE_BOOTSEL_USB_MSD_IFC</name>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>DISABLE_WATCHDOG_SCRATCH</name>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>DISABLE_POWER_SCRATCH</name>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>ENABLE_OTP_BOOT</name>
+                        <description>Enable OTP boot. A number of OTP rows specified by OTPBOOT_LEN will be loaded, starting from OTPBOOT_SRC, into the SRAM location specified by OTPBOOT_DST1 and OTPBOOT_DST0.
+
+                            The loaded program image is stored with ECC, 16 bits per row, and must contain a valid IMAGE_DEF. Do not set this bit without first programming an image into OTP and configuring OTPBOOT_LEN, OTPBOOT_SRC, OTPBOOT_DST0 and OTPBOOT_DST1.
+
+                            Note that OTPBOOT_LEN and OTPBOOT_SRC must be even numbers of OTP rows. Equivalently, the image must be a multiple of 32 bits in size, and must start at a 32-bit-aligned address in the ECC read data address window.</description>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>DISABLE_OTP_BOOT</name>
+                        <description>Takes precedence over ENABLE_OTP_BOOT.</description>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>DISABLE_FLASH_BOOT</name>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>ROLLBACK_REQUIRED</name>
+                        <description>Require binaries to have a rollback version. Set automatically the first time a binary with a rollback version is booted.</description>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>HASHED_PARTITION_TABLE</name>
+                        <description>Require a partition table to be hashed (if not signed)</description>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SECURE_PARTITION_TABLE</name>
+                        <description>Require a partition table to be signed</description>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>DISABLE_AUTO_SWITCH_ARCH</name>
+                        <description>Disable auto-switch of CPU architecture on boot when the (only) binary to be booted is for the other Arm/RISC-V architecture and both architectures are enabled</description>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>SINGLE_FLASH_BINARY</name>
+                        <description>Restrict flash boot path to use of a single binary at the start of flash</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>OVERRIDE_FLASH_PARTITION_SLOT_SIZE</name>
+                        <description>Override the limit for default flash metadata scanning.
+
+                            The value is specified in FLASH_PARTITION_SLOT_SIZE. Make sure FLASH_PARTITION_SLOT_SIZE is valid before setting this bit</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>FLASH_DEVINFO_ENABLE</name>
+                        <description>Mark FLASH_DEVINFO as containing valid, ECC&#39;d data which describes external flash devices.</description>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>FAST_SIGCHECK_ROSC_DIV</name>
+                        <description>Enable quartering of ROSC divisor during signature check, to reduce secure boot time</description>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>FLASH_IO_VOLTAGE_1V8</name>
+                        <description>If 1, configure the QSPI pads for 1.8 V operation when accessing flash for the first time from the bootrom, using the VOLTAGE_SELECT register for the QSPI pads bank. This slightly improves the input timing of the pads at low voltages, but does not affect their output characteristics.
+
+                            If 0, leave VOLTAGE_SELECT in its reset state (suitable for operation at and above 2.5 V)</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>ENABLE_BOOTSEL_NON_DEFAULT_PLL_XOSC_CFG</name>
+                        <description>Enable loading of the non-default XOSC and PLL configuration before entering BOOTSEL mode.
+
+                            Ensure that BOOTSEL_XOSC_CFG and BOOTSEL_PLL_CFG are correctly programmed before setting this bit.
+
+                            If this bit is set, user software may use the contents of BOOTSEL_PLL_CFG to calculated the expected XOSC frequency based on the fixed USB boot frequency of 48 MHz.</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>ENABLE_BOOTSEL_LED</name>
+                        <description>Enable bootloader activity LED. If set, bootsel_led_cfg is assumed to be valid</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>DISABLE_BOOTSEL_EXEC2</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>BOOT_FLAGS0_R1</name>
+                <addressOffset>0x000124</addressOffset>
+                <description>Redundant copy of BOOT_FLAGS0</description>
+                <size>24</size>
+                <resetMask>0x000000</resetMask>
+                <fields>
+                    <field>
+                        <name>BOOT_FLAGS0_R1</name>
+                        <bitRange>[23:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>BOOT_FLAGS0_R2</name>
+                <addressOffset>0x000128</addressOffset>
+                <description>Redundant copy of BOOT_FLAGS0</description>
+                <size>24</size>
+                <resetMask>0x000000</resetMask>
+                <fields>
+                    <field>
+                        <name>BOOT_FLAGS0_R2</name>
+                        <bitRange>[23:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>BOOT_FLAGS1</name>
+                <addressOffset>0x00012c</addressOffset>
+                <description>Disable/Enable boot paths/features in the RP2350 mask ROM. Disables always supersede enables. Enables are provided where there are other configurations in OTP that must be valid. (RBIT-3)</description>
+                <size>24</size>
+                <resetValue>0x000000</resetValue>
+                <fields>
+                    <field>
+                        <name>DOUBLE_TAP</name>
+                        <description>Enable entering BOOTSEL mode via double-tap of the RUN/RSTn pin. Adds a significant delay to boot time, as configured by DOUBLE_TAP_DELAY.
+
+                            This functions by waiting at startup (i.e. following a reset) to see if a second reset is applied soon afterward. The second reset is detected by the bootrom with help of the POWMAN_CHIP_RESET_DOUBLE_TAP flag, which is not reset by the external reset pin, and the bootrom enters BOOTSEL mode (NSBOOT) to await further instruction over USB or UART.</description>
+                        <bitRange>[19:19]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>DOUBLE_TAP_DELAY</name>
+                        <description>Adjust how long to wait for a second reset when double tap BOOTSEL mode is enabled via DOUBLE_TAP. The minimum is 50 milliseconds, and each unit of this field adds an additional 50 milliseconds.
+
+                            For example, settings this field to its maximum value of 7 will cause the chip to wait for 400 milliseconds at boot to check for a second reset which requests entry to BOOTSEL mode.
+
+                            200 milliseconds (DOUBLE_TAP_DELAY=3) is a good intermediate value.</description>
+                        <bitRange>[18:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>KEY_INVALID</name>
+                        <description>Mark a boot key as invalid, or prevent it from ever becoming valid. The bootrom will ignore any boot key marked as invalid during secure boot signature checks.
+
+                            Each bit in this field corresponds to one of the four 256-bit boot key hashes that may be stored in page 2 of the OTP.
+
+                            When provisioning boot keys, it&#39;s recommended to mark any boot key slots you don&#39;t intend to use as KEY_INVALID, so that spurious keys can not be installed at a later time.</description>
+                        <bitRange>[11:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>KEY_VALID</name>
+                        <description>Mark each of the possible boot keys as valid. The bootrom will check signatures against all valid boot keys, and ignore invalid boot keys.
+
+                            Each bit in this field corresponds to one of the four 256-bit boot key hashes that may be stored in page 2 of the OTP.
+
+                            A KEY_VALID bit is ignored if the corresponding KEY_INVALID bit is set. Boot keys are considered valid only when KEY_VALID is set and KEY_INVALID is clear.
+
+                            Do not mark a boot key as KEY_VALID if it does not contain a valid SHA-256 hash of your secp256k1 public key. Verify keys after programming, before setting the KEY_VALID bits -- a boot key with uncorrectable ECC faults will render your device unbootable if secure boot is enabled.
+
+                            Do not enable secure boot without first installing a valid key. This will render your device unbootable.</description>
+                        <bitRange>[3:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>BOOT_FLAGS1_R1</name>
+                <addressOffset>0x000130</addressOffset>
+                <description>Redundant copy of BOOT_FLAGS1</description>
+                <size>24</size>
+                <resetMask>0x000000</resetMask>
+                <fields>
+                    <field>
+                        <name>BOOT_FLAGS1_R1</name>
+                        <bitRange>[23:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>BOOT_FLAGS1_R2</name>
+                <addressOffset>0x000134</addressOffset>
+                <description>Redundant copy of BOOT_FLAGS1</description>
+                <size>24</size>
+                <resetMask>0x000000</resetMask>
+                <fields>
+                    <field>
+                        <name>BOOT_FLAGS1_R2</name>
+                        <bitRange>[23:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>DEFAULT_BOOT_VERSION0</name>
+                <addressOffset>0x000138</addressOffset>
+                <description>Default boot version thermometer counter, bits 23:0 (RBIT-3)</description>
+                <size>24</size>
+                <resetMask>0x000000</resetMask>
+                <fields>
+                    <field>
+                        <name>DEFAULT_BOOT_VERSION0</name>
+                        <bitRange>[23:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>DEFAULT_BOOT_VERSION0_R1</name>
+                <addressOffset>0x00013c</addressOffset>
+                <description>Redundant copy of DEFAULT_BOOT_VERSION0</description>
+                <size>24</size>
+                <resetMask>0x000000</resetMask>
+                <fields>
+                    <field>
+                        <name>DEFAULT_BOOT_VERSION0_R1</name>
+                        <bitRange>[23:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>DEFAULT_BOOT_VERSION0_R2</name>
+                <addressOffset>0x000140</addressOffset>
+                <description>Redundant copy of DEFAULT_BOOT_VERSION0</description>
+                <size>24</size>
+                <resetMask>0x000000</resetMask>
+                <fields>
+                    <field>
+                        <name>DEFAULT_BOOT_VERSION0_R2</name>
+                        <bitRange>[23:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>DEFAULT_BOOT_VERSION1</name>
+                <addressOffset>0x000144</addressOffset>
+                <description>Default boot version thermometer counter, bits 47:24 (RBIT-3)</description>
+                <size>24</size>
+                <resetMask>0x000000</resetMask>
+                <fields>
+                    <field>
+                        <name>DEFAULT_BOOT_VERSION1</name>
+                        <bitRange>[23:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>DEFAULT_BOOT_VERSION1_R1</name>
+                <addressOffset>0x000148</addressOffset>
+                <description>Redundant copy of DEFAULT_BOOT_VERSION1</description>
+                <size>24</size>
+                <resetMask>0x000000</resetMask>
+                <fields>
+                    <field>
+                        <name>DEFAULT_BOOT_VERSION1_R1</name>
+                        <bitRange>[23:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>DEFAULT_BOOT_VERSION1_R2</name>
+                <addressOffset>0x00014c</addressOffset>
+                <description>Redundant copy of DEFAULT_BOOT_VERSION1</description>
+                <size>24</size>
+                <resetMask>0x000000</resetMask>
+                <fields>
+                    <field>
+                        <name>DEFAULT_BOOT_VERSION1_R2</name>
+                        <bitRange>[23:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>FLASH_DEVINFO</name>
+                <addressOffset>0x000150</addressOffset>
+                <description>Stores information about external flash device(s). (ECC)
+
+                    Assumed to be valid if BOOT_FLAGS0_FLASH_DEVINFO_ENABLE is set.</description>
+                <size>24</size>
+                <resetValue>0x000000</resetValue>
+                <fields>
+                    <field>
+                        <name>CS1_SIZE</name>
+                        <description>The size of the flash/PSRAM device on chip select 1 (addressable at 0x11000000 through 0x11ffffff).
+
+                            A value of zero is decoded as a size of zero (no device). Nonzero values are decoded as 4kiB &lt;&lt; CS1_SIZE. For example, four megabytes is encoded with a CS1_SIZE value of 10, and 16 megabytes is encoded with a CS1_SIZE value of 12.
+
+                            When BOOT_FLAGS0_FLASH_DEVINFO_ENABLE is not set, a default of zero is used.</description>
+                        <bitRange>[23:12]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NONE</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>8K</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>16K</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>32K</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>64k</name>
+                                <value>4</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>128K</name>
+                                <value>5</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>256K</name>
+                                <value>6</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>512K</name>
+                                <value>7</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>1M</name>
+                                <value>8</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>2M</name>
+                                <value>9</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>4M</name>
+                                <value>10</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>8M</name>
+                                <value>11</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>16M</name>
+                                <value>12</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>CS0_SIZE</name>
+                        <description>The size of the flash/PSRAM device on chip select 0 (addressable at 0x10000000 through 0x10ffffff).
+
+                            A value of zero is decoded as a size of zero (no device). Nonzero values are decoded as 4kiB &lt;&lt; CS0_SIZE. For example, four megabytes is encoded with a CS0_SIZE value of 10, and 16 megabytes is encoded with a CS0_SIZE value of 12.
+
+                            When BOOT_FLAGS0_FLASH_DEVINFO_ENABLE is not set, a default of 12 (16 MiB) is used.</description>
+                        <bitRange>[11:8]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>NONE</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>8K</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>16K</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>32K</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>64k</name>
+                                <value>4</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>128K</name>
+                                <value>5</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>256K</name>
+                                <value>6</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>512K</name>
+                                <value>7</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>1M</name>
+                                <value>8</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>2M</name>
+                                <value>9</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>4M</name>
+                                <value>10</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>8M</name>
+                                <value>11</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>16M</name>
+                                <value>12</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>D8H_ERASE_SUPPORTED</name>
+                        <description>If true, all attached devices are assumed to support (or ignore, in the case of PSRAM) a block erase command with a command prefix of D8h, an erase size of 64 kiB, and a 24-bit address. Almost all 25-series flash devices support this command.
+
+                            If set, the bootrom will use the D8h erase command where it is able, to accelerate bulk erase operations. This makes flash programming faster.
+
+                            When BOOT_FLAGS0_FLASH_DEVINFO_ENABLE is not set, this field defaults to false.</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>CS1_GPIO</name>
+                        <description>Indicate a GPIO number to be used for the secondary flash chip select (CS1), which selects the external QSPI device mapped at system addresses 0x11000000 through 0x11ffffff. There is no such configuration for CS0, as the primary chip select has a dedicated pin.
+
+                            On RP2350 the permissible GPIO numbers are 0, 8, 19 and 47.
+
+                            Ignored if CS1_size is zero. If CS1_SIZE is nonzero, the bootrom will automatically configure this GPIO as a second chip select upon entering the flash boot path, or entering any other path that may use the QSPI flash interface, such as BOOTSEL mode (nsboot).</description>
+                        <bitRange>[5:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>FLASH_PARTITION_SLOT_SIZE</name>
+                <addressOffset>0x000154</addressOffset>
+                <description>Gap between partition table slot 0 and slot 1 at the start of flash (the default size is 4096 bytes) (ECC) Enabled by the OVERRIDE_FLASH_PARTITION_SLOT_SIZE bit in BOOT_FLAGS, the size is 4096 * (value + 1)</description>
+                <size>24</size>
+                <resetMask>0x000000</resetMask>
+                <fields>
+                    <field>
+                        <name>FLASH_PARTITION_SLOT_SIZE</name>
+                        <bitRange>[23:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>BOOTSEL_LED_CFG</name>
+                <addressOffset>0x000158</addressOffset>
+                <description>Pin configuration for LED status, used by USB bootloader. (ECC) 
+                    Must be valid if BOOT_FLAGS0_ENABLE_BOOTSEL_LED is set.</description>
+                <size>24</size>
+                <resetValue>0x000000</resetValue>
+                <fields>
+                    <field>
+                        <name>ACTIVELOW</name>
+                        <description>LED is active-low. (Default: active-high.)</description>
+                        <bitRange>[23:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>PIN</name>
+                        <description>GPIO index to use for bootloader activity LED.</description>
+                        <bitRange>[5:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>BOOTSEL_PLL_CFG</name>
+                <addressOffset>0x00015c</addressOffset>
+                <description>Optional PLL configuration for BOOTSEL mode. (ECC)
+
+                    This should be configured to produce an exact 48 MHz based on the crystal oscillator frequency. User mode software may also use this value to calculate the expected crystal frequency based on an assumed 48 MHz PLL output.
+
+                    If no configuration is given, the crystal is assumed to be 12 MHz.
+
+                    The PLL frequency can be calculated as:
+
+                    PLL out = (XOSC frequency / (REFDIV+1)) x FBDIV / (POSTDIV1 x POSTDIV2)
+
+                    Conversely the crystal frequency can be calculated as:
+
+                    XOSC frequency = 48 MHz x (REFDIV+1) x (POSTDIV1 x POSTDIV2) / FBDIV
+
+                    (Note the  +1 on REFDIV is because the value stored in this OTP location is the actual divisor value minus one.)
+
+                    Used if and only if ENABLE_BOOTSEL_NON_DEFAULT_PLL_XOSC_CFG is set in BOOT_FLAGS0. That bit should be set only after this row and BOOTSEL_XOSC_CFG are both correctly programmed.</description>
+                <size>24</size>
+                <resetValue>0x000000</resetValue>
+                <fields>
+                    <field>
+                        <name>REFDIV</name>
+                        <description>PLL reference divisor, minus one.
+
+                            Programming a value of 0 means a reference divisor of 1. Programming a value of 1 means a reference divisor of 2 (for exceptionally fast XIN inputs)</description>
+                        <bitRange>[23:15]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>POSTDIV2</name>
+                        <description>PLL post-divide 2 divisor, in the range 1..7 inclusive.</description>
+                        <bitRange>[14:12]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>POSTDIV1</name>
+                        <description>PLL post-divide 1 divisor, in the range 1..7 inclusive.</description>
+                        <bitRange>[11:9]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>FBDIV</name>
+                        <description>PLL feedback divisor, in the range 16..320 inclusive.</description>
+                        <bitRange>[8:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>BOOTSEL_XOSC_CFG</name>
+                <addressOffset>0x000160</addressOffset>
+                <description>Non-default crystal oscillator configuration for the USB bootloader. (ECC)
+
+                    These values may also be used by user code configuring the crystal oscillator.
+
+                    Used if and only if ENABLE_BOOTSEL_NON_DEFAULT_PLL_XOSC_CFG is set in BOOT_FLAGS0. That bit should be set only after this row and BOOTSEL_PLL_CFG are both correctly programmed.</description>
+                <size>24</size>
+                <resetValue>0x000000</resetValue>
+                <fields>
+                    <field>
+                        <name>RANGE</name>
+                        <description>Value of the XOSC_CTRL_FREQ_RANGE register.</description>
+                        <bitRange>[23:14]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>1_15MHZ</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>10_30MHZ</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>25_60MHZ</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>40_100MHZ</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>STARTUP</name>
+                        <description>Value of the XOSC_STARTUP register</description>
+                        <bitRange>[13:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>USB_BOOT_FLAGS</name>
+                <addressOffset>0x000164</addressOffset>
+                <description>USB boot specific feature flags (RBIT-3)</description>
+                <size>24</size>
+                <resetValue>0x000000</resetValue>
+                <fields>
+                    <field>
+                        <name>DP_DM_SWAP</name>
+                        <description>Swap DM/DP during USB boot, to support board layouts with mirrored USB routing (deliberate or accidental).</description>
+                        <bitRange>[23:23]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>WHITE_LABEL_ADDR_VALID</name>
+                        <description>valid flag for INFO_UF2_TXT_BOARD_ID_STRDEF entry of the USB_WHITE_LABEL struct (index 15)</description>
+                        <bitRange>[22:22]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>WL_INFO_UF2_TXT_BOARD_ID_STRDEF_VALID</name>
+                        <description>valid flag for the USB_WHITE_LABEL_ADDR field</description>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>WL_INFO_UF2_TXT_MODEL_STRDEF_VALID</name>
+                        <description>valid flag for INFO_UF2_TXT_MODEL_STRDEF entry of the USB_WHITE_LABEL struct (index 14)</description>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>WL_INDEX_HTM_REDIRECT_NAME_STRDEF_VALID</name>
+                        <description>valid flag for INDEX_HTM_REDIRECT_NAME_STRDEF entry of the USB_WHITE_LABEL struct (index 13)</description>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>WL_INDEX_HTM_REDIRECT_URL_STRDEF_VALID</name>
+                        <description>valid flag for INDEX_HTM_REDIRECT_URL_STRDEF entry of the USB_WHITE_LABEL struct (index 12)</description>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>WL_SCSI_INQUIRY_VERSION_STRDEF_VALID</name>
+                        <description>valid flag for SCSI_INQUIRY_VERSION_STRDEF entry of the USB_WHITE_LABEL struct (index 11)</description>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>WL_SCSI_INQUIRY_PRODUCT_STRDEF_VALID</name>
+                        <description>valid flag for SCSI_INQUIRY_PRODUCT_STRDEF entry of the USB_WHITE_LABEL struct (index 10)</description>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>WL_SCSI_INQUIRY_VENDOR_STRDEF_VALID</name>
+                        <description>valid flag for SCSI_INQUIRY_VENDOR_STRDEF entry of the USB_WHITE_LABEL struct (index 9)</description>
+                        <bitRange>[9:9]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>WL_VOLUME_LABEL_STRDEF_VALID</name>
+                        <description>valid flag for VOLUME_LABEL_STRDEF entry of the USB_WHITE_LABEL struct (index 8)</description>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>WL_USB_CONFIG_ATTRIBUTES_MAX_POWER_VALUES_VALID</name>
+                        <description>valid flag for USB_CONFIG_ATTRIBUTES_MAX_POWER_VALUES entry of the USB_WHITE_LABEL struct (index 7)</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>WL_USB_DEVICE_SERIAL_NUMBER_STRDEF_VALID</name>
+                        <description>valid flag for USB_DEVICE_SERIAL_NUMBER_STRDEF entry of the USB_WHITE_LABEL struct (index 6)</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>WL_USB_DEVICE_PRODUCT_STRDEF_VALID</name>
+                        <description>valid flag for USB_DEVICE_PRODUCT_STRDEF entry of the USB_WHITE_LABEL struct (index 5)</description>
+                        <bitRange>[5:5]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>WL_USB_DEVICE_MANUFACTURER_STRDEF_VALID</name>
+                        <description>valid flag for USB_DEVICE_MANUFACTURER_STRDEF entry of the USB_WHITE_LABEL struct (index 4)</description>
+                        <bitRange>[4:4]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>WL_USB_DEVICE_LANG_ID_VALUE_VALID</name>
+                        <description>valid flag for USB_DEVICE_LANG_ID_VALUE entry of the USB_WHITE_LABEL struct (index 3)</description>
+                        <bitRange>[3:3]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>WL_USB_DEVICE_SERIAL_NUMBER_VALUE_VALID</name>
+                        <description>valid flag for USB_DEVICE_BCD_DEVICEVALUE entry of the USB_WHITE_LABEL struct (index 2)</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>WL_USB_DEVICE_PID_VALUE_VALID</name>
+                        <description>valid flag for USB_DEVICE_PID_VALUE entry of the USB_WHITE_LABEL struct (index 1)</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>WL_USB_DEVICE_VID_VALUE_VALID</name>
+                        <description>valid flag for USB_DEVICE_VID_VALUE entry of the USB_WHITE_LABEL struct (index 0)</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>USB_BOOT_FLAGS_R1</name>
+                <addressOffset>0x000168</addressOffset>
+                <description>Redundant copy of USB_BOOT_FLAGS</description>
+                <size>24</size>
+                <resetMask>0x000000</resetMask>
+                <fields>
+                    <field>
+                        <name>USB_BOOT_FLAGS_R1</name>
+                        <bitRange>[23:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>USB_BOOT_FLAGS_R2</name>
+                <addressOffset>0x00016c</addressOffset>
+                <description>Redundant copy of USB_BOOT_FLAGS</description>
+                <size>24</size>
+                <resetMask>0x000000</resetMask>
+                <fields>
+                    <field>
+                        <name>USB_BOOT_FLAGS_R2</name>
+                        <bitRange>[23:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>USB_WHITE_LABEL_ADDR</name>
+                <addressOffset>0x000170</addressOffset>
+                <description>Row index of the USB_WHITE_LABEL structure within OTP (ECC)
+
+                    The table has 16 rows, each of which are also ECC and marked valid by the corresponding valid bit in USB_BOOT_FLAGS (ECC).
+
+                    The entries are either _VALUEs where the 16 bit value is used as is, or _STRDEFs which acts as a pointers to a string value.
+
+                    The value stored in a _STRDEF is two separate bytes: The low seven bits of the first (LSB) byte indicates the number of characters in the string, and the top bit of the first (LSB) byte if set to indicate that each character in the string is two bytes (Unicode) versus one byte if unset. The second (MSB) byte represents the location of the string data, and is encoded as the number of rows from this USB_WHITE_LABEL_ADDR; i.e. the row of the start of the string is USB_WHITE_LABEL_ADDR value + msb_byte.
+
+                    In each case, the corresponding valid bit enables replacing the default value for the corresponding item provided by the boot rom.
+
+                    Note that Unicode _STRDEFs are only supported for USB_DEVICE_PRODUCT_STRDEF, USB_DEVICE_SERIAL_NUMBER_STRDEF and USB_DEVICE_MANUFACTURER_STRDEF. Unicode values will be ignored if specified for other fields, and non-unicode values for these three items will be converted to Unicode characters by setting the upper 8 bits to zero.
+
+                    Note that if the USB_WHITE_LABEL structure or the corresponding strings are not readable by BOOTSEL mode based on OTP permissions, or if alignment requirements are not met, then the corresponding default values are used.
+
+                    The index values indicate where each field is located (row USB_WHITE_LABEL_ADDR value + index):</description>
+                <size>24</size>
+                <resetMask>0x000000</resetMask>
+                <fields>
+                    <field>
+                        <name>USB_WHITE_LABEL_ADDR</name>
+                        <bitRange>[23:0]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>INDEX_USB_DEVICE_VID_VALUE</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INDEX_USB_DEVICE_PID_VALUE</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INDEX_USB_DEVICE_BCD_DEVICE_VALUE</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INDEX_USB_DEVICE_LANG_ID_VALUE</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INDEX_USB_DEVICE_MANUFACTURER_STRDEF</name>
+                                <value>4</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INDEX_USB_DEVICE_PRODUCT_STRDEF</name>
+                                <value>5</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INDEX_USB_DEVICE_SERIAL_NUMBER_STRDEF</name>
+                                <value>6</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INDEX_USB_CONFIG_ATTRIBUTES_MAX_POWER_VALUES</name>
+                                <value>7</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INDEX_VOLUME_LABEL_STRDEF</name>
+                                <value>8</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INDEX_SCSI_INQUIRY_VENDOR_STRDEF</name>
+                                <value>9</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INDEX_SCSI_INQUIRY_PRODUCT_STRDEF</name>
+                                <value>10</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INDEX_SCSI_INQUIRY_VERSION_STRDEF</name>
+                                <value>11</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INDEX_INDEX_HTM_REDIRECT_URL_STRDEF</name>
+                                <value>12</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INDEX_INDEX_HTM_REDIRECT_NAME_STRDEF</name>
+                                <value>13</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INDEX_INFO_UF2_TXT_MODEL_STRDEF</name>
+                                <value>14</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>INDEX_INFO_UF2_TXT_BOARD_ID_STRDEF</name>
+                                <value>15</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>OTPBOOT_SRC</name>
+                <addressOffset>0x000178</addressOffset>
+                <description>OTP start row for the OTP boot image. (ECC)
+
+                    If OTP boot is enabled, the bootrom will load from this location into SRAM and then directly enter the loaded image. Note that the image must be signed if SECURE_BOOT_ENABLE is set. The image itself is assumed to be ECC-protected.
+
+                    This must be an even number. Equivalently, the OTP boot image must start at a word-aligned location in the ECC read data address window.</description>
+                <size>24</size>
+                <resetMask>0x000000</resetMask>
+                <fields>
+                    <field>
+                        <name>OTPBOOT_SRC</name>
+                        <bitRange>[23:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>OTPBOOT_LEN</name>
+                <addressOffset>0x00017c</addressOffset>
+                <description>Length in rows of the OTP boot image. (ECC)
+
+                    OTPBOOT_LEN must be even. The total image size must be a multiple of 4 bytes (32 bits).</description>
+                <size>24</size>
+                <resetMask>0x000000</resetMask>
+                <fields>
+                    <field>
+                        <name>OTPBOOT_LEN</name>
+                        <bitRange>[23:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>OTPBOOT_DST0</name>
+                <addressOffset>0x000180</addressOffset>
+                <description>Bits 15:0 of the OTP boot image load destination (and entry point). (ECC)
+
+                    This must be a location in main SRAM (main SRAM is addresses 0x20000000 through 0x20082000) and must be word-aligned.</description>
+                <size>24</size>
+                <resetMask>0x000000</resetMask>
+                <fields>
+                    <field>
+                        <name>OTPBOOT_DST0</name>
+                        <bitRange>[23:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>OTPBOOT_DST1</name>
+                <addressOffset>0x000184</addressOffset>
+                <description>Bits 31:16 of the OTP boot image load destination (and entry point). (ECC)
+
+                    This must be a location in main SRAM (main SRAM is addresses 0x20000000 through 0x20082000) and must be word-aligned.</description>
+                <size>24</size>
+                <resetMask>0x000000</resetMask>
+                <fields>
+                    <field>
+                        <name>OTPBOOT_DST1</name>
+                        <bitRange>[23:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>BOOTKEY0_0</name>
+                <addressOffset>0x000200</addressOffset>
+                <description>Bits 15:0 of SHA-256 hash of boot key 0 (ECC)</description>
+                <size>24</size>
+                <resetMask>0x000000</resetMask>
+                <fields>
+                    <field>
+                        <name>BOOTKEY0_0</name>
+                        <bitRange>[23:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>BOOTKEY0_1</name>
+                <addressOffset>0x000204</addressOffset>
+                <description>Bits 31:16 of SHA-256 hash of boot key 0 (ECC)</description>
+                <size>24</size>
+                <resetMask>0x000000</resetMask>
+                <fields>
+                    <field>
+                        <name>BOOTKEY0_1</name>
+                        <bitRange>[23:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>BOOTKEY0_2</name>
+                <addressOffset>0x000208</addressOffset>
+                <description>Bits 47:32 of SHA-256 hash of boot key 0 (ECC)</description>
+                <size>24</size>
+                <resetMask>0x000000</resetMask>
+                <fields>
+                    <field>
+                        <name>BOOTKEY0_2</name>
+                        <bitRange>[23:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>BOOTKEY0_3</name>
+                <addressOffset>0x00020c</addressOffset>
+                <description>Bits 63:48 of SHA-256 hash of boot key 0 (ECC)</description>
+                <size>24</size>
+                <resetMask>0x000000</resetMask>
+                <fields>
+                    <field>
+                        <name>BOOTKEY0_3</name>
+                        <bitRange>[23:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>BOOTKEY0_4</name>
+                <addressOffset>0x000210</addressOffset>
+                <description>Bits 79:64 of SHA-256 hash of boot key 0 (ECC)</description>
+                <size>24</size>
+                <resetMask>0x000000</resetMask>
+                <fields>
+                    <field>
+                        <name>BOOTKEY0_4</name>
+                        <bitRange>[23:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>BOOTKEY0_5</name>
+                <addressOffset>0x000214</addressOffset>
+                <description>Bits 95:80 of SHA-256 hash of boot key 0 (ECC)</description>
+                <size>24</size>
+                <resetMask>0x000000</resetMask>
+                <fields>
+                    <field>
+                        <name>BOOTKEY0_5</name>
+                        <bitRange>[23:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>BOOTKEY0_6</name>
+                <addressOffset>0x000218</addressOffset>
+                <description>Bits 111:96 of SHA-256 hash of boot key 0 (ECC)</description>
+                <size>24</size>
+                <resetMask>0x000000</resetMask>
+                <fields>
+                    <field>
+                        <name>BOOTKEY0_6</name>
+                        <bitRange>[23:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>BOOTKEY0_7</name>
+                <addressOffset>0x00021c</addressOffset>
+                <description>Bits 127:112 of SHA-256 hash of boot key 0 (ECC)</description>
+                <size>24</size>
+                <resetMask>0x000000</resetMask>
+                <fields>
+                    <field>
+                        <name>BOOTKEY0_7</name>
+                        <bitRange>[23:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>BOOTKEY0_8</name>
+                <addressOffset>0x000220</addressOffset>
+                <description>Bits 143:128 of SHA-256 hash of boot key 0 (ECC)</description>
+                <size>24</size>
+                <resetMask>0x000000</resetMask>
+                <fields>
+                    <field>
+                        <name>BOOTKEY0_8</name>
+                        <bitRange>[23:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>BOOTKEY0_9</name>
+                <addressOffset>0x000224</addressOffset>
+                <description>Bits 159:144 of SHA-256 hash of boot key 0 (ECC)</description>
+                <size>24</size>
+                <resetMask>0x000000</resetMask>
+                <fields>
+                    <field>
+                        <name>BOOTKEY0_9</name>
+                        <bitRange>[23:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>BOOTKEY0_10</name>
+                <addressOffset>0x000228</addressOffset>
+                <description>Bits 175:160 of SHA-256 hash of boot key 0 (ECC)</description>
+                <size>24</size>
+                <resetMask>0x000000</resetMask>
+                <fields>
+                    <field>
+                        <name>BOOTKEY0_10</name>
+                        <bitRange>[23:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>BOOTKEY0_11</name>
+                <addressOffset>0x00022c</addressOffset>
+                <description>Bits 191:176 of SHA-256 hash of boot key 0 (ECC)</description>
+                <size>24</size>
+                <resetMask>0x000000</resetMask>
+                <fields>
+                    <field>
+                        <name>BOOTKEY0_11</name>
+                        <bitRange>[23:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>BOOTKEY0_12</name>
+                <addressOffset>0x000230</addressOffset>
+                <description>Bits 207:192 of SHA-256 hash of boot key 0 (ECC)</description>
+                <size>24</size>
+                <resetMask>0x000000</resetMask>
+                <fields>
+                    <field>
+                        <name>BOOTKEY0_12</name>
+                        <bitRange>[23:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>BOOTKEY0_13</name>
+                <addressOffset>0x000234</addressOffset>
+                <description>Bits 223:208 of SHA-256 hash of boot key 0 (ECC)</description>
+                <size>24</size>
+                <resetMask>0x000000</resetMask>
+                <fields>
+                    <field>
+                        <name>BOOTKEY0_13</name>
+                        <bitRange>[23:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>BOOTKEY0_14</name>
+                <addressOffset>0x000238</addressOffset>
+                <description>Bits 239:224 of SHA-256 hash of boot key 0 (ECC)</description>
+                <size>24</size>
+                <resetMask>0x000000</resetMask>
+                <fields>
+                    <field>
+                        <name>BOOTKEY0_14</name>
+                        <bitRange>[23:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>BOOTKEY0_15</name>
+                <addressOffset>0x00023c</addressOffset>
+                <description>Bits 255:240 of SHA-256 hash of boot key 0 (ECC)</description>
+                <size>24</size>
+                <resetMask>0x000000</resetMask>
+                <fields>
+                    <field>
+                        <name>BOOTKEY0_15</name>
+                        <bitRange>[23:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>BOOTKEY1_0</name>
+                <addressOffset>0x000240</addressOffset>
+                <description>Bits 15:0 of SHA-256 hash of boot key 1 (ECC)</description>
+                <size>24</size>
+                <resetMask>0x000000</resetMask>
+                <fields>
+                    <field>
+                        <name>BOOTKEY1_0</name>
+                        <bitRange>[23:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>BOOTKEY1_1</name>
+                <addressOffset>0x000244</addressOffset>
+                <description>Bits 31:16 of SHA-256 hash of boot key 1 (ECC)</description>
+                <size>24</size>
+                <resetMask>0x000000</resetMask>
+                <fields>
+                    <field>
+                        <name>BOOTKEY1_1</name>
+                        <bitRange>[23:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>BOOTKEY1_2</name>
+                <addressOffset>0x000248</addressOffset>
+                <description>Bits 47:32 of SHA-256 hash of boot key 1 (ECC)</description>
+                <size>24</size>
+                <resetMask>0x000000</resetMask>
+                <fields>
+                    <field>
+                        <name>BOOTKEY1_2</name>
+                        <bitRange>[23:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>BOOTKEY1_3</name>
+                <addressOffset>0x00024c</addressOffset>
+                <description>Bits 63:48 of SHA-256 hash of boot key 1 (ECC)</description>
+                <size>24</size>
+                <resetMask>0x000000</resetMask>
+                <fields>
+                    <field>
+                        <name>BOOTKEY1_3</name>
+                        <bitRange>[23:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>BOOTKEY1_4</name>
+                <addressOffset>0x000250</addressOffset>
+                <description>Bits 79:64 of SHA-256 hash of boot key 1 (ECC)</description>
+                <size>24</size>
+                <resetMask>0x000000</resetMask>
+                <fields>
+                    <field>
+                        <name>BOOTKEY1_4</name>
+                        <bitRange>[23:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>BOOTKEY1_5</name>
+                <addressOffset>0x000254</addressOffset>
+                <description>Bits 95:80 of SHA-256 hash of boot key 1 (ECC)</description>
+                <size>24</size>
+                <resetMask>0x000000</resetMask>
+                <fields>
+                    <field>
+                        <name>BOOTKEY1_5</name>
+                        <bitRange>[23:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>BOOTKEY1_6</name>
+                <addressOffset>0x000258</addressOffset>
+                <description>Bits 111:96 of SHA-256 hash of boot key 1 (ECC)</description>
+                <size>24</size>
+                <resetMask>0x000000</resetMask>
+                <fields>
+                    <field>
+                        <name>BOOTKEY1_6</name>
+                        <bitRange>[23:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>BOOTKEY1_7</name>
+                <addressOffset>0x00025c</addressOffset>
+                <description>Bits 127:112 of SHA-256 hash of boot key 1 (ECC)</description>
+                <size>24</size>
+                <resetMask>0x000000</resetMask>
+                <fields>
+                    <field>
+                        <name>BOOTKEY1_7</name>
+                        <bitRange>[23:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>BOOTKEY1_8</name>
+                <addressOffset>0x000260</addressOffset>
+                <description>Bits 143:128 of SHA-256 hash of boot key 1 (ECC)</description>
+                <size>24</size>
+                <resetMask>0x000000</resetMask>
+                <fields>
+                    <field>
+                        <name>BOOTKEY1_8</name>
+                        <bitRange>[23:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>BOOTKEY1_9</name>
+                <addressOffset>0x000264</addressOffset>
+                <description>Bits 159:144 of SHA-256 hash of boot key 1 (ECC)</description>
+                <size>24</size>
+                <resetMask>0x000000</resetMask>
+                <fields>
+                    <field>
+                        <name>BOOTKEY1_9</name>
+                        <bitRange>[23:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>BOOTKEY1_10</name>
+                <addressOffset>0x000268</addressOffset>
+                <description>Bits 175:160 of SHA-256 hash of boot key 1 (ECC)</description>
+                <size>24</size>
+                <resetMask>0x000000</resetMask>
+                <fields>
+                    <field>
+                        <name>BOOTKEY1_10</name>
+                        <bitRange>[23:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>BOOTKEY1_11</name>
+                <addressOffset>0x00026c</addressOffset>
+                <description>Bits 191:176 of SHA-256 hash of boot key 1 (ECC)</description>
+                <size>24</size>
+                <resetMask>0x000000</resetMask>
+                <fields>
+                    <field>
+                        <name>BOOTKEY1_11</name>
+                        <bitRange>[23:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>BOOTKEY1_12</name>
+                <addressOffset>0x000270</addressOffset>
+                <description>Bits 207:192 of SHA-256 hash of boot key 1 (ECC)</description>
+                <size>24</size>
+                <resetMask>0x000000</resetMask>
+                <fields>
+                    <field>
+                        <name>BOOTKEY1_12</name>
+                        <bitRange>[23:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>BOOTKEY1_13</name>
+                <addressOffset>0x000274</addressOffset>
+                <description>Bits 223:208 of SHA-256 hash of boot key 1 (ECC)</description>
+                <size>24</size>
+                <resetMask>0x000000</resetMask>
+                <fields>
+                    <field>
+                        <name>BOOTKEY1_13</name>
+                        <bitRange>[23:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>BOOTKEY1_14</name>
+                <addressOffset>0x000278</addressOffset>
+                <description>Bits 239:224 of SHA-256 hash of boot key 1 (ECC)</description>
+                <size>24</size>
+                <resetMask>0x000000</resetMask>
+                <fields>
+                    <field>
+                        <name>BOOTKEY1_14</name>
+                        <bitRange>[23:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>BOOTKEY1_15</name>
+                <addressOffset>0x00027c</addressOffset>
+                <description>Bits 255:240 of SHA-256 hash of boot key 1 (ECC)</description>
+                <size>24</size>
+                <resetMask>0x000000</resetMask>
+                <fields>
+                    <field>
+                        <name>BOOTKEY1_15</name>
+                        <bitRange>[23:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>BOOTKEY2_0</name>
+                <addressOffset>0x000280</addressOffset>
+                <description>Bits 15:0 of SHA-256 hash of boot key 2 (ECC)</description>
+                <size>24</size>
+                <resetMask>0x000000</resetMask>
+                <fields>
+                    <field>
+                        <name>BOOTKEY2_0</name>
+                        <bitRange>[23:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>BOOTKEY2_1</name>
+                <addressOffset>0x000284</addressOffset>
+                <description>Bits 31:16 of SHA-256 hash of boot key 2 (ECC)</description>
+                <size>24</size>
+                <resetMask>0x000000</resetMask>
+                <fields>
+                    <field>
+                        <name>BOOTKEY2_1</name>
+                        <bitRange>[23:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>BOOTKEY2_2</name>
+                <addressOffset>0x000288</addressOffset>
+                <description>Bits 47:32 of SHA-256 hash of boot key 2 (ECC)</description>
+                <size>24</size>
+                <resetMask>0x000000</resetMask>
+                <fields>
+                    <field>
+                        <name>BOOTKEY2_2</name>
+                        <bitRange>[23:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>BOOTKEY2_3</name>
+                <addressOffset>0x00028c</addressOffset>
+                <description>Bits 63:48 of SHA-256 hash of boot key 2 (ECC)</description>
+                <size>24</size>
+                <resetMask>0x000000</resetMask>
+                <fields>
+                    <field>
+                        <name>BOOTKEY2_3</name>
+                        <bitRange>[23:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>BOOTKEY2_4</name>
+                <addressOffset>0x000290</addressOffset>
+                <description>Bits 79:64 of SHA-256 hash of boot key 2 (ECC)</description>
+                <size>24</size>
+                <resetMask>0x000000</resetMask>
+                <fields>
+                    <field>
+                        <name>BOOTKEY2_4</name>
+                        <bitRange>[23:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>BOOTKEY2_5</name>
+                <addressOffset>0x000294</addressOffset>
+                <description>Bits 95:80 of SHA-256 hash of boot key 2 (ECC)</description>
+                <size>24</size>
+                <resetMask>0x000000</resetMask>
+                <fields>
+                    <field>
+                        <name>BOOTKEY2_5</name>
+                        <bitRange>[23:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>BOOTKEY2_6</name>
+                <addressOffset>0x000298</addressOffset>
+                <description>Bits 111:96 of SHA-256 hash of boot key 2 (ECC)</description>
+                <size>24</size>
+                <resetMask>0x000000</resetMask>
+                <fields>
+                    <field>
+                        <name>BOOTKEY2_6</name>
+                        <bitRange>[23:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>BOOTKEY2_7</name>
+                <addressOffset>0x00029c</addressOffset>
+                <description>Bits 127:112 of SHA-256 hash of boot key 2 (ECC)</description>
+                <size>24</size>
+                <resetMask>0x000000</resetMask>
+                <fields>
+                    <field>
+                        <name>BOOTKEY2_7</name>
+                        <bitRange>[23:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>BOOTKEY2_8</name>
+                <addressOffset>0x0002a0</addressOffset>
+                <description>Bits 143:128 of SHA-256 hash of boot key 2 (ECC)</description>
+                <size>24</size>
+                <resetMask>0x000000</resetMask>
+                <fields>
+                    <field>
+                        <name>BOOTKEY2_8</name>
+                        <bitRange>[23:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>BOOTKEY2_9</name>
+                <addressOffset>0x0002a4</addressOffset>
+                <description>Bits 159:144 of SHA-256 hash of boot key 2 (ECC)</description>
+                <size>24</size>
+                <resetMask>0x000000</resetMask>
+                <fields>
+                    <field>
+                        <name>BOOTKEY2_9</name>
+                        <bitRange>[23:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>BOOTKEY2_10</name>
+                <addressOffset>0x0002a8</addressOffset>
+                <description>Bits 175:160 of SHA-256 hash of boot key 2 (ECC)</description>
+                <size>24</size>
+                <resetMask>0x000000</resetMask>
+                <fields>
+                    <field>
+                        <name>BOOTKEY2_10</name>
+                        <bitRange>[23:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>BOOTKEY2_11</name>
+                <addressOffset>0x0002ac</addressOffset>
+                <description>Bits 191:176 of SHA-256 hash of boot key 2 (ECC)</description>
+                <size>24</size>
+                <resetMask>0x000000</resetMask>
+                <fields>
+                    <field>
+                        <name>BOOTKEY2_11</name>
+                        <bitRange>[23:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>BOOTKEY2_12</name>
+                <addressOffset>0x0002b0</addressOffset>
+                <description>Bits 207:192 of SHA-256 hash of boot key 2 (ECC)</description>
+                <size>24</size>
+                <resetMask>0x000000</resetMask>
+                <fields>
+                    <field>
+                        <name>BOOTKEY2_12</name>
+                        <bitRange>[23:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>BOOTKEY2_13</name>
+                <addressOffset>0x0002b4</addressOffset>
+                <description>Bits 223:208 of SHA-256 hash of boot key 2 (ECC)</description>
+                <size>24</size>
+                <resetMask>0x000000</resetMask>
+                <fields>
+                    <field>
+                        <name>BOOTKEY2_13</name>
+                        <bitRange>[23:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>BOOTKEY2_14</name>
+                <addressOffset>0x0002b8</addressOffset>
+                <description>Bits 239:224 of SHA-256 hash of boot key 2 (ECC)</description>
+                <size>24</size>
+                <resetMask>0x000000</resetMask>
+                <fields>
+                    <field>
+                        <name>BOOTKEY2_14</name>
+                        <bitRange>[23:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>BOOTKEY2_15</name>
+                <addressOffset>0x0002bc</addressOffset>
+                <description>Bits 255:240 of SHA-256 hash of boot key 2 (ECC)</description>
+                <size>24</size>
+                <resetMask>0x000000</resetMask>
+                <fields>
+                    <field>
+                        <name>BOOTKEY2_15</name>
+                        <bitRange>[23:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>BOOTKEY3_0</name>
+                <addressOffset>0x0002c0</addressOffset>
+                <description>Bits 15:0 of SHA-256 hash of boot key 3 (ECC)</description>
+                <size>24</size>
+                <resetMask>0x000000</resetMask>
+                <fields>
+                    <field>
+                        <name>BOOTKEY3_0</name>
+                        <bitRange>[23:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>BOOTKEY3_1</name>
+                <addressOffset>0x0002c4</addressOffset>
+                <description>Bits 31:16 of SHA-256 hash of boot key 3 (ECC)</description>
+                <size>24</size>
+                <resetMask>0x000000</resetMask>
+                <fields>
+                    <field>
+                        <name>BOOTKEY3_1</name>
+                        <bitRange>[23:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>BOOTKEY3_2</name>
+                <addressOffset>0x0002c8</addressOffset>
+                <description>Bits 47:32 of SHA-256 hash of boot key 3 (ECC)</description>
+                <size>24</size>
+                <resetMask>0x000000</resetMask>
+                <fields>
+                    <field>
+                        <name>BOOTKEY3_2</name>
+                        <bitRange>[23:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>BOOTKEY3_3</name>
+                <addressOffset>0x0002cc</addressOffset>
+                <description>Bits 63:48 of SHA-256 hash of boot key 3 (ECC)</description>
+                <size>24</size>
+                <resetMask>0x000000</resetMask>
+                <fields>
+                    <field>
+                        <name>BOOTKEY3_3</name>
+                        <bitRange>[23:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>BOOTKEY3_4</name>
+                <addressOffset>0x0002d0</addressOffset>
+                <description>Bits 79:64 of SHA-256 hash of boot key 3 (ECC)</description>
+                <size>24</size>
+                <resetMask>0x000000</resetMask>
+                <fields>
+                    <field>
+                        <name>BOOTKEY3_4</name>
+                        <bitRange>[23:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>BOOTKEY3_5</name>
+                <addressOffset>0x0002d4</addressOffset>
+                <description>Bits 95:80 of SHA-256 hash of boot key 3 (ECC)</description>
+                <size>24</size>
+                <resetMask>0x000000</resetMask>
+                <fields>
+                    <field>
+                        <name>BOOTKEY3_5</name>
+                        <bitRange>[23:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>BOOTKEY3_6</name>
+                <addressOffset>0x0002d8</addressOffset>
+                <description>Bits 111:96 of SHA-256 hash of boot key 3 (ECC)</description>
+                <size>24</size>
+                <resetMask>0x000000</resetMask>
+                <fields>
+                    <field>
+                        <name>BOOTKEY3_6</name>
+                        <bitRange>[23:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>BOOTKEY3_7</name>
+                <addressOffset>0x0002dc</addressOffset>
+                <description>Bits 127:112 of SHA-256 hash of boot key 3 (ECC)</description>
+                <size>24</size>
+                <resetMask>0x000000</resetMask>
+                <fields>
+                    <field>
+                        <name>BOOTKEY3_7</name>
+                        <bitRange>[23:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>BOOTKEY3_8</name>
+                <addressOffset>0x0002e0</addressOffset>
+                <description>Bits 143:128 of SHA-256 hash of boot key 3 (ECC)</description>
+                <size>24</size>
+                <resetMask>0x000000</resetMask>
+                <fields>
+                    <field>
+                        <name>BOOTKEY3_8</name>
+                        <bitRange>[23:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>BOOTKEY3_9</name>
+                <addressOffset>0x0002e4</addressOffset>
+                <description>Bits 159:144 of SHA-256 hash of boot key 3 (ECC)</description>
+                <size>24</size>
+                <resetMask>0x000000</resetMask>
+                <fields>
+                    <field>
+                        <name>BOOTKEY3_9</name>
+                        <bitRange>[23:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>BOOTKEY3_10</name>
+                <addressOffset>0x0002e8</addressOffset>
+                <description>Bits 175:160 of SHA-256 hash of boot key 3 (ECC)</description>
+                <size>24</size>
+                <resetMask>0x000000</resetMask>
+                <fields>
+                    <field>
+                        <name>BOOTKEY3_10</name>
+                        <bitRange>[23:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>BOOTKEY3_11</name>
+                <addressOffset>0x0002ec</addressOffset>
+                <description>Bits 191:176 of SHA-256 hash of boot key 3 (ECC)</description>
+                <size>24</size>
+                <resetMask>0x000000</resetMask>
+                <fields>
+                    <field>
+                        <name>BOOTKEY3_11</name>
+                        <bitRange>[23:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>BOOTKEY3_12</name>
+                <addressOffset>0x0002f0</addressOffset>
+                <description>Bits 207:192 of SHA-256 hash of boot key 3 (ECC)</description>
+                <size>24</size>
+                <resetMask>0x000000</resetMask>
+                <fields>
+                    <field>
+                        <name>BOOTKEY3_12</name>
+                        <bitRange>[23:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>BOOTKEY3_13</name>
+                <addressOffset>0x0002f4</addressOffset>
+                <description>Bits 223:208 of SHA-256 hash of boot key 3 (ECC)</description>
+                <size>24</size>
+                <resetMask>0x000000</resetMask>
+                <fields>
+                    <field>
+                        <name>BOOTKEY3_13</name>
+                        <bitRange>[23:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>BOOTKEY3_14</name>
+                <addressOffset>0x0002f8</addressOffset>
+                <description>Bits 239:224 of SHA-256 hash of boot key 3 (ECC)</description>
+                <size>24</size>
+                <resetMask>0x000000</resetMask>
+                <fields>
+                    <field>
+                        <name>BOOTKEY3_14</name>
+                        <bitRange>[23:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>BOOTKEY3_15</name>
+                <addressOffset>0x0002fc</addressOffset>
+                <description>Bits 255:240 of SHA-256 hash of boot key 3 (ECC)</description>
+                <size>24</size>
+                <resetMask>0x000000</resetMask>
+                <fields>
+                    <field>
+                        <name>BOOTKEY3_15</name>
+                        <bitRange>[23:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>KEY1_0</name>
+                <addressOffset>0x003d20</addressOffset>
+                <description>Bits 15:0 of OTP access key 1 (ECC)</description>
+                <size>24</size>
+                <resetMask>0x000000</resetMask>
+                <fields>
+                    <field>
+                        <name>KEY1_0</name>
+                        <bitRange>[23:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>KEY1_1</name>
+                <addressOffset>0x003d24</addressOffset>
+                <description>Bits 31:16 of OTP access key 1 (ECC)</description>
+                <size>24</size>
+                <resetMask>0x000000</resetMask>
+                <fields>
+                    <field>
+                        <name>KEY1_1</name>
+                        <bitRange>[23:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>KEY1_2</name>
+                <addressOffset>0x003d28</addressOffset>
+                <description>Bits 47:32 of OTP access key 1 (ECC)</description>
+                <size>24</size>
+                <resetMask>0x000000</resetMask>
+                <fields>
+                    <field>
+                        <name>KEY1_2</name>
+                        <bitRange>[23:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>KEY1_3</name>
+                <addressOffset>0x003d2c</addressOffset>
+                <description>Bits 63:48 of OTP access key 1 (ECC)</description>
+                <size>24</size>
+                <resetMask>0x000000</resetMask>
+                <fields>
+                    <field>
+                        <name>KEY1_3</name>
+                        <bitRange>[23:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>KEY1_4</name>
+                <addressOffset>0x003d30</addressOffset>
+                <description>Bits 79:64 of OTP access key 1 (ECC)</description>
+                <size>24</size>
+                <resetMask>0x000000</resetMask>
+                <fields>
+                    <field>
+                        <name>KEY1_4</name>
+                        <bitRange>[23:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>KEY1_5</name>
+                <addressOffset>0x003d34</addressOffset>
+                <description>Bits 95:80 of OTP access key 1 (ECC)</description>
+                <size>24</size>
+                <resetMask>0x000000</resetMask>
+                <fields>
+                    <field>
+                        <name>KEY1_5</name>
+                        <bitRange>[23:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>KEY1_6</name>
+                <addressOffset>0x003d38</addressOffset>
+                <description>Bits 111:96 of OTP access key 1 (ECC)</description>
+                <size>24</size>
+                <resetMask>0x000000</resetMask>
+                <fields>
+                    <field>
+                        <name>KEY1_6</name>
+                        <bitRange>[23:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>KEY1_7</name>
+                <addressOffset>0x003d3c</addressOffset>
+                <description>Bits 127:112 of OTP access key 1 (ECC)</description>
+                <size>24</size>
+                <resetMask>0x000000</resetMask>
+                <fields>
+                    <field>
+                        <name>KEY1_7</name>
+                        <bitRange>[23:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>KEY2_0</name>
+                <addressOffset>0x003d40</addressOffset>
+                <description>Bits 15:0 of OTP access key 2 (ECC)</description>
+                <size>24</size>
+                <resetMask>0x000000</resetMask>
+                <fields>
+                    <field>
+                        <name>KEY2_0</name>
+                        <bitRange>[23:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>KEY2_1</name>
+                <addressOffset>0x003d44</addressOffset>
+                <description>Bits 31:16 of OTP access key 2 (ECC)</description>
+                <size>24</size>
+                <resetMask>0x000000</resetMask>
+                <fields>
+                    <field>
+                        <name>KEY2_1</name>
+                        <bitRange>[23:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>KEY2_2</name>
+                <addressOffset>0x003d48</addressOffset>
+                <description>Bits 47:32 of OTP access key 2 (ECC)</description>
+                <size>24</size>
+                <resetMask>0x000000</resetMask>
+                <fields>
+                    <field>
+                        <name>KEY2_2</name>
+                        <bitRange>[23:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>KEY2_3</name>
+                <addressOffset>0x003d4c</addressOffset>
+                <description>Bits 63:48 of OTP access key 2 (ECC)</description>
+                <size>24</size>
+                <resetMask>0x000000</resetMask>
+                <fields>
+                    <field>
+                        <name>KEY2_3</name>
+                        <bitRange>[23:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>KEY2_4</name>
+                <addressOffset>0x003d50</addressOffset>
+                <description>Bits 79:64 of OTP access key 2 (ECC)</description>
+                <size>24</size>
+                <resetMask>0x000000</resetMask>
+                <fields>
+                    <field>
+                        <name>KEY2_4</name>
+                        <bitRange>[23:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>KEY2_5</name>
+                <addressOffset>0x003d54</addressOffset>
+                <description>Bits 95:80 of OTP access key 2 (ECC)</description>
+                <size>24</size>
+                <resetMask>0x000000</resetMask>
+                <fields>
+                    <field>
+                        <name>KEY2_5</name>
+                        <bitRange>[23:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>KEY2_6</name>
+                <addressOffset>0x003d58</addressOffset>
+                <description>Bits 111:96 of OTP access key 2 (ECC)</description>
+                <size>24</size>
+                <resetMask>0x000000</resetMask>
+                <fields>
+                    <field>
+                        <name>KEY2_6</name>
+                        <bitRange>[23:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>KEY2_7</name>
+                <addressOffset>0x003d5c</addressOffset>
+                <description>Bits 127:112 of OTP access key 2 (ECC)</description>
+                <size>24</size>
+                <resetMask>0x000000</resetMask>
+                <fields>
+                    <field>
+                        <name>KEY2_7</name>
+                        <bitRange>[23:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>KEY3_0</name>
+                <addressOffset>0x003d60</addressOffset>
+                <description>Bits 15:0 of OTP access key 3 (ECC)</description>
+                <size>24</size>
+                <resetMask>0x000000</resetMask>
+                <fields>
+                    <field>
+                        <name>KEY3_0</name>
+                        <bitRange>[23:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>KEY3_1</name>
+                <addressOffset>0x003d64</addressOffset>
+                <description>Bits 31:16 of OTP access key 3 (ECC)</description>
+                <size>24</size>
+                <resetMask>0x000000</resetMask>
+                <fields>
+                    <field>
+                        <name>KEY3_1</name>
+                        <bitRange>[23:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>KEY3_2</name>
+                <addressOffset>0x003d68</addressOffset>
+                <description>Bits 47:32 of OTP access key 3 (ECC)</description>
+                <size>24</size>
+                <resetMask>0x000000</resetMask>
+                <fields>
+                    <field>
+                        <name>KEY3_2</name>
+                        <bitRange>[23:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>KEY3_3</name>
+                <addressOffset>0x003d6c</addressOffset>
+                <description>Bits 63:48 of OTP access key 3 (ECC)</description>
+                <size>24</size>
+                <resetMask>0x000000</resetMask>
+                <fields>
+                    <field>
+                        <name>KEY3_3</name>
+                        <bitRange>[23:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>KEY3_4</name>
+                <addressOffset>0x003d70</addressOffset>
+                <description>Bits 79:64 of OTP access key 3 (ECC)</description>
+                <size>24</size>
+                <resetMask>0x000000</resetMask>
+                <fields>
+                    <field>
+                        <name>KEY3_4</name>
+                        <bitRange>[23:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>KEY3_5</name>
+                <addressOffset>0x003d74</addressOffset>
+                <description>Bits 95:80 of OTP access key 3 (ECC)</description>
+                <size>24</size>
+                <resetMask>0x000000</resetMask>
+                <fields>
+                    <field>
+                        <name>KEY3_5</name>
+                        <bitRange>[23:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>KEY3_6</name>
+                <addressOffset>0x003d78</addressOffset>
+                <description>Bits 111:96 of OTP access key 3 (ECC)</description>
+                <size>24</size>
+                <resetMask>0x000000</resetMask>
+                <fields>
+                    <field>
+                        <name>KEY3_6</name>
+                        <bitRange>[23:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>KEY3_7</name>
+                <addressOffset>0x003d7c</addressOffset>
+                <description>Bits 127:112 of OTP access key 3 (ECC)</description>
+                <size>24</size>
+                <resetMask>0x000000</resetMask>
+                <fields>
+                    <field>
+                        <name>KEY3_7</name>
+                        <bitRange>[23:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>KEY4_0</name>
+                <addressOffset>0x003d80</addressOffset>
+                <description>Bits 15:0 of OTP access key 4 (ECC)</description>
+                <size>24</size>
+                <resetMask>0x000000</resetMask>
+                <fields>
+                    <field>
+                        <name>KEY4_0</name>
+                        <bitRange>[23:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>KEY4_1</name>
+                <addressOffset>0x003d84</addressOffset>
+                <description>Bits 31:16 of OTP access key 4 (ECC)</description>
+                <size>24</size>
+                <resetMask>0x000000</resetMask>
+                <fields>
+                    <field>
+                        <name>KEY4_1</name>
+                        <bitRange>[23:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>KEY4_2</name>
+                <addressOffset>0x003d88</addressOffset>
+                <description>Bits 47:32 of OTP access key 4 (ECC)</description>
+                <size>24</size>
+                <resetMask>0x000000</resetMask>
+                <fields>
+                    <field>
+                        <name>KEY4_2</name>
+                        <bitRange>[23:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>KEY4_3</name>
+                <addressOffset>0x003d8c</addressOffset>
+                <description>Bits 63:48 of OTP access key 4 (ECC)</description>
+                <size>24</size>
+                <resetMask>0x000000</resetMask>
+                <fields>
+                    <field>
+                        <name>KEY4_3</name>
+                        <bitRange>[23:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>KEY4_4</name>
+                <addressOffset>0x003d90</addressOffset>
+                <description>Bits 79:64 of OTP access key 4 (ECC)</description>
+                <size>24</size>
+                <resetMask>0x000000</resetMask>
+                <fields>
+                    <field>
+                        <name>KEY4_4</name>
+                        <bitRange>[23:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>KEY4_5</name>
+                <addressOffset>0x003d94</addressOffset>
+                <description>Bits 95:80 of OTP access key 4 (ECC)</description>
+                <size>24</size>
+                <resetMask>0x000000</resetMask>
+                <fields>
+                    <field>
+                        <name>KEY4_5</name>
+                        <bitRange>[23:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>KEY4_6</name>
+                <addressOffset>0x003d98</addressOffset>
+                <description>Bits 111:96 of OTP access key 4 (ECC)</description>
+                <size>24</size>
+                <resetMask>0x000000</resetMask>
+                <fields>
+                    <field>
+                        <name>KEY4_6</name>
+                        <bitRange>[23:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>KEY4_7</name>
+                <addressOffset>0x003d9c</addressOffset>
+                <description>Bits 127:112 of OTP access key 4 (ECC)</description>
+                <size>24</size>
+                <resetMask>0x000000</resetMask>
+                <fields>
+                    <field>
+                        <name>KEY4_7</name>
+                        <bitRange>[23:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>KEY5_0</name>
+                <addressOffset>0x003da0</addressOffset>
+                <description>Bits 15:0 of OTP access key 5 (ECC)</description>
+                <size>24</size>
+                <resetMask>0x000000</resetMask>
+                <fields>
+                    <field>
+                        <name>KEY5_0</name>
+                        <bitRange>[23:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>KEY5_1</name>
+                <addressOffset>0x003da4</addressOffset>
+                <description>Bits 31:16 of OTP access key 5 (ECC)</description>
+                <size>24</size>
+                <resetMask>0x000000</resetMask>
+                <fields>
+                    <field>
+                        <name>KEY5_1</name>
+                        <bitRange>[23:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>KEY5_2</name>
+                <addressOffset>0x003da8</addressOffset>
+                <description>Bits 47:32 of OTP access key 5 (ECC)</description>
+                <size>24</size>
+                <resetMask>0x000000</resetMask>
+                <fields>
+                    <field>
+                        <name>KEY5_2</name>
+                        <bitRange>[23:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>KEY5_3</name>
+                <addressOffset>0x003dac</addressOffset>
+                <description>Bits 63:48 of OTP access key 5 (ECC)</description>
+                <size>24</size>
+                <resetMask>0x000000</resetMask>
+                <fields>
+                    <field>
+                        <name>KEY5_3</name>
+                        <bitRange>[23:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>KEY5_4</name>
+                <addressOffset>0x003db0</addressOffset>
+                <description>Bits 79:64 of OTP access key 5 (ECC)</description>
+                <size>24</size>
+                <resetMask>0x000000</resetMask>
+                <fields>
+                    <field>
+                        <name>KEY5_4</name>
+                        <bitRange>[23:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>KEY5_5</name>
+                <addressOffset>0x003db4</addressOffset>
+                <description>Bits 95:80 of OTP access key 5 (ECC)</description>
+                <size>24</size>
+                <resetMask>0x000000</resetMask>
+                <fields>
+                    <field>
+                        <name>KEY5_5</name>
+                        <bitRange>[23:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>KEY5_6</name>
+                <addressOffset>0x003db8</addressOffset>
+                <description>Bits 111:96 of OTP access key 5 (ECC)</description>
+                <size>24</size>
+                <resetMask>0x000000</resetMask>
+                <fields>
+                    <field>
+                        <name>KEY5_6</name>
+                        <bitRange>[23:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>KEY5_7</name>
+                <addressOffset>0x003dbc</addressOffset>
+                <description>Bits 127:112 of OTP access key 5 (ECC)</description>
+                <size>24</size>
+                <resetMask>0x000000</resetMask>
+                <fields>
+                    <field>
+                        <name>KEY5_7</name>
+                        <bitRange>[23:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>KEY6_0</name>
+                <addressOffset>0x003dc0</addressOffset>
+                <description>Bits 15:0 of OTP access key 6 (ECC)</description>
+                <size>24</size>
+                <resetMask>0x000000</resetMask>
+                <fields>
+                    <field>
+                        <name>KEY6_0</name>
+                        <bitRange>[23:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>KEY6_1</name>
+                <addressOffset>0x003dc4</addressOffset>
+                <description>Bits 31:16 of OTP access key 6 (ECC)</description>
+                <size>24</size>
+                <resetMask>0x000000</resetMask>
+                <fields>
+                    <field>
+                        <name>KEY6_1</name>
+                        <bitRange>[23:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>KEY6_2</name>
+                <addressOffset>0x003dc8</addressOffset>
+                <description>Bits 47:32 of OTP access key 6 (ECC)</description>
+                <size>24</size>
+                <resetMask>0x000000</resetMask>
+                <fields>
+                    <field>
+                        <name>KEY6_2</name>
+                        <bitRange>[23:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>KEY6_3</name>
+                <addressOffset>0x003dcc</addressOffset>
+                <description>Bits 63:48 of OTP access key 6 (ECC)</description>
+                <size>24</size>
+                <resetMask>0x000000</resetMask>
+                <fields>
+                    <field>
+                        <name>KEY6_3</name>
+                        <bitRange>[23:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>KEY6_4</name>
+                <addressOffset>0x003dd0</addressOffset>
+                <description>Bits 79:64 of OTP access key 6 (ECC)</description>
+                <size>24</size>
+                <resetMask>0x000000</resetMask>
+                <fields>
+                    <field>
+                        <name>KEY6_4</name>
+                        <bitRange>[23:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>KEY6_5</name>
+                <addressOffset>0x003dd4</addressOffset>
+                <description>Bits 95:80 of OTP access key 6 (ECC)</description>
+                <size>24</size>
+                <resetMask>0x000000</resetMask>
+                <fields>
+                    <field>
+                        <name>KEY6_5</name>
+                        <bitRange>[23:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>KEY6_6</name>
+                <addressOffset>0x003dd8</addressOffset>
+                <description>Bits 111:96 of OTP access key 6 (ECC)</description>
+                <size>24</size>
+                <resetMask>0x000000</resetMask>
+                <fields>
+                    <field>
+                        <name>KEY6_6</name>
+                        <bitRange>[23:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>KEY6_7</name>
+                <addressOffset>0x003ddc</addressOffset>
+                <description>Bits 127:112 of OTP access key 6 (ECC)</description>
+                <size>24</size>
+                <resetMask>0x000000</resetMask>
+                <fields>
+                    <field>
+                        <name>KEY6_7</name>
+                        <bitRange>[23:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>KEY1_VALID</name>
+                <addressOffset>0x003de4</addressOffset>
+                <description>Valid flag for key 1. Once the valid flag is set, the key can no longer be read or written, and becomes a valid fixed key for protecting OTP pages.</description>
+                <size>24</size>
+                <resetValue>0x000000</resetValue>
+                <fields>
+                    <field>
+                        <name>VALID_R2</name>
+                        <description>Redundant copy of VALID, with 3-way majority vote</description>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>VALID_R1</name>
+                        <description>Redundant copy of VALID, with 3-way majority vote</description>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>VALID</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>KEY2_VALID</name>
+                <addressOffset>0x003de8</addressOffset>
+                <description>Valid flag for key 2. Once the valid flag is set, the key can no longer be read or written, and becomes a valid fixed key for protecting OTP pages.</description>
+                <size>24</size>
+                <resetValue>0x000000</resetValue>
+                <fields>
+                    <field>
+                        <name>VALID_R2</name>
+                        <description>Redundant copy of VALID, with 3-way majority vote</description>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>VALID_R1</name>
+                        <description>Redundant copy of VALID, with 3-way majority vote</description>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>VALID</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>KEY3_VALID</name>
+                <addressOffset>0x003dec</addressOffset>
+                <description>Valid flag for key 3. Once the valid flag is set, the key can no longer be read or written, and becomes a valid fixed key for protecting OTP pages.</description>
+                <size>24</size>
+                <resetValue>0x000000</resetValue>
+                <fields>
+                    <field>
+                        <name>VALID_R2</name>
+                        <description>Redundant copy of VALID, with 3-way majority vote</description>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>VALID_R1</name>
+                        <description>Redundant copy of VALID, with 3-way majority vote</description>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>VALID</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>KEY4_VALID</name>
+                <addressOffset>0x003df0</addressOffset>
+                <description>Valid flag for key 4. Once the valid flag is set, the key can no longer be read or written, and becomes a valid fixed key for protecting OTP pages.</description>
+                <size>24</size>
+                <resetValue>0x000000</resetValue>
+                <fields>
+                    <field>
+                        <name>VALID_R2</name>
+                        <description>Redundant copy of VALID, with 3-way majority vote</description>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>VALID_R1</name>
+                        <description>Redundant copy of VALID, with 3-way majority vote</description>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>VALID</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>KEY5_VALID</name>
+                <addressOffset>0x003df4</addressOffset>
+                <description>Valid flag for key 5. Once the valid flag is set, the key can no longer be read or written, and becomes a valid fixed key for protecting OTP pages.</description>
+                <size>24</size>
+                <resetValue>0x000000</resetValue>
+                <fields>
+                    <field>
+                        <name>VALID_R2</name>
+                        <description>Redundant copy of VALID, with 3-way majority vote</description>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>VALID_R1</name>
+                        <description>Redundant copy of VALID, with 3-way majority vote</description>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>VALID</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>KEY6_VALID</name>
+                <addressOffset>0x003df8</addressOffset>
+                <description>Valid flag for key 6. Once the valid flag is set, the key can no longer be read or written, and becomes a valid fixed key for protecting OTP pages.</description>
+                <size>24</size>
+                <resetValue>0x000000</resetValue>
+                <fields>
+                    <field>
+                        <name>VALID_R2</name>
+                        <description>Redundant copy of VALID, with 3-way majority vote</description>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>VALID_R1</name>
+                        <description>Redundant copy of VALID, with 3-way majority vote</description>
+                        <bitRange>[8:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>VALID</name>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PAGE0_LOCK0</name>
+                <addressOffset>0x003e00</addressOffset>
+                <description>Lock configuration LSBs for page 0 (rows 0x0 through 0x3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently.
+
+                    This OTP location is always readable, and is write-protected by its own permissions.</description>
+                <size>24</size>
+                <resetValue>0x000000</resetValue>
+                <fields>
+                    <field>
+                        <name>R2</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[23:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>R1</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[15:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>NO_KEY_STATE</name>
+                        <description>State when at least one key is registered for this page and no matching key has been entered.</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>KEY_R</name>
+                        <description>Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required.</description>
+                        <bitRange>[5:3]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>KEY_W</name>
+                        <description>Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required.</description>
+                        <bitRange>[2:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PAGE0_LOCK1</name>
+                <addressOffset>0x003e04</addressOffset>
+                <description>Lock configuration MSBs for page 0 (rows 0x0 through 0x3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently.
+
+                    This OTP location is always readable, and is write-protected by its own permissions.</description>
+                <size>24</size>
+                <resetValue>0x000000</resetValue>
+                <fields>
+                    <field>
+                        <name>R2</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[23:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>R1</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[15:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>LOCK_BL</name>
+                        <description>Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers.</description>
+                        <bitRange>[5:4]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                                <description>Bootloader permits user reads and writes to this page</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                                <description>Bootloader permits user reads of this page</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>reserved</name>
+                                <value>2</value>
+                                <description>Do not use. Behaves the same as INACCESSIBLE</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                                <description>Bootloader does not permit user access to this page</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>LOCK_NS</name>
+                        <description>Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers.
+
+                            Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API.</description>
+                        <bitRange>[3:2]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                                <description>Page can be read by Non-secure software, and Secure software may permit Non-secure writes.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                                <description>Page can be read by Non-secure software</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>reserved</name>
+                                <value>2</value>
+                                <description>Do not use. Behaves the same as INACCESSIBLE.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                                <description>Page can not be accessed by Non-secure software.</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>LOCK_S</name>
+                        <description>Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers.</description>
+                        <bitRange>[1:0]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                                <description>Page is fully accessible by Secure software.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                                <description>Page can be read by Secure software, but can not be written.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>reserved</name>
+                                <value>2</value>
+                                <description>Do not use. Behaves the same as INACCESSIBLE.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                                <description>Page can not be accessed by Secure software.</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PAGE1_LOCK0</name>
+                <addressOffset>0x003e08</addressOffset>
+                <description>Lock configuration LSBs for page 1 (rows 0x40 through 0x7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently.
+
+                    This OTP location is always readable, and is write-protected by its own permissions.</description>
+                <size>24</size>
+                <resetValue>0x000000</resetValue>
+                <fields>
+                    <field>
+                        <name>R2</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[23:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>R1</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[15:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>NO_KEY_STATE</name>
+                        <description>State when at least one key is registered for this page and no matching key has been entered.</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>KEY_R</name>
+                        <description>Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required.</description>
+                        <bitRange>[5:3]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>KEY_W</name>
+                        <description>Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required.</description>
+                        <bitRange>[2:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PAGE1_LOCK1</name>
+                <addressOffset>0x003e0c</addressOffset>
+                <description>Lock configuration MSBs for page 1 (rows 0x40 through 0x7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently.
+
+                    This OTP location is always readable, and is write-protected by its own permissions.</description>
+                <size>24</size>
+                <resetValue>0x000000</resetValue>
+                <fields>
+                    <field>
+                        <name>R2</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[23:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>R1</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[15:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>LOCK_BL</name>
+                        <description>Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers.</description>
+                        <bitRange>[5:4]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                                <description>Bootloader permits user reads and writes to this page</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                                <description>Bootloader permits user reads of this page</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>reserved</name>
+                                <value>2</value>
+                                <description>Do not use. Behaves the same as INACCESSIBLE</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                                <description>Bootloader does not permit user access to this page</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>LOCK_NS</name>
+                        <description>Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers.
+
+                            Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API.</description>
+                        <bitRange>[3:2]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                                <description>Page can be read by Non-secure software, and Secure software may permit Non-secure writes.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                                <description>Page can be read by Non-secure software</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>reserved</name>
+                                <value>2</value>
+                                <description>Do not use. Behaves the same as INACCESSIBLE.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                                <description>Page can not be accessed by Non-secure software.</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>LOCK_S</name>
+                        <description>Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers.</description>
+                        <bitRange>[1:0]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                                <description>Page is fully accessible by Secure software.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                                <description>Page can be read by Secure software, but can not be written.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>reserved</name>
+                                <value>2</value>
+                                <description>Do not use. Behaves the same as INACCESSIBLE.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                                <description>Page can not be accessed by Secure software.</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PAGE2_LOCK0</name>
+                <addressOffset>0x003e10</addressOffset>
+                <description>Lock configuration LSBs for page 2 (rows 0x80 through 0xbf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently.
+
+                    This OTP location is always readable, and is write-protected by its own permissions.</description>
+                <size>24</size>
+                <resetValue>0x000000</resetValue>
+                <fields>
+                    <field>
+                        <name>R2</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[23:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>R1</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[15:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>NO_KEY_STATE</name>
+                        <description>State when at least one key is registered for this page and no matching key has been entered.</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>KEY_R</name>
+                        <description>Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required.</description>
+                        <bitRange>[5:3]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>KEY_W</name>
+                        <description>Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required.</description>
+                        <bitRange>[2:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PAGE2_LOCK1</name>
+                <addressOffset>0x003e14</addressOffset>
+                <description>Lock configuration MSBs for page 2 (rows 0x80 through 0xbf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently.
+
+                    This OTP location is always readable, and is write-protected by its own permissions.</description>
+                <size>24</size>
+                <resetValue>0x000000</resetValue>
+                <fields>
+                    <field>
+                        <name>R2</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[23:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>R1</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[15:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>LOCK_BL</name>
+                        <description>Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers.</description>
+                        <bitRange>[5:4]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                                <description>Bootloader permits user reads and writes to this page</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                                <description>Bootloader permits user reads of this page</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>reserved</name>
+                                <value>2</value>
+                                <description>Do not use. Behaves the same as INACCESSIBLE</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                                <description>Bootloader does not permit user access to this page</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>LOCK_NS</name>
+                        <description>Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers.
+
+                            Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API.</description>
+                        <bitRange>[3:2]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                                <description>Page can be read by Non-secure software, and Secure software may permit Non-secure writes.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                                <description>Page can be read by Non-secure software</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>reserved</name>
+                                <value>2</value>
+                                <description>Do not use. Behaves the same as INACCESSIBLE.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                                <description>Page can not be accessed by Non-secure software.</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>LOCK_S</name>
+                        <description>Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers.</description>
+                        <bitRange>[1:0]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                                <description>Page is fully accessible by Secure software.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                                <description>Page can be read by Secure software, but can not be written.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>reserved</name>
+                                <value>2</value>
+                                <description>Do not use. Behaves the same as INACCESSIBLE.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                                <description>Page can not be accessed by Secure software.</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PAGE3_LOCK0</name>
+                <addressOffset>0x003e18</addressOffset>
+                <description>Lock configuration LSBs for page 3 (rows 0xc0 through 0xff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently.
+
+                    This OTP location is always readable, and is write-protected by its own permissions.</description>
+                <size>24</size>
+                <resetValue>0x000000</resetValue>
+                <fields>
+                    <field>
+                        <name>R2</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[23:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>R1</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[15:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>NO_KEY_STATE</name>
+                        <description>State when at least one key is registered for this page and no matching key has been entered.</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>KEY_R</name>
+                        <description>Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required.</description>
+                        <bitRange>[5:3]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>KEY_W</name>
+                        <description>Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required.</description>
+                        <bitRange>[2:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PAGE3_LOCK1</name>
+                <addressOffset>0x003e1c</addressOffset>
+                <description>Lock configuration MSBs for page 3 (rows 0xc0 through 0xff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently.
+
+                    This OTP location is always readable, and is write-protected by its own permissions.</description>
+                <size>24</size>
+                <resetValue>0x000000</resetValue>
+                <fields>
+                    <field>
+                        <name>R2</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[23:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>R1</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[15:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>LOCK_BL</name>
+                        <description>Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers.</description>
+                        <bitRange>[5:4]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                                <description>Bootloader permits user reads and writes to this page</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                                <description>Bootloader permits user reads of this page</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>reserved</name>
+                                <value>2</value>
+                                <description>Do not use. Behaves the same as INACCESSIBLE</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                                <description>Bootloader does not permit user access to this page</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>LOCK_NS</name>
+                        <description>Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers.
+
+                            Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API.</description>
+                        <bitRange>[3:2]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                                <description>Page can be read by Non-secure software, and Secure software may permit Non-secure writes.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                                <description>Page can be read by Non-secure software</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>reserved</name>
+                                <value>2</value>
+                                <description>Do not use. Behaves the same as INACCESSIBLE.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                                <description>Page can not be accessed by Non-secure software.</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>LOCK_S</name>
+                        <description>Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers.</description>
+                        <bitRange>[1:0]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                                <description>Page is fully accessible by Secure software.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                                <description>Page can be read by Secure software, but can not be written.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>reserved</name>
+                                <value>2</value>
+                                <description>Do not use. Behaves the same as INACCESSIBLE.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                                <description>Page can not be accessed by Secure software.</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PAGE4_LOCK0</name>
+                <addressOffset>0x003e20</addressOffset>
+                <description>Lock configuration LSBs for page 4 (rows 0x100 through 0x13f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently.
+
+                    This OTP location is always readable, and is write-protected by its own permissions.</description>
+                <size>24</size>
+                <resetValue>0x000000</resetValue>
+                <fields>
+                    <field>
+                        <name>R2</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[23:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>R1</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[15:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>NO_KEY_STATE</name>
+                        <description>State when at least one key is registered for this page and no matching key has been entered.</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>KEY_R</name>
+                        <description>Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required.</description>
+                        <bitRange>[5:3]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>KEY_W</name>
+                        <description>Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required.</description>
+                        <bitRange>[2:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PAGE4_LOCK1</name>
+                <addressOffset>0x003e24</addressOffset>
+                <description>Lock configuration MSBs for page 4 (rows 0x100 through 0x13f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently.
+
+                    This OTP location is always readable, and is write-protected by its own permissions.</description>
+                <size>24</size>
+                <resetValue>0x000000</resetValue>
+                <fields>
+                    <field>
+                        <name>R2</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[23:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>R1</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[15:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>LOCK_BL</name>
+                        <description>Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers.</description>
+                        <bitRange>[5:4]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                                <description>Bootloader permits user reads and writes to this page</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                                <description>Bootloader permits user reads of this page</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>reserved</name>
+                                <value>2</value>
+                                <description>Do not use. Behaves the same as INACCESSIBLE</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                                <description>Bootloader does not permit user access to this page</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>LOCK_NS</name>
+                        <description>Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers.
+
+                            Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API.</description>
+                        <bitRange>[3:2]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                                <description>Page can be read by Non-secure software, and Secure software may permit Non-secure writes.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                                <description>Page can be read by Non-secure software</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>reserved</name>
+                                <value>2</value>
+                                <description>Do not use. Behaves the same as INACCESSIBLE.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                                <description>Page can not be accessed by Non-secure software.</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>LOCK_S</name>
+                        <description>Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers.</description>
+                        <bitRange>[1:0]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                                <description>Page is fully accessible by Secure software.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                                <description>Page can be read by Secure software, but can not be written.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>reserved</name>
+                                <value>2</value>
+                                <description>Do not use. Behaves the same as INACCESSIBLE.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                                <description>Page can not be accessed by Secure software.</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PAGE5_LOCK0</name>
+                <addressOffset>0x003e28</addressOffset>
+                <description>Lock configuration LSBs for page 5 (rows 0x140 through 0x17f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently.
+
+                    This OTP location is always readable, and is write-protected by its own permissions.</description>
+                <size>24</size>
+                <resetValue>0x000000</resetValue>
+                <fields>
+                    <field>
+                        <name>R2</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[23:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>R1</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[15:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>NO_KEY_STATE</name>
+                        <description>State when at least one key is registered for this page and no matching key has been entered.</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>KEY_R</name>
+                        <description>Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required.</description>
+                        <bitRange>[5:3]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>KEY_W</name>
+                        <description>Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required.</description>
+                        <bitRange>[2:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PAGE5_LOCK1</name>
+                <addressOffset>0x003e2c</addressOffset>
+                <description>Lock configuration MSBs for page 5 (rows 0x140 through 0x17f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently.
+
+                    This OTP location is always readable, and is write-protected by its own permissions.</description>
+                <size>24</size>
+                <resetValue>0x000000</resetValue>
+                <fields>
+                    <field>
+                        <name>R2</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[23:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>R1</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[15:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>LOCK_BL</name>
+                        <description>Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers.</description>
+                        <bitRange>[5:4]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                                <description>Bootloader permits user reads and writes to this page</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                                <description>Bootloader permits user reads of this page</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>reserved</name>
+                                <value>2</value>
+                                <description>Do not use. Behaves the same as INACCESSIBLE</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                                <description>Bootloader does not permit user access to this page</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>LOCK_NS</name>
+                        <description>Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers.
+
+                            Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API.</description>
+                        <bitRange>[3:2]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                                <description>Page can be read by Non-secure software, and Secure software may permit Non-secure writes.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                                <description>Page can be read by Non-secure software</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>reserved</name>
+                                <value>2</value>
+                                <description>Do not use. Behaves the same as INACCESSIBLE.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                                <description>Page can not be accessed by Non-secure software.</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>LOCK_S</name>
+                        <description>Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers.</description>
+                        <bitRange>[1:0]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                                <description>Page is fully accessible by Secure software.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                                <description>Page can be read by Secure software, but can not be written.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>reserved</name>
+                                <value>2</value>
+                                <description>Do not use. Behaves the same as INACCESSIBLE.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                                <description>Page can not be accessed by Secure software.</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PAGE6_LOCK0</name>
+                <addressOffset>0x003e30</addressOffset>
+                <description>Lock configuration LSBs for page 6 (rows 0x180 through 0x1bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently.
+
+                    This OTP location is always readable, and is write-protected by its own permissions.</description>
+                <size>24</size>
+                <resetValue>0x000000</resetValue>
+                <fields>
+                    <field>
+                        <name>R2</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[23:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>R1</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[15:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>NO_KEY_STATE</name>
+                        <description>State when at least one key is registered for this page and no matching key has been entered.</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>KEY_R</name>
+                        <description>Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required.</description>
+                        <bitRange>[5:3]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>KEY_W</name>
+                        <description>Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required.</description>
+                        <bitRange>[2:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PAGE6_LOCK1</name>
+                <addressOffset>0x003e34</addressOffset>
+                <description>Lock configuration MSBs for page 6 (rows 0x180 through 0x1bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently.
+
+                    This OTP location is always readable, and is write-protected by its own permissions.</description>
+                <size>24</size>
+                <resetValue>0x000000</resetValue>
+                <fields>
+                    <field>
+                        <name>R2</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[23:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>R1</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[15:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>LOCK_BL</name>
+                        <description>Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers.</description>
+                        <bitRange>[5:4]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                                <description>Bootloader permits user reads and writes to this page</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                                <description>Bootloader permits user reads of this page</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>reserved</name>
+                                <value>2</value>
+                                <description>Do not use. Behaves the same as INACCESSIBLE</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                                <description>Bootloader does not permit user access to this page</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>LOCK_NS</name>
+                        <description>Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers.
+
+                            Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API.</description>
+                        <bitRange>[3:2]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                                <description>Page can be read by Non-secure software, and Secure software may permit Non-secure writes.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                                <description>Page can be read by Non-secure software</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>reserved</name>
+                                <value>2</value>
+                                <description>Do not use. Behaves the same as INACCESSIBLE.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                                <description>Page can not be accessed by Non-secure software.</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>LOCK_S</name>
+                        <description>Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers.</description>
+                        <bitRange>[1:0]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                                <description>Page is fully accessible by Secure software.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                                <description>Page can be read by Secure software, but can not be written.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>reserved</name>
+                                <value>2</value>
+                                <description>Do not use. Behaves the same as INACCESSIBLE.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                                <description>Page can not be accessed by Secure software.</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PAGE7_LOCK0</name>
+                <addressOffset>0x003e38</addressOffset>
+                <description>Lock configuration LSBs for page 7 (rows 0x1c0 through 0x1ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently.
+
+                    This OTP location is always readable, and is write-protected by its own permissions.</description>
+                <size>24</size>
+                <resetValue>0x000000</resetValue>
+                <fields>
+                    <field>
+                        <name>R2</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[23:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>R1</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[15:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>NO_KEY_STATE</name>
+                        <description>State when at least one key is registered for this page and no matching key has been entered.</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>KEY_R</name>
+                        <description>Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required.</description>
+                        <bitRange>[5:3]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>KEY_W</name>
+                        <description>Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required.</description>
+                        <bitRange>[2:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PAGE7_LOCK1</name>
+                <addressOffset>0x003e3c</addressOffset>
+                <description>Lock configuration MSBs for page 7 (rows 0x1c0 through 0x1ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently.
+
+                    This OTP location is always readable, and is write-protected by its own permissions.</description>
+                <size>24</size>
+                <resetValue>0x000000</resetValue>
+                <fields>
+                    <field>
+                        <name>R2</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[23:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>R1</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[15:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>LOCK_BL</name>
+                        <description>Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers.</description>
+                        <bitRange>[5:4]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                                <description>Bootloader permits user reads and writes to this page</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                                <description>Bootloader permits user reads of this page</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>reserved</name>
+                                <value>2</value>
+                                <description>Do not use. Behaves the same as INACCESSIBLE</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                                <description>Bootloader does not permit user access to this page</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>LOCK_NS</name>
+                        <description>Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers.
+
+                            Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API.</description>
+                        <bitRange>[3:2]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                                <description>Page can be read by Non-secure software, and Secure software may permit Non-secure writes.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                                <description>Page can be read by Non-secure software</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>reserved</name>
+                                <value>2</value>
+                                <description>Do not use. Behaves the same as INACCESSIBLE.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                                <description>Page can not be accessed by Non-secure software.</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>LOCK_S</name>
+                        <description>Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers.</description>
+                        <bitRange>[1:0]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                                <description>Page is fully accessible by Secure software.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                                <description>Page can be read by Secure software, but can not be written.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>reserved</name>
+                                <value>2</value>
+                                <description>Do not use. Behaves the same as INACCESSIBLE.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                                <description>Page can not be accessed by Secure software.</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PAGE8_LOCK0</name>
+                <addressOffset>0x003e40</addressOffset>
+                <description>Lock configuration LSBs for page 8 (rows 0x200 through 0x23f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently.
+
+                    This OTP location is always readable, and is write-protected by its own permissions.</description>
+                <size>24</size>
+                <resetValue>0x000000</resetValue>
+                <fields>
+                    <field>
+                        <name>R2</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[23:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>R1</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[15:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>NO_KEY_STATE</name>
+                        <description>State when at least one key is registered for this page and no matching key has been entered.</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>KEY_R</name>
+                        <description>Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required.</description>
+                        <bitRange>[5:3]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>KEY_W</name>
+                        <description>Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required.</description>
+                        <bitRange>[2:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PAGE8_LOCK1</name>
+                <addressOffset>0x003e44</addressOffset>
+                <description>Lock configuration MSBs for page 8 (rows 0x200 through 0x23f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently.
+
+                    This OTP location is always readable, and is write-protected by its own permissions.</description>
+                <size>24</size>
+                <resetValue>0x000000</resetValue>
+                <fields>
+                    <field>
+                        <name>R2</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[23:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>R1</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[15:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>LOCK_BL</name>
+                        <description>Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers.</description>
+                        <bitRange>[5:4]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                                <description>Bootloader permits user reads and writes to this page</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                                <description>Bootloader permits user reads of this page</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>reserved</name>
+                                <value>2</value>
+                                <description>Do not use. Behaves the same as INACCESSIBLE</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                                <description>Bootloader does not permit user access to this page</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>LOCK_NS</name>
+                        <description>Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers.
+
+                            Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API.</description>
+                        <bitRange>[3:2]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                                <description>Page can be read by Non-secure software, and Secure software may permit Non-secure writes.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                                <description>Page can be read by Non-secure software</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>reserved</name>
+                                <value>2</value>
+                                <description>Do not use. Behaves the same as INACCESSIBLE.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                                <description>Page can not be accessed by Non-secure software.</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>LOCK_S</name>
+                        <description>Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers.</description>
+                        <bitRange>[1:0]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                                <description>Page is fully accessible by Secure software.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                                <description>Page can be read by Secure software, but can not be written.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>reserved</name>
+                                <value>2</value>
+                                <description>Do not use. Behaves the same as INACCESSIBLE.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                                <description>Page can not be accessed by Secure software.</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PAGE9_LOCK0</name>
+                <addressOffset>0x003e48</addressOffset>
+                <description>Lock configuration LSBs for page 9 (rows 0x240 through 0x27f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently.
+
+                    This OTP location is always readable, and is write-protected by its own permissions.</description>
+                <size>24</size>
+                <resetValue>0x000000</resetValue>
+                <fields>
+                    <field>
+                        <name>R2</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[23:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>R1</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[15:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>NO_KEY_STATE</name>
+                        <description>State when at least one key is registered for this page and no matching key has been entered.</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>KEY_R</name>
+                        <description>Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required.</description>
+                        <bitRange>[5:3]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>KEY_W</name>
+                        <description>Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required.</description>
+                        <bitRange>[2:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PAGE9_LOCK1</name>
+                <addressOffset>0x003e4c</addressOffset>
+                <description>Lock configuration MSBs for page 9 (rows 0x240 through 0x27f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently.
+
+                    This OTP location is always readable, and is write-protected by its own permissions.</description>
+                <size>24</size>
+                <resetValue>0x000000</resetValue>
+                <fields>
+                    <field>
+                        <name>R2</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[23:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>R1</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[15:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>LOCK_BL</name>
+                        <description>Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers.</description>
+                        <bitRange>[5:4]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                                <description>Bootloader permits user reads and writes to this page</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                                <description>Bootloader permits user reads of this page</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>reserved</name>
+                                <value>2</value>
+                                <description>Do not use. Behaves the same as INACCESSIBLE</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                                <description>Bootloader does not permit user access to this page</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>LOCK_NS</name>
+                        <description>Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers.
+
+                            Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API.</description>
+                        <bitRange>[3:2]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                                <description>Page can be read by Non-secure software, and Secure software may permit Non-secure writes.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                                <description>Page can be read by Non-secure software</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>reserved</name>
+                                <value>2</value>
+                                <description>Do not use. Behaves the same as INACCESSIBLE.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                                <description>Page can not be accessed by Non-secure software.</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>LOCK_S</name>
+                        <description>Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers.</description>
+                        <bitRange>[1:0]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                                <description>Page is fully accessible by Secure software.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                                <description>Page can be read by Secure software, but can not be written.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>reserved</name>
+                                <value>2</value>
+                                <description>Do not use. Behaves the same as INACCESSIBLE.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                                <description>Page can not be accessed by Secure software.</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PAGE10_LOCK0</name>
+                <addressOffset>0x003e50</addressOffset>
+                <description>Lock configuration LSBs for page 10 (rows 0x280 through 0x2bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently.
+
+                    This OTP location is always readable, and is write-protected by its own permissions.</description>
+                <size>24</size>
+                <resetValue>0x000000</resetValue>
+                <fields>
+                    <field>
+                        <name>R2</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[23:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>R1</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[15:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>NO_KEY_STATE</name>
+                        <description>State when at least one key is registered for this page and no matching key has been entered.</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>KEY_R</name>
+                        <description>Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required.</description>
+                        <bitRange>[5:3]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>KEY_W</name>
+                        <description>Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required.</description>
+                        <bitRange>[2:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PAGE10_LOCK1</name>
+                <addressOffset>0x003e54</addressOffset>
+                <description>Lock configuration MSBs for page 10 (rows 0x280 through 0x2bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently.
+
+                    This OTP location is always readable, and is write-protected by its own permissions.</description>
+                <size>24</size>
+                <resetValue>0x000000</resetValue>
+                <fields>
+                    <field>
+                        <name>R2</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[23:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>R1</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[15:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>LOCK_BL</name>
+                        <description>Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers.</description>
+                        <bitRange>[5:4]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                                <description>Bootloader permits user reads and writes to this page</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                                <description>Bootloader permits user reads of this page</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>reserved</name>
+                                <value>2</value>
+                                <description>Do not use. Behaves the same as INACCESSIBLE</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                                <description>Bootloader does not permit user access to this page</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>LOCK_NS</name>
+                        <description>Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers.
+
+                            Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API.</description>
+                        <bitRange>[3:2]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                                <description>Page can be read by Non-secure software, and Secure software may permit Non-secure writes.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                                <description>Page can be read by Non-secure software</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>reserved</name>
+                                <value>2</value>
+                                <description>Do not use. Behaves the same as INACCESSIBLE.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                                <description>Page can not be accessed by Non-secure software.</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>LOCK_S</name>
+                        <description>Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers.</description>
+                        <bitRange>[1:0]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                                <description>Page is fully accessible by Secure software.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                                <description>Page can be read by Secure software, but can not be written.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>reserved</name>
+                                <value>2</value>
+                                <description>Do not use. Behaves the same as INACCESSIBLE.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                                <description>Page can not be accessed by Secure software.</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PAGE11_LOCK0</name>
+                <addressOffset>0x003e58</addressOffset>
+                <description>Lock configuration LSBs for page 11 (rows 0x2c0 through 0x2ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently.
+
+                    This OTP location is always readable, and is write-protected by its own permissions.</description>
+                <size>24</size>
+                <resetValue>0x000000</resetValue>
+                <fields>
+                    <field>
+                        <name>R2</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[23:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>R1</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[15:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>NO_KEY_STATE</name>
+                        <description>State when at least one key is registered for this page and no matching key has been entered.</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>KEY_R</name>
+                        <description>Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required.</description>
+                        <bitRange>[5:3]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>KEY_W</name>
+                        <description>Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required.</description>
+                        <bitRange>[2:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PAGE11_LOCK1</name>
+                <addressOffset>0x003e5c</addressOffset>
+                <description>Lock configuration MSBs for page 11 (rows 0x2c0 through 0x2ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently.
+
+                    This OTP location is always readable, and is write-protected by its own permissions.</description>
+                <size>24</size>
+                <resetValue>0x000000</resetValue>
+                <fields>
+                    <field>
+                        <name>R2</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[23:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>R1</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[15:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>LOCK_BL</name>
+                        <description>Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers.</description>
+                        <bitRange>[5:4]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                                <description>Bootloader permits user reads and writes to this page</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                                <description>Bootloader permits user reads of this page</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>reserved</name>
+                                <value>2</value>
+                                <description>Do not use. Behaves the same as INACCESSIBLE</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                                <description>Bootloader does not permit user access to this page</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>LOCK_NS</name>
+                        <description>Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers.
+
+                            Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API.</description>
+                        <bitRange>[3:2]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                                <description>Page can be read by Non-secure software, and Secure software may permit Non-secure writes.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                                <description>Page can be read by Non-secure software</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>reserved</name>
+                                <value>2</value>
+                                <description>Do not use. Behaves the same as INACCESSIBLE.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                                <description>Page can not be accessed by Non-secure software.</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>LOCK_S</name>
+                        <description>Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers.</description>
+                        <bitRange>[1:0]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                                <description>Page is fully accessible by Secure software.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                                <description>Page can be read by Secure software, but can not be written.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>reserved</name>
+                                <value>2</value>
+                                <description>Do not use. Behaves the same as INACCESSIBLE.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                                <description>Page can not be accessed by Secure software.</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PAGE12_LOCK0</name>
+                <addressOffset>0x003e60</addressOffset>
+                <description>Lock configuration LSBs for page 12 (rows 0x300 through 0x33f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently.
+
+                    This OTP location is always readable, and is write-protected by its own permissions.</description>
+                <size>24</size>
+                <resetValue>0x000000</resetValue>
+                <fields>
+                    <field>
+                        <name>R2</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[23:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>R1</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[15:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>NO_KEY_STATE</name>
+                        <description>State when at least one key is registered for this page and no matching key has been entered.</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>KEY_R</name>
+                        <description>Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required.</description>
+                        <bitRange>[5:3]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>KEY_W</name>
+                        <description>Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required.</description>
+                        <bitRange>[2:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PAGE12_LOCK1</name>
+                <addressOffset>0x003e64</addressOffset>
+                <description>Lock configuration MSBs for page 12 (rows 0x300 through 0x33f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently.
+
+                    This OTP location is always readable, and is write-protected by its own permissions.</description>
+                <size>24</size>
+                <resetValue>0x000000</resetValue>
+                <fields>
+                    <field>
+                        <name>R2</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[23:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>R1</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[15:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>LOCK_BL</name>
+                        <description>Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers.</description>
+                        <bitRange>[5:4]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                                <description>Bootloader permits user reads and writes to this page</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                                <description>Bootloader permits user reads of this page</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>reserved</name>
+                                <value>2</value>
+                                <description>Do not use. Behaves the same as INACCESSIBLE</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                                <description>Bootloader does not permit user access to this page</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>LOCK_NS</name>
+                        <description>Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers.
+
+                            Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API.</description>
+                        <bitRange>[3:2]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                                <description>Page can be read by Non-secure software, and Secure software may permit Non-secure writes.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                                <description>Page can be read by Non-secure software</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>reserved</name>
+                                <value>2</value>
+                                <description>Do not use. Behaves the same as INACCESSIBLE.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                                <description>Page can not be accessed by Non-secure software.</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>LOCK_S</name>
+                        <description>Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers.</description>
+                        <bitRange>[1:0]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                                <description>Page is fully accessible by Secure software.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                                <description>Page can be read by Secure software, but can not be written.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>reserved</name>
+                                <value>2</value>
+                                <description>Do not use. Behaves the same as INACCESSIBLE.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                                <description>Page can not be accessed by Secure software.</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PAGE13_LOCK0</name>
+                <addressOffset>0x003e68</addressOffset>
+                <description>Lock configuration LSBs for page 13 (rows 0x340 through 0x37f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently.
+
+                    This OTP location is always readable, and is write-protected by its own permissions.</description>
+                <size>24</size>
+                <resetValue>0x000000</resetValue>
+                <fields>
+                    <field>
+                        <name>R2</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[23:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>R1</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[15:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>NO_KEY_STATE</name>
+                        <description>State when at least one key is registered for this page and no matching key has been entered.</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>KEY_R</name>
+                        <description>Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required.</description>
+                        <bitRange>[5:3]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>KEY_W</name>
+                        <description>Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required.</description>
+                        <bitRange>[2:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PAGE13_LOCK1</name>
+                <addressOffset>0x003e6c</addressOffset>
+                <description>Lock configuration MSBs for page 13 (rows 0x340 through 0x37f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently.
+
+                    This OTP location is always readable, and is write-protected by its own permissions.</description>
+                <size>24</size>
+                <resetValue>0x000000</resetValue>
+                <fields>
+                    <field>
+                        <name>R2</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[23:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>R1</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[15:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>LOCK_BL</name>
+                        <description>Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers.</description>
+                        <bitRange>[5:4]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                                <description>Bootloader permits user reads and writes to this page</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                                <description>Bootloader permits user reads of this page</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>reserved</name>
+                                <value>2</value>
+                                <description>Do not use. Behaves the same as INACCESSIBLE</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                                <description>Bootloader does not permit user access to this page</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>LOCK_NS</name>
+                        <description>Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers.
+
+                            Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API.</description>
+                        <bitRange>[3:2]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                                <description>Page can be read by Non-secure software, and Secure software may permit Non-secure writes.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                                <description>Page can be read by Non-secure software</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>reserved</name>
+                                <value>2</value>
+                                <description>Do not use. Behaves the same as INACCESSIBLE.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                                <description>Page can not be accessed by Non-secure software.</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>LOCK_S</name>
+                        <description>Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers.</description>
+                        <bitRange>[1:0]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                                <description>Page is fully accessible by Secure software.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                                <description>Page can be read by Secure software, but can not be written.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>reserved</name>
+                                <value>2</value>
+                                <description>Do not use. Behaves the same as INACCESSIBLE.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                                <description>Page can not be accessed by Secure software.</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PAGE14_LOCK0</name>
+                <addressOffset>0x003e70</addressOffset>
+                <description>Lock configuration LSBs for page 14 (rows 0x380 through 0x3bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently.
+
+                    This OTP location is always readable, and is write-protected by its own permissions.</description>
+                <size>24</size>
+                <resetValue>0x000000</resetValue>
+                <fields>
+                    <field>
+                        <name>R2</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[23:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>R1</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[15:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>NO_KEY_STATE</name>
+                        <description>State when at least one key is registered for this page and no matching key has been entered.</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>KEY_R</name>
+                        <description>Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required.</description>
+                        <bitRange>[5:3]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>KEY_W</name>
+                        <description>Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required.</description>
+                        <bitRange>[2:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PAGE14_LOCK1</name>
+                <addressOffset>0x003e74</addressOffset>
+                <description>Lock configuration MSBs for page 14 (rows 0x380 through 0x3bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently.
+
+                    This OTP location is always readable, and is write-protected by its own permissions.</description>
+                <size>24</size>
+                <resetValue>0x000000</resetValue>
+                <fields>
+                    <field>
+                        <name>R2</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[23:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>R1</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[15:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>LOCK_BL</name>
+                        <description>Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers.</description>
+                        <bitRange>[5:4]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                                <description>Bootloader permits user reads and writes to this page</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                                <description>Bootloader permits user reads of this page</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>reserved</name>
+                                <value>2</value>
+                                <description>Do not use. Behaves the same as INACCESSIBLE</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                                <description>Bootloader does not permit user access to this page</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>LOCK_NS</name>
+                        <description>Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers.
+
+                            Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API.</description>
+                        <bitRange>[3:2]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                                <description>Page can be read by Non-secure software, and Secure software may permit Non-secure writes.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                                <description>Page can be read by Non-secure software</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>reserved</name>
+                                <value>2</value>
+                                <description>Do not use. Behaves the same as INACCESSIBLE.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                                <description>Page can not be accessed by Non-secure software.</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>LOCK_S</name>
+                        <description>Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers.</description>
+                        <bitRange>[1:0]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                                <description>Page is fully accessible by Secure software.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                                <description>Page can be read by Secure software, but can not be written.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>reserved</name>
+                                <value>2</value>
+                                <description>Do not use. Behaves the same as INACCESSIBLE.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                                <description>Page can not be accessed by Secure software.</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PAGE15_LOCK0</name>
+                <addressOffset>0x003e78</addressOffset>
+                <description>Lock configuration LSBs for page 15 (rows 0x3c0 through 0x3ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently.
+
+                    This OTP location is always readable, and is write-protected by its own permissions.</description>
+                <size>24</size>
+                <resetValue>0x000000</resetValue>
+                <fields>
+                    <field>
+                        <name>R2</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[23:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>R1</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[15:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>NO_KEY_STATE</name>
+                        <description>State when at least one key is registered for this page and no matching key has been entered.</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>KEY_R</name>
+                        <description>Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required.</description>
+                        <bitRange>[5:3]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>KEY_W</name>
+                        <description>Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required.</description>
+                        <bitRange>[2:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PAGE15_LOCK1</name>
+                <addressOffset>0x003e7c</addressOffset>
+                <description>Lock configuration MSBs for page 15 (rows 0x3c0 through 0x3ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently.
+
+                    This OTP location is always readable, and is write-protected by its own permissions.</description>
+                <size>24</size>
+                <resetValue>0x000000</resetValue>
+                <fields>
+                    <field>
+                        <name>R2</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[23:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>R1</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[15:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>LOCK_BL</name>
+                        <description>Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers.</description>
+                        <bitRange>[5:4]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                                <description>Bootloader permits user reads and writes to this page</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                                <description>Bootloader permits user reads of this page</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>reserved</name>
+                                <value>2</value>
+                                <description>Do not use. Behaves the same as INACCESSIBLE</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                                <description>Bootloader does not permit user access to this page</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>LOCK_NS</name>
+                        <description>Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers.
+
+                            Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API.</description>
+                        <bitRange>[3:2]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                                <description>Page can be read by Non-secure software, and Secure software may permit Non-secure writes.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                                <description>Page can be read by Non-secure software</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>reserved</name>
+                                <value>2</value>
+                                <description>Do not use. Behaves the same as INACCESSIBLE.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                                <description>Page can not be accessed by Non-secure software.</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>LOCK_S</name>
+                        <description>Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers.</description>
+                        <bitRange>[1:0]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                                <description>Page is fully accessible by Secure software.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                                <description>Page can be read by Secure software, but can not be written.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>reserved</name>
+                                <value>2</value>
+                                <description>Do not use. Behaves the same as INACCESSIBLE.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                                <description>Page can not be accessed by Secure software.</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PAGE16_LOCK0</name>
+                <addressOffset>0x003e80</addressOffset>
+                <description>Lock configuration LSBs for page 16 (rows 0x400 through 0x43f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently.
+
+                    This OTP location is always readable, and is write-protected by its own permissions.</description>
+                <size>24</size>
+                <resetValue>0x000000</resetValue>
+                <fields>
+                    <field>
+                        <name>R2</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[23:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>R1</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[15:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>NO_KEY_STATE</name>
+                        <description>State when at least one key is registered for this page and no matching key has been entered.</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>KEY_R</name>
+                        <description>Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required.</description>
+                        <bitRange>[5:3]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>KEY_W</name>
+                        <description>Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required.</description>
+                        <bitRange>[2:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PAGE16_LOCK1</name>
+                <addressOffset>0x003e84</addressOffset>
+                <description>Lock configuration MSBs for page 16 (rows 0x400 through 0x43f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently.
+
+                    This OTP location is always readable, and is write-protected by its own permissions.</description>
+                <size>24</size>
+                <resetValue>0x000000</resetValue>
+                <fields>
+                    <field>
+                        <name>R2</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[23:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>R1</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[15:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>LOCK_BL</name>
+                        <description>Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers.</description>
+                        <bitRange>[5:4]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                                <description>Bootloader permits user reads and writes to this page</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                                <description>Bootloader permits user reads of this page</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>reserved</name>
+                                <value>2</value>
+                                <description>Do not use. Behaves the same as INACCESSIBLE</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                                <description>Bootloader does not permit user access to this page</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>LOCK_NS</name>
+                        <description>Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers.
+
+                            Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API.</description>
+                        <bitRange>[3:2]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                                <description>Page can be read by Non-secure software, and Secure software may permit Non-secure writes.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                                <description>Page can be read by Non-secure software</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>reserved</name>
+                                <value>2</value>
+                                <description>Do not use. Behaves the same as INACCESSIBLE.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                                <description>Page can not be accessed by Non-secure software.</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>LOCK_S</name>
+                        <description>Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers.</description>
+                        <bitRange>[1:0]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                                <description>Page is fully accessible by Secure software.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                                <description>Page can be read by Secure software, but can not be written.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>reserved</name>
+                                <value>2</value>
+                                <description>Do not use. Behaves the same as INACCESSIBLE.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                                <description>Page can not be accessed by Secure software.</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PAGE17_LOCK0</name>
+                <addressOffset>0x003e88</addressOffset>
+                <description>Lock configuration LSBs for page 17 (rows 0x440 through 0x47f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently.
+
+                    This OTP location is always readable, and is write-protected by its own permissions.</description>
+                <size>24</size>
+                <resetValue>0x000000</resetValue>
+                <fields>
+                    <field>
+                        <name>R2</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[23:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>R1</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[15:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>NO_KEY_STATE</name>
+                        <description>State when at least one key is registered for this page and no matching key has been entered.</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>KEY_R</name>
+                        <description>Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required.</description>
+                        <bitRange>[5:3]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>KEY_W</name>
+                        <description>Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required.</description>
+                        <bitRange>[2:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PAGE17_LOCK1</name>
+                <addressOffset>0x003e8c</addressOffset>
+                <description>Lock configuration MSBs for page 17 (rows 0x440 through 0x47f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently.
+
+                    This OTP location is always readable, and is write-protected by its own permissions.</description>
+                <size>24</size>
+                <resetValue>0x000000</resetValue>
+                <fields>
+                    <field>
+                        <name>R2</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[23:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>R1</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[15:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>LOCK_BL</name>
+                        <description>Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers.</description>
+                        <bitRange>[5:4]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                                <description>Bootloader permits user reads and writes to this page</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                                <description>Bootloader permits user reads of this page</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>reserved</name>
+                                <value>2</value>
+                                <description>Do not use. Behaves the same as INACCESSIBLE</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                                <description>Bootloader does not permit user access to this page</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>LOCK_NS</name>
+                        <description>Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers.
+
+                            Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API.</description>
+                        <bitRange>[3:2]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                                <description>Page can be read by Non-secure software, and Secure software may permit Non-secure writes.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                                <description>Page can be read by Non-secure software</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>reserved</name>
+                                <value>2</value>
+                                <description>Do not use. Behaves the same as INACCESSIBLE.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                                <description>Page can not be accessed by Non-secure software.</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>LOCK_S</name>
+                        <description>Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers.</description>
+                        <bitRange>[1:0]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                                <description>Page is fully accessible by Secure software.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                                <description>Page can be read by Secure software, but can not be written.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>reserved</name>
+                                <value>2</value>
+                                <description>Do not use. Behaves the same as INACCESSIBLE.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                                <description>Page can not be accessed by Secure software.</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PAGE18_LOCK0</name>
+                <addressOffset>0x003e90</addressOffset>
+                <description>Lock configuration LSBs for page 18 (rows 0x480 through 0x4bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently.
+
+                    This OTP location is always readable, and is write-protected by its own permissions.</description>
+                <size>24</size>
+                <resetValue>0x000000</resetValue>
+                <fields>
+                    <field>
+                        <name>R2</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[23:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>R1</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[15:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>NO_KEY_STATE</name>
+                        <description>State when at least one key is registered for this page and no matching key has been entered.</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>KEY_R</name>
+                        <description>Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required.</description>
+                        <bitRange>[5:3]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>KEY_W</name>
+                        <description>Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required.</description>
+                        <bitRange>[2:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PAGE18_LOCK1</name>
+                <addressOffset>0x003e94</addressOffset>
+                <description>Lock configuration MSBs for page 18 (rows 0x480 through 0x4bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently.
+
+                    This OTP location is always readable, and is write-protected by its own permissions.</description>
+                <size>24</size>
+                <resetValue>0x000000</resetValue>
+                <fields>
+                    <field>
+                        <name>R2</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[23:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>R1</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[15:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>LOCK_BL</name>
+                        <description>Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers.</description>
+                        <bitRange>[5:4]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                                <description>Bootloader permits user reads and writes to this page</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                                <description>Bootloader permits user reads of this page</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>reserved</name>
+                                <value>2</value>
+                                <description>Do not use. Behaves the same as INACCESSIBLE</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                                <description>Bootloader does not permit user access to this page</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>LOCK_NS</name>
+                        <description>Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers.
+
+                            Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API.</description>
+                        <bitRange>[3:2]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                                <description>Page can be read by Non-secure software, and Secure software may permit Non-secure writes.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                                <description>Page can be read by Non-secure software</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>reserved</name>
+                                <value>2</value>
+                                <description>Do not use. Behaves the same as INACCESSIBLE.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                                <description>Page can not be accessed by Non-secure software.</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>LOCK_S</name>
+                        <description>Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers.</description>
+                        <bitRange>[1:0]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                                <description>Page is fully accessible by Secure software.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                                <description>Page can be read by Secure software, but can not be written.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>reserved</name>
+                                <value>2</value>
+                                <description>Do not use. Behaves the same as INACCESSIBLE.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                                <description>Page can not be accessed by Secure software.</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PAGE19_LOCK0</name>
+                <addressOffset>0x003e98</addressOffset>
+                <description>Lock configuration LSBs for page 19 (rows 0x4c0 through 0x4ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently.
+
+                    This OTP location is always readable, and is write-protected by its own permissions.</description>
+                <size>24</size>
+                <resetValue>0x000000</resetValue>
+                <fields>
+                    <field>
+                        <name>R2</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[23:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>R1</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[15:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>NO_KEY_STATE</name>
+                        <description>State when at least one key is registered for this page and no matching key has been entered.</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>KEY_R</name>
+                        <description>Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required.</description>
+                        <bitRange>[5:3]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>KEY_W</name>
+                        <description>Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required.</description>
+                        <bitRange>[2:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PAGE19_LOCK1</name>
+                <addressOffset>0x003e9c</addressOffset>
+                <description>Lock configuration MSBs for page 19 (rows 0x4c0 through 0x4ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently.
+
+                    This OTP location is always readable, and is write-protected by its own permissions.</description>
+                <size>24</size>
+                <resetValue>0x000000</resetValue>
+                <fields>
+                    <field>
+                        <name>R2</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[23:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>R1</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[15:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>LOCK_BL</name>
+                        <description>Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers.</description>
+                        <bitRange>[5:4]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                                <description>Bootloader permits user reads and writes to this page</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                                <description>Bootloader permits user reads of this page</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>reserved</name>
+                                <value>2</value>
+                                <description>Do not use. Behaves the same as INACCESSIBLE</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                                <description>Bootloader does not permit user access to this page</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>LOCK_NS</name>
+                        <description>Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers.
+
+                            Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API.</description>
+                        <bitRange>[3:2]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                                <description>Page can be read by Non-secure software, and Secure software may permit Non-secure writes.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                                <description>Page can be read by Non-secure software</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>reserved</name>
+                                <value>2</value>
+                                <description>Do not use. Behaves the same as INACCESSIBLE.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                                <description>Page can not be accessed by Non-secure software.</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>LOCK_S</name>
+                        <description>Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers.</description>
+                        <bitRange>[1:0]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                                <description>Page is fully accessible by Secure software.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                                <description>Page can be read by Secure software, but can not be written.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>reserved</name>
+                                <value>2</value>
+                                <description>Do not use. Behaves the same as INACCESSIBLE.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                                <description>Page can not be accessed by Secure software.</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PAGE20_LOCK0</name>
+                <addressOffset>0x003ea0</addressOffset>
+                <description>Lock configuration LSBs for page 20 (rows 0x500 through 0x53f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently.
+
+                    This OTP location is always readable, and is write-protected by its own permissions.</description>
+                <size>24</size>
+                <resetValue>0x000000</resetValue>
+                <fields>
+                    <field>
+                        <name>R2</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[23:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>R1</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[15:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>NO_KEY_STATE</name>
+                        <description>State when at least one key is registered for this page and no matching key has been entered.</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>KEY_R</name>
+                        <description>Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required.</description>
+                        <bitRange>[5:3]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>KEY_W</name>
+                        <description>Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required.</description>
+                        <bitRange>[2:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PAGE20_LOCK1</name>
+                <addressOffset>0x003ea4</addressOffset>
+                <description>Lock configuration MSBs for page 20 (rows 0x500 through 0x53f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently.
+
+                    This OTP location is always readable, and is write-protected by its own permissions.</description>
+                <size>24</size>
+                <resetValue>0x000000</resetValue>
+                <fields>
+                    <field>
+                        <name>R2</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[23:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>R1</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[15:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>LOCK_BL</name>
+                        <description>Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers.</description>
+                        <bitRange>[5:4]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                                <description>Bootloader permits user reads and writes to this page</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                                <description>Bootloader permits user reads of this page</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>reserved</name>
+                                <value>2</value>
+                                <description>Do not use. Behaves the same as INACCESSIBLE</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                                <description>Bootloader does not permit user access to this page</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>LOCK_NS</name>
+                        <description>Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers.
+
+                            Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API.</description>
+                        <bitRange>[3:2]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                                <description>Page can be read by Non-secure software, and Secure software may permit Non-secure writes.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                                <description>Page can be read by Non-secure software</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>reserved</name>
+                                <value>2</value>
+                                <description>Do not use. Behaves the same as INACCESSIBLE.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                                <description>Page can not be accessed by Non-secure software.</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>LOCK_S</name>
+                        <description>Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers.</description>
+                        <bitRange>[1:0]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                                <description>Page is fully accessible by Secure software.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                                <description>Page can be read by Secure software, but can not be written.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>reserved</name>
+                                <value>2</value>
+                                <description>Do not use. Behaves the same as INACCESSIBLE.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                                <description>Page can not be accessed by Secure software.</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PAGE21_LOCK0</name>
+                <addressOffset>0x003ea8</addressOffset>
+                <description>Lock configuration LSBs for page 21 (rows 0x540 through 0x57f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently.
+
+                    This OTP location is always readable, and is write-protected by its own permissions.</description>
+                <size>24</size>
+                <resetValue>0x000000</resetValue>
+                <fields>
+                    <field>
+                        <name>R2</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[23:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>R1</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[15:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>NO_KEY_STATE</name>
+                        <description>State when at least one key is registered for this page and no matching key has been entered.</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>KEY_R</name>
+                        <description>Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required.</description>
+                        <bitRange>[5:3]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>KEY_W</name>
+                        <description>Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required.</description>
+                        <bitRange>[2:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PAGE21_LOCK1</name>
+                <addressOffset>0x003eac</addressOffset>
+                <description>Lock configuration MSBs for page 21 (rows 0x540 through 0x57f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently.
+
+                    This OTP location is always readable, and is write-protected by its own permissions.</description>
+                <size>24</size>
+                <resetValue>0x000000</resetValue>
+                <fields>
+                    <field>
+                        <name>R2</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[23:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>R1</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[15:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>LOCK_BL</name>
+                        <description>Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers.</description>
+                        <bitRange>[5:4]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                                <description>Bootloader permits user reads and writes to this page</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                                <description>Bootloader permits user reads of this page</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>reserved</name>
+                                <value>2</value>
+                                <description>Do not use. Behaves the same as INACCESSIBLE</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                                <description>Bootloader does not permit user access to this page</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>LOCK_NS</name>
+                        <description>Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers.
+
+                            Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API.</description>
+                        <bitRange>[3:2]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                                <description>Page can be read by Non-secure software, and Secure software may permit Non-secure writes.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                                <description>Page can be read by Non-secure software</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>reserved</name>
+                                <value>2</value>
+                                <description>Do not use. Behaves the same as INACCESSIBLE.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                                <description>Page can not be accessed by Non-secure software.</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>LOCK_S</name>
+                        <description>Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers.</description>
+                        <bitRange>[1:0]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                                <description>Page is fully accessible by Secure software.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                                <description>Page can be read by Secure software, but can not be written.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>reserved</name>
+                                <value>2</value>
+                                <description>Do not use. Behaves the same as INACCESSIBLE.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                                <description>Page can not be accessed by Secure software.</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PAGE22_LOCK0</name>
+                <addressOffset>0x003eb0</addressOffset>
+                <description>Lock configuration LSBs for page 22 (rows 0x580 through 0x5bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently.
+
+                    This OTP location is always readable, and is write-protected by its own permissions.</description>
+                <size>24</size>
+                <resetValue>0x000000</resetValue>
+                <fields>
+                    <field>
+                        <name>R2</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[23:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>R1</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[15:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>NO_KEY_STATE</name>
+                        <description>State when at least one key is registered for this page and no matching key has been entered.</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>KEY_R</name>
+                        <description>Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required.</description>
+                        <bitRange>[5:3]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>KEY_W</name>
+                        <description>Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required.</description>
+                        <bitRange>[2:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PAGE22_LOCK1</name>
+                <addressOffset>0x003eb4</addressOffset>
+                <description>Lock configuration MSBs for page 22 (rows 0x580 through 0x5bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently.
+
+                    This OTP location is always readable, and is write-protected by its own permissions.</description>
+                <size>24</size>
+                <resetValue>0x000000</resetValue>
+                <fields>
+                    <field>
+                        <name>R2</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[23:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>R1</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[15:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>LOCK_BL</name>
+                        <description>Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers.</description>
+                        <bitRange>[5:4]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                                <description>Bootloader permits user reads and writes to this page</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                                <description>Bootloader permits user reads of this page</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>reserved</name>
+                                <value>2</value>
+                                <description>Do not use. Behaves the same as INACCESSIBLE</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                                <description>Bootloader does not permit user access to this page</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>LOCK_NS</name>
+                        <description>Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers.
+
+                            Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API.</description>
+                        <bitRange>[3:2]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                                <description>Page can be read by Non-secure software, and Secure software may permit Non-secure writes.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                                <description>Page can be read by Non-secure software</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>reserved</name>
+                                <value>2</value>
+                                <description>Do not use. Behaves the same as INACCESSIBLE.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                                <description>Page can not be accessed by Non-secure software.</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>LOCK_S</name>
+                        <description>Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers.</description>
+                        <bitRange>[1:0]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                                <description>Page is fully accessible by Secure software.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                                <description>Page can be read by Secure software, but can not be written.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>reserved</name>
+                                <value>2</value>
+                                <description>Do not use. Behaves the same as INACCESSIBLE.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                                <description>Page can not be accessed by Secure software.</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PAGE23_LOCK0</name>
+                <addressOffset>0x003eb8</addressOffset>
+                <description>Lock configuration LSBs for page 23 (rows 0x5c0 through 0x5ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently.
+
+                    This OTP location is always readable, and is write-protected by its own permissions.</description>
+                <size>24</size>
+                <resetValue>0x000000</resetValue>
+                <fields>
+                    <field>
+                        <name>R2</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[23:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>R1</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[15:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>NO_KEY_STATE</name>
+                        <description>State when at least one key is registered for this page and no matching key has been entered.</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>KEY_R</name>
+                        <description>Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required.</description>
+                        <bitRange>[5:3]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>KEY_W</name>
+                        <description>Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required.</description>
+                        <bitRange>[2:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PAGE23_LOCK1</name>
+                <addressOffset>0x003ebc</addressOffset>
+                <description>Lock configuration MSBs for page 23 (rows 0x5c0 through 0x5ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently.
+
+                    This OTP location is always readable, and is write-protected by its own permissions.</description>
+                <size>24</size>
+                <resetValue>0x000000</resetValue>
+                <fields>
+                    <field>
+                        <name>R2</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[23:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>R1</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[15:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>LOCK_BL</name>
+                        <description>Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers.</description>
+                        <bitRange>[5:4]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                                <description>Bootloader permits user reads and writes to this page</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                                <description>Bootloader permits user reads of this page</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>reserved</name>
+                                <value>2</value>
+                                <description>Do not use. Behaves the same as INACCESSIBLE</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                                <description>Bootloader does not permit user access to this page</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>LOCK_NS</name>
+                        <description>Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers.
+
+                            Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API.</description>
+                        <bitRange>[3:2]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                                <description>Page can be read by Non-secure software, and Secure software may permit Non-secure writes.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                                <description>Page can be read by Non-secure software</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>reserved</name>
+                                <value>2</value>
+                                <description>Do not use. Behaves the same as INACCESSIBLE.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                                <description>Page can not be accessed by Non-secure software.</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>LOCK_S</name>
+                        <description>Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers.</description>
+                        <bitRange>[1:0]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                                <description>Page is fully accessible by Secure software.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                                <description>Page can be read by Secure software, but can not be written.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>reserved</name>
+                                <value>2</value>
+                                <description>Do not use. Behaves the same as INACCESSIBLE.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                                <description>Page can not be accessed by Secure software.</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PAGE24_LOCK0</name>
+                <addressOffset>0x003ec0</addressOffset>
+                <description>Lock configuration LSBs for page 24 (rows 0x600 through 0x63f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently.
+
+                    This OTP location is always readable, and is write-protected by its own permissions.</description>
+                <size>24</size>
+                <resetValue>0x000000</resetValue>
+                <fields>
+                    <field>
+                        <name>R2</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[23:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>R1</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[15:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>NO_KEY_STATE</name>
+                        <description>State when at least one key is registered for this page and no matching key has been entered.</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>KEY_R</name>
+                        <description>Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required.</description>
+                        <bitRange>[5:3]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>KEY_W</name>
+                        <description>Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required.</description>
+                        <bitRange>[2:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PAGE24_LOCK1</name>
+                <addressOffset>0x003ec4</addressOffset>
+                <description>Lock configuration MSBs for page 24 (rows 0x600 through 0x63f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently.
+
+                    This OTP location is always readable, and is write-protected by its own permissions.</description>
+                <size>24</size>
+                <resetValue>0x000000</resetValue>
+                <fields>
+                    <field>
+                        <name>R2</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[23:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>R1</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[15:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>LOCK_BL</name>
+                        <description>Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers.</description>
+                        <bitRange>[5:4]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                                <description>Bootloader permits user reads and writes to this page</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                                <description>Bootloader permits user reads of this page</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>reserved</name>
+                                <value>2</value>
+                                <description>Do not use. Behaves the same as INACCESSIBLE</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                                <description>Bootloader does not permit user access to this page</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>LOCK_NS</name>
+                        <description>Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers.
+
+                            Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API.</description>
+                        <bitRange>[3:2]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                                <description>Page can be read by Non-secure software, and Secure software may permit Non-secure writes.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                                <description>Page can be read by Non-secure software</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>reserved</name>
+                                <value>2</value>
+                                <description>Do not use. Behaves the same as INACCESSIBLE.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                                <description>Page can not be accessed by Non-secure software.</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>LOCK_S</name>
+                        <description>Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers.</description>
+                        <bitRange>[1:0]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                                <description>Page is fully accessible by Secure software.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                                <description>Page can be read by Secure software, but can not be written.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>reserved</name>
+                                <value>2</value>
+                                <description>Do not use. Behaves the same as INACCESSIBLE.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                                <description>Page can not be accessed by Secure software.</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PAGE25_LOCK0</name>
+                <addressOffset>0x003ec8</addressOffset>
+                <description>Lock configuration LSBs for page 25 (rows 0x640 through 0x67f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently.
+
+                    This OTP location is always readable, and is write-protected by its own permissions.</description>
+                <size>24</size>
+                <resetValue>0x000000</resetValue>
+                <fields>
+                    <field>
+                        <name>R2</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[23:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>R1</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[15:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>NO_KEY_STATE</name>
+                        <description>State when at least one key is registered for this page and no matching key has been entered.</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>KEY_R</name>
+                        <description>Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required.</description>
+                        <bitRange>[5:3]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>KEY_W</name>
+                        <description>Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required.</description>
+                        <bitRange>[2:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PAGE25_LOCK1</name>
+                <addressOffset>0x003ecc</addressOffset>
+                <description>Lock configuration MSBs for page 25 (rows 0x640 through 0x67f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently.
+
+                    This OTP location is always readable, and is write-protected by its own permissions.</description>
+                <size>24</size>
+                <resetValue>0x000000</resetValue>
+                <fields>
+                    <field>
+                        <name>R2</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[23:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>R1</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[15:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>LOCK_BL</name>
+                        <description>Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers.</description>
+                        <bitRange>[5:4]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                                <description>Bootloader permits user reads and writes to this page</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                                <description>Bootloader permits user reads of this page</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>reserved</name>
+                                <value>2</value>
+                                <description>Do not use. Behaves the same as INACCESSIBLE</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                                <description>Bootloader does not permit user access to this page</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>LOCK_NS</name>
+                        <description>Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers.
+
+                            Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API.</description>
+                        <bitRange>[3:2]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                                <description>Page can be read by Non-secure software, and Secure software may permit Non-secure writes.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                                <description>Page can be read by Non-secure software</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>reserved</name>
+                                <value>2</value>
+                                <description>Do not use. Behaves the same as INACCESSIBLE.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                                <description>Page can not be accessed by Non-secure software.</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>LOCK_S</name>
+                        <description>Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers.</description>
+                        <bitRange>[1:0]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                                <description>Page is fully accessible by Secure software.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                                <description>Page can be read by Secure software, but can not be written.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>reserved</name>
+                                <value>2</value>
+                                <description>Do not use. Behaves the same as INACCESSIBLE.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                                <description>Page can not be accessed by Secure software.</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PAGE26_LOCK0</name>
+                <addressOffset>0x003ed0</addressOffset>
+                <description>Lock configuration LSBs for page 26 (rows 0x680 through 0x6bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently.
+
+                    This OTP location is always readable, and is write-protected by its own permissions.</description>
+                <size>24</size>
+                <resetValue>0x000000</resetValue>
+                <fields>
+                    <field>
+                        <name>R2</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[23:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>R1</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[15:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>NO_KEY_STATE</name>
+                        <description>State when at least one key is registered for this page and no matching key has been entered.</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>KEY_R</name>
+                        <description>Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required.</description>
+                        <bitRange>[5:3]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>KEY_W</name>
+                        <description>Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required.</description>
+                        <bitRange>[2:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PAGE26_LOCK1</name>
+                <addressOffset>0x003ed4</addressOffset>
+                <description>Lock configuration MSBs for page 26 (rows 0x680 through 0x6bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently.
+
+                    This OTP location is always readable, and is write-protected by its own permissions.</description>
+                <size>24</size>
+                <resetValue>0x000000</resetValue>
+                <fields>
+                    <field>
+                        <name>R2</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[23:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>R1</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[15:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>LOCK_BL</name>
+                        <description>Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers.</description>
+                        <bitRange>[5:4]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                                <description>Bootloader permits user reads and writes to this page</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                                <description>Bootloader permits user reads of this page</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>reserved</name>
+                                <value>2</value>
+                                <description>Do not use. Behaves the same as INACCESSIBLE</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                                <description>Bootloader does not permit user access to this page</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>LOCK_NS</name>
+                        <description>Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers.
+
+                            Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API.</description>
+                        <bitRange>[3:2]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                                <description>Page can be read by Non-secure software, and Secure software may permit Non-secure writes.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                                <description>Page can be read by Non-secure software</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>reserved</name>
+                                <value>2</value>
+                                <description>Do not use. Behaves the same as INACCESSIBLE.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                                <description>Page can not be accessed by Non-secure software.</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>LOCK_S</name>
+                        <description>Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers.</description>
+                        <bitRange>[1:0]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                                <description>Page is fully accessible by Secure software.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                                <description>Page can be read by Secure software, but can not be written.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>reserved</name>
+                                <value>2</value>
+                                <description>Do not use. Behaves the same as INACCESSIBLE.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                                <description>Page can not be accessed by Secure software.</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PAGE27_LOCK0</name>
+                <addressOffset>0x003ed8</addressOffset>
+                <description>Lock configuration LSBs for page 27 (rows 0x6c0 through 0x6ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently.
+
+                    This OTP location is always readable, and is write-protected by its own permissions.</description>
+                <size>24</size>
+                <resetValue>0x000000</resetValue>
+                <fields>
+                    <field>
+                        <name>R2</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[23:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>R1</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[15:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>NO_KEY_STATE</name>
+                        <description>State when at least one key is registered for this page and no matching key has been entered.</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>KEY_R</name>
+                        <description>Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required.</description>
+                        <bitRange>[5:3]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>KEY_W</name>
+                        <description>Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required.</description>
+                        <bitRange>[2:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PAGE27_LOCK1</name>
+                <addressOffset>0x003edc</addressOffset>
+                <description>Lock configuration MSBs for page 27 (rows 0x6c0 through 0x6ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently.
+
+                    This OTP location is always readable, and is write-protected by its own permissions.</description>
+                <size>24</size>
+                <resetValue>0x000000</resetValue>
+                <fields>
+                    <field>
+                        <name>R2</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[23:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>R1</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[15:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>LOCK_BL</name>
+                        <description>Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers.</description>
+                        <bitRange>[5:4]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                                <description>Bootloader permits user reads and writes to this page</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                                <description>Bootloader permits user reads of this page</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>reserved</name>
+                                <value>2</value>
+                                <description>Do not use. Behaves the same as INACCESSIBLE</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                                <description>Bootloader does not permit user access to this page</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>LOCK_NS</name>
+                        <description>Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers.
+
+                            Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API.</description>
+                        <bitRange>[3:2]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                                <description>Page can be read by Non-secure software, and Secure software may permit Non-secure writes.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                                <description>Page can be read by Non-secure software</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>reserved</name>
+                                <value>2</value>
+                                <description>Do not use. Behaves the same as INACCESSIBLE.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                                <description>Page can not be accessed by Non-secure software.</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>LOCK_S</name>
+                        <description>Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers.</description>
+                        <bitRange>[1:0]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                                <description>Page is fully accessible by Secure software.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                                <description>Page can be read by Secure software, but can not be written.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>reserved</name>
+                                <value>2</value>
+                                <description>Do not use. Behaves the same as INACCESSIBLE.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                                <description>Page can not be accessed by Secure software.</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PAGE28_LOCK0</name>
+                <addressOffset>0x003ee0</addressOffset>
+                <description>Lock configuration LSBs for page 28 (rows 0x700 through 0x73f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently.
+
+                    This OTP location is always readable, and is write-protected by its own permissions.</description>
+                <size>24</size>
+                <resetValue>0x000000</resetValue>
+                <fields>
+                    <field>
+                        <name>R2</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[23:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>R1</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[15:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>NO_KEY_STATE</name>
+                        <description>State when at least one key is registered for this page and no matching key has been entered.</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>KEY_R</name>
+                        <description>Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required.</description>
+                        <bitRange>[5:3]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>KEY_W</name>
+                        <description>Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required.</description>
+                        <bitRange>[2:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PAGE28_LOCK1</name>
+                <addressOffset>0x003ee4</addressOffset>
+                <description>Lock configuration MSBs for page 28 (rows 0x700 through 0x73f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently.
+
+                    This OTP location is always readable, and is write-protected by its own permissions.</description>
+                <size>24</size>
+                <resetValue>0x000000</resetValue>
+                <fields>
+                    <field>
+                        <name>R2</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[23:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>R1</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[15:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>LOCK_BL</name>
+                        <description>Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers.</description>
+                        <bitRange>[5:4]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                                <description>Bootloader permits user reads and writes to this page</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                                <description>Bootloader permits user reads of this page</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>reserved</name>
+                                <value>2</value>
+                                <description>Do not use. Behaves the same as INACCESSIBLE</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                                <description>Bootloader does not permit user access to this page</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>LOCK_NS</name>
+                        <description>Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers.
+
+                            Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API.</description>
+                        <bitRange>[3:2]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                                <description>Page can be read by Non-secure software, and Secure software may permit Non-secure writes.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                                <description>Page can be read by Non-secure software</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>reserved</name>
+                                <value>2</value>
+                                <description>Do not use. Behaves the same as INACCESSIBLE.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                                <description>Page can not be accessed by Non-secure software.</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>LOCK_S</name>
+                        <description>Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers.</description>
+                        <bitRange>[1:0]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                                <description>Page is fully accessible by Secure software.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                                <description>Page can be read by Secure software, but can not be written.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>reserved</name>
+                                <value>2</value>
+                                <description>Do not use. Behaves the same as INACCESSIBLE.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                                <description>Page can not be accessed by Secure software.</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PAGE29_LOCK0</name>
+                <addressOffset>0x003ee8</addressOffset>
+                <description>Lock configuration LSBs for page 29 (rows 0x740 through 0x77f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently.
+
+                    This OTP location is always readable, and is write-protected by its own permissions.</description>
+                <size>24</size>
+                <resetValue>0x000000</resetValue>
+                <fields>
+                    <field>
+                        <name>R2</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[23:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>R1</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[15:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>NO_KEY_STATE</name>
+                        <description>State when at least one key is registered for this page and no matching key has been entered.</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>KEY_R</name>
+                        <description>Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required.</description>
+                        <bitRange>[5:3]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>KEY_W</name>
+                        <description>Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required.</description>
+                        <bitRange>[2:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PAGE29_LOCK1</name>
+                <addressOffset>0x003eec</addressOffset>
+                <description>Lock configuration MSBs for page 29 (rows 0x740 through 0x77f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently.
+
+                    This OTP location is always readable, and is write-protected by its own permissions.</description>
+                <size>24</size>
+                <resetValue>0x000000</resetValue>
+                <fields>
+                    <field>
+                        <name>R2</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[23:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>R1</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[15:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>LOCK_BL</name>
+                        <description>Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers.</description>
+                        <bitRange>[5:4]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                                <description>Bootloader permits user reads and writes to this page</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                                <description>Bootloader permits user reads of this page</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>reserved</name>
+                                <value>2</value>
+                                <description>Do not use. Behaves the same as INACCESSIBLE</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                                <description>Bootloader does not permit user access to this page</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>LOCK_NS</name>
+                        <description>Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers.
+
+                            Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API.</description>
+                        <bitRange>[3:2]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                                <description>Page can be read by Non-secure software, and Secure software may permit Non-secure writes.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                                <description>Page can be read by Non-secure software</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>reserved</name>
+                                <value>2</value>
+                                <description>Do not use. Behaves the same as INACCESSIBLE.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                                <description>Page can not be accessed by Non-secure software.</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>LOCK_S</name>
+                        <description>Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers.</description>
+                        <bitRange>[1:0]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                                <description>Page is fully accessible by Secure software.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                                <description>Page can be read by Secure software, but can not be written.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>reserved</name>
+                                <value>2</value>
+                                <description>Do not use. Behaves the same as INACCESSIBLE.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                                <description>Page can not be accessed by Secure software.</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PAGE30_LOCK0</name>
+                <addressOffset>0x003ef0</addressOffset>
+                <description>Lock configuration LSBs for page 30 (rows 0x780 through 0x7bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently.
+
+                    This OTP location is always readable, and is write-protected by its own permissions.</description>
+                <size>24</size>
+                <resetValue>0x000000</resetValue>
+                <fields>
+                    <field>
+                        <name>R2</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[23:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>R1</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[15:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>NO_KEY_STATE</name>
+                        <description>State when at least one key is registered for this page and no matching key has been entered.</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>KEY_R</name>
+                        <description>Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required.</description>
+                        <bitRange>[5:3]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>KEY_W</name>
+                        <description>Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required.</description>
+                        <bitRange>[2:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PAGE30_LOCK1</name>
+                <addressOffset>0x003ef4</addressOffset>
+                <description>Lock configuration MSBs for page 30 (rows 0x780 through 0x7bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently.
+
+                    This OTP location is always readable, and is write-protected by its own permissions.</description>
+                <size>24</size>
+                <resetValue>0x000000</resetValue>
+                <fields>
+                    <field>
+                        <name>R2</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[23:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>R1</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[15:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>LOCK_BL</name>
+                        <description>Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers.</description>
+                        <bitRange>[5:4]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                                <description>Bootloader permits user reads and writes to this page</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                                <description>Bootloader permits user reads of this page</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>reserved</name>
+                                <value>2</value>
+                                <description>Do not use. Behaves the same as INACCESSIBLE</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                                <description>Bootloader does not permit user access to this page</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>LOCK_NS</name>
+                        <description>Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers.
+
+                            Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API.</description>
+                        <bitRange>[3:2]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                                <description>Page can be read by Non-secure software, and Secure software may permit Non-secure writes.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                                <description>Page can be read by Non-secure software</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>reserved</name>
+                                <value>2</value>
+                                <description>Do not use. Behaves the same as INACCESSIBLE.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                                <description>Page can not be accessed by Non-secure software.</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>LOCK_S</name>
+                        <description>Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers.</description>
+                        <bitRange>[1:0]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                                <description>Page is fully accessible by Secure software.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                                <description>Page can be read by Secure software, but can not be written.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>reserved</name>
+                                <value>2</value>
+                                <description>Do not use. Behaves the same as INACCESSIBLE.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                                <description>Page can not be accessed by Secure software.</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PAGE31_LOCK0</name>
+                <addressOffset>0x003ef8</addressOffset>
+                <description>Lock configuration LSBs for page 31 (rows 0x7c0 through 0x7ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently.
+
+                    This OTP location is always readable, and is write-protected by its own permissions.</description>
+                <size>24</size>
+                <resetValue>0x000000</resetValue>
+                <fields>
+                    <field>
+                        <name>R2</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[23:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>R1</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[15:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>NO_KEY_STATE</name>
+                        <description>State when at least one key is registered for this page and no matching key has been entered.</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>KEY_R</name>
+                        <description>Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required.</description>
+                        <bitRange>[5:3]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>KEY_W</name>
+                        <description>Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required.</description>
+                        <bitRange>[2:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PAGE31_LOCK1</name>
+                <addressOffset>0x003efc</addressOffset>
+                <description>Lock configuration MSBs for page 31 (rows 0x7c0 through 0x7ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently.
+
+                    This OTP location is always readable, and is write-protected by its own permissions.</description>
+                <size>24</size>
+                <resetValue>0x000000</resetValue>
+                <fields>
+                    <field>
+                        <name>R2</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[23:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>R1</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[15:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>LOCK_BL</name>
+                        <description>Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers.</description>
+                        <bitRange>[5:4]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                                <description>Bootloader permits user reads and writes to this page</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                                <description>Bootloader permits user reads of this page</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>reserved</name>
+                                <value>2</value>
+                                <description>Do not use. Behaves the same as INACCESSIBLE</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                                <description>Bootloader does not permit user access to this page</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>LOCK_NS</name>
+                        <description>Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers.
+
+                            Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API.</description>
+                        <bitRange>[3:2]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                                <description>Page can be read by Non-secure software, and Secure software may permit Non-secure writes.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                                <description>Page can be read by Non-secure software</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>reserved</name>
+                                <value>2</value>
+                                <description>Do not use. Behaves the same as INACCESSIBLE.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                                <description>Page can not be accessed by Non-secure software.</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>LOCK_S</name>
+                        <description>Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers.</description>
+                        <bitRange>[1:0]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                                <description>Page is fully accessible by Secure software.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                                <description>Page can be read by Secure software, but can not be written.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>reserved</name>
+                                <value>2</value>
+                                <description>Do not use. Behaves the same as INACCESSIBLE.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                                <description>Page can not be accessed by Secure software.</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PAGE32_LOCK0</name>
+                <addressOffset>0x003f00</addressOffset>
+                <description>Lock configuration LSBs for page 32 (rows 0x800 through 0x83f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently.
+
+                    This OTP location is always readable, and is write-protected by its own permissions.</description>
+                <size>24</size>
+                <resetValue>0x000000</resetValue>
+                <fields>
+                    <field>
+                        <name>R2</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[23:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>R1</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[15:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>NO_KEY_STATE</name>
+                        <description>State when at least one key is registered for this page and no matching key has been entered.</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>KEY_R</name>
+                        <description>Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required.</description>
+                        <bitRange>[5:3]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>KEY_W</name>
+                        <description>Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required.</description>
+                        <bitRange>[2:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PAGE32_LOCK1</name>
+                <addressOffset>0x003f04</addressOffset>
+                <description>Lock configuration MSBs for page 32 (rows 0x800 through 0x83f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently.
+
+                    This OTP location is always readable, and is write-protected by its own permissions.</description>
+                <size>24</size>
+                <resetValue>0x000000</resetValue>
+                <fields>
+                    <field>
+                        <name>R2</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[23:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>R1</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[15:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>LOCK_BL</name>
+                        <description>Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers.</description>
+                        <bitRange>[5:4]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                                <description>Bootloader permits user reads and writes to this page</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                                <description>Bootloader permits user reads of this page</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>reserved</name>
+                                <value>2</value>
+                                <description>Do not use. Behaves the same as INACCESSIBLE</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                                <description>Bootloader does not permit user access to this page</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>LOCK_NS</name>
+                        <description>Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers.
+
+                            Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API.</description>
+                        <bitRange>[3:2]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                                <description>Page can be read by Non-secure software, and Secure software may permit Non-secure writes.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                                <description>Page can be read by Non-secure software</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>reserved</name>
+                                <value>2</value>
+                                <description>Do not use. Behaves the same as INACCESSIBLE.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                                <description>Page can not be accessed by Non-secure software.</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>LOCK_S</name>
+                        <description>Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers.</description>
+                        <bitRange>[1:0]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                                <description>Page is fully accessible by Secure software.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                                <description>Page can be read by Secure software, but can not be written.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>reserved</name>
+                                <value>2</value>
+                                <description>Do not use. Behaves the same as INACCESSIBLE.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                                <description>Page can not be accessed by Secure software.</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PAGE33_LOCK0</name>
+                <addressOffset>0x003f08</addressOffset>
+                <description>Lock configuration LSBs for page 33 (rows 0x840 through 0x87f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently.
+
+                    This OTP location is always readable, and is write-protected by its own permissions.</description>
+                <size>24</size>
+                <resetValue>0x000000</resetValue>
+                <fields>
+                    <field>
+                        <name>R2</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[23:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>R1</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[15:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>NO_KEY_STATE</name>
+                        <description>State when at least one key is registered for this page and no matching key has been entered.</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>KEY_R</name>
+                        <description>Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required.</description>
+                        <bitRange>[5:3]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>KEY_W</name>
+                        <description>Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required.</description>
+                        <bitRange>[2:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PAGE33_LOCK1</name>
+                <addressOffset>0x003f0c</addressOffset>
+                <description>Lock configuration MSBs for page 33 (rows 0x840 through 0x87f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently.
+
+                    This OTP location is always readable, and is write-protected by its own permissions.</description>
+                <size>24</size>
+                <resetValue>0x000000</resetValue>
+                <fields>
+                    <field>
+                        <name>R2</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[23:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>R1</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[15:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>LOCK_BL</name>
+                        <description>Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers.</description>
+                        <bitRange>[5:4]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                                <description>Bootloader permits user reads and writes to this page</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                                <description>Bootloader permits user reads of this page</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>reserved</name>
+                                <value>2</value>
+                                <description>Do not use. Behaves the same as INACCESSIBLE</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                                <description>Bootloader does not permit user access to this page</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>LOCK_NS</name>
+                        <description>Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers.
+
+                            Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API.</description>
+                        <bitRange>[3:2]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                                <description>Page can be read by Non-secure software, and Secure software may permit Non-secure writes.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                                <description>Page can be read by Non-secure software</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>reserved</name>
+                                <value>2</value>
+                                <description>Do not use. Behaves the same as INACCESSIBLE.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                                <description>Page can not be accessed by Non-secure software.</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>LOCK_S</name>
+                        <description>Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers.</description>
+                        <bitRange>[1:0]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                                <description>Page is fully accessible by Secure software.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                                <description>Page can be read by Secure software, but can not be written.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>reserved</name>
+                                <value>2</value>
+                                <description>Do not use. Behaves the same as INACCESSIBLE.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                                <description>Page can not be accessed by Secure software.</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PAGE34_LOCK0</name>
+                <addressOffset>0x003f10</addressOffset>
+                <description>Lock configuration LSBs for page 34 (rows 0x880 through 0x8bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently.
+
+                    This OTP location is always readable, and is write-protected by its own permissions.</description>
+                <size>24</size>
+                <resetValue>0x000000</resetValue>
+                <fields>
+                    <field>
+                        <name>R2</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[23:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>R1</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[15:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>NO_KEY_STATE</name>
+                        <description>State when at least one key is registered for this page and no matching key has been entered.</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>KEY_R</name>
+                        <description>Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required.</description>
+                        <bitRange>[5:3]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>KEY_W</name>
+                        <description>Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required.</description>
+                        <bitRange>[2:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PAGE34_LOCK1</name>
+                <addressOffset>0x003f14</addressOffset>
+                <description>Lock configuration MSBs for page 34 (rows 0x880 through 0x8bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently.
+
+                    This OTP location is always readable, and is write-protected by its own permissions.</description>
+                <size>24</size>
+                <resetValue>0x000000</resetValue>
+                <fields>
+                    <field>
+                        <name>R2</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[23:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>R1</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[15:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>LOCK_BL</name>
+                        <description>Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers.</description>
+                        <bitRange>[5:4]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                                <description>Bootloader permits user reads and writes to this page</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                                <description>Bootloader permits user reads of this page</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>reserved</name>
+                                <value>2</value>
+                                <description>Do not use. Behaves the same as INACCESSIBLE</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                                <description>Bootloader does not permit user access to this page</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>LOCK_NS</name>
+                        <description>Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers.
+
+                            Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API.</description>
+                        <bitRange>[3:2]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                                <description>Page can be read by Non-secure software, and Secure software may permit Non-secure writes.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                                <description>Page can be read by Non-secure software</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>reserved</name>
+                                <value>2</value>
+                                <description>Do not use. Behaves the same as INACCESSIBLE.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                                <description>Page can not be accessed by Non-secure software.</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>LOCK_S</name>
+                        <description>Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers.</description>
+                        <bitRange>[1:0]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                                <description>Page is fully accessible by Secure software.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                                <description>Page can be read by Secure software, but can not be written.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>reserved</name>
+                                <value>2</value>
+                                <description>Do not use. Behaves the same as INACCESSIBLE.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                                <description>Page can not be accessed by Secure software.</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PAGE35_LOCK0</name>
+                <addressOffset>0x003f18</addressOffset>
+                <description>Lock configuration LSBs for page 35 (rows 0x8c0 through 0x8ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently.
+
+                    This OTP location is always readable, and is write-protected by its own permissions.</description>
+                <size>24</size>
+                <resetValue>0x000000</resetValue>
+                <fields>
+                    <field>
+                        <name>R2</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[23:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>R1</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[15:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>NO_KEY_STATE</name>
+                        <description>State when at least one key is registered for this page and no matching key has been entered.</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>KEY_R</name>
+                        <description>Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required.</description>
+                        <bitRange>[5:3]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>KEY_W</name>
+                        <description>Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required.</description>
+                        <bitRange>[2:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PAGE35_LOCK1</name>
+                <addressOffset>0x003f1c</addressOffset>
+                <description>Lock configuration MSBs for page 35 (rows 0x8c0 through 0x8ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently.
+
+                    This OTP location is always readable, and is write-protected by its own permissions.</description>
+                <size>24</size>
+                <resetValue>0x000000</resetValue>
+                <fields>
+                    <field>
+                        <name>R2</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[23:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>R1</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[15:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>LOCK_BL</name>
+                        <description>Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers.</description>
+                        <bitRange>[5:4]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                                <description>Bootloader permits user reads and writes to this page</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                                <description>Bootloader permits user reads of this page</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>reserved</name>
+                                <value>2</value>
+                                <description>Do not use. Behaves the same as INACCESSIBLE</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                                <description>Bootloader does not permit user access to this page</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>LOCK_NS</name>
+                        <description>Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers.
+
+                            Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API.</description>
+                        <bitRange>[3:2]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                                <description>Page can be read by Non-secure software, and Secure software may permit Non-secure writes.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                                <description>Page can be read by Non-secure software</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>reserved</name>
+                                <value>2</value>
+                                <description>Do not use. Behaves the same as INACCESSIBLE.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                                <description>Page can not be accessed by Non-secure software.</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>LOCK_S</name>
+                        <description>Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers.</description>
+                        <bitRange>[1:0]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                                <description>Page is fully accessible by Secure software.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                                <description>Page can be read by Secure software, but can not be written.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>reserved</name>
+                                <value>2</value>
+                                <description>Do not use. Behaves the same as INACCESSIBLE.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                                <description>Page can not be accessed by Secure software.</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PAGE36_LOCK0</name>
+                <addressOffset>0x003f20</addressOffset>
+                <description>Lock configuration LSBs for page 36 (rows 0x900 through 0x93f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently.
+
+                    This OTP location is always readable, and is write-protected by its own permissions.</description>
+                <size>24</size>
+                <resetValue>0x000000</resetValue>
+                <fields>
+                    <field>
+                        <name>R2</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[23:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>R1</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[15:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>NO_KEY_STATE</name>
+                        <description>State when at least one key is registered for this page and no matching key has been entered.</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>KEY_R</name>
+                        <description>Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required.</description>
+                        <bitRange>[5:3]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>KEY_W</name>
+                        <description>Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required.</description>
+                        <bitRange>[2:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PAGE36_LOCK1</name>
+                <addressOffset>0x003f24</addressOffset>
+                <description>Lock configuration MSBs for page 36 (rows 0x900 through 0x93f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently.
+
+                    This OTP location is always readable, and is write-protected by its own permissions.</description>
+                <size>24</size>
+                <resetValue>0x000000</resetValue>
+                <fields>
+                    <field>
+                        <name>R2</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[23:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>R1</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[15:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>LOCK_BL</name>
+                        <description>Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers.</description>
+                        <bitRange>[5:4]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                                <description>Bootloader permits user reads and writes to this page</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                                <description>Bootloader permits user reads of this page</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>reserved</name>
+                                <value>2</value>
+                                <description>Do not use. Behaves the same as INACCESSIBLE</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                                <description>Bootloader does not permit user access to this page</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>LOCK_NS</name>
+                        <description>Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers.
+
+                            Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API.</description>
+                        <bitRange>[3:2]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                                <description>Page can be read by Non-secure software, and Secure software may permit Non-secure writes.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                                <description>Page can be read by Non-secure software</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>reserved</name>
+                                <value>2</value>
+                                <description>Do not use. Behaves the same as INACCESSIBLE.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                                <description>Page can not be accessed by Non-secure software.</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>LOCK_S</name>
+                        <description>Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers.</description>
+                        <bitRange>[1:0]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                                <description>Page is fully accessible by Secure software.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                                <description>Page can be read by Secure software, but can not be written.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>reserved</name>
+                                <value>2</value>
+                                <description>Do not use. Behaves the same as INACCESSIBLE.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                                <description>Page can not be accessed by Secure software.</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PAGE37_LOCK0</name>
+                <addressOffset>0x003f28</addressOffset>
+                <description>Lock configuration LSBs for page 37 (rows 0x940 through 0x97f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently.
+
+                    This OTP location is always readable, and is write-protected by its own permissions.</description>
+                <size>24</size>
+                <resetValue>0x000000</resetValue>
+                <fields>
+                    <field>
+                        <name>R2</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[23:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>R1</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[15:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>NO_KEY_STATE</name>
+                        <description>State when at least one key is registered for this page and no matching key has been entered.</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>KEY_R</name>
+                        <description>Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required.</description>
+                        <bitRange>[5:3]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>KEY_W</name>
+                        <description>Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required.</description>
+                        <bitRange>[2:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PAGE37_LOCK1</name>
+                <addressOffset>0x003f2c</addressOffset>
+                <description>Lock configuration MSBs for page 37 (rows 0x940 through 0x97f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently.
+
+                    This OTP location is always readable, and is write-protected by its own permissions.</description>
+                <size>24</size>
+                <resetValue>0x000000</resetValue>
+                <fields>
+                    <field>
+                        <name>R2</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[23:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>R1</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[15:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>LOCK_BL</name>
+                        <description>Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers.</description>
+                        <bitRange>[5:4]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                                <description>Bootloader permits user reads and writes to this page</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                                <description>Bootloader permits user reads of this page</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>reserved</name>
+                                <value>2</value>
+                                <description>Do not use. Behaves the same as INACCESSIBLE</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                                <description>Bootloader does not permit user access to this page</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>LOCK_NS</name>
+                        <description>Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers.
+
+                            Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API.</description>
+                        <bitRange>[3:2]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                                <description>Page can be read by Non-secure software, and Secure software may permit Non-secure writes.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                                <description>Page can be read by Non-secure software</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>reserved</name>
+                                <value>2</value>
+                                <description>Do not use. Behaves the same as INACCESSIBLE.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                                <description>Page can not be accessed by Non-secure software.</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>LOCK_S</name>
+                        <description>Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers.</description>
+                        <bitRange>[1:0]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                                <description>Page is fully accessible by Secure software.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                                <description>Page can be read by Secure software, but can not be written.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>reserved</name>
+                                <value>2</value>
+                                <description>Do not use. Behaves the same as INACCESSIBLE.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                                <description>Page can not be accessed by Secure software.</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PAGE38_LOCK0</name>
+                <addressOffset>0x003f30</addressOffset>
+                <description>Lock configuration LSBs for page 38 (rows 0x980 through 0x9bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently.
+
+                    This OTP location is always readable, and is write-protected by its own permissions.</description>
+                <size>24</size>
+                <resetValue>0x000000</resetValue>
+                <fields>
+                    <field>
+                        <name>R2</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[23:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>R1</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[15:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>NO_KEY_STATE</name>
+                        <description>State when at least one key is registered for this page and no matching key has been entered.</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>KEY_R</name>
+                        <description>Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required.</description>
+                        <bitRange>[5:3]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>KEY_W</name>
+                        <description>Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required.</description>
+                        <bitRange>[2:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PAGE38_LOCK1</name>
+                <addressOffset>0x003f34</addressOffset>
+                <description>Lock configuration MSBs for page 38 (rows 0x980 through 0x9bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently.
+
+                    This OTP location is always readable, and is write-protected by its own permissions.</description>
+                <size>24</size>
+                <resetValue>0x000000</resetValue>
+                <fields>
+                    <field>
+                        <name>R2</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[23:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>R1</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[15:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>LOCK_BL</name>
+                        <description>Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers.</description>
+                        <bitRange>[5:4]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                                <description>Bootloader permits user reads and writes to this page</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                                <description>Bootloader permits user reads of this page</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>reserved</name>
+                                <value>2</value>
+                                <description>Do not use. Behaves the same as INACCESSIBLE</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                                <description>Bootloader does not permit user access to this page</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>LOCK_NS</name>
+                        <description>Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers.
+
+                            Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API.</description>
+                        <bitRange>[3:2]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                                <description>Page can be read by Non-secure software, and Secure software may permit Non-secure writes.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                                <description>Page can be read by Non-secure software</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>reserved</name>
+                                <value>2</value>
+                                <description>Do not use. Behaves the same as INACCESSIBLE.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                                <description>Page can not be accessed by Non-secure software.</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>LOCK_S</name>
+                        <description>Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers.</description>
+                        <bitRange>[1:0]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                                <description>Page is fully accessible by Secure software.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                                <description>Page can be read by Secure software, but can not be written.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>reserved</name>
+                                <value>2</value>
+                                <description>Do not use. Behaves the same as INACCESSIBLE.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                                <description>Page can not be accessed by Secure software.</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PAGE39_LOCK0</name>
+                <addressOffset>0x003f38</addressOffset>
+                <description>Lock configuration LSBs for page 39 (rows 0x9c0 through 0x9ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently.
+
+                    This OTP location is always readable, and is write-protected by its own permissions.</description>
+                <size>24</size>
+                <resetValue>0x000000</resetValue>
+                <fields>
+                    <field>
+                        <name>R2</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[23:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>R1</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[15:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>NO_KEY_STATE</name>
+                        <description>State when at least one key is registered for this page and no matching key has been entered.</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>KEY_R</name>
+                        <description>Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required.</description>
+                        <bitRange>[5:3]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>KEY_W</name>
+                        <description>Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required.</description>
+                        <bitRange>[2:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PAGE39_LOCK1</name>
+                <addressOffset>0x003f3c</addressOffset>
+                <description>Lock configuration MSBs for page 39 (rows 0x9c0 through 0x9ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently.
+
+                    This OTP location is always readable, and is write-protected by its own permissions.</description>
+                <size>24</size>
+                <resetValue>0x000000</resetValue>
+                <fields>
+                    <field>
+                        <name>R2</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[23:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>R1</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[15:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>LOCK_BL</name>
+                        <description>Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers.</description>
+                        <bitRange>[5:4]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                                <description>Bootloader permits user reads and writes to this page</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                                <description>Bootloader permits user reads of this page</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>reserved</name>
+                                <value>2</value>
+                                <description>Do not use. Behaves the same as INACCESSIBLE</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                                <description>Bootloader does not permit user access to this page</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>LOCK_NS</name>
+                        <description>Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers.
+
+                            Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API.</description>
+                        <bitRange>[3:2]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                                <description>Page can be read by Non-secure software, and Secure software may permit Non-secure writes.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                                <description>Page can be read by Non-secure software</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>reserved</name>
+                                <value>2</value>
+                                <description>Do not use. Behaves the same as INACCESSIBLE.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                                <description>Page can not be accessed by Non-secure software.</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>LOCK_S</name>
+                        <description>Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers.</description>
+                        <bitRange>[1:0]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                                <description>Page is fully accessible by Secure software.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                                <description>Page can be read by Secure software, but can not be written.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>reserved</name>
+                                <value>2</value>
+                                <description>Do not use. Behaves the same as INACCESSIBLE.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                                <description>Page can not be accessed by Secure software.</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PAGE40_LOCK0</name>
+                <addressOffset>0x003f40</addressOffset>
+                <description>Lock configuration LSBs for page 40 (rows 0xa00 through 0xa3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently.
+
+                    This OTP location is always readable, and is write-protected by its own permissions.</description>
+                <size>24</size>
+                <resetValue>0x000000</resetValue>
+                <fields>
+                    <field>
+                        <name>R2</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[23:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>R1</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[15:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>NO_KEY_STATE</name>
+                        <description>State when at least one key is registered for this page and no matching key has been entered.</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>KEY_R</name>
+                        <description>Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required.</description>
+                        <bitRange>[5:3]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>KEY_W</name>
+                        <description>Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required.</description>
+                        <bitRange>[2:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PAGE40_LOCK1</name>
+                <addressOffset>0x003f44</addressOffset>
+                <description>Lock configuration MSBs for page 40 (rows 0xa00 through 0xa3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently.
+
+                    This OTP location is always readable, and is write-protected by its own permissions.</description>
+                <size>24</size>
+                <resetValue>0x000000</resetValue>
+                <fields>
+                    <field>
+                        <name>R2</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[23:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>R1</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[15:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>LOCK_BL</name>
+                        <description>Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers.</description>
+                        <bitRange>[5:4]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                                <description>Bootloader permits user reads and writes to this page</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                                <description>Bootloader permits user reads of this page</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>reserved</name>
+                                <value>2</value>
+                                <description>Do not use. Behaves the same as INACCESSIBLE</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                                <description>Bootloader does not permit user access to this page</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>LOCK_NS</name>
+                        <description>Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers.
+
+                            Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API.</description>
+                        <bitRange>[3:2]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                                <description>Page can be read by Non-secure software, and Secure software may permit Non-secure writes.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                                <description>Page can be read by Non-secure software</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>reserved</name>
+                                <value>2</value>
+                                <description>Do not use. Behaves the same as INACCESSIBLE.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                                <description>Page can not be accessed by Non-secure software.</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>LOCK_S</name>
+                        <description>Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers.</description>
+                        <bitRange>[1:0]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                                <description>Page is fully accessible by Secure software.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                                <description>Page can be read by Secure software, but can not be written.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>reserved</name>
+                                <value>2</value>
+                                <description>Do not use. Behaves the same as INACCESSIBLE.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                                <description>Page can not be accessed by Secure software.</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PAGE41_LOCK0</name>
+                <addressOffset>0x003f48</addressOffset>
+                <description>Lock configuration LSBs for page 41 (rows 0xa40 through 0xa7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently.
+
+                    This OTP location is always readable, and is write-protected by its own permissions.</description>
+                <size>24</size>
+                <resetValue>0x000000</resetValue>
+                <fields>
+                    <field>
+                        <name>R2</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[23:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>R1</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[15:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>NO_KEY_STATE</name>
+                        <description>State when at least one key is registered for this page and no matching key has been entered.</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>KEY_R</name>
+                        <description>Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required.</description>
+                        <bitRange>[5:3]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>KEY_W</name>
+                        <description>Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required.</description>
+                        <bitRange>[2:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PAGE41_LOCK1</name>
+                <addressOffset>0x003f4c</addressOffset>
+                <description>Lock configuration MSBs for page 41 (rows 0xa40 through 0xa7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently.
+
+                    This OTP location is always readable, and is write-protected by its own permissions.</description>
+                <size>24</size>
+                <resetValue>0x000000</resetValue>
+                <fields>
+                    <field>
+                        <name>R2</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[23:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>R1</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[15:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>LOCK_BL</name>
+                        <description>Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers.</description>
+                        <bitRange>[5:4]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                                <description>Bootloader permits user reads and writes to this page</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                                <description>Bootloader permits user reads of this page</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>reserved</name>
+                                <value>2</value>
+                                <description>Do not use. Behaves the same as INACCESSIBLE</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                                <description>Bootloader does not permit user access to this page</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>LOCK_NS</name>
+                        <description>Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers.
+
+                            Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API.</description>
+                        <bitRange>[3:2]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                                <description>Page can be read by Non-secure software, and Secure software may permit Non-secure writes.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                                <description>Page can be read by Non-secure software</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>reserved</name>
+                                <value>2</value>
+                                <description>Do not use. Behaves the same as INACCESSIBLE.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                                <description>Page can not be accessed by Non-secure software.</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>LOCK_S</name>
+                        <description>Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers.</description>
+                        <bitRange>[1:0]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                                <description>Page is fully accessible by Secure software.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                                <description>Page can be read by Secure software, but can not be written.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>reserved</name>
+                                <value>2</value>
+                                <description>Do not use. Behaves the same as INACCESSIBLE.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                                <description>Page can not be accessed by Secure software.</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PAGE42_LOCK0</name>
+                <addressOffset>0x003f50</addressOffset>
+                <description>Lock configuration LSBs for page 42 (rows 0xa80 through 0xabf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently.
+
+                    This OTP location is always readable, and is write-protected by its own permissions.</description>
+                <size>24</size>
+                <resetValue>0x000000</resetValue>
+                <fields>
+                    <field>
+                        <name>R2</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[23:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>R1</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[15:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>NO_KEY_STATE</name>
+                        <description>State when at least one key is registered for this page and no matching key has been entered.</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>KEY_R</name>
+                        <description>Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required.</description>
+                        <bitRange>[5:3]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>KEY_W</name>
+                        <description>Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required.</description>
+                        <bitRange>[2:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PAGE42_LOCK1</name>
+                <addressOffset>0x003f54</addressOffset>
+                <description>Lock configuration MSBs for page 42 (rows 0xa80 through 0xabf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently.
+
+                    This OTP location is always readable, and is write-protected by its own permissions.</description>
+                <size>24</size>
+                <resetValue>0x000000</resetValue>
+                <fields>
+                    <field>
+                        <name>R2</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[23:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>R1</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[15:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>LOCK_BL</name>
+                        <description>Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers.</description>
+                        <bitRange>[5:4]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                                <description>Bootloader permits user reads and writes to this page</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                                <description>Bootloader permits user reads of this page</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>reserved</name>
+                                <value>2</value>
+                                <description>Do not use. Behaves the same as INACCESSIBLE</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                                <description>Bootloader does not permit user access to this page</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>LOCK_NS</name>
+                        <description>Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers.
+
+                            Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API.</description>
+                        <bitRange>[3:2]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                                <description>Page can be read by Non-secure software, and Secure software may permit Non-secure writes.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                                <description>Page can be read by Non-secure software</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>reserved</name>
+                                <value>2</value>
+                                <description>Do not use. Behaves the same as INACCESSIBLE.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                                <description>Page can not be accessed by Non-secure software.</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>LOCK_S</name>
+                        <description>Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers.</description>
+                        <bitRange>[1:0]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                                <description>Page is fully accessible by Secure software.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                                <description>Page can be read by Secure software, but can not be written.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>reserved</name>
+                                <value>2</value>
+                                <description>Do not use. Behaves the same as INACCESSIBLE.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                                <description>Page can not be accessed by Secure software.</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PAGE43_LOCK0</name>
+                <addressOffset>0x003f58</addressOffset>
+                <description>Lock configuration LSBs for page 43 (rows 0xac0 through 0xaff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently.
+
+                    This OTP location is always readable, and is write-protected by its own permissions.</description>
+                <size>24</size>
+                <resetValue>0x000000</resetValue>
+                <fields>
+                    <field>
+                        <name>R2</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[23:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>R1</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[15:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>NO_KEY_STATE</name>
+                        <description>State when at least one key is registered for this page and no matching key has been entered.</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>KEY_R</name>
+                        <description>Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required.</description>
+                        <bitRange>[5:3]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>KEY_W</name>
+                        <description>Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required.</description>
+                        <bitRange>[2:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PAGE43_LOCK1</name>
+                <addressOffset>0x003f5c</addressOffset>
+                <description>Lock configuration MSBs for page 43 (rows 0xac0 through 0xaff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently.
+
+                    This OTP location is always readable, and is write-protected by its own permissions.</description>
+                <size>24</size>
+                <resetValue>0x000000</resetValue>
+                <fields>
+                    <field>
+                        <name>R2</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[23:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>R1</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[15:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>LOCK_BL</name>
+                        <description>Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers.</description>
+                        <bitRange>[5:4]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                                <description>Bootloader permits user reads and writes to this page</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                                <description>Bootloader permits user reads of this page</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>reserved</name>
+                                <value>2</value>
+                                <description>Do not use. Behaves the same as INACCESSIBLE</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                                <description>Bootloader does not permit user access to this page</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>LOCK_NS</name>
+                        <description>Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers.
+
+                            Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API.</description>
+                        <bitRange>[3:2]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                                <description>Page can be read by Non-secure software, and Secure software may permit Non-secure writes.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                                <description>Page can be read by Non-secure software</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>reserved</name>
+                                <value>2</value>
+                                <description>Do not use. Behaves the same as INACCESSIBLE.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                                <description>Page can not be accessed by Non-secure software.</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>LOCK_S</name>
+                        <description>Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers.</description>
+                        <bitRange>[1:0]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                                <description>Page is fully accessible by Secure software.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                                <description>Page can be read by Secure software, but can not be written.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>reserved</name>
+                                <value>2</value>
+                                <description>Do not use. Behaves the same as INACCESSIBLE.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                                <description>Page can not be accessed by Secure software.</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PAGE44_LOCK0</name>
+                <addressOffset>0x003f60</addressOffset>
+                <description>Lock configuration LSBs for page 44 (rows 0xb00 through 0xb3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently.
+
+                    This OTP location is always readable, and is write-protected by its own permissions.</description>
+                <size>24</size>
+                <resetValue>0x000000</resetValue>
+                <fields>
+                    <field>
+                        <name>R2</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[23:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>R1</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[15:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>NO_KEY_STATE</name>
+                        <description>State when at least one key is registered for this page and no matching key has been entered.</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>KEY_R</name>
+                        <description>Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required.</description>
+                        <bitRange>[5:3]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>KEY_W</name>
+                        <description>Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required.</description>
+                        <bitRange>[2:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PAGE44_LOCK1</name>
+                <addressOffset>0x003f64</addressOffset>
+                <description>Lock configuration MSBs for page 44 (rows 0xb00 through 0xb3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently.
+
+                    This OTP location is always readable, and is write-protected by its own permissions.</description>
+                <size>24</size>
+                <resetValue>0x000000</resetValue>
+                <fields>
+                    <field>
+                        <name>R2</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[23:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>R1</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[15:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>LOCK_BL</name>
+                        <description>Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers.</description>
+                        <bitRange>[5:4]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                                <description>Bootloader permits user reads and writes to this page</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                                <description>Bootloader permits user reads of this page</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>reserved</name>
+                                <value>2</value>
+                                <description>Do not use. Behaves the same as INACCESSIBLE</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                                <description>Bootloader does not permit user access to this page</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>LOCK_NS</name>
+                        <description>Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers.
+
+                            Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API.</description>
+                        <bitRange>[3:2]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                                <description>Page can be read by Non-secure software, and Secure software may permit Non-secure writes.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                                <description>Page can be read by Non-secure software</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>reserved</name>
+                                <value>2</value>
+                                <description>Do not use. Behaves the same as INACCESSIBLE.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                                <description>Page can not be accessed by Non-secure software.</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>LOCK_S</name>
+                        <description>Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers.</description>
+                        <bitRange>[1:0]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                                <description>Page is fully accessible by Secure software.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                                <description>Page can be read by Secure software, but can not be written.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>reserved</name>
+                                <value>2</value>
+                                <description>Do not use. Behaves the same as INACCESSIBLE.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                                <description>Page can not be accessed by Secure software.</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PAGE45_LOCK0</name>
+                <addressOffset>0x003f68</addressOffset>
+                <description>Lock configuration LSBs for page 45 (rows 0xb40 through 0xb7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently.
+
+                    This OTP location is always readable, and is write-protected by its own permissions.</description>
+                <size>24</size>
+                <resetValue>0x000000</resetValue>
+                <fields>
+                    <field>
+                        <name>R2</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[23:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>R1</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[15:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>NO_KEY_STATE</name>
+                        <description>State when at least one key is registered for this page and no matching key has been entered.</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>KEY_R</name>
+                        <description>Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required.</description>
+                        <bitRange>[5:3]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>KEY_W</name>
+                        <description>Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required.</description>
+                        <bitRange>[2:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PAGE45_LOCK1</name>
+                <addressOffset>0x003f6c</addressOffset>
+                <description>Lock configuration MSBs for page 45 (rows 0xb40 through 0xb7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently.
+
+                    This OTP location is always readable, and is write-protected by its own permissions.</description>
+                <size>24</size>
+                <resetValue>0x000000</resetValue>
+                <fields>
+                    <field>
+                        <name>R2</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[23:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>R1</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[15:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>LOCK_BL</name>
+                        <description>Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers.</description>
+                        <bitRange>[5:4]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                                <description>Bootloader permits user reads and writes to this page</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                                <description>Bootloader permits user reads of this page</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>reserved</name>
+                                <value>2</value>
+                                <description>Do not use. Behaves the same as INACCESSIBLE</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                                <description>Bootloader does not permit user access to this page</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>LOCK_NS</name>
+                        <description>Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers.
+
+                            Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API.</description>
+                        <bitRange>[3:2]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                                <description>Page can be read by Non-secure software, and Secure software may permit Non-secure writes.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                                <description>Page can be read by Non-secure software</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>reserved</name>
+                                <value>2</value>
+                                <description>Do not use. Behaves the same as INACCESSIBLE.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                                <description>Page can not be accessed by Non-secure software.</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>LOCK_S</name>
+                        <description>Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers.</description>
+                        <bitRange>[1:0]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                                <description>Page is fully accessible by Secure software.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                                <description>Page can be read by Secure software, but can not be written.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>reserved</name>
+                                <value>2</value>
+                                <description>Do not use. Behaves the same as INACCESSIBLE.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                                <description>Page can not be accessed by Secure software.</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PAGE46_LOCK0</name>
+                <addressOffset>0x003f70</addressOffset>
+                <description>Lock configuration LSBs for page 46 (rows 0xb80 through 0xbbf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently.
+
+                    This OTP location is always readable, and is write-protected by its own permissions.</description>
+                <size>24</size>
+                <resetValue>0x000000</resetValue>
+                <fields>
+                    <field>
+                        <name>R2</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[23:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>R1</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[15:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>NO_KEY_STATE</name>
+                        <description>State when at least one key is registered for this page and no matching key has been entered.</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>KEY_R</name>
+                        <description>Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required.</description>
+                        <bitRange>[5:3]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>KEY_W</name>
+                        <description>Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required.</description>
+                        <bitRange>[2:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PAGE46_LOCK1</name>
+                <addressOffset>0x003f74</addressOffset>
+                <description>Lock configuration MSBs for page 46 (rows 0xb80 through 0xbbf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently.
+
+                    This OTP location is always readable, and is write-protected by its own permissions.</description>
+                <size>24</size>
+                <resetValue>0x000000</resetValue>
+                <fields>
+                    <field>
+                        <name>R2</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[23:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>R1</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[15:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>LOCK_BL</name>
+                        <description>Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers.</description>
+                        <bitRange>[5:4]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                                <description>Bootloader permits user reads and writes to this page</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                                <description>Bootloader permits user reads of this page</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>reserved</name>
+                                <value>2</value>
+                                <description>Do not use. Behaves the same as INACCESSIBLE</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                                <description>Bootloader does not permit user access to this page</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>LOCK_NS</name>
+                        <description>Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers.
+
+                            Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API.</description>
+                        <bitRange>[3:2]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                                <description>Page can be read by Non-secure software, and Secure software may permit Non-secure writes.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                                <description>Page can be read by Non-secure software</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>reserved</name>
+                                <value>2</value>
+                                <description>Do not use. Behaves the same as INACCESSIBLE.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                                <description>Page can not be accessed by Non-secure software.</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>LOCK_S</name>
+                        <description>Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers.</description>
+                        <bitRange>[1:0]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                                <description>Page is fully accessible by Secure software.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                                <description>Page can be read by Secure software, but can not be written.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>reserved</name>
+                                <value>2</value>
+                                <description>Do not use. Behaves the same as INACCESSIBLE.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                                <description>Page can not be accessed by Secure software.</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PAGE47_LOCK0</name>
+                <addressOffset>0x003f78</addressOffset>
+                <description>Lock configuration LSBs for page 47 (rows 0xbc0 through 0xbff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently.
+
+                    This OTP location is always readable, and is write-protected by its own permissions.</description>
+                <size>24</size>
+                <resetValue>0x000000</resetValue>
+                <fields>
+                    <field>
+                        <name>R2</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[23:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>R1</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[15:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>NO_KEY_STATE</name>
+                        <description>State when at least one key is registered for this page and no matching key has been entered.</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>KEY_R</name>
+                        <description>Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required.</description>
+                        <bitRange>[5:3]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>KEY_W</name>
+                        <description>Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required.</description>
+                        <bitRange>[2:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PAGE47_LOCK1</name>
+                <addressOffset>0x003f7c</addressOffset>
+                <description>Lock configuration MSBs for page 47 (rows 0xbc0 through 0xbff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently.
+
+                    This OTP location is always readable, and is write-protected by its own permissions.</description>
+                <size>24</size>
+                <resetValue>0x000000</resetValue>
+                <fields>
+                    <field>
+                        <name>R2</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[23:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>R1</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[15:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>LOCK_BL</name>
+                        <description>Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers.</description>
+                        <bitRange>[5:4]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                                <description>Bootloader permits user reads and writes to this page</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                                <description>Bootloader permits user reads of this page</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>reserved</name>
+                                <value>2</value>
+                                <description>Do not use. Behaves the same as INACCESSIBLE</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                                <description>Bootloader does not permit user access to this page</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>LOCK_NS</name>
+                        <description>Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers.
+
+                            Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API.</description>
+                        <bitRange>[3:2]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                                <description>Page can be read by Non-secure software, and Secure software may permit Non-secure writes.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                                <description>Page can be read by Non-secure software</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>reserved</name>
+                                <value>2</value>
+                                <description>Do not use. Behaves the same as INACCESSIBLE.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                                <description>Page can not be accessed by Non-secure software.</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>LOCK_S</name>
+                        <description>Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers.</description>
+                        <bitRange>[1:0]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                                <description>Page is fully accessible by Secure software.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                                <description>Page can be read by Secure software, but can not be written.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>reserved</name>
+                                <value>2</value>
+                                <description>Do not use. Behaves the same as INACCESSIBLE.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                                <description>Page can not be accessed by Secure software.</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PAGE48_LOCK0</name>
+                <addressOffset>0x003f80</addressOffset>
+                <description>Lock configuration LSBs for page 48 (rows 0xc00 through 0xc3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently.
+
+                    This OTP location is always readable, and is write-protected by its own permissions.</description>
+                <size>24</size>
+                <resetValue>0x000000</resetValue>
+                <fields>
+                    <field>
+                        <name>R2</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[23:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>R1</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[15:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>NO_KEY_STATE</name>
+                        <description>State when at least one key is registered for this page and no matching key has been entered.</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>KEY_R</name>
+                        <description>Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required.</description>
+                        <bitRange>[5:3]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>KEY_W</name>
+                        <description>Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required.</description>
+                        <bitRange>[2:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PAGE48_LOCK1</name>
+                <addressOffset>0x003f84</addressOffset>
+                <description>Lock configuration MSBs for page 48 (rows 0xc00 through 0xc3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently.
+
+                    This OTP location is always readable, and is write-protected by its own permissions.</description>
+                <size>24</size>
+                <resetValue>0x000000</resetValue>
+                <fields>
+                    <field>
+                        <name>R2</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[23:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>R1</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[15:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>LOCK_BL</name>
+                        <description>Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers.</description>
+                        <bitRange>[5:4]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                                <description>Bootloader permits user reads and writes to this page</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                                <description>Bootloader permits user reads of this page</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>reserved</name>
+                                <value>2</value>
+                                <description>Do not use. Behaves the same as INACCESSIBLE</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                                <description>Bootloader does not permit user access to this page</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>LOCK_NS</name>
+                        <description>Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers.
+
+                            Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API.</description>
+                        <bitRange>[3:2]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                                <description>Page can be read by Non-secure software, and Secure software may permit Non-secure writes.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                                <description>Page can be read by Non-secure software</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>reserved</name>
+                                <value>2</value>
+                                <description>Do not use. Behaves the same as INACCESSIBLE.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                                <description>Page can not be accessed by Non-secure software.</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>LOCK_S</name>
+                        <description>Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers.</description>
+                        <bitRange>[1:0]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                                <description>Page is fully accessible by Secure software.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                                <description>Page can be read by Secure software, but can not be written.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>reserved</name>
+                                <value>2</value>
+                                <description>Do not use. Behaves the same as INACCESSIBLE.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                                <description>Page can not be accessed by Secure software.</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PAGE49_LOCK0</name>
+                <addressOffset>0x003f88</addressOffset>
+                <description>Lock configuration LSBs for page 49 (rows 0xc40 through 0xc7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently.
+
+                    This OTP location is always readable, and is write-protected by its own permissions.</description>
+                <size>24</size>
+                <resetValue>0x000000</resetValue>
+                <fields>
+                    <field>
+                        <name>R2</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[23:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>R1</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[15:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>NO_KEY_STATE</name>
+                        <description>State when at least one key is registered for this page and no matching key has been entered.</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>KEY_R</name>
+                        <description>Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required.</description>
+                        <bitRange>[5:3]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>KEY_W</name>
+                        <description>Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required.</description>
+                        <bitRange>[2:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PAGE49_LOCK1</name>
+                <addressOffset>0x003f8c</addressOffset>
+                <description>Lock configuration MSBs for page 49 (rows 0xc40 through 0xc7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently.
+
+                    This OTP location is always readable, and is write-protected by its own permissions.</description>
+                <size>24</size>
+                <resetValue>0x000000</resetValue>
+                <fields>
+                    <field>
+                        <name>R2</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[23:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>R1</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[15:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>LOCK_BL</name>
+                        <description>Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers.</description>
+                        <bitRange>[5:4]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                                <description>Bootloader permits user reads and writes to this page</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                                <description>Bootloader permits user reads of this page</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>reserved</name>
+                                <value>2</value>
+                                <description>Do not use. Behaves the same as INACCESSIBLE</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                                <description>Bootloader does not permit user access to this page</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>LOCK_NS</name>
+                        <description>Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers.
+
+                            Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API.</description>
+                        <bitRange>[3:2]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                                <description>Page can be read by Non-secure software, and Secure software may permit Non-secure writes.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                                <description>Page can be read by Non-secure software</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>reserved</name>
+                                <value>2</value>
+                                <description>Do not use. Behaves the same as INACCESSIBLE.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                                <description>Page can not be accessed by Non-secure software.</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>LOCK_S</name>
+                        <description>Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers.</description>
+                        <bitRange>[1:0]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                                <description>Page is fully accessible by Secure software.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                                <description>Page can be read by Secure software, but can not be written.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>reserved</name>
+                                <value>2</value>
+                                <description>Do not use. Behaves the same as INACCESSIBLE.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                                <description>Page can not be accessed by Secure software.</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PAGE50_LOCK0</name>
+                <addressOffset>0x003f90</addressOffset>
+                <description>Lock configuration LSBs for page 50 (rows 0xc80 through 0xcbf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently.
+
+                    This OTP location is always readable, and is write-protected by its own permissions.</description>
+                <size>24</size>
+                <resetValue>0x000000</resetValue>
+                <fields>
+                    <field>
+                        <name>R2</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[23:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>R1</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[15:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>NO_KEY_STATE</name>
+                        <description>State when at least one key is registered for this page and no matching key has been entered.</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>KEY_R</name>
+                        <description>Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required.</description>
+                        <bitRange>[5:3]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>KEY_W</name>
+                        <description>Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required.</description>
+                        <bitRange>[2:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PAGE50_LOCK1</name>
+                <addressOffset>0x003f94</addressOffset>
+                <description>Lock configuration MSBs for page 50 (rows 0xc80 through 0xcbf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently.
+
+                    This OTP location is always readable, and is write-protected by its own permissions.</description>
+                <size>24</size>
+                <resetValue>0x000000</resetValue>
+                <fields>
+                    <field>
+                        <name>R2</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[23:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>R1</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[15:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>LOCK_BL</name>
+                        <description>Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers.</description>
+                        <bitRange>[5:4]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                                <description>Bootloader permits user reads and writes to this page</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                                <description>Bootloader permits user reads of this page</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>reserved</name>
+                                <value>2</value>
+                                <description>Do not use. Behaves the same as INACCESSIBLE</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                                <description>Bootloader does not permit user access to this page</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>LOCK_NS</name>
+                        <description>Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers.
+
+                            Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API.</description>
+                        <bitRange>[3:2]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                                <description>Page can be read by Non-secure software, and Secure software may permit Non-secure writes.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                                <description>Page can be read by Non-secure software</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>reserved</name>
+                                <value>2</value>
+                                <description>Do not use. Behaves the same as INACCESSIBLE.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                                <description>Page can not be accessed by Non-secure software.</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>LOCK_S</name>
+                        <description>Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers.</description>
+                        <bitRange>[1:0]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                                <description>Page is fully accessible by Secure software.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                                <description>Page can be read by Secure software, but can not be written.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>reserved</name>
+                                <value>2</value>
+                                <description>Do not use. Behaves the same as INACCESSIBLE.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                                <description>Page can not be accessed by Secure software.</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PAGE51_LOCK0</name>
+                <addressOffset>0x003f98</addressOffset>
+                <description>Lock configuration LSBs for page 51 (rows 0xcc0 through 0xcff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently.
+
+                    This OTP location is always readable, and is write-protected by its own permissions.</description>
+                <size>24</size>
+                <resetValue>0x000000</resetValue>
+                <fields>
+                    <field>
+                        <name>R2</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[23:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>R1</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[15:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>NO_KEY_STATE</name>
+                        <description>State when at least one key is registered for this page and no matching key has been entered.</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>KEY_R</name>
+                        <description>Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required.</description>
+                        <bitRange>[5:3]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>KEY_W</name>
+                        <description>Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required.</description>
+                        <bitRange>[2:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PAGE51_LOCK1</name>
+                <addressOffset>0x003f9c</addressOffset>
+                <description>Lock configuration MSBs for page 51 (rows 0xcc0 through 0xcff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently.
+
+                    This OTP location is always readable, and is write-protected by its own permissions.</description>
+                <size>24</size>
+                <resetValue>0x000000</resetValue>
+                <fields>
+                    <field>
+                        <name>R2</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[23:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>R1</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[15:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>LOCK_BL</name>
+                        <description>Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers.</description>
+                        <bitRange>[5:4]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                                <description>Bootloader permits user reads and writes to this page</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                                <description>Bootloader permits user reads of this page</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>reserved</name>
+                                <value>2</value>
+                                <description>Do not use. Behaves the same as INACCESSIBLE</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                                <description>Bootloader does not permit user access to this page</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>LOCK_NS</name>
+                        <description>Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers.
+
+                            Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API.</description>
+                        <bitRange>[3:2]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                                <description>Page can be read by Non-secure software, and Secure software may permit Non-secure writes.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                                <description>Page can be read by Non-secure software</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>reserved</name>
+                                <value>2</value>
+                                <description>Do not use. Behaves the same as INACCESSIBLE.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                                <description>Page can not be accessed by Non-secure software.</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>LOCK_S</name>
+                        <description>Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers.</description>
+                        <bitRange>[1:0]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                                <description>Page is fully accessible by Secure software.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                                <description>Page can be read by Secure software, but can not be written.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>reserved</name>
+                                <value>2</value>
+                                <description>Do not use. Behaves the same as INACCESSIBLE.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                                <description>Page can not be accessed by Secure software.</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PAGE52_LOCK0</name>
+                <addressOffset>0x003fa0</addressOffset>
+                <description>Lock configuration LSBs for page 52 (rows 0xd00 through 0xd3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently.
+
+                    This OTP location is always readable, and is write-protected by its own permissions.</description>
+                <size>24</size>
+                <resetValue>0x000000</resetValue>
+                <fields>
+                    <field>
+                        <name>R2</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[23:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>R1</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[15:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>NO_KEY_STATE</name>
+                        <description>State when at least one key is registered for this page and no matching key has been entered.</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>KEY_R</name>
+                        <description>Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required.</description>
+                        <bitRange>[5:3]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>KEY_W</name>
+                        <description>Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required.</description>
+                        <bitRange>[2:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PAGE52_LOCK1</name>
+                <addressOffset>0x003fa4</addressOffset>
+                <description>Lock configuration MSBs for page 52 (rows 0xd00 through 0xd3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently.
+
+                    This OTP location is always readable, and is write-protected by its own permissions.</description>
+                <size>24</size>
+                <resetValue>0x000000</resetValue>
+                <fields>
+                    <field>
+                        <name>R2</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[23:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>R1</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[15:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>LOCK_BL</name>
+                        <description>Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers.</description>
+                        <bitRange>[5:4]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                                <description>Bootloader permits user reads and writes to this page</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                                <description>Bootloader permits user reads of this page</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>reserved</name>
+                                <value>2</value>
+                                <description>Do not use. Behaves the same as INACCESSIBLE</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                                <description>Bootloader does not permit user access to this page</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>LOCK_NS</name>
+                        <description>Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers.
+
+                            Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API.</description>
+                        <bitRange>[3:2]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                                <description>Page can be read by Non-secure software, and Secure software may permit Non-secure writes.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                                <description>Page can be read by Non-secure software</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>reserved</name>
+                                <value>2</value>
+                                <description>Do not use. Behaves the same as INACCESSIBLE.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                                <description>Page can not be accessed by Non-secure software.</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>LOCK_S</name>
+                        <description>Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers.</description>
+                        <bitRange>[1:0]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                                <description>Page is fully accessible by Secure software.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                                <description>Page can be read by Secure software, but can not be written.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>reserved</name>
+                                <value>2</value>
+                                <description>Do not use. Behaves the same as INACCESSIBLE.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                                <description>Page can not be accessed by Secure software.</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PAGE53_LOCK0</name>
+                <addressOffset>0x003fa8</addressOffset>
+                <description>Lock configuration LSBs for page 53 (rows 0xd40 through 0xd7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently.
+
+                    This OTP location is always readable, and is write-protected by its own permissions.</description>
+                <size>24</size>
+                <resetValue>0x000000</resetValue>
+                <fields>
+                    <field>
+                        <name>R2</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[23:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>R1</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[15:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>NO_KEY_STATE</name>
+                        <description>State when at least one key is registered for this page and no matching key has been entered.</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>KEY_R</name>
+                        <description>Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required.</description>
+                        <bitRange>[5:3]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>KEY_W</name>
+                        <description>Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required.</description>
+                        <bitRange>[2:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PAGE53_LOCK1</name>
+                <addressOffset>0x003fac</addressOffset>
+                <description>Lock configuration MSBs for page 53 (rows 0xd40 through 0xd7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently.
+
+                    This OTP location is always readable, and is write-protected by its own permissions.</description>
+                <size>24</size>
+                <resetValue>0x000000</resetValue>
+                <fields>
+                    <field>
+                        <name>R2</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[23:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>R1</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[15:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>LOCK_BL</name>
+                        <description>Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers.</description>
+                        <bitRange>[5:4]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                                <description>Bootloader permits user reads and writes to this page</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                                <description>Bootloader permits user reads of this page</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>reserved</name>
+                                <value>2</value>
+                                <description>Do not use. Behaves the same as INACCESSIBLE</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                                <description>Bootloader does not permit user access to this page</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>LOCK_NS</name>
+                        <description>Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers.
+
+                            Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API.</description>
+                        <bitRange>[3:2]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                                <description>Page can be read by Non-secure software, and Secure software may permit Non-secure writes.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                                <description>Page can be read by Non-secure software</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>reserved</name>
+                                <value>2</value>
+                                <description>Do not use. Behaves the same as INACCESSIBLE.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                                <description>Page can not be accessed by Non-secure software.</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>LOCK_S</name>
+                        <description>Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers.</description>
+                        <bitRange>[1:0]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                                <description>Page is fully accessible by Secure software.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                                <description>Page can be read by Secure software, but can not be written.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>reserved</name>
+                                <value>2</value>
+                                <description>Do not use. Behaves the same as INACCESSIBLE.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                                <description>Page can not be accessed by Secure software.</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PAGE54_LOCK0</name>
+                <addressOffset>0x003fb0</addressOffset>
+                <description>Lock configuration LSBs for page 54 (rows 0xd80 through 0xdbf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently.
+
+                    This OTP location is always readable, and is write-protected by its own permissions.</description>
+                <size>24</size>
+                <resetValue>0x000000</resetValue>
+                <fields>
+                    <field>
+                        <name>R2</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[23:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>R1</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[15:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>NO_KEY_STATE</name>
+                        <description>State when at least one key is registered for this page and no matching key has been entered.</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>KEY_R</name>
+                        <description>Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required.</description>
+                        <bitRange>[5:3]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>KEY_W</name>
+                        <description>Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required.</description>
+                        <bitRange>[2:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PAGE54_LOCK1</name>
+                <addressOffset>0x003fb4</addressOffset>
+                <description>Lock configuration MSBs for page 54 (rows 0xd80 through 0xdbf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently.
+
+                    This OTP location is always readable, and is write-protected by its own permissions.</description>
+                <size>24</size>
+                <resetValue>0x000000</resetValue>
+                <fields>
+                    <field>
+                        <name>R2</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[23:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>R1</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[15:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>LOCK_BL</name>
+                        <description>Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers.</description>
+                        <bitRange>[5:4]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                                <description>Bootloader permits user reads and writes to this page</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                                <description>Bootloader permits user reads of this page</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>reserved</name>
+                                <value>2</value>
+                                <description>Do not use. Behaves the same as INACCESSIBLE</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                                <description>Bootloader does not permit user access to this page</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>LOCK_NS</name>
+                        <description>Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers.
+
+                            Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API.</description>
+                        <bitRange>[3:2]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                                <description>Page can be read by Non-secure software, and Secure software may permit Non-secure writes.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                                <description>Page can be read by Non-secure software</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>reserved</name>
+                                <value>2</value>
+                                <description>Do not use. Behaves the same as INACCESSIBLE.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                                <description>Page can not be accessed by Non-secure software.</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>LOCK_S</name>
+                        <description>Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers.</description>
+                        <bitRange>[1:0]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                                <description>Page is fully accessible by Secure software.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                                <description>Page can be read by Secure software, but can not be written.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>reserved</name>
+                                <value>2</value>
+                                <description>Do not use. Behaves the same as INACCESSIBLE.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                                <description>Page can not be accessed by Secure software.</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PAGE55_LOCK0</name>
+                <addressOffset>0x003fb8</addressOffset>
+                <description>Lock configuration LSBs for page 55 (rows 0xdc0 through 0xdff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently.
+
+                    This OTP location is always readable, and is write-protected by its own permissions.</description>
+                <size>24</size>
+                <resetValue>0x000000</resetValue>
+                <fields>
+                    <field>
+                        <name>R2</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[23:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>R1</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[15:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>NO_KEY_STATE</name>
+                        <description>State when at least one key is registered for this page and no matching key has been entered.</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>KEY_R</name>
+                        <description>Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required.</description>
+                        <bitRange>[5:3]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>KEY_W</name>
+                        <description>Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required.</description>
+                        <bitRange>[2:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PAGE55_LOCK1</name>
+                <addressOffset>0x003fbc</addressOffset>
+                <description>Lock configuration MSBs for page 55 (rows 0xdc0 through 0xdff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently.
+
+                    This OTP location is always readable, and is write-protected by its own permissions.</description>
+                <size>24</size>
+                <resetValue>0x000000</resetValue>
+                <fields>
+                    <field>
+                        <name>R2</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[23:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>R1</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[15:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>LOCK_BL</name>
+                        <description>Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers.</description>
+                        <bitRange>[5:4]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                                <description>Bootloader permits user reads and writes to this page</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                                <description>Bootloader permits user reads of this page</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>reserved</name>
+                                <value>2</value>
+                                <description>Do not use. Behaves the same as INACCESSIBLE</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                                <description>Bootloader does not permit user access to this page</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>LOCK_NS</name>
+                        <description>Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers.
+
+                            Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API.</description>
+                        <bitRange>[3:2]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                                <description>Page can be read by Non-secure software, and Secure software may permit Non-secure writes.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                                <description>Page can be read by Non-secure software</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>reserved</name>
+                                <value>2</value>
+                                <description>Do not use. Behaves the same as INACCESSIBLE.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                                <description>Page can not be accessed by Non-secure software.</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>LOCK_S</name>
+                        <description>Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers.</description>
+                        <bitRange>[1:0]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                                <description>Page is fully accessible by Secure software.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                                <description>Page can be read by Secure software, but can not be written.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>reserved</name>
+                                <value>2</value>
+                                <description>Do not use. Behaves the same as INACCESSIBLE.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                                <description>Page can not be accessed by Secure software.</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PAGE56_LOCK0</name>
+                <addressOffset>0x003fc0</addressOffset>
+                <description>Lock configuration LSBs for page 56 (rows 0xe00 through 0xe3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently.
+
+                    This OTP location is always readable, and is write-protected by its own permissions.</description>
+                <size>24</size>
+                <resetValue>0x000000</resetValue>
+                <fields>
+                    <field>
+                        <name>R2</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[23:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>R1</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[15:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>NO_KEY_STATE</name>
+                        <description>State when at least one key is registered for this page and no matching key has been entered.</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>KEY_R</name>
+                        <description>Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required.</description>
+                        <bitRange>[5:3]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>KEY_W</name>
+                        <description>Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required.</description>
+                        <bitRange>[2:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PAGE56_LOCK1</name>
+                <addressOffset>0x003fc4</addressOffset>
+                <description>Lock configuration MSBs for page 56 (rows 0xe00 through 0xe3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently.
+
+                    This OTP location is always readable, and is write-protected by its own permissions.</description>
+                <size>24</size>
+                <resetValue>0x000000</resetValue>
+                <fields>
+                    <field>
+                        <name>R2</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[23:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>R1</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[15:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>LOCK_BL</name>
+                        <description>Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers.</description>
+                        <bitRange>[5:4]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                                <description>Bootloader permits user reads and writes to this page</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                                <description>Bootloader permits user reads of this page</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>reserved</name>
+                                <value>2</value>
+                                <description>Do not use. Behaves the same as INACCESSIBLE</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                                <description>Bootloader does not permit user access to this page</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>LOCK_NS</name>
+                        <description>Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers.
+
+                            Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API.</description>
+                        <bitRange>[3:2]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                                <description>Page can be read by Non-secure software, and Secure software may permit Non-secure writes.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                                <description>Page can be read by Non-secure software</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>reserved</name>
+                                <value>2</value>
+                                <description>Do not use. Behaves the same as INACCESSIBLE.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                                <description>Page can not be accessed by Non-secure software.</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>LOCK_S</name>
+                        <description>Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers.</description>
+                        <bitRange>[1:0]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                                <description>Page is fully accessible by Secure software.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                                <description>Page can be read by Secure software, but can not be written.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>reserved</name>
+                                <value>2</value>
+                                <description>Do not use. Behaves the same as INACCESSIBLE.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                                <description>Page can not be accessed by Secure software.</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PAGE57_LOCK0</name>
+                <addressOffset>0x003fc8</addressOffset>
+                <description>Lock configuration LSBs for page 57 (rows 0xe40 through 0xe7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently.
+
+                    This OTP location is always readable, and is write-protected by its own permissions.</description>
+                <size>24</size>
+                <resetValue>0x000000</resetValue>
+                <fields>
+                    <field>
+                        <name>R2</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[23:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>R1</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[15:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>NO_KEY_STATE</name>
+                        <description>State when at least one key is registered for this page and no matching key has been entered.</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>KEY_R</name>
+                        <description>Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required.</description>
+                        <bitRange>[5:3]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>KEY_W</name>
+                        <description>Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required.</description>
+                        <bitRange>[2:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PAGE57_LOCK1</name>
+                <addressOffset>0x003fcc</addressOffset>
+                <description>Lock configuration MSBs for page 57 (rows 0xe40 through 0xe7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently.
+
+                    This OTP location is always readable, and is write-protected by its own permissions.</description>
+                <size>24</size>
+                <resetValue>0x000000</resetValue>
+                <fields>
+                    <field>
+                        <name>R2</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[23:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>R1</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[15:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>LOCK_BL</name>
+                        <description>Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers.</description>
+                        <bitRange>[5:4]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                                <description>Bootloader permits user reads and writes to this page</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                                <description>Bootloader permits user reads of this page</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>reserved</name>
+                                <value>2</value>
+                                <description>Do not use. Behaves the same as INACCESSIBLE</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                                <description>Bootloader does not permit user access to this page</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>LOCK_NS</name>
+                        <description>Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers.
+
+                            Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API.</description>
+                        <bitRange>[3:2]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                                <description>Page can be read by Non-secure software, and Secure software may permit Non-secure writes.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                                <description>Page can be read by Non-secure software</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>reserved</name>
+                                <value>2</value>
+                                <description>Do not use. Behaves the same as INACCESSIBLE.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                                <description>Page can not be accessed by Non-secure software.</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>LOCK_S</name>
+                        <description>Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers.</description>
+                        <bitRange>[1:0]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                                <description>Page is fully accessible by Secure software.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                                <description>Page can be read by Secure software, but can not be written.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>reserved</name>
+                                <value>2</value>
+                                <description>Do not use. Behaves the same as INACCESSIBLE.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                                <description>Page can not be accessed by Secure software.</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PAGE58_LOCK0</name>
+                <addressOffset>0x003fd0</addressOffset>
+                <description>Lock configuration LSBs for page 58 (rows 0xe80 through 0xebf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently.
+
+                    This OTP location is always readable, and is write-protected by its own permissions.</description>
+                <size>24</size>
+                <resetValue>0x000000</resetValue>
+                <fields>
+                    <field>
+                        <name>R2</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[23:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>R1</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[15:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>NO_KEY_STATE</name>
+                        <description>State when at least one key is registered for this page and no matching key has been entered.</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>KEY_R</name>
+                        <description>Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required.</description>
+                        <bitRange>[5:3]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>KEY_W</name>
+                        <description>Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required.</description>
+                        <bitRange>[2:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PAGE58_LOCK1</name>
+                <addressOffset>0x003fd4</addressOffset>
+                <description>Lock configuration MSBs for page 58 (rows 0xe80 through 0xebf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently.
+
+                    This OTP location is always readable, and is write-protected by its own permissions.</description>
+                <size>24</size>
+                <resetValue>0x000000</resetValue>
+                <fields>
+                    <field>
+                        <name>R2</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[23:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>R1</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[15:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>LOCK_BL</name>
+                        <description>Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers.</description>
+                        <bitRange>[5:4]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                                <description>Bootloader permits user reads and writes to this page</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                                <description>Bootloader permits user reads of this page</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>reserved</name>
+                                <value>2</value>
+                                <description>Do not use. Behaves the same as INACCESSIBLE</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                                <description>Bootloader does not permit user access to this page</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>LOCK_NS</name>
+                        <description>Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers.
+
+                            Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API.</description>
+                        <bitRange>[3:2]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                                <description>Page can be read by Non-secure software, and Secure software may permit Non-secure writes.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                                <description>Page can be read by Non-secure software</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>reserved</name>
+                                <value>2</value>
+                                <description>Do not use. Behaves the same as INACCESSIBLE.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                                <description>Page can not be accessed by Non-secure software.</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>LOCK_S</name>
+                        <description>Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers.</description>
+                        <bitRange>[1:0]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                                <description>Page is fully accessible by Secure software.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                                <description>Page can be read by Secure software, but can not be written.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>reserved</name>
+                                <value>2</value>
+                                <description>Do not use. Behaves the same as INACCESSIBLE.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                                <description>Page can not be accessed by Secure software.</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PAGE59_LOCK0</name>
+                <addressOffset>0x003fd8</addressOffset>
+                <description>Lock configuration LSBs for page 59 (rows 0xec0 through 0xeff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently.
+
+                    This OTP location is always readable, and is write-protected by its own permissions.</description>
+                <size>24</size>
+                <resetValue>0x000000</resetValue>
+                <fields>
+                    <field>
+                        <name>R2</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[23:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>R1</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[15:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>NO_KEY_STATE</name>
+                        <description>State when at least one key is registered for this page and no matching key has been entered.</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>KEY_R</name>
+                        <description>Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required.</description>
+                        <bitRange>[5:3]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>KEY_W</name>
+                        <description>Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required.</description>
+                        <bitRange>[2:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PAGE59_LOCK1</name>
+                <addressOffset>0x003fdc</addressOffset>
+                <description>Lock configuration MSBs for page 59 (rows 0xec0 through 0xeff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently.
+
+                    This OTP location is always readable, and is write-protected by its own permissions.</description>
+                <size>24</size>
+                <resetValue>0x000000</resetValue>
+                <fields>
+                    <field>
+                        <name>R2</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[23:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>R1</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[15:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>LOCK_BL</name>
+                        <description>Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers.</description>
+                        <bitRange>[5:4]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                                <description>Bootloader permits user reads and writes to this page</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                                <description>Bootloader permits user reads of this page</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>reserved</name>
+                                <value>2</value>
+                                <description>Do not use. Behaves the same as INACCESSIBLE</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                                <description>Bootloader does not permit user access to this page</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>LOCK_NS</name>
+                        <description>Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers.
+
+                            Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API.</description>
+                        <bitRange>[3:2]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                                <description>Page can be read by Non-secure software, and Secure software may permit Non-secure writes.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                                <description>Page can be read by Non-secure software</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>reserved</name>
+                                <value>2</value>
+                                <description>Do not use. Behaves the same as INACCESSIBLE.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                                <description>Page can not be accessed by Non-secure software.</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>LOCK_S</name>
+                        <description>Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers.</description>
+                        <bitRange>[1:0]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                                <description>Page is fully accessible by Secure software.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                                <description>Page can be read by Secure software, but can not be written.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>reserved</name>
+                                <value>2</value>
+                                <description>Do not use. Behaves the same as INACCESSIBLE.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                                <description>Page can not be accessed by Secure software.</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PAGE60_LOCK0</name>
+                <addressOffset>0x003fe0</addressOffset>
+                <description>Lock configuration LSBs for page 60 (rows 0xf00 through 0xf3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently.
+
+                    This OTP location is always readable, and is write-protected by its own permissions.</description>
+                <size>24</size>
+                <resetValue>0x000000</resetValue>
+                <fields>
+                    <field>
+                        <name>R2</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[23:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>R1</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[15:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>NO_KEY_STATE</name>
+                        <description>State when at least one key is registered for this page and no matching key has been entered.</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>KEY_R</name>
+                        <description>Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required.</description>
+                        <bitRange>[5:3]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>KEY_W</name>
+                        <description>Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required.</description>
+                        <bitRange>[2:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PAGE60_LOCK1</name>
+                <addressOffset>0x003fe4</addressOffset>
+                <description>Lock configuration MSBs for page 60 (rows 0xf00 through 0xf3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently.
+
+                    This OTP location is always readable, and is write-protected by its own permissions.</description>
+                <size>24</size>
+                <resetValue>0x000000</resetValue>
+                <fields>
+                    <field>
+                        <name>R2</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[23:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>R1</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[15:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>LOCK_BL</name>
+                        <description>Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers.</description>
+                        <bitRange>[5:4]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                                <description>Bootloader permits user reads and writes to this page</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                                <description>Bootloader permits user reads of this page</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>reserved</name>
+                                <value>2</value>
+                                <description>Do not use. Behaves the same as INACCESSIBLE</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                                <description>Bootloader does not permit user access to this page</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>LOCK_NS</name>
+                        <description>Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers.
+
+                            Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API.</description>
+                        <bitRange>[3:2]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                                <description>Page can be read by Non-secure software, and Secure software may permit Non-secure writes.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                                <description>Page can be read by Non-secure software</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>reserved</name>
+                                <value>2</value>
+                                <description>Do not use. Behaves the same as INACCESSIBLE.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                                <description>Page can not be accessed by Non-secure software.</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>LOCK_S</name>
+                        <description>Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers.</description>
+                        <bitRange>[1:0]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                                <description>Page is fully accessible by Secure software.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                                <description>Page can be read by Secure software, but can not be written.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>reserved</name>
+                                <value>2</value>
+                                <description>Do not use. Behaves the same as INACCESSIBLE.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                                <description>Page can not be accessed by Secure software.</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PAGE61_LOCK0</name>
+                <addressOffset>0x003fe8</addressOffset>
+                <description>Lock configuration LSBs for page 61 (rows 0xf40 through 0xf7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently.
+
+                    This OTP location is always readable, and is write-protected by its own permissions.</description>
+                <size>24</size>
+                <resetValue>0x000000</resetValue>
+                <fields>
+                    <field>
+                        <name>R2</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[23:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>R1</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[15:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>NO_KEY_STATE</name>
+                        <description>State when at least one key is registered for this page and no matching key has been entered.</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>KEY_R</name>
+                        <description>Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required.</description>
+                        <bitRange>[5:3]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>KEY_W</name>
+                        <description>Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required.</description>
+                        <bitRange>[2:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PAGE61_LOCK1</name>
+                <addressOffset>0x003fec</addressOffset>
+                <description>Lock configuration MSBs for page 61 (rows 0xf40 through 0xf7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently.
+
+                    This OTP location is always readable, and is write-protected by its own permissions.</description>
+                <size>24</size>
+                <resetValue>0x000000</resetValue>
+                <fields>
+                    <field>
+                        <name>R2</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[23:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>R1</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[15:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>LOCK_BL</name>
+                        <description>Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers.</description>
+                        <bitRange>[5:4]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                                <description>Bootloader permits user reads and writes to this page</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                                <description>Bootloader permits user reads of this page</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>reserved</name>
+                                <value>2</value>
+                                <description>Do not use. Behaves the same as INACCESSIBLE</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                                <description>Bootloader does not permit user access to this page</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>LOCK_NS</name>
+                        <description>Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers.
+
+                            Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API.</description>
+                        <bitRange>[3:2]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                                <description>Page can be read by Non-secure software, and Secure software may permit Non-secure writes.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                                <description>Page can be read by Non-secure software</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>reserved</name>
+                                <value>2</value>
+                                <description>Do not use. Behaves the same as INACCESSIBLE.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                                <description>Page can not be accessed by Non-secure software.</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>LOCK_S</name>
+                        <description>Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers.</description>
+                        <bitRange>[1:0]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                                <description>Page is fully accessible by Secure software.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                                <description>Page can be read by Secure software, but can not be written.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>reserved</name>
+                                <value>2</value>
+                                <description>Do not use. Behaves the same as INACCESSIBLE.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                                <description>Page can not be accessed by Secure software.</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PAGE62_LOCK0</name>
+                <addressOffset>0x003ff0</addressOffset>
+                <description>Lock configuration LSBs for page 62 (rows 0xf80 through 0xfbf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently.
+
+                    This OTP location is always readable, and is write-protected by its own permissions.</description>
+                <size>24</size>
+                <resetValue>0x000000</resetValue>
+                <fields>
+                    <field>
+                        <name>R2</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[23:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>R1</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[15:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>NO_KEY_STATE</name>
+                        <description>State when at least one key is registered for this page and no matching key has been entered.</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>KEY_R</name>
+                        <description>Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required.</description>
+                        <bitRange>[5:3]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>KEY_W</name>
+                        <description>Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required.</description>
+                        <bitRange>[2:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PAGE62_LOCK1</name>
+                <addressOffset>0x003ff4</addressOffset>
+                <description>Lock configuration MSBs for page 62 (rows 0xf80 through 0xfbf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently.
+
+                    This OTP location is always readable, and is write-protected by its own permissions.</description>
+                <size>24</size>
+                <resetValue>0x000000</resetValue>
+                <fields>
+                    <field>
+                        <name>R2</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[23:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>R1</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[15:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>LOCK_BL</name>
+                        <description>Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers.</description>
+                        <bitRange>[5:4]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                                <description>Bootloader permits user reads and writes to this page</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                                <description>Bootloader permits user reads of this page</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>reserved</name>
+                                <value>2</value>
+                                <description>Do not use. Behaves the same as INACCESSIBLE</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                                <description>Bootloader does not permit user access to this page</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>LOCK_NS</name>
+                        <description>Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers.
+
+                            Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API.</description>
+                        <bitRange>[3:2]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                                <description>Page can be read by Non-secure software, and Secure software may permit Non-secure writes.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                                <description>Page can be read by Non-secure software</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>reserved</name>
+                                <value>2</value>
+                                <description>Do not use. Behaves the same as INACCESSIBLE.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                                <description>Page can not be accessed by Non-secure software.</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>LOCK_S</name>
+                        <description>Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers.</description>
+                        <bitRange>[1:0]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                                <description>Page is fully accessible by Secure software.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                                <description>Page can be read by Secure software, but can not be written.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>reserved</name>
+                                <value>2</value>
+                                <description>Do not use. Behaves the same as INACCESSIBLE.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                                <description>Page can not be accessed by Secure software.</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PAGE63_LOCK0</name>
+                <addressOffset>0x003ff8</addressOffset>
+                <description>Lock configuration LSBs for page 63 (rows 0xfc0 through 0xfff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently.
+
+                    This OTP location is always readable, and is write-protected by its own permissions.</description>
+                <size>24</size>
+                <resetValue>0x000000</resetValue>
+                <fields>
+                    <field>
+                        <name>R2</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[23:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>R1</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[15:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>RMA</name>
+                        <description>Decommission for RMA of a suspected faulty device. This re-enables the factory test JTAG interface, and makes pages 3 through 61 of the OTP permanently inaccessible.</description>
+                        <bitRange>[7:7]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>NO_KEY_STATE</name>
+                        <description>State when at least one key is registered for this page and no matching key has been entered.</description>
+                        <bitRange>[6:6]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>KEY_R</name>
+                        <description>Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required.</description>
+                        <bitRange>[5:3]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>KEY_W</name>
+                        <description>Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required.</description>
+                        <bitRange>[2:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>PAGE63_LOCK1</name>
+                <addressOffset>0x003ffc</addressOffset>
+                <description>Lock configuration MSBs for page 63 (rows 0xfc0 through 0xfff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently.
+
+                    This OTP location is always readable, and is write-protected by its own permissions.</description>
+                <size>24</size>
+                <resetValue>0x000000</resetValue>
+                <fields>
+                    <field>
+                        <name>R2</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[23:16]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>R1</name>
+                        <description>Redundant copy of bits 7:0</description>
+                        <bitRange>[15:8]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>LOCK_BL</name>
+                        <description>Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers.</description>
+                        <bitRange>[5:4]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                                <description>Bootloader permits user reads and writes to this page</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                                <description>Bootloader permits user reads of this page</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>reserved</name>
+                                <value>2</value>
+                                <description>Do not use. Behaves the same as INACCESSIBLE</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                                <description>Bootloader does not permit user access to this page</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>LOCK_NS</name>
+                        <description>Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers.
+
+                            Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API.</description>
+                        <bitRange>[3:2]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                                <description>Page can be read by Non-secure software, and Secure software may permit Non-secure writes.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                                <description>Page can be read by Non-secure software</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>reserved</name>
+                                <value>2</value>
+                                <description>Do not use. Behaves the same as INACCESSIBLE.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                                <description>Page can not be accessed by Non-secure software.</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>LOCK_S</name>
+                        <description>Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers.</description>
+                        <bitRange>[1:0]</bitRange>
+                        <access>read-only</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>read_write</name>
+                                <value>0</value>
+                                <description>Page is fully accessible by Secure software.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>read_only</name>
+                                <value>1</value>
+                                <description>Page can be read by Secure software, but can not be written.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>reserved</name>
+                                <value>2</value>
+                                <description>Do not use. Behaves the same as INACCESSIBLE.</description>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>inaccessible</name>
+                                <value>3</value>
+                                <description>Page can not be accessed by Secure software.</description>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                </fields>
+            </register>
+        </registers>
+    </peripheral>
+    <peripheral>
+        <name>TBMAN</name>
+        <description>For managing simulation testbenches</description>
+        <baseAddress>0x40160000</baseAddress>
+        <addressBlock>
+            <offset>0</offset>
+            <size>4</size>
+            <usage>registers</usage>
+        </addressBlock>
+        <registers>
+            <register>
+                <name>PLATFORM</name>
+                <addressOffset>0x00000000</addressOffset>
+                <description>Indicates the type of platform in use</description>
+                <resetValue>0x00000001</resetValue>
+                <fields>
+                    <field>
+                        <name>HDLSIM</name>
+                        <description>Indicates the platform is a simulation</description>
+                        <bitRange>[2:2]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>FPGA</name>
+                        <description>Indicates the platform is an FPGA</description>
+                        <bitRange>[1:1]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                    <field>
+                        <name>ASIC</name>
+                        <description>Indicates the platform is an ASIC</description>
+                        <bitRange>[0:0]</bitRange>
+                        <access>read-only</access>
+                    </field>
+                </fields>
+            </register>
+        </registers>
+    </peripheral>
+    <peripheral>
+        <name>USB_DPRAM</name>
+        <description>DPRAM layout for USB device.</description>
+        <baseAddress>0x50100000</baseAddress>
+        <addressBlock>
+            <offset>0</offset>
+            <size>256</size>
+            <usage>registers</usage>
+        </addressBlock>
+        <registers>
+            <register>
+                <name>SETUP_PACKET_LOW</name>
+                <addressOffset>0x00000000</addressOffset>
+                <description>Bytes 0-3 of the SETUP packet from the host.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>WVALUE</name>
+                        <bitRange>[31:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>BREQUEST</name>
+                        <bitRange>[15:8]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>BMREQUESTTYPE</name>
+                        <bitRange>[7:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>SETUP_PACKET_HIGH</name>
+                <addressOffset>0x00000004</addressOffset>
+                <description>Bytes 4-7 of the setup packet from the host.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>WLENGTH</name>
+                        <bitRange>[31:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>WINDEX</name>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>EP1_IN_CONTROL</name>
+                <addressOffset>0x00000008</addressOffset>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>ENABLE</name>
+                        <description>Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.</description>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DOUBLE_BUFFERED</name>
+                        <description>This endpoint is double buffered.</description>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_PER_BUFF</name>
+                        <description>Trigger an interrupt each time a buffer is done.</description>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_PER_DOUBLE_BUFF</name>
+                        <description>Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.</description>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ENDPOINT_TYPE</name>
+                        <bitRange>[27:26]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>Control</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Isochronous</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Bulk</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Interrupt</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_ON_STALL</name>
+                        <description>Trigger an interrupt if a STALL is sent. Intended for debug only.</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_ON_NAK</name>
+                        <description>Trigger an interrupt if a NAK is sent. Intended for debug only.</description>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>BUFFER_ADDRESS</name>
+                        <description>64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.</description>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>EP1_OUT_CONTROL</name>
+                <addressOffset>0x0000000c</addressOffset>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>ENABLE</name>
+                        <description>Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.</description>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DOUBLE_BUFFERED</name>
+                        <description>This endpoint is double buffered.</description>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_PER_BUFF</name>
+                        <description>Trigger an interrupt each time a buffer is done.</description>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_PER_DOUBLE_BUFF</name>
+                        <description>Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.</description>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ENDPOINT_TYPE</name>
+                        <bitRange>[27:26]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>Control</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Isochronous</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Bulk</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Interrupt</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_ON_STALL</name>
+                        <description>Trigger an interrupt if a STALL is sent. Intended for debug only.</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_ON_NAK</name>
+                        <description>Trigger an interrupt if a NAK is sent. Intended for debug only.</description>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>BUFFER_ADDRESS</name>
+                        <description>64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.</description>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>EP2_IN_CONTROL</name>
+                <addressOffset>0x00000010</addressOffset>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>ENABLE</name>
+                        <description>Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.</description>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DOUBLE_BUFFERED</name>
+                        <description>This endpoint is double buffered.</description>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_PER_BUFF</name>
+                        <description>Trigger an interrupt each time a buffer is done.</description>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_PER_DOUBLE_BUFF</name>
+                        <description>Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.</description>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ENDPOINT_TYPE</name>
+                        <bitRange>[27:26]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>Control</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Isochronous</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Bulk</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Interrupt</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_ON_STALL</name>
+                        <description>Trigger an interrupt if a STALL is sent. Intended for debug only.</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_ON_NAK</name>
+                        <description>Trigger an interrupt if a NAK is sent. Intended for debug only.</description>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>BUFFER_ADDRESS</name>
+                        <description>64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.</description>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>EP2_OUT_CONTROL</name>
+                <addressOffset>0x00000014</addressOffset>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>ENABLE</name>
+                        <description>Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.</description>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DOUBLE_BUFFERED</name>
+                        <description>This endpoint is double buffered.</description>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_PER_BUFF</name>
+                        <description>Trigger an interrupt each time a buffer is done.</description>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_PER_DOUBLE_BUFF</name>
+                        <description>Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.</description>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ENDPOINT_TYPE</name>
+                        <bitRange>[27:26]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>Control</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Isochronous</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Bulk</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Interrupt</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_ON_STALL</name>
+                        <description>Trigger an interrupt if a STALL is sent. Intended for debug only.</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_ON_NAK</name>
+                        <description>Trigger an interrupt if a NAK is sent. Intended for debug only.</description>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>BUFFER_ADDRESS</name>
+                        <description>64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.</description>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>EP3_IN_CONTROL</name>
+                <addressOffset>0x00000018</addressOffset>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>ENABLE</name>
+                        <description>Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.</description>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DOUBLE_BUFFERED</name>
+                        <description>This endpoint is double buffered.</description>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_PER_BUFF</name>
+                        <description>Trigger an interrupt each time a buffer is done.</description>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_PER_DOUBLE_BUFF</name>
+                        <description>Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.</description>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ENDPOINT_TYPE</name>
+                        <bitRange>[27:26]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>Control</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Isochronous</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Bulk</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Interrupt</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_ON_STALL</name>
+                        <description>Trigger an interrupt if a STALL is sent. Intended for debug only.</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_ON_NAK</name>
+                        <description>Trigger an interrupt if a NAK is sent. Intended for debug only.</description>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>BUFFER_ADDRESS</name>
+                        <description>64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.</description>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>EP3_OUT_CONTROL</name>
+                <addressOffset>0x0000001c</addressOffset>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>ENABLE</name>
+                        <description>Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.</description>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DOUBLE_BUFFERED</name>
+                        <description>This endpoint is double buffered.</description>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_PER_BUFF</name>
+                        <description>Trigger an interrupt each time a buffer is done.</description>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_PER_DOUBLE_BUFF</name>
+                        <description>Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.</description>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ENDPOINT_TYPE</name>
+                        <bitRange>[27:26]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>Control</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Isochronous</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Bulk</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Interrupt</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_ON_STALL</name>
+                        <description>Trigger an interrupt if a STALL is sent. Intended for debug only.</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_ON_NAK</name>
+                        <description>Trigger an interrupt if a NAK is sent. Intended for debug only.</description>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>BUFFER_ADDRESS</name>
+                        <description>64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.</description>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>EP4_IN_CONTROL</name>
+                <addressOffset>0x00000020</addressOffset>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>ENABLE</name>
+                        <description>Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.</description>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DOUBLE_BUFFERED</name>
+                        <description>This endpoint is double buffered.</description>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_PER_BUFF</name>
+                        <description>Trigger an interrupt each time a buffer is done.</description>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_PER_DOUBLE_BUFF</name>
+                        <description>Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.</description>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ENDPOINT_TYPE</name>
+                        <bitRange>[27:26]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>Control</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Isochronous</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Bulk</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Interrupt</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_ON_STALL</name>
+                        <description>Trigger an interrupt if a STALL is sent. Intended for debug only.</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_ON_NAK</name>
+                        <description>Trigger an interrupt if a NAK is sent. Intended for debug only.</description>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>BUFFER_ADDRESS</name>
+                        <description>64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.</description>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>EP4_OUT_CONTROL</name>
+                <addressOffset>0x00000024</addressOffset>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>ENABLE</name>
+                        <description>Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.</description>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DOUBLE_BUFFERED</name>
+                        <description>This endpoint is double buffered.</description>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_PER_BUFF</name>
+                        <description>Trigger an interrupt each time a buffer is done.</description>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_PER_DOUBLE_BUFF</name>
+                        <description>Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.</description>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ENDPOINT_TYPE</name>
+                        <bitRange>[27:26]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>Control</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Isochronous</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Bulk</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Interrupt</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_ON_STALL</name>
+                        <description>Trigger an interrupt if a STALL is sent. Intended for debug only.</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_ON_NAK</name>
+                        <description>Trigger an interrupt if a NAK is sent. Intended for debug only.</description>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>BUFFER_ADDRESS</name>
+                        <description>64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.</description>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>EP5_IN_CONTROL</name>
+                <addressOffset>0x00000028</addressOffset>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>ENABLE</name>
+                        <description>Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.</description>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DOUBLE_BUFFERED</name>
+                        <description>This endpoint is double buffered.</description>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_PER_BUFF</name>
+                        <description>Trigger an interrupt each time a buffer is done.</description>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_PER_DOUBLE_BUFF</name>
+                        <description>Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.</description>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ENDPOINT_TYPE</name>
+                        <bitRange>[27:26]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>Control</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Isochronous</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Bulk</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Interrupt</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_ON_STALL</name>
+                        <description>Trigger an interrupt if a STALL is sent. Intended for debug only.</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_ON_NAK</name>
+                        <description>Trigger an interrupt if a NAK is sent. Intended for debug only.</description>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>BUFFER_ADDRESS</name>
+                        <description>64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.</description>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>EP5_OUT_CONTROL</name>
+                <addressOffset>0x0000002c</addressOffset>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>ENABLE</name>
+                        <description>Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.</description>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DOUBLE_BUFFERED</name>
+                        <description>This endpoint is double buffered.</description>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_PER_BUFF</name>
+                        <description>Trigger an interrupt each time a buffer is done.</description>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_PER_DOUBLE_BUFF</name>
+                        <description>Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.</description>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ENDPOINT_TYPE</name>
+                        <bitRange>[27:26]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>Control</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Isochronous</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Bulk</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Interrupt</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_ON_STALL</name>
+                        <description>Trigger an interrupt if a STALL is sent. Intended for debug only.</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_ON_NAK</name>
+                        <description>Trigger an interrupt if a NAK is sent. Intended for debug only.</description>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>BUFFER_ADDRESS</name>
+                        <description>64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.</description>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>EP6_IN_CONTROL</name>
+                <addressOffset>0x00000030</addressOffset>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>ENABLE</name>
+                        <description>Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.</description>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DOUBLE_BUFFERED</name>
+                        <description>This endpoint is double buffered.</description>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_PER_BUFF</name>
+                        <description>Trigger an interrupt each time a buffer is done.</description>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_PER_DOUBLE_BUFF</name>
+                        <description>Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.</description>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ENDPOINT_TYPE</name>
+                        <bitRange>[27:26]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>Control</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Isochronous</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Bulk</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Interrupt</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_ON_STALL</name>
+                        <description>Trigger an interrupt if a STALL is sent. Intended for debug only.</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_ON_NAK</name>
+                        <description>Trigger an interrupt if a NAK is sent. Intended for debug only.</description>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>BUFFER_ADDRESS</name>
+                        <description>64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.</description>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>EP6_OUT_CONTROL</name>
+                <addressOffset>0x00000034</addressOffset>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>ENABLE</name>
+                        <description>Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.</description>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DOUBLE_BUFFERED</name>
+                        <description>This endpoint is double buffered.</description>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_PER_BUFF</name>
+                        <description>Trigger an interrupt each time a buffer is done.</description>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_PER_DOUBLE_BUFF</name>
+                        <description>Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.</description>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ENDPOINT_TYPE</name>
+                        <bitRange>[27:26]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>Control</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Isochronous</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Bulk</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Interrupt</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_ON_STALL</name>
+                        <description>Trigger an interrupt if a STALL is sent. Intended for debug only.</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_ON_NAK</name>
+                        <description>Trigger an interrupt if a NAK is sent. Intended for debug only.</description>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>BUFFER_ADDRESS</name>
+                        <description>64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.</description>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>EP7_IN_CONTROL</name>
+                <addressOffset>0x00000038</addressOffset>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>ENABLE</name>
+                        <description>Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.</description>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DOUBLE_BUFFERED</name>
+                        <description>This endpoint is double buffered.</description>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_PER_BUFF</name>
+                        <description>Trigger an interrupt each time a buffer is done.</description>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_PER_DOUBLE_BUFF</name>
+                        <description>Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.</description>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ENDPOINT_TYPE</name>
+                        <bitRange>[27:26]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>Control</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Isochronous</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Bulk</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Interrupt</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_ON_STALL</name>
+                        <description>Trigger an interrupt if a STALL is sent. Intended for debug only.</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_ON_NAK</name>
+                        <description>Trigger an interrupt if a NAK is sent. Intended for debug only.</description>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>BUFFER_ADDRESS</name>
+                        <description>64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.</description>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>EP7_OUT_CONTROL</name>
+                <addressOffset>0x0000003c</addressOffset>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>ENABLE</name>
+                        <description>Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.</description>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DOUBLE_BUFFERED</name>
+                        <description>This endpoint is double buffered.</description>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_PER_BUFF</name>
+                        <description>Trigger an interrupt each time a buffer is done.</description>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_PER_DOUBLE_BUFF</name>
+                        <description>Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.</description>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ENDPOINT_TYPE</name>
+                        <bitRange>[27:26]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>Control</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Isochronous</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Bulk</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Interrupt</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_ON_STALL</name>
+                        <description>Trigger an interrupt if a STALL is sent. Intended for debug only.</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_ON_NAK</name>
+                        <description>Trigger an interrupt if a NAK is sent. Intended for debug only.</description>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>BUFFER_ADDRESS</name>
+                        <description>64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.</description>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>EP8_IN_CONTROL</name>
+                <addressOffset>0x00000040</addressOffset>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>ENABLE</name>
+                        <description>Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.</description>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DOUBLE_BUFFERED</name>
+                        <description>This endpoint is double buffered.</description>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_PER_BUFF</name>
+                        <description>Trigger an interrupt each time a buffer is done.</description>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_PER_DOUBLE_BUFF</name>
+                        <description>Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.</description>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ENDPOINT_TYPE</name>
+                        <bitRange>[27:26]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>Control</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Isochronous</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Bulk</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Interrupt</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_ON_STALL</name>
+                        <description>Trigger an interrupt if a STALL is sent. Intended for debug only.</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_ON_NAK</name>
+                        <description>Trigger an interrupt if a NAK is sent. Intended for debug only.</description>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>BUFFER_ADDRESS</name>
+                        <description>64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.</description>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>EP8_OUT_CONTROL</name>
+                <addressOffset>0x00000044</addressOffset>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>ENABLE</name>
+                        <description>Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.</description>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DOUBLE_BUFFERED</name>
+                        <description>This endpoint is double buffered.</description>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_PER_BUFF</name>
+                        <description>Trigger an interrupt each time a buffer is done.</description>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_PER_DOUBLE_BUFF</name>
+                        <description>Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.</description>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ENDPOINT_TYPE</name>
+                        <bitRange>[27:26]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>Control</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Isochronous</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Bulk</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Interrupt</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_ON_STALL</name>
+                        <description>Trigger an interrupt if a STALL is sent. Intended for debug only.</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_ON_NAK</name>
+                        <description>Trigger an interrupt if a NAK is sent. Intended for debug only.</description>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>BUFFER_ADDRESS</name>
+                        <description>64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.</description>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>EP9_IN_CONTROL</name>
+                <addressOffset>0x00000048</addressOffset>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>ENABLE</name>
+                        <description>Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.</description>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DOUBLE_BUFFERED</name>
+                        <description>This endpoint is double buffered.</description>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_PER_BUFF</name>
+                        <description>Trigger an interrupt each time a buffer is done.</description>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_PER_DOUBLE_BUFF</name>
+                        <description>Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.</description>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ENDPOINT_TYPE</name>
+                        <bitRange>[27:26]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>Control</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Isochronous</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Bulk</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Interrupt</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_ON_STALL</name>
+                        <description>Trigger an interrupt if a STALL is sent. Intended for debug only.</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_ON_NAK</name>
+                        <description>Trigger an interrupt if a NAK is sent. Intended for debug only.</description>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>BUFFER_ADDRESS</name>
+                        <description>64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.</description>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>EP9_OUT_CONTROL</name>
+                <addressOffset>0x0000004c</addressOffset>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>ENABLE</name>
+                        <description>Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.</description>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DOUBLE_BUFFERED</name>
+                        <description>This endpoint is double buffered.</description>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_PER_BUFF</name>
+                        <description>Trigger an interrupt each time a buffer is done.</description>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_PER_DOUBLE_BUFF</name>
+                        <description>Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.</description>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ENDPOINT_TYPE</name>
+                        <bitRange>[27:26]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>Control</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Isochronous</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Bulk</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Interrupt</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_ON_STALL</name>
+                        <description>Trigger an interrupt if a STALL is sent. Intended for debug only.</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_ON_NAK</name>
+                        <description>Trigger an interrupt if a NAK is sent. Intended for debug only.</description>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>BUFFER_ADDRESS</name>
+                        <description>64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.</description>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>EP10_IN_CONTROL</name>
+                <addressOffset>0x00000050</addressOffset>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>ENABLE</name>
+                        <description>Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.</description>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DOUBLE_BUFFERED</name>
+                        <description>This endpoint is double buffered.</description>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_PER_BUFF</name>
+                        <description>Trigger an interrupt each time a buffer is done.</description>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_PER_DOUBLE_BUFF</name>
+                        <description>Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.</description>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ENDPOINT_TYPE</name>
+                        <bitRange>[27:26]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>Control</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Isochronous</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Bulk</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Interrupt</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_ON_STALL</name>
+                        <description>Trigger an interrupt if a STALL is sent. Intended for debug only.</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_ON_NAK</name>
+                        <description>Trigger an interrupt if a NAK is sent. Intended for debug only.</description>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>BUFFER_ADDRESS</name>
+                        <description>64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.</description>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>EP10_OUT_CONTROL</name>
+                <addressOffset>0x00000054</addressOffset>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>ENABLE</name>
+                        <description>Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.</description>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DOUBLE_BUFFERED</name>
+                        <description>This endpoint is double buffered.</description>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_PER_BUFF</name>
+                        <description>Trigger an interrupt each time a buffer is done.</description>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_PER_DOUBLE_BUFF</name>
+                        <description>Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.</description>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ENDPOINT_TYPE</name>
+                        <bitRange>[27:26]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>Control</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Isochronous</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Bulk</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Interrupt</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_ON_STALL</name>
+                        <description>Trigger an interrupt if a STALL is sent. Intended for debug only.</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_ON_NAK</name>
+                        <description>Trigger an interrupt if a NAK is sent. Intended for debug only.</description>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>BUFFER_ADDRESS</name>
+                        <description>64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.</description>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>EP11_IN_CONTROL</name>
+                <addressOffset>0x00000058</addressOffset>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>ENABLE</name>
+                        <description>Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.</description>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DOUBLE_BUFFERED</name>
+                        <description>This endpoint is double buffered.</description>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_PER_BUFF</name>
+                        <description>Trigger an interrupt each time a buffer is done.</description>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_PER_DOUBLE_BUFF</name>
+                        <description>Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.</description>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ENDPOINT_TYPE</name>
+                        <bitRange>[27:26]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>Control</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Isochronous</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Bulk</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Interrupt</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_ON_STALL</name>
+                        <description>Trigger an interrupt if a STALL is sent. Intended for debug only.</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_ON_NAK</name>
+                        <description>Trigger an interrupt if a NAK is sent. Intended for debug only.</description>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>BUFFER_ADDRESS</name>
+                        <description>64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.</description>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>EP11_OUT_CONTROL</name>
+                <addressOffset>0x0000005c</addressOffset>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>ENABLE</name>
+                        <description>Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.</description>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DOUBLE_BUFFERED</name>
+                        <description>This endpoint is double buffered.</description>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_PER_BUFF</name>
+                        <description>Trigger an interrupt each time a buffer is done.</description>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_PER_DOUBLE_BUFF</name>
+                        <description>Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.</description>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ENDPOINT_TYPE</name>
+                        <bitRange>[27:26]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>Control</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Isochronous</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Bulk</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Interrupt</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_ON_STALL</name>
+                        <description>Trigger an interrupt if a STALL is sent. Intended for debug only.</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_ON_NAK</name>
+                        <description>Trigger an interrupt if a NAK is sent. Intended for debug only.</description>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>BUFFER_ADDRESS</name>
+                        <description>64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.</description>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>EP12_IN_CONTROL</name>
+                <addressOffset>0x00000060</addressOffset>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>ENABLE</name>
+                        <description>Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.</description>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DOUBLE_BUFFERED</name>
+                        <description>This endpoint is double buffered.</description>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_PER_BUFF</name>
+                        <description>Trigger an interrupt each time a buffer is done.</description>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_PER_DOUBLE_BUFF</name>
+                        <description>Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.</description>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ENDPOINT_TYPE</name>
+                        <bitRange>[27:26]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>Control</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Isochronous</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Bulk</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Interrupt</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_ON_STALL</name>
+                        <description>Trigger an interrupt if a STALL is sent. Intended for debug only.</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_ON_NAK</name>
+                        <description>Trigger an interrupt if a NAK is sent. Intended for debug only.</description>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>BUFFER_ADDRESS</name>
+                        <description>64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.</description>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>EP12_OUT_CONTROL</name>
+                <addressOffset>0x00000064</addressOffset>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>ENABLE</name>
+                        <description>Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.</description>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DOUBLE_BUFFERED</name>
+                        <description>This endpoint is double buffered.</description>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_PER_BUFF</name>
+                        <description>Trigger an interrupt each time a buffer is done.</description>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_PER_DOUBLE_BUFF</name>
+                        <description>Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.</description>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ENDPOINT_TYPE</name>
+                        <bitRange>[27:26]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>Control</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Isochronous</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Bulk</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Interrupt</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_ON_STALL</name>
+                        <description>Trigger an interrupt if a STALL is sent. Intended for debug only.</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_ON_NAK</name>
+                        <description>Trigger an interrupt if a NAK is sent. Intended for debug only.</description>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>BUFFER_ADDRESS</name>
+                        <description>64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.</description>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>EP13_IN_CONTROL</name>
+                <addressOffset>0x00000068</addressOffset>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>ENABLE</name>
+                        <description>Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.</description>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DOUBLE_BUFFERED</name>
+                        <description>This endpoint is double buffered.</description>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_PER_BUFF</name>
+                        <description>Trigger an interrupt each time a buffer is done.</description>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_PER_DOUBLE_BUFF</name>
+                        <description>Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.</description>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ENDPOINT_TYPE</name>
+                        <bitRange>[27:26]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>Control</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Isochronous</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Bulk</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Interrupt</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_ON_STALL</name>
+                        <description>Trigger an interrupt if a STALL is sent. Intended for debug only.</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_ON_NAK</name>
+                        <description>Trigger an interrupt if a NAK is sent. Intended for debug only.</description>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>BUFFER_ADDRESS</name>
+                        <description>64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.</description>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>EP13_OUT_CONTROL</name>
+                <addressOffset>0x0000006c</addressOffset>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>ENABLE</name>
+                        <description>Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.</description>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DOUBLE_BUFFERED</name>
+                        <description>This endpoint is double buffered.</description>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_PER_BUFF</name>
+                        <description>Trigger an interrupt each time a buffer is done.</description>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_PER_DOUBLE_BUFF</name>
+                        <description>Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.</description>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ENDPOINT_TYPE</name>
+                        <bitRange>[27:26]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>Control</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Isochronous</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Bulk</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Interrupt</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_ON_STALL</name>
+                        <description>Trigger an interrupt if a STALL is sent. Intended for debug only.</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_ON_NAK</name>
+                        <description>Trigger an interrupt if a NAK is sent. Intended for debug only.</description>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>BUFFER_ADDRESS</name>
+                        <description>64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.</description>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>EP14_IN_CONTROL</name>
+                <addressOffset>0x00000070</addressOffset>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>ENABLE</name>
+                        <description>Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.</description>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DOUBLE_BUFFERED</name>
+                        <description>This endpoint is double buffered.</description>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_PER_BUFF</name>
+                        <description>Trigger an interrupt each time a buffer is done.</description>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_PER_DOUBLE_BUFF</name>
+                        <description>Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.</description>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ENDPOINT_TYPE</name>
+                        <bitRange>[27:26]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>Control</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Isochronous</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Bulk</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Interrupt</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_ON_STALL</name>
+                        <description>Trigger an interrupt if a STALL is sent. Intended for debug only.</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_ON_NAK</name>
+                        <description>Trigger an interrupt if a NAK is sent. Intended for debug only.</description>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>BUFFER_ADDRESS</name>
+                        <description>64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.</description>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>EP14_OUT_CONTROL</name>
+                <addressOffset>0x00000074</addressOffset>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>ENABLE</name>
+                        <description>Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.</description>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DOUBLE_BUFFERED</name>
+                        <description>This endpoint is double buffered.</description>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_PER_BUFF</name>
+                        <description>Trigger an interrupt each time a buffer is done.</description>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_PER_DOUBLE_BUFF</name>
+                        <description>Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.</description>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ENDPOINT_TYPE</name>
+                        <bitRange>[27:26]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>Control</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Isochronous</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Bulk</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Interrupt</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_ON_STALL</name>
+                        <description>Trigger an interrupt if a STALL is sent. Intended for debug only.</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_ON_NAK</name>
+                        <description>Trigger an interrupt if a NAK is sent. Intended for debug only.</description>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>BUFFER_ADDRESS</name>
+                        <description>64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.</description>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>EP15_IN_CONTROL</name>
+                <addressOffset>0x00000078</addressOffset>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>ENABLE</name>
+                        <description>Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.</description>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DOUBLE_BUFFERED</name>
+                        <description>This endpoint is double buffered.</description>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_PER_BUFF</name>
+                        <description>Trigger an interrupt each time a buffer is done.</description>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_PER_DOUBLE_BUFF</name>
+                        <description>Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.</description>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ENDPOINT_TYPE</name>
+                        <bitRange>[27:26]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>Control</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Isochronous</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Bulk</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Interrupt</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_ON_STALL</name>
+                        <description>Trigger an interrupt if a STALL is sent. Intended for debug only.</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_ON_NAK</name>
+                        <description>Trigger an interrupt if a NAK is sent. Intended for debug only.</description>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>BUFFER_ADDRESS</name>
+                        <description>64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.</description>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>EP15_OUT_CONTROL</name>
+                <addressOffset>0x0000007c</addressOffset>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>ENABLE</name>
+                        <description>Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.</description>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DOUBLE_BUFFERED</name>
+                        <description>This endpoint is double buffered.</description>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_PER_BUFF</name>
+                        <description>Trigger an interrupt each time a buffer is done.</description>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_PER_DOUBLE_BUFF</name>
+                        <description>Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.</description>
+                        <bitRange>[28:28]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>ENDPOINT_TYPE</name>
+                        <bitRange>[27:26]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>Control</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Isochronous</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Bulk</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>Interrupt</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_ON_STALL</name>
+                        <description>Trigger an interrupt if a STALL is sent. Intended for debug only.</description>
+                        <bitRange>[17:17]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>INTERRUPT_ON_NAK</name>
+                        <description>Trigger an interrupt if a NAK is sent. Intended for debug only.</description>
+                        <bitRange>[16:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>BUFFER_ADDRESS</name>
+                        <description>64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.</description>
+                        <bitRange>[15:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>EP0_IN_BUFFER_CONTROL</name>
+                <addressOffset>0x00000080</addressOffset>
+                <description>Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. 
+                    Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>FULL_1</name>
+                        <description>Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LAST_1</name>
+                        <description>Buffer 1 is the last buffer of the transfer.</description>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PID_1</name>
+                        <description>The data pid of buffer 1.</description>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DOUBLE_BUFFER_ISO_OFFSET</name>
+                        <description>The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. 
+                            For a non Isochronous endpoint the offset is always 64 bytes.</description>
+                        <bitRange>[28:27]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>128</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>256</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>512</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>1024</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>AVAILABLE_1</name>
+                        <description>Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LENGTH_1</name>
+                        <description>The length of the data in buffer 1.</description>
+                        <bitRange>[25:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>FULL_0</name>
+                        <description>Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LAST_0</name>
+                        <description>Buffer 0 is the last buffer of the transfer.</description>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PID_0</name>
+                        <description>The data pid of buffer 0.</description>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>RESET</name>
+                        <description>Reset the buffer selector to buffer 0.</description>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>STALL</name>
+                        <description>Reply with a stall (valid for both buffers).</description>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>AVAILABLE_0</name>
+                        <description>Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LENGTH_0</name>
+                        <description>The length of the data in buffer 1.</description>
+                        <bitRange>[9:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>EP0_OUT_BUFFER_CONTROL</name>
+                <addressOffset>0x00000084</addressOffset>
+                <description>Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. 
+                    Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>FULL_1</name>
+                        <description>Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LAST_1</name>
+                        <description>Buffer 1 is the last buffer of the transfer.</description>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PID_1</name>
+                        <description>The data pid of buffer 1.</description>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DOUBLE_BUFFER_ISO_OFFSET</name>
+                        <description>The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. 
+                            For a non Isochronous endpoint the offset is always 64 bytes.</description>
+                        <bitRange>[28:27]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>128</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>256</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>512</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>1024</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>AVAILABLE_1</name>
+                        <description>Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LENGTH_1</name>
+                        <description>The length of the data in buffer 1.</description>
+                        <bitRange>[25:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>FULL_0</name>
+                        <description>Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LAST_0</name>
+                        <description>Buffer 0 is the last buffer of the transfer.</description>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PID_0</name>
+                        <description>The data pid of buffer 0.</description>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>RESET</name>
+                        <description>Reset the buffer selector to buffer 0.</description>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>STALL</name>
+                        <description>Reply with a stall (valid for both buffers).</description>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>AVAILABLE_0</name>
+                        <description>Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LENGTH_0</name>
+                        <description>The length of the data in buffer 1.</description>
+                        <bitRange>[9:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>EP1_IN_BUFFER_CONTROL</name>
+                <addressOffset>0x00000088</addressOffset>
+                <description>Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. 
+                    Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>FULL_1</name>
+                        <description>Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LAST_1</name>
+                        <description>Buffer 1 is the last buffer of the transfer.</description>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PID_1</name>
+                        <description>The data pid of buffer 1.</description>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DOUBLE_BUFFER_ISO_OFFSET</name>
+                        <description>The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. 
+                            For a non Isochronous endpoint the offset is always 64 bytes.</description>
+                        <bitRange>[28:27]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>128</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>256</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>512</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>1024</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>AVAILABLE_1</name>
+                        <description>Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LENGTH_1</name>
+                        <description>The length of the data in buffer 1.</description>
+                        <bitRange>[25:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>FULL_0</name>
+                        <description>Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LAST_0</name>
+                        <description>Buffer 0 is the last buffer of the transfer.</description>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PID_0</name>
+                        <description>The data pid of buffer 0.</description>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>RESET</name>
+                        <description>Reset the buffer selector to buffer 0.</description>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>STALL</name>
+                        <description>Reply with a stall (valid for both buffers).</description>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>AVAILABLE_0</name>
+                        <description>Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LENGTH_0</name>
+                        <description>The length of the data in buffer 1.</description>
+                        <bitRange>[9:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>EP1_OUT_BUFFER_CONTROL</name>
+                <addressOffset>0x0000008c</addressOffset>
+                <description>Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. 
+                    Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>FULL_1</name>
+                        <description>Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LAST_1</name>
+                        <description>Buffer 1 is the last buffer of the transfer.</description>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PID_1</name>
+                        <description>The data pid of buffer 1.</description>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DOUBLE_BUFFER_ISO_OFFSET</name>
+                        <description>The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. 
+                            For a non Isochronous endpoint the offset is always 64 bytes.</description>
+                        <bitRange>[28:27]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>128</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>256</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>512</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>1024</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>AVAILABLE_1</name>
+                        <description>Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LENGTH_1</name>
+                        <description>The length of the data in buffer 1.</description>
+                        <bitRange>[25:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>FULL_0</name>
+                        <description>Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LAST_0</name>
+                        <description>Buffer 0 is the last buffer of the transfer.</description>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PID_0</name>
+                        <description>The data pid of buffer 0.</description>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>RESET</name>
+                        <description>Reset the buffer selector to buffer 0.</description>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>STALL</name>
+                        <description>Reply with a stall (valid for both buffers).</description>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>AVAILABLE_0</name>
+                        <description>Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LENGTH_0</name>
+                        <description>The length of the data in buffer 1.</description>
+                        <bitRange>[9:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>EP2_IN_BUFFER_CONTROL</name>
+                <addressOffset>0x00000090</addressOffset>
+                <description>Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. 
+                    Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>FULL_1</name>
+                        <description>Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LAST_1</name>
+                        <description>Buffer 1 is the last buffer of the transfer.</description>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PID_1</name>
+                        <description>The data pid of buffer 1.</description>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DOUBLE_BUFFER_ISO_OFFSET</name>
+                        <description>The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. 
+                            For a non Isochronous endpoint the offset is always 64 bytes.</description>
+                        <bitRange>[28:27]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>128</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>256</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>512</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>1024</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>AVAILABLE_1</name>
+                        <description>Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LENGTH_1</name>
+                        <description>The length of the data in buffer 1.</description>
+                        <bitRange>[25:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>FULL_0</name>
+                        <description>Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LAST_0</name>
+                        <description>Buffer 0 is the last buffer of the transfer.</description>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PID_0</name>
+                        <description>The data pid of buffer 0.</description>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>RESET</name>
+                        <description>Reset the buffer selector to buffer 0.</description>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>STALL</name>
+                        <description>Reply with a stall (valid for both buffers).</description>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>AVAILABLE_0</name>
+                        <description>Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LENGTH_0</name>
+                        <description>The length of the data in buffer 1.</description>
+                        <bitRange>[9:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>EP2_OUT_BUFFER_CONTROL</name>
+                <addressOffset>0x00000094</addressOffset>
+                <description>Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. 
+                    Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>FULL_1</name>
+                        <description>Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LAST_1</name>
+                        <description>Buffer 1 is the last buffer of the transfer.</description>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PID_1</name>
+                        <description>The data pid of buffer 1.</description>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DOUBLE_BUFFER_ISO_OFFSET</name>
+                        <description>The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. 
+                            For a non Isochronous endpoint the offset is always 64 bytes.</description>
+                        <bitRange>[28:27]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>128</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>256</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>512</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>1024</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>AVAILABLE_1</name>
+                        <description>Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LENGTH_1</name>
+                        <description>The length of the data in buffer 1.</description>
+                        <bitRange>[25:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>FULL_0</name>
+                        <description>Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LAST_0</name>
+                        <description>Buffer 0 is the last buffer of the transfer.</description>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PID_0</name>
+                        <description>The data pid of buffer 0.</description>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>RESET</name>
+                        <description>Reset the buffer selector to buffer 0.</description>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>STALL</name>
+                        <description>Reply with a stall (valid for both buffers).</description>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>AVAILABLE_0</name>
+                        <description>Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LENGTH_0</name>
+                        <description>The length of the data in buffer 1.</description>
+                        <bitRange>[9:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>EP3_IN_BUFFER_CONTROL</name>
+                <addressOffset>0x00000098</addressOffset>
+                <description>Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. 
+                    Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>FULL_1</name>
+                        <description>Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LAST_1</name>
+                        <description>Buffer 1 is the last buffer of the transfer.</description>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PID_1</name>
+                        <description>The data pid of buffer 1.</description>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DOUBLE_BUFFER_ISO_OFFSET</name>
+                        <description>The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. 
+                            For a non Isochronous endpoint the offset is always 64 bytes.</description>
+                        <bitRange>[28:27]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>128</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>256</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>512</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>1024</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>AVAILABLE_1</name>
+                        <description>Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LENGTH_1</name>
+                        <description>The length of the data in buffer 1.</description>
+                        <bitRange>[25:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>FULL_0</name>
+                        <description>Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LAST_0</name>
+                        <description>Buffer 0 is the last buffer of the transfer.</description>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PID_0</name>
+                        <description>The data pid of buffer 0.</description>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>RESET</name>
+                        <description>Reset the buffer selector to buffer 0.</description>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>STALL</name>
+                        <description>Reply with a stall (valid for both buffers).</description>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>AVAILABLE_0</name>
+                        <description>Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LENGTH_0</name>
+                        <description>The length of the data in buffer 1.</description>
+                        <bitRange>[9:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>EP3_OUT_BUFFER_CONTROL</name>
+                <addressOffset>0x0000009c</addressOffset>
+                <description>Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. 
+                    Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>FULL_1</name>
+                        <description>Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LAST_1</name>
+                        <description>Buffer 1 is the last buffer of the transfer.</description>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PID_1</name>
+                        <description>The data pid of buffer 1.</description>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DOUBLE_BUFFER_ISO_OFFSET</name>
+                        <description>The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. 
+                            For a non Isochronous endpoint the offset is always 64 bytes.</description>
+                        <bitRange>[28:27]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>128</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>256</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>512</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>1024</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>AVAILABLE_1</name>
+                        <description>Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LENGTH_1</name>
+                        <description>The length of the data in buffer 1.</description>
+                        <bitRange>[25:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>FULL_0</name>
+                        <description>Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LAST_0</name>
+                        <description>Buffer 0 is the last buffer of the transfer.</description>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PID_0</name>
+                        <description>The data pid of buffer 0.</description>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>RESET</name>
+                        <description>Reset the buffer selector to buffer 0.</description>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>STALL</name>
+                        <description>Reply with a stall (valid for both buffers).</description>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>AVAILABLE_0</name>
+                        <description>Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LENGTH_0</name>
+                        <description>The length of the data in buffer 1.</description>
+                        <bitRange>[9:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>EP4_IN_BUFFER_CONTROL</name>
+                <addressOffset>0x000000a0</addressOffset>
+                <description>Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. 
+                    Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>FULL_1</name>
+                        <description>Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LAST_1</name>
+                        <description>Buffer 1 is the last buffer of the transfer.</description>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PID_1</name>
+                        <description>The data pid of buffer 1.</description>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DOUBLE_BUFFER_ISO_OFFSET</name>
+                        <description>The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. 
+                            For a non Isochronous endpoint the offset is always 64 bytes.</description>
+                        <bitRange>[28:27]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>128</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>256</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>512</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>1024</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>AVAILABLE_1</name>
+                        <description>Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LENGTH_1</name>
+                        <description>The length of the data in buffer 1.</description>
+                        <bitRange>[25:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>FULL_0</name>
+                        <description>Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LAST_0</name>
+                        <description>Buffer 0 is the last buffer of the transfer.</description>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PID_0</name>
+                        <description>The data pid of buffer 0.</description>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>RESET</name>
+                        <description>Reset the buffer selector to buffer 0.</description>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>STALL</name>
+                        <description>Reply with a stall (valid for both buffers).</description>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>AVAILABLE_0</name>
+                        <description>Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LENGTH_0</name>
+                        <description>The length of the data in buffer 1.</description>
+                        <bitRange>[9:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>EP4_OUT_BUFFER_CONTROL</name>
+                <addressOffset>0x000000a4</addressOffset>
+                <description>Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. 
+                    Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>FULL_1</name>
+                        <description>Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LAST_1</name>
+                        <description>Buffer 1 is the last buffer of the transfer.</description>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PID_1</name>
+                        <description>The data pid of buffer 1.</description>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DOUBLE_BUFFER_ISO_OFFSET</name>
+                        <description>The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. 
+                            For a non Isochronous endpoint the offset is always 64 bytes.</description>
+                        <bitRange>[28:27]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>128</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>256</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>512</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>1024</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>AVAILABLE_1</name>
+                        <description>Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LENGTH_1</name>
+                        <description>The length of the data in buffer 1.</description>
+                        <bitRange>[25:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>FULL_0</name>
+                        <description>Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LAST_0</name>
+                        <description>Buffer 0 is the last buffer of the transfer.</description>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PID_0</name>
+                        <description>The data pid of buffer 0.</description>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>RESET</name>
+                        <description>Reset the buffer selector to buffer 0.</description>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>STALL</name>
+                        <description>Reply with a stall (valid for both buffers).</description>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>AVAILABLE_0</name>
+                        <description>Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LENGTH_0</name>
+                        <description>The length of the data in buffer 1.</description>
+                        <bitRange>[9:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>EP5_IN_BUFFER_CONTROL</name>
+                <addressOffset>0x000000a8</addressOffset>
+                <description>Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. 
+                    Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>FULL_1</name>
+                        <description>Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LAST_1</name>
+                        <description>Buffer 1 is the last buffer of the transfer.</description>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PID_1</name>
+                        <description>The data pid of buffer 1.</description>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DOUBLE_BUFFER_ISO_OFFSET</name>
+                        <description>The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. 
+                            For a non Isochronous endpoint the offset is always 64 bytes.</description>
+                        <bitRange>[28:27]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>128</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>256</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>512</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>1024</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>AVAILABLE_1</name>
+                        <description>Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LENGTH_1</name>
+                        <description>The length of the data in buffer 1.</description>
+                        <bitRange>[25:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>FULL_0</name>
+                        <description>Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LAST_0</name>
+                        <description>Buffer 0 is the last buffer of the transfer.</description>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PID_0</name>
+                        <description>The data pid of buffer 0.</description>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>RESET</name>
+                        <description>Reset the buffer selector to buffer 0.</description>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>STALL</name>
+                        <description>Reply with a stall (valid for both buffers).</description>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>AVAILABLE_0</name>
+                        <description>Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LENGTH_0</name>
+                        <description>The length of the data in buffer 1.</description>
+                        <bitRange>[9:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>EP5_OUT_BUFFER_CONTROL</name>
+                <addressOffset>0x000000ac</addressOffset>
+                <description>Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. 
+                    Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>FULL_1</name>
+                        <description>Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LAST_1</name>
+                        <description>Buffer 1 is the last buffer of the transfer.</description>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PID_1</name>
+                        <description>The data pid of buffer 1.</description>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DOUBLE_BUFFER_ISO_OFFSET</name>
+                        <description>The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. 
+                            For a non Isochronous endpoint the offset is always 64 bytes.</description>
+                        <bitRange>[28:27]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>128</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>256</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>512</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>1024</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>AVAILABLE_1</name>
+                        <description>Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LENGTH_1</name>
+                        <description>The length of the data in buffer 1.</description>
+                        <bitRange>[25:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>FULL_0</name>
+                        <description>Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LAST_0</name>
+                        <description>Buffer 0 is the last buffer of the transfer.</description>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PID_0</name>
+                        <description>The data pid of buffer 0.</description>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>RESET</name>
+                        <description>Reset the buffer selector to buffer 0.</description>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>STALL</name>
+                        <description>Reply with a stall (valid for both buffers).</description>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>AVAILABLE_0</name>
+                        <description>Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LENGTH_0</name>
+                        <description>The length of the data in buffer 1.</description>
+                        <bitRange>[9:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>EP6_IN_BUFFER_CONTROL</name>
+                <addressOffset>0x000000b0</addressOffset>
+                <description>Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. 
+                    Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>FULL_1</name>
+                        <description>Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LAST_1</name>
+                        <description>Buffer 1 is the last buffer of the transfer.</description>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PID_1</name>
+                        <description>The data pid of buffer 1.</description>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DOUBLE_BUFFER_ISO_OFFSET</name>
+                        <description>The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. 
+                            For a non Isochronous endpoint the offset is always 64 bytes.</description>
+                        <bitRange>[28:27]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>128</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>256</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>512</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>1024</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>AVAILABLE_1</name>
+                        <description>Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LENGTH_1</name>
+                        <description>The length of the data in buffer 1.</description>
+                        <bitRange>[25:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>FULL_0</name>
+                        <description>Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LAST_0</name>
+                        <description>Buffer 0 is the last buffer of the transfer.</description>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PID_0</name>
+                        <description>The data pid of buffer 0.</description>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>RESET</name>
+                        <description>Reset the buffer selector to buffer 0.</description>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>STALL</name>
+                        <description>Reply with a stall (valid for both buffers).</description>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>AVAILABLE_0</name>
+                        <description>Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LENGTH_0</name>
+                        <description>The length of the data in buffer 1.</description>
+                        <bitRange>[9:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>EP6_OUT_BUFFER_CONTROL</name>
+                <addressOffset>0x000000b4</addressOffset>
+                <description>Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. 
+                    Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>FULL_1</name>
+                        <description>Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LAST_1</name>
+                        <description>Buffer 1 is the last buffer of the transfer.</description>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PID_1</name>
+                        <description>The data pid of buffer 1.</description>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DOUBLE_BUFFER_ISO_OFFSET</name>
+                        <description>The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. 
+                            For a non Isochronous endpoint the offset is always 64 bytes.</description>
+                        <bitRange>[28:27]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>128</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>256</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>512</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>1024</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>AVAILABLE_1</name>
+                        <description>Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LENGTH_1</name>
+                        <description>The length of the data in buffer 1.</description>
+                        <bitRange>[25:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>FULL_0</name>
+                        <description>Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LAST_0</name>
+                        <description>Buffer 0 is the last buffer of the transfer.</description>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PID_0</name>
+                        <description>The data pid of buffer 0.</description>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>RESET</name>
+                        <description>Reset the buffer selector to buffer 0.</description>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>STALL</name>
+                        <description>Reply with a stall (valid for both buffers).</description>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>AVAILABLE_0</name>
+                        <description>Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LENGTH_0</name>
+                        <description>The length of the data in buffer 1.</description>
+                        <bitRange>[9:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>EP7_IN_BUFFER_CONTROL</name>
+                <addressOffset>0x000000b8</addressOffset>
+                <description>Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. 
+                    Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>FULL_1</name>
+                        <description>Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LAST_1</name>
+                        <description>Buffer 1 is the last buffer of the transfer.</description>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PID_1</name>
+                        <description>The data pid of buffer 1.</description>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DOUBLE_BUFFER_ISO_OFFSET</name>
+                        <description>The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. 
+                            For a non Isochronous endpoint the offset is always 64 bytes.</description>
+                        <bitRange>[28:27]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>128</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>256</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>512</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>1024</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>AVAILABLE_1</name>
+                        <description>Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LENGTH_1</name>
+                        <description>The length of the data in buffer 1.</description>
+                        <bitRange>[25:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>FULL_0</name>
+                        <description>Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LAST_0</name>
+                        <description>Buffer 0 is the last buffer of the transfer.</description>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PID_0</name>
+                        <description>The data pid of buffer 0.</description>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>RESET</name>
+                        <description>Reset the buffer selector to buffer 0.</description>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>STALL</name>
+                        <description>Reply with a stall (valid for both buffers).</description>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>AVAILABLE_0</name>
+                        <description>Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LENGTH_0</name>
+                        <description>The length of the data in buffer 1.</description>
+                        <bitRange>[9:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>EP7_OUT_BUFFER_CONTROL</name>
+                <addressOffset>0x000000bc</addressOffset>
+                <description>Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. 
+                    Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>FULL_1</name>
+                        <description>Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LAST_1</name>
+                        <description>Buffer 1 is the last buffer of the transfer.</description>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PID_1</name>
+                        <description>The data pid of buffer 1.</description>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DOUBLE_BUFFER_ISO_OFFSET</name>
+                        <description>The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. 
+                            For a non Isochronous endpoint the offset is always 64 bytes.</description>
+                        <bitRange>[28:27]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>128</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>256</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>512</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>1024</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>AVAILABLE_1</name>
+                        <description>Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LENGTH_1</name>
+                        <description>The length of the data in buffer 1.</description>
+                        <bitRange>[25:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>FULL_0</name>
+                        <description>Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LAST_0</name>
+                        <description>Buffer 0 is the last buffer of the transfer.</description>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PID_0</name>
+                        <description>The data pid of buffer 0.</description>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>RESET</name>
+                        <description>Reset the buffer selector to buffer 0.</description>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>STALL</name>
+                        <description>Reply with a stall (valid for both buffers).</description>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>AVAILABLE_0</name>
+                        <description>Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LENGTH_0</name>
+                        <description>The length of the data in buffer 1.</description>
+                        <bitRange>[9:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>EP8_IN_BUFFER_CONTROL</name>
+                <addressOffset>0x000000c0</addressOffset>
+                <description>Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. 
+                    Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>FULL_1</name>
+                        <description>Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LAST_1</name>
+                        <description>Buffer 1 is the last buffer of the transfer.</description>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PID_1</name>
+                        <description>The data pid of buffer 1.</description>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DOUBLE_BUFFER_ISO_OFFSET</name>
+                        <description>The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. 
+                            For a non Isochronous endpoint the offset is always 64 bytes.</description>
+                        <bitRange>[28:27]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>128</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>256</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>512</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>1024</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>AVAILABLE_1</name>
+                        <description>Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LENGTH_1</name>
+                        <description>The length of the data in buffer 1.</description>
+                        <bitRange>[25:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>FULL_0</name>
+                        <description>Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LAST_0</name>
+                        <description>Buffer 0 is the last buffer of the transfer.</description>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PID_0</name>
+                        <description>The data pid of buffer 0.</description>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>RESET</name>
+                        <description>Reset the buffer selector to buffer 0.</description>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>STALL</name>
+                        <description>Reply with a stall (valid for both buffers).</description>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>AVAILABLE_0</name>
+                        <description>Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LENGTH_0</name>
+                        <description>The length of the data in buffer 1.</description>
+                        <bitRange>[9:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>EP8_OUT_BUFFER_CONTROL</name>
+                <addressOffset>0x000000c4</addressOffset>
+                <description>Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. 
+                    Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>FULL_1</name>
+                        <description>Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LAST_1</name>
+                        <description>Buffer 1 is the last buffer of the transfer.</description>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PID_1</name>
+                        <description>The data pid of buffer 1.</description>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DOUBLE_BUFFER_ISO_OFFSET</name>
+                        <description>The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. 
+                            For a non Isochronous endpoint the offset is always 64 bytes.</description>
+                        <bitRange>[28:27]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>128</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>256</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>512</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>1024</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>AVAILABLE_1</name>
+                        <description>Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LENGTH_1</name>
+                        <description>The length of the data in buffer 1.</description>
+                        <bitRange>[25:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>FULL_0</name>
+                        <description>Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LAST_0</name>
+                        <description>Buffer 0 is the last buffer of the transfer.</description>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PID_0</name>
+                        <description>The data pid of buffer 0.</description>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>RESET</name>
+                        <description>Reset the buffer selector to buffer 0.</description>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>STALL</name>
+                        <description>Reply with a stall (valid for both buffers).</description>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>AVAILABLE_0</name>
+                        <description>Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LENGTH_0</name>
+                        <description>The length of the data in buffer 1.</description>
+                        <bitRange>[9:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>EP9_IN_BUFFER_CONTROL</name>
+                <addressOffset>0x000000c8</addressOffset>
+                <description>Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. 
+                    Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>FULL_1</name>
+                        <description>Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LAST_1</name>
+                        <description>Buffer 1 is the last buffer of the transfer.</description>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PID_1</name>
+                        <description>The data pid of buffer 1.</description>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DOUBLE_BUFFER_ISO_OFFSET</name>
+                        <description>The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. 
+                            For a non Isochronous endpoint the offset is always 64 bytes.</description>
+                        <bitRange>[28:27]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>128</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>256</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>512</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>1024</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>AVAILABLE_1</name>
+                        <description>Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LENGTH_1</name>
+                        <description>The length of the data in buffer 1.</description>
+                        <bitRange>[25:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>FULL_0</name>
+                        <description>Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LAST_0</name>
+                        <description>Buffer 0 is the last buffer of the transfer.</description>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PID_0</name>
+                        <description>The data pid of buffer 0.</description>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>RESET</name>
+                        <description>Reset the buffer selector to buffer 0.</description>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>STALL</name>
+                        <description>Reply with a stall (valid for both buffers).</description>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>AVAILABLE_0</name>
+                        <description>Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LENGTH_0</name>
+                        <description>The length of the data in buffer 1.</description>
+                        <bitRange>[9:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>EP9_OUT_BUFFER_CONTROL</name>
+                <addressOffset>0x000000cc</addressOffset>
+                <description>Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. 
+                    Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>FULL_1</name>
+                        <description>Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LAST_1</name>
+                        <description>Buffer 1 is the last buffer of the transfer.</description>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PID_1</name>
+                        <description>The data pid of buffer 1.</description>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DOUBLE_BUFFER_ISO_OFFSET</name>
+                        <description>The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. 
+                            For a non Isochronous endpoint the offset is always 64 bytes.</description>
+                        <bitRange>[28:27]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>128</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>256</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>512</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>1024</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>AVAILABLE_1</name>
+                        <description>Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LENGTH_1</name>
+                        <description>The length of the data in buffer 1.</description>
+                        <bitRange>[25:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>FULL_0</name>
+                        <description>Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LAST_0</name>
+                        <description>Buffer 0 is the last buffer of the transfer.</description>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PID_0</name>
+                        <description>The data pid of buffer 0.</description>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>RESET</name>
+                        <description>Reset the buffer selector to buffer 0.</description>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>STALL</name>
+                        <description>Reply with a stall (valid for both buffers).</description>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>AVAILABLE_0</name>
+                        <description>Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LENGTH_0</name>
+                        <description>The length of the data in buffer 1.</description>
+                        <bitRange>[9:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>EP10_IN_BUFFER_CONTROL</name>
+                <addressOffset>0x000000d0</addressOffset>
+                <description>Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. 
+                    Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>FULL_1</name>
+                        <description>Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LAST_1</name>
+                        <description>Buffer 1 is the last buffer of the transfer.</description>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PID_1</name>
+                        <description>The data pid of buffer 1.</description>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DOUBLE_BUFFER_ISO_OFFSET</name>
+                        <description>The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. 
+                            For a non Isochronous endpoint the offset is always 64 bytes.</description>
+                        <bitRange>[28:27]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>128</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>256</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>512</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>1024</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>AVAILABLE_1</name>
+                        <description>Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LENGTH_1</name>
+                        <description>The length of the data in buffer 1.</description>
+                        <bitRange>[25:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>FULL_0</name>
+                        <description>Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LAST_0</name>
+                        <description>Buffer 0 is the last buffer of the transfer.</description>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PID_0</name>
+                        <description>The data pid of buffer 0.</description>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>RESET</name>
+                        <description>Reset the buffer selector to buffer 0.</description>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>STALL</name>
+                        <description>Reply with a stall (valid for both buffers).</description>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>AVAILABLE_0</name>
+                        <description>Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LENGTH_0</name>
+                        <description>The length of the data in buffer 1.</description>
+                        <bitRange>[9:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>EP10_OUT_BUFFER_CONTROL</name>
+                <addressOffset>0x000000d4</addressOffset>
+                <description>Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. 
+                    Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>FULL_1</name>
+                        <description>Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LAST_1</name>
+                        <description>Buffer 1 is the last buffer of the transfer.</description>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PID_1</name>
+                        <description>The data pid of buffer 1.</description>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DOUBLE_BUFFER_ISO_OFFSET</name>
+                        <description>The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. 
+                            For a non Isochronous endpoint the offset is always 64 bytes.</description>
+                        <bitRange>[28:27]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>128</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>256</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>512</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>1024</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>AVAILABLE_1</name>
+                        <description>Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LENGTH_1</name>
+                        <description>The length of the data in buffer 1.</description>
+                        <bitRange>[25:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>FULL_0</name>
+                        <description>Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LAST_0</name>
+                        <description>Buffer 0 is the last buffer of the transfer.</description>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PID_0</name>
+                        <description>The data pid of buffer 0.</description>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>RESET</name>
+                        <description>Reset the buffer selector to buffer 0.</description>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>STALL</name>
+                        <description>Reply with a stall (valid for both buffers).</description>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>AVAILABLE_0</name>
+                        <description>Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LENGTH_0</name>
+                        <description>The length of the data in buffer 1.</description>
+                        <bitRange>[9:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>EP11_IN_BUFFER_CONTROL</name>
+                <addressOffset>0x000000d8</addressOffset>
+                <description>Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. 
+                    Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>FULL_1</name>
+                        <description>Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LAST_1</name>
+                        <description>Buffer 1 is the last buffer of the transfer.</description>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PID_1</name>
+                        <description>The data pid of buffer 1.</description>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DOUBLE_BUFFER_ISO_OFFSET</name>
+                        <description>The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. 
+                            For a non Isochronous endpoint the offset is always 64 bytes.</description>
+                        <bitRange>[28:27]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>128</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>256</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>512</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>1024</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>AVAILABLE_1</name>
+                        <description>Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LENGTH_1</name>
+                        <description>The length of the data in buffer 1.</description>
+                        <bitRange>[25:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>FULL_0</name>
+                        <description>Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LAST_0</name>
+                        <description>Buffer 0 is the last buffer of the transfer.</description>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PID_0</name>
+                        <description>The data pid of buffer 0.</description>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>RESET</name>
+                        <description>Reset the buffer selector to buffer 0.</description>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>STALL</name>
+                        <description>Reply with a stall (valid for both buffers).</description>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>AVAILABLE_0</name>
+                        <description>Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LENGTH_0</name>
+                        <description>The length of the data in buffer 1.</description>
+                        <bitRange>[9:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>EP11_OUT_BUFFER_CONTROL</name>
+                <addressOffset>0x000000dc</addressOffset>
+                <description>Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. 
+                    Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>FULL_1</name>
+                        <description>Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LAST_1</name>
+                        <description>Buffer 1 is the last buffer of the transfer.</description>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PID_1</name>
+                        <description>The data pid of buffer 1.</description>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DOUBLE_BUFFER_ISO_OFFSET</name>
+                        <description>The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. 
+                            For a non Isochronous endpoint the offset is always 64 bytes.</description>
+                        <bitRange>[28:27]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>128</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>256</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>512</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>1024</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>AVAILABLE_1</name>
+                        <description>Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LENGTH_1</name>
+                        <description>The length of the data in buffer 1.</description>
+                        <bitRange>[25:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>FULL_0</name>
+                        <description>Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LAST_0</name>
+                        <description>Buffer 0 is the last buffer of the transfer.</description>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PID_0</name>
+                        <description>The data pid of buffer 0.</description>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>RESET</name>
+                        <description>Reset the buffer selector to buffer 0.</description>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>STALL</name>
+                        <description>Reply with a stall (valid for both buffers).</description>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>AVAILABLE_0</name>
+                        <description>Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LENGTH_0</name>
+                        <description>The length of the data in buffer 1.</description>
+                        <bitRange>[9:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>EP12_IN_BUFFER_CONTROL</name>
+                <addressOffset>0x000000e0</addressOffset>
+                <description>Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. 
+                    Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>FULL_1</name>
+                        <description>Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LAST_1</name>
+                        <description>Buffer 1 is the last buffer of the transfer.</description>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PID_1</name>
+                        <description>The data pid of buffer 1.</description>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DOUBLE_BUFFER_ISO_OFFSET</name>
+                        <description>The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. 
+                            For a non Isochronous endpoint the offset is always 64 bytes.</description>
+                        <bitRange>[28:27]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>128</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>256</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>512</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>1024</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>AVAILABLE_1</name>
+                        <description>Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LENGTH_1</name>
+                        <description>The length of the data in buffer 1.</description>
+                        <bitRange>[25:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>FULL_0</name>
+                        <description>Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LAST_0</name>
+                        <description>Buffer 0 is the last buffer of the transfer.</description>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PID_0</name>
+                        <description>The data pid of buffer 0.</description>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>RESET</name>
+                        <description>Reset the buffer selector to buffer 0.</description>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>STALL</name>
+                        <description>Reply with a stall (valid for both buffers).</description>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>AVAILABLE_0</name>
+                        <description>Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LENGTH_0</name>
+                        <description>The length of the data in buffer 1.</description>
+                        <bitRange>[9:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>EP12_OUT_BUFFER_CONTROL</name>
+                <addressOffset>0x000000e4</addressOffset>
+                <description>Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. 
+                    Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>FULL_1</name>
+                        <description>Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LAST_1</name>
+                        <description>Buffer 1 is the last buffer of the transfer.</description>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PID_1</name>
+                        <description>The data pid of buffer 1.</description>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DOUBLE_BUFFER_ISO_OFFSET</name>
+                        <description>The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. 
+                            For a non Isochronous endpoint the offset is always 64 bytes.</description>
+                        <bitRange>[28:27]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>128</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>256</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>512</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>1024</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>AVAILABLE_1</name>
+                        <description>Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LENGTH_1</name>
+                        <description>The length of the data in buffer 1.</description>
+                        <bitRange>[25:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>FULL_0</name>
+                        <description>Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LAST_0</name>
+                        <description>Buffer 0 is the last buffer of the transfer.</description>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PID_0</name>
+                        <description>The data pid of buffer 0.</description>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>RESET</name>
+                        <description>Reset the buffer selector to buffer 0.</description>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>STALL</name>
+                        <description>Reply with a stall (valid for both buffers).</description>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>AVAILABLE_0</name>
+                        <description>Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LENGTH_0</name>
+                        <description>The length of the data in buffer 1.</description>
+                        <bitRange>[9:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>EP13_IN_BUFFER_CONTROL</name>
+                <addressOffset>0x000000e8</addressOffset>
+                <description>Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. 
+                    Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>FULL_1</name>
+                        <description>Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LAST_1</name>
+                        <description>Buffer 1 is the last buffer of the transfer.</description>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PID_1</name>
+                        <description>The data pid of buffer 1.</description>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DOUBLE_BUFFER_ISO_OFFSET</name>
+                        <description>The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. 
+                            For a non Isochronous endpoint the offset is always 64 bytes.</description>
+                        <bitRange>[28:27]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>128</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>256</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>512</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>1024</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>AVAILABLE_1</name>
+                        <description>Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LENGTH_1</name>
+                        <description>The length of the data in buffer 1.</description>
+                        <bitRange>[25:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>FULL_0</name>
+                        <description>Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LAST_0</name>
+                        <description>Buffer 0 is the last buffer of the transfer.</description>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PID_0</name>
+                        <description>The data pid of buffer 0.</description>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>RESET</name>
+                        <description>Reset the buffer selector to buffer 0.</description>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>STALL</name>
+                        <description>Reply with a stall (valid for both buffers).</description>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>AVAILABLE_0</name>
+                        <description>Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LENGTH_0</name>
+                        <description>The length of the data in buffer 1.</description>
+                        <bitRange>[9:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>EP13_OUT_BUFFER_CONTROL</name>
+                <addressOffset>0x000000ec</addressOffset>
+                <description>Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. 
+                    Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>FULL_1</name>
+                        <description>Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LAST_1</name>
+                        <description>Buffer 1 is the last buffer of the transfer.</description>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PID_1</name>
+                        <description>The data pid of buffer 1.</description>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DOUBLE_BUFFER_ISO_OFFSET</name>
+                        <description>The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. 
+                            For a non Isochronous endpoint the offset is always 64 bytes.</description>
+                        <bitRange>[28:27]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>128</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>256</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>512</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>1024</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>AVAILABLE_1</name>
+                        <description>Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LENGTH_1</name>
+                        <description>The length of the data in buffer 1.</description>
+                        <bitRange>[25:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>FULL_0</name>
+                        <description>Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LAST_0</name>
+                        <description>Buffer 0 is the last buffer of the transfer.</description>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PID_0</name>
+                        <description>The data pid of buffer 0.</description>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>RESET</name>
+                        <description>Reset the buffer selector to buffer 0.</description>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>STALL</name>
+                        <description>Reply with a stall (valid for both buffers).</description>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>AVAILABLE_0</name>
+                        <description>Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LENGTH_0</name>
+                        <description>The length of the data in buffer 1.</description>
+                        <bitRange>[9:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>EP14_IN_BUFFER_CONTROL</name>
+                <addressOffset>0x000000f0</addressOffset>
+                <description>Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. 
+                    Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>FULL_1</name>
+                        <description>Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LAST_1</name>
+                        <description>Buffer 1 is the last buffer of the transfer.</description>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PID_1</name>
+                        <description>The data pid of buffer 1.</description>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DOUBLE_BUFFER_ISO_OFFSET</name>
+                        <description>The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. 
+                            For a non Isochronous endpoint the offset is always 64 bytes.</description>
+                        <bitRange>[28:27]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>128</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>256</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>512</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>1024</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>AVAILABLE_1</name>
+                        <description>Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LENGTH_1</name>
+                        <description>The length of the data in buffer 1.</description>
+                        <bitRange>[25:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>FULL_0</name>
+                        <description>Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LAST_0</name>
+                        <description>Buffer 0 is the last buffer of the transfer.</description>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PID_0</name>
+                        <description>The data pid of buffer 0.</description>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>RESET</name>
+                        <description>Reset the buffer selector to buffer 0.</description>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>STALL</name>
+                        <description>Reply with a stall (valid for both buffers).</description>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>AVAILABLE_0</name>
+                        <description>Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LENGTH_0</name>
+                        <description>The length of the data in buffer 1.</description>
+                        <bitRange>[9:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>EP14_OUT_BUFFER_CONTROL</name>
+                <addressOffset>0x000000f4</addressOffset>
+                <description>Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. 
+                    Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>FULL_1</name>
+                        <description>Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LAST_1</name>
+                        <description>Buffer 1 is the last buffer of the transfer.</description>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PID_1</name>
+                        <description>The data pid of buffer 1.</description>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DOUBLE_BUFFER_ISO_OFFSET</name>
+                        <description>The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. 
+                            For a non Isochronous endpoint the offset is always 64 bytes.</description>
+                        <bitRange>[28:27]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>128</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>256</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>512</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>1024</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>AVAILABLE_1</name>
+                        <description>Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LENGTH_1</name>
+                        <description>The length of the data in buffer 1.</description>
+                        <bitRange>[25:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>FULL_0</name>
+                        <description>Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LAST_0</name>
+                        <description>Buffer 0 is the last buffer of the transfer.</description>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PID_0</name>
+                        <description>The data pid of buffer 0.</description>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>RESET</name>
+                        <description>Reset the buffer selector to buffer 0.</description>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>STALL</name>
+                        <description>Reply with a stall (valid for both buffers).</description>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>AVAILABLE_0</name>
+                        <description>Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LENGTH_0</name>
+                        <description>The length of the data in buffer 1.</description>
+                        <bitRange>[9:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>EP15_IN_BUFFER_CONTROL</name>
+                <addressOffset>0x000000f8</addressOffset>
+                <description>Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. 
+                    Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>FULL_1</name>
+                        <description>Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LAST_1</name>
+                        <description>Buffer 1 is the last buffer of the transfer.</description>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PID_1</name>
+                        <description>The data pid of buffer 1.</description>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DOUBLE_BUFFER_ISO_OFFSET</name>
+                        <description>The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. 
+                            For a non Isochronous endpoint the offset is always 64 bytes.</description>
+                        <bitRange>[28:27]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>128</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>256</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>512</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>1024</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>AVAILABLE_1</name>
+                        <description>Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LENGTH_1</name>
+                        <description>The length of the data in buffer 1.</description>
+                        <bitRange>[25:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>FULL_0</name>
+                        <description>Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LAST_0</name>
+                        <description>Buffer 0 is the last buffer of the transfer.</description>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PID_0</name>
+                        <description>The data pid of buffer 0.</description>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>RESET</name>
+                        <description>Reset the buffer selector to buffer 0.</description>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>STALL</name>
+                        <description>Reply with a stall (valid for both buffers).</description>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>AVAILABLE_0</name>
+                        <description>Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LENGTH_0</name>
+                        <description>The length of the data in buffer 1.</description>
+                        <bitRange>[9:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+            <register>
+                <name>EP15_OUT_BUFFER_CONTROL</name>
+                <addressOffset>0x000000fc</addressOffset>
+                <description>Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. 
+                    Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.</description>
+                <resetValue>0x00000000</resetValue>
+                <fields>
+                    <field>
+                        <name>FULL_1</name>
+                        <description>Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+                        <bitRange>[31:31]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LAST_1</name>
+                        <description>Buffer 1 is the last buffer of the transfer.</description>
+                        <bitRange>[30:30]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PID_1</name>
+                        <description>The data pid of buffer 1.</description>
+                        <bitRange>[29:29]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>DOUBLE_BUFFER_ISO_OFFSET</name>
+                        <description>The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. 
+                            For a non Isochronous endpoint the offset is always 64 bytes.</description>
+                        <bitRange>[28:27]</bitRange>
+                        <access>read-write</access>
+                        <enumeratedValues>
+                            <enumeratedValue>
+                                <name>128</name>
+                                <value>0</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>256</name>
+                                <value>1</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>512</name>
+                                <value>2</value>
+                            </enumeratedValue>
+                            <enumeratedValue>
+                                <name>1024</name>
+                                <value>3</value>
+                            </enumeratedValue>
+                        </enumeratedValues>
+                    </field>
+                    <field>
+                        <name>AVAILABLE_1</name>
+                        <description>Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+                        <bitRange>[26:26]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LENGTH_1</name>
+                        <description>The length of the data in buffer 1.</description>
+                        <bitRange>[25:16]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>FULL_0</name>
+                        <description>Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+                        <bitRange>[15:15]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LAST_0</name>
+                        <description>Buffer 0 is the last buffer of the transfer.</description>
+                        <bitRange>[14:14]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>PID_0</name>
+                        <description>The data pid of buffer 0.</description>
+                        <bitRange>[13:13]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>RESET</name>
+                        <description>Reset the buffer selector to buffer 0.</description>
+                        <bitRange>[12:12]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>STALL</name>
+                        <description>Reply with a stall (valid for both buffers).</description>
+                        <bitRange>[11:11]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>AVAILABLE_0</name>
+                        <description>Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+                        <bitRange>[10:10]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                    <field>
+                        <name>LENGTH_0</name>
+                        <description>The length of the data in buffer 1.</description>
+                        <bitRange>[9:0]</bitRange>
+                        <access>read-write</access>
+                    </field>
+                </fields>
+            </register>
+        </registers>
+    </peripheral>
+    <peripheral>
+      <name>SWI_IRQ</name>
+      <description>Virtual Peripheral to access unused NVIC software interrupts</description>
+      <baseAddress>0</baseAddress>
+      <registers></registers>
+      <interrupt>
+        <name>SWI_IRQ_0</name>
+        <value>47</value>
+      </interrupt>
+      <interrupt>
+        <name>SWI_IRQ_1</name>
+        <value>48</value>
+      </interrupt>
+      <interrupt>
+        <name>SWI_IRQ_2</name>
+        <value>49</value>
+      </interrupt>
+      <interrupt>
+        <name>SWI_IRQ_3</name>
+        <value>50</value>
+      </interrupt>
+      <interrupt>
+        <name>SWI_IRQ_4</name>
+        <value>51</value>
+      </interrupt>
+      <interrupt>
+        <name>SWI_IRQ_5</name>
+        <value>52</value>
+      </interrupt>
+    </peripheral>
+    </peripherals>
+</device>
diff --git a/svd/rp2040.svd b/svd/rp2040.svd
deleted file mode 100644
index 22f8ba8e..00000000
--- a/svd/rp2040.svd
+++ /dev/null
@@ -1,46417 +0,0 @@
-<?xml version="1.0" encoding="utf-8"?>
-<!--
-  Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
-
-  SPDX-License-Identifier: BSD-3-Clause
--->
-<device schemaVersion="1.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD.xsd">
-  <addressUnitBits>8</addressUnitBits>
-  <vendor>Raspberry Pi</vendor>
-  <name>RP2040</name>
-  <licenseText>
-    Copyright (c) 2020 Raspberry Pi (Trading) Ltd. \n
-    \n
-    SPDX-License-Identifier: BSD-3-Clause
-  </licenseText>
-  <version>0.1</version>
-  <width>32</width>
-  <cpu>
-    <name>CM0PLUS</name>
-    <revision>r0p1</revision>
-    <endian>little</endian>
-    <mpuPresent>true</mpuPresent>
-    <fpuPresent>false</fpuPresent>
-    <nvicPrioBits>2</nvicPrioBits>
-    <vtorPresent>1</vtorPresent>
-    <vendorSystickConfig>false</vendorSystickConfig>
-    <deviceNumInterrupts>26</deviceNumInterrupts>
-  </cpu>
-  <peripherals>
-    <peripheral>
-      <addressBlock>
-        <offset>0</offset>
-        <size>0x0020</size>
-        <usage>registers</usage>
-      </addressBlock>
-      <baseAddress>0x14000000</baseAddress>
-      <description>QSPI flash execute-in-place block</description>
-      <interrupt>
-        <name>XIP_IRQ</name>
-        <value>6</value>
-      </interrupt>
-      <name>XIP_CTRL</name>
-      <registers>
-        <register>
-          <addressOffset>0x0000</addressOffset>
-          <description>Cache control</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[3:3]</bitRange>
-              <description>When 1, the cache memories are powered down. They retain state,\n
-                but can not be accessed. This reduces static power dissipation.\n
-                Writing 1 to this bit forces CTRL_EN to 0, i.e. the cache cannot\n
-                be enabled when powered down.\n
-                Cache-as-SRAM accesses will produce a bus error response when\n
-                the cache is powered down.</description>
-              <name>POWER_DOWN</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[1:1]</bitRange>
-              <description>When 1, writes to any alias other than 0x0 (caching, allocating)\n
-                will produce a bus fault. When 0, these writes are silently ignored.\n
-                In either case, writes to the 0x0 alias will deallocate on tag match,\n
-                as usual.</description>
-              <name>ERR_BADWRITE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[0:0]</bitRange>
-              <description>When 1, enable the cache. When the cache is disabled, all XIP accesses\n
-                will go straight to the flash, without querying the cache. When enabled,\n
-                cacheable XIP accesses will query the cache, and the flash will\n
-                not be accessed if the tag matches and the valid bit is set.\n\n
-                If the cache is enabled, cache-as-SRAM accesses have no effect on the\n
-                cache data RAM, and will produce a bus error response.</description>
-              <name>EN</name>
-            </field>
-          </fields>
-          <name>CTRL</name>
-          <resetValue>0x00000003</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0004</addressOffset>
-          <description>Cache Flush control</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[0:0]</bitRange>
-              <description>Write 1 to flush the cache. This clears the tag memory, but\n
-                the data memory retains its contents. (This means cache-as-SRAM\n
-                contents is not affected by flush or reset.)\n
-                Reading will hold the bus (stall the processor) until the flush\n
-                completes. Alternatively STAT can be polled until completion.</description>
-              <modifiedWriteValues>clear</modifiedWriteValues>
-              <name>FLUSH</name>
-            </field>
-          </fields>
-          <name>FLUSH</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0008</addressOffset>
-          <description>Cache Status</description>
-          <fields>
-            <field>
-              <access>read-only</access>
-              <bitRange>[2:2]</bitRange>
-              <description>When 1, indicates the XIP streaming FIFO is completely full.\n
-                The streaming FIFO is 2 entries deep, so the full and empty\n
-                flag allow its level to be ascertained.</description>
-              <name>FIFO_FULL</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[1:1]</bitRange>
-              <description>When 1, indicates the XIP streaming FIFO is completely empty.</description>
-              <name>FIFO_EMPTY</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[0:0]</bitRange>
-              <description>Reads as 0 while a cache flush is in progress, and 1 otherwise.\n
-                The cache is flushed whenever the XIP block is reset, and also\n
-                when requested via the FLUSH register.</description>
-              <name>FLUSH_READY</name>
-            </field>
-          </fields>
-          <name>STAT</name>
-          <resetValue>0x00000002</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x000c</addressOffset>
-          <description>Cache Hit counter\n
-            A 32 bit saturating counter that increments upon each cache hit,\n
-            i.e. when an XIP access is serviced directly from cached data.\n
-            Write any value to clear.</description>
-          <modifiedWriteValues>oneToClear</modifiedWriteValues>
-          <name>CTR_HIT</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x0010</addressOffset>
-          <description>Cache Access counter\n
-            A 32 bit saturating counter that increments upon each XIP access,\n
-            whether the cache is hit or not. This includes noncacheable accesses.\n
-            Write any value to clear.</description>
-          <modifiedWriteValues>oneToClear</modifiedWriteValues>
-          <name>CTR_ACC</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0014</addressOffset>
-          <description>FIFO stream address</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[31:2]</bitRange>
-              <description>The address of the next word to be streamed from flash to the streaming FIFO.\n
-                Increments automatically after each flash access.\n
-                Write the initial access address here before starting a streaming read.</description>
-              <name>STREAM_ADDR</name>
-            </field>
-          </fields>
-          <name>STREAM_ADDR</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0018</addressOffset>
-          <description>FIFO stream control</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[21:0]</bitRange>
-              <description>Write a nonzero value to start a streaming read. This will then\n
-                progress in the background, using flash idle cycles to transfer\n
-                a linear data block from flash to the streaming FIFO.\n
-                Decrements automatically (1 at a time) as the stream\n
-                progresses, and halts on reaching 0.\n
-                Write 0 to halt an in-progress stream, and discard any in-flight\n
-                read, so that a new stream can immediately be started (after\n
-                draining the FIFO and reinitialising STREAM_ADDR)</description>
-              <name>STREAM_CTR</name>
-            </field>
-          </fields>
-          <name>STREAM_CTR</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-only</access>
-          <addressOffset>0x001c</addressOffset>
-          <description>FIFO stream data\n
-            Streamed data is buffered here, for retrieval by the system DMA.\n
-            This FIFO can also be accessed via the XIP_AUX slave, to avoid exposing\n
-            the DMA to bus stalls caused by other XIP traffic.</description>
-          <name>STREAM_FIFO</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-      </registers>
-      <size>32</size>
-      <version>1</version>
-    </peripheral>
-    <peripheral>
-      <addressBlock>
-        <offset>0</offset>
-        <size>0x0100</size>
-        <usage>registers</usage>
-      </addressBlock>
-      <baseAddress>0x18000000</baseAddress>
-      <description>DW_apb_ssi has the following features:\n
-        * APB interface – Allows for easy integration into a DesignWare Synthesizable Components for AMBA 2 implementation.\n
-        * APB3 and APB4 protocol support.\n
-        * Scalable APB data bus width – Supports APB data bus widths of 8, 16, and 32 bits.\n
-        * Serial-master or serial-slave operation – Enables serial communication with serial-master or serial-slave peripheral devices.\n
-        * Programmable Dual/Quad/Octal SPI support in Master Mode.\n
-        * Dual Data Rate (DDR) and Read Data Strobe (RDS) Support - Enables the DW_apb_ssi master to perform operations with the device in DDR and RDS modes when working in Dual/Quad/Octal mode of operation.\n
-        * Data Mask Support - Enables the DW_apb_ssi to selectively update the bytes in the device. This feature is applicable only in enhanced SPI modes.\n
-        * eXecute-In-Place (XIP) support - Enables the DW_apb_ssi master to behave as a memory mapped I/O and fetches the data from the device based on the APB read request. This feature is applicable only in enhanced SPI modes.\n
-        * DMA Controller Interface – Enables the DW_apb_ssi to interface to a DMA controller over the bus using a handshaking interface for transfer requests.\n
-        * Independent masking of interrupts – Master collision, transmit FIFO overflow, transmit FIFO empty, receive FIFO full, receive FIFO underflow, and receive FIFO overflow interrupts can all be masked independently.\n
-        * Multi-master contention detection – Informs the processor of multiple serial-master accesses on the serial bus.\n
-        * Bypass of meta-stability flip-flops for synchronous clocks – When the APB clock (pclk) and the DW_apb_ssi serial clock (ssi_clk) are synchronous, meta-stable flip-flops are not used when transferring control signals across these clock domains.\n
-        * Programmable delay on the sample time of the received serial data bit (rxd); enables programmable control of routing delays resulting in higher serial data-bit rates.\n
-        * Programmable features:\n
-        - Serial interface operation – Choice of Motorola SPI, Texas Instruments Synchronous Serial Protocol or National Semiconductor Microwire.\n
-        - Clock bit-rate – Dynamic control of the serial bit rate of the data transfer; used in only serial-master mode of operation.\n
-        - Data Item size (4 to 32 bits) – Item size of each data transfer under the control of the programmer.\n
-        * Configured features:\n
-        - FIFO depth – 16 words deep. The FIFO width is fixed at 32 bits.\n
-        - 1 slave select output.\n
-        - Hardware slave-select – Dedicated hardware slave-select line.\n
-        - Combined interrupt line - one combined interrupt line from the DW_apb_ssi to the interrupt controller.\n
-        - Interrupt polarity – active high interrupt lines.\n
-        - Serial clock polarity – low serial-clock polarity directly after reset.\n
-        - Serial clock phase – capture on first edge of serial-clock directly after reset.</description>
-      <name>XIP_SSI</name>
-      <registers>
-        <register>
-          <addressOffset>0x0000</addressOffset>
-          <description>Control register 0</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[24:24]</bitRange>
-              <description>Slave select toggle enable</description>
-              <name>SSTE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[22:21]</bitRange>
-              <description>SPI frame format</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>Standard 1-bit SPI frame format; 1 bit per SCK, full-duplex</description>
-                  <name>STD</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>Dual-SPI frame format; two bits per SCK, half-duplex</description>
-                  <name>DUAL</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>Quad-SPI frame format; four bits per SCK, half-duplex</description>
-                  <name>QUAD</name>
-                  <value>2</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>SPI_FRF</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[20:16]</bitRange>
-              <description>Data frame size in 32b transfer mode\n
-                Value of n -&gt; n+1 clocks per frame.</description>
-              <name>DFS_32</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[15:12]</bitRange>
-              <description>Control frame size\n
-                Value of n -&gt; n+1 clocks per frame.</description>
-              <name>CFS</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[11:11]</bitRange>
-              <description>Shift register loop (test mode)</description>
-              <name>SRL</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[10:10]</bitRange>
-              <description>Slave output enable</description>
-              <name>SLV_OE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[9:8]</bitRange>
-              <description>Transfer mode</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>Both transmit and receive</description>
-                  <name>TX_AND_RX</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>Transmit only (not for FRF == 0, standard SPI mode)</description>
-                  <name>TX_ONLY</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>Receive only (not for FRF == 0, standard SPI mode)</description>
-                  <name>RX_ONLY</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>EEPROM read mode (TX then RX; RX starts after control data TX'd)</description>
-                  <name>EEPROM_READ</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>TMOD</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[7:7]</bitRange>
-              <description>Serial clock polarity</description>
-              <name>SCPOL</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[6:6]</bitRange>
-              <description>Serial clock phase</description>
-              <name>SCPH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[5:4]</bitRange>
-              <description>Frame format</description>
-              <name>FRF</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[3:0]</bitRange>
-              <description>Data frame size</description>
-              <name>DFS</name>
-            </field>
-          </fields>
-          <name>CTRLR0</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0004</addressOffset>
-          <description>Master Control register 1</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[15:0]</bitRange>
-              <description>Number of data frames</description>
-              <name>NDF</name>
-            </field>
-          </fields>
-          <name>CTRLR1</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0008</addressOffset>
-          <description>SSI Enable</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[0:0]</bitRange>
-              <description>SSI enable</description>
-              <name>SSI_EN</name>
-            </field>
-          </fields>
-          <name>SSIENR</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x000c</addressOffset>
-          <description>Microwire Control</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[2:2]</bitRange>
-              <description>Microwire handshaking</description>
-              <name>MHS</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[1:1]</bitRange>
-              <description>Microwire control</description>
-              <name>MDD</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[0:0]</bitRange>
-              <description>Microwire transfer mode</description>
-              <name>MWMOD</name>
-            </field>
-          </fields>
-          <name>MWCR</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0010</addressOffset>
-          <description>Slave enable</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[0:0]</bitRange>
-              <description>For each bit:\n
-                0 -&gt; slave not selected\n
-                1 -&gt; slave selected</description>
-              <name>SER</name>
-            </field>
-          </fields>
-          <name>SER</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0014</addressOffset>
-          <description>Baud rate</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[15:0]</bitRange>
-              <description>SSI clock divider</description>
-              <name>SCKDV</name>
-            </field>
-          </fields>
-          <name>BAUDR</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0018</addressOffset>
-          <description>TX FIFO threshold level</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[7:0]</bitRange>
-              <description>Transmit FIFO threshold</description>
-              <name>TFT</name>
-            </field>
-          </fields>
-          <name>TXFTLR</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x001c</addressOffset>
-          <description>RX FIFO threshold level</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[7:0]</bitRange>
-              <description>Receive FIFO threshold</description>
-              <name>RFT</name>
-            </field>
-          </fields>
-          <name>RXFTLR</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0020</addressOffset>
-          <description>TX FIFO level</description>
-          <fields>
-            <field>
-              <access>read-only</access>
-              <bitRange>[7:0]</bitRange>
-              <description>Transmit FIFO level</description>
-              <name>TFTFL</name>
-            </field>
-          </fields>
-          <name>TXFLR</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0024</addressOffset>
-          <description>RX FIFO level</description>
-          <fields>
-            <field>
-              <access>read-only</access>
-              <bitRange>[7:0]</bitRange>
-              <description>Receive FIFO level</description>
-              <name>RXTFL</name>
-            </field>
-          </fields>
-          <name>RXFLR</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0028</addressOffset>
-          <description>Status register</description>
-          <fields>
-            <field>
-              <access>read-only</access>
-              <bitRange>[6:6]</bitRange>
-              <description>Data collision error</description>
-              <name>DCOL</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[5:5]</bitRange>
-              <description>Transmission error</description>
-              <name>TXE</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[4:4]</bitRange>
-              <description>Receive FIFO full</description>
-              <name>RFF</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[3:3]</bitRange>
-              <description>Receive FIFO not empty</description>
-              <name>RFNE</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[2:2]</bitRange>
-              <description>Transmit FIFO empty</description>
-              <name>TFE</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[1:1]</bitRange>
-              <description>Transmit FIFO not full</description>
-              <name>TFNF</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[0:0]</bitRange>
-              <description>SSI busy flag</description>
-              <name>BUSY</name>
-            </field>
-          </fields>
-          <name>SR</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x002c</addressOffset>
-          <description>Interrupt mask</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[5:5]</bitRange>
-              <description>Multi-master contention interrupt mask</description>
-              <name>MSTIM</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[4:4]</bitRange>
-              <description>Receive FIFO full interrupt mask</description>
-              <name>RXFIM</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[3:3]</bitRange>
-              <description>Receive FIFO overflow interrupt mask</description>
-              <name>RXOIM</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[2:2]</bitRange>
-              <description>Receive FIFO underflow interrupt mask</description>
-              <name>RXUIM</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[1:1]</bitRange>
-              <description>Transmit FIFO overflow interrupt mask</description>
-              <name>TXOIM</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[0:0]</bitRange>
-              <description>Transmit FIFO empty interrupt mask</description>
-              <name>TXEIM</name>
-            </field>
-          </fields>
-          <name>IMR</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0030</addressOffset>
-          <description>Interrupt status</description>
-          <fields>
-            <field>
-              <access>read-only</access>
-              <bitRange>[5:5]</bitRange>
-              <description>Multi-master contention interrupt status</description>
-              <name>MSTIS</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[4:4]</bitRange>
-              <description>Receive FIFO full interrupt status</description>
-              <name>RXFIS</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[3:3]</bitRange>
-              <description>Receive FIFO overflow interrupt status</description>
-              <name>RXOIS</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[2:2]</bitRange>
-              <description>Receive FIFO underflow interrupt status</description>
-              <name>RXUIS</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[1:1]</bitRange>
-              <description>Transmit FIFO overflow interrupt status</description>
-              <name>TXOIS</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[0:0]</bitRange>
-              <description>Transmit FIFO empty interrupt status</description>
-              <name>TXEIS</name>
-            </field>
-          </fields>
-          <name>ISR</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0034</addressOffset>
-          <description>Raw interrupt status</description>
-          <fields>
-            <field>
-              <access>read-only</access>
-              <bitRange>[5:5]</bitRange>
-              <description>Multi-master contention raw interrupt status</description>
-              <name>MSTIR</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[4:4]</bitRange>
-              <description>Receive FIFO full raw interrupt status</description>
-              <name>RXFIR</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[3:3]</bitRange>
-              <description>Receive FIFO overflow raw interrupt status</description>
-              <name>RXOIR</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[2:2]</bitRange>
-              <description>Receive FIFO underflow raw interrupt status</description>
-              <name>RXUIR</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[1:1]</bitRange>
-              <description>Transmit FIFO overflow raw interrupt status</description>
-              <name>TXOIR</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[0:0]</bitRange>
-              <description>Transmit FIFO empty raw interrupt status</description>
-              <name>TXEIR</name>
-            </field>
-          </fields>
-          <name>RISR</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0038</addressOffset>
-          <description>TX FIFO overflow interrupt clear</description>
-          <fields>
-            <field>
-              <access>read-only</access>
-              <bitRange>[0:0]</bitRange>
-              <description>Clear-on-read transmit FIFO overflow interrupt</description>
-              <name>TXOICR</name>
-            </field>
-          </fields>
-          <name>TXOICR</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x003c</addressOffset>
-          <description>RX FIFO overflow interrupt clear</description>
-          <fields>
-            <field>
-              <access>read-only</access>
-              <bitRange>[0:0]</bitRange>
-              <description>Clear-on-read receive FIFO overflow interrupt</description>
-              <name>RXOICR</name>
-            </field>
-          </fields>
-          <name>RXOICR</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0040</addressOffset>
-          <description>RX FIFO underflow interrupt clear</description>
-          <fields>
-            <field>
-              <access>read-only</access>
-              <bitRange>[0:0]</bitRange>
-              <description>Clear-on-read receive FIFO underflow interrupt</description>
-              <name>RXUICR</name>
-            </field>
-          </fields>
-          <name>RXUICR</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0044</addressOffset>
-          <description>Multi-master interrupt clear</description>
-          <fields>
-            <field>
-              <access>read-only</access>
-              <bitRange>[0:0]</bitRange>
-              <description>Clear-on-read multi-master contention interrupt</description>
-              <name>MSTICR</name>
-            </field>
-          </fields>
-          <name>MSTICR</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0048</addressOffset>
-          <description>Interrupt clear</description>
-          <fields>
-            <field>
-              <access>read-only</access>
-              <bitRange>[0:0]</bitRange>
-              <description>Clear-on-read all active interrupts</description>
-              <name>ICR</name>
-            </field>
-          </fields>
-          <name>ICR</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x004c</addressOffset>
-          <description>DMA control</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[1:1]</bitRange>
-              <description>Transmit DMA enable</description>
-              <name>TDMAE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[0:0]</bitRange>
-              <description>Receive DMA enable</description>
-              <name>RDMAE</name>
-            </field>
-          </fields>
-          <name>DMACR</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0050</addressOffset>
-          <description>DMA TX data level</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[7:0]</bitRange>
-              <description>Transmit data watermark level</description>
-              <name>DMATDL</name>
-            </field>
-          </fields>
-          <name>DMATDLR</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0054</addressOffset>
-          <description>DMA RX data level</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[7:0]</bitRange>
-              <description>Receive data watermark level (DMARDLR+1)</description>
-              <name>DMARDL</name>
-            </field>
-          </fields>
-          <name>DMARDLR</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0058</addressOffset>
-          <description>Identification register</description>
-          <fields>
-            <field>
-              <access>read-only</access>
-              <bitRange>[31:0]</bitRange>
-              <description>Peripheral dentification code</description>
-              <name>IDCODE</name>
-            </field>
-          </fields>
-          <name>IDR</name>
-          <resetValue>0x51535049</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x005c</addressOffset>
-          <description>Version ID</description>
-          <fields>
-            <field>
-              <access>read-only</access>
-              <bitRange>[31:0]</bitRange>
-              <description>SNPS component version (format X.YY)</description>
-              <name>SSI_COMP_VERSION</name>
-            </field>
-          </fields>
-          <name>SSI_VERSION_ID</name>
-          <resetValue>0x3430312a</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0060</addressOffset>
-          <description>Data Register 0 (of 36)</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[31:0]</bitRange>
-              <description>First data register of 36</description>
-              <name>DR</name>
-            </field>
-          </fields>
-          <name>DR0</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x00f0</addressOffset>
-          <description>RX sample delay</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[7:0]</bitRange>
-              <description>RXD sample delay (in SCLK cycles)</description>
-              <name>RSD</name>
-            </field>
-          </fields>
-          <name>RX_SAMPLE_DLY</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x00f4</addressOffset>
-          <description>SPI control</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[31:24]</bitRange>
-              <description>SPI Command to send in XIP mode (INST_L = 8-bit) or to append to Address (INST_L = 0-bit)</description>
-              <name>XIP_CMD</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[18:18]</bitRange>
-              <description>Read data strobe enable</description>
-              <name>SPI_RXDS_EN</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[17:17]</bitRange>
-              <description>Instruction DDR transfer enable</description>
-              <name>INST_DDR_EN</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[16:16]</bitRange>
-              <description>SPI DDR transfer enable</description>
-              <name>SPI_DDR_EN</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[15:11]</bitRange>
-              <description>Wait cycles between control frame transmit and data reception (in SCLK cycles)</description>
-              <name>WAIT_CYCLES</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[9:8]</bitRange>
-              <description>Instruction length (0/4/8/16b)</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>No instruction</description>
-                  <name>NONE</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>4-bit instruction</description>
-                  <name>4B</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>8-bit instruction</description>
-                  <name>8B</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>16-bit instruction</description>
-                  <name>16B</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>INST_L</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[5:2]</bitRange>
-              <description>Address length (0b-60b in 4b increments)</description>
-              <name>ADDR_L</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[1:0]</bitRange>
-              <description>Address and instruction transfer format</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>Command and address both in standard SPI frame format</description>
-                  <name>1C1A</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>Command in standard SPI format, address in format specified by FRF</description>
-                  <name>1C2A</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>Command and address both in format specified by FRF (e.g. Dual-SPI)</description>
-                  <name>2C2A</name>
-                  <value>2</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>TRANS_TYPE</name>
-            </field>
-          </fields>
-          <name>SPI_CTRLR0</name>
-          <resetValue>0x03000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x00f8</addressOffset>
-          <description>TX drive edge</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[7:0]</bitRange>
-              <description>TXD drive edge</description>
-              <name>TDE</name>
-            </field>
-          </fields>
-          <name>TXD_DRIVE_EDGE</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-      </registers>
-      <size>32</size>
-      <version>1</version>
-    </peripheral>
-    <peripheral>
-      <addressBlock>
-        <offset>0</offset>
-        <size>0x1000</size>
-        <usage>registers</usage>
-      </addressBlock>
-      <baseAddress>0x40000000</baseAddress>
-      <name>SYSINFO</name>
-      <registers>
-        <register>
-          <addressOffset>0x0000</addressOffset>
-          <description>JEDEC JEP-106 compliant chip identifier.</description>
-          <fields>
-            <field>
-              <access>read-only</access>
-              <bitRange>[31:28]</bitRange>
-              <name>REVISION</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[27:12]</bitRange>
-              <name>PART</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[11:0]</bitRange>
-              <name>MANUFACTURER</name>
-            </field>
-          </fields>
-          <name>CHIP_ID</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0004</addressOffset>
-          <description>Platform register. Allows software to know what environment it is running in.</description>
-          <fields>
-            <field>
-              <access>read-only</access>
-              <bitRange>[1:1]</bitRange>
-              <name>ASIC</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[0:0]</bitRange>
-              <name>FPGA</name>
-            </field>
-          </fields>
-          <name>PLATFORM</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-only</access>
-          <addressOffset>0x0040</addressOffset>
-          <description>Git hash of the chip source. Used to identify chip version.</description>
-          <name>GITREF_RP2040</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-      </registers>
-      <size>32</size>
-      <version>1</version>
-    </peripheral>
-    <peripheral>
-      <addressBlock>
-        <offset>0</offset>
-        <size>0x1000</size>
-        <usage>registers</usage>
-      </addressBlock>
-      <baseAddress>0x40004000</baseAddress>
-      <description>Register block for various chip control signals</description>
-      <name>SYSCFG</name>
-      <registers>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x0000</addressOffset>
-          <description>Processor core 0 NMI source mask\n
-            Set a bit high to enable NMI from that IRQ</description>
-          <name>PROC0_NMI_MASK</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x0004</addressOffset>
-          <description>Processor core 1 NMI source mask\n
-            Set a bit high to enable NMI from that IRQ</description>
-          <name>PROC1_NMI_MASK</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0008</addressOffset>
-          <description>Configuration for processors</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[31:28]</bitRange>
-              <description>Configure proc1 DAP instance ID.\n
-                Recommend that this is NOT changed until you require debug access in multi-chip environment\n
-                WARNING: do not set to 15 as this is reserved for RescueDP</description>
-              <name>PROC1_DAP_INSTID</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[27:24]</bitRange>
-              <description>Configure proc0 DAP instance ID.\n
-                Recommend that this is NOT changed until you require debug access in multi-chip environment\n
-                WARNING: do not set to 15 as this is reserved for RescueDP</description>
-              <name>PROC0_DAP_INSTID</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[1:1]</bitRange>
-              <description>Indication that proc1 has halted</description>
-              <name>PROC1_HALTED</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[0:0]</bitRange>
-              <description>Indication that proc0 has halted</description>
-              <name>PROC0_HALTED</name>
-            </field>
-          </fields>
-          <name>PROC_CONFIG</name>
-          <resetValue>0x10000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x000c</addressOffset>
-          <description>For each bit, if 1, bypass the input synchronizer between that GPIO\n
-            and the GPIO input register in the SIO. The input synchronizers should\n
-            generally be unbypassed, to avoid injecting metastabilities into processors.\n
-            If you're feeling brave, you can bypass to save two cycles of input\n
-            latency. This register applies to GPIO 0...29.</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[29:0]</bitRange>
-              <name>PROC_IN_SYNC_BYPASS</name>
-            </field>
-          </fields>
-          <name>PROC_IN_SYNC_BYPASS</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0010</addressOffset>
-          <description>For each bit, if 1, bypass the input synchronizer between that GPIO\n
-            and the GPIO input register in the SIO. The input synchronizers should\n
-            generally be unbypassed, to avoid injecting metastabilities into processors.\n
-            If you're feeling brave, you can bypass to save two cycles of input\n
-            latency. This register applies to GPIO 30...35 (the QSPI IOs).</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[5:0]</bitRange>
-              <name>PROC_IN_SYNC_BYPASS_HI</name>
-            </field>
-          </fields>
-          <name>PROC_IN_SYNC_BYPASS_HI</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0014</addressOffset>
-          <description>Directly control the SWD debug port of either processor</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[7:7]</bitRange>
-              <description>Attach processor 1 debug port to syscfg controls, and disconnect it from external SWD pads.</description>
-              <name>PROC1_ATTACH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[6:6]</bitRange>
-              <description>Directly drive processor 1 SWCLK, if PROC1_ATTACH is set</description>
-              <name>PROC1_SWCLK</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[5:5]</bitRange>
-              <description>Directly drive processor 1 SWDIO input, if PROC1_ATTACH is set</description>
-              <name>PROC1_SWDI</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[4:4]</bitRange>
-              <description>Observe the value of processor 1 SWDIO output.</description>
-              <name>PROC1_SWDO</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[3:3]</bitRange>
-              <description>Attach processor 0 debug port to syscfg controls, and disconnect it from external SWD pads.</description>
-              <name>PROC0_ATTACH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[2:2]</bitRange>
-              <description>Directly drive processor 0 SWCLK, if PROC0_ATTACH is set</description>
-              <name>PROC0_SWCLK</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[1:1]</bitRange>
-              <description>Directly drive processor 0 SWDIO input, if PROC0_ATTACH is set</description>
-              <name>PROC0_SWDI</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[0:0]</bitRange>
-              <description>Observe the value of processor 0 SWDIO output.</description>
-              <name>PROC0_SWDO</name>
-            </field>
-          </fields>
-          <name>DBGFORCE</name>
-          <resetValue>0x00000066</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0018</addressOffset>
-          <description>Control power downs to memories. Set high to power down memories.\n
-            Use with extreme caution</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[7:7]</bitRange>
-              <name>ROM</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[6:6]</bitRange>
-              <name>USB</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[5:5]</bitRange>
-              <name>SRAM5</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[4:4]</bitRange>
-              <name>SRAM4</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[3:3]</bitRange>
-              <name>SRAM3</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[2:2]</bitRange>
-              <name>SRAM2</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[1:1]</bitRange>
-              <name>SRAM1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[0:0]</bitRange>
-              <name>SRAM0</name>
-            </field>
-          </fields>
-          <name>MEMPOWERDOWN</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-      </registers>
-      <size>32</size>
-      <version>1</version>
-    </peripheral>
-    <peripheral>
-      <addressBlock>
-        <offset>0</offset>
-        <size>0x1000</size>
-        <usage>registers</usage>
-      </addressBlock>
-      <baseAddress>0x40008000</baseAddress>
-      <interrupt>
-        <name>CLOCKS_IRQ</name>
-        <value>17</value>
-      </interrupt>
-      <name>CLOCKS</name>
-      <registers>
-        <register>
-          <addressOffset>0x0000</addressOffset>
-          <description>Clock control, can be changed on-the-fly (except for auxsrc)</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[20:20]</bitRange>
-              <description>An edge on this signal shifts the phase of the output by 1 cycle of the input clock\n
-                This can be done at any time</description>
-              <name>NUDGE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[17:16]</bitRange>
-              <description>This delays the enable signal by up to 3 cycles of the input clock\n
-                This must be set before the clock is enabled to have any effect</description>
-              <name>PHASE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[12:12]</bitRange>
-              <description>Enables duty cycle correction for odd divisors</description>
-              <name>DC50</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[11:11]</bitRange>
-              <description>Starts and stops the clock generator cleanly</description>
-              <name>ENABLE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[10:10]</bitRange>
-              <description>Asynchronously kills the clock generator</description>
-              <name>KILL</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[8:5]</bitRange>
-              <description>Selects the auxiliary clock source, will glitch when switching</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>clksrc_pll_sys</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>clksrc_gpin0</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>clksrc_gpin1</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>clksrc_pll_usb</name>
-                  <value>3</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>rosc_clksrc</name>
-                  <value>4</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>xosc_clksrc</name>
-                  <value>5</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>clk_sys</name>
-                  <value>6</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>clk_usb</name>
-                  <value>7</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>clk_adc</name>
-                  <value>8</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>clk_rtc</name>
-                  <value>9</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>clk_ref</name>
-                  <value>10</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>AUXSRC</name>
-            </field>
-          </fields>
-          <name>CLK_GPOUT0_CTRL</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0004</addressOffset>
-          <description>Clock divisor, can be changed on-the-fly</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[31:8]</bitRange>
-              <description>Integer component of the divisor, 0 -&gt; divide by 2^16</description>
-              <name>INT</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[7:0]</bitRange>
-              <description>Fractional component of the divisor</description>
-              <name>FRAC</name>
-            </field>
-          </fields>
-          <name>CLK_GPOUT0_DIV</name>
-          <resetValue>0x00000100</resetValue>
-        </register>
-        <register>
-          <access>read-only</access>
-          <addressOffset>0x0008</addressOffset>
-          <description>Indicates which SRC is currently selected by the glitchless mux (one-hot).\n
-            This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1.</description>
-          <name>CLK_GPOUT0_SELECTED</name>
-          <resetValue>0x00000001</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x000c</addressOffset>
-          <description>Clock control, can be changed on-the-fly (except for auxsrc)</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[20:20]</bitRange>
-              <description>An edge on this signal shifts the phase of the output by 1 cycle of the input clock\n
-                This can be done at any time</description>
-              <name>NUDGE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[17:16]</bitRange>
-              <description>This delays the enable signal by up to 3 cycles of the input clock\n
-                This must be set before the clock is enabled to have any effect</description>
-              <name>PHASE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[12:12]</bitRange>
-              <description>Enables duty cycle correction for odd divisors</description>
-              <name>DC50</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[11:11]</bitRange>
-              <description>Starts and stops the clock generator cleanly</description>
-              <name>ENABLE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[10:10]</bitRange>
-              <description>Asynchronously kills the clock generator</description>
-              <name>KILL</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[8:5]</bitRange>
-              <description>Selects the auxiliary clock source, will glitch when switching</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>clksrc_pll_sys</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>clksrc_gpin0</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>clksrc_gpin1</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>clksrc_pll_usb</name>
-                  <value>3</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>rosc_clksrc</name>
-                  <value>4</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>xosc_clksrc</name>
-                  <value>5</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>clk_sys</name>
-                  <value>6</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>clk_usb</name>
-                  <value>7</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>clk_adc</name>
-                  <value>8</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>clk_rtc</name>
-                  <value>9</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>clk_ref</name>
-                  <value>10</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>AUXSRC</name>
-            </field>
-          </fields>
-          <name>CLK_GPOUT1_CTRL</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0010</addressOffset>
-          <description>Clock divisor, can be changed on-the-fly</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[31:8]</bitRange>
-              <description>Integer component of the divisor, 0 -&gt; divide by 2^16</description>
-              <name>INT</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[7:0]</bitRange>
-              <description>Fractional component of the divisor</description>
-              <name>FRAC</name>
-            </field>
-          </fields>
-          <name>CLK_GPOUT1_DIV</name>
-          <resetValue>0x00000100</resetValue>
-        </register>
-        <register>
-          <access>read-only</access>
-          <addressOffset>0x0014</addressOffset>
-          <description>Indicates which SRC is currently selected by the glitchless mux (one-hot).\n
-            This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1.</description>
-          <name>CLK_GPOUT1_SELECTED</name>
-          <resetValue>0x00000001</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0018</addressOffset>
-          <description>Clock control, can be changed on-the-fly (except for auxsrc)</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[20:20]</bitRange>
-              <description>An edge on this signal shifts the phase of the output by 1 cycle of the input clock\n
-                This can be done at any time</description>
-              <name>NUDGE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[17:16]</bitRange>
-              <description>This delays the enable signal by up to 3 cycles of the input clock\n
-                This must be set before the clock is enabled to have any effect</description>
-              <name>PHASE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[12:12]</bitRange>
-              <description>Enables duty cycle correction for odd divisors</description>
-              <name>DC50</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[11:11]</bitRange>
-              <description>Starts and stops the clock generator cleanly</description>
-              <name>ENABLE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[10:10]</bitRange>
-              <description>Asynchronously kills the clock generator</description>
-              <name>KILL</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[8:5]</bitRange>
-              <description>Selects the auxiliary clock source, will glitch when switching</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>clksrc_pll_sys</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>clksrc_gpin0</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>clksrc_gpin1</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>clksrc_pll_usb</name>
-                  <value>3</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>rosc_clksrc_ph</name>
-                  <value>4</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>xosc_clksrc</name>
-                  <value>5</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>clk_sys</name>
-                  <value>6</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>clk_usb</name>
-                  <value>7</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>clk_adc</name>
-                  <value>8</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>clk_rtc</name>
-                  <value>9</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>clk_ref</name>
-                  <value>10</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>AUXSRC</name>
-            </field>
-          </fields>
-          <name>CLK_GPOUT2_CTRL</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x001c</addressOffset>
-          <description>Clock divisor, can be changed on-the-fly</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[31:8]</bitRange>
-              <description>Integer component of the divisor, 0 -&gt; divide by 2^16</description>
-              <name>INT</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[7:0]</bitRange>
-              <description>Fractional component of the divisor</description>
-              <name>FRAC</name>
-            </field>
-          </fields>
-          <name>CLK_GPOUT2_DIV</name>
-          <resetValue>0x00000100</resetValue>
-        </register>
-        <register>
-          <access>read-only</access>
-          <addressOffset>0x0020</addressOffset>
-          <description>Indicates which SRC is currently selected by the glitchless mux (one-hot).\n
-            This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1.</description>
-          <name>CLK_GPOUT2_SELECTED</name>
-          <resetValue>0x00000001</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0024</addressOffset>
-          <description>Clock control, can be changed on-the-fly (except for auxsrc)</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[20:20]</bitRange>
-              <description>An edge on this signal shifts the phase of the output by 1 cycle of the input clock\n
-                This can be done at any time</description>
-              <name>NUDGE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[17:16]</bitRange>
-              <description>This delays the enable signal by up to 3 cycles of the input clock\n
-                This must be set before the clock is enabled to have any effect</description>
-              <name>PHASE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[12:12]</bitRange>
-              <description>Enables duty cycle correction for odd divisors</description>
-              <name>DC50</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[11:11]</bitRange>
-              <description>Starts and stops the clock generator cleanly</description>
-              <name>ENABLE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[10:10]</bitRange>
-              <description>Asynchronously kills the clock generator</description>
-              <name>KILL</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[8:5]</bitRange>
-              <description>Selects the auxiliary clock source, will glitch when switching</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>clksrc_pll_sys</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>clksrc_gpin0</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>clksrc_gpin1</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>clksrc_pll_usb</name>
-                  <value>3</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>rosc_clksrc_ph</name>
-                  <value>4</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>xosc_clksrc</name>
-                  <value>5</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>clk_sys</name>
-                  <value>6</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>clk_usb</name>
-                  <value>7</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>clk_adc</name>
-                  <value>8</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>clk_rtc</name>
-                  <value>9</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>clk_ref</name>
-                  <value>10</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>AUXSRC</name>
-            </field>
-          </fields>
-          <name>CLK_GPOUT3_CTRL</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0028</addressOffset>
-          <description>Clock divisor, can be changed on-the-fly</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[31:8]</bitRange>
-              <description>Integer component of the divisor, 0 -&gt; divide by 2^16</description>
-              <name>INT</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[7:0]</bitRange>
-              <description>Fractional component of the divisor</description>
-              <name>FRAC</name>
-            </field>
-          </fields>
-          <name>CLK_GPOUT3_DIV</name>
-          <resetValue>0x00000100</resetValue>
-        </register>
-        <register>
-          <access>read-only</access>
-          <addressOffset>0x002c</addressOffset>
-          <description>Indicates which SRC is currently selected by the glitchless mux (one-hot).\n
-            This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1.</description>
-          <name>CLK_GPOUT3_SELECTED</name>
-          <resetValue>0x00000001</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0030</addressOffset>
-          <description>Clock control, can be changed on-the-fly (except for auxsrc)</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[6:5]</bitRange>
-              <description>Selects the auxiliary clock source, will glitch when switching</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>clksrc_pll_usb</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>clksrc_gpin0</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>clksrc_gpin1</name>
-                  <value>2</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>AUXSRC</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[1:0]</bitRange>
-              <description>Selects the clock source glitchlessly, can be changed on-the-fly</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>rosc_clksrc_ph</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>clksrc_clk_ref_aux</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>xosc_clksrc</name>
-                  <value>2</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>SRC</name>
-            </field>
-          </fields>
-          <name>CLK_REF_CTRL</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0034</addressOffset>
-          <description>Clock divisor, can be changed on-the-fly</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[9:8]</bitRange>
-              <description>Integer component of the divisor, 0 -&gt; divide by 2^16</description>
-              <name>INT</name>
-            </field>
-          </fields>
-          <name>CLK_REF_DIV</name>
-          <resetValue>0x00000100</resetValue>
-        </register>
-        <register>
-          <access>read-only</access>
-          <addressOffset>0x0038</addressOffset>
-          <description>Indicates which SRC is currently selected by the glitchless mux (one-hot).\n
-            The glitchless multiplexer does not switch instantaneously (to avoid glitches), so software should poll this register to wait for the switch to complete. This register contains one decoded bit for each of the clock sources enumerated in the CTRL SRC field. At most one of these bits will be set at any time, indicating that clock is currently present at the output of the glitchless mux. Whilst switching is in progress, this register may briefly show all-0s.</description>
-          <name>CLK_REF_SELECTED</name>
-          <resetValue>0x00000001</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x003c</addressOffset>
-          <description>Clock control, can be changed on-the-fly (except for auxsrc)</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[7:5]</bitRange>
-              <description>Selects the auxiliary clock source, will glitch when switching</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>clksrc_pll_sys</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>clksrc_pll_usb</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>rosc_clksrc</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>xosc_clksrc</name>
-                  <value>3</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>clksrc_gpin0</name>
-                  <value>4</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>clksrc_gpin1</name>
-                  <value>5</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>AUXSRC</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[0:0]</bitRange>
-              <description>Selects the clock source glitchlessly, can be changed on-the-fly</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>clk_ref</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>clksrc_clk_sys_aux</name>
-                  <value>1</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>SRC</name>
-            </field>
-          </fields>
-          <name>CLK_SYS_CTRL</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0040</addressOffset>
-          <description>Clock divisor, can be changed on-the-fly</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[31:8]</bitRange>
-              <description>Integer component of the divisor, 0 -&gt; divide by 2^16</description>
-              <name>INT</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[7:0]</bitRange>
-              <description>Fractional component of the divisor</description>
-              <name>FRAC</name>
-            </field>
-          </fields>
-          <name>CLK_SYS_DIV</name>
-          <resetValue>0x00000100</resetValue>
-        </register>
-        <register>
-          <access>read-only</access>
-          <addressOffset>0x0044</addressOffset>
-          <description>Indicates which SRC is currently selected by the glitchless mux (one-hot).\n
-            The glitchless multiplexer does not switch instantaneously (to avoid glitches), so software should poll this register to wait for the switch to complete. This register contains one decoded bit for each of the clock sources enumerated in the CTRL SRC field. At most one of these bits will be set at any time, indicating that clock is currently present at the output of the glitchless mux. Whilst switching is in progress, this register may briefly show all-0s.</description>
-          <name>CLK_SYS_SELECTED</name>
-          <resetValue>0x00000001</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0048</addressOffset>
-          <description>Clock control, can be changed on-the-fly (except for auxsrc)</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[11:11]</bitRange>
-              <description>Starts and stops the clock generator cleanly</description>
-              <name>ENABLE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[10:10]</bitRange>
-              <description>Asynchronously kills the clock generator</description>
-              <name>KILL</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[7:5]</bitRange>
-              <description>Selects the auxiliary clock source, will glitch when switching</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>clk_sys</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>clksrc_pll_sys</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>clksrc_pll_usb</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>rosc_clksrc_ph</name>
-                  <value>3</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>xosc_clksrc</name>
-                  <value>4</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>clksrc_gpin0</name>
-                  <value>5</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>clksrc_gpin1</name>
-                  <value>6</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>AUXSRC</name>
-            </field>
-          </fields>
-          <name>CLK_PERI_CTRL</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-only</access>
-          <addressOffset>0x0050</addressOffset>
-          <description>Indicates which SRC is currently selected by the glitchless mux (one-hot).\n
-            This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1.</description>
-          <name>CLK_PERI_SELECTED</name>
-          <resetValue>0x00000001</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0054</addressOffset>
-          <description>Clock control, can be changed on-the-fly (except for auxsrc)</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[20:20]</bitRange>
-              <description>An edge on this signal shifts the phase of the output by 1 cycle of the input clock\n
-                This can be done at any time</description>
-              <name>NUDGE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[17:16]</bitRange>
-              <description>This delays the enable signal by up to 3 cycles of the input clock\n
-                This must be set before the clock is enabled to have any effect</description>
-              <name>PHASE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[11:11]</bitRange>
-              <description>Starts and stops the clock generator cleanly</description>
-              <name>ENABLE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[10:10]</bitRange>
-              <description>Asynchronously kills the clock generator</description>
-              <name>KILL</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[7:5]</bitRange>
-              <description>Selects the auxiliary clock source, will glitch when switching</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>clksrc_pll_usb</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>clksrc_pll_sys</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>rosc_clksrc_ph</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>xosc_clksrc</name>
-                  <value>3</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>clksrc_gpin0</name>
-                  <value>4</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>clksrc_gpin1</name>
-                  <value>5</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>AUXSRC</name>
-            </field>
-          </fields>
-          <name>CLK_USB_CTRL</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0058</addressOffset>
-          <description>Clock divisor, can be changed on-the-fly</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[9:8]</bitRange>
-              <description>Integer component of the divisor, 0 -&gt; divide by 2^16</description>
-              <name>INT</name>
-            </field>
-          </fields>
-          <name>CLK_USB_DIV</name>
-          <resetValue>0x00000100</resetValue>
-        </register>
-        <register>
-          <access>read-only</access>
-          <addressOffset>0x005c</addressOffset>
-          <description>Indicates which SRC is currently selected by the glitchless mux (one-hot).\n
-            This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1.</description>
-          <name>CLK_USB_SELECTED</name>
-          <resetValue>0x00000001</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0060</addressOffset>
-          <description>Clock control, can be changed on-the-fly (except for auxsrc)</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[20:20]</bitRange>
-              <description>An edge on this signal shifts the phase of the output by 1 cycle of the input clock\n
-                This can be done at any time</description>
-              <name>NUDGE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[17:16]</bitRange>
-              <description>This delays the enable signal by up to 3 cycles of the input clock\n
-                This must be set before the clock is enabled to have any effect</description>
-              <name>PHASE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[11:11]</bitRange>
-              <description>Starts and stops the clock generator cleanly</description>
-              <name>ENABLE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[10:10]</bitRange>
-              <description>Asynchronously kills the clock generator</description>
-              <name>KILL</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[7:5]</bitRange>
-              <description>Selects the auxiliary clock source, will glitch when switching</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>clksrc_pll_usb</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>clksrc_pll_sys</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>rosc_clksrc_ph</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>xosc_clksrc</name>
-                  <value>3</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>clksrc_gpin0</name>
-                  <value>4</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>clksrc_gpin1</name>
-                  <value>5</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>AUXSRC</name>
-            </field>
-          </fields>
-          <name>CLK_ADC_CTRL</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0064</addressOffset>
-          <description>Clock divisor, can be changed on-the-fly</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[9:8]</bitRange>
-              <description>Integer component of the divisor, 0 -&gt; divide by 2^16</description>
-              <name>INT</name>
-            </field>
-          </fields>
-          <name>CLK_ADC_DIV</name>
-          <resetValue>0x00000100</resetValue>
-        </register>
-        <register>
-          <access>read-only</access>
-          <addressOffset>0x0068</addressOffset>
-          <description>Indicates which SRC is currently selected by the glitchless mux (one-hot).\n
-            This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1.</description>
-          <name>CLK_ADC_SELECTED</name>
-          <resetValue>0x00000001</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x006c</addressOffset>
-          <description>Clock control, can be changed on-the-fly (except for auxsrc)</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[20:20]</bitRange>
-              <description>An edge on this signal shifts the phase of the output by 1 cycle of the input clock\n
-                This can be done at any time</description>
-              <name>NUDGE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[17:16]</bitRange>
-              <description>This delays the enable signal by up to 3 cycles of the input clock\n
-                This must be set before the clock is enabled to have any effect</description>
-              <name>PHASE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[11:11]</bitRange>
-              <description>Starts and stops the clock generator cleanly</description>
-              <name>ENABLE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[10:10]</bitRange>
-              <description>Asynchronously kills the clock generator</description>
-              <name>KILL</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[7:5]</bitRange>
-              <description>Selects the auxiliary clock source, will glitch when switching</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>clksrc_pll_usb</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>clksrc_pll_sys</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>rosc_clksrc_ph</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>xosc_clksrc</name>
-                  <value>3</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>clksrc_gpin0</name>
-                  <value>4</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>clksrc_gpin1</name>
-                  <value>5</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>AUXSRC</name>
-            </field>
-          </fields>
-          <name>CLK_RTC_CTRL</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0070</addressOffset>
-          <description>Clock divisor, can be changed on-the-fly</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[31:8]</bitRange>
-              <description>Integer component of the divisor, 0 -&gt; divide by 2^16</description>
-              <name>INT</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[7:0]</bitRange>
-              <description>Fractional component of the divisor</description>
-              <name>FRAC</name>
-            </field>
-          </fields>
-          <name>CLK_RTC_DIV</name>
-          <resetValue>0x00000100</resetValue>
-        </register>
-        <register>
-          <access>read-only</access>
-          <addressOffset>0x0074</addressOffset>
-          <description>Indicates which SRC is currently selected by the glitchless mux (one-hot).\n
-            This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1.</description>
-          <name>CLK_RTC_SELECTED</name>
-          <resetValue>0x00000001</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0078</addressOffset>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[16:16]</bitRange>
-              <description>For clearing the resus after the fault that triggered it has been corrected</description>
-              <name>CLEAR</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[12:12]</bitRange>
-              <description>Force a resus, for test purposes only</description>
-              <name>FRCE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[8:8]</bitRange>
-              <description>Enable resus</description>
-              <name>ENABLE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[7:0]</bitRange>
-              <description>This is expressed as a number of clk_ref cycles\n
-                and must be &gt;= 2x clk_ref_freq/min_clk_tst_freq</description>
-              <name>TIMEOUT</name>
-            </field>
-          </fields>
-          <name>CLK_SYS_RESUS_CTRL</name>
-          <resetValue>0x000000ff</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x007c</addressOffset>
-          <fields>
-            <field>
-              <access>read-only</access>
-              <bitRange>[0:0]</bitRange>
-              <description>Clock has been resuscitated, correct the error then send ctrl_clear=1</description>
-              <name>RESUSSED</name>
-            </field>
-          </fields>
-          <name>CLK_SYS_RESUS_STATUS</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0080</addressOffset>
-          <description>Reference clock frequency in kHz</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[19:0]</bitRange>
-              <name>FC0_REF_KHZ</name>
-            </field>
-          </fields>
-          <name>FC0_REF_KHZ</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0084</addressOffset>
-          <description>Minimum pass frequency in kHz. This is optional. Set to 0 if you are not using the pass/fail flags</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[24:0]</bitRange>
-              <name>FC0_MIN_KHZ</name>
-            </field>
-          </fields>
-          <name>FC0_MIN_KHZ</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0088</addressOffset>
-          <description>Maximum pass frequency in kHz. This is optional. Set to 0x1ffffff if you are not using the pass/fail flags</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[24:0]</bitRange>
-              <name>FC0_MAX_KHZ</name>
-            </field>
-          </fields>
-          <name>FC0_MAX_KHZ</name>
-          <resetValue>0x01ffffff</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x008c</addressOffset>
-          <description>Delays the start of frequency counting to allow the mux to settle\n
-            Delay is measured in multiples of the reference clock period</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[2:0]</bitRange>
-              <name>FC0_DELAY</name>
-            </field>
-          </fields>
-          <name>FC0_DELAY</name>
-          <resetValue>0x00000001</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0090</addressOffset>
-          <description>The test interval is 0.98us * 2**interval, but let's call it 1us * 2**interval\n
-            The default gives a test interval of 250us</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[3:0]</bitRange>
-              <name>FC0_INTERVAL</name>
-            </field>
-          </fields>
-          <name>FC0_INTERVAL</name>
-          <resetValue>0x00000008</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0094</addressOffset>
-          <description>Clock sent to frequency counter, set to 0 when not required\n
-            Writing to this register initiates the frequency count</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[7:0]</bitRange>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>NULL</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>pll_sys_clksrc_primary</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>pll_usb_clksrc_primary</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>rosc_clksrc</name>
-                  <value>3</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>rosc_clksrc_ph</name>
-                  <value>4</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>xosc_clksrc</name>
-                  <value>5</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>clksrc_gpin0</name>
-                  <value>6</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>clksrc_gpin1</name>
-                  <value>7</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>clk_ref</name>
-                  <value>8</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>clk_sys</name>
-                  <value>9</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>clk_peri</name>
-                  <value>10</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>clk_usb</name>
-                  <value>11</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>clk_adc</name>
-                  <value>12</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>clk_rtc</name>
-                  <value>13</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>FC0_SRC</name>
-            </field>
-          </fields>
-          <name>FC0_SRC</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0098</addressOffset>
-          <description>Frequency counter status</description>
-          <fields>
-            <field>
-              <access>read-only</access>
-              <bitRange>[28:28]</bitRange>
-              <description>Test clock stopped during test</description>
-              <name>DIED</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[24:24]</bitRange>
-              <description>Test clock faster than expected, only valid when status_done=1</description>
-              <name>FAST</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[20:20]</bitRange>
-              <description>Test clock slower than expected, only valid when status_done=1</description>
-              <name>SLOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[16:16]</bitRange>
-              <description>Test failed</description>
-              <name>FAIL</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[12:12]</bitRange>
-              <description>Waiting for test clock to start</description>
-              <name>WAITING</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[8:8]</bitRange>
-              <description>Test running</description>
-              <name>RUNNING</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[4:4]</bitRange>
-              <description>Test complete</description>
-              <name>DONE</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[0:0]</bitRange>
-              <description>Test passed</description>
-              <name>PASS</name>
-            </field>
-          </fields>
-          <name>FC0_STATUS</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x009c</addressOffset>
-          <description>Result of frequency measurement, only valid when status_done=1</description>
-          <fields>
-            <field>
-              <access>read-only</access>
-              <bitRange>[29:5]</bitRange>
-              <name>KHZ</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[4:0]</bitRange>
-              <name>FRAC</name>
-            </field>
-          </fields>
-          <name>FC0_RESULT</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x00a0</addressOffset>
-          <description>enable clock in wake mode</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[31:31]</bitRange>
-              <name>clk_sys_sram3</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[30:30]</bitRange>
-              <name>clk_sys_sram2</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[29:29]</bitRange>
-              <name>clk_sys_sram1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[28:28]</bitRange>
-              <name>clk_sys_sram0</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[27:27]</bitRange>
-              <name>clk_sys_spi1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[26:26]</bitRange>
-              <name>clk_peri_spi1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[25:25]</bitRange>
-              <name>clk_sys_spi0</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[24:24]</bitRange>
-              <name>clk_peri_spi0</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[23:23]</bitRange>
-              <name>clk_sys_sio</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[22:22]</bitRange>
-              <name>clk_sys_rtc</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[21:21]</bitRange>
-              <name>clk_rtc_rtc</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[20:20]</bitRange>
-              <name>clk_sys_rosc</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[19:19]</bitRange>
-              <name>clk_sys_rom</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[18:18]</bitRange>
-              <name>clk_sys_resets</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[17:17]</bitRange>
-              <name>clk_sys_pwm</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[16:16]</bitRange>
-              <name>clk_sys_psm</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[15:15]</bitRange>
-              <name>clk_sys_pll_usb</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[14:14]</bitRange>
-              <name>clk_sys_pll_sys</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[13:13]</bitRange>
-              <name>clk_sys_pio1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[12:12]</bitRange>
-              <name>clk_sys_pio0</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[11:11]</bitRange>
-              <name>clk_sys_pads</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[10:10]</bitRange>
-              <name>clk_sys_vreg_and_chip_reset</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[9:9]</bitRange>
-              <name>clk_sys_jtag</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[8:8]</bitRange>
-              <name>clk_sys_io</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[7:7]</bitRange>
-              <name>clk_sys_i2c1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[6:6]</bitRange>
-              <name>clk_sys_i2c0</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[5:5]</bitRange>
-              <name>clk_sys_dma</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[4:4]</bitRange>
-              <name>clk_sys_busfabric</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[3:3]</bitRange>
-              <name>clk_sys_busctrl</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[2:2]</bitRange>
-              <name>clk_sys_adc</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[1:1]</bitRange>
-              <name>clk_adc_adc</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[0:0]</bitRange>
-              <name>clk_sys_clocks</name>
-            </field>
-          </fields>
-          <name>WAKE_EN0</name>
-          <resetValue>0xffffffff</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x00a4</addressOffset>
-          <description>enable clock in wake mode</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[14:14]</bitRange>
-              <name>clk_sys_xosc</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[13:13]</bitRange>
-              <name>clk_sys_xip</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[12:12]</bitRange>
-              <name>clk_sys_watchdog</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[11:11]</bitRange>
-              <name>clk_usb_usbctrl</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[10:10]</bitRange>
-              <name>clk_sys_usbctrl</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[9:9]</bitRange>
-              <name>clk_sys_uart1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[8:8]</bitRange>
-              <name>clk_peri_uart1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[7:7]</bitRange>
-              <name>clk_sys_uart0</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[6:6]</bitRange>
-              <name>clk_peri_uart0</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[5:5]</bitRange>
-              <name>clk_sys_timer</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[4:4]</bitRange>
-              <name>clk_sys_tbman</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[3:3]</bitRange>
-              <name>clk_sys_sysinfo</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[2:2]</bitRange>
-              <name>clk_sys_syscfg</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[1:1]</bitRange>
-              <name>clk_sys_sram5</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[0:0]</bitRange>
-              <name>clk_sys_sram4</name>
-            </field>
-          </fields>
-          <name>WAKE_EN1</name>
-          <resetValue>0x00007fff</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x00a8</addressOffset>
-          <description>enable clock in sleep mode</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[31:31]</bitRange>
-              <name>clk_sys_sram3</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[30:30]</bitRange>
-              <name>clk_sys_sram2</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[29:29]</bitRange>
-              <name>clk_sys_sram1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[28:28]</bitRange>
-              <name>clk_sys_sram0</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[27:27]</bitRange>
-              <name>clk_sys_spi1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[26:26]</bitRange>
-              <name>clk_peri_spi1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[25:25]</bitRange>
-              <name>clk_sys_spi0</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[24:24]</bitRange>
-              <name>clk_peri_spi0</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[23:23]</bitRange>
-              <name>clk_sys_sio</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[22:22]</bitRange>
-              <name>clk_sys_rtc</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[21:21]</bitRange>
-              <name>clk_rtc_rtc</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[20:20]</bitRange>
-              <name>clk_sys_rosc</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[19:19]</bitRange>
-              <name>clk_sys_rom</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[18:18]</bitRange>
-              <name>clk_sys_resets</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[17:17]</bitRange>
-              <name>clk_sys_pwm</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[16:16]</bitRange>
-              <name>clk_sys_psm</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[15:15]</bitRange>
-              <name>clk_sys_pll_usb</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[14:14]</bitRange>
-              <name>clk_sys_pll_sys</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[13:13]</bitRange>
-              <name>clk_sys_pio1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[12:12]</bitRange>
-              <name>clk_sys_pio0</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[11:11]</bitRange>
-              <name>clk_sys_pads</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[10:10]</bitRange>
-              <name>clk_sys_vreg_and_chip_reset</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[9:9]</bitRange>
-              <name>clk_sys_jtag</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[8:8]</bitRange>
-              <name>clk_sys_io</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[7:7]</bitRange>
-              <name>clk_sys_i2c1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[6:6]</bitRange>
-              <name>clk_sys_i2c0</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[5:5]</bitRange>
-              <name>clk_sys_dma</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[4:4]</bitRange>
-              <name>clk_sys_busfabric</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[3:3]</bitRange>
-              <name>clk_sys_busctrl</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[2:2]</bitRange>
-              <name>clk_sys_adc</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[1:1]</bitRange>
-              <name>clk_adc_adc</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[0:0]</bitRange>
-              <name>clk_sys_clocks</name>
-            </field>
-          </fields>
-          <name>SLEEP_EN0</name>
-          <resetValue>0xffffffff</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x00ac</addressOffset>
-          <description>enable clock in sleep mode</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[14:14]</bitRange>
-              <name>clk_sys_xosc</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[13:13]</bitRange>
-              <name>clk_sys_xip</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[12:12]</bitRange>
-              <name>clk_sys_watchdog</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[11:11]</bitRange>
-              <name>clk_usb_usbctrl</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[10:10]</bitRange>
-              <name>clk_sys_usbctrl</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[9:9]</bitRange>
-              <name>clk_sys_uart1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[8:8]</bitRange>
-              <name>clk_peri_uart1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[7:7]</bitRange>
-              <name>clk_sys_uart0</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[6:6]</bitRange>
-              <name>clk_peri_uart0</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[5:5]</bitRange>
-              <name>clk_sys_timer</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[4:4]</bitRange>
-              <name>clk_sys_tbman</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[3:3]</bitRange>
-              <name>clk_sys_sysinfo</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[2:2]</bitRange>
-              <name>clk_sys_syscfg</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[1:1]</bitRange>
-              <name>clk_sys_sram5</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[0:0]</bitRange>
-              <name>clk_sys_sram4</name>
-            </field>
-          </fields>
-          <name>SLEEP_EN1</name>
-          <resetValue>0x00007fff</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x00b0</addressOffset>
-          <description>indicates the state of the clock enable</description>
-          <fields>
-            <field>
-              <access>read-only</access>
-              <bitRange>[31:31]</bitRange>
-              <name>clk_sys_sram3</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[30:30]</bitRange>
-              <name>clk_sys_sram2</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[29:29]</bitRange>
-              <name>clk_sys_sram1</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[28:28]</bitRange>
-              <name>clk_sys_sram0</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[27:27]</bitRange>
-              <name>clk_sys_spi1</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[26:26]</bitRange>
-              <name>clk_peri_spi1</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[25:25]</bitRange>
-              <name>clk_sys_spi0</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[24:24]</bitRange>
-              <name>clk_peri_spi0</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[23:23]</bitRange>
-              <name>clk_sys_sio</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[22:22]</bitRange>
-              <name>clk_sys_rtc</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[21:21]</bitRange>
-              <name>clk_rtc_rtc</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[20:20]</bitRange>
-              <name>clk_sys_rosc</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[19:19]</bitRange>
-              <name>clk_sys_rom</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[18:18]</bitRange>
-              <name>clk_sys_resets</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[17:17]</bitRange>
-              <name>clk_sys_pwm</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[16:16]</bitRange>
-              <name>clk_sys_psm</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[15:15]</bitRange>
-              <name>clk_sys_pll_usb</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[14:14]</bitRange>
-              <name>clk_sys_pll_sys</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[13:13]</bitRange>
-              <name>clk_sys_pio1</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[12:12]</bitRange>
-              <name>clk_sys_pio0</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[11:11]</bitRange>
-              <name>clk_sys_pads</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[10:10]</bitRange>
-              <name>clk_sys_vreg_and_chip_reset</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[9:9]</bitRange>
-              <name>clk_sys_jtag</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[8:8]</bitRange>
-              <name>clk_sys_io</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[7:7]</bitRange>
-              <name>clk_sys_i2c1</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[6:6]</bitRange>
-              <name>clk_sys_i2c0</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[5:5]</bitRange>
-              <name>clk_sys_dma</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[4:4]</bitRange>
-              <name>clk_sys_busfabric</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[3:3]</bitRange>
-              <name>clk_sys_busctrl</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[2:2]</bitRange>
-              <name>clk_sys_adc</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[1:1]</bitRange>
-              <name>clk_adc_adc</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[0:0]</bitRange>
-              <name>clk_sys_clocks</name>
-            </field>
-          </fields>
-          <name>ENABLED0</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x00b4</addressOffset>
-          <description>indicates the state of the clock enable</description>
-          <fields>
-            <field>
-              <access>read-only</access>
-              <bitRange>[14:14]</bitRange>
-              <name>clk_sys_xosc</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[13:13]</bitRange>
-              <name>clk_sys_xip</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[12:12]</bitRange>
-              <name>clk_sys_watchdog</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[11:11]</bitRange>
-              <name>clk_usb_usbctrl</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[10:10]</bitRange>
-              <name>clk_sys_usbctrl</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[9:9]</bitRange>
-              <name>clk_sys_uart1</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[8:8]</bitRange>
-              <name>clk_peri_uart1</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[7:7]</bitRange>
-              <name>clk_sys_uart0</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[6:6]</bitRange>
-              <name>clk_peri_uart0</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[5:5]</bitRange>
-              <name>clk_sys_timer</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[4:4]</bitRange>
-              <name>clk_sys_tbman</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[3:3]</bitRange>
-              <name>clk_sys_sysinfo</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[2:2]</bitRange>
-              <name>clk_sys_syscfg</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[1:1]</bitRange>
-              <name>clk_sys_sram5</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[0:0]</bitRange>
-              <name>clk_sys_sram4</name>
-            </field>
-          </fields>
-          <name>ENABLED1</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x00b8</addressOffset>
-          <description>Raw Interrupts</description>
-          <fields>
-            <field>
-              <access>read-only</access>
-              <bitRange>[0:0]</bitRange>
-              <name>CLK_SYS_RESUS</name>
-            </field>
-          </fields>
-          <name>INTR</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x00bc</addressOffset>
-          <description>Interrupt Enable</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[0:0]</bitRange>
-              <name>CLK_SYS_RESUS</name>
-            </field>
-          </fields>
-          <name>INTE</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x00c0</addressOffset>
-          <description>Interrupt Force</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[0:0]</bitRange>
-              <name>CLK_SYS_RESUS</name>
-            </field>
-          </fields>
-          <name>INTF</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x00c4</addressOffset>
-          <description>Interrupt status after masking &amp; forcing</description>
-          <fields>
-            <field>
-              <access>read-only</access>
-              <bitRange>[0:0]</bitRange>
-              <name>CLK_SYS_RESUS</name>
-            </field>
-          </fields>
-          <name>INTS</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-      </registers>
-      <size>32</size>
-      <version>1</version>
-    </peripheral>
-    <peripheral>
-      <addressBlock>
-        <offset>0</offset>
-        <size>0x1000</size>
-        <usage>registers</usage>
-      </addressBlock>
-      <baseAddress>0x4000c000</baseAddress>
-      <name>RESETS</name>
-      <registers>
-        <register>
-          <addressOffset>0x0000</addressOffset>
-          <description>Reset control. If a bit is set it means the peripheral is in reset. 0 means the peripheral's reset is deasserted.</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[24:24]</bitRange>
-              <name>usbctrl</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[23:23]</bitRange>
-              <name>uart1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[22:22]</bitRange>
-              <name>uart0</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[21:21]</bitRange>
-              <name>timer</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[20:20]</bitRange>
-              <name>tbman</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[19:19]</bitRange>
-              <name>sysinfo</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[18:18]</bitRange>
-              <name>syscfg</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[17:17]</bitRange>
-              <name>spi1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[16:16]</bitRange>
-              <name>spi0</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[15:15]</bitRange>
-              <name>rtc</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[14:14]</bitRange>
-              <name>pwm</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[13:13]</bitRange>
-              <name>pll_usb</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[12:12]</bitRange>
-              <name>pll_sys</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[11:11]</bitRange>
-              <name>pio1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[10:10]</bitRange>
-              <name>pio0</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[9:9]</bitRange>
-              <name>pads_qspi</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[8:8]</bitRange>
-              <name>pads_bank0</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[7:7]</bitRange>
-              <name>jtag</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[6:6]</bitRange>
-              <name>io_qspi</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[5:5]</bitRange>
-              <name>io_bank0</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[4:4]</bitRange>
-              <name>i2c1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[3:3]</bitRange>
-              <name>i2c0</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[2:2]</bitRange>
-              <name>dma</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[1:1]</bitRange>
-              <name>busctrl</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[0:0]</bitRange>
-              <name>adc</name>
-            </field>
-          </fields>
-          <name>RESET</name>
-          <resetValue>0x01ffffff</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0004</addressOffset>
-          <description>Watchdog select. If a bit is set then the watchdog will reset this peripheral when the watchdog fires.</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[24:24]</bitRange>
-              <name>usbctrl</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[23:23]</bitRange>
-              <name>uart1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[22:22]</bitRange>
-              <name>uart0</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[21:21]</bitRange>
-              <name>timer</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[20:20]</bitRange>
-              <name>tbman</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[19:19]</bitRange>
-              <name>sysinfo</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[18:18]</bitRange>
-              <name>syscfg</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[17:17]</bitRange>
-              <name>spi1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[16:16]</bitRange>
-              <name>spi0</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[15:15]</bitRange>
-              <name>rtc</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[14:14]</bitRange>
-              <name>pwm</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[13:13]</bitRange>
-              <name>pll_usb</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[12:12]</bitRange>
-              <name>pll_sys</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[11:11]</bitRange>
-              <name>pio1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[10:10]</bitRange>
-              <name>pio0</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[9:9]</bitRange>
-              <name>pads_qspi</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[8:8]</bitRange>
-              <name>pads_bank0</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[7:7]</bitRange>
-              <name>jtag</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[6:6]</bitRange>
-              <name>io_qspi</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[5:5]</bitRange>
-              <name>io_bank0</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[4:4]</bitRange>
-              <name>i2c1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[3:3]</bitRange>
-              <name>i2c0</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[2:2]</bitRange>
-              <name>dma</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[1:1]</bitRange>
-              <name>busctrl</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[0:0]</bitRange>
-              <name>adc</name>
-            </field>
-          </fields>
-          <name>WDSEL</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0008</addressOffset>
-          <description>Reset done. If a bit is set then a reset done signal has been returned by the peripheral. This indicates that the peripheral's registers are ready to be accessed.</description>
-          <fields>
-            <field>
-              <access>read-only</access>
-              <bitRange>[24:24]</bitRange>
-              <name>usbctrl</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[23:23]</bitRange>
-              <name>uart1</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[22:22]</bitRange>
-              <name>uart0</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[21:21]</bitRange>
-              <name>timer</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[20:20]</bitRange>
-              <name>tbman</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[19:19]</bitRange>
-              <name>sysinfo</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[18:18]</bitRange>
-              <name>syscfg</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[17:17]</bitRange>
-              <name>spi1</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[16:16]</bitRange>
-              <name>spi0</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[15:15]</bitRange>
-              <name>rtc</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[14:14]</bitRange>
-              <name>pwm</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[13:13]</bitRange>
-              <name>pll_usb</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[12:12]</bitRange>
-              <name>pll_sys</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[11:11]</bitRange>
-              <name>pio1</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[10:10]</bitRange>
-              <name>pio0</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[9:9]</bitRange>
-              <name>pads_qspi</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[8:8]</bitRange>
-              <name>pads_bank0</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[7:7]</bitRange>
-              <name>jtag</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[6:6]</bitRange>
-              <name>io_qspi</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[5:5]</bitRange>
-              <name>io_bank0</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[4:4]</bitRange>
-              <name>i2c1</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[3:3]</bitRange>
-              <name>i2c0</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[2:2]</bitRange>
-              <name>dma</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[1:1]</bitRange>
-              <name>busctrl</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[0:0]</bitRange>
-              <name>adc</name>
-            </field>
-          </fields>
-          <name>RESET_DONE</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-      </registers>
-      <size>32</size>
-      <version>1</version>
-    </peripheral>
-    <peripheral>
-      <addressBlock>
-        <offset>0</offset>
-        <size>0x1000</size>
-        <usage>registers</usage>
-      </addressBlock>
-      <baseAddress>0x40010000</baseAddress>
-      <name>PSM</name>
-      <registers>
-        <register>
-          <addressOffset>0x0000</addressOffset>
-          <description>Force block out of reset (i.e. power it on)</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[16:16]</bitRange>
-              <name>proc1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[15:15]</bitRange>
-              <name>proc0</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[14:14]</bitRange>
-              <name>sio</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[13:13]</bitRange>
-              <name>vreg_and_chip_reset</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[12:12]</bitRange>
-              <name>xip</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[11:11]</bitRange>
-              <name>sram5</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[10:10]</bitRange>
-              <name>sram4</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[9:9]</bitRange>
-              <name>sram3</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[8:8]</bitRange>
-              <name>sram2</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[7:7]</bitRange>
-              <name>sram1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[6:6]</bitRange>
-              <name>sram0</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[5:5]</bitRange>
-              <name>rom</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[4:4]</bitRange>
-              <name>busfabric</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[3:3]</bitRange>
-              <name>resets</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[2:2]</bitRange>
-              <name>clocks</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[1:1]</bitRange>
-              <name>xosc</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[0:0]</bitRange>
-              <name>rosc</name>
-            </field>
-          </fields>
-          <name>FRCE_ON</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0004</addressOffset>
-          <description>Force into reset (i.e. power it off)</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[16:16]</bitRange>
-              <name>proc1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[15:15]</bitRange>
-              <name>proc0</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[14:14]</bitRange>
-              <name>sio</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[13:13]</bitRange>
-              <name>vreg_and_chip_reset</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[12:12]</bitRange>
-              <name>xip</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[11:11]</bitRange>
-              <name>sram5</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[10:10]</bitRange>
-              <name>sram4</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[9:9]</bitRange>
-              <name>sram3</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[8:8]</bitRange>
-              <name>sram2</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[7:7]</bitRange>
-              <name>sram1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[6:6]</bitRange>
-              <name>sram0</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[5:5]</bitRange>
-              <name>rom</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[4:4]</bitRange>
-              <name>busfabric</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[3:3]</bitRange>
-              <name>resets</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[2:2]</bitRange>
-              <name>clocks</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[1:1]</bitRange>
-              <name>xosc</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[0:0]</bitRange>
-              <name>rosc</name>
-            </field>
-          </fields>
-          <name>FRCE_OFF</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0008</addressOffset>
-          <description>Set to 1 if this peripheral should be reset when the watchdog fires.</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[16:16]</bitRange>
-              <name>proc1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[15:15]</bitRange>
-              <name>proc0</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[14:14]</bitRange>
-              <name>sio</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[13:13]</bitRange>
-              <name>vreg_and_chip_reset</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[12:12]</bitRange>
-              <name>xip</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[11:11]</bitRange>
-              <name>sram5</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[10:10]</bitRange>
-              <name>sram4</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[9:9]</bitRange>
-              <name>sram3</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[8:8]</bitRange>
-              <name>sram2</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[7:7]</bitRange>
-              <name>sram1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[6:6]</bitRange>
-              <name>sram0</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[5:5]</bitRange>
-              <name>rom</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[4:4]</bitRange>
-              <name>busfabric</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[3:3]</bitRange>
-              <name>resets</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[2:2]</bitRange>
-              <name>clocks</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[1:1]</bitRange>
-              <name>xosc</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[0:0]</bitRange>
-              <name>rosc</name>
-            </field>
-          </fields>
-          <name>WDSEL</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x000c</addressOffset>
-          <description>Indicates the peripheral's registers are ready to access.</description>
-          <fields>
-            <field>
-              <access>read-only</access>
-              <bitRange>[16:16]</bitRange>
-              <name>proc1</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[15:15]</bitRange>
-              <name>proc0</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[14:14]</bitRange>
-              <name>sio</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[13:13]</bitRange>
-              <name>vreg_and_chip_reset</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[12:12]</bitRange>
-              <name>xip</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[11:11]</bitRange>
-              <name>sram5</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[10:10]</bitRange>
-              <name>sram4</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[9:9]</bitRange>
-              <name>sram3</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[8:8]</bitRange>
-              <name>sram2</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[7:7]</bitRange>
-              <name>sram1</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[6:6]</bitRange>
-              <name>sram0</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[5:5]</bitRange>
-              <name>rom</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[4:4]</bitRange>
-              <name>busfabric</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[3:3]</bitRange>
-              <name>resets</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[2:2]</bitRange>
-              <name>clocks</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[1:1]</bitRange>
-              <name>xosc</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[0:0]</bitRange>
-              <name>rosc</name>
-            </field>
-          </fields>
-          <name>DONE</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-      </registers>
-      <size>32</size>
-      <version>1</version>
-    </peripheral>
-    <peripheral>
-      <addressBlock>
-        <offset>0</offset>
-        <size>0x1000</size>
-        <usage>registers</usage>
-      </addressBlock>
-      <baseAddress>0x40014000</baseAddress>
-      <interrupt>
-        <name>IO_IRQ_BANK0</name>
-        <value>13</value>
-      </interrupt>
-      <name>IO_BANK0</name>
-      <registers>
-        <register>
-          <addressOffset>0x0000</addressOffset>
-          <description>GPIO status</description>
-          <fields>
-            <field>
-              <access>read-only</access>
-              <bitRange>[26:26]</bitRange>
-              <description>interrupt to processors, after override is applied</description>
-              <name>IRQTOPROC</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[24:24]</bitRange>
-              <description>interrupt from pad before override is applied</description>
-              <name>IRQFROMPAD</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[19:19]</bitRange>
-              <description>input signal to peripheral, after override is applied</description>
-              <name>INTOPERI</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[17:17]</bitRange>
-              <description>input signal from pad, before override is applied</description>
-              <name>INFROMPAD</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[13:13]</bitRange>
-              <description>output enable to pad after register override is applied</description>
-              <name>OETOPAD</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[12:12]</bitRange>
-              <description>output enable from selected peripheral, before register override is applied</description>
-              <name>OEFROMPERI</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[9:9]</bitRange>
-              <description>output signal to pad after register override is applied</description>
-              <name>OUTTOPAD</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[8:8]</bitRange>
-              <description>output signal from selected peripheral, before register override is applied</description>
-              <name>OUTFROMPERI</name>
-            </field>
-          </fields>
-          <name>GPIO0_STATUS</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0004</addressOffset>
-          <description>GPIO control including function select and overrides.</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[29:28]</bitRange>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>don't invert the interrupt</description>
-                  <name>NORMAL</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>invert the interrupt</description>
-                  <name>INVERT</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive interrupt low</description>
-                  <name>LOW</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive interrupt high</description>
-                  <name>HIGH</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>IRQOVER</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[17:16]</bitRange>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>don't invert the peri input</description>
-                  <name>NORMAL</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>invert the peri input</description>
-                  <name>INVERT</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive peri input low</description>
-                  <name>LOW</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive peri input high</description>
-                  <name>HIGH</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>INOVER</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[13:12]</bitRange>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>drive output enable from peripheral signal selected by funcsel</description>
-                  <name>NORMAL</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
-                  <name>INVERT</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>disable output</description>
-                  <name>DISABLE</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>enable output</description>
-                  <name>ENABLE</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>OEOVER</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[9:8]</bitRange>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>drive output from peripheral signal selected by funcsel</description>
-                  <name>NORMAL</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive output from inverse of peripheral signal selected by funcsel</description>
-                  <name>INVERT</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive output low</description>
-                  <name>LOW</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive output high</description>
-                  <name>HIGH</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>OUTOVER</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[4:0]</bitRange>
-              <description>0-31 -&gt; selects pin function according to the gpio table\n
-                31 == NULL</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>jtag_tck</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>spi0_rx</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>uart0_tx</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>i2c0_sda</name>
-                  <value>3</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>pwm_a_0</name>
-                  <value>4</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>sio_0</name>
-                  <value>5</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>pio0_0</name>
-                  <value>6</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>pio1_0</name>
-                  <value>7</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>usb_muxing_overcurr_detect</name>
-                  <value>9</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>null</name>
-                  <value>31</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>FUNCSEL</name>
-            </field>
-          </fields>
-          <name>GPIO0_CTRL</name>
-          <resetValue>0x0000001f</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0008</addressOffset>
-          <description>GPIO status</description>
-          <fields>
-            <field>
-              <access>read-only</access>
-              <bitRange>[26:26]</bitRange>
-              <description>interrupt to processors, after override is applied</description>
-              <name>IRQTOPROC</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[24:24]</bitRange>
-              <description>interrupt from pad before override is applied</description>
-              <name>IRQFROMPAD</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[19:19]</bitRange>
-              <description>input signal to peripheral, after override is applied</description>
-              <name>INTOPERI</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[17:17]</bitRange>
-              <description>input signal from pad, before override is applied</description>
-              <name>INFROMPAD</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[13:13]</bitRange>
-              <description>output enable to pad after register override is applied</description>
-              <name>OETOPAD</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[12:12]</bitRange>
-              <description>output enable from selected peripheral, before register override is applied</description>
-              <name>OEFROMPERI</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[9:9]</bitRange>
-              <description>output signal to pad after register override is applied</description>
-              <name>OUTTOPAD</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[8:8]</bitRange>
-              <description>output signal from selected peripheral, before register override is applied</description>
-              <name>OUTFROMPERI</name>
-            </field>
-          </fields>
-          <name>GPIO1_STATUS</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x000c</addressOffset>
-          <description>GPIO control including function select and overrides.</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[29:28]</bitRange>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>don't invert the interrupt</description>
-                  <name>NORMAL</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>invert the interrupt</description>
-                  <name>INVERT</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive interrupt low</description>
-                  <name>LOW</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive interrupt high</description>
-                  <name>HIGH</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>IRQOVER</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[17:16]</bitRange>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>don't invert the peri input</description>
-                  <name>NORMAL</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>invert the peri input</description>
-                  <name>INVERT</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive peri input low</description>
-                  <name>LOW</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive peri input high</description>
-                  <name>HIGH</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>INOVER</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[13:12]</bitRange>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>drive output enable from peripheral signal selected by funcsel</description>
-                  <name>NORMAL</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
-                  <name>INVERT</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>disable output</description>
-                  <name>DISABLE</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>enable output</description>
-                  <name>ENABLE</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>OEOVER</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[9:8]</bitRange>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>drive output from peripheral signal selected by funcsel</description>
-                  <name>NORMAL</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive output from inverse of peripheral signal selected by funcsel</description>
-                  <name>INVERT</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive output low</description>
-                  <name>LOW</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive output high</description>
-                  <name>HIGH</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>OUTOVER</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[4:0]</bitRange>
-              <description>0-31 -&gt; selects pin function according to the gpio table\n
-                31 == NULL</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>jtag_tms</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>spi0_ss_n</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>uart0_rx</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>i2c0_scl</name>
-                  <value>3</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>pwm_b_0</name>
-                  <value>4</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>sio_1</name>
-                  <value>5</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>pio0_1</name>
-                  <value>6</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>pio1_1</name>
-                  <value>7</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>usb_muxing_vbus_detect</name>
-                  <value>9</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>null</name>
-                  <value>31</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>FUNCSEL</name>
-            </field>
-          </fields>
-          <name>GPIO1_CTRL</name>
-          <resetValue>0x0000001f</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0010</addressOffset>
-          <description>GPIO status</description>
-          <fields>
-            <field>
-              <access>read-only</access>
-              <bitRange>[26:26]</bitRange>
-              <description>interrupt to processors, after override is applied</description>
-              <name>IRQTOPROC</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[24:24]</bitRange>
-              <description>interrupt from pad before override is applied</description>
-              <name>IRQFROMPAD</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[19:19]</bitRange>
-              <description>input signal to peripheral, after override is applied</description>
-              <name>INTOPERI</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[17:17]</bitRange>
-              <description>input signal from pad, before override is applied</description>
-              <name>INFROMPAD</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[13:13]</bitRange>
-              <description>output enable to pad after register override is applied</description>
-              <name>OETOPAD</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[12:12]</bitRange>
-              <description>output enable from selected peripheral, before register override is applied</description>
-              <name>OEFROMPERI</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[9:9]</bitRange>
-              <description>output signal to pad after register override is applied</description>
-              <name>OUTTOPAD</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[8:8]</bitRange>
-              <description>output signal from selected peripheral, before register override is applied</description>
-              <name>OUTFROMPERI</name>
-            </field>
-          </fields>
-          <name>GPIO2_STATUS</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0014</addressOffset>
-          <description>GPIO control including function select and overrides.</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[29:28]</bitRange>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>don't invert the interrupt</description>
-                  <name>NORMAL</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>invert the interrupt</description>
-                  <name>INVERT</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive interrupt low</description>
-                  <name>LOW</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive interrupt high</description>
-                  <name>HIGH</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>IRQOVER</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[17:16]</bitRange>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>don't invert the peri input</description>
-                  <name>NORMAL</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>invert the peri input</description>
-                  <name>INVERT</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive peri input low</description>
-                  <name>LOW</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive peri input high</description>
-                  <name>HIGH</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>INOVER</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[13:12]</bitRange>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>drive output enable from peripheral signal selected by funcsel</description>
-                  <name>NORMAL</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
-                  <name>INVERT</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>disable output</description>
-                  <name>DISABLE</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>enable output</description>
-                  <name>ENABLE</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>OEOVER</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[9:8]</bitRange>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>drive output from peripheral signal selected by funcsel</description>
-                  <name>NORMAL</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive output from inverse of peripheral signal selected by funcsel</description>
-                  <name>INVERT</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive output low</description>
-                  <name>LOW</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive output high</description>
-                  <name>HIGH</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>OUTOVER</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[4:0]</bitRange>
-              <description>0-31 -&gt; selects pin function according to the gpio table\n
-                31 == NULL</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>jtag_tdi</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>spi0_sclk</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>uart0_cts</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>i2c1_sda</name>
-                  <value>3</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>pwm_a_1</name>
-                  <value>4</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>sio_2</name>
-                  <value>5</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>pio0_2</name>
-                  <value>6</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>pio1_2</name>
-                  <value>7</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>usb_muxing_vbus_en</name>
-                  <value>9</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>null</name>
-                  <value>31</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>FUNCSEL</name>
-            </field>
-          </fields>
-          <name>GPIO2_CTRL</name>
-          <resetValue>0x0000001f</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0018</addressOffset>
-          <description>GPIO status</description>
-          <fields>
-            <field>
-              <access>read-only</access>
-              <bitRange>[26:26]</bitRange>
-              <description>interrupt to processors, after override is applied</description>
-              <name>IRQTOPROC</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[24:24]</bitRange>
-              <description>interrupt from pad before override is applied</description>
-              <name>IRQFROMPAD</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[19:19]</bitRange>
-              <description>input signal to peripheral, after override is applied</description>
-              <name>INTOPERI</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[17:17]</bitRange>
-              <description>input signal from pad, before override is applied</description>
-              <name>INFROMPAD</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[13:13]</bitRange>
-              <description>output enable to pad after register override is applied</description>
-              <name>OETOPAD</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[12:12]</bitRange>
-              <description>output enable from selected peripheral, before register override is applied</description>
-              <name>OEFROMPERI</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[9:9]</bitRange>
-              <description>output signal to pad after register override is applied</description>
-              <name>OUTTOPAD</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[8:8]</bitRange>
-              <description>output signal from selected peripheral, before register override is applied</description>
-              <name>OUTFROMPERI</name>
-            </field>
-          </fields>
-          <name>GPIO3_STATUS</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x001c</addressOffset>
-          <description>GPIO control including function select and overrides.</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[29:28]</bitRange>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>don't invert the interrupt</description>
-                  <name>NORMAL</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>invert the interrupt</description>
-                  <name>INVERT</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive interrupt low</description>
-                  <name>LOW</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive interrupt high</description>
-                  <name>HIGH</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>IRQOVER</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[17:16]</bitRange>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>don't invert the peri input</description>
-                  <name>NORMAL</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>invert the peri input</description>
-                  <name>INVERT</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive peri input low</description>
-                  <name>LOW</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive peri input high</description>
-                  <name>HIGH</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>INOVER</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[13:12]</bitRange>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>drive output enable from peripheral signal selected by funcsel</description>
-                  <name>NORMAL</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
-                  <name>INVERT</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>disable output</description>
-                  <name>DISABLE</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>enable output</description>
-                  <name>ENABLE</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>OEOVER</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[9:8]</bitRange>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>drive output from peripheral signal selected by funcsel</description>
-                  <name>NORMAL</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive output from inverse of peripheral signal selected by funcsel</description>
-                  <name>INVERT</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive output low</description>
-                  <name>LOW</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive output high</description>
-                  <name>HIGH</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>OUTOVER</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[4:0]</bitRange>
-              <description>0-31 -&gt; selects pin function according to the gpio table\n
-                31 == NULL</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>jtag_tdo</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>spi0_tx</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>uart0_rts</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>i2c1_scl</name>
-                  <value>3</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>pwm_b_1</name>
-                  <value>4</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>sio_3</name>
-                  <value>5</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>pio0_3</name>
-                  <value>6</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>pio1_3</name>
-                  <value>7</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>usb_muxing_overcurr_detect</name>
-                  <value>9</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>null</name>
-                  <value>31</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>FUNCSEL</name>
-            </field>
-          </fields>
-          <name>GPIO3_CTRL</name>
-          <resetValue>0x0000001f</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0020</addressOffset>
-          <description>GPIO status</description>
-          <fields>
-            <field>
-              <access>read-only</access>
-              <bitRange>[26:26]</bitRange>
-              <description>interrupt to processors, after override is applied</description>
-              <name>IRQTOPROC</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[24:24]</bitRange>
-              <description>interrupt from pad before override is applied</description>
-              <name>IRQFROMPAD</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[19:19]</bitRange>
-              <description>input signal to peripheral, after override is applied</description>
-              <name>INTOPERI</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[17:17]</bitRange>
-              <description>input signal from pad, before override is applied</description>
-              <name>INFROMPAD</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[13:13]</bitRange>
-              <description>output enable to pad after register override is applied</description>
-              <name>OETOPAD</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[12:12]</bitRange>
-              <description>output enable from selected peripheral, before register override is applied</description>
-              <name>OEFROMPERI</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[9:9]</bitRange>
-              <description>output signal to pad after register override is applied</description>
-              <name>OUTTOPAD</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[8:8]</bitRange>
-              <description>output signal from selected peripheral, before register override is applied</description>
-              <name>OUTFROMPERI</name>
-            </field>
-          </fields>
-          <name>GPIO4_STATUS</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0024</addressOffset>
-          <description>GPIO control including function select and overrides.</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[29:28]</bitRange>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>don't invert the interrupt</description>
-                  <name>NORMAL</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>invert the interrupt</description>
-                  <name>INVERT</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive interrupt low</description>
-                  <name>LOW</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive interrupt high</description>
-                  <name>HIGH</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>IRQOVER</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[17:16]</bitRange>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>don't invert the peri input</description>
-                  <name>NORMAL</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>invert the peri input</description>
-                  <name>INVERT</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive peri input low</description>
-                  <name>LOW</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive peri input high</description>
-                  <name>HIGH</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>INOVER</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[13:12]</bitRange>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>drive output enable from peripheral signal selected by funcsel</description>
-                  <name>NORMAL</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
-                  <name>INVERT</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>disable output</description>
-                  <name>DISABLE</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>enable output</description>
-                  <name>ENABLE</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>OEOVER</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[9:8]</bitRange>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>drive output from peripheral signal selected by funcsel</description>
-                  <name>NORMAL</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive output from inverse of peripheral signal selected by funcsel</description>
-                  <name>INVERT</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive output low</description>
-                  <name>LOW</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive output high</description>
-                  <name>HIGH</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>OUTOVER</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[4:0]</bitRange>
-              <description>0-31 -&gt; selects pin function according to the gpio table\n
-                31 == NULL</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>spi0_rx</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>uart1_tx</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>i2c0_sda</name>
-                  <value>3</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>pwm_a_2</name>
-                  <value>4</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>sio_4</name>
-                  <value>5</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>pio0_4</name>
-                  <value>6</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>pio1_4</name>
-                  <value>7</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>usb_muxing_vbus_detect</name>
-                  <value>9</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>null</name>
-                  <value>31</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>FUNCSEL</name>
-            </field>
-          </fields>
-          <name>GPIO4_CTRL</name>
-          <resetValue>0x0000001f</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0028</addressOffset>
-          <description>GPIO status</description>
-          <fields>
-            <field>
-              <access>read-only</access>
-              <bitRange>[26:26]</bitRange>
-              <description>interrupt to processors, after override is applied</description>
-              <name>IRQTOPROC</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[24:24]</bitRange>
-              <description>interrupt from pad before override is applied</description>
-              <name>IRQFROMPAD</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[19:19]</bitRange>
-              <description>input signal to peripheral, after override is applied</description>
-              <name>INTOPERI</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[17:17]</bitRange>
-              <description>input signal from pad, before override is applied</description>
-              <name>INFROMPAD</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[13:13]</bitRange>
-              <description>output enable to pad after register override is applied</description>
-              <name>OETOPAD</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[12:12]</bitRange>
-              <description>output enable from selected peripheral, before register override is applied</description>
-              <name>OEFROMPERI</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[9:9]</bitRange>
-              <description>output signal to pad after register override is applied</description>
-              <name>OUTTOPAD</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[8:8]</bitRange>
-              <description>output signal from selected peripheral, before register override is applied</description>
-              <name>OUTFROMPERI</name>
-            </field>
-          </fields>
-          <name>GPIO5_STATUS</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x002c</addressOffset>
-          <description>GPIO control including function select and overrides.</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[29:28]</bitRange>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>don't invert the interrupt</description>
-                  <name>NORMAL</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>invert the interrupt</description>
-                  <name>INVERT</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive interrupt low</description>
-                  <name>LOW</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive interrupt high</description>
-                  <name>HIGH</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>IRQOVER</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[17:16]</bitRange>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>don't invert the peri input</description>
-                  <name>NORMAL</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>invert the peri input</description>
-                  <name>INVERT</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive peri input low</description>
-                  <name>LOW</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive peri input high</description>
-                  <name>HIGH</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>INOVER</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[13:12]</bitRange>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>drive output enable from peripheral signal selected by funcsel</description>
-                  <name>NORMAL</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
-                  <name>INVERT</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>disable output</description>
-                  <name>DISABLE</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>enable output</description>
-                  <name>ENABLE</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>OEOVER</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[9:8]</bitRange>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>drive output from peripheral signal selected by funcsel</description>
-                  <name>NORMAL</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive output from inverse of peripheral signal selected by funcsel</description>
-                  <name>INVERT</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive output low</description>
-                  <name>LOW</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive output high</description>
-                  <name>HIGH</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>OUTOVER</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[4:0]</bitRange>
-              <description>0-31 -&gt; selects pin function according to the gpio table\n
-                31 == NULL</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>spi0_ss_n</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>uart1_rx</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>i2c0_scl</name>
-                  <value>3</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>pwm_b_2</name>
-                  <value>4</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>sio_5</name>
-                  <value>5</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>pio0_5</name>
-                  <value>6</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>pio1_5</name>
-                  <value>7</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>usb_muxing_vbus_en</name>
-                  <value>9</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>null</name>
-                  <value>31</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>FUNCSEL</name>
-            </field>
-          </fields>
-          <name>GPIO5_CTRL</name>
-          <resetValue>0x0000001f</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0030</addressOffset>
-          <description>GPIO status</description>
-          <fields>
-            <field>
-              <access>read-only</access>
-              <bitRange>[26:26]</bitRange>
-              <description>interrupt to processors, after override is applied</description>
-              <name>IRQTOPROC</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[24:24]</bitRange>
-              <description>interrupt from pad before override is applied</description>
-              <name>IRQFROMPAD</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[19:19]</bitRange>
-              <description>input signal to peripheral, after override is applied</description>
-              <name>INTOPERI</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[17:17]</bitRange>
-              <description>input signal from pad, before override is applied</description>
-              <name>INFROMPAD</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[13:13]</bitRange>
-              <description>output enable to pad after register override is applied</description>
-              <name>OETOPAD</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[12:12]</bitRange>
-              <description>output enable from selected peripheral, before register override is applied</description>
-              <name>OEFROMPERI</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[9:9]</bitRange>
-              <description>output signal to pad after register override is applied</description>
-              <name>OUTTOPAD</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[8:8]</bitRange>
-              <description>output signal from selected peripheral, before register override is applied</description>
-              <name>OUTFROMPERI</name>
-            </field>
-          </fields>
-          <name>GPIO6_STATUS</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0034</addressOffset>
-          <description>GPIO control including function select and overrides.</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[29:28]</bitRange>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>don't invert the interrupt</description>
-                  <name>NORMAL</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>invert the interrupt</description>
-                  <name>INVERT</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive interrupt low</description>
-                  <name>LOW</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive interrupt high</description>
-                  <name>HIGH</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>IRQOVER</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[17:16]</bitRange>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>don't invert the peri input</description>
-                  <name>NORMAL</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>invert the peri input</description>
-                  <name>INVERT</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive peri input low</description>
-                  <name>LOW</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive peri input high</description>
-                  <name>HIGH</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>INOVER</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[13:12]</bitRange>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>drive output enable from peripheral signal selected by funcsel</description>
-                  <name>NORMAL</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
-                  <name>INVERT</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>disable output</description>
-                  <name>DISABLE</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>enable output</description>
-                  <name>ENABLE</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>OEOVER</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[9:8]</bitRange>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>drive output from peripheral signal selected by funcsel</description>
-                  <name>NORMAL</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive output from inverse of peripheral signal selected by funcsel</description>
-                  <name>INVERT</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive output low</description>
-                  <name>LOW</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive output high</description>
-                  <name>HIGH</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>OUTOVER</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[4:0]</bitRange>
-              <description>0-31 -&gt; selects pin function according to the gpio table\n
-                31 == NULL</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>spi0_sclk</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>uart1_cts</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>i2c1_sda</name>
-                  <value>3</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>pwm_a_3</name>
-                  <value>4</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>sio_6</name>
-                  <value>5</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>pio0_6</name>
-                  <value>6</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>pio1_6</name>
-                  <value>7</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>usb_muxing_extphy_softcon</name>
-                  <value>8</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>usb_muxing_overcurr_detect</name>
-                  <value>9</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>null</name>
-                  <value>31</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>FUNCSEL</name>
-            </field>
-          </fields>
-          <name>GPIO6_CTRL</name>
-          <resetValue>0x0000001f</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0038</addressOffset>
-          <description>GPIO status</description>
-          <fields>
-            <field>
-              <access>read-only</access>
-              <bitRange>[26:26]</bitRange>
-              <description>interrupt to processors, after override is applied</description>
-              <name>IRQTOPROC</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[24:24]</bitRange>
-              <description>interrupt from pad before override is applied</description>
-              <name>IRQFROMPAD</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[19:19]</bitRange>
-              <description>input signal to peripheral, after override is applied</description>
-              <name>INTOPERI</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[17:17]</bitRange>
-              <description>input signal from pad, before override is applied</description>
-              <name>INFROMPAD</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[13:13]</bitRange>
-              <description>output enable to pad after register override is applied</description>
-              <name>OETOPAD</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[12:12]</bitRange>
-              <description>output enable from selected peripheral, before register override is applied</description>
-              <name>OEFROMPERI</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[9:9]</bitRange>
-              <description>output signal to pad after register override is applied</description>
-              <name>OUTTOPAD</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[8:8]</bitRange>
-              <description>output signal from selected peripheral, before register override is applied</description>
-              <name>OUTFROMPERI</name>
-            </field>
-          </fields>
-          <name>GPIO7_STATUS</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x003c</addressOffset>
-          <description>GPIO control including function select and overrides.</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[29:28]</bitRange>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>don't invert the interrupt</description>
-                  <name>NORMAL</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>invert the interrupt</description>
-                  <name>INVERT</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive interrupt low</description>
-                  <name>LOW</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive interrupt high</description>
-                  <name>HIGH</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>IRQOVER</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[17:16]</bitRange>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>don't invert the peri input</description>
-                  <name>NORMAL</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>invert the peri input</description>
-                  <name>INVERT</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive peri input low</description>
-                  <name>LOW</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive peri input high</description>
-                  <name>HIGH</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>INOVER</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[13:12]</bitRange>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>drive output enable from peripheral signal selected by funcsel</description>
-                  <name>NORMAL</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
-                  <name>INVERT</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>disable output</description>
-                  <name>DISABLE</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>enable output</description>
-                  <name>ENABLE</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>OEOVER</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[9:8]</bitRange>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>drive output from peripheral signal selected by funcsel</description>
-                  <name>NORMAL</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive output from inverse of peripheral signal selected by funcsel</description>
-                  <name>INVERT</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive output low</description>
-                  <name>LOW</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive output high</description>
-                  <name>HIGH</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>OUTOVER</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[4:0]</bitRange>
-              <description>0-31 -&gt; selects pin function according to the gpio table\n
-                31 == NULL</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>spi0_tx</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>uart1_rts</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>i2c1_scl</name>
-                  <value>3</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>pwm_b_3</name>
-                  <value>4</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>sio_7</name>
-                  <value>5</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>pio0_7</name>
-                  <value>6</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>pio1_7</name>
-                  <value>7</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>usb_muxing_extphy_oe_n</name>
-                  <value>8</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>usb_muxing_vbus_detect</name>
-                  <value>9</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>null</name>
-                  <value>31</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>FUNCSEL</name>
-            </field>
-          </fields>
-          <name>GPIO7_CTRL</name>
-          <resetValue>0x0000001f</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0040</addressOffset>
-          <description>GPIO status</description>
-          <fields>
-            <field>
-              <access>read-only</access>
-              <bitRange>[26:26]</bitRange>
-              <description>interrupt to processors, after override is applied</description>
-              <name>IRQTOPROC</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[24:24]</bitRange>
-              <description>interrupt from pad before override is applied</description>
-              <name>IRQFROMPAD</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[19:19]</bitRange>
-              <description>input signal to peripheral, after override is applied</description>
-              <name>INTOPERI</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[17:17]</bitRange>
-              <description>input signal from pad, before override is applied</description>
-              <name>INFROMPAD</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[13:13]</bitRange>
-              <description>output enable to pad after register override is applied</description>
-              <name>OETOPAD</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[12:12]</bitRange>
-              <description>output enable from selected peripheral, before register override is applied</description>
-              <name>OEFROMPERI</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[9:9]</bitRange>
-              <description>output signal to pad after register override is applied</description>
-              <name>OUTTOPAD</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[8:8]</bitRange>
-              <description>output signal from selected peripheral, before register override is applied</description>
-              <name>OUTFROMPERI</name>
-            </field>
-          </fields>
-          <name>GPIO8_STATUS</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0044</addressOffset>
-          <description>GPIO control including function select and overrides.</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[29:28]</bitRange>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>don't invert the interrupt</description>
-                  <name>NORMAL</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>invert the interrupt</description>
-                  <name>INVERT</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive interrupt low</description>
-                  <name>LOW</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive interrupt high</description>
-                  <name>HIGH</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>IRQOVER</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[17:16]</bitRange>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>don't invert the peri input</description>
-                  <name>NORMAL</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>invert the peri input</description>
-                  <name>INVERT</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive peri input low</description>
-                  <name>LOW</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive peri input high</description>
-                  <name>HIGH</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>INOVER</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[13:12]</bitRange>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>drive output enable from peripheral signal selected by funcsel</description>
-                  <name>NORMAL</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
-                  <name>INVERT</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>disable output</description>
-                  <name>DISABLE</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>enable output</description>
-                  <name>ENABLE</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>OEOVER</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[9:8]</bitRange>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>drive output from peripheral signal selected by funcsel</description>
-                  <name>NORMAL</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive output from inverse of peripheral signal selected by funcsel</description>
-                  <name>INVERT</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive output low</description>
-                  <name>LOW</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive output high</description>
-                  <name>HIGH</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>OUTOVER</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[4:0]</bitRange>
-              <description>0-31 -&gt; selects pin function according to the gpio table\n
-                31 == NULL</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>spi1_rx</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>uart1_tx</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>i2c0_sda</name>
-                  <value>3</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>pwm_a_4</name>
-                  <value>4</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>sio_8</name>
-                  <value>5</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>pio0_8</name>
-                  <value>6</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>pio1_8</name>
-                  <value>7</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>usb_muxing_extphy_rcv</name>
-                  <value>8</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>usb_muxing_vbus_en</name>
-                  <value>9</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>null</name>
-                  <value>31</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>FUNCSEL</name>
-            </field>
-          </fields>
-          <name>GPIO8_CTRL</name>
-          <resetValue>0x0000001f</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0048</addressOffset>
-          <description>GPIO status</description>
-          <fields>
-            <field>
-              <access>read-only</access>
-              <bitRange>[26:26]</bitRange>
-              <description>interrupt to processors, after override is applied</description>
-              <name>IRQTOPROC</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[24:24]</bitRange>
-              <description>interrupt from pad before override is applied</description>
-              <name>IRQFROMPAD</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[19:19]</bitRange>
-              <description>input signal to peripheral, after override is applied</description>
-              <name>INTOPERI</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[17:17]</bitRange>
-              <description>input signal from pad, before override is applied</description>
-              <name>INFROMPAD</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[13:13]</bitRange>
-              <description>output enable to pad after register override is applied</description>
-              <name>OETOPAD</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[12:12]</bitRange>
-              <description>output enable from selected peripheral, before register override is applied</description>
-              <name>OEFROMPERI</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[9:9]</bitRange>
-              <description>output signal to pad after register override is applied</description>
-              <name>OUTTOPAD</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[8:8]</bitRange>
-              <description>output signal from selected peripheral, before register override is applied</description>
-              <name>OUTFROMPERI</name>
-            </field>
-          </fields>
-          <name>GPIO9_STATUS</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x004c</addressOffset>
-          <description>GPIO control including function select and overrides.</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[29:28]</bitRange>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>don't invert the interrupt</description>
-                  <name>NORMAL</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>invert the interrupt</description>
-                  <name>INVERT</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive interrupt low</description>
-                  <name>LOW</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive interrupt high</description>
-                  <name>HIGH</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>IRQOVER</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[17:16]</bitRange>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>don't invert the peri input</description>
-                  <name>NORMAL</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>invert the peri input</description>
-                  <name>INVERT</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive peri input low</description>
-                  <name>LOW</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive peri input high</description>
-                  <name>HIGH</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>INOVER</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[13:12]</bitRange>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>drive output enable from peripheral signal selected by funcsel</description>
-                  <name>NORMAL</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
-                  <name>INVERT</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>disable output</description>
-                  <name>DISABLE</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>enable output</description>
-                  <name>ENABLE</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>OEOVER</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[9:8]</bitRange>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>drive output from peripheral signal selected by funcsel</description>
-                  <name>NORMAL</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive output from inverse of peripheral signal selected by funcsel</description>
-                  <name>INVERT</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive output low</description>
-                  <name>LOW</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive output high</description>
-                  <name>HIGH</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>OUTOVER</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[4:0]</bitRange>
-              <description>0-31 -&gt; selects pin function according to the gpio table\n
-                31 == NULL</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>spi1_ss_n</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>uart1_rx</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>i2c0_scl</name>
-                  <value>3</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>pwm_b_4</name>
-                  <value>4</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>sio_9</name>
-                  <value>5</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>pio0_9</name>
-                  <value>6</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>pio1_9</name>
-                  <value>7</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>usb_muxing_extphy_vp</name>
-                  <value>8</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>usb_muxing_overcurr_detect</name>
-                  <value>9</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>null</name>
-                  <value>31</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>FUNCSEL</name>
-            </field>
-          </fields>
-          <name>GPIO9_CTRL</name>
-          <resetValue>0x0000001f</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0050</addressOffset>
-          <description>GPIO status</description>
-          <fields>
-            <field>
-              <access>read-only</access>
-              <bitRange>[26:26]</bitRange>
-              <description>interrupt to processors, after override is applied</description>
-              <name>IRQTOPROC</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[24:24]</bitRange>
-              <description>interrupt from pad before override is applied</description>
-              <name>IRQFROMPAD</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[19:19]</bitRange>
-              <description>input signal to peripheral, after override is applied</description>
-              <name>INTOPERI</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[17:17]</bitRange>
-              <description>input signal from pad, before override is applied</description>
-              <name>INFROMPAD</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[13:13]</bitRange>
-              <description>output enable to pad after register override is applied</description>
-              <name>OETOPAD</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[12:12]</bitRange>
-              <description>output enable from selected peripheral, before register override is applied</description>
-              <name>OEFROMPERI</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[9:9]</bitRange>
-              <description>output signal to pad after register override is applied</description>
-              <name>OUTTOPAD</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[8:8]</bitRange>
-              <description>output signal from selected peripheral, before register override is applied</description>
-              <name>OUTFROMPERI</name>
-            </field>
-          </fields>
-          <name>GPIO10_STATUS</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0054</addressOffset>
-          <description>GPIO control including function select and overrides.</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[29:28]</bitRange>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>don't invert the interrupt</description>
-                  <name>NORMAL</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>invert the interrupt</description>
-                  <name>INVERT</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive interrupt low</description>
-                  <name>LOW</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive interrupt high</description>
-                  <name>HIGH</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>IRQOVER</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[17:16]</bitRange>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>don't invert the peri input</description>
-                  <name>NORMAL</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>invert the peri input</description>
-                  <name>INVERT</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive peri input low</description>
-                  <name>LOW</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive peri input high</description>
-                  <name>HIGH</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>INOVER</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[13:12]</bitRange>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>drive output enable from peripheral signal selected by funcsel</description>
-                  <name>NORMAL</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
-                  <name>INVERT</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>disable output</description>
-                  <name>DISABLE</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>enable output</description>
-                  <name>ENABLE</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>OEOVER</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[9:8]</bitRange>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>drive output from peripheral signal selected by funcsel</description>
-                  <name>NORMAL</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive output from inverse of peripheral signal selected by funcsel</description>
-                  <name>INVERT</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive output low</description>
-                  <name>LOW</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive output high</description>
-                  <name>HIGH</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>OUTOVER</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[4:0]</bitRange>
-              <description>0-31 -&gt; selects pin function according to the gpio table\n
-                31 == NULL</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>spi1_sclk</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>uart1_cts</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>i2c1_sda</name>
-                  <value>3</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>pwm_a_5</name>
-                  <value>4</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>sio_10</name>
-                  <value>5</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>pio0_10</name>
-                  <value>6</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>pio1_10</name>
-                  <value>7</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>usb_muxing_extphy_vm</name>
-                  <value>8</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>usb_muxing_vbus_detect</name>
-                  <value>9</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>null</name>
-                  <value>31</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>FUNCSEL</name>
-            </field>
-          </fields>
-          <name>GPIO10_CTRL</name>
-          <resetValue>0x0000001f</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0058</addressOffset>
-          <description>GPIO status</description>
-          <fields>
-            <field>
-              <access>read-only</access>
-              <bitRange>[26:26]</bitRange>
-              <description>interrupt to processors, after override is applied</description>
-              <name>IRQTOPROC</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[24:24]</bitRange>
-              <description>interrupt from pad before override is applied</description>
-              <name>IRQFROMPAD</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[19:19]</bitRange>
-              <description>input signal to peripheral, after override is applied</description>
-              <name>INTOPERI</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[17:17]</bitRange>
-              <description>input signal from pad, before override is applied</description>
-              <name>INFROMPAD</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[13:13]</bitRange>
-              <description>output enable to pad after register override is applied</description>
-              <name>OETOPAD</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[12:12]</bitRange>
-              <description>output enable from selected peripheral, before register override is applied</description>
-              <name>OEFROMPERI</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[9:9]</bitRange>
-              <description>output signal to pad after register override is applied</description>
-              <name>OUTTOPAD</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[8:8]</bitRange>
-              <description>output signal from selected peripheral, before register override is applied</description>
-              <name>OUTFROMPERI</name>
-            </field>
-          </fields>
-          <name>GPIO11_STATUS</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x005c</addressOffset>
-          <description>GPIO control including function select and overrides.</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[29:28]</bitRange>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>don't invert the interrupt</description>
-                  <name>NORMAL</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>invert the interrupt</description>
-                  <name>INVERT</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive interrupt low</description>
-                  <name>LOW</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive interrupt high</description>
-                  <name>HIGH</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>IRQOVER</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[17:16]</bitRange>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>don't invert the peri input</description>
-                  <name>NORMAL</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>invert the peri input</description>
-                  <name>INVERT</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive peri input low</description>
-                  <name>LOW</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive peri input high</description>
-                  <name>HIGH</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>INOVER</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[13:12]</bitRange>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>drive output enable from peripheral signal selected by funcsel</description>
-                  <name>NORMAL</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
-                  <name>INVERT</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>disable output</description>
-                  <name>DISABLE</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>enable output</description>
-                  <name>ENABLE</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>OEOVER</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[9:8]</bitRange>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>drive output from peripheral signal selected by funcsel</description>
-                  <name>NORMAL</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive output from inverse of peripheral signal selected by funcsel</description>
-                  <name>INVERT</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive output low</description>
-                  <name>LOW</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive output high</description>
-                  <name>HIGH</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>OUTOVER</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[4:0]</bitRange>
-              <description>0-31 -&gt; selects pin function according to the gpio table\n
-                31 == NULL</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>spi1_tx</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>uart1_rts</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>i2c1_scl</name>
-                  <value>3</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>pwm_b_5</name>
-                  <value>4</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>sio_11</name>
-                  <value>5</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>pio0_11</name>
-                  <value>6</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>pio1_11</name>
-                  <value>7</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>usb_muxing_extphy_suspnd</name>
-                  <value>8</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>usb_muxing_vbus_en</name>
-                  <value>9</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>null</name>
-                  <value>31</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>FUNCSEL</name>
-            </field>
-          </fields>
-          <name>GPIO11_CTRL</name>
-          <resetValue>0x0000001f</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0060</addressOffset>
-          <description>GPIO status</description>
-          <fields>
-            <field>
-              <access>read-only</access>
-              <bitRange>[26:26]</bitRange>
-              <description>interrupt to processors, after override is applied</description>
-              <name>IRQTOPROC</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[24:24]</bitRange>
-              <description>interrupt from pad before override is applied</description>
-              <name>IRQFROMPAD</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[19:19]</bitRange>
-              <description>input signal to peripheral, after override is applied</description>
-              <name>INTOPERI</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[17:17]</bitRange>
-              <description>input signal from pad, before override is applied</description>
-              <name>INFROMPAD</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[13:13]</bitRange>
-              <description>output enable to pad after register override is applied</description>
-              <name>OETOPAD</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[12:12]</bitRange>
-              <description>output enable from selected peripheral, before register override is applied</description>
-              <name>OEFROMPERI</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[9:9]</bitRange>
-              <description>output signal to pad after register override is applied</description>
-              <name>OUTTOPAD</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[8:8]</bitRange>
-              <description>output signal from selected peripheral, before register override is applied</description>
-              <name>OUTFROMPERI</name>
-            </field>
-          </fields>
-          <name>GPIO12_STATUS</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0064</addressOffset>
-          <description>GPIO control including function select and overrides.</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[29:28]</bitRange>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>don't invert the interrupt</description>
-                  <name>NORMAL</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>invert the interrupt</description>
-                  <name>INVERT</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive interrupt low</description>
-                  <name>LOW</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive interrupt high</description>
-                  <name>HIGH</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>IRQOVER</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[17:16]</bitRange>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>don't invert the peri input</description>
-                  <name>NORMAL</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>invert the peri input</description>
-                  <name>INVERT</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive peri input low</description>
-                  <name>LOW</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive peri input high</description>
-                  <name>HIGH</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>INOVER</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[13:12]</bitRange>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>drive output enable from peripheral signal selected by funcsel</description>
-                  <name>NORMAL</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
-                  <name>INVERT</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>disable output</description>
-                  <name>DISABLE</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>enable output</description>
-                  <name>ENABLE</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>OEOVER</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[9:8]</bitRange>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>drive output from peripheral signal selected by funcsel</description>
-                  <name>NORMAL</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive output from inverse of peripheral signal selected by funcsel</description>
-                  <name>INVERT</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive output low</description>
-                  <name>LOW</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive output high</description>
-                  <name>HIGH</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>OUTOVER</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[4:0]</bitRange>
-              <description>0-31 -&gt; selects pin function according to the gpio table\n
-                31 == NULL</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>spi1_rx</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>uart0_tx</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>i2c0_sda</name>
-                  <value>3</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>pwm_a_6</name>
-                  <value>4</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>sio_12</name>
-                  <value>5</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>pio0_12</name>
-                  <value>6</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>pio1_12</name>
-                  <value>7</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>usb_muxing_extphy_speed</name>
-                  <value>8</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>usb_muxing_overcurr_detect</name>
-                  <value>9</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>null</name>
-                  <value>31</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>FUNCSEL</name>
-            </field>
-          </fields>
-          <name>GPIO12_CTRL</name>
-          <resetValue>0x0000001f</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0068</addressOffset>
-          <description>GPIO status</description>
-          <fields>
-            <field>
-              <access>read-only</access>
-              <bitRange>[26:26]</bitRange>
-              <description>interrupt to processors, after override is applied</description>
-              <name>IRQTOPROC</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[24:24]</bitRange>
-              <description>interrupt from pad before override is applied</description>
-              <name>IRQFROMPAD</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[19:19]</bitRange>
-              <description>input signal to peripheral, after override is applied</description>
-              <name>INTOPERI</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[17:17]</bitRange>
-              <description>input signal from pad, before override is applied</description>
-              <name>INFROMPAD</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[13:13]</bitRange>
-              <description>output enable to pad after register override is applied</description>
-              <name>OETOPAD</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[12:12]</bitRange>
-              <description>output enable from selected peripheral, before register override is applied</description>
-              <name>OEFROMPERI</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[9:9]</bitRange>
-              <description>output signal to pad after register override is applied</description>
-              <name>OUTTOPAD</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[8:8]</bitRange>
-              <description>output signal from selected peripheral, before register override is applied</description>
-              <name>OUTFROMPERI</name>
-            </field>
-          </fields>
-          <name>GPIO13_STATUS</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x006c</addressOffset>
-          <description>GPIO control including function select and overrides.</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[29:28]</bitRange>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>don't invert the interrupt</description>
-                  <name>NORMAL</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>invert the interrupt</description>
-                  <name>INVERT</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive interrupt low</description>
-                  <name>LOW</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive interrupt high</description>
-                  <name>HIGH</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>IRQOVER</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[17:16]</bitRange>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>don't invert the peri input</description>
-                  <name>NORMAL</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>invert the peri input</description>
-                  <name>INVERT</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive peri input low</description>
-                  <name>LOW</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive peri input high</description>
-                  <name>HIGH</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>INOVER</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[13:12]</bitRange>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>drive output enable from peripheral signal selected by funcsel</description>
-                  <name>NORMAL</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
-                  <name>INVERT</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>disable output</description>
-                  <name>DISABLE</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>enable output</description>
-                  <name>ENABLE</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>OEOVER</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[9:8]</bitRange>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>drive output from peripheral signal selected by funcsel</description>
-                  <name>NORMAL</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive output from inverse of peripheral signal selected by funcsel</description>
-                  <name>INVERT</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive output low</description>
-                  <name>LOW</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive output high</description>
-                  <name>HIGH</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>OUTOVER</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[4:0]</bitRange>
-              <description>0-31 -&gt; selects pin function according to the gpio table\n
-                31 == NULL</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>spi1_ss_n</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>uart0_rx</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>i2c0_scl</name>
-                  <value>3</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>pwm_b_6</name>
-                  <value>4</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>sio_13</name>
-                  <value>5</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>pio0_13</name>
-                  <value>6</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>pio1_13</name>
-                  <value>7</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>usb_muxing_extphy_vpo</name>
-                  <value>8</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>usb_muxing_vbus_detect</name>
-                  <value>9</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>null</name>
-                  <value>31</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>FUNCSEL</name>
-            </field>
-          </fields>
-          <name>GPIO13_CTRL</name>
-          <resetValue>0x0000001f</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0070</addressOffset>
-          <description>GPIO status</description>
-          <fields>
-            <field>
-              <access>read-only</access>
-              <bitRange>[26:26]</bitRange>
-              <description>interrupt to processors, after override is applied</description>
-              <name>IRQTOPROC</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[24:24]</bitRange>
-              <description>interrupt from pad before override is applied</description>
-              <name>IRQFROMPAD</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[19:19]</bitRange>
-              <description>input signal to peripheral, after override is applied</description>
-              <name>INTOPERI</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[17:17]</bitRange>
-              <description>input signal from pad, before override is applied</description>
-              <name>INFROMPAD</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[13:13]</bitRange>
-              <description>output enable to pad after register override is applied</description>
-              <name>OETOPAD</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[12:12]</bitRange>
-              <description>output enable from selected peripheral, before register override is applied</description>
-              <name>OEFROMPERI</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[9:9]</bitRange>
-              <description>output signal to pad after register override is applied</description>
-              <name>OUTTOPAD</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[8:8]</bitRange>
-              <description>output signal from selected peripheral, before register override is applied</description>
-              <name>OUTFROMPERI</name>
-            </field>
-          </fields>
-          <name>GPIO14_STATUS</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0074</addressOffset>
-          <description>GPIO control including function select and overrides.</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[29:28]</bitRange>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>don't invert the interrupt</description>
-                  <name>NORMAL</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>invert the interrupt</description>
-                  <name>INVERT</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive interrupt low</description>
-                  <name>LOW</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive interrupt high</description>
-                  <name>HIGH</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>IRQOVER</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[17:16]</bitRange>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>don't invert the peri input</description>
-                  <name>NORMAL</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>invert the peri input</description>
-                  <name>INVERT</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive peri input low</description>
-                  <name>LOW</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive peri input high</description>
-                  <name>HIGH</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>INOVER</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[13:12]</bitRange>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>drive output enable from peripheral signal selected by funcsel</description>
-                  <name>NORMAL</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
-                  <name>INVERT</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>disable output</description>
-                  <name>DISABLE</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>enable output</description>
-                  <name>ENABLE</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>OEOVER</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[9:8]</bitRange>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>drive output from peripheral signal selected by funcsel</description>
-                  <name>NORMAL</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive output from inverse of peripheral signal selected by funcsel</description>
-                  <name>INVERT</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive output low</description>
-                  <name>LOW</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive output high</description>
-                  <name>HIGH</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>OUTOVER</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[4:0]</bitRange>
-              <description>0-31 -&gt; selects pin function according to the gpio table\n
-                31 == NULL</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>spi1_sclk</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>uart0_cts</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>i2c1_sda</name>
-                  <value>3</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>pwm_a_7</name>
-                  <value>4</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>sio_14</name>
-                  <value>5</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>pio0_14</name>
-                  <value>6</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>pio1_14</name>
-                  <value>7</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>usb_muxing_extphy_vmo</name>
-                  <value>8</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>usb_muxing_vbus_en</name>
-                  <value>9</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>null</name>
-                  <value>31</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>FUNCSEL</name>
-            </field>
-          </fields>
-          <name>GPIO14_CTRL</name>
-          <resetValue>0x0000001f</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0078</addressOffset>
-          <description>GPIO status</description>
-          <fields>
-            <field>
-              <access>read-only</access>
-              <bitRange>[26:26]</bitRange>
-              <description>interrupt to processors, after override is applied</description>
-              <name>IRQTOPROC</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[24:24]</bitRange>
-              <description>interrupt from pad before override is applied</description>
-              <name>IRQFROMPAD</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[19:19]</bitRange>
-              <description>input signal to peripheral, after override is applied</description>
-              <name>INTOPERI</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[17:17]</bitRange>
-              <description>input signal from pad, before override is applied</description>
-              <name>INFROMPAD</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[13:13]</bitRange>
-              <description>output enable to pad after register override is applied</description>
-              <name>OETOPAD</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[12:12]</bitRange>
-              <description>output enable from selected peripheral, before register override is applied</description>
-              <name>OEFROMPERI</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[9:9]</bitRange>
-              <description>output signal to pad after register override is applied</description>
-              <name>OUTTOPAD</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[8:8]</bitRange>
-              <description>output signal from selected peripheral, before register override is applied</description>
-              <name>OUTFROMPERI</name>
-            </field>
-          </fields>
-          <name>GPIO15_STATUS</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x007c</addressOffset>
-          <description>GPIO control including function select and overrides.</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[29:28]</bitRange>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>don't invert the interrupt</description>
-                  <name>NORMAL</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>invert the interrupt</description>
-                  <name>INVERT</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive interrupt low</description>
-                  <name>LOW</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive interrupt high</description>
-                  <name>HIGH</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>IRQOVER</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[17:16]</bitRange>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>don't invert the peri input</description>
-                  <name>NORMAL</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>invert the peri input</description>
-                  <name>INVERT</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive peri input low</description>
-                  <name>LOW</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive peri input high</description>
-                  <name>HIGH</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>INOVER</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[13:12]</bitRange>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>drive output enable from peripheral signal selected by funcsel</description>
-                  <name>NORMAL</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
-                  <name>INVERT</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>disable output</description>
-                  <name>DISABLE</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>enable output</description>
-                  <name>ENABLE</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>OEOVER</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[9:8]</bitRange>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>drive output from peripheral signal selected by funcsel</description>
-                  <name>NORMAL</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive output from inverse of peripheral signal selected by funcsel</description>
-                  <name>INVERT</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive output low</description>
-                  <name>LOW</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive output high</description>
-                  <name>HIGH</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>OUTOVER</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[4:0]</bitRange>
-              <description>0-31 -&gt; selects pin function according to the gpio table\n
-                31 == NULL</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>spi1_tx</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>uart0_rts</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>i2c1_scl</name>
-                  <value>3</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>pwm_b_7</name>
-                  <value>4</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>sio_15</name>
-                  <value>5</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>pio0_15</name>
-                  <value>6</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>pio1_15</name>
-                  <value>7</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>usb_muxing_digital_dp</name>
-                  <value>8</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>usb_muxing_overcurr_detect</name>
-                  <value>9</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>null</name>
-                  <value>31</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>FUNCSEL</name>
-            </field>
-          </fields>
-          <name>GPIO15_CTRL</name>
-          <resetValue>0x0000001f</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0080</addressOffset>
-          <description>GPIO status</description>
-          <fields>
-            <field>
-              <access>read-only</access>
-              <bitRange>[26:26]</bitRange>
-              <description>interrupt to processors, after override is applied</description>
-              <name>IRQTOPROC</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[24:24]</bitRange>
-              <description>interrupt from pad before override is applied</description>
-              <name>IRQFROMPAD</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[19:19]</bitRange>
-              <description>input signal to peripheral, after override is applied</description>
-              <name>INTOPERI</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[17:17]</bitRange>
-              <description>input signal from pad, before override is applied</description>
-              <name>INFROMPAD</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[13:13]</bitRange>
-              <description>output enable to pad after register override is applied</description>
-              <name>OETOPAD</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[12:12]</bitRange>
-              <description>output enable from selected peripheral, before register override is applied</description>
-              <name>OEFROMPERI</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[9:9]</bitRange>
-              <description>output signal to pad after register override is applied</description>
-              <name>OUTTOPAD</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[8:8]</bitRange>
-              <description>output signal from selected peripheral, before register override is applied</description>
-              <name>OUTFROMPERI</name>
-            </field>
-          </fields>
-          <name>GPIO16_STATUS</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0084</addressOffset>
-          <description>GPIO control including function select and overrides.</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[29:28]</bitRange>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>don't invert the interrupt</description>
-                  <name>NORMAL</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>invert the interrupt</description>
-                  <name>INVERT</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive interrupt low</description>
-                  <name>LOW</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive interrupt high</description>
-                  <name>HIGH</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>IRQOVER</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[17:16]</bitRange>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>don't invert the peri input</description>
-                  <name>NORMAL</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>invert the peri input</description>
-                  <name>INVERT</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive peri input low</description>
-                  <name>LOW</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive peri input high</description>
-                  <name>HIGH</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>INOVER</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[13:12]</bitRange>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>drive output enable from peripheral signal selected by funcsel</description>
-                  <name>NORMAL</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
-                  <name>INVERT</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>disable output</description>
-                  <name>DISABLE</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>enable output</description>
-                  <name>ENABLE</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>OEOVER</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[9:8]</bitRange>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>drive output from peripheral signal selected by funcsel</description>
-                  <name>NORMAL</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive output from inverse of peripheral signal selected by funcsel</description>
-                  <name>INVERT</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive output low</description>
-                  <name>LOW</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive output high</description>
-                  <name>HIGH</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>OUTOVER</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[4:0]</bitRange>
-              <description>0-31 -&gt; selects pin function according to the gpio table\n
-                31 == NULL</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>spi0_rx</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>uart0_tx</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>i2c0_sda</name>
-                  <value>3</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>pwm_a_0</name>
-                  <value>4</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>sio_16</name>
-                  <value>5</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>pio0_16</name>
-                  <value>6</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>pio1_16</name>
-                  <value>7</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>usb_muxing_digital_dm</name>
-                  <value>8</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>usb_muxing_vbus_detect</name>
-                  <value>9</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>null</name>
-                  <value>31</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>FUNCSEL</name>
-            </field>
-          </fields>
-          <name>GPIO16_CTRL</name>
-          <resetValue>0x0000001f</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0088</addressOffset>
-          <description>GPIO status</description>
-          <fields>
-            <field>
-              <access>read-only</access>
-              <bitRange>[26:26]</bitRange>
-              <description>interrupt to processors, after override is applied</description>
-              <name>IRQTOPROC</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[24:24]</bitRange>
-              <description>interrupt from pad before override is applied</description>
-              <name>IRQFROMPAD</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[19:19]</bitRange>
-              <description>input signal to peripheral, after override is applied</description>
-              <name>INTOPERI</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[17:17]</bitRange>
-              <description>input signal from pad, before override is applied</description>
-              <name>INFROMPAD</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[13:13]</bitRange>
-              <description>output enable to pad after register override is applied</description>
-              <name>OETOPAD</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[12:12]</bitRange>
-              <description>output enable from selected peripheral, before register override is applied</description>
-              <name>OEFROMPERI</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[9:9]</bitRange>
-              <description>output signal to pad after register override is applied</description>
-              <name>OUTTOPAD</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[8:8]</bitRange>
-              <description>output signal from selected peripheral, before register override is applied</description>
-              <name>OUTFROMPERI</name>
-            </field>
-          </fields>
-          <name>GPIO17_STATUS</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x008c</addressOffset>
-          <description>GPIO control including function select and overrides.</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[29:28]</bitRange>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>don't invert the interrupt</description>
-                  <name>NORMAL</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>invert the interrupt</description>
-                  <name>INVERT</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive interrupt low</description>
-                  <name>LOW</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive interrupt high</description>
-                  <name>HIGH</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>IRQOVER</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[17:16]</bitRange>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>don't invert the peri input</description>
-                  <name>NORMAL</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>invert the peri input</description>
-                  <name>INVERT</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive peri input low</description>
-                  <name>LOW</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive peri input high</description>
-                  <name>HIGH</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>INOVER</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[13:12]</bitRange>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>drive output enable from peripheral signal selected by funcsel</description>
-                  <name>NORMAL</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
-                  <name>INVERT</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>disable output</description>
-                  <name>DISABLE</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>enable output</description>
-                  <name>ENABLE</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>OEOVER</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[9:8]</bitRange>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>drive output from peripheral signal selected by funcsel</description>
-                  <name>NORMAL</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive output from inverse of peripheral signal selected by funcsel</description>
-                  <name>INVERT</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive output low</description>
-                  <name>LOW</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive output high</description>
-                  <name>HIGH</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>OUTOVER</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[4:0]</bitRange>
-              <description>0-31 -&gt; selects pin function according to the gpio table\n
-                31 == NULL</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>spi0_ss_n</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>uart0_rx</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>i2c0_scl</name>
-                  <value>3</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>pwm_b_0</name>
-                  <value>4</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>sio_17</name>
-                  <value>5</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>pio0_17</name>
-                  <value>6</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>pio1_17</name>
-                  <value>7</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>usb_muxing_vbus_en</name>
-                  <value>9</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>null</name>
-                  <value>31</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>FUNCSEL</name>
-            </field>
-          </fields>
-          <name>GPIO17_CTRL</name>
-          <resetValue>0x0000001f</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0090</addressOffset>
-          <description>GPIO status</description>
-          <fields>
-            <field>
-              <access>read-only</access>
-              <bitRange>[26:26]</bitRange>
-              <description>interrupt to processors, after override is applied</description>
-              <name>IRQTOPROC</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[24:24]</bitRange>
-              <description>interrupt from pad before override is applied</description>
-              <name>IRQFROMPAD</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[19:19]</bitRange>
-              <description>input signal to peripheral, after override is applied</description>
-              <name>INTOPERI</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[17:17]</bitRange>
-              <description>input signal from pad, before override is applied</description>
-              <name>INFROMPAD</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[13:13]</bitRange>
-              <description>output enable to pad after register override is applied</description>
-              <name>OETOPAD</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[12:12]</bitRange>
-              <description>output enable from selected peripheral, before register override is applied</description>
-              <name>OEFROMPERI</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[9:9]</bitRange>
-              <description>output signal to pad after register override is applied</description>
-              <name>OUTTOPAD</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[8:8]</bitRange>
-              <description>output signal from selected peripheral, before register override is applied</description>
-              <name>OUTFROMPERI</name>
-            </field>
-          </fields>
-          <name>GPIO18_STATUS</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0094</addressOffset>
-          <description>GPIO control including function select and overrides.</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[29:28]</bitRange>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>don't invert the interrupt</description>
-                  <name>NORMAL</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>invert the interrupt</description>
-                  <name>INVERT</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive interrupt low</description>
-                  <name>LOW</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive interrupt high</description>
-                  <name>HIGH</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>IRQOVER</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[17:16]</bitRange>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>don't invert the peri input</description>
-                  <name>NORMAL</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>invert the peri input</description>
-                  <name>INVERT</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive peri input low</description>
-                  <name>LOW</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive peri input high</description>
-                  <name>HIGH</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>INOVER</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[13:12]</bitRange>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>drive output enable from peripheral signal selected by funcsel</description>
-                  <name>NORMAL</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
-                  <name>INVERT</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>disable output</description>
-                  <name>DISABLE</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>enable output</description>
-                  <name>ENABLE</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>OEOVER</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[9:8]</bitRange>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>drive output from peripheral signal selected by funcsel</description>
-                  <name>NORMAL</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive output from inverse of peripheral signal selected by funcsel</description>
-                  <name>INVERT</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive output low</description>
-                  <name>LOW</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive output high</description>
-                  <name>HIGH</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>OUTOVER</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[4:0]</bitRange>
-              <description>0-31 -&gt; selects pin function according to the gpio table\n
-                31 == NULL</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>spi0_sclk</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>uart0_cts</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>i2c1_sda</name>
-                  <value>3</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>pwm_a_1</name>
-                  <value>4</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>sio_18</name>
-                  <value>5</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>pio0_18</name>
-                  <value>6</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>pio1_18</name>
-                  <value>7</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>usb_muxing_overcurr_detect</name>
-                  <value>9</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>null</name>
-                  <value>31</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>FUNCSEL</name>
-            </field>
-          </fields>
-          <name>GPIO18_CTRL</name>
-          <resetValue>0x0000001f</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0098</addressOffset>
-          <description>GPIO status</description>
-          <fields>
-            <field>
-              <access>read-only</access>
-              <bitRange>[26:26]</bitRange>
-              <description>interrupt to processors, after override is applied</description>
-              <name>IRQTOPROC</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[24:24]</bitRange>
-              <description>interrupt from pad before override is applied</description>
-              <name>IRQFROMPAD</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[19:19]</bitRange>
-              <description>input signal to peripheral, after override is applied</description>
-              <name>INTOPERI</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[17:17]</bitRange>
-              <description>input signal from pad, before override is applied</description>
-              <name>INFROMPAD</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[13:13]</bitRange>
-              <description>output enable to pad after register override is applied</description>
-              <name>OETOPAD</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[12:12]</bitRange>
-              <description>output enable from selected peripheral, before register override is applied</description>
-              <name>OEFROMPERI</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[9:9]</bitRange>
-              <description>output signal to pad after register override is applied</description>
-              <name>OUTTOPAD</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[8:8]</bitRange>
-              <description>output signal from selected peripheral, before register override is applied</description>
-              <name>OUTFROMPERI</name>
-            </field>
-          </fields>
-          <name>GPIO19_STATUS</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x009c</addressOffset>
-          <description>GPIO control including function select and overrides.</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[29:28]</bitRange>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>don't invert the interrupt</description>
-                  <name>NORMAL</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>invert the interrupt</description>
-                  <name>INVERT</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive interrupt low</description>
-                  <name>LOW</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive interrupt high</description>
-                  <name>HIGH</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>IRQOVER</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[17:16]</bitRange>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>don't invert the peri input</description>
-                  <name>NORMAL</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>invert the peri input</description>
-                  <name>INVERT</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive peri input low</description>
-                  <name>LOW</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive peri input high</description>
-                  <name>HIGH</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>INOVER</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[13:12]</bitRange>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>drive output enable from peripheral signal selected by funcsel</description>
-                  <name>NORMAL</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
-                  <name>INVERT</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>disable output</description>
-                  <name>DISABLE</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>enable output</description>
-                  <name>ENABLE</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>OEOVER</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[9:8]</bitRange>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>drive output from peripheral signal selected by funcsel</description>
-                  <name>NORMAL</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive output from inverse of peripheral signal selected by funcsel</description>
-                  <name>INVERT</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive output low</description>
-                  <name>LOW</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive output high</description>
-                  <name>HIGH</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>OUTOVER</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[4:0]</bitRange>
-              <description>0-31 -&gt; selects pin function according to the gpio table\n
-                31 == NULL</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>spi0_tx</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>uart0_rts</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>i2c1_scl</name>
-                  <value>3</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>pwm_b_1</name>
-                  <value>4</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>sio_19</name>
-                  <value>5</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>pio0_19</name>
-                  <value>6</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>pio1_19</name>
-                  <value>7</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>usb_muxing_vbus_detect</name>
-                  <value>9</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>null</name>
-                  <value>31</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>FUNCSEL</name>
-            </field>
-          </fields>
-          <name>GPIO19_CTRL</name>
-          <resetValue>0x0000001f</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x00a0</addressOffset>
-          <description>GPIO status</description>
-          <fields>
-            <field>
-              <access>read-only</access>
-              <bitRange>[26:26]</bitRange>
-              <description>interrupt to processors, after override is applied</description>
-              <name>IRQTOPROC</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[24:24]</bitRange>
-              <description>interrupt from pad before override is applied</description>
-              <name>IRQFROMPAD</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[19:19]</bitRange>
-              <description>input signal to peripheral, after override is applied</description>
-              <name>INTOPERI</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[17:17]</bitRange>
-              <description>input signal from pad, before override is applied</description>
-              <name>INFROMPAD</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[13:13]</bitRange>
-              <description>output enable to pad after register override is applied</description>
-              <name>OETOPAD</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[12:12]</bitRange>
-              <description>output enable from selected peripheral, before register override is applied</description>
-              <name>OEFROMPERI</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[9:9]</bitRange>
-              <description>output signal to pad after register override is applied</description>
-              <name>OUTTOPAD</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[8:8]</bitRange>
-              <description>output signal from selected peripheral, before register override is applied</description>
-              <name>OUTFROMPERI</name>
-            </field>
-          </fields>
-          <name>GPIO20_STATUS</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x00a4</addressOffset>
-          <description>GPIO control including function select and overrides.</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[29:28]</bitRange>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>don't invert the interrupt</description>
-                  <name>NORMAL</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>invert the interrupt</description>
-                  <name>INVERT</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive interrupt low</description>
-                  <name>LOW</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive interrupt high</description>
-                  <name>HIGH</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>IRQOVER</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[17:16]</bitRange>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>don't invert the peri input</description>
-                  <name>NORMAL</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>invert the peri input</description>
-                  <name>INVERT</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive peri input low</description>
-                  <name>LOW</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive peri input high</description>
-                  <name>HIGH</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>INOVER</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[13:12]</bitRange>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>drive output enable from peripheral signal selected by funcsel</description>
-                  <name>NORMAL</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
-                  <name>INVERT</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>disable output</description>
-                  <name>DISABLE</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>enable output</description>
-                  <name>ENABLE</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>OEOVER</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[9:8]</bitRange>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>drive output from peripheral signal selected by funcsel</description>
-                  <name>NORMAL</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive output from inverse of peripheral signal selected by funcsel</description>
-                  <name>INVERT</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive output low</description>
-                  <name>LOW</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive output high</description>
-                  <name>HIGH</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>OUTOVER</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[4:0]</bitRange>
-              <description>0-31 -&gt; selects pin function according to the gpio table\n
-                31 == NULL</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>spi0_rx</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>uart1_tx</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>i2c0_sda</name>
-                  <value>3</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>pwm_a_2</name>
-                  <value>4</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>sio_20</name>
-                  <value>5</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>pio0_20</name>
-                  <value>6</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>pio1_20</name>
-                  <value>7</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>clocks_gpin_0</name>
-                  <value>8</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>usb_muxing_vbus_en</name>
-                  <value>9</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>null</name>
-                  <value>31</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>FUNCSEL</name>
-            </field>
-          </fields>
-          <name>GPIO20_CTRL</name>
-          <resetValue>0x0000001f</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x00a8</addressOffset>
-          <description>GPIO status</description>
-          <fields>
-            <field>
-              <access>read-only</access>
-              <bitRange>[26:26]</bitRange>
-              <description>interrupt to processors, after override is applied</description>
-              <name>IRQTOPROC</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[24:24]</bitRange>
-              <description>interrupt from pad before override is applied</description>
-              <name>IRQFROMPAD</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[19:19]</bitRange>
-              <description>input signal to peripheral, after override is applied</description>
-              <name>INTOPERI</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[17:17]</bitRange>
-              <description>input signal from pad, before override is applied</description>
-              <name>INFROMPAD</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[13:13]</bitRange>
-              <description>output enable to pad after register override is applied</description>
-              <name>OETOPAD</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[12:12]</bitRange>
-              <description>output enable from selected peripheral, before register override is applied</description>
-              <name>OEFROMPERI</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[9:9]</bitRange>
-              <description>output signal to pad after register override is applied</description>
-              <name>OUTTOPAD</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[8:8]</bitRange>
-              <description>output signal from selected peripheral, before register override is applied</description>
-              <name>OUTFROMPERI</name>
-            </field>
-          </fields>
-          <name>GPIO21_STATUS</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x00ac</addressOffset>
-          <description>GPIO control including function select and overrides.</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[29:28]</bitRange>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>don't invert the interrupt</description>
-                  <name>NORMAL</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>invert the interrupt</description>
-                  <name>INVERT</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive interrupt low</description>
-                  <name>LOW</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive interrupt high</description>
-                  <name>HIGH</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>IRQOVER</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[17:16]</bitRange>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>don't invert the peri input</description>
-                  <name>NORMAL</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>invert the peri input</description>
-                  <name>INVERT</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive peri input low</description>
-                  <name>LOW</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive peri input high</description>
-                  <name>HIGH</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>INOVER</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[13:12]</bitRange>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>drive output enable from peripheral signal selected by funcsel</description>
-                  <name>NORMAL</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
-                  <name>INVERT</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>disable output</description>
-                  <name>DISABLE</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>enable output</description>
-                  <name>ENABLE</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>OEOVER</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[9:8]</bitRange>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>drive output from peripheral signal selected by funcsel</description>
-                  <name>NORMAL</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive output from inverse of peripheral signal selected by funcsel</description>
-                  <name>INVERT</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive output low</description>
-                  <name>LOW</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive output high</description>
-                  <name>HIGH</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>OUTOVER</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[4:0]</bitRange>
-              <description>0-31 -&gt; selects pin function according to the gpio table\n
-                31 == NULL</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>spi0_ss_n</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>uart1_rx</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>i2c0_scl</name>
-                  <value>3</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>pwm_b_2</name>
-                  <value>4</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>sio_21</name>
-                  <value>5</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>pio0_21</name>
-                  <value>6</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>pio1_21</name>
-                  <value>7</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>clocks_gpout_0</name>
-                  <value>8</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>usb_muxing_overcurr_detect</name>
-                  <value>9</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>null</name>
-                  <value>31</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>FUNCSEL</name>
-            </field>
-          </fields>
-          <name>GPIO21_CTRL</name>
-          <resetValue>0x0000001f</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x00b0</addressOffset>
-          <description>GPIO status</description>
-          <fields>
-            <field>
-              <access>read-only</access>
-              <bitRange>[26:26]</bitRange>
-              <description>interrupt to processors, after override is applied</description>
-              <name>IRQTOPROC</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[24:24]</bitRange>
-              <description>interrupt from pad before override is applied</description>
-              <name>IRQFROMPAD</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[19:19]</bitRange>
-              <description>input signal to peripheral, after override is applied</description>
-              <name>INTOPERI</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[17:17]</bitRange>
-              <description>input signal from pad, before override is applied</description>
-              <name>INFROMPAD</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[13:13]</bitRange>
-              <description>output enable to pad after register override is applied</description>
-              <name>OETOPAD</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[12:12]</bitRange>
-              <description>output enable from selected peripheral, before register override is applied</description>
-              <name>OEFROMPERI</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[9:9]</bitRange>
-              <description>output signal to pad after register override is applied</description>
-              <name>OUTTOPAD</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[8:8]</bitRange>
-              <description>output signal from selected peripheral, before register override is applied</description>
-              <name>OUTFROMPERI</name>
-            </field>
-          </fields>
-          <name>GPIO22_STATUS</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x00b4</addressOffset>
-          <description>GPIO control including function select and overrides.</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[29:28]</bitRange>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>don't invert the interrupt</description>
-                  <name>NORMAL</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>invert the interrupt</description>
-                  <name>INVERT</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive interrupt low</description>
-                  <name>LOW</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive interrupt high</description>
-                  <name>HIGH</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>IRQOVER</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[17:16]</bitRange>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>don't invert the peri input</description>
-                  <name>NORMAL</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>invert the peri input</description>
-                  <name>INVERT</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive peri input low</description>
-                  <name>LOW</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive peri input high</description>
-                  <name>HIGH</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>INOVER</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[13:12]</bitRange>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>drive output enable from peripheral signal selected by funcsel</description>
-                  <name>NORMAL</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
-                  <name>INVERT</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>disable output</description>
-                  <name>DISABLE</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>enable output</description>
-                  <name>ENABLE</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>OEOVER</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[9:8]</bitRange>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>drive output from peripheral signal selected by funcsel</description>
-                  <name>NORMAL</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive output from inverse of peripheral signal selected by funcsel</description>
-                  <name>INVERT</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive output low</description>
-                  <name>LOW</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive output high</description>
-                  <name>HIGH</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>OUTOVER</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[4:0]</bitRange>
-              <description>0-31 -&gt; selects pin function according to the gpio table\n
-                31 == NULL</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>spi0_sclk</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>uart1_cts</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>i2c1_sda</name>
-                  <value>3</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>pwm_a_3</name>
-                  <value>4</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>sio_22</name>
-                  <value>5</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>pio0_22</name>
-                  <value>6</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>pio1_22</name>
-                  <value>7</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>clocks_gpin_1</name>
-                  <value>8</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>usb_muxing_vbus_detect</name>
-                  <value>9</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>null</name>
-                  <value>31</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>FUNCSEL</name>
-            </field>
-          </fields>
-          <name>GPIO22_CTRL</name>
-          <resetValue>0x0000001f</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x00b8</addressOffset>
-          <description>GPIO status</description>
-          <fields>
-            <field>
-              <access>read-only</access>
-              <bitRange>[26:26]</bitRange>
-              <description>interrupt to processors, after override is applied</description>
-              <name>IRQTOPROC</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[24:24]</bitRange>
-              <description>interrupt from pad before override is applied</description>
-              <name>IRQFROMPAD</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[19:19]</bitRange>
-              <description>input signal to peripheral, after override is applied</description>
-              <name>INTOPERI</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[17:17]</bitRange>
-              <description>input signal from pad, before override is applied</description>
-              <name>INFROMPAD</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[13:13]</bitRange>
-              <description>output enable to pad after register override is applied</description>
-              <name>OETOPAD</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[12:12]</bitRange>
-              <description>output enable from selected peripheral, before register override is applied</description>
-              <name>OEFROMPERI</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[9:9]</bitRange>
-              <description>output signal to pad after register override is applied</description>
-              <name>OUTTOPAD</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[8:8]</bitRange>
-              <description>output signal from selected peripheral, before register override is applied</description>
-              <name>OUTFROMPERI</name>
-            </field>
-          </fields>
-          <name>GPIO23_STATUS</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x00bc</addressOffset>
-          <description>GPIO control including function select and overrides.</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[29:28]</bitRange>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>don't invert the interrupt</description>
-                  <name>NORMAL</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>invert the interrupt</description>
-                  <name>INVERT</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive interrupt low</description>
-                  <name>LOW</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive interrupt high</description>
-                  <name>HIGH</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>IRQOVER</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[17:16]</bitRange>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>don't invert the peri input</description>
-                  <name>NORMAL</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>invert the peri input</description>
-                  <name>INVERT</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive peri input low</description>
-                  <name>LOW</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive peri input high</description>
-                  <name>HIGH</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>INOVER</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[13:12]</bitRange>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>drive output enable from peripheral signal selected by funcsel</description>
-                  <name>NORMAL</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
-                  <name>INVERT</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>disable output</description>
-                  <name>DISABLE</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>enable output</description>
-                  <name>ENABLE</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>OEOVER</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[9:8]</bitRange>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>drive output from peripheral signal selected by funcsel</description>
-                  <name>NORMAL</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive output from inverse of peripheral signal selected by funcsel</description>
-                  <name>INVERT</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive output low</description>
-                  <name>LOW</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive output high</description>
-                  <name>HIGH</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>OUTOVER</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[4:0]</bitRange>
-              <description>0-31 -&gt; selects pin function according to the gpio table\n
-                31 == NULL</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>spi0_tx</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>uart1_rts</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>i2c1_scl</name>
-                  <value>3</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>pwm_b_3</name>
-                  <value>4</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>sio_23</name>
-                  <value>5</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>pio0_23</name>
-                  <value>6</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>pio1_23</name>
-                  <value>7</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>clocks_gpout_1</name>
-                  <value>8</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>usb_muxing_vbus_en</name>
-                  <value>9</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>null</name>
-                  <value>31</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>FUNCSEL</name>
-            </field>
-          </fields>
-          <name>GPIO23_CTRL</name>
-          <resetValue>0x0000001f</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x00c0</addressOffset>
-          <description>GPIO status</description>
-          <fields>
-            <field>
-              <access>read-only</access>
-              <bitRange>[26:26]</bitRange>
-              <description>interrupt to processors, after override is applied</description>
-              <name>IRQTOPROC</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[24:24]</bitRange>
-              <description>interrupt from pad before override is applied</description>
-              <name>IRQFROMPAD</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[19:19]</bitRange>
-              <description>input signal to peripheral, after override is applied</description>
-              <name>INTOPERI</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[17:17]</bitRange>
-              <description>input signal from pad, before override is applied</description>
-              <name>INFROMPAD</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[13:13]</bitRange>
-              <description>output enable to pad after register override is applied</description>
-              <name>OETOPAD</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[12:12]</bitRange>
-              <description>output enable from selected peripheral, before register override is applied</description>
-              <name>OEFROMPERI</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[9:9]</bitRange>
-              <description>output signal to pad after register override is applied</description>
-              <name>OUTTOPAD</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[8:8]</bitRange>
-              <description>output signal from selected peripheral, before register override is applied</description>
-              <name>OUTFROMPERI</name>
-            </field>
-          </fields>
-          <name>GPIO24_STATUS</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x00c4</addressOffset>
-          <description>GPIO control including function select and overrides.</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[29:28]</bitRange>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>don't invert the interrupt</description>
-                  <name>NORMAL</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>invert the interrupt</description>
-                  <name>INVERT</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive interrupt low</description>
-                  <name>LOW</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive interrupt high</description>
-                  <name>HIGH</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>IRQOVER</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[17:16]</bitRange>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>don't invert the peri input</description>
-                  <name>NORMAL</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>invert the peri input</description>
-                  <name>INVERT</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive peri input low</description>
-                  <name>LOW</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive peri input high</description>
-                  <name>HIGH</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>INOVER</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[13:12]</bitRange>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>drive output enable from peripheral signal selected by funcsel</description>
-                  <name>NORMAL</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
-                  <name>INVERT</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>disable output</description>
-                  <name>DISABLE</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>enable output</description>
-                  <name>ENABLE</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>OEOVER</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[9:8]</bitRange>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>drive output from peripheral signal selected by funcsel</description>
-                  <name>NORMAL</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive output from inverse of peripheral signal selected by funcsel</description>
-                  <name>INVERT</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive output low</description>
-                  <name>LOW</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive output high</description>
-                  <name>HIGH</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>OUTOVER</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[4:0]</bitRange>
-              <description>0-31 -&gt; selects pin function according to the gpio table\n
-                31 == NULL</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>spi1_rx</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>uart1_tx</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>i2c0_sda</name>
-                  <value>3</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>pwm_a_4</name>
-                  <value>4</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>sio_24</name>
-                  <value>5</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>pio0_24</name>
-                  <value>6</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>pio1_24</name>
-                  <value>7</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>clocks_gpout_2</name>
-                  <value>8</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>usb_muxing_overcurr_detect</name>
-                  <value>9</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>null</name>
-                  <value>31</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>FUNCSEL</name>
-            </field>
-          </fields>
-          <name>GPIO24_CTRL</name>
-          <resetValue>0x0000001f</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x00c8</addressOffset>
-          <description>GPIO status</description>
-          <fields>
-            <field>
-              <access>read-only</access>
-              <bitRange>[26:26]</bitRange>
-              <description>interrupt to processors, after override is applied</description>
-              <name>IRQTOPROC</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[24:24]</bitRange>
-              <description>interrupt from pad before override is applied</description>
-              <name>IRQFROMPAD</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[19:19]</bitRange>
-              <description>input signal to peripheral, after override is applied</description>
-              <name>INTOPERI</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[17:17]</bitRange>
-              <description>input signal from pad, before override is applied</description>
-              <name>INFROMPAD</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[13:13]</bitRange>
-              <description>output enable to pad after register override is applied</description>
-              <name>OETOPAD</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[12:12]</bitRange>
-              <description>output enable from selected peripheral, before register override is applied</description>
-              <name>OEFROMPERI</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[9:9]</bitRange>
-              <description>output signal to pad after register override is applied</description>
-              <name>OUTTOPAD</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[8:8]</bitRange>
-              <description>output signal from selected peripheral, before register override is applied</description>
-              <name>OUTFROMPERI</name>
-            </field>
-          </fields>
-          <name>GPIO25_STATUS</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x00cc</addressOffset>
-          <description>GPIO control including function select and overrides.</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[29:28]</bitRange>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>don't invert the interrupt</description>
-                  <name>NORMAL</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>invert the interrupt</description>
-                  <name>INVERT</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive interrupt low</description>
-                  <name>LOW</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive interrupt high</description>
-                  <name>HIGH</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>IRQOVER</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[17:16]</bitRange>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>don't invert the peri input</description>
-                  <name>NORMAL</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>invert the peri input</description>
-                  <name>INVERT</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive peri input low</description>
-                  <name>LOW</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive peri input high</description>
-                  <name>HIGH</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>INOVER</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[13:12]</bitRange>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>drive output enable from peripheral signal selected by funcsel</description>
-                  <name>NORMAL</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
-                  <name>INVERT</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>disable output</description>
-                  <name>DISABLE</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>enable output</description>
-                  <name>ENABLE</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>OEOVER</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[9:8]</bitRange>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>drive output from peripheral signal selected by funcsel</description>
-                  <name>NORMAL</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive output from inverse of peripheral signal selected by funcsel</description>
-                  <name>INVERT</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive output low</description>
-                  <name>LOW</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive output high</description>
-                  <name>HIGH</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>OUTOVER</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[4:0]</bitRange>
-              <description>0-31 -&gt; selects pin function according to the gpio table\n
-                31 == NULL</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>spi1_ss_n</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>uart1_rx</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>i2c0_scl</name>
-                  <value>3</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>pwm_b_4</name>
-                  <value>4</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>sio_25</name>
-                  <value>5</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>pio0_25</name>
-                  <value>6</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>pio1_25</name>
-                  <value>7</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>clocks_gpout_3</name>
-                  <value>8</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>usb_muxing_vbus_detect</name>
-                  <value>9</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>null</name>
-                  <value>31</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>FUNCSEL</name>
-            </field>
-          </fields>
-          <name>GPIO25_CTRL</name>
-          <resetValue>0x0000001f</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x00d0</addressOffset>
-          <description>GPIO status</description>
-          <fields>
-            <field>
-              <access>read-only</access>
-              <bitRange>[26:26]</bitRange>
-              <description>interrupt to processors, after override is applied</description>
-              <name>IRQTOPROC</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[24:24]</bitRange>
-              <description>interrupt from pad before override is applied</description>
-              <name>IRQFROMPAD</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[19:19]</bitRange>
-              <description>input signal to peripheral, after override is applied</description>
-              <name>INTOPERI</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[17:17]</bitRange>
-              <description>input signal from pad, before override is applied</description>
-              <name>INFROMPAD</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[13:13]</bitRange>
-              <description>output enable to pad after register override is applied</description>
-              <name>OETOPAD</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[12:12]</bitRange>
-              <description>output enable from selected peripheral, before register override is applied</description>
-              <name>OEFROMPERI</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[9:9]</bitRange>
-              <description>output signal to pad after register override is applied</description>
-              <name>OUTTOPAD</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[8:8]</bitRange>
-              <description>output signal from selected peripheral, before register override is applied</description>
-              <name>OUTFROMPERI</name>
-            </field>
-          </fields>
-          <name>GPIO26_STATUS</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x00d4</addressOffset>
-          <description>GPIO control including function select and overrides.</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[29:28]</bitRange>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>don't invert the interrupt</description>
-                  <name>NORMAL</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>invert the interrupt</description>
-                  <name>INVERT</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive interrupt low</description>
-                  <name>LOW</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive interrupt high</description>
-                  <name>HIGH</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>IRQOVER</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[17:16]</bitRange>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>don't invert the peri input</description>
-                  <name>NORMAL</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>invert the peri input</description>
-                  <name>INVERT</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive peri input low</description>
-                  <name>LOW</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive peri input high</description>
-                  <name>HIGH</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>INOVER</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[13:12]</bitRange>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>drive output enable from peripheral signal selected by funcsel</description>
-                  <name>NORMAL</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
-                  <name>INVERT</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>disable output</description>
-                  <name>DISABLE</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>enable output</description>
-                  <name>ENABLE</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>OEOVER</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[9:8]</bitRange>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>drive output from peripheral signal selected by funcsel</description>
-                  <name>NORMAL</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive output from inverse of peripheral signal selected by funcsel</description>
-                  <name>INVERT</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive output low</description>
-                  <name>LOW</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive output high</description>
-                  <name>HIGH</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>OUTOVER</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[4:0]</bitRange>
-              <description>0-31 -&gt; selects pin function according to the gpio table\n
-                31 == NULL</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>spi1_sclk</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>uart1_cts</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>i2c1_sda</name>
-                  <value>3</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>pwm_a_5</name>
-                  <value>4</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>sio_26</name>
-                  <value>5</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>pio0_26</name>
-                  <value>6</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>pio1_26</name>
-                  <value>7</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>usb_muxing_vbus_en</name>
-                  <value>9</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>null</name>
-                  <value>31</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>FUNCSEL</name>
-            </field>
-          </fields>
-          <name>GPIO26_CTRL</name>
-          <resetValue>0x0000001f</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x00d8</addressOffset>
-          <description>GPIO status</description>
-          <fields>
-            <field>
-              <access>read-only</access>
-              <bitRange>[26:26]</bitRange>
-              <description>interrupt to processors, after override is applied</description>
-              <name>IRQTOPROC</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[24:24]</bitRange>
-              <description>interrupt from pad before override is applied</description>
-              <name>IRQFROMPAD</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[19:19]</bitRange>
-              <description>input signal to peripheral, after override is applied</description>
-              <name>INTOPERI</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[17:17]</bitRange>
-              <description>input signal from pad, before override is applied</description>
-              <name>INFROMPAD</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[13:13]</bitRange>
-              <description>output enable to pad after register override is applied</description>
-              <name>OETOPAD</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[12:12]</bitRange>
-              <description>output enable from selected peripheral, before register override is applied</description>
-              <name>OEFROMPERI</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[9:9]</bitRange>
-              <description>output signal to pad after register override is applied</description>
-              <name>OUTTOPAD</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[8:8]</bitRange>
-              <description>output signal from selected peripheral, before register override is applied</description>
-              <name>OUTFROMPERI</name>
-            </field>
-          </fields>
-          <name>GPIO27_STATUS</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x00dc</addressOffset>
-          <description>GPIO control including function select and overrides.</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[29:28]</bitRange>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>don't invert the interrupt</description>
-                  <name>NORMAL</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>invert the interrupt</description>
-                  <name>INVERT</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive interrupt low</description>
-                  <name>LOW</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive interrupt high</description>
-                  <name>HIGH</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>IRQOVER</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[17:16]</bitRange>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>don't invert the peri input</description>
-                  <name>NORMAL</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>invert the peri input</description>
-                  <name>INVERT</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive peri input low</description>
-                  <name>LOW</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive peri input high</description>
-                  <name>HIGH</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>INOVER</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[13:12]</bitRange>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>drive output enable from peripheral signal selected by funcsel</description>
-                  <name>NORMAL</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
-                  <name>INVERT</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>disable output</description>
-                  <name>DISABLE</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>enable output</description>
-                  <name>ENABLE</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>OEOVER</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[9:8]</bitRange>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>drive output from peripheral signal selected by funcsel</description>
-                  <name>NORMAL</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive output from inverse of peripheral signal selected by funcsel</description>
-                  <name>INVERT</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive output low</description>
-                  <name>LOW</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive output high</description>
-                  <name>HIGH</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>OUTOVER</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[4:0]</bitRange>
-              <description>0-31 -&gt; selects pin function according to the gpio table\n
-                31 == NULL</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>spi1_tx</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>uart1_rts</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>i2c1_scl</name>
-                  <value>3</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>pwm_b_5</name>
-                  <value>4</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>sio_27</name>
-                  <value>5</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>pio0_27</name>
-                  <value>6</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>pio1_27</name>
-                  <value>7</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>usb_muxing_overcurr_detect</name>
-                  <value>9</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>null</name>
-                  <value>31</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>FUNCSEL</name>
-            </field>
-          </fields>
-          <name>GPIO27_CTRL</name>
-          <resetValue>0x0000001f</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x00e0</addressOffset>
-          <description>GPIO status</description>
-          <fields>
-            <field>
-              <access>read-only</access>
-              <bitRange>[26:26]</bitRange>
-              <description>interrupt to processors, after override is applied</description>
-              <name>IRQTOPROC</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[24:24]</bitRange>
-              <description>interrupt from pad before override is applied</description>
-              <name>IRQFROMPAD</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[19:19]</bitRange>
-              <description>input signal to peripheral, after override is applied</description>
-              <name>INTOPERI</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[17:17]</bitRange>
-              <description>input signal from pad, before override is applied</description>
-              <name>INFROMPAD</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[13:13]</bitRange>
-              <description>output enable to pad after register override is applied</description>
-              <name>OETOPAD</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[12:12]</bitRange>
-              <description>output enable from selected peripheral, before register override is applied</description>
-              <name>OEFROMPERI</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[9:9]</bitRange>
-              <description>output signal to pad after register override is applied</description>
-              <name>OUTTOPAD</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[8:8]</bitRange>
-              <description>output signal from selected peripheral, before register override is applied</description>
-              <name>OUTFROMPERI</name>
-            </field>
-          </fields>
-          <name>GPIO28_STATUS</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x00e4</addressOffset>
-          <description>GPIO control including function select and overrides.</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[29:28]</bitRange>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>don't invert the interrupt</description>
-                  <name>NORMAL</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>invert the interrupt</description>
-                  <name>INVERT</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive interrupt low</description>
-                  <name>LOW</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive interrupt high</description>
-                  <name>HIGH</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>IRQOVER</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[17:16]</bitRange>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>don't invert the peri input</description>
-                  <name>NORMAL</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>invert the peri input</description>
-                  <name>INVERT</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive peri input low</description>
-                  <name>LOW</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive peri input high</description>
-                  <name>HIGH</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>INOVER</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[13:12]</bitRange>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>drive output enable from peripheral signal selected by funcsel</description>
-                  <name>NORMAL</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
-                  <name>INVERT</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>disable output</description>
-                  <name>DISABLE</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>enable output</description>
-                  <name>ENABLE</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>OEOVER</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[9:8]</bitRange>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>drive output from peripheral signal selected by funcsel</description>
-                  <name>NORMAL</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive output from inverse of peripheral signal selected by funcsel</description>
-                  <name>INVERT</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive output low</description>
-                  <name>LOW</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive output high</description>
-                  <name>HIGH</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>OUTOVER</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[4:0]</bitRange>
-              <description>0-31 -&gt; selects pin function according to the gpio table\n
-                31 == NULL</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>spi1_rx</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>uart0_tx</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>i2c0_sda</name>
-                  <value>3</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>pwm_a_6</name>
-                  <value>4</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>sio_28</name>
-                  <value>5</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>pio0_28</name>
-                  <value>6</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>pio1_28</name>
-                  <value>7</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>usb_muxing_vbus_detect</name>
-                  <value>9</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>null</name>
-                  <value>31</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>FUNCSEL</name>
-            </field>
-          </fields>
-          <name>GPIO28_CTRL</name>
-          <resetValue>0x0000001f</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x00e8</addressOffset>
-          <description>GPIO status</description>
-          <fields>
-            <field>
-              <access>read-only</access>
-              <bitRange>[26:26]</bitRange>
-              <description>interrupt to processors, after override is applied</description>
-              <name>IRQTOPROC</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[24:24]</bitRange>
-              <description>interrupt from pad before override is applied</description>
-              <name>IRQFROMPAD</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[19:19]</bitRange>
-              <description>input signal to peripheral, after override is applied</description>
-              <name>INTOPERI</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[17:17]</bitRange>
-              <description>input signal from pad, before override is applied</description>
-              <name>INFROMPAD</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[13:13]</bitRange>
-              <description>output enable to pad after register override is applied</description>
-              <name>OETOPAD</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[12:12]</bitRange>
-              <description>output enable from selected peripheral, before register override is applied</description>
-              <name>OEFROMPERI</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[9:9]</bitRange>
-              <description>output signal to pad after register override is applied</description>
-              <name>OUTTOPAD</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[8:8]</bitRange>
-              <description>output signal from selected peripheral, before register override is applied</description>
-              <name>OUTFROMPERI</name>
-            </field>
-          </fields>
-          <name>GPIO29_STATUS</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x00ec</addressOffset>
-          <description>GPIO control including function select and overrides.</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[29:28]</bitRange>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>don't invert the interrupt</description>
-                  <name>NORMAL</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>invert the interrupt</description>
-                  <name>INVERT</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive interrupt low</description>
-                  <name>LOW</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive interrupt high</description>
-                  <name>HIGH</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>IRQOVER</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[17:16]</bitRange>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>don't invert the peri input</description>
-                  <name>NORMAL</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>invert the peri input</description>
-                  <name>INVERT</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive peri input low</description>
-                  <name>LOW</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive peri input high</description>
-                  <name>HIGH</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>INOVER</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[13:12]</bitRange>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>drive output enable from peripheral signal selected by funcsel</description>
-                  <name>NORMAL</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
-                  <name>INVERT</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>disable output</description>
-                  <name>DISABLE</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>enable output</description>
-                  <name>ENABLE</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>OEOVER</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[9:8]</bitRange>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>drive output from peripheral signal selected by funcsel</description>
-                  <name>NORMAL</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive output from inverse of peripheral signal selected by funcsel</description>
-                  <name>INVERT</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive output low</description>
-                  <name>LOW</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive output high</description>
-                  <name>HIGH</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>OUTOVER</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[4:0]</bitRange>
-              <description>0-31 -&gt; selects pin function according to the gpio table\n
-                31 == NULL</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>spi1_ss_n</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>uart0_rx</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>i2c0_scl</name>
-                  <value>3</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>pwm_b_6</name>
-                  <value>4</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>sio_29</name>
-                  <value>5</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>pio0_29</name>
-                  <value>6</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>pio1_29</name>
-                  <value>7</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>usb_muxing_vbus_en</name>
-                  <value>9</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>null</name>
-                  <value>31</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>FUNCSEL</name>
-            </field>
-          </fields>
-          <name>GPIO29_CTRL</name>
-          <resetValue>0x0000001f</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x00f0</addressOffset>
-          <description>Raw Interrupts</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[31:31]</bitRange>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>GPIO7_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[30:30]</bitRange>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>GPIO7_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[29:29]</bitRange>
-              <name>GPIO7_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[28:28]</bitRange>
-              <name>GPIO7_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[27:27]</bitRange>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>GPIO6_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[26:26]</bitRange>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>GPIO6_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[25:25]</bitRange>
-              <name>GPIO6_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[24:24]</bitRange>
-              <name>GPIO6_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[23:23]</bitRange>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>GPIO5_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[22:22]</bitRange>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>GPIO5_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[21:21]</bitRange>
-              <name>GPIO5_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[20:20]</bitRange>
-              <name>GPIO5_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[19:19]</bitRange>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>GPIO4_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[18:18]</bitRange>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>GPIO4_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[17:17]</bitRange>
-              <name>GPIO4_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[16:16]</bitRange>
-              <name>GPIO4_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[15:15]</bitRange>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>GPIO3_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[14:14]</bitRange>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>GPIO3_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[13:13]</bitRange>
-              <name>GPIO3_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[12:12]</bitRange>
-              <name>GPIO3_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[11:11]</bitRange>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>GPIO2_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[10:10]</bitRange>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>GPIO2_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[9:9]</bitRange>
-              <name>GPIO2_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[8:8]</bitRange>
-              <name>GPIO2_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[7:7]</bitRange>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>GPIO1_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[6:6]</bitRange>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>GPIO1_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[5:5]</bitRange>
-              <name>GPIO1_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[4:4]</bitRange>
-              <name>GPIO1_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[3:3]</bitRange>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>GPIO0_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[2:2]</bitRange>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>GPIO0_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[1:1]</bitRange>
-              <name>GPIO0_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[0:0]</bitRange>
-              <name>GPIO0_LEVEL_LOW</name>
-            </field>
-          </fields>
-          <name>INTR0</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x00f4</addressOffset>
-          <description>Raw Interrupts</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[31:31]</bitRange>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>GPIO15_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[30:30]</bitRange>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>GPIO15_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[29:29]</bitRange>
-              <name>GPIO15_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[28:28]</bitRange>
-              <name>GPIO15_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[27:27]</bitRange>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>GPIO14_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[26:26]</bitRange>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>GPIO14_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[25:25]</bitRange>
-              <name>GPIO14_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[24:24]</bitRange>
-              <name>GPIO14_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[23:23]</bitRange>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>GPIO13_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[22:22]</bitRange>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>GPIO13_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[21:21]</bitRange>
-              <name>GPIO13_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[20:20]</bitRange>
-              <name>GPIO13_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[19:19]</bitRange>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>GPIO12_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[18:18]</bitRange>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>GPIO12_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[17:17]</bitRange>
-              <name>GPIO12_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[16:16]</bitRange>
-              <name>GPIO12_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[15:15]</bitRange>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>GPIO11_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[14:14]</bitRange>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>GPIO11_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[13:13]</bitRange>
-              <name>GPIO11_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[12:12]</bitRange>
-              <name>GPIO11_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[11:11]</bitRange>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>GPIO10_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[10:10]</bitRange>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>GPIO10_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[9:9]</bitRange>
-              <name>GPIO10_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[8:8]</bitRange>
-              <name>GPIO10_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[7:7]</bitRange>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>GPIO9_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[6:6]</bitRange>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>GPIO9_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[5:5]</bitRange>
-              <name>GPIO9_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[4:4]</bitRange>
-              <name>GPIO9_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[3:3]</bitRange>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>GPIO8_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[2:2]</bitRange>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>GPIO8_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[1:1]</bitRange>
-              <name>GPIO8_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[0:0]</bitRange>
-              <name>GPIO8_LEVEL_LOW</name>
-            </field>
-          </fields>
-          <name>INTR1</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x00f8</addressOffset>
-          <description>Raw Interrupts</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[31:31]</bitRange>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>GPIO23_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[30:30]</bitRange>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>GPIO23_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[29:29]</bitRange>
-              <name>GPIO23_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[28:28]</bitRange>
-              <name>GPIO23_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[27:27]</bitRange>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>GPIO22_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[26:26]</bitRange>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>GPIO22_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[25:25]</bitRange>
-              <name>GPIO22_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[24:24]</bitRange>
-              <name>GPIO22_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[23:23]</bitRange>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>GPIO21_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[22:22]</bitRange>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>GPIO21_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[21:21]</bitRange>
-              <name>GPIO21_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[20:20]</bitRange>
-              <name>GPIO21_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[19:19]</bitRange>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>GPIO20_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[18:18]</bitRange>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>GPIO20_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[17:17]</bitRange>
-              <name>GPIO20_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[16:16]</bitRange>
-              <name>GPIO20_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[15:15]</bitRange>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>GPIO19_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[14:14]</bitRange>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>GPIO19_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[13:13]</bitRange>
-              <name>GPIO19_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[12:12]</bitRange>
-              <name>GPIO19_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[11:11]</bitRange>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>GPIO18_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[10:10]</bitRange>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>GPIO18_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[9:9]</bitRange>
-              <name>GPIO18_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[8:8]</bitRange>
-              <name>GPIO18_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[7:7]</bitRange>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>GPIO17_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[6:6]</bitRange>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>GPIO17_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[5:5]</bitRange>
-              <name>GPIO17_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[4:4]</bitRange>
-              <name>GPIO17_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[3:3]</bitRange>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>GPIO16_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[2:2]</bitRange>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>GPIO16_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[1:1]</bitRange>
-              <name>GPIO16_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[0:0]</bitRange>
-              <name>GPIO16_LEVEL_LOW</name>
-            </field>
-          </fields>
-          <name>INTR2</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x00fc</addressOffset>
-          <description>Raw Interrupts</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[23:23]</bitRange>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>GPIO29_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[22:22]</bitRange>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>GPIO29_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[21:21]</bitRange>
-              <name>GPIO29_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[20:20]</bitRange>
-              <name>GPIO29_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[19:19]</bitRange>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>GPIO28_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[18:18]</bitRange>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>GPIO28_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[17:17]</bitRange>
-              <name>GPIO28_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[16:16]</bitRange>
-              <name>GPIO28_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[15:15]</bitRange>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>GPIO27_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[14:14]</bitRange>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>GPIO27_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[13:13]</bitRange>
-              <name>GPIO27_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[12:12]</bitRange>
-              <name>GPIO27_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[11:11]</bitRange>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>GPIO26_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[10:10]</bitRange>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>GPIO26_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[9:9]</bitRange>
-              <name>GPIO26_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[8:8]</bitRange>
-              <name>GPIO26_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[7:7]</bitRange>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>GPIO25_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[6:6]</bitRange>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>GPIO25_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[5:5]</bitRange>
-              <name>GPIO25_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[4:4]</bitRange>
-              <name>GPIO25_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[3:3]</bitRange>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>GPIO24_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[2:2]</bitRange>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>GPIO24_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[1:1]</bitRange>
-              <name>GPIO24_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[0:0]</bitRange>
-              <name>GPIO24_LEVEL_LOW</name>
-            </field>
-          </fields>
-          <name>INTR3</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0100</addressOffset>
-          <description>Interrupt Enable for proc0</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[31:31]</bitRange>
-              <name>GPIO7_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[30:30]</bitRange>
-              <name>GPIO7_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[29:29]</bitRange>
-              <name>GPIO7_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[28:28]</bitRange>
-              <name>GPIO7_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[27:27]</bitRange>
-              <name>GPIO6_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[26:26]</bitRange>
-              <name>GPIO6_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[25:25]</bitRange>
-              <name>GPIO6_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[24:24]</bitRange>
-              <name>GPIO6_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[23:23]</bitRange>
-              <name>GPIO5_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[22:22]</bitRange>
-              <name>GPIO5_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[21:21]</bitRange>
-              <name>GPIO5_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[20:20]</bitRange>
-              <name>GPIO5_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[19:19]</bitRange>
-              <name>GPIO4_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[18:18]</bitRange>
-              <name>GPIO4_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[17:17]</bitRange>
-              <name>GPIO4_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[16:16]</bitRange>
-              <name>GPIO4_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[15:15]</bitRange>
-              <name>GPIO3_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[14:14]</bitRange>
-              <name>GPIO3_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[13:13]</bitRange>
-              <name>GPIO3_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[12:12]</bitRange>
-              <name>GPIO3_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[11:11]</bitRange>
-              <name>GPIO2_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[10:10]</bitRange>
-              <name>GPIO2_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[9:9]</bitRange>
-              <name>GPIO2_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[8:8]</bitRange>
-              <name>GPIO2_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[7:7]</bitRange>
-              <name>GPIO1_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[6:6]</bitRange>
-              <name>GPIO1_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[5:5]</bitRange>
-              <name>GPIO1_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[4:4]</bitRange>
-              <name>GPIO1_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[3:3]</bitRange>
-              <name>GPIO0_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[2:2]</bitRange>
-              <name>GPIO0_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[1:1]</bitRange>
-              <name>GPIO0_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[0:0]</bitRange>
-              <name>GPIO0_LEVEL_LOW</name>
-            </field>
-          </fields>
-          <name>PROC0_INTE0</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0104</addressOffset>
-          <description>Interrupt Enable for proc0</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[31:31]</bitRange>
-              <name>GPIO15_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[30:30]</bitRange>
-              <name>GPIO15_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[29:29]</bitRange>
-              <name>GPIO15_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[28:28]</bitRange>
-              <name>GPIO15_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[27:27]</bitRange>
-              <name>GPIO14_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[26:26]</bitRange>
-              <name>GPIO14_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[25:25]</bitRange>
-              <name>GPIO14_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[24:24]</bitRange>
-              <name>GPIO14_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[23:23]</bitRange>
-              <name>GPIO13_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[22:22]</bitRange>
-              <name>GPIO13_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[21:21]</bitRange>
-              <name>GPIO13_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[20:20]</bitRange>
-              <name>GPIO13_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[19:19]</bitRange>
-              <name>GPIO12_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[18:18]</bitRange>
-              <name>GPIO12_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[17:17]</bitRange>
-              <name>GPIO12_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[16:16]</bitRange>
-              <name>GPIO12_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[15:15]</bitRange>
-              <name>GPIO11_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[14:14]</bitRange>
-              <name>GPIO11_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[13:13]</bitRange>
-              <name>GPIO11_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[12:12]</bitRange>
-              <name>GPIO11_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[11:11]</bitRange>
-              <name>GPIO10_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[10:10]</bitRange>
-              <name>GPIO10_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[9:9]</bitRange>
-              <name>GPIO10_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[8:8]</bitRange>
-              <name>GPIO10_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[7:7]</bitRange>
-              <name>GPIO9_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[6:6]</bitRange>
-              <name>GPIO9_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[5:5]</bitRange>
-              <name>GPIO9_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[4:4]</bitRange>
-              <name>GPIO9_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[3:3]</bitRange>
-              <name>GPIO8_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[2:2]</bitRange>
-              <name>GPIO8_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[1:1]</bitRange>
-              <name>GPIO8_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[0:0]</bitRange>
-              <name>GPIO8_LEVEL_LOW</name>
-            </field>
-          </fields>
-          <name>PROC0_INTE1</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0108</addressOffset>
-          <description>Interrupt Enable for proc0</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[31:31]</bitRange>
-              <name>GPIO23_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[30:30]</bitRange>
-              <name>GPIO23_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[29:29]</bitRange>
-              <name>GPIO23_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[28:28]</bitRange>
-              <name>GPIO23_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[27:27]</bitRange>
-              <name>GPIO22_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[26:26]</bitRange>
-              <name>GPIO22_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[25:25]</bitRange>
-              <name>GPIO22_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[24:24]</bitRange>
-              <name>GPIO22_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[23:23]</bitRange>
-              <name>GPIO21_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[22:22]</bitRange>
-              <name>GPIO21_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[21:21]</bitRange>
-              <name>GPIO21_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[20:20]</bitRange>
-              <name>GPIO21_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[19:19]</bitRange>
-              <name>GPIO20_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[18:18]</bitRange>
-              <name>GPIO20_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[17:17]</bitRange>
-              <name>GPIO20_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[16:16]</bitRange>
-              <name>GPIO20_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[15:15]</bitRange>
-              <name>GPIO19_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[14:14]</bitRange>
-              <name>GPIO19_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[13:13]</bitRange>
-              <name>GPIO19_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[12:12]</bitRange>
-              <name>GPIO19_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[11:11]</bitRange>
-              <name>GPIO18_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[10:10]</bitRange>
-              <name>GPIO18_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[9:9]</bitRange>
-              <name>GPIO18_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[8:8]</bitRange>
-              <name>GPIO18_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[7:7]</bitRange>
-              <name>GPIO17_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[6:6]</bitRange>
-              <name>GPIO17_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[5:5]</bitRange>
-              <name>GPIO17_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[4:4]</bitRange>
-              <name>GPIO17_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[3:3]</bitRange>
-              <name>GPIO16_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[2:2]</bitRange>
-              <name>GPIO16_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[1:1]</bitRange>
-              <name>GPIO16_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[0:0]</bitRange>
-              <name>GPIO16_LEVEL_LOW</name>
-            </field>
-          </fields>
-          <name>PROC0_INTE2</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x010c</addressOffset>
-          <description>Interrupt Enable for proc0</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[23:23]</bitRange>
-              <name>GPIO29_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[22:22]</bitRange>
-              <name>GPIO29_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[21:21]</bitRange>
-              <name>GPIO29_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[20:20]</bitRange>
-              <name>GPIO29_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[19:19]</bitRange>
-              <name>GPIO28_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[18:18]</bitRange>
-              <name>GPIO28_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[17:17]</bitRange>
-              <name>GPIO28_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[16:16]</bitRange>
-              <name>GPIO28_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[15:15]</bitRange>
-              <name>GPIO27_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[14:14]</bitRange>
-              <name>GPIO27_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[13:13]</bitRange>
-              <name>GPIO27_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[12:12]</bitRange>
-              <name>GPIO27_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[11:11]</bitRange>
-              <name>GPIO26_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[10:10]</bitRange>
-              <name>GPIO26_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[9:9]</bitRange>
-              <name>GPIO26_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[8:8]</bitRange>
-              <name>GPIO26_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[7:7]</bitRange>
-              <name>GPIO25_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[6:6]</bitRange>
-              <name>GPIO25_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[5:5]</bitRange>
-              <name>GPIO25_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[4:4]</bitRange>
-              <name>GPIO25_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[3:3]</bitRange>
-              <name>GPIO24_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[2:2]</bitRange>
-              <name>GPIO24_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[1:1]</bitRange>
-              <name>GPIO24_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[0:0]</bitRange>
-              <name>GPIO24_LEVEL_LOW</name>
-            </field>
-          </fields>
-          <name>PROC0_INTE3</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0110</addressOffset>
-          <description>Interrupt Force for proc0</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[31:31]</bitRange>
-              <name>GPIO7_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[30:30]</bitRange>
-              <name>GPIO7_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[29:29]</bitRange>
-              <name>GPIO7_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[28:28]</bitRange>
-              <name>GPIO7_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[27:27]</bitRange>
-              <name>GPIO6_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[26:26]</bitRange>
-              <name>GPIO6_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[25:25]</bitRange>
-              <name>GPIO6_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[24:24]</bitRange>
-              <name>GPIO6_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[23:23]</bitRange>
-              <name>GPIO5_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[22:22]</bitRange>
-              <name>GPIO5_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[21:21]</bitRange>
-              <name>GPIO5_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[20:20]</bitRange>
-              <name>GPIO5_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[19:19]</bitRange>
-              <name>GPIO4_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[18:18]</bitRange>
-              <name>GPIO4_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[17:17]</bitRange>
-              <name>GPIO4_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[16:16]</bitRange>
-              <name>GPIO4_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[15:15]</bitRange>
-              <name>GPIO3_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[14:14]</bitRange>
-              <name>GPIO3_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[13:13]</bitRange>
-              <name>GPIO3_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[12:12]</bitRange>
-              <name>GPIO3_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[11:11]</bitRange>
-              <name>GPIO2_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[10:10]</bitRange>
-              <name>GPIO2_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[9:9]</bitRange>
-              <name>GPIO2_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[8:8]</bitRange>
-              <name>GPIO2_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[7:7]</bitRange>
-              <name>GPIO1_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[6:6]</bitRange>
-              <name>GPIO1_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[5:5]</bitRange>
-              <name>GPIO1_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[4:4]</bitRange>
-              <name>GPIO1_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[3:3]</bitRange>
-              <name>GPIO0_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[2:2]</bitRange>
-              <name>GPIO0_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[1:1]</bitRange>
-              <name>GPIO0_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[0:0]</bitRange>
-              <name>GPIO0_LEVEL_LOW</name>
-            </field>
-          </fields>
-          <name>PROC0_INTF0</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0114</addressOffset>
-          <description>Interrupt Force for proc0</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[31:31]</bitRange>
-              <name>GPIO15_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[30:30]</bitRange>
-              <name>GPIO15_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[29:29]</bitRange>
-              <name>GPIO15_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[28:28]</bitRange>
-              <name>GPIO15_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[27:27]</bitRange>
-              <name>GPIO14_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[26:26]</bitRange>
-              <name>GPIO14_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[25:25]</bitRange>
-              <name>GPIO14_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[24:24]</bitRange>
-              <name>GPIO14_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[23:23]</bitRange>
-              <name>GPIO13_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[22:22]</bitRange>
-              <name>GPIO13_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[21:21]</bitRange>
-              <name>GPIO13_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[20:20]</bitRange>
-              <name>GPIO13_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[19:19]</bitRange>
-              <name>GPIO12_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[18:18]</bitRange>
-              <name>GPIO12_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[17:17]</bitRange>
-              <name>GPIO12_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[16:16]</bitRange>
-              <name>GPIO12_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[15:15]</bitRange>
-              <name>GPIO11_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[14:14]</bitRange>
-              <name>GPIO11_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[13:13]</bitRange>
-              <name>GPIO11_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[12:12]</bitRange>
-              <name>GPIO11_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[11:11]</bitRange>
-              <name>GPIO10_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[10:10]</bitRange>
-              <name>GPIO10_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[9:9]</bitRange>
-              <name>GPIO10_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[8:8]</bitRange>
-              <name>GPIO10_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[7:7]</bitRange>
-              <name>GPIO9_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[6:6]</bitRange>
-              <name>GPIO9_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[5:5]</bitRange>
-              <name>GPIO9_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[4:4]</bitRange>
-              <name>GPIO9_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[3:3]</bitRange>
-              <name>GPIO8_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[2:2]</bitRange>
-              <name>GPIO8_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[1:1]</bitRange>
-              <name>GPIO8_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[0:0]</bitRange>
-              <name>GPIO8_LEVEL_LOW</name>
-            </field>
-          </fields>
-          <name>PROC0_INTF1</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0118</addressOffset>
-          <description>Interrupt Force for proc0</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[31:31]</bitRange>
-              <name>GPIO23_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[30:30]</bitRange>
-              <name>GPIO23_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[29:29]</bitRange>
-              <name>GPIO23_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[28:28]</bitRange>
-              <name>GPIO23_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[27:27]</bitRange>
-              <name>GPIO22_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[26:26]</bitRange>
-              <name>GPIO22_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[25:25]</bitRange>
-              <name>GPIO22_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[24:24]</bitRange>
-              <name>GPIO22_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[23:23]</bitRange>
-              <name>GPIO21_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[22:22]</bitRange>
-              <name>GPIO21_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[21:21]</bitRange>
-              <name>GPIO21_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[20:20]</bitRange>
-              <name>GPIO21_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[19:19]</bitRange>
-              <name>GPIO20_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[18:18]</bitRange>
-              <name>GPIO20_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[17:17]</bitRange>
-              <name>GPIO20_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[16:16]</bitRange>
-              <name>GPIO20_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[15:15]</bitRange>
-              <name>GPIO19_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[14:14]</bitRange>
-              <name>GPIO19_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[13:13]</bitRange>
-              <name>GPIO19_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[12:12]</bitRange>
-              <name>GPIO19_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[11:11]</bitRange>
-              <name>GPIO18_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[10:10]</bitRange>
-              <name>GPIO18_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[9:9]</bitRange>
-              <name>GPIO18_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[8:8]</bitRange>
-              <name>GPIO18_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[7:7]</bitRange>
-              <name>GPIO17_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[6:6]</bitRange>
-              <name>GPIO17_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[5:5]</bitRange>
-              <name>GPIO17_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[4:4]</bitRange>
-              <name>GPIO17_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[3:3]</bitRange>
-              <name>GPIO16_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[2:2]</bitRange>
-              <name>GPIO16_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[1:1]</bitRange>
-              <name>GPIO16_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[0:0]</bitRange>
-              <name>GPIO16_LEVEL_LOW</name>
-            </field>
-          </fields>
-          <name>PROC0_INTF2</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x011c</addressOffset>
-          <description>Interrupt Force for proc0</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[23:23]</bitRange>
-              <name>GPIO29_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[22:22]</bitRange>
-              <name>GPIO29_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[21:21]</bitRange>
-              <name>GPIO29_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[20:20]</bitRange>
-              <name>GPIO29_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[19:19]</bitRange>
-              <name>GPIO28_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[18:18]</bitRange>
-              <name>GPIO28_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[17:17]</bitRange>
-              <name>GPIO28_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[16:16]</bitRange>
-              <name>GPIO28_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[15:15]</bitRange>
-              <name>GPIO27_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[14:14]</bitRange>
-              <name>GPIO27_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[13:13]</bitRange>
-              <name>GPIO27_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[12:12]</bitRange>
-              <name>GPIO27_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[11:11]</bitRange>
-              <name>GPIO26_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[10:10]</bitRange>
-              <name>GPIO26_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[9:9]</bitRange>
-              <name>GPIO26_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[8:8]</bitRange>
-              <name>GPIO26_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[7:7]</bitRange>
-              <name>GPIO25_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[6:6]</bitRange>
-              <name>GPIO25_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[5:5]</bitRange>
-              <name>GPIO25_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[4:4]</bitRange>
-              <name>GPIO25_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[3:3]</bitRange>
-              <name>GPIO24_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[2:2]</bitRange>
-              <name>GPIO24_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[1:1]</bitRange>
-              <name>GPIO24_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[0:0]</bitRange>
-              <name>GPIO24_LEVEL_LOW</name>
-            </field>
-          </fields>
-          <name>PROC0_INTF3</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0120</addressOffset>
-          <description>Interrupt status after masking &amp; forcing for proc0</description>
-          <fields>
-            <field>
-              <access>read-only</access>
-              <bitRange>[31:31]</bitRange>
-              <name>GPIO7_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[30:30]</bitRange>
-              <name>GPIO7_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[29:29]</bitRange>
-              <name>GPIO7_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[28:28]</bitRange>
-              <name>GPIO7_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[27:27]</bitRange>
-              <name>GPIO6_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[26:26]</bitRange>
-              <name>GPIO6_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[25:25]</bitRange>
-              <name>GPIO6_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[24:24]</bitRange>
-              <name>GPIO6_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[23:23]</bitRange>
-              <name>GPIO5_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[22:22]</bitRange>
-              <name>GPIO5_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[21:21]</bitRange>
-              <name>GPIO5_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[20:20]</bitRange>
-              <name>GPIO5_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[19:19]</bitRange>
-              <name>GPIO4_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[18:18]</bitRange>
-              <name>GPIO4_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[17:17]</bitRange>
-              <name>GPIO4_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[16:16]</bitRange>
-              <name>GPIO4_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[15:15]</bitRange>
-              <name>GPIO3_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[14:14]</bitRange>
-              <name>GPIO3_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[13:13]</bitRange>
-              <name>GPIO3_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[12:12]</bitRange>
-              <name>GPIO3_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[11:11]</bitRange>
-              <name>GPIO2_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[10:10]</bitRange>
-              <name>GPIO2_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[9:9]</bitRange>
-              <name>GPIO2_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[8:8]</bitRange>
-              <name>GPIO2_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[7:7]</bitRange>
-              <name>GPIO1_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[6:6]</bitRange>
-              <name>GPIO1_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[5:5]</bitRange>
-              <name>GPIO1_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[4:4]</bitRange>
-              <name>GPIO1_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[3:3]</bitRange>
-              <name>GPIO0_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[2:2]</bitRange>
-              <name>GPIO0_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[1:1]</bitRange>
-              <name>GPIO0_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[0:0]</bitRange>
-              <name>GPIO0_LEVEL_LOW</name>
-            </field>
-          </fields>
-          <name>PROC0_INTS0</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0124</addressOffset>
-          <description>Interrupt status after masking &amp; forcing for proc0</description>
-          <fields>
-            <field>
-              <access>read-only</access>
-              <bitRange>[31:31]</bitRange>
-              <name>GPIO15_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[30:30]</bitRange>
-              <name>GPIO15_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[29:29]</bitRange>
-              <name>GPIO15_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[28:28]</bitRange>
-              <name>GPIO15_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[27:27]</bitRange>
-              <name>GPIO14_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[26:26]</bitRange>
-              <name>GPIO14_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[25:25]</bitRange>
-              <name>GPIO14_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[24:24]</bitRange>
-              <name>GPIO14_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[23:23]</bitRange>
-              <name>GPIO13_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[22:22]</bitRange>
-              <name>GPIO13_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[21:21]</bitRange>
-              <name>GPIO13_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[20:20]</bitRange>
-              <name>GPIO13_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[19:19]</bitRange>
-              <name>GPIO12_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[18:18]</bitRange>
-              <name>GPIO12_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[17:17]</bitRange>
-              <name>GPIO12_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[16:16]</bitRange>
-              <name>GPIO12_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[15:15]</bitRange>
-              <name>GPIO11_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[14:14]</bitRange>
-              <name>GPIO11_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[13:13]</bitRange>
-              <name>GPIO11_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[12:12]</bitRange>
-              <name>GPIO11_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[11:11]</bitRange>
-              <name>GPIO10_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[10:10]</bitRange>
-              <name>GPIO10_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[9:9]</bitRange>
-              <name>GPIO10_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[8:8]</bitRange>
-              <name>GPIO10_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[7:7]</bitRange>
-              <name>GPIO9_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[6:6]</bitRange>
-              <name>GPIO9_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[5:5]</bitRange>
-              <name>GPIO9_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[4:4]</bitRange>
-              <name>GPIO9_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[3:3]</bitRange>
-              <name>GPIO8_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[2:2]</bitRange>
-              <name>GPIO8_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[1:1]</bitRange>
-              <name>GPIO8_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[0:0]</bitRange>
-              <name>GPIO8_LEVEL_LOW</name>
-            </field>
-          </fields>
-          <name>PROC0_INTS1</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0128</addressOffset>
-          <description>Interrupt status after masking &amp; forcing for proc0</description>
-          <fields>
-            <field>
-              <access>read-only</access>
-              <bitRange>[31:31]</bitRange>
-              <name>GPIO23_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[30:30]</bitRange>
-              <name>GPIO23_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[29:29]</bitRange>
-              <name>GPIO23_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[28:28]</bitRange>
-              <name>GPIO23_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[27:27]</bitRange>
-              <name>GPIO22_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[26:26]</bitRange>
-              <name>GPIO22_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[25:25]</bitRange>
-              <name>GPIO22_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[24:24]</bitRange>
-              <name>GPIO22_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[23:23]</bitRange>
-              <name>GPIO21_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[22:22]</bitRange>
-              <name>GPIO21_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[21:21]</bitRange>
-              <name>GPIO21_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[20:20]</bitRange>
-              <name>GPIO21_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[19:19]</bitRange>
-              <name>GPIO20_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[18:18]</bitRange>
-              <name>GPIO20_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[17:17]</bitRange>
-              <name>GPIO20_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[16:16]</bitRange>
-              <name>GPIO20_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[15:15]</bitRange>
-              <name>GPIO19_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[14:14]</bitRange>
-              <name>GPIO19_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[13:13]</bitRange>
-              <name>GPIO19_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[12:12]</bitRange>
-              <name>GPIO19_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[11:11]</bitRange>
-              <name>GPIO18_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[10:10]</bitRange>
-              <name>GPIO18_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[9:9]</bitRange>
-              <name>GPIO18_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[8:8]</bitRange>
-              <name>GPIO18_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[7:7]</bitRange>
-              <name>GPIO17_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[6:6]</bitRange>
-              <name>GPIO17_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[5:5]</bitRange>
-              <name>GPIO17_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[4:4]</bitRange>
-              <name>GPIO17_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[3:3]</bitRange>
-              <name>GPIO16_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[2:2]</bitRange>
-              <name>GPIO16_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[1:1]</bitRange>
-              <name>GPIO16_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[0:0]</bitRange>
-              <name>GPIO16_LEVEL_LOW</name>
-            </field>
-          </fields>
-          <name>PROC0_INTS2</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x012c</addressOffset>
-          <description>Interrupt status after masking &amp; forcing for proc0</description>
-          <fields>
-            <field>
-              <access>read-only</access>
-              <bitRange>[23:23]</bitRange>
-              <name>GPIO29_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[22:22]</bitRange>
-              <name>GPIO29_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[21:21]</bitRange>
-              <name>GPIO29_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[20:20]</bitRange>
-              <name>GPIO29_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[19:19]</bitRange>
-              <name>GPIO28_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[18:18]</bitRange>
-              <name>GPIO28_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[17:17]</bitRange>
-              <name>GPIO28_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[16:16]</bitRange>
-              <name>GPIO28_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[15:15]</bitRange>
-              <name>GPIO27_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[14:14]</bitRange>
-              <name>GPIO27_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[13:13]</bitRange>
-              <name>GPIO27_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[12:12]</bitRange>
-              <name>GPIO27_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[11:11]</bitRange>
-              <name>GPIO26_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[10:10]</bitRange>
-              <name>GPIO26_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[9:9]</bitRange>
-              <name>GPIO26_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[8:8]</bitRange>
-              <name>GPIO26_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[7:7]</bitRange>
-              <name>GPIO25_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[6:6]</bitRange>
-              <name>GPIO25_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[5:5]</bitRange>
-              <name>GPIO25_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[4:4]</bitRange>
-              <name>GPIO25_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[3:3]</bitRange>
-              <name>GPIO24_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[2:2]</bitRange>
-              <name>GPIO24_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[1:1]</bitRange>
-              <name>GPIO24_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[0:0]</bitRange>
-              <name>GPIO24_LEVEL_LOW</name>
-            </field>
-          </fields>
-          <name>PROC0_INTS3</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0130</addressOffset>
-          <description>Interrupt Enable for proc1</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[31:31]</bitRange>
-              <name>GPIO7_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[30:30]</bitRange>
-              <name>GPIO7_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[29:29]</bitRange>
-              <name>GPIO7_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[28:28]</bitRange>
-              <name>GPIO7_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[27:27]</bitRange>
-              <name>GPIO6_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[26:26]</bitRange>
-              <name>GPIO6_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[25:25]</bitRange>
-              <name>GPIO6_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[24:24]</bitRange>
-              <name>GPIO6_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[23:23]</bitRange>
-              <name>GPIO5_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[22:22]</bitRange>
-              <name>GPIO5_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[21:21]</bitRange>
-              <name>GPIO5_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[20:20]</bitRange>
-              <name>GPIO5_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[19:19]</bitRange>
-              <name>GPIO4_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[18:18]</bitRange>
-              <name>GPIO4_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[17:17]</bitRange>
-              <name>GPIO4_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[16:16]</bitRange>
-              <name>GPIO4_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[15:15]</bitRange>
-              <name>GPIO3_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[14:14]</bitRange>
-              <name>GPIO3_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[13:13]</bitRange>
-              <name>GPIO3_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[12:12]</bitRange>
-              <name>GPIO3_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[11:11]</bitRange>
-              <name>GPIO2_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[10:10]</bitRange>
-              <name>GPIO2_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[9:9]</bitRange>
-              <name>GPIO2_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[8:8]</bitRange>
-              <name>GPIO2_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[7:7]</bitRange>
-              <name>GPIO1_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[6:6]</bitRange>
-              <name>GPIO1_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[5:5]</bitRange>
-              <name>GPIO1_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[4:4]</bitRange>
-              <name>GPIO1_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[3:3]</bitRange>
-              <name>GPIO0_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[2:2]</bitRange>
-              <name>GPIO0_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[1:1]</bitRange>
-              <name>GPIO0_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[0:0]</bitRange>
-              <name>GPIO0_LEVEL_LOW</name>
-            </field>
-          </fields>
-          <name>PROC1_INTE0</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0134</addressOffset>
-          <description>Interrupt Enable for proc1</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[31:31]</bitRange>
-              <name>GPIO15_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[30:30]</bitRange>
-              <name>GPIO15_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[29:29]</bitRange>
-              <name>GPIO15_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[28:28]</bitRange>
-              <name>GPIO15_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[27:27]</bitRange>
-              <name>GPIO14_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[26:26]</bitRange>
-              <name>GPIO14_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[25:25]</bitRange>
-              <name>GPIO14_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[24:24]</bitRange>
-              <name>GPIO14_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[23:23]</bitRange>
-              <name>GPIO13_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[22:22]</bitRange>
-              <name>GPIO13_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[21:21]</bitRange>
-              <name>GPIO13_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[20:20]</bitRange>
-              <name>GPIO13_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[19:19]</bitRange>
-              <name>GPIO12_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[18:18]</bitRange>
-              <name>GPIO12_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[17:17]</bitRange>
-              <name>GPIO12_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[16:16]</bitRange>
-              <name>GPIO12_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[15:15]</bitRange>
-              <name>GPIO11_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[14:14]</bitRange>
-              <name>GPIO11_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[13:13]</bitRange>
-              <name>GPIO11_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[12:12]</bitRange>
-              <name>GPIO11_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[11:11]</bitRange>
-              <name>GPIO10_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[10:10]</bitRange>
-              <name>GPIO10_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[9:9]</bitRange>
-              <name>GPIO10_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[8:8]</bitRange>
-              <name>GPIO10_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[7:7]</bitRange>
-              <name>GPIO9_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[6:6]</bitRange>
-              <name>GPIO9_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[5:5]</bitRange>
-              <name>GPIO9_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[4:4]</bitRange>
-              <name>GPIO9_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[3:3]</bitRange>
-              <name>GPIO8_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[2:2]</bitRange>
-              <name>GPIO8_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[1:1]</bitRange>
-              <name>GPIO8_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[0:0]</bitRange>
-              <name>GPIO8_LEVEL_LOW</name>
-            </field>
-          </fields>
-          <name>PROC1_INTE1</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0138</addressOffset>
-          <description>Interrupt Enable for proc1</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[31:31]</bitRange>
-              <name>GPIO23_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[30:30]</bitRange>
-              <name>GPIO23_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[29:29]</bitRange>
-              <name>GPIO23_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[28:28]</bitRange>
-              <name>GPIO23_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[27:27]</bitRange>
-              <name>GPIO22_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[26:26]</bitRange>
-              <name>GPIO22_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[25:25]</bitRange>
-              <name>GPIO22_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[24:24]</bitRange>
-              <name>GPIO22_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[23:23]</bitRange>
-              <name>GPIO21_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[22:22]</bitRange>
-              <name>GPIO21_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[21:21]</bitRange>
-              <name>GPIO21_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[20:20]</bitRange>
-              <name>GPIO21_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[19:19]</bitRange>
-              <name>GPIO20_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[18:18]</bitRange>
-              <name>GPIO20_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[17:17]</bitRange>
-              <name>GPIO20_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[16:16]</bitRange>
-              <name>GPIO20_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[15:15]</bitRange>
-              <name>GPIO19_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[14:14]</bitRange>
-              <name>GPIO19_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[13:13]</bitRange>
-              <name>GPIO19_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[12:12]</bitRange>
-              <name>GPIO19_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[11:11]</bitRange>
-              <name>GPIO18_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[10:10]</bitRange>
-              <name>GPIO18_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[9:9]</bitRange>
-              <name>GPIO18_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[8:8]</bitRange>
-              <name>GPIO18_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[7:7]</bitRange>
-              <name>GPIO17_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[6:6]</bitRange>
-              <name>GPIO17_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[5:5]</bitRange>
-              <name>GPIO17_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[4:4]</bitRange>
-              <name>GPIO17_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[3:3]</bitRange>
-              <name>GPIO16_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[2:2]</bitRange>
-              <name>GPIO16_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[1:1]</bitRange>
-              <name>GPIO16_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[0:0]</bitRange>
-              <name>GPIO16_LEVEL_LOW</name>
-            </field>
-          </fields>
-          <name>PROC1_INTE2</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x013c</addressOffset>
-          <description>Interrupt Enable for proc1</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[23:23]</bitRange>
-              <name>GPIO29_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[22:22]</bitRange>
-              <name>GPIO29_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[21:21]</bitRange>
-              <name>GPIO29_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[20:20]</bitRange>
-              <name>GPIO29_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[19:19]</bitRange>
-              <name>GPIO28_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[18:18]</bitRange>
-              <name>GPIO28_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[17:17]</bitRange>
-              <name>GPIO28_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[16:16]</bitRange>
-              <name>GPIO28_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[15:15]</bitRange>
-              <name>GPIO27_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[14:14]</bitRange>
-              <name>GPIO27_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[13:13]</bitRange>
-              <name>GPIO27_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[12:12]</bitRange>
-              <name>GPIO27_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[11:11]</bitRange>
-              <name>GPIO26_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[10:10]</bitRange>
-              <name>GPIO26_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[9:9]</bitRange>
-              <name>GPIO26_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[8:8]</bitRange>
-              <name>GPIO26_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[7:7]</bitRange>
-              <name>GPIO25_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[6:6]</bitRange>
-              <name>GPIO25_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[5:5]</bitRange>
-              <name>GPIO25_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[4:4]</bitRange>
-              <name>GPIO25_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[3:3]</bitRange>
-              <name>GPIO24_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[2:2]</bitRange>
-              <name>GPIO24_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[1:1]</bitRange>
-              <name>GPIO24_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[0:0]</bitRange>
-              <name>GPIO24_LEVEL_LOW</name>
-            </field>
-          </fields>
-          <name>PROC1_INTE3</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0140</addressOffset>
-          <description>Interrupt Force for proc1</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[31:31]</bitRange>
-              <name>GPIO7_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[30:30]</bitRange>
-              <name>GPIO7_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[29:29]</bitRange>
-              <name>GPIO7_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[28:28]</bitRange>
-              <name>GPIO7_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[27:27]</bitRange>
-              <name>GPIO6_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[26:26]</bitRange>
-              <name>GPIO6_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[25:25]</bitRange>
-              <name>GPIO6_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[24:24]</bitRange>
-              <name>GPIO6_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[23:23]</bitRange>
-              <name>GPIO5_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[22:22]</bitRange>
-              <name>GPIO5_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[21:21]</bitRange>
-              <name>GPIO5_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[20:20]</bitRange>
-              <name>GPIO5_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[19:19]</bitRange>
-              <name>GPIO4_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[18:18]</bitRange>
-              <name>GPIO4_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[17:17]</bitRange>
-              <name>GPIO4_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[16:16]</bitRange>
-              <name>GPIO4_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[15:15]</bitRange>
-              <name>GPIO3_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[14:14]</bitRange>
-              <name>GPIO3_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[13:13]</bitRange>
-              <name>GPIO3_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[12:12]</bitRange>
-              <name>GPIO3_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[11:11]</bitRange>
-              <name>GPIO2_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[10:10]</bitRange>
-              <name>GPIO2_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[9:9]</bitRange>
-              <name>GPIO2_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[8:8]</bitRange>
-              <name>GPIO2_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[7:7]</bitRange>
-              <name>GPIO1_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[6:6]</bitRange>
-              <name>GPIO1_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[5:5]</bitRange>
-              <name>GPIO1_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[4:4]</bitRange>
-              <name>GPIO1_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[3:3]</bitRange>
-              <name>GPIO0_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[2:2]</bitRange>
-              <name>GPIO0_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[1:1]</bitRange>
-              <name>GPIO0_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[0:0]</bitRange>
-              <name>GPIO0_LEVEL_LOW</name>
-            </field>
-          </fields>
-          <name>PROC1_INTF0</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0144</addressOffset>
-          <description>Interrupt Force for proc1</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[31:31]</bitRange>
-              <name>GPIO15_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[30:30]</bitRange>
-              <name>GPIO15_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[29:29]</bitRange>
-              <name>GPIO15_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[28:28]</bitRange>
-              <name>GPIO15_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[27:27]</bitRange>
-              <name>GPIO14_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[26:26]</bitRange>
-              <name>GPIO14_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[25:25]</bitRange>
-              <name>GPIO14_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[24:24]</bitRange>
-              <name>GPIO14_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[23:23]</bitRange>
-              <name>GPIO13_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[22:22]</bitRange>
-              <name>GPIO13_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[21:21]</bitRange>
-              <name>GPIO13_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[20:20]</bitRange>
-              <name>GPIO13_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[19:19]</bitRange>
-              <name>GPIO12_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[18:18]</bitRange>
-              <name>GPIO12_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[17:17]</bitRange>
-              <name>GPIO12_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[16:16]</bitRange>
-              <name>GPIO12_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[15:15]</bitRange>
-              <name>GPIO11_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[14:14]</bitRange>
-              <name>GPIO11_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[13:13]</bitRange>
-              <name>GPIO11_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[12:12]</bitRange>
-              <name>GPIO11_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[11:11]</bitRange>
-              <name>GPIO10_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[10:10]</bitRange>
-              <name>GPIO10_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[9:9]</bitRange>
-              <name>GPIO10_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[8:8]</bitRange>
-              <name>GPIO10_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[7:7]</bitRange>
-              <name>GPIO9_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[6:6]</bitRange>
-              <name>GPIO9_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[5:5]</bitRange>
-              <name>GPIO9_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[4:4]</bitRange>
-              <name>GPIO9_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[3:3]</bitRange>
-              <name>GPIO8_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[2:2]</bitRange>
-              <name>GPIO8_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[1:1]</bitRange>
-              <name>GPIO8_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[0:0]</bitRange>
-              <name>GPIO8_LEVEL_LOW</name>
-            </field>
-          </fields>
-          <name>PROC1_INTF1</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0148</addressOffset>
-          <description>Interrupt Force for proc1</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[31:31]</bitRange>
-              <name>GPIO23_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[30:30]</bitRange>
-              <name>GPIO23_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[29:29]</bitRange>
-              <name>GPIO23_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[28:28]</bitRange>
-              <name>GPIO23_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[27:27]</bitRange>
-              <name>GPIO22_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[26:26]</bitRange>
-              <name>GPIO22_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[25:25]</bitRange>
-              <name>GPIO22_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[24:24]</bitRange>
-              <name>GPIO22_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[23:23]</bitRange>
-              <name>GPIO21_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[22:22]</bitRange>
-              <name>GPIO21_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[21:21]</bitRange>
-              <name>GPIO21_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[20:20]</bitRange>
-              <name>GPIO21_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[19:19]</bitRange>
-              <name>GPIO20_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[18:18]</bitRange>
-              <name>GPIO20_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[17:17]</bitRange>
-              <name>GPIO20_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[16:16]</bitRange>
-              <name>GPIO20_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[15:15]</bitRange>
-              <name>GPIO19_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[14:14]</bitRange>
-              <name>GPIO19_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[13:13]</bitRange>
-              <name>GPIO19_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[12:12]</bitRange>
-              <name>GPIO19_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[11:11]</bitRange>
-              <name>GPIO18_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[10:10]</bitRange>
-              <name>GPIO18_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[9:9]</bitRange>
-              <name>GPIO18_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[8:8]</bitRange>
-              <name>GPIO18_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[7:7]</bitRange>
-              <name>GPIO17_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[6:6]</bitRange>
-              <name>GPIO17_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[5:5]</bitRange>
-              <name>GPIO17_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[4:4]</bitRange>
-              <name>GPIO17_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[3:3]</bitRange>
-              <name>GPIO16_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[2:2]</bitRange>
-              <name>GPIO16_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[1:1]</bitRange>
-              <name>GPIO16_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[0:0]</bitRange>
-              <name>GPIO16_LEVEL_LOW</name>
-            </field>
-          </fields>
-          <name>PROC1_INTF2</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x014c</addressOffset>
-          <description>Interrupt Force for proc1</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[23:23]</bitRange>
-              <name>GPIO29_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[22:22]</bitRange>
-              <name>GPIO29_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[21:21]</bitRange>
-              <name>GPIO29_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[20:20]</bitRange>
-              <name>GPIO29_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[19:19]</bitRange>
-              <name>GPIO28_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[18:18]</bitRange>
-              <name>GPIO28_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[17:17]</bitRange>
-              <name>GPIO28_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[16:16]</bitRange>
-              <name>GPIO28_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[15:15]</bitRange>
-              <name>GPIO27_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[14:14]</bitRange>
-              <name>GPIO27_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[13:13]</bitRange>
-              <name>GPIO27_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[12:12]</bitRange>
-              <name>GPIO27_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[11:11]</bitRange>
-              <name>GPIO26_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[10:10]</bitRange>
-              <name>GPIO26_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[9:9]</bitRange>
-              <name>GPIO26_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[8:8]</bitRange>
-              <name>GPIO26_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[7:7]</bitRange>
-              <name>GPIO25_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[6:6]</bitRange>
-              <name>GPIO25_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[5:5]</bitRange>
-              <name>GPIO25_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[4:4]</bitRange>
-              <name>GPIO25_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[3:3]</bitRange>
-              <name>GPIO24_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[2:2]</bitRange>
-              <name>GPIO24_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[1:1]</bitRange>
-              <name>GPIO24_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[0:0]</bitRange>
-              <name>GPIO24_LEVEL_LOW</name>
-            </field>
-          </fields>
-          <name>PROC1_INTF3</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0150</addressOffset>
-          <description>Interrupt status after masking &amp; forcing for proc1</description>
-          <fields>
-            <field>
-              <access>read-only</access>
-              <bitRange>[31:31]</bitRange>
-              <name>GPIO7_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[30:30]</bitRange>
-              <name>GPIO7_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[29:29]</bitRange>
-              <name>GPIO7_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[28:28]</bitRange>
-              <name>GPIO7_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[27:27]</bitRange>
-              <name>GPIO6_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[26:26]</bitRange>
-              <name>GPIO6_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[25:25]</bitRange>
-              <name>GPIO6_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[24:24]</bitRange>
-              <name>GPIO6_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[23:23]</bitRange>
-              <name>GPIO5_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[22:22]</bitRange>
-              <name>GPIO5_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[21:21]</bitRange>
-              <name>GPIO5_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[20:20]</bitRange>
-              <name>GPIO5_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[19:19]</bitRange>
-              <name>GPIO4_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[18:18]</bitRange>
-              <name>GPIO4_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[17:17]</bitRange>
-              <name>GPIO4_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[16:16]</bitRange>
-              <name>GPIO4_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[15:15]</bitRange>
-              <name>GPIO3_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[14:14]</bitRange>
-              <name>GPIO3_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[13:13]</bitRange>
-              <name>GPIO3_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[12:12]</bitRange>
-              <name>GPIO3_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[11:11]</bitRange>
-              <name>GPIO2_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[10:10]</bitRange>
-              <name>GPIO2_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[9:9]</bitRange>
-              <name>GPIO2_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[8:8]</bitRange>
-              <name>GPIO2_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[7:7]</bitRange>
-              <name>GPIO1_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[6:6]</bitRange>
-              <name>GPIO1_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[5:5]</bitRange>
-              <name>GPIO1_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[4:4]</bitRange>
-              <name>GPIO1_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[3:3]</bitRange>
-              <name>GPIO0_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[2:2]</bitRange>
-              <name>GPIO0_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[1:1]</bitRange>
-              <name>GPIO0_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[0:0]</bitRange>
-              <name>GPIO0_LEVEL_LOW</name>
-            </field>
-          </fields>
-          <name>PROC1_INTS0</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0154</addressOffset>
-          <description>Interrupt status after masking &amp; forcing for proc1</description>
-          <fields>
-            <field>
-              <access>read-only</access>
-              <bitRange>[31:31]</bitRange>
-              <name>GPIO15_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[30:30]</bitRange>
-              <name>GPIO15_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[29:29]</bitRange>
-              <name>GPIO15_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[28:28]</bitRange>
-              <name>GPIO15_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[27:27]</bitRange>
-              <name>GPIO14_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[26:26]</bitRange>
-              <name>GPIO14_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[25:25]</bitRange>
-              <name>GPIO14_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[24:24]</bitRange>
-              <name>GPIO14_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[23:23]</bitRange>
-              <name>GPIO13_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[22:22]</bitRange>
-              <name>GPIO13_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[21:21]</bitRange>
-              <name>GPIO13_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[20:20]</bitRange>
-              <name>GPIO13_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[19:19]</bitRange>
-              <name>GPIO12_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[18:18]</bitRange>
-              <name>GPIO12_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[17:17]</bitRange>
-              <name>GPIO12_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[16:16]</bitRange>
-              <name>GPIO12_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[15:15]</bitRange>
-              <name>GPIO11_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[14:14]</bitRange>
-              <name>GPIO11_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[13:13]</bitRange>
-              <name>GPIO11_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[12:12]</bitRange>
-              <name>GPIO11_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[11:11]</bitRange>
-              <name>GPIO10_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[10:10]</bitRange>
-              <name>GPIO10_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[9:9]</bitRange>
-              <name>GPIO10_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[8:8]</bitRange>
-              <name>GPIO10_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[7:7]</bitRange>
-              <name>GPIO9_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[6:6]</bitRange>
-              <name>GPIO9_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[5:5]</bitRange>
-              <name>GPIO9_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[4:4]</bitRange>
-              <name>GPIO9_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[3:3]</bitRange>
-              <name>GPIO8_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[2:2]</bitRange>
-              <name>GPIO8_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[1:1]</bitRange>
-              <name>GPIO8_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[0:0]</bitRange>
-              <name>GPIO8_LEVEL_LOW</name>
-            </field>
-          </fields>
-          <name>PROC1_INTS1</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0158</addressOffset>
-          <description>Interrupt status after masking &amp; forcing for proc1</description>
-          <fields>
-            <field>
-              <access>read-only</access>
-              <bitRange>[31:31]</bitRange>
-              <name>GPIO23_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[30:30]</bitRange>
-              <name>GPIO23_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[29:29]</bitRange>
-              <name>GPIO23_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[28:28]</bitRange>
-              <name>GPIO23_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[27:27]</bitRange>
-              <name>GPIO22_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[26:26]</bitRange>
-              <name>GPIO22_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[25:25]</bitRange>
-              <name>GPIO22_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[24:24]</bitRange>
-              <name>GPIO22_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[23:23]</bitRange>
-              <name>GPIO21_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[22:22]</bitRange>
-              <name>GPIO21_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[21:21]</bitRange>
-              <name>GPIO21_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[20:20]</bitRange>
-              <name>GPIO21_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[19:19]</bitRange>
-              <name>GPIO20_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[18:18]</bitRange>
-              <name>GPIO20_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[17:17]</bitRange>
-              <name>GPIO20_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[16:16]</bitRange>
-              <name>GPIO20_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[15:15]</bitRange>
-              <name>GPIO19_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[14:14]</bitRange>
-              <name>GPIO19_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[13:13]</bitRange>
-              <name>GPIO19_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[12:12]</bitRange>
-              <name>GPIO19_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[11:11]</bitRange>
-              <name>GPIO18_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[10:10]</bitRange>
-              <name>GPIO18_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[9:9]</bitRange>
-              <name>GPIO18_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[8:8]</bitRange>
-              <name>GPIO18_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[7:7]</bitRange>
-              <name>GPIO17_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[6:6]</bitRange>
-              <name>GPIO17_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[5:5]</bitRange>
-              <name>GPIO17_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[4:4]</bitRange>
-              <name>GPIO17_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[3:3]</bitRange>
-              <name>GPIO16_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[2:2]</bitRange>
-              <name>GPIO16_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[1:1]</bitRange>
-              <name>GPIO16_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[0:0]</bitRange>
-              <name>GPIO16_LEVEL_LOW</name>
-            </field>
-          </fields>
-          <name>PROC1_INTS2</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x015c</addressOffset>
-          <description>Interrupt status after masking &amp; forcing for proc1</description>
-          <fields>
-            <field>
-              <access>read-only</access>
-              <bitRange>[23:23]</bitRange>
-              <name>GPIO29_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[22:22]</bitRange>
-              <name>GPIO29_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[21:21]</bitRange>
-              <name>GPIO29_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[20:20]</bitRange>
-              <name>GPIO29_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[19:19]</bitRange>
-              <name>GPIO28_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[18:18]</bitRange>
-              <name>GPIO28_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[17:17]</bitRange>
-              <name>GPIO28_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[16:16]</bitRange>
-              <name>GPIO28_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[15:15]</bitRange>
-              <name>GPIO27_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[14:14]</bitRange>
-              <name>GPIO27_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[13:13]</bitRange>
-              <name>GPIO27_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[12:12]</bitRange>
-              <name>GPIO27_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[11:11]</bitRange>
-              <name>GPIO26_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[10:10]</bitRange>
-              <name>GPIO26_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[9:9]</bitRange>
-              <name>GPIO26_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[8:8]</bitRange>
-              <name>GPIO26_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[7:7]</bitRange>
-              <name>GPIO25_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[6:6]</bitRange>
-              <name>GPIO25_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[5:5]</bitRange>
-              <name>GPIO25_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[4:4]</bitRange>
-              <name>GPIO25_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[3:3]</bitRange>
-              <name>GPIO24_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[2:2]</bitRange>
-              <name>GPIO24_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[1:1]</bitRange>
-              <name>GPIO24_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[0:0]</bitRange>
-              <name>GPIO24_LEVEL_LOW</name>
-            </field>
-          </fields>
-          <name>PROC1_INTS3</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0160</addressOffset>
-          <description>Interrupt Enable for dormant_wake</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[31:31]</bitRange>
-              <name>GPIO7_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[30:30]</bitRange>
-              <name>GPIO7_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[29:29]</bitRange>
-              <name>GPIO7_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[28:28]</bitRange>
-              <name>GPIO7_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[27:27]</bitRange>
-              <name>GPIO6_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[26:26]</bitRange>
-              <name>GPIO6_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[25:25]</bitRange>
-              <name>GPIO6_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[24:24]</bitRange>
-              <name>GPIO6_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[23:23]</bitRange>
-              <name>GPIO5_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[22:22]</bitRange>
-              <name>GPIO5_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[21:21]</bitRange>
-              <name>GPIO5_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[20:20]</bitRange>
-              <name>GPIO5_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[19:19]</bitRange>
-              <name>GPIO4_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[18:18]</bitRange>
-              <name>GPIO4_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[17:17]</bitRange>
-              <name>GPIO4_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[16:16]</bitRange>
-              <name>GPIO4_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[15:15]</bitRange>
-              <name>GPIO3_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[14:14]</bitRange>
-              <name>GPIO3_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[13:13]</bitRange>
-              <name>GPIO3_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[12:12]</bitRange>
-              <name>GPIO3_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[11:11]</bitRange>
-              <name>GPIO2_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[10:10]</bitRange>
-              <name>GPIO2_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[9:9]</bitRange>
-              <name>GPIO2_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[8:8]</bitRange>
-              <name>GPIO2_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[7:7]</bitRange>
-              <name>GPIO1_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[6:6]</bitRange>
-              <name>GPIO1_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[5:5]</bitRange>
-              <name>GPIO1_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[4:4]</bitRange>
-              <name>GPIO1_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[3:3]</bitRange>
-              <name>GPIO0_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[2:2]</bitRange>
-              <name>GPIO0_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[1:1]</bitRange>
-              <name>GPIO0_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[0:0]</bitRange>
-              <name>GPIO0_LEVEL_LOW</name>
-            </field>
-          </fields>
-          <name>DORMANT_WAKE_INTE0</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0164</addressOffset>
-          <description>Interrupt Enable for dormant_wake</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[31:31]</bitRange>
-              <name>GPIO15_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[30:30]</bitRange>
-              <name>GPIO15_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[29:29]</bitRange>
-              <name>GPIO15_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[28:28]</bitRange>
-              <name>GPIO15_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[27:27]</bitRange>
-              <name>GPIO14_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[26:26]</bitRange>
-              <name>GPIO14_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[25:25]</bitRange>
-              <name>GPIO14_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[24:24]</bitRange>
-              <name>GPIO14_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[23:23]</bitRange>
-              <name>GPIO13_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[22:22]</bitRange>
-              <name>GPIO13_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[21:21]</bitRange>
-              <name>GPIO13_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[20:20]</bitRange>
-              <name>GPIO13_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[19:19]</bitRange>
-              <name>GPIO12_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[18:18]</bitRange>
-              <name>GPIO12_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[17:17]</bitRange>
-              <name>GPIO12_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[16:16]</bitRange>
-              <name>GPIO12_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[15:15]</bitRange>
-              <name>GPIO11_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[14:14]</bitRange>
-              <name>GPIO11_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[13:13]</bitRange>
-              <name>GPIO11_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[12:12]</bitRange>
-              <name>GPIO11_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[11:11]</bitRange>
-              <name>GPIO10_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[10:10]</bitRange>
-              <name>GPIO10_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[9:9]</bitRange>
-              <name>GPIO10_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[8:8]</bitRange>
-              <name>GPIO10_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[7:7]</bitRange>
-              <name>GPIO9_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[6:6]</bitRange>
-              <name>GPIO9_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[5:5]</bitRange>
-              <name>GPIO9_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[4:4]</bitRange>
-              <name>GPIO9_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[3:3]</bitRange>
-              <name>GPIO8_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[2:2]</bitRange>
-              <name>GPIO8_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[1:1]</bitRange>
-              <name>GPIO8_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[0:0]</bitRange>
-              <name>GPIO8_LEVEL_LOW</name>
-            </field>
-          </fields>
-          <name>DORMANT_WAKE_INTE1</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0168</addressOffset>
-          <description>Interrupt Enable for dormant_wake</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[31:31]</bitRange>
-              <name>GPIO23_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[30:30]</bitRange>
-              <name>GPIO23_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[29:29]</bitRange>
-              <name>GPIO23_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[28:28]</bitRange>
-              <name>GPIO23_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[27:27]</bitRange>
-              <name>GPIO22_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[26:26]</bitRange>
-              <name>GPIO22_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[25:25]</bitRange>
-              <name>GPIO22_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[24:24]</bitRange>
-              <name>GPIO22_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[23:23]</bitRange>
-              <name>GPIO21_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[22:22]</bitRange>
-              <name>GPIO21_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[21:21]</bitRange>
-              <name>GPIO21_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[20:20]</bitRange>
-              <name>GPIO21_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[19:19]</bitRange>
-              <name>GPIO20_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[18:18]</bitRange>
-              <name>GPIO20_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[17:17]</bitRange>
-              <name>GPIO20_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[16:16]</bitRange>
-              <name>GPIO20_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[15:15]</bitRange>
-              <name>GPIO19_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[14:14]</bitRange>
-              <name>GPIO19_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[13:13]</bitRange>
-              <name>GPIO19_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[12:12]</bitRange>
-              <name>GPIO19_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[11:11]</bitRange>
-              <name>GPIO18_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[10:10]</bitRange>
-              <name>GPIO18_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[9:9]</bitRange>
-              <name>GPIO18_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[8:8]</bitRange>
-              <name>GPIO18_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[7:7]</bitRange>
-              <name>GPIO17_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[6:6]</bitRange>
-              <name>GPIO17_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[5:5]</bitRange>
-              <name>GPIO17_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[4:4]</bitRange>
-              <name>GPIO17_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[3:3]</bitRange>
-              <name>GPIO16_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[2:2]</bitRange>
-              <name>GPIO16_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[1:1]</bitRange>
-              <name>GPIO16_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[0:0]</bitRange>
-              <name>GPIO16_LEVEL_LOW</name>
-            </field>
-          </fields>
-          <name>DORMANT_WAKE_INTE2</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x016c</addressOffset>
-          <description>Interrupt Enable for dormant_wake</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[23:23]</bitRange>
-              <name>GPIO29_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[22:22]</bitRange>
-              <name>GPIO29_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[21:21]</bitRange>
-              <name>GPIO29_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[20:20]</bitRange>
-              <name>GPIO29_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[19:19]</bitRange>
-              <name>GPIO28_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[18:18]</bitRange>
-              <name>GPIO28_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[17:17]</bitRange>
-              <name>GPIO28_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[16:16]</bitRange>
-              <name>GPIO28_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[15:15]</bitRange>
-              <name>GPIO27_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[14:14]</bitRange>
-              <name>GPIO27_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[13:13]</bitRange>
-              <name>GPIO27_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[12:12]</bitRange>
-              <name>GPIO27_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[11:11]</bitRange>
-              <name>GPIO26_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[10:10]</bitRange>
-              <name>GPIO26_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[9:9]</bitRange>
-              <name>GPIO26_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[8:8]</bitRange>
-              <name>GPIO26_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[7:7]</bitRange>
-              <name>GPIO25_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[6:6]</bitRange>
-              <name>GPIO25_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[5:5]</bitRange>
-              <name>GPIO25_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[4:4]</bitRange>
-              <name>GPIO25_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[3:3]</bitRange>
-              <name>GPIO24_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[2:2]</bitRange>
-              <name>GPIO24_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[1:1]</bitRange>
-              <name>GPIO24_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[0:0]</bitRange>
-              <name>GPIO24_LEVEL_LOW</name>
-            </field>
-          </fields>
-          <name>DORMANT_WAKE_INTE3</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0170</addressOffset>
-          <description>Interrupt Force for dormant_wake</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[31:31]</bitRange>
-              <name>GPIO7_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[30:30]</bitRange>
-              <name>GPIO7_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[29:29]</bitRange>
-              <name>GPIO7_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[28:28]</bitRange>
-              <name>GPIO7_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[27:27]</bitRange>
-              <name>GPIO6_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[26:26]</bitRange>
-              <name>GPIO6_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[25:25]</bitRange>
-              <name>GPIO6_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[24:24]</bitRange>
-              <name>GPIO6_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[23:23]</bitRange>
-              <name>GPIO5_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[22:22]</bitRange>
-              <name>GPIO5_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[21:21]</bitRange>
-              <name>GPIO5_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[20:20]</bitRange>
-              <name>GPIO5_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[19:19]</bitRange>
-              <name>GPIO4_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[18:18]</bitRange>
-              <name>GPIO4_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[17:17]</bitRange>
-              <name>GPIO4_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[16:16]</bitRange>
-              <name>GPIO4_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[15:15]</bitRange>
-              <name>GPIO3_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[14:14]</bitRange>
-              <name>GPIO3_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[13:13]</bitRange>
-              <name>GPIO3_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[12:12]</bitRange>
-              <name>GPIO3_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[11:11]</bitRange>
-              <name>GPIO2_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[10:10]</bitRange>
-              <name>GPIO2_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[9:9]</bitRange>
-              <name>GPIO2_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[8:8]</bitRange>
-              <name>GPIO2_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[7:7]</bitRange>
-              <name>GPIO1_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[6:6]</bitRange>
-              <name>GPIO1_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[5:5]</bitRange>
-              <name>GPIO1_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[4:4]</bitRange>
-              <name>GPIO1_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[3:3]</bitRange>
-              <name>GPIO0_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[2:2]</bitRange>
-              <name>GPIO0_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[1:1]</bitRange>
-              <name>GPIO0_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[0:0]</bitRange>
-              <name>GPIO0_LEVEL_LOW</name>
-            </field>
-          </fields>
-          <name>DORMANT_WAKE_INTF0</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0174</addressOffset>
-          <description>Interrupt Force for dormant_wake</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[31:31]</bitRange>
-              <name>GPIO15_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[30:30]</bitRange>
-              <name>GPIO15_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[29:29]</bitRange>
-              <name>GPIO15_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[28:28]</bitRange>
-              <name>GPIO15_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[27:27]</bitRange>
-              <name>GPIO14_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[26:26]</bitRange>
-              <name>GPIO14_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[25:25]</bitRange>
-              <name>GPIO14_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[24:24]</bitRange>
-              <name>GPIO14_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[23:23]</bitRange>
-              <name>GPIO13_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[22:22]</bitRange>
-              <name>GPIO13_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[21:21]</bitRange>
-              <name>GPIO13_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[20:20]</bitRange>
-              <name>GPIO13_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[19:19]</bitRange>
-              <name>GPIO12_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[18:18]</bitRange>
-              <name>GPIO12_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[17:17]</bitRange>
-              <name>GPIO12_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[16:16]</bitRange>
-              <name>GPIO12_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[15:15]</bitRange>
-              <name>GPIO11_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[14:14]</bitRange>
-              <name>GPIO11_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[13:13]</bitRange>
-              <name>GPIO11_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[12:12]</bitRange>
-              <name>GPIO11_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[11:11]</bitRange>
-              <name>GPIO10_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[10:10]</bitRange>
-              <name>GPIO10_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[9:9]</bitRange>
-              <name>GPIO10_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[8:8]</bitRange>
-              <name>GPIO10_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[7:7]</bitRange>
-              <name>GPIO9_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[6:6]</bitRange>
-              <name>GPIO9_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[5:5]</bitRange>
-              <name>GPIO9_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[4:4]</bitRange>
-              <name>GPIO9_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[3:3]</bitRange>
-              <name>GPIO8_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[2:2]</bitRange>
-              <name>GPIO8_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[1:1]</bitRange>
-              <name>GPIO8_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[0:0]</bitRange>
-              <name>GPIO8_LEVEL_LOW</name>
-            </field>
-          </fields>
-          <name>DORMANT_WAKE_INTF1</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0178</addressOffset>
-          <description>Interrupt Force for dormant_wake</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[31:31]</bitRange>
-              <name>GPIO23_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[30:30]</bitRange>
-              <name>GPIO23_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[29:29]</bitRange>
-              <name>GPIO23_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[28:28]</bitRange>
-              <name>GPIO23_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[27:27]</bitRange>
-              <name>GPIO22_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[26:26]</bitRange>
-              <name>GPIO22_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[25:25]</bitRange>
-              <name>GPIO22_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[24:24]</bitRange>
-              <name>GPIO22_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[23:23]</bitRange>
-              <name>GPIO21_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[22:22]</bitRange>
-              <name>GPIO21_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[21:21]</bitRange>
-              <name>GPIO21_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[20:20]</bitRange>
-              <name>GPIO21_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[19:19]</bitRange>
-              <name>GPIO20_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[18:18]</bitRange>
-              <name>GPIO20_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[17:17]</bitRange>
-              <name>GPIO20_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[16:16]</bitRange>
-              <name>GPIO20_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[15:15]</bitRange>
-              <name>GPIO19_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[14:14]</bitRange>
-              <name>GPIO19_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[13:13]</bitRange>
-              <name>GPIO19_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[12:12]</bitRange>
-              <name>GPIO19_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[11:11]</bitRange>
-              <name>GPIO18_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[10:10]</bitRange>
-              <name>GPIO18_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[9:9]</bitRange>
-              <name>GPIO18_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[8:8]</bitRange>
-              <name>GPIO18_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[7:7]</bitRange>
-              <name>GPIO17_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[6:6]</bitRange>
-              <name>GPIO17_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[5:5]</bitRange>
-              <name>GPIO17_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[4:4]</bitRange>
-              <name>GPIO17_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[3:3]</bitRange>
-              <name>GPIO16_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[2:2]</bitRange>
-              <name>GPIO16_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[1:1]</bitRange>
-              <name>GPIO16_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[0:0]</bitRange>
-              <name>GPIO16_LEVEL_LOW</name>
-            </field>
-          </fields>
-          <name>DORMANT_WAKE_INTF2</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x017c</addressOffset>
-          <description>Interrupt Force for dormant_wake</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[23:23]</bitRange>
-              <name>GPIO29_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[22:22]</bitRange>
-              <name>GPIO29_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[21:21]</bitRange>
-              <name>GPIO29_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[20:20]</bitRange>
-              <name>GPIO29_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[19:19]</bitRange>
-              <name>GPIO28_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[18:18]</bitRange>
-              <name>GPIO28_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[17:17]</bitRange>
-              <name>GPIO28_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[16:16]</bitRange>
-              <name>GPIO28_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[15:15]</bitRange>
-              <name>GPIO27_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[14:14]</bitRange>
-              <name>GPIO27_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[13:13]</bitRange>
-              <name>GPIO27_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[12:12]</bitRange>
-              <name>GPIO27_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[11:11]</bitRange>
-              <name>GPIO26_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[10:10]</bitRange>
-              <name>GPIO26_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[9:9]</bitRange>
-              <name>GPIO26_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[8:8]</bitRange>
-              <name>GPIO26_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[7:7]</bitRange>
-              <name>GPIO25_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[6:6]</bitRange>
-              <name>GPIO25_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[5:5]</bitRange>
-              <name>GPIO25_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[4:4]</bitRange>
-              <name>GPIO25_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[3:3]</bitRange>
-              <name>GPIO24_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[2:2]</bitRange>
-              <name>GPIO24_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[1:1]</bitRange>
-              <name>GPIO24_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[0:0]</bitRange>
-              <name>GPIO24_LEVEL_LOW</name>
-            </field>
-          </fields>
-          <name>DORMANT_WAKE_INTF3</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0180</addressOffset>
-          <description>Interrupt status after masking &amp; forcing for dormant_wake</description>
-          <fields>
-            <field>
-              <access>read-only</access>
-              <bitRange>[31:31]</bitRange>
-              <name>GPIO7_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[30:30]</bitRange>
-              <name>GPIO7_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[29:29]</bitRange>
-              <name>GPIO7_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[28:28]</bitRange>
-              <name>GPIO7_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[27:27]</bitRange>
-              <name>GPIO6_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[26:26]</bitRange>
-              <name>GPIO6_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[25:25]</bitRange>
-              <name>GPIO6_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[24:24]</bitRange>
-              <name>GPIO6_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[23:23]</bitRange>
-              <name>GPIO5_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[22:22]</bitRange>
-              <name>GPIO5_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[21:21]</bitRange>
-              <name>GPIO5_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[20:20]</bitRange>
-              <name>GPIO5_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[19:19]</bitRange>
-              <name>GPIO4_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[18:18]</bitRange>
-              <name>GPIO4_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[17:17]</bitRange>
-              <name>GPIO4_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[16:16]</bitRange>
-              <name>GPIO4_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[15:15]</bitRange>
-              <name>GPIO3_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[14:14]</bitRange>
-              <name>GPIO3_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[13:13]</bitRange>
-              <name>GPIO3_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[12:12]</bitRange>
-              <name>GPIO3_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[11:11]</bitRange>
-              <name>GPIO2_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[10:10]</bitRange>
-              <name>GPIO2_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[9:9]</bitRange>
-              <name>GPIO2_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[8:8]</bitRange>
-              <name>GPIO2_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[7:7]</bitRange>
-              <name>GPIO1_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[6:6]</bitRange>
-              <name>GPIO1_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[5:5]</bitRange>
-              <name>GPIO1_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[4:4]</bitRange>
-              <name>GPIO1_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[3:3]</bitRange>
-              <name>GPIO0_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[2:2]</bitRange>
-              <name>GPIO0_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[1:1]</bitRange>
-              <name>GPIO0_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[0:0]</bitRange>
-              <name>GPIO0_LEVEL_LOW</name>
-            </field>
-          </fields>
-          <name>DORMANT_WAKE_INTS0</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0184</addressOffset>
-          <description>Interrupt status after masking &amp; forcing for dormant_wake</description>
-          <fields>
-            <field>
-              <access>read-only</access>
-              <bitRange>[31:31]</bitRange>
-              <name>GPIO15_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[30:30]</bitRange>
-              <name>GPIO15_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[29:29]</bitRange>
-              <name>GPIO15_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[28:28]</bitRange>
-              <name>GPIO15_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[27:27]</bitRange>
-              <name>GPIO14_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[26:26]</bitRange>
-              <name>GPIO14_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[25:25]</bitRange>
-              <name>GPIO14_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[24:24]</bitRange>
-              <name>GPIO14_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[23:23]</bitRange>
-              <name>GPIO13_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[22:22]</bitRange>
-              <name>GPIO13_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[21:21]</bitRange>
-              <name>GPIO13_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[20:20]</bitRange>
-              <name>GPIO13_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[19:19]</bitRange>
-              <name>GPIO12_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[18:18]</bitRange>
-              <name>GPIO12_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[17:17]</bitRange>
-              <name>GPIO12_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[16:16]</bitRange>
-              <name>GPIO12_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[15:15]</bitRange>
-              <name>GPIO11_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[14:14]</bitRange>
-              <name>GPIO11_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[13:13]</bitRange>
-              <name>GPIO11_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[12:12]</bitRange>
-              <name>GPIO11_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[11:11]</bitRange>
-              <name>GPIO10_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[10:10]</bitRange>
-              <name>GPIO10_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[9:9]</bitRange>
-              <name>GPIO10_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[8:8]</bitRange>
-              <name>GPIO10_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[7:7]</bitRange>
-              <name>GPIO9_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[6:6]</bitRange>
-              <name>GPIO9_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[5:5]</bitRange>
-              <name>GPIO9_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[4:4]</bitRange>
-              <name>GPIO9_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[3:3]</bitRange>
-              <name>GPIO8_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[2:2]</bitRange>
-              <name>GPIO8_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[1:1]</bitRange>
-              <name>GPIO8_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[0:0]</bitRange>
-              <name>GPIO8_LEVEL_LOW</name>
-            </field>
-          </fields>
-          <name>DORMANT_WAKE_INTS1</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0188</addressOffset>
-          <description>Interrupt status after masking &amp; forcing for dormant_wake</description>
-          <fields>
-            <field>
-              <access>read-only</access>
-              <bitRange>[31:31]</bitRange>
-              <name>GPIO23_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[30:30]</bitRange>
-              <name>GPIO23_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[29:29]</bitRange>
-              <name>GPIO23_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[28:28]</bitRange>
-              <name>GPIO23_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[27:27]</bitRange>
-              <name>GPIO22_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[26:26]</bitRange>
-              <name>GPIO22_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[25:25]</bitRange>
-              <name>GPIO22_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[24:24]</bitRange>
-              <name>GPIO22_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[23:23]</bitRange>
-              <name>GPIO21_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[22:22]</bitRange>
-              <name>GPIO21_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[21:21]</bitRange>
-              <name>GPIO21_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[20:20]</bitRange>
-              <name>GPIO21_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[19:19]</bitRange>
-              <name>GPIO20_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[18:18]</bitRange>
-              <name>GPIO20_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[17:17]</bitRange>
-              <name>GPIO20_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[16:16]</bitRange>
-              <name>GPIO20_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[15:15]</bitRange>
-              <name>GPIO19_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[14:14]</bitRange>
-              <name>GPIO19_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[13:13]</bitRange>
-              <name>GPIO19_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[12:12]</bitRange>
-              <name>GPIO19_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[11:11]</bitRange>
-              <name>GPIO18_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[10:10]</bitRange>
-              <name>GPIO18_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[9:9]</bitRange>
-              <name>GPIO18_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[8:8]</bitRange>
-              <name>GPIO18_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[7:7]</bitRange>
-              <name>GPIO17_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[6:6]</bitRange>
-              <name>GPIO17_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[5:5]</bitRange>
-              <name>GPIO17_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[4:4]</bitRange>
-              <name>GPIO17_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[3:3]</bitRange>
-              <name>GPIO16_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[2:2]</bitRange>
-              <name>GPIO16_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[1:1]</bitRange>
-              <name>GPIO16_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[0:0]</bitRange>
-              <name>GPIO16_LEVEL_LOW</name>
-            </field>
-          </fields>
-          <name>DORMANT_WAKE_INTS2</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x018c</addressOffset>
-          <description>Interrupt status after masking &amp; forcing for dormant_wake</description>
-          <fields>
-            <field>
-              <access>read-only</access>
-              <bitRange>[23:23]</bitRange>
-              <name>GPIO29_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[22:22]</bitRange>
-              <name>GPIO29_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[21:21]</bitRange>
-              <name>GPIO29_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[20:20]</bitRange>
-              <name>GPIO29_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[19:19]</bitRange>
-              <name>GPIO28_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[18:18]</bitRange>
-              <name>GPIO28_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[17:17]</bitRange>
-              <name>GPIO28_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[16:16]</bitRange>
-              <name>GPIO28_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[15:15]</bitRange>
-              <name>GPIO27_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[14:14]</bitRange>
-              <name>GPIO27_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[13:13]</bitRange>
-              <name>GPIO27_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[12:12]</bitRange>
-              <name>GPIO27_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[11:11]</bitRange>
-              <name>GPIO26_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[10:10]</bitRange>
-              <name>GPIO26_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[9:9]</bitRange>
-              <name>GPIO26_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[8:8]</bitRange>
-              <name>GPIO26_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[7:7]</bitRange>
-              <name>GPIO25_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[6:6]</bitRange>
-              <name>GPIO25_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[5:5]</bitRange>
-              <name>GPIO25_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[4:4]</bitRange>
-              <name>GPIO25_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[3:3]</bitRange>
-              <name>GPIO24_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[2:2]</bitRange>
-              <name>GPIO24_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[1:1]</bitRange>
-              <name>GPIO24_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[0:0]</bitRange>
-              <name>GPIO24_LEVEL_LOW</name>
-            </field>
-          </fields>
-          <name>DORMANT_WAKE_INTS3</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-      </registers>
-      <size>32</size>
-      <version>1</version>
-    </peripheral>
-    <peripheral>
-      <addressBlock>
-        <offset>0</offset>
-        <size>0x1000</size>
-        <usage>registers</usage>
-      </addressBlock>
-      <baseAddress>0x40018000</baseAddress>
-      <interrupt>
-        <name>IO_IRQ_QSPI</name>
-        <value>14</value>
-      </interrupt>
-      <name>IO_QSPI</name>
-      <registers>
-        <register>
-          <addressOffset>0x0000</addressOffset>
-          <description>GPIO status</description>
-          <fields>
-            <field>
-              <access>read-only</access>
-              <bitRange>[26:26]</bitRange>
-              <description>interrupt to processors, after override is applied</description>
-              <name>IRQTOPROC</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[24:24]</bitRange>
-              <description>interrupt from pad before override is applied</description>
-              <name>IRQFROMPAD</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[19:19]</bitRange>
-              <description>input signal to peripheral, after override is applied</description>
-              <name>INTOPERI</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[17:17]</bitRange>
-              <description>input signal from pad, before override is applied</description>
-              <name>INFROMPAD</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[13:13]</bitRange>
-              <description>output enable to pad after register override is applied</description>
-              <name>OETOPAD</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[12:12]</bitRange>
-              <description>output enable from selected peripheral, before register override is applied</description>
-              <name>OEFROMPERI</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[9:9]</bitRange>
-              <description>output signal to pad after register override is applied</description>
-              <name>OUTTOPAD</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[8:8]</bitRange>
-              <description>output signal from selected peripheral, before register override is applied</description>
-              <name>OUTFROMPERI</name>
-            </field>
-          </fields>
-          <name>GPIO_QSPI_SCLK_STATUS</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0004</addressOffset>
-          <description>GPIO control including function select and overrides.</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[29:28]</bitRange>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>don't invert the interrupt</description>
-                  <name>NORMAL</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>invert the interrupt</description>
-                  <name>INVERT</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive interrupt low</description>
-                  <name>LOW</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive interrupt high</description>
-                  <name>HIGH</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>IRQOVER</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[17:16]</bitRange>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>don't invert the peri input</description>
-                  <name>NORMAL</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>invert the peri input</description>
-                  <name>INVERT</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive peri input low</description>
-                  <name>LOW</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive peri input high</description>
-                  <name>HIGH</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>INOVER</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[13:12]</bitRange>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>drive output enable from peripheral signal selected by funcsel</description>
-                  <name>NORMAL</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
-                  <name>INVERT</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>disable output</description>
-                  <name>DISABLE</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>enable output</description>
-                  <name>ENABLE</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>OEOVER</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[9:8]</bitRange>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>drive output from peripheral signal selected by funcsel</description>
-                  <name>NORMAL</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive output from inverse of peripheral signal selected by funcsel</description>
-                  <name>INVERT</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive output low</description>
-                  <name>LOW</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive output high</description>
-                  <name>HIGH</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>OUTOVER</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[4:0]</bitRange>
-              <description>0-31 -&gt; selects pin function according to the gpio table\n
-                31 == NULL</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>xip_sclk</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>sio_30</name>
-                  <value>5</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>null</name>
-                  <value>31</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>FUNCSEL</name>
-            </field>
-          </fields>
-          <name>GPIO_QSPI_SCLK_CTRL</name>
-          <resetValue>0x0000001f</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0008</addressOffset>
-          <description>GPIO status</description>
-          <fields>
-            <field>
-              <access>read-only</access>
-              <bitRange>[26:26]</bitRange>
-              <description>interrupt to processors, after override is applied</description>
-              <name>IRQTOPROC</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[24:24]</bitRange>
-              <description>interrupt from pad before override is applied</description>
-              <name>IRQFROMPAD</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[19:19]</bitRange>
-              <description>input signal to peripheral, after override is applied</description>
-              <name>INTOPERI</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[17:17]</bitRange>
-              <description>input signal from pad, before override is applied</description>
-              <name>INFROMPAD</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[13:13]</bitRange>
-              <description>output enable to pad after register override is applied</description>
-              <name>OETOPAD</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[12:12]</bitRange>
-              <description>output enable from selected peripheral, before register override is applied</description>
-              <name>OEFROMPERI</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[9:9]</bitRange>
-              <description>output signal to pad after register override is applied</description>
-              <name>OUTTOPAD</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[8:8]</bitRange>
-              <description>output signal from selected peripheral, before register override is applied</description>
-              <name>OUTFROMPERI</name>
-            </field>
-          </fields>
-          <name>GPIO_QSPI_SS_STATUS</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x000c</addressOffset>
-          <description>GPIO control including function select and overrides.</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[29:28]</bitRange>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>don't invert the interrupt</description>
-                  <name>NORMAL</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>invert the interrupt</description>
-                  <name>INVERT</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive interrupt low</description>
-                  <name>LOW</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive interrupt high</description>
-                  <name>HIGH</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>IRQOVER</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[17:16]</bitRange>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>don't invert the peri input</description>
-                  <name>NORMAL</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>invert the peri input</description>
-                  <name>INVERT</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive peri input low</description>
-                  <name>LOW</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive peri input high</description>
-                  <name>HIGH</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>INOVER</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[13:12]</bitRange>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>drive output enable from peripheral signal selected by funcsel</description>
-                  <name>NORMAL</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
-                  <name>INVERT</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>disable output</description>
-                  <name>DISABLE</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>enable output</description>
-                  <name>ENABLE</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>OEOVER</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[9:8]</bitRange>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>drive output from peripheral signal selected by funcsel</description>
-                  <name>NORMAL</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive output from inverse of peripheral signal selected by funcsel</description>
-                  <name>INVERT</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive output low</description>
-                  <name>LOW</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive output high</description>
-                  <name>HIGH</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>OUTOVER</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[4:0]</bitRange>
-              <description>0-31 -&gt; selects pin function according to the gpio table\n
-                31 == NULL</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>xip_ss_n</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>sio_31</name>
-                  <value>5</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>null</name>
-                  <value>31</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>FUNCSEL</name>
-            </field>
-          </fields>
-          <name>GPIO_QSPI_SS_CTRL</name>
-          <resetValue>0x0000001f</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0010</addressOffset>
-          <description>GPIO status</description>
-          <fields>
-            <field>
-              <access>read-only</access>
-              <bitRange>[26:26]</bitRange>
-              <description>interrupt to processors, after override is applied</description>
-              <name>IRQTOPROC</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[24:24]</bitRange>
-              <description>interrupt from pad before override is applied</description>
-              <name>IRQFROMPAD</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[19:19]</bitRange>
-              <description>input signal to peripheral, after override is applied</description>
-              <name>INTOPERI</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[17:17]</bitRange>
-              <description>input signal from pad, before override is applied</description>
-              <name>INFROMPAD</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[13:13]</bitRange>
-              <description>output enable to pad after register override is applied</description>
-              <name>OETOPAD</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[12:12]</bitRange>
-              <description>output enable from selected peripheral, before register override is applied</description>
-              <name>OEFROMPERI</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[9:9]</bitRange>
-              <description>output signal to pad after register override is applied</description>
-              <name>OUTTOPAD</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[8:8]</bitRange>
-              <description>output signal from selected peripheral, before register override is applied</description>
-              <name>OUTFROMPERI</name>
-            </field>
-          </fields>
-          <name>GPIO_QSPI_SD0_STATUS</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0014</addressOffset>
-          <description>GPIO control including function select and overrides.</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[29:28]</bitRange>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>don't invert the interrupt</description>
-                  <name>NORMAL</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>invert the interrupt</description>
-                  <name>INVERT</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive interrupt low</description>
-                  <name>LOW</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive interrupt high</description>
-                  <name>HIGH</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>IRQOVER</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[17:16]</bitRange>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>don't invert the peri input</description>
-                  <name>NORMAL</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>invert the peri input</description>
-                  <name>INVERT</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive peri input low</description>
-                  <name>LOW</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive peri input high</description>
-                  <name>HIGH</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>INOVER</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[13:12]</bitRange>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>drive output enable from peripheral signal selected by funcsel</description>
-                  <name>NORMAL</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
-                  <name>INVERT</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>disable output</description>
-                  <name>DISABLE</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>enable output</description>
-                  <name>ENABLE</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>OEOVER</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[9:8]</bitRange>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>drive output from peripheral signal selected by funcsel</description>
-                  <name>NORMAL</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive output from inverse of peripheral signal selected by funcsel</description>
-                  <name>INVERT</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive output low</description>
-                  <name>LOW</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive output high</description>
-                  <name>HIGH</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>OUTOVER</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[4:0]</bitRange>
-              <description>0-31 -&gt; selects pin function according to the gpio table\n
-                31 == NULL</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>xip_sd0</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>sio_32</name>
-                  <value>5</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>null</name>
-                  <value>31</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>FUNCSEL</name>
-            </field>
-          </fields>
-          <name>GPIO_QSPI_SD0_CTRL</name>
-          <resetValue>0x0000001f</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0018</addressOffset>
-          <description>GPIO status</description>
-          <fields>
-            <field>
-              <access>read-only</access>
-              <bitRange>[26:26]</bitRange>
-              <description>interrupt to processors, after override is applied</description>
-              <name>IRQTOPROC</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[24:24]</bitRange>
-              <description>interrupt from pad before override is applied</description>
-              <name>IRQFROMPAD</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[19:19]</bitRange>
-              <description>input signal to peripheral, after override is applied</description>
-              <name>INTOPERI</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[17:17]</bitRange>
-              <description>input signal from pad, before override is applied</description>
-              <name>INFROMPAD</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[13:13]</bitRange>
-              <description>output enable to pad after register override is applied</description>
-              <name>OETOPAD</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[12:12]</bitRange>
-              <description>output enable from selected peripheral, before register override is applied</description>
-              <name>OEFROMPERI</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[9:9]</bitRange>
-              <description>output signal to pad after register override is applied</description>
-              <name>OUTTOPAD</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[8:8]</bitRange>
-              <description>output signal from selected peripheral, before register override is applied</description>
-              <name>OUTFROMPERI</name>
-            </field>
-          </fields>
-          <name>GPIO_QSPI_SD1_STATUS</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x001c</addressOffset>
-          <description>GPIO control including function select and overrides.</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[29:28]</bitRange>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>don't invert the interrupt</description>
-                  <name>NORMAL</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>invert the interrupt</description>
-                  <name>INVERT</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive interrupt low</description>
-                  <name>LOW</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive interrupt high</description>
-                  <name>HIGH</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>IRQOVER</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[17:16]</bitRange>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>don't invert the peri input</description>
-                  <name>NORMAL</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>invert the peri input</description>
-                  <name>INVERT</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive peri input low</description>
-                  <name>LOW</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive peri input high</description>
-                  <name>HIGH</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>INOVER</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[13:12]</bitRange>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>drive output enable from peripheral signal selected by funcsel</description>
-                  <name>NORMAL</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
-                  <name>INVERT</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>disable output</description>
-                  <name>DISABLE</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>enable output</description>
-                  <name>ENABLE</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>OEOVER</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[9:8]</bitRange>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>drive output from peripheral signal selected by funcsel</description>
-                  <name>NORMAL</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive output from inverse of peripheral signal selected by funcsel</description>
-                  <name>INVERT</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive output low</description>
-                  <name>LOW</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive output high</description>
-                  <name>HIGH</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>OUTOVER</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[4:0]</bitRange>
-              <description>0-31 -&gt; selects pin function according to the gpio table\n
-                31 == NULL</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>xip_sd1</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>sio_33</name>
-                  <value>5</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>null</name>
-                  <value>31</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>FUNCSEL</name>
-            </field>
-          </fields>
-          <name>GPIO_QSPI_SD1_CTRL</name>
-          <resetValue>0x0000001f</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0020</addressOffset>
-          <description>GPIO status</description>
-          <fields>
-            <field>
-              <access>read-only</access>
-              <bitRange>[26:26]</bitRange>
-              <description>interrupt to processors, after override is applied</description>
-              <name>IRQTOPROC</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[24:24]</bitRange>
-              <description>interrupt from pad before override is applied</description>
-              <name>IRQFROMPAD</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[19:19]</bitRange>
-              <description>input signal to peripheral, after override is applied</description>
-              <name>INTOPERI</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[17:17]</bitRange>
-              <description>input signal from pad, before override is applied</description>
-              <name>INFROMPAD</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[13:13]</bitRange>
-              <description>output enable to pad after register override is applied</description>
-              <name>OETOPAD</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[12:12]</bitRange>
-              <description>output enable from selected peripheral, before register override is applied</description>
-              <name>OEFROMPERI</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[9:9]</bitRange>
-              <description>output signal to pad after register override is applied</description>
-              <name>OUTTOPAD</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[8:8]</bitRange>
-              <description>output signal from selected peripheral, before register override is applied</description>
-              <name>OUTFROMPERI</name>
-            </field>
-          </fields>
-          <name>GPIO_QSPI_SD2_STATUS</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0024</addressOffset>
-          <description>GPIO control including function select and overrides.</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[29:28]</bitRange>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>don't invert the interrupt</description>
-                  <name>NORMAL</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>invert the interrupt</description>
-                  <name>INVERT</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive interrupt low</description>
-                  <name>LOW</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive interrupt high</description>
-                  <name>HIGH</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>IRQOVER</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[17:16]</bitRange>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>don't invert the peri input</description>
-                  <name>NORMAL</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>invert the peri input</description>
-                  <name>INVERT</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive peri input low</description>
-                  <name>LOW</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive peri input high</description>
-                  <name>HIGH</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>INOVER</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[13:12]</bitRange>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>drive output enable from peripheral signal selected by funcsel</description>
-                  <name>NORMAL</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
-                  <name>INVERT</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>disable output</description>
-                  <name>DISABLE</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>enable output</description>
-                  <name>ENABLE</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>OEOVER</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[9:8]</bitRange>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>drive output from peripheral signal selected by funcsel</description>
-                  <name>NORMAL</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive output from inverse of peripheral signal selected by funcsel</description>
-                  <name>INVERT</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive output low</description>
-                  <name>LOW</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive output high</description>
-                  <name>HIGH</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>OUTOVER</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[4:0]</bitRange>
-              <description>0-31 -&gt; selects pin function according to the gpio table\n
-                31 == NULL</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>xip_sd2</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>sio_34</name>
-                  <value>5</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>null</name>
-                  <value>31</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>FUNCSEL</name>
-            </field>
-          </fields>
-          <name>GPIO_QSPI_SD2_CTRL</name>
-          <resetValue>0x0000001f</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0028</addressOffset>
-          <description>GPIO status</description>
-          <fields>
-            <field>
-              <access>read-only</access>
-              <bitRange>[26:26]</bitRange>
-              <description>interrupt to processors, after override is applied</description>
-              <name>IRQTOPROC</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[24:24]</bitRange>
-              <description>interrupt from pad before override is applied</description>
-              <name>IRQFROMPAD</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[19:19]</bitRange>
-              <description>input signal to peripheral, after override is applied</description>
-              <name>INTOPERI</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[17:17]</bitRange>
-              <description>input signal from pad, before override is applied</description>
-              <name>INFROMPAD</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[13:13]</bitRange>
-              <description>output enable to pad after register override is applied</description>
-              <name>OETOPAD</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[12:12]</bitRange>
-              <description>output enable from selected peripheral, before register override is applied</description>
-              <name>OEFROMPERI</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[9:9]</bitRange>
-              <description>output signal to pad after register override is applied</description>
-              <name>OUTTOPAD</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[8:8]</bitRange>
-              <description>output signal from selected peripheral, before register override is applied</description>
-              <name>OUTFROMPERI</name>
-            </field>
-          </fields>
-          <name>GPIO_QSPI_SD3_STATUS</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x002c</addressOffset>
-          <description>GPIO control including function select and overrides.</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[29:28]</bitRange>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>don't invert the interrupt</description>
-                  <name>NORMAL</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>invert the interrupt</description>
-                  <name>INVERT</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive interrupt low</description>
-                  <name>LOW</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive interrupt high</description>
-                  <name>HIGH</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>IRQOVER</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[17:16]</bitRange>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>don't invert the peri input</description>
-                  <name>NORMAL</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>invert the peri input</description>
-                  <name>INVERT</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive peri input low</description>
-                  <name>LOW</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive peri input high</description>
-                  <name>HIGH</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>INOVER</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[13:12]</bitRange>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>drive output enable from peripheral signal selected by funcsel</description>
-                  <name>NORMAL</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
-                  <name>INVERT</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>disable output</description>
-                  <name>DISABLE</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>enable output</description>
-                  <name>ENABLE</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>OEOVER</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[9:8]</bitRange>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>drive output from peripheral signal selected by funcsel</description>
-                  <name>NORMAL</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive output from inverse of peripheral signal selected by funcsel</description>
-                  <name>INVERT</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive output low</description>
-                  <name>LOW</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>drive output high</description>
-                  <name>HIGH</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>OUTOVER</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[4:0]</bitRange>
-              <description>0-31 -&gt; selects pin function according to the gpio table\n
-                31 == NULL</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>xip_sd3</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>sio_35</name>
-                  <value>5</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>null</name>
-                  <value>31</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>FUNCSEL</name>
-            </field>
-          </fields>
-          <name>GPIO_QSPI_SD3_CTRL</name>
-          <resetValue>0x0000001f</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0030</addressOffset>
-          <description>Raw Interrupts</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[23:23]</bitRange>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>GPIO_QSPI_SD3_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[22:22]</bitRange>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>GPIO_QSPI_SD3_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[21:21]</bitRange>
-              <name>GPIO_QSPI_SD3_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[20:20]</bitRange>
-              <name>GPIO_QSPI_SD3_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[19:19]</bitRange>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>GPIO_QSPI_SD2_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[18:18]</bitRange>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>GPIO_QSPI_SD2_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[17:17]</bitRange>
-              <name>GPIO_QSPI_SD2_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[16:16]</bitRange>
-              <name>GPIO_QSPI_SD2_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[15:15]</bitRange>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>GPIO_QSPI_SD1_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[14:14]</bitRange>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>GPIO_QSPI_SD1_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[13:13]</bitRange>
-              <name>GPIO_QSPI_SD1_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[12:12]</bitRange>
-              <name>GPIO_QSPI_SD1_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[11:11]</bitRange>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>GPIO_QSPI_SD0_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[10:10]</bitRange>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>GPIO_QSPI_SD0_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[9:9]</bitRange>
-              <name>GPIO_QSPI_SD0_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[8:8]</bitRange>
-              <name>GPIO_QSPI_SD0_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[7:7]</bitRange>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>GPIO_QSPI_SS_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[6:6]</bitRange>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>GPIO_QSPI_SS_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[5:5]</bitRange>
-              <name>GPIO_QSPI_SS_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[4:4]</bitRange>
-              <name>GPIO_QSPI_SS_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[3:3]</bitRange>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>GPIO_QSPI_SCLK_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[2:2]</bitRange>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>GPIO_QSPI_SCLK_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[1:1]</bitRange>
-              <name>GPIO_QSPI_SCLK_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[0:0]</bitRange>
-              <name>GPIO_QSPI_SCLK_LEVEL_LOW</name>
-            </field>
-          </fields>
-          <name>INTR</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0034</addressOffset>
-          <description>Interrupt Enable for proc0</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[23:23]</bitRange>
-              <name>GPIO_QSPI_SD3_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[22:22]</bitRange>
-              <name>GPIO_QSPI_SD3_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[21:21]</bitRange>
-              <name>GPIO_QSPI_SD3_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[20:20]</bitRange>
-              <name>GPIO_QSPI_SD3_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[19:19]</bitRange>
-              <name>GPIO_QSPI_SD2_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[18:18]</bitRange>
-              <name>GPIO_QSPI_SD2_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[17:17]</bitRange>
-              <name>GPIO_QSPI_SD2_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[16:16]</bitRange>
-              <name>GPIO_QSPI_SD2_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[15:15]</bitRange>
-              <name>GPIO_QSPI_SD1_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[14:14]</bitRange>
-              <name>GPIO_QSPI_SD1_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[13:13]</bitRange>
-              <name>GPIO_QSPI_SD1_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[12:12]</bitRange>
-              <name>GPIO_QSPI_SD1_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[11:11]</bitRange>
-              <name>GPIO_QSPI_SD0_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[10:10]</bitRange>
-              <name>GPIO_QSPI_SD0_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[9:9]</bitRange>
-              <name>GPIO_QSPI_SD0_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[8:8]</bitRange>
-              <name>GPIO_QSPI_SD0_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[7:7]</bitRange>
-              <name>GPIO_QSPI_SS_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[6:6]</bitRange>
-              <name>GPIO_QSPI_SS_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[5:5]</bitRange>
-              <name>GPIO_QSPI_SS_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[4:4]</bitRange>
-              <name>GPIO_QSPI_SS_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[3:3]</bitRange>
-              <name>GPIO_QSPI_SCLK_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[2:2]</bitRange>
-              <name>GPIO_QSPI_SCLK_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[1:1]</bitRange>
-              <name>GPIO_QSPI_SCLK_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[0:0]</bitRange>
-              <name>GPIO_QSPI_SCLK_LEVEL_LOW</name>
-            </field>
-          </fields>
-          <name>PROC0_INTE</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0038</addressOffset>
-          <description>Interrupt Force for proc0</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[23:23]</bitRange>
-              <name>GPIO_QSPI_SD3_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[22:22]</bitRange>
-              <name>GPIO_QSPI_SD3_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[21:21]</bitRange>
-              <name>GPIO_QSPI_SD3_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[20:20]</bitRange>
-              <name>GPIO_QSPI_SD3_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[19:19]</bitRange>
-              <name>GPIO_QSPI_SD2_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[18:18]</bitRange>
-              <name>GPIO_QSPI_SD2_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[17:17]</bitRange>
-              <name>GPIO_QSPI_SD2_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[16:16]</bitRange>
-              <name>GPIO_QSPI_SD2_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[15:15]</bitRange>
-              <name>GPIO_QSPI_SD1_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[14:14]</bitRange>
-              <name>GPIO_QSPI_SD1_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[13:13]</bitRange>
-              <name>GPIO_QSPI_SD1_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[12:12]</bitRange>
-              <name>GPIO_QSPI_SD1_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[11:11]</bitRange>
-              <name>GPIO_QSPI_SD0_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[10:10]</bitRange>
-              <name>GPIO_QSPI_SD0_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[9:9]</bitRange>
-              <name>GPIO_QSPI_SD0_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[8:8]</bitRange>
-              <name>GPIO_QSPI_SD0_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[7:7]</bitRange>
-              <name>GPIO_QSPI_SS_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[6:6]</bitRange>
-              <name>GPIO_QSPI_SS_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[5:5]</bitRange>
-              <name>GPIO_QSPI_SS_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[4:4]</bitRange>
-              <name>GPIO_QSPI_SS_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[3:3]</bitRange>
-              <name>GPIO_QSPI_SCLK_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[2:2]</bitRange>
-              <name>GPIO_QSPI_SCLK_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[1:1]</bitRange>
-              <name>GPIO_QSPI_SCLK_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[0:0]</bitRange>
-              <name>GPIO_QSPI_SCLK_LEVEL_LOW</name>
-            </field>
-          </fields>
-          <name>PROC0_INTF</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x003c</addressOffset>
-          <description>Interrupt status after masking &amp; forcing for proc0</description>
-          <fields>
-            <field>
-              <access>read-only</access>
-              <bitRange>[23:23]</bitRange>
-              <name>GPIO_QSPI_SD3_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[22:22]</bitRange>
-              <name>GPIO_QSPI_SD3_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[21:21]</bitRange>
-              <name>GPIO_QSPI_SD3_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[20:20]</bitRange>
-              <name>GPIO_QSPI_SD3_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[19:19]</bitRange>
-              <name>GPIO_QSPI_SD2_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[18:18]</bitRange>
-              <name>GPIO_QSPI_SD2_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[17:17]</bitRange>
-              <name>GPIO_QSPI_SD2_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[16:16]</bitRange>
-              <name>GPIO_QSPI_SD2_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[15:15]</bitRange>
-              <name>GPIO_QSPI_SD1_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[14:14]</bitRange>
-              <name>GPIO_QSPI_SD1_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[13:13]</bitRange>
-              <name>GPIO_QSPI_SD1_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[12:12]</bitRange>
-              <name>GPIO_QSPI_SD1_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[11:11]</bitRange>
-              <name>GPIO_QSPI_SD0_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[10:10]</bitRange>
-              <name>GPIO_QSPI_SD0_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[9:9]</bitRange>
-              <name>GPIO_QSPI_SD0_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[8:8]</bitRange>
-              <name>GPIO_QSPI_SD0_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[7:7]</bitRange>
-              <name>GPIO_QSPI_SS_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[6:6]</bitRange>
-              <name>GPIO_QSPI_SS_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[5:5]</bitRange>
-              <name>GPIO_QSPI_SS_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[4:4]</bitRange>
-              <name>GPIO_QSPI_SS_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[3:3]</bitRange>
-              <name>GPIO_QSPI_SCLK_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[2:2]</bitRange>
-              <name>GPIO_QSPI_SCLK_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[1:1]</bitRange>
-              <name>GPIO_QSPI_SCLK_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[0:0]</bitRange>
-              <name>GPIO_QSPI_SCLK_LEVEL_LOW</name>
-            </field>
-          </fields>
-          <name>PROC0_INTS</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0040</addressOffset>
-          <description>Interrupt Enable for proc1</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[23:23]</bitRange>
-              <name>GPIO_QSPI_SD3_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[22:22]</bitRange>
-              <name>GPIO_QSPI_SD3_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[21:21]</bitRange>
-              <name>GPIO_QSPI_SD3_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[20:20]</bitRange>
-              <name>GPIO_QSPI_SD3_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[19:19]</bitRange>
-              <name>GPIO_QSPI_SD2_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[18:18]</bitRange>
-              <name>GPIO_QSPI_SD2_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[17:17]</bitRange>
-              <name>GPIO_QSPI_SD2_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[16:16]</bitRange>
-              <name>GPIO_QSPI_SD2_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[15:15]</bitRange>
-              <name>GPIO_QSPI_SD1_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[14:14]</bitRange>
-              <name>GPIO_QSPI_SD1_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[13:13]</bitRange>
-              <name>GPIO_QSPI_SD1_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[12:12]</bitRange>
-              <name>GPIO_QSPI_SD1_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[11:11]</bitRange>
-              <name>GPIO_QSPI_SD0_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[10:10]</bitRange>
-              <name>GPIO_QSPI_SD0_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[9:9]</bitRange>
-              <name>GPIO_QSPI_SD0_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[8:8]</bitRange>
-              <name>GPIO_QSPI_SD0_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[7:7]</bitRange>
-              <name>GPIO_QSPI_SS_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[6:6]</bitRange>
-              <name>GPIO_QSPI_SS_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[5:5]</bitRange>
-              <name>GPIO_QSPI_SS_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[4:4]</bitRange>
-              <name>GPIO_QSPI_SS_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[3:3]</bitRange>
-              <name>GPIO_QSPI_SCLK_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[2:2]</bitRange>
-              <name>GPIO_QSPI_SCLK_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[1:1]</bitRange>
-              <name>GPIO_QSPI_SCLK_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[0:0]</bitRange>
-              <name>GPIO_QSPI_SCLK_LEVEL_LOW</name>
-            </field>
-          </fields>
-          <name>PROC1_INTE</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0044</addressOffset>
-          <description>Interrupt Force for proc1</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[23:23]</bitRange>
-              <name>GPIO_QSPI_SD3_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[22:22]</bitRange>
-              <name>GPIO_QSPI_SD3_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[21:21]</bitRange>
-              <name>GPIO_QSPI_SD3_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[20:20]</bitRange>
-              <name>GPIO_QSPI_SD3_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[19:19]</bitRange>
-              <name>GPIO_QSPI_SD2_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[18:18]</bitRange>
-              <name>GPIO_QSPI_SD2_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[17:17]</bitRange>
-              <name>GPIO_QSPI_SD2_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[16:16]</bitRange>
-              <name>GPIO_QSPI_SD2_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[15:15]</bitRange>
-              <name>GPIO_QSPI_SD1_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[14:14]</bitRange>
-              <name>GPIO_QSPI_SD1_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[13:13]</bitRange>
-              <name>GPIO_QSPI_SD1_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[12:12]</bitRange>
-              <name>GPIO_QSPI_SD1_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[11:11]</bitRange>
-              <name>GPIO_QSPI_SD0_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[10:10]</bitRange>
-              <name>GPIO_QSPI_SD0_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[9:9]</bitRange>
-              <name>GPIO_QSPI_SD0_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[8:8]</bitRange>
-              <name>GPIO_QSPI_SD0_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[7:7]</bitRange>
-              <name>GPIO_QSPI_SS_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[6:6]</bitRange>
-              <name>GPIO_QSPI_SS_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[5:5]</bitRange>
-              <name>GPIO_QSPI_SS_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[4:4]</bitRange>
-              <name>GPIO_QSPI_SS_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[3:3]</bitRange>
-              <name>GPIO_QSPI_SCLK_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[2:2]</bitRange>
-              <name>GPIO_QSPI_SCLK_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[1:1]</bitRange>
-              <name>GPIO_QSPI_SCLK_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[0:0]</bitRange>
-              <name>GPIO_QSPI_SCLK_LEVEL_LOW</name>
-            </field>
-          </fields>
-          <name>PROC1_INTF</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0048</addressOffset>
-          <description>Interrupt status after masking &amp; forcing for proc1</description>
-          <fields>
-            <field>
-              <access>read-only</access>
-              <bitRange>[23:23]</bitRange>
-              <name>GPIO_QSPI_SD3_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[22:22]</bitRange>
-              <name>GPIO_QSPI_SD3_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[21:21]</bitRange>
-              <name>GPIO_QSPI_SD3_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[20:20]</bitRange>
-              <name>GPIO_QSPI_SD3_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[19:19]</bitRange>
-              <name>GPIO_QSPI_SD2_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[18:18]</bitRange>
-              <name>GPIO_QSPI_SD2_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[17:17]</bitRange>
-              <name>GPIO_QSPI_SD2_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[16:16]</bitRange>
-              <name>GPIO_QSPI_SD2_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[15:15]</bitRange>
-              <name>GPIO_QSPI_SD1_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[14:14]</bitRange>
-              <name>GPIO_QSPI_SD1_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[13:13]</bitRange>
-              <name>GPIO_QSPI_SD1_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[12:12]</bitRange>
-              <name>GPIO_QSPI_SD1_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[11:11]</bitRange>
-              <name>GPIO_QSPI_SD0_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[10:10]</bitRange>
-              <name>GPIO_QSPI_SD0_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[9:9]</bitRange>
-              <name>GPIO_QSPI_SD0_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[8:8]</bitRange>
-              <name>GPIO_QSPI_SD0_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[7:7]</bitRange>
-              <name>GPIO_QSPI_SS_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[6:6]</bitRange>
-              <name>GPIO_QSPI_SS_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[5:5]</bitRange>
-              <name>GPIO_QSPI_SS_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[4:4]</bitRange>
-              <name>GPIO_QSPI_SS_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[3:3]</bitRange>
-              <name>GPIO_QSPI_SCLK_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[2:2]</bitRange>
-              <name>GPIO_QSPI_SCLK_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[1:1]</bitRange>
-              <name>GPIO_QSPI_SCLK_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[0:0]</bitRange>
-              <name>GPIO_QSPI_SCLK_LEVEL_LOW</name>
-            </field>
-          </fields>
-          <name>PROC1_INTS</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x004c</addressOffset>
-          <description>Interrupt Enable for dormant_wake</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[23:23]</bitRange>
-              <name>GPIO_QSPI_SD3_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[22:22]</bitRange>
-              <name>GPIO_QSPI_SD3_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[21:21]</bitRange>
-              <name>GPIO_QSPI_SD3_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[20:20]</bitRange>
-              <name>GPIO_QSPI_SD3_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[19:19]</bitRange>
-              <name>GPIO_QSPI_SD2_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[18:18]</bitRange>
-              <name>GPIO_QSPI_SD2_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[17:17]</bitRange>
-              <name>GPIO_QSPI_SD2_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[16:16]</bitRange>
-              <name>GPIO_QSPI_SD2_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[15:15]</bitRange>
-              <name>GPIO_QSPI_SD1_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[14:14]</bitRange>
-              <name>GPIO_QSPI_SD1_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[13:13]</bitRange>
-              <name>GPIO_QSPI_SD1_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[12:12]</bitRange>
-              <name>GPIO_QSPI_SD1_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[11:11]</bitRange>
-              <name>GPIO_QSPI_SD0_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[10:10]</bitRange>
-              <name>GPIO_QSPI_SD0_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[9:9]</bitRange>
-              <name>GPIO_QSPI_SD0_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[8:8]</bitRange>
-              <name>GPIO_QSPI_SD0_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[7:7]</bitRange>
-              <name>GPIO_QSPI_SS_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[6:6]</bitRange>
-              <name>GPIO_QSPI_SS_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[5:5]</bitRange>
-              <name>GPIO_QSPI_SS_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[4:4]</bitRange>
-              <name>GPIO_QSPI_SS_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[3:3]</bitRange>
-              <name>GPIO_QSPI_SCLK_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[2:2]</bitRange>
-              <name>GPIO_QSPI_SCLK_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[1:1]</bitRange>
-              <name>GPIO_QSPI_SCLK_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[0:0]</bitRange>
-              <name>GPIO_QSPI_SCLK_LEVEL_LOW</name>
-            </field>
-          </fields>
-          <name>DORMANT_WAKE_INTE</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0050</addressOffset>
-          <description>Interrupt Force for dormant_wake</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[23:23]</bitRange>
-              <name>GPIO_QSPI_SD3_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[22:22]</bitRange>
-              <name>GPIO_QSPI_SD3_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[21:21]</bitRange>
-              <name>GPIO_QSPI_SD3_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[20:20]</bitRange>
-              <name>GPIO_QSPI_SD3_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[19:19]</bitRange>
-              <name>GPIO_QSPI_SD2_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[18:18]</bitRange>
-              <name>GPIO_QSPI_SD2_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[17:17]</bitRange>
-              <name>GPIO_QSPI_SD2_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[16:16]</bitRange>
-              <name>GPIO_QSPI_SD2_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[15:15]</bitRange>
-              <name>GPIO_QSPI_SD1_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[14:14]</bitRange>
-              <name>GPIO_QSPI_SD1_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[13:13]</bitRange>
-              <name>GPIO_QSPI_SD1_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[12:12]</bitRange>
-              <name>GPIO_QSPI_SD1_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[11:11]</bitRange>
-              <name>GPIO_QSPI_SD0_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[10:10]</bitRange>
-              <name>GPIO_QSPI_SD0_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[9:9]</bitRange>
-              <name>GPIO_QSPI_SD0_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[8:8]</bitRange>
-              <name>GPIO_QSPI_SD0_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[7:7]</bitRange>
-              <name>GPIO_QSPI_SS_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[6:6]</bitRange>
-              <name>GPIO_QSPI_SS_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[5:5]</bitRange>
-              <name>GPIO_QSPI_SS_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[4:4]</bitRange>
-              <name>GPIO_QSPI_SS_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[3:3]</bitRange>
-              <name>GPIO_QSPI_SCLK_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[2:2]</bitRange>
-              <name>GPIO_QSPI_SCLK_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[1:1]</bitRange>
-              <name>GPIO_QSPI_SCLK_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[0:0]</bitRange>
-              <name>GPIO_QSPI_SCLK_LEVEL_LOW</name>
-            </field>
-          </fields>
-          <name>DORMANT_WAKE_INTF</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0054</addressOffset>
-          <description>Interrupt status after masking &amp; forcing for dormant_wake</description>
-          <fields>
-            <field>
-              <access>read-only</access>
-              <bitRange>[23:23]</bitRange>
-              <name>GPIO_QSPI_SD3_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[22:22]</bitRange>
-              <name>GPIO_QSPI_SD3_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[21:21]</bitRange>
-              <name>GPIO_QSPI_SD3_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[20:20]</bitRange>
-              <name>GPIO_QSPI_SD3_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[19:19]</bitRange>
-              <name>GPIO_QSPI_SD2_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[18:18]</bitRange>
-              <name>GPIO_QSPI_SD2_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[17:17]</bitRange>
-              <name>GPIO_QSPI_SD2_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[16:16]</bitRange>
-              <name>GPIO_QSPI_SD2_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[15:15]</bitRange>
-              <name>GPIO_QSPI_SD1_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[14:14]</bitRange>
-              <name>GPIO_QSPI_SD1_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[13:13]</bitRange>
-              <name>GPIO_QSPI_SD1_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[12:12]</bitRange>
-              <name>GPIO_QSPI_SD1_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[11:11]</bitRange>
-              <name>GPIO_QSPI_SD0_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[10:10]</bitRange>
-              <name>GPIO_QSPI_SD0_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[9:9]</bitRange>
-              <name>GPIO_QSPI_SD0_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[8:8]</bitRange>
-              <name>GPIO_QSPI_SD0_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[7:7]</bitRange>
-              <name>GPIO_QSPI_SS_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[6:6]</bitRange>
-              <name>GPIO_QSPI_SS_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[5:5]</bitRange>
-              <name>GPIO_QSPI_SS_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[4:4]</bitRange>
-              <name>GPIO_QSPI_SS_LEVEL_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[3:3]</bitRange>
-              <name>GPIO_QSPI_SCLK_EDGE_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[2:2]</bitRange>
-              <name>GPIO_QSPI_SCLK_EDGE_LOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[1:1]</bitRange>
-              <name>GPIO_QSPI_SCLK_LEVEL_HIGH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[0:0]</bitRange>
-              <name>GPIO_QSPI_SCLK_LEVEL_LOW</name>
-            </field>
-          </fields>
-          <name>DORMANT_WAKE_INTS</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-      </registers>
-      <size>32</size>
-      <version>1</version>
-    </peripheral>
-    <peripheral>
-      <addressBlock>
-        <offset>0</offset>
-        <size>0x1000</size>
-        <usage>registers</usage>
-      </addressBlock>
-      <baseAddress>0x4001c000</baseAddress>
-      <name>PADS_BANK0</name>
-      <registers>
-        <register>
-          <addressOffset>0x0000</addressOffset>
-          <description>Voltage select. Per bank control</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[0:0]</bitRange>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>Set voltage to 3.3V (DVDD &gt;= 2V5)</description>
-                  <name>3v3</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>Set voltage to 1.8V (DVDD &lt;= 1V8)</description>
-                  <name>1v8</name>
-                  <value>1</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>VOLTAGE_SELECT</name>
-            </field>
-          </fields>
-          <name>VOLTAGE_SELECT</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0004</addressOffset>
-          <description>Pad control register</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[7:7]</bitRange>
-              <description>Output disable. Has priority over output enable from peripherals</description>
-              <name>OD</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[6:6]</bitRange>
-              <description>Input enable</description>
-              <name>IE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[5:4]</bitRange>
-              <description>Drive strength.</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>2mA</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>4mA</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>8mA</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>12mA</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>DRIVE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[3:3]</bitRange>
-              <description>Pull up enable</description>
-              <name>PUE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[2:2]</bitRange>
-              <description>Pull down enable</description>
-              <name>PDE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[1:1]</bitRange>
-              <description>Enable schmitt trigger</description>
-              <name>SCHMITT</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[0:0]</bitRange>
-              <description>Slew rate control. 1 = Fast, 0 = Slow</description>
-              <name>SLEWFAST</name>
-            </field>
-          </fields>
-          <name>GPIO0</name>
-          <resetValue>0x00000056</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0008</addressOffset>
-          <description>Pad control register</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[7:7]</bitRange>
-              <description>Output disable. Has priority over output enable from peripherals</description>
-              <name>OD</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[6:6]</bitRange>
-              <description>Input enable</description>
-              <name>IE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[5:4]</bitRange>
-              <description>Drive strength.</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>2mA</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>4mA</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>8mA</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>12mA</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>DRIVE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[3:3]</bitRange>
-              <description>Pull up enable</description>
-              <name>PUE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[2:2]</bitRange>
-              <description>Pull down enable</description>
-              <name>PDE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[1:1]</bitRange>
-              <description>Enable schmitt trigger</description>
-              <name>SCHMITT</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[0:0]</bitRange>
-              <description>Slew rate control. 1 = Fast, 0 = Slow</description>
-              <name>SLEWFAST</name>
-            </field>
-          </fields>
-          <name>GPIO1</name>
-          <resetValue>0x00000056</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x000c</addressOffset>
-          <description>Pad control register</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[7:7]</bitRange>
-              <description>Output disable. Has priority over output enable from peripherals</description>
-              <name>OD</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[6:6]</bitRange>
-              <description>Input enable</description>
-              <name>IE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[5:4]</bitRange>
-              <description>Drive strength.</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>2mA</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>4mA</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>8mA</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>12mA</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>DRIVE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[3:3]</bitRange>
-              <description>Pull up enable</description>
-              <name>PUE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[2:2]</bitRange>
-              <description>Pull down enable</description>
-              <name>PDE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[1:1]</bitRange>
-              <description>Enable schmitt trigger</description>
-              <name>SCHMITT</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[0:0]</bitRange>
-              <description>Slew rate control. 1 = Fast, 0 = Slow</description>
-              <name>SLEWFAST</name>
-            </field>
-          </fields>
-          <name>GPIO2</name>
-          <resetValue>0x00000056</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0010</addressOffset>
-          <description>Pad control register</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[7:7]</bitRange>
-              <description>Output disable. Has priority over output enable from peripherals</description>
-              <name>OD</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[6:6]</bitRange>
-              <description>Input enable</description>
-              <name>IE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[5:4]</bitRange>
-              <description>Drive strength.</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>2mA</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>4mA</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>8mA</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>12mA</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>DRIVE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[3:3]</bitRange>
-              <description>Pull up enable</description>
-              <name>PUE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[2:2]</bitRange>
-              <description>Pull down enable</description>
-              <name>PDE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[1:1]</bitRange>
-              <description>Enable schmitt trigger</description>
-              <name>SCHMITT</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[0:0]</bitRange>
-              <description>Slew rate control. 1 = Fast, 0 = Slow</description>
-              <name>SLEWFAST</name>
-            </field>
-          </fields>
-          <name>GPIO3</name>
-          <resetValue>0x00000056</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0014</addressOffset>
-          <description>Pad control register</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[7:7]</bitRange>
-              <description>Output disable. Has priority over output enable from peripherals</description>
-              <name>OD</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[6:6]</bitRange>
-              <description>Input enable</description>
-              <name>IE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[5:4]</bitRange>
-              <description>Drive strength.</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>2mA</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>4mA</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>8mA</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>12mA</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>DRIVE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[3:3]</bitRange>
-              <description>Pull up enable</description>
-              <name>PUE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[2:2]</bitRange>
-              <description>Pull down enable</description>
-              <name>PDE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[1:1]</bitRange>
-              <description>Enable schmitt trigger</description>
-              <name>SCHMITT</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[0:0]</bitRange>
-              <description>Slew rate control. 1 = Fast, 0 = Slow</description>
-              <name>SLEWFAST</name>
-            </field>
-          </fields>
-          <name>GPIO4</name>
-          <resetValue>0x00000056</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0018</addressOffset>
-          <description>Pad control register</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[7:7]</bitRange>
-              <description>Output disable. Has priority over output enable from peripherals</description>
-              <name>OD</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[6:6]</bitRange>
-              <description>Input enable</description>
-              <name>IE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[5:4]</bitRange>
-              <description>Drive strength.</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>2mA</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>4mA</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>8mA</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>12mA</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>DRIVE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[3:3]</bitRange>
-              <description>Pull up enable</description>
-              <name>PUE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[2:2]</bitRange>
-              <description>Pull down enable</description>
-              <name>PDE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[1:1]</bitRange>
-              <description>Enable schmitt trigger</description>
-              <name>SCHMITT</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[0:0]</bitRange>
-              <description>Slew rate control. 1 = Fast, 0 = Slow</description>
-              <name>SLEWFAST</name>
-            </field>
-          </fields>
-          <name>GPIO5</name>
-          <resetValue>0x00000056</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x001c</addressOffset>
-          <description>Pad control register</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[7:7]</bitRange>
-              <description>Output disable. Has priority over output enable from peripherals</description>
-              <name>OD</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[6:6]</bitRange>
-              <description>Input enable</description>
-              <name>IE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[5:4]</bitRange>
-              <description>Drive strength.</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>2mA</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>4mA</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>8mA</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>12mA</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>DRIVE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[3:3]</bitRange>
-              <description>Pull up enable</description>
-              <name>PUE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[2:2]</bitRange>
-              <description>Pull down enable</description>
-              <name>PDE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[1:1]</bitRange>
-              <description>Enable schmitt trigger</description>
-              <name>SCHMITT</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[0:0]</bitRange>
-              <description>Slew rate control. 1 = Fast, 0 = Slow</description>
-              <name>SLEWFAST</name>
-            </field>
-          </fields>
-          <name>GPIO6</name>
-          <resetValue>0x00000056</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0020</addressOffset>
-          <description>Pad control register</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[7:7]</bitRange>
-              <description>Output disable. Has priority over output enable from peripherals</description>
-              <name>OD</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[6:6]</bitRange>
-              <description>Input enable</description>
-              <name>IE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[5:4]</bitRange>
-              <description>Drive strength.</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>2mA</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>4mA</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>8mA</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>12mA</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>DRIVE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[3:3]</bitRange>
-              <description>Pull up enable</description>
-              <name>PUE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[2:2]</bitRange>
-              <description>Pull down enable</description>
-              <name>PDE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[1:1]</bitRange>
-              <description>Enable schmitt trigger</description>
-              <name>SCHMITT</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[0:0]</bitRange>
-              <description>Slew rate control. 1 = Fast, 0 = Slow</description>
-              <name>SLEWFAST</name>
-            </field>
-          </fields>
-          <name>GPIO7</name>
-          <resetValue>0x00000056</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0024</addressOffset>
-          <description>Pad control register</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[7:7]</bitRange>
-              <description>Output disable. Has priority over output enable from peripherals</description>
-              <name>OD</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[6:6]</bitRange>
-              <description>Input enable</description>
-              <name>IE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[5:4]</bitRange>
-              <description>Drive strength.</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>2mA</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>4mA</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>8mA</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>12mA</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>DRIVE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[3:3]</bitRange>
-              <description>Pull up enable</description>
-              <name>PUE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[2:2]</bitRange>
-              <description>Pull down enable</description>
-              <name>PDE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[1:1]</bitRange>
-              <description>Enable schmitt trigger</description>
-              <name>SCHMITT</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[0:0]</bitRange>
-              <description>Slew rate control. 1 = Fast, 0 = Slow</description>
-              <name>SLEWFAST</name>
-            </field>
-          </fields>
-          <name>GPIO8</name>
-          <resetValue>0x00000056</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0028</addressOffset>
-          <description>Pad control register</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[7:7]</bitRange>
-              <description>Output disable. Has priority over output enable from peripherals</description>
-              <name>OD</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[6:6]</bitRange>
-              <description>Input enable</description>
-              <name>IE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[5:4]</bitRange>
-              <description>Drive strength.</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>2mA</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>4mA</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>8mA</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>12mA</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>DRIVE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[3:3]</bitRange>
-              <description>Pull up enable</description>
-              <name>PUE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[2:2]</bitRange>
-              <description>Pull down enable</description>
-              <name>PDE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[1:1]</bitRange>
-              <description>Enable schmitt trigger</description>
-              <name>SCHMITT</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[0:0]</bitRange>
-              <description>Slew rate control. 1 = Fast, 0 = Slow</description>
-              <name>SLEWFAST</name>
-            </field>
-          </fields>
-          <name>GPIO9</name>
-          <resetValue>0x00000056</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x002c</addressOffset>
-          <description>Pad control register</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[7:7]</bitRange>
-              <description>Output disable. Has priority over output enable from peripherals</description>
-              <name>OD</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[6:6]</bitRange>
-              <description>Input enable</description>
-              <name>IE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[5:4]</bitRange>
-              <description>Drive strength.</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>2mA</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>4mA</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>8mA</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>12mA</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>DRIVE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[3:3]</bitRange>
-              <description>Pull up enable</description>
-              <name>PUE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[2:2]</bitRange>
-              <description>Pull down enable</description>
-              <name>PDE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[1:1]</bitRange>
-              <description>Enable schmitt trigger</description>
-              <name>SCHMITT</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[0:0]</bitRange>
-              <description>Slew rate control. 1 = Fast, 0 = Slow</description>
-              <name>SLEWFAST</name>
-            </field>
-          </fields>
-          <name>GPIO10</name>
-          <resetValue>0x00000056</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0030</addressOffset>
-          <description>Pad control register</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[7:7]</bitRange>
-              <description>Output disable. Has priority over output enable from peripherals</description>
-              <name>OD</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[6:6]</bitRange>
-              <description>Input enable</description>
-              <name>IE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[5:4]</bitRange>
-              <description>Drive strength.</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>2mA</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>4mA</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>8mA</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>12mA</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>DRIVE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[3:3]</bitRange>
-              <description>Pull up enable</description>
-              <name>PUE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[2:2]</bitRange>
-              <description>Pull down enable</description>
-              <name>PDE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[1:1]</bitRange>
-              <description>Enable schmitt trigger</description>
-              <name>SCHMITT</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[0:0]</bitRange>
-              <description>Slew rate control. 1 = Fast, 0 = Slow</description>
-              <name>SLEWFAST</name>
-            </field>
-          </fields>
-          <name>GPIO11</name>
-          <resetValue>0x00000056</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0034</addressOffset>
-          <description>Pad control register</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[7:7]</bitRange>
-              <description>Output disable. Has priority over output enable from peripherals</description>
-              <name>OD</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[6:6]</bitRange>
-              <description>Input enable</description>
-              <name>IE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[5:4]</bitRange>
-              <description>Drive strength.</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>2mA</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>4mA</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>8mA</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>12mA</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>DRIVE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[3:3]</bitRange>
-              <description>Pull up enable</description>
-              <name>PUE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[2:2]</bitRange>
-              <description>Pull down enable</description>
-              <name>PDE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[1:1]</bitRange>
-              <description>Enable schmitt trigger</description>
-              <name>SCHMITT</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[0:0]</bitRange>
-              <description>Slew rate control. 1 = Fast, 0 = Slow</description>
-              <name>SLEWFAST</name>
-            </field>
-          </fields>
-          <name>GPIO12</name>
-          <resetValue>0x00000056</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0038</addressOffset>
-          <description>Pad control register</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[7:7]</bitRange>
-              <description>Output disable. Has priority over output enable from peripherals</description>
-              <name>OD</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[6:6]</bitRange>
-              <description>Input enable</description>
-              <name>IE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[5:4]</bitRange>
-              <description>Drive strength.</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>2mA</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>4mA</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>8mA</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>12mA</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>DRIVE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[3:3]</bitRange>
-              <description>Pull up enable</description>
-              <name>PUE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[2:2]</bitRange>
-              <description>Pull down enable</description>
-              <name>PDE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[1:1]</bitRange>
-              <description>Enable schmitt trigger</description>
-              <name>SCHMITT</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[0:0]</bitRange>
-              <description>Slew rate control. 1 = Fast, 0 = Slow</description>
-              <name>SLEWFAST</name>
-            </field>
-          </fields>
-          <name>GPIO13</name>
-          <resetValue>0x00000056</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x003c</addressOffset>
-          <description>Pad control register</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[7:7]</bitRange>
-              <description>Output disable. Has priority over output enable from peripherals</description>
-              <name>OD</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[6:6]</bitRange>
-              <description>Input enable</description>
-              <name>IE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[5:4]</bitRange>
-              <description>Drive strength.</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>2mA</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>4mA</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>8mA</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>12mA</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>DRIVE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[3:3]</bitRange>
-              <description>Pull up enable</description>
-              <name>PUE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[2:2]</bitRange>
-              <description>Pull down enable</description>
-              <name>PDE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[1:1]</bitRange>
-              <description>Enable schmitt trigger</description>
-              <name>SCHMITT</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[0:0]</bitRange>
-              <description>Slew rate control. 1 = Fast, 0 = Slow</description>
-              <name>SLEWFAST</name>
-            </field>
-          </fields>
-          <name>GPIO14</name>
-          <resetValue>0x00000056</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0040</addressOffset>
-          <description>Pad control register</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[7:7]</bitRange>
-              <description>Output disable. Has priority over output enable from peripherals</description>
-              <name>OD</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[6:6]</bitRange>
-              <description>Input enable</description>
-              <name>IE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[5:4]</bitRange>
-              <description>Drive strength.</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>2mA</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>4mA</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>8mA</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>12mA</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>DRIVE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[3:3]</bitRange>
-              <description>Pull up enable</description>
-              <name>PUE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[2:2]</bitRange>
-              <description>Pull down enable</description>
-              <name>PDE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[1:1]</bitRange>
-              <description>Enable schmitt trigger</description>
-              <name>SCHMITT</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[0:0]</bitRange>
-              <description>Slew rate control. 1 = Fast, 0 = Slow</description>
-              <name>SLEWFAST</name>
-            </field>
-          </fields>
-          <name>GPIO15</name>
-          <resetValue>0x00000056</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0044</addressOffset>
-          <description>Pad control register</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[7:7]</bitRange>
-              <description>Output disable. Has priority over output enable from peripherals</description>
-              <name>OD</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[6:6]</bitRange>
-              <description>Input enable</description>
-              <name>IE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[5:4]</bitRange>
-              <description>Drive strength.</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>2mA</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>4mA</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>8mA</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>12mA</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>DRIVE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[3:3]</bitRange>
-              <description>Pull up enable</description>
-              <name>PUE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[2:2]</bitRange>
-              <description>Pull down enable</description>
-              <name>PDE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[1:1]</bitRange>
-              <description>Enable schmitt trigger</description>
-              <name>SCHMITT</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[0:0]</bitRange>
-              <description>Slew rate control. 1 = Fast, 0 = Slow</description>
-              <name>SLEWFAST</name>
-            </field>
-          </fields>
-          <name>GPIO16</name>
-          <resetValue>0x00000056</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0048</addressOffset>
-          <description>Pad control register</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[7:7]</bitRange>
-              <description>Output disable. Has priority over output enable from peripherals</description>
-              <name>OD</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[6:6]</bitRange>
-              <description>Input enable</description>
-              <name>IE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[5:4]</bitRange>
-              <description>Drive strength.</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>2mA</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>4mA</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>8mA</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>12mA</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>DRIVE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[3:3]</bitRange>
-              <description>Pull up enable</description>
-              <name>PUE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[2:2]</bitRange>
-              <description>Pull down enable</description>
-              <name>PDE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[1:1]</bitRange>
-              <description>Enable schmitt trigger</description>
-              <name>SCHMITT</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[0:0]</bitRange>
-              <description>Slew rate control. 1 = Fast, 0 = Slow</description>
-              <name>SLEWFAST</name>
-            </field>
-          </fields>
-          <name>GPIO17</name>
-          <resetValue>0x00000056</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x004c</addressOffset>
-          <description>Pad control register</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[7:7]</bitRange>
-              <description>Output disable. Has priority over output enable from peripherals</description>
-              <name>OD</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[6:6]</bitRange>
-              <description>Input enable</description>
-              <name>IE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[5:4]</bitRange>
-              <description>Drive strength.</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>2mA</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>4mA</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>8mA</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>12mA</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>DRIVE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[3:3]</bitRange>
-              <description>Pull up enable</description>
-              <name>PUE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[2:2]</bitRange>
-              <description>Pull down enable</description>
-              <name>PDE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[1:1]</bitRange>
-              <description>Enable schmitt trigger</description>
-              <name>SCHMITT</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[0:0]</bitRange>
-              <description>Slew rate control. 1 = Fast, 0 = Slow</description>
-              <name>SLEWFAST</name>
-            </field>
-          </fields>
-          <name>GPIO18</name>
-          <resetValue>0x00000056</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0050</addressOffset>
-          <description>Pad control register</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[7:7]</bitRange>
-              <description>Output disable. Has priority over output enable from peripherals</description>
-              <name>OD</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[6:6]</bitRange>
-              <description>Input enable</description>
-              <name>IE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[5:4]</bitRange>
-              <description>Drive strength.</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>2mA</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>4mA</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>8mA</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>12mA</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>DRIVE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[3:3]</bitRange>
-              <description>Pull up enable</description>
-              <name>PUE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[2:2]</bitRange>
-              <description>Pull down enable</description>
-              <name>PDE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[1:1]</bitRange>
-              <description>Enable schmitt trigger</description>
-              <name>SCHMITT</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[0:0]</bitRange>
-              <description>Slew rate control. 1 = Fast, 0 = Slow</description>
-              <name>SLEWFAST</name>
-            </field>
-          </fields>
-          <name>GPIO19</name>
-          <resetValue>0x00000056</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0054</addressOffset>
-          <description>Pad control register</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[7:7]</bitRange>
-              <description>Output disable. Has priority over output enable from peripherals</description>
-              <name>OD</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[6:6]</bitRange>
-              <description>Input enable</description>
-              <name>IE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[5:4]</bitRange>
-              <description>Drive strength.</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>2mA</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>4mA</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>8mA</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>12mA</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>DRIVE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[3:3]</bitRange>
-              <description>Pull up enable</description>
-              <name>PUE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[2:2]</bitRange>
-              <description>Pull down enable</description>
-              <name>PDE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[1:1]</bitRange>
-              <description>Enable schmitt trigger</description>
-              <name>SCHMITT</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[0:0]</bitRange>
-              <description>Slew rate control. 1 = Fast, 0 = Slow</description>
-              <name>SLEWFAST</name>
-            </field>
-          </fields>
-          <name>GPIO20</name>
-          <resetValue>0x00000056</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0058</addressOffset>
-          <description>Pad control register</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[7:7]</bitRange>
-              <description>Output disable. Has priority over output enable from peripherals</description>
-              <name>OD</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[6:6]</bitRange>
-              <description>Input enable</description>
-              <name>IE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[5:4]</bitRange>
-              <description>Drive strength.</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>2mA</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>4mA</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>8mA</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>12mA</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>DRIVE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[3:3]</bitRange>
-              <description>Pull up enable</description>
-              <name>PUE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[2:2]</bitRange>
-              <description>Pull down enable</description>
-              <name>PDE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[1:1]</bitRange>
-              <description>Enable schmitt trigger</description>
-              <name>SCHMITT</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[0:0]</bitRange>
-              <description>Slew rate control. 1 = Fast, 0 = Slow</description>
-              <name>SLEWFAST</name>
-            </field>
-          </fields>
-          <name>GPIO21</name>
-          <resetValue>0x00000056</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x005c</addressOffset>
-          <description>Pad control register</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[7:7]</bitRange>
-              <description>Output disable. Has priority over output enable from peripherals</description>
-              <name>OD</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[6:6]</bitRange>
-              <description>Input enable</description>
-              <name>IE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[5:4]</bitRange>
-              <description>Drive strength.</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>2mA</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>4mA</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>8mA</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>12mA</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>DRIVE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[3:3]</bitRange>
-              <description>Pull up enable</description>
-              <name>PUE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[2:2]</bitRange>
-              <description>Pull down enable</description>
-              <name>PDE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[1:1]</bitRange>
-              <description>Enable schmitt trigger</description>
-              <name>SCHMITT</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[0:0]</bitRange>
-              <description>Slew rate control. 1 = Fast, 0 = Slow</description>
-              <name>SLEWFAST</name>
-            </field>
-          </fields>
-          <name>GPIO22</name>
-          <resetValue>0x00000056</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0060</addressOffset>
-          <description>Pad control register</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[7:7]</bitRange>
-              <description>Output disable. Has priority over output enable from peripherals</description>
-              <name>OD</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[6:6]</bitRange>
-              <description>Input enable</description>
-              <name>IE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[5:4]</bitRange>
-              <description>Drive strength.</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>2mA</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>4mA</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>8mA</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>12mA</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>DRIVE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[3:3]</bitRange>
-              <description>Pull up enable</description>
-              <name>PUE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[2:2]</bitRange>
-              <description>Pull down enable</description>
-              <name>PDE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[1:1]</bitRange>
-              <description>Enable schmitt trigger</description>
-              <name>SCHMITT</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[0:0]</bitRange>
-              <description>Slew rate control. 1 = Fast, 0 = Slow</description>
-              <name>SLEWFAST</name>
-            </field>
-          </fields>
-          <name>GPIO23</name>
-          <resetValue>0x00000056</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0064</addressOffset>
-          <description>Pad control register</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[7:7]</bitRange>
-              <description>Output disable. Has priority over output enable from peripherals</description>
-              <name>OD</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[6:6]</bitRange>
-              <description>Input enable</description>
-              <name>IE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[5:4]</bitRange>
-              <description>Drive strength.</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>2mA</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>4mA</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>8mA</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>12mA</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>DRIVE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[3:3]</bitRange>
-              <description>Pull up enable</description>
-              <name>PUE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[2:2]</bitRange>
-              <description>Pull down enable</description>
-              <name>PDE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[1:1]</bitRange>
-              <description>Enable schmitt trigger</description>
-              <name>SCHMITT</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[0:0]</bitRange>
-              <description>Slew rate control. 1 = Fast, 0 = Slow</description>
-              <name>SLEWFAST</name>
-            </field>
-          </fields>
-          <name>GPIO24</name>
-          <resetValue>0x00000056</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0068</addressOffset>
-          <description>Pad control register</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[7:7]</bitRange>
-              <description>Output disable. Has priority over output enable from peripherals</description>
-              <name>OD</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[6:6]</bitRange>
-              <description>Input enable</description>
-              <name>IE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[5:4]</bitRange>
-              <description>Drive strength.</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>2mA</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>4mA</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>8mA</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>12mA</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>DRIVE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[3:3]</bitRange>
-              <description>Pull up enable</description>
-              <name>PUE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[2:2]</bitRange>
-              <description>Pull down enable</description>
-              <name>PDE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[1:1]</bitRange>
-              <description>Enable schmitt trigger</description>
-              <name>SCHMITT</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[0:0]</bitRange>
-              <description>Slew rate control. 1 = Fast, 0 = Slow</description>
-              <name>SLEWFAST</name>
-            </field>
-          </fields>
-          <name>GPIO25</name>
-          <resetValue>0x00000056</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x006c</addressOffset>
-          <description>Pad control register</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[7:7]</bitRange>
-              <description>Output disable. Has priority over output enable from peripherals</description>
-              <name>OD</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[6:6]</bitRange>
-              <description>Input enable</description>
-              <name>IE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[5:4]</bitRange>
-              <description>Drive strength.</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>2mA</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>4mA</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>8mA</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>12mA</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>DRIVE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[3:3]</bitRange>
-              <description>Pull up enable</description>
-              <name>PUE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[2:2]</bitRange>
-              <description>Pull down enable</description>
-              <name>PDE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[1:1]</bitRange>
-              <description>Enable schmitt trigger</description>
-              <name>SCHMITT</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[0:0]</bitRange>
-              <description>Slew rate control. 1 = Fast, 0 = Slow</description>
-              <name>SLEWFAST</name>
-            </field>
-          </fields>
-          <name>GPIO26</name>
-          <resetValue>0x00000056</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0070</addressOffset>
-          <description>Pad control register</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[7:7]</bitRange>
-              <description>Output disable. Has priority over output enable from peripherals</description>
-              <name>OD</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[6:6]</bitRange>
-              <description>Input enable</description>
-              <name>IE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[5:4]</bitRange>
-              <description>Drive strength.</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>2mA</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>4mA</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>8mA</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>12mA</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>DRIVE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[3:3]</bitRange>
-              <description>Pull up enable</description>
-              <name>PUE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[2:2]</bitRange>
-              <description>Pull down enable</description>
-              <name>PDE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[1:1]</bitRange>
-              <description>Enable schmitt trigger</description>
-              <name>SCHMITT</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[0:0]</bitRange>
-              <description>Slew rate control. 1 = Fast, 0 = Slow</description>
-              <name>SLEWFAST</name>
-            </field>
-          </fields>
-          <name>GPIO27</name>
-          <resetValue>0x00000056</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0074</addressOffset>
-          <description>Pad control register</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[7:7]</bitRange>
-              <description>Output disable. Has priority over output enable from peripherals</description>
-              <name>OD</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[6:6]</bitRange>
-              <description>Input enable</description>
-              <name>IE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[5:4]</bitRange>
-              <description>Drive strength.</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>2mA</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>4mA</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>8mA</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>12mA</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>DRIVE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[3:3]</bitRange>
-              <description>Pull up enable</description>
-              <name>PUE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[2:2]</bitRange>
-              <description>Pull down enable</description>
-              <name>PDE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[1:1]</bitRange>
-              <description>Enable schmitt trigger</description>
-              <name>SCHMITT</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[0:0]</bitRange>
-              <description>Slew rate control. 1 = Fast, 0 = Slow</description>
-              <name>SLEWFAST</name>
-            </field>
-          </fields>
-          <name>GPIO28</name>
-          <resetValue>0x00000056</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0078</addressOffset>
-          <description>Pad control register</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[7:7]</bitRange>
-              <description>Output disable. Has priority over output enable from peripherals</description>
-              <name>OD</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[6:6]</bitRange>
-              <description>Input enable</description>
-              <name>IE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[5:4]</bitRange>
-              <description>Drive strength.</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>2mA</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>4mA</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>8mA</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>12mA</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>DRIVE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[3:3]</bitRange>
-              <description>Pull up enable</description>
-              <name>PUE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[2:2]</bitRange>
-              <description>Pull down enable</description>
-              <name>PDE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[1:1]</bitRange>
-              <description>Enable schmitt trigger</description>
-              <name>SCHMITT</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[0:0]</bitRange>
-              <description>Slew rate control. 1 = Fast, 0 = Slow</description>
-              <name>SLEWFAST</name>
-            </field>
-          </fields>
-          <name>GPIO29</name>
-          <resetValue>0x00000056</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x007c</addressOffset>
-          <description>Pad control register</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[7:7]</bitRange>
-              <description>Output disable. Has priority over output enable from peripherals</description>
-              <name>OD</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[6:6]</bitRange>
-              <description>Input enable</description>
-              <name>IE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[5:4]</bitRange>
-              <description>Drive strength.</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>2mA</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>4mA</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>8mA</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>12mA</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>DRIVE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[3:3]</bitRange>
-              <description>Pull up enable</description>
-              <name>PUE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[2:2]</bitRange>
-              <description>Pull down enable</description>
-              <name>PDE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[1:1]</bitRange>
-              <description>Enable schmitt trigger</description>
-              <name>SCHMITT</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[0:0]</bitRange>
-              <description>Slew rate control. 1 = Fast, 0 = Slow</description>
-              <name>SLEWFAST</name>
-            </field>
-          </fields>
-          <name>SWCLK</name>
-          <resetValue>0x000000da</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0080</addressOffset>
-          <description>Pad control register</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[7:7]</bitRange>
-              <description>Output disable. Has priority over output enable from peripherals</description>
-              <name>OD</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[6:6]</bitRange>
-              <description>Input enable</description>
-              <name>IE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[5:4]</bitRange>
-              <description>Drive strength.</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>2mA</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>4mA</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>8mA</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>12mA</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>DRIVE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[3:3]</bitRange>
-              <description>Pull up enable</description>
-              <name>PUE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[2:2]</bitRange>
-              <description>Pull down enable</description>
-              <name>PDE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[1:1]</bitRange>
-              <description>Enable schmitt trigger</description>
-              <name>SCHMITT</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[0:0]</bitRange>
-              <description>Slew rate control. 1 = Fast, 0 = Slow</description>
-              <name>SLEWFAST</name>
-            </field>
-          </fields>
-          <name>SWD</name>
-          <resetValue>0x0000005a</resetValue>
-        </register>
-      </registers>
-      <size>32</size>
-      <version>1</version>
-    </peripheral>
-    <peripheral>
-      <addressBlock>
-        <offset>0</offset>
-        <size>0x1000</size>
-        <usage>registers</usage>
-      </addressBlock>
-      <baseAddress>0x40020000</baseAddress>
-      <name>PADS_QSPI</name>
-      <registers>
-        <register>
-          <addressOffset>0x0000</addressOffset>
-          <description>Voltage select. Per bank control</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[0:0]</bitRange>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>Set voltage to 3.3V (DVDD &gt;= 2V5)</description>
-                  <name>3v3</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>Set voltage to 1.8V (DVDD &lt;= 1V8)</description>
-                  <name>1v8</name>
-                  <value>1</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>VOLTAGE_SELECT</name>
-            </field>
-          </fields>
-          <name>VOLTAGE_SELECT</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0004</addressOffset>
-          <description>Pad control register</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[7:7]</bitRange>
-              <description>Output disable. Has priority over output enable from peripherals</description>
-              <name>OD</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[6:6]</bitRange>
-              <description>Input enable</description>
-              <name>IE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[5:4]</bitRange>
-              <description>Drive strength.</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>2mA</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>4mA</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>8mA</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>12mA</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>DRIVE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[3:3]</bitRange>
-              <description>Pull up enable</description>
-              <name>PUE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[2:2]</bitRange>
-              <description>Pull down enable</description>
-              <name>PDE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[1:1]</bitRange>
-              <description>Enable schmitt trigger</description>
-              <name>SCHMITT</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[0:0]</bitRange>
-              <description>Slew rate control. 1 = Fast, 0 = Slow</description>
-              <name>SLEWFAST</name>
-            </field>
-          </fields>
-          <name>GPIO_QSPI_SCLK</name>
-          <resetValue>0x00000056</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0008</addressOffset>
-          <description>Pad control register</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[7:7]</bitRange>
-              <description>Output disable. Has priority over output enable from peripherals</description>
-              <name>OD</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[6:6]</bitRange>
-              <description>Input enable</description>
-              <name>IE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[5:4]</bitRange>
-              <description>Drive strength.</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>2mA</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>4mA</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>8mA</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>12mA</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>DRIVE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[3:3]</bitRange>
-              <description>Pull up enable</description>
-              <name>PUE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[2:2]</bitRange>
-              <description>Pull down enable</description>
-              <name>PDE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[1:1]</bitRange>
-              <description>Enable schmitt trigger</description>
-              <name>SCHMITT</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[0:0]</bitRange>
-              <description>Slew rate control. 1 = Fast, 0 = Slow</description>
-              <name>SLEWFAST</name>
-            </field>
-          </fields>
-          <name>GPIO_QSPI_SD0</name>
-          <resetValue>0x00000052</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x000c</addressOffset>
-          <description>Pad control register</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[7:7]</bitRange>
-              <description>Output disable. Has priority over output enable from peripherals</description>
-              <name>OD</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[6:6]</bitRange>
-              <description>Input enable</description>
-              <name>IE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[5:4]</bitRange>
-              <description>Drive strength.</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>2mA</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>4mA</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>8mA</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>12mA</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>DRIVE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[3:3]</bitRange>
-              <description>Pull up enable</description>
-              <name>PUE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[2:2]</bitRange>
-              <description>Pull down enable</description>
-              <name>PDE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[1:1]</bitRange>
-              <description>Enable schmitt trigger</description>
-              <name>SCHMITT</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[0:0]</bitRange>
-              <description>Slew rate control. 1 = Fast, 0 = Slow</description>
-              <name>SLEWFAST</name>
-            </field>
-          </fields>
-          <name>GPIO_QSPI_SD1</name>
-          <resetValue>0x00000052</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0010</addressOffset>
-          <description>Pad control register</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[7:7]</bitRange>
-              <description>Output disable. Has priority over output enable from peripherals</description>
-              <name>OD</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[6:6]</bitRange>
-              <description>Input enable</description>
-              <name>IE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[5:4]</bitRange>
-              <description>Drive strength.</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>2mA</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>4mA</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>8mA</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>12mA</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>DRIVE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[3:3]</bitRange>
-              <description>Pull up enable</description>
-              <name>PUE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[2:2]</bitRange>
-              <description>Pull down enable</description>
-              <name>PDE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[1:1]</bitRange>
-              <description>Enable schmitt trigger</description>
-              <name>SCHMITT</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[0:0]</bitRange>
-              <description>Slew rate control. 1 = Fast, 0 = Slow</description>
-              <name>SLEWFAST</name>
-            </field>
-          </fields>
-          <name>GPIO_QSPI_SD2</name>
-          <resetValue>0x00000052</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0014</addressOffset>
-          <description>Pad control register</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[7:7]</bitRange>
-              <description>Output disable. Has priority over output enable from peripherals</description>
-              <name>OD</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[6:6]</bitRange>
-              <description>Input enable</description>
-              <name>IE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[5:4]</bitRange>
-              <description>Drive strength.</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>2mA</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>4mA</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>8mA</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>12mA</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>DRIVE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[3:3]</bitRange>
-              <description>Pull up enable</description>
-              <name>PUE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[2:2]</bitRange>
-              <description>Pull down enable</description>
-              <name>PDE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[1:1]</bitRange>
-              <description>Enable schmitt trigger</description>
-              <name>SCHMITT</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[0:0]</bitRange>
-              <description>Slew rate control. 1 = Fast, 0 = Slow</description>
-              <name>SLEWFAST</name>
-            </field>
-          </fields>
-          <name>GPIO_QSPI_SD3</name>
-          <resetValue>0x00000052</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0018</addressOffset>
-          <description>Pad control register</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[7:7]</bitRange>
-              <description>Output disable. Has priority over output enable from peripherals</description>
-              <name>OD</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[6:6]</bitRange>
-              <description>Input enable</description>
-              <name>IE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[5:4]</bitRange>
-              <description>Drive strength.</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>2mA</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>4mA</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>8mA</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>12mA</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>DRIVE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[3:3]</bitRange>
-              <description>Pull up enable</description>
-              <name>PUE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[2:2]</bitRange>
-              <description>Pull down enable</description>
-              <name>PDE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[1:1]</bitRange>
-              <description>Enable schmitt trigger</description>
-              <name>SCHMITT</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[0:0]</bitRange>
-              <description>Slew rate control. 1 = Fast, 0 = Slow</description>
-              <name>SLEWFAST</name>
-            </field>
-          </fields>
-          <name>GPIO_QSPI_SS</name>
-          <resetValue>0x0000005a</resetValue>
-        </register>
-      </registers>
-      <size>32</size>
-      <version>1</version>
-    </peripheral>
-    <peripheral>
-      <addressBlock>
-        <offset>0</offset>
-        <size>0x1000</size>
-        <usage>registers</usage>
-      </addressBlock>
-      <baseAddress>0x40024000</baseAddress>
-      <description>Controls the crystal oscillator</description>
-      <name>XOSC</name>
-      <registers>
-        <register>
-          <addressOffset>0x0000</addressOffset>
-          <description>Crystal Oscillator Control</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[23:12]</bitRange>
-              <description>On power-up this field is initialised to DISABLE and the chip runs from the ROSC.\n
-                If the chip has subsequently been programmed to run from the XOSC then setting this field to DISABLE may lock-up the chip. If this is a concern then run the clk_ref from the ROSC and enable the clk_sys RESUS feature.\n
-                The 12-bit code is intended to give some protection against accidental writes. An invalid setting will enable the oscillator.</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>DISABLE</name>
-                  <value>3358</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>ENABLE</name>
-                  <value>4011</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>ENABLE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[11:0]</bitRange>
-              <description>Frequency range. This resets to 0xAA0 and cannot be changed.</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>1_15MHZ</name>
-                  <value>2720</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>RESERVED_1</name>
-                  <value>2721</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>RESERVED_2</name>
-                  <value>2722</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>RESERVED_3</name>
-                  <value>2723</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>FREQ_RANGE</name>
-            </field>
-          </fields>
-          <name>CTRL</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0004</addressOffset>
-          <description>Crystal Oscillator Status</description>
-          <fields>
-            <field>
-              <access>read-only</access>
-              <bitRange>[31:31]</bitRange>
-              <description>Oscillator is running and stable</description>
-              <name>STABLE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[24:24]</bitRange>
-              <description>An invalid value has been written to CTRL_ENABLE or CTRL_FREQ_RANGE or DORMANT</description>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>BADWRITE</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[12:12]</bitRange>
-              <description>Oscillator is enabled but not necessarily running and stable, resets to 0</description>
-              <name>ENABLED</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[1:0]</bitRange>
-              <description>The current frequency range setting, always reads 0</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>1_15MHZ</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>RESERVED_1</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>RESERVED_2</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>RESERVED_3</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>FREQ_RANGE</name>
-            </field>
-          </fields>
-          <name>STATUS</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x0008</addressOffset>
-          <description>Crystal Oscillator pause control\n
-            This is used to save power by pausing the XOSC\n
-            On power-up this field is initialised to WAKE\n
-            An invalid write will also select WAKE\n
-            WARNING: stop the PLLs before selecting dormant mode\n
-            WARNING: setup the irq before selecting dormant mode</description>
-          <name>DORMANT</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x000c</addressOffset>
-          <description>Controls the startup delay</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[20:20]</bitRange>
-              <description>Multiplies the startup_delay by 4. This is of little value to the user given that the delay can be programmed directly.</description>
-              <name>X4</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[13:0]</bitRange>
-              <description>in multiples of 256*xtal_period. The reset value of 0xc4 corresponds to approx 50 000 cycles.</description>
-              <name>DELAY</name>
-            </field>
-          </fields>
-          <name>STARTUP</name>
-          <resetValue>0x000000c4</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x001c</addressOffset>
-          <description>A down counter running at the xosc frequency which counts to zero and stops.\n
-            To start the counter write a non-zero value.\n
-            Can be used for short software pauses when setting up time sensitive hardware.</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[7:0]</bitRange>
-              <name>COUNT</name>
-            </field>
-          </fields>
-          <name>COUNT</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-      </registers>
-      <size>32</size>
-      <version>1</version>
-    </peripheral>
-    <peripheral>
-      <addressBlock>
-        <offset>0</offset>
-        <size>0x1000</size>
-        <usage>registers</usage>
-      </addressBlock>
-      <baseAddress>0x40028000</baseAddress>
-      <name>PLL_SYS</name>
-      <registers>
-        <register>
-          <addressOffset>0x0000</addressOffset>
-          <description>Control and Status\n
-            GENERAL CONSTRAINTS:\n
-            Reference clock frequency min=5MHz, max=800MHz\n
-            Feedback divider min=16, max=320\n
-            VCO frequency min=750MHz, max=1600MHz</description>
-          <fields>
-            <field>
-              <access>read-only</access>
-              <bitRange>[31:31]</bitRange>
-              <description>PLL is locked</description>
-              <name>LOCK</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[8:8]</bitRange>
-              <description>Passes the reference clock to the output instead of the divided VCO. The VCO continues to run so the user can switch between the reference clock and the divided VCO but the output will glitch when doing so.</description>
-              <name>BYPASS</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[5:0]</bitRange>
-              <description>Divides the PLL input reference clock.\n
-                Behaviour is undefined for div=0.\n
-                PLL output will be unpredictable during refdiv changes, wait for lock=1 before using it.</description>
-              <name>REFDIV</name>
-            </field>
-          </fields>
-          <name>CS</name>
-          <resetValue>0x00000001</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0004</addressOffset>
-          <description>Controls the PLL power modes.</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[5:5]</bitRange>
-              <description>PLL VCO powerdown\n
-                To save power set high when PLL output not required or bypass=1.</description>
-              <name>VCOPD</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[3:3]</bitRange>
-              <description>PLL post divider powerdown\n
-                To save power set high when PLL output not required or bypass=1.</description>
-              <name>POSTDIVPD</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[2:2]</bitRange>
-              <description>PLL DSM powerdown\n
-                Nothing is achieved by setting this low.</description>
-              <name>DSMPD</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[0:0]</bitRange>
-              <description>PLL powerdown\n
-                To save power set high when PLL output not required.</description>
-              <name>PD</name>
-            </field>
-          </fields>
-          <name>PWR</name>
-          <resetValue>0x0000002d</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0008</addressOffset>
-          <description>Feedback divisor\n
-            (note: this PLL does not support fractional division)</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[11:0]</bitRange>
-              <description>see ctrl reg description for constraints</description>
-              <name>FBDIV_INT</name>
-            </field>
-          </fields>
-          <name>FBDIV_INT</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x000c</addressOffset>
-          <description>Controls the PLL post dividers for the primary output\n
-            (note: this PLL does not have a secondary output)\n
-            the primary output is driven from VCO divided by postdiv1*postdiv2</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[18:16]</bitRange>
-              <description>divide by 1-7</description>
-              <name>POSTDIV1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[14:12]</bitRange>
-              <description>divide by 1-7</description>
-              <name>POSTDIV2</name>
-            </field>
-          </fields>
-          <name>PRIM</name>
-          <resetValue>0x00077000</resetValue>
-        </register>
-      </registers>
-      <size>32</size>
-      <version>1</version>
-    </peripheral>
-    <peripheral derivedFrom="PLL_SYS">
-      <baseAddress>0x4002c000</baseAddress>
-      <name>PLL_USB</name>
-    </peripheral>
-    <peripheral>
-      <addressBlock>
-        <offset>0</offset>
-        <size>0x1000</size>
-        <usage>registers</usage>
-      </addressBlock>
-      <baseAddress>0x40030000</baseAddress>
-      <description>Register block for busfabric control signals and performance counters</description>
-      <name>BUSCTRL</name>
-      <registers>
-        <register>
-          <addressOffset>0x0000</addressOffset>
-          <description>Set the priority of each master for bus arbitration.</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[12:12]</bitRange>
-              <description>0 - low priority, 1 - high priority</description>
-              <name>DMA_W</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[8:8]</bitRange>
-              <description>0 - low priority, 1 - high priority</description>
-              <name>DMA_R</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[4:4]</bitRange>
-              <description>0 - low priority, 1 - high priority</description>
-              <name>PROC1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[0:0]</bitRange>
-              <description>0 - low priority, 1 - high priority</description>
-              <name>PROC0</name>
-            </field>
-          </fields>
-          <name>BUS_PRIORITY</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0004</addressOffset>
-          <description>Bus priority acknowledge</description>
-          <fields>
-            <field>
-              <access>read-only</access>
-              <bitRange>[0:0]</bitRange>
-              <description>Goes to 1 once all arbiters have registered the new global priority levels.\n
-                Arbiters update their local priority when servicing a new nonsequential access.\n
-                In normal circumstances this will happen almost immediately.</description>
-              <name>BUS_PRIORITY_ACK</name>
-            </field>
-          </fields>
-          <name>BUS_PRIORITY_ACK</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0008</addressOffset>
-          <description>Bus fabric performance counter 0</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[23:0]</bitRange>
-              <description>Busfabric saturating performance counter 0\n
-                Count some event signal from the busfabric arbiters.\n
-                Write any value to clear. Select an event to count using PERFSEL0</description>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>PERFCTR0</name>
-            </field>
-          </fields>
-          <name>PERFCTR0</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x000c</addressOffset>
-          <description>Bus fabric performance event select for PERFCTR0</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[4:0]</bitRange>
-              <description>Select an event for PERFCTR0. Count either contested accesses, or all accesses, on a downstream port of the main crossbar.</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>apb_contested</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>apb</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>fastperi_contested</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>fastperi</name>
-                  <value>3</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>sram5_contested</name>
-                  <value>4</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>sram5</name>
-                  <value>5</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>sram4_contested</name>
-                  <value>6</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>sram4</name>
-                  <value>7</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>sram3_contested</name>
-                  <value>8</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>sram3</name>
-                  <value>9</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>sram2_contested</name>
-                  <value>10</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>sram2</name>
-                  <value>11</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>sram1_contested</name>
-                  <value>12</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>sram1</name>
-                  <value>13</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>sram0_contested</name>
-                  <value>14</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>sram0</name>
-                  <value>15</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>xip_main_contested</name>
-                  <value>16</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>xip_main</name>
-                  <value>17</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>rom_contested</name>
-                  <value>18</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>rom</name>
-                  <value>19</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>PERFSEL0</name>
-            </field>
-          </fields>
-          <name>PERFSEL0</name>
-          <resetValue>0x0000001f</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0010</addressOffset>
-          <description>Bus fabric performance counter 1</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[23:0]</bitRange>
-              <description>Busfabric saturating performance counter 1\n
-                Count some event signal from the busfabric arbiters.\n
-                Write any value to clear. Select an event to count using PERFSEL1</description>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>PERFCTR1</name>
-            </field>
-          </fields>
-          <name>PERFCTR1</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0014</addressOffset>
-          <description>Bus fabric performance event select for PERFCTR1</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[4:0]</bitRange>
-              <description>Select an event for PERFCTR1. Count either contested accesses, or all accesses, on a downstream port of the main crossbar.</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>apb_contested</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>apb</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>fastperi_contested</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>fastperi</name>
-                  <value>3</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>sram5_contested</name>
-                  <value>4</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>sram5</name>
-                  <value>5</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>sram4_contested</name>
-                  <value>6</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>sram4</name>
-                  <value>7</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>sram3_contested</name>
-                  <value>8</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>sram3</name>
-                  <value>9</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>sram2_contested</name>
-                  <value>10</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>sram2</name>
-                  <value>11</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>sram1_contested</name>
-                  <value>12</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>sram1</name>
-                  <value>13</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>sram0_contested</name>
-                  <value>14</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>sram0</name>
-                  <value>15</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>xip_main_contested</name>
-                  <value>16</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>xip_main</name>
-                  <value>17</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>rom_contested</name>
-                  <value>18</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>rom</name>
-                  <value>19</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>PERFSEL1</name>
-            </field>
-          </fields>
-          <name>PERFSEL1</name>
-          <resetValue>0x0000001f</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0018</addressOffset>
-          <description>Bus fabric performance counter 2</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[23:0]</bitRange>
-              <description>Busfabric saturating performance counter 2\n
-                Count some event signal from the busfabric arbiters.\n
-                Write any value to clear. Select an event to count using PERFSEL2</description>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>PERFCTR2</name>
-            </field>
-          </fields>
-          <name>PERFCTR2</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x001c</addressOffset>
-          <description>Bus fabric performance event select for PERFCTR2</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[4:0]</bitRange>
-              <description>Select an event for PERFCTR2. Count either contested accesses, or all accesses, on a downstream port of the main crossbar.</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>apb_contested</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>apb</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>fastperi_contested</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>fastperi</name>
-                  <value>3</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>sram5_contested</name>
-                  <value>4</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>sram5</name>
-                  <value>5</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>sram4_contested</name>
-                  <value>6</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>sram4</name>
-                  <value>7</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>sram3_contested</name>
-                  <value>8</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>sram3</name>
-                  <value>9</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>sram2_contested</name>
-                  <value>10</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>sram2</name>
-                  <value>11</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>sram1_contested</name>
-                  <value>12</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>sram1</name>
-                  <value>13</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>sram0_contested</name>
-                  <value>14</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>sram0</name>
-                  <value>15</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>xip_main_contested</name>
-                  <value>16</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>xip_main</name>
-                  <value>17</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>rom_contested</name>
-                  <value>18</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>rom</name>
-                  <value>19</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>PERFSEL2</name>
-            </field>
-          </fields>
-          <name>PERFSEL2</name>
-          <resetValue>0x0000001f</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0020</addressOffset>
-          <description>Bus fabric performance counter 3</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[23:0]</bitRange>
-              <description>Busfabric saturating performance counter 3\n
-                Count some event signal from the busfabric arbiters.\n
-                Write any value to clear. Select an event to count using PERFSEL3</description>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>PERFCTR3</name>
-            </field>
-          </fields>
-          <name>PERFCTR3</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0024</addressOffset>
-          <description>Bus fabric performance event select for PERFCTR3</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[4:0]</bitRange>
-              <description>Select an event for PERFCTR3. Count either contested accesses, or all accesses, on a downstream port of the main crossbar.</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>apb_contested</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>apb</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>fastperi_contested</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>fastperi</name>
-                  <value>3</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>sram5_contested</name>
-                  <value>4</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>sram5</name>
-                  <value>5</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>sram4_contested</name>
-                  <value>6</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>sram4</name>
-                  <value>7</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>sram3_contested</name>
-                  <value>8</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>sram3</name>
-                  <value>9</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>sram2_contested</name>
-                  <value>10</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>sram2</name>
-                  <value>11</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>sram1_contested</name>
-                  <value>12</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>sram1</name>
-                  <value>13</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>sram0_contested</name>
-                  <value>14</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>sram0</name>
-                  <value>15</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>xip_main_contested</name>
-                  <value>16</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>xip_main</name>
-                  <value>17</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>rom_contested</name>
-                  <value>18</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>rom</name>
-                  <value>19</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>PERFSEL3</name>
-            </field>
-          </fields>
-          <name>PERFSEL3</name>
-          <resetValue>0x0000001f</resetValue>
-        </register>
-      </registers>
-      <size>32</size>
-      <version>1</version>
-    </peripheral>
-    <peripheral>
-      <addressBlock>
-        <offset>0</offset>
-        <size>0x1000</size>
-        <usage>registers</usage>
-      </addressBlock>
-      <baseAddress>0x40034000</baseAddress>
-      <interrupt>
-        <name>UART0_IRQ</name>
-        <value>20</value>
-      </interrupt>
-      <name>UART0</name>
-      <registers>
-        <register>
-          <addressOffset>0x0000</addressOffset>
-          <description>Data Register, UARTDR</description>
-          <fields>
-            <field>
-              <access>read-only</access>
-              <bitRange>[11:11]</bitRange>
-              <description>Overrun error. This bit is set to 1 if data is received and the receive FIFO is already full. This is cleared to 0 once there is an empty space in the FIFO and a new character can be written to it.</description>
-              <name>OE</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[10:10]</bitRange>
-              <description>Break error. This bit is set to 1 if a break condition was detected, indicating that the received data input was held LOW for longer than a full-word transmission time (defined as start, data, parity and stop bits). In FIFO mode, this error is associated with the character at the top of the FIFO. When a break occurs, only one 0 character is loaded into the FIFO. The next character is only enabled after the receive data input goes to a 1 (marking state), and the next valid start bit is received.</description>
-              <name>BE</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[9:9]</bitRange>
-              <description>Parity error. When set to 1, it indicates that the parity of the received data character does not match the parity that the EPS and SPS bits in the Line Control Register, UARTLCR_H. In FIFO mode, this error is associated with the character at the top of the FIFO.</description>
-              <name>PE</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[8:8]</bitRange>
-              <description>Framing error. When set to 1, it indicates that the received character did not have a valid stop bit (a valid stop bit is 1). In FIFO mode, this error is associated with the character at the top of the FIFO.</description>
-              <name>FE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[7:0]</bitRange>
-              <description>Receive (read) data character. Transmit (write) data character.</description>
-              <name>DATA</name>
-            </field>
-          </fields>
-          <name>UARTDR</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0004</addressOffset>
-          <description>Receive Status Register/Error Clear Register, UARTRSR/UARTECR</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[3:3]</bitRange>
-              <description>Overrun error. This bit is set to 1 if data is received and the FIFO is already full. This bit is cleared to 0 by a write to UARTECR. The FIFO contents remain valid because no more data is written when the FIFO is full, only the contents of the shift register are overwritten. The CPU must now read the data, to empty the FIFO.</description>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>OE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[2:2]</bitRange>
-              <description>Break error. This bit is set to 1 if a break condition was detected, indicating that the received data input was held LOW for longer than a full-word transmission time (defined as start, data, parity, and stop bits). This bit is cleared to 0 after a write to UARTECR. In FIFO mode, this error is associated with the character at the top of the FIFO. When a break occurs, only one 0 character is loaded into the FIFO. The next character is only enabled after the receive data input goes to a 1 (marking state) and the next valid start bit is received.</description>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>BE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[1:1]</bitRange>
-              <description>Parity error. When set to 1, it indicates that the parity of the received data character does not match the parity that the EPS and SPS bits in the Line Control Register, UARTLCR_H. This bit is cleared to 0 by a write to UARTECR. In FIFO mode, this error is associated with the character at the top of the FIFO.</description>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>PE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[0:0]</bitRange>
-              <description>Framing error. When set to 1, it indicates that the received character did not have a valid stop bit (a valid stop bit is 1). This bit is cleared to 0 by a write to UARTECR. In FIFO mode, this error is associated with the character at the top of the FIFO.</description>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>FE</name>
-            </field>
-          </fields>
-          <name>UARTRSR</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0018</addressOffset>
-          <description>Flag Register, UARTFR</description>
-          <fields>
-            <field>
-              <access>read-only</access>
-              <bitRange>[8:8]</bitRange>
-              <description>Ring indicator. This bit is the complement of the UART ring indicator, nUARTRI, modem status input. That is, the bit is 1 when nUARTRI is LOW.</description>
-              <name>RI</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[7:7]</bitRange>
-              <description>Transmit FIFO empty. The meaning of this bit depends on the state of the FEN bit in the Line Control Register, UARTLCR_H. If the FIFO is disabled, this bit is set when the transmit holding register is empty. If the FIFO is enabled, the TXFE bit is set when the transmit FIFO is empty. This bit does not indicate if there is data in the transmit shift register.</description>
-              <name>TXFE</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[6:6]</bitRange>
-              <description>Receive FIFO full. The meaning of this bit depends on the state of the FEN bit in the UARTLCR_H Register. If the FIFO is disabled, this bit is set when the receive holding register is full. If the FIFO is enabled, the RXFF bit is set when the receive FIFO is full.</description>
-              <name>RXFF</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[5:5]</bitRange>
-              <description>Transmit FIFO full. The meaning of this bit depends on the state of the FEN bit in the UARTLCR_H Register. If the FIFO is disabled, this bit is set when the transmit holding register is full. If the FIFO is enabled, the TXFF bit is set when the transmit FIFO is full.</description>
-              <name>TXFF</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[4:4]</bitRange>
-              <description>Receive FIFO empty. The meaning of this bit depends on the state of the FEN bit in the UARTLCR_H Register. If the FIFO is disabled, this bit is set when the receive holding register is empty. If the FIFO is enabled, the RXFE bit is set when the receive FIFO is empty.</description>
-              <name>RXFE</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[3:3]</bitRange>
-              <description>UART busy. If this bit is set to 1, the UART is busy transmitting data. This bit remains set until the complete byte, including all the stop bits, has been sent from the shift register. This bit is set as soon as the transmit FIFO becomes non-empty, regardless of whether the UART is enabled or not.</description>
-              <name>BUSY</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[2:2]</bitRange>
-              <description>Data carrier detect. This bit is the complement of the UART data carrier detect, nUARTDCD, modem status input. That is, the bit is 1 when nUARTDCD is LOW.</description>
-              <name>DCD</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[1:1]</bitRange>
-              <description>Data set ready. This bit is the complement of the UART data set ready, nUARTDSR, modem status input. That is, the bit is 1 when nUARTDSR is LOW.</description>
-              <name>DSR</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[0:0]</bitRange>
-              <description>Clear to send. This bit is the complement of the UART clear to send, nUARTCTS, modem status input. That is, the bit is 1 when nUARTCTS is LOW.</description>
-              <name>CTS</name>
-            </field>
-          </fields>
-          <name>UARTFR</name>
-          <resetValue>0x00000090</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0020</addressOffset>
-          <description>IrDA Low-Power Counter Register, UARTILPR</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[7:0]</bitRange>
-              <description>8-bit low-power divisor value. These bits are cleared to 0 at reset.</description>
-              <name>ILPDVSR</name>
-            </field>
-          </fields>
-          <name>UARTILPR</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0024</addressOffset>
-          <description>Integer Baud Rate Register, UARTIBRD</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[15:0]</bitRange>
-              <description>The integer baud rate divisor. These bits are cleared to 0 on reset.</description>
-              <name>BAUD_DIVINT</name>
-            </field>
-          </fields>
-          <name>UARTIBRD</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0028</addressOffset>
-          <description>Fractional Baud Rate Register, UARTFBRD</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[5:0]</bitRange>
-              <description>The fractional baud rate divisor. These bits are cleared to 0 on reset.</description>
-              <name>BAUD_DIVFRAC</name>
-            </field>
-          </fields>
-          <name>UARTFBRD</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x002c</addressOffset>
-          <description>Line Control Register, UARTLCR_H</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[7:7]</bitRange>
-              <description>Stick parity select. 0 = stick parity is disabled 1 = either: * if the EPS bit is 0 then the parity bit is transmitted and checked as a 1 * if the EPS bit is 1 then the parity bit is transmitted and checked as a 0. This bit has no effect when the PEN bit disables parity checking and generation.</description>
-              <name>SPS</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[6:5]</bitRange>
-              <description>Word length. These bits indicate the number of data bits transmitted or received in a frame as follows: b11 = 8 bits b10 = 7 bits b01 = 6 bits b00 = 5 bits.</description>
-              <name>WLEN</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[4:4]</bitRange>
-              <description>Enable FIFOs: 0 = FIFOs are disabled (character mode) that is, the FIFOs become 1-byte-deep holding registers 1 = transmit and receive FIFO buffers are enabled (FIFO mode).</description>
-              <name>FEN</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[3:3]</bitRange>
-              <description>Two stop bits select. If this bit is set to 1, two stop bits are transmitted at the end of the frame. The receive logic does not check for two stop bits being received.</description>
-              <name>STP2</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[2:2]</bitRange>
-              <description>Even parity select. Controls the type of parity the UART uses during transmission and reception: 0 = odd parity. The UART generates or checks for an odd number of 1s in the data and parity bits. 1 = even parity. The UART generates or checks for an even number of 1s in the data and parity bits. This bit has no effect when the PEN bit disables parity checking and generation.</description>
-              <name>EPS</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[1:1]</bitRange>
-              <description>Parity enable: 0 = parity is disabled and no parity bit added to the data frame 1 = parity checking and generation is enabled.</description>
-              <name>PEN</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[0:0]</bitRange>
-              <description>Send break. If this bit is set to 1, a low-level is continually output on the UARTTXD output, after completing transmission of the current character. For the proper execution of the break command, the software must set this bit for at least two complete frames. For normal use, this bit must be cleared to 0.</description>
-              <name>BRK</name>
-            </field>
-          </fields>
-          <name>UARTLCR_H</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0030</addressOffset>
-          <description>Control Register, UARTCR</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[15:15]</bitRange>
-              <description>CTS hardware flow control enable. If this bit is set to 1, CTS hardware flow control is enabled. Data is only transmitted when the nUARTCTS signal is asserted.</description>
-              <name>CTSEN</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[14:14]</bitRange>
-              <description>RTS hardware flow control enable. If this bit is set to 1, RTS hardware flow control is enabled. Data is only requested when there is space in the receive FIFO for it to be received.</description>
-              <name>RTSEN</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[13:13]</bitRange>
-              <description>This bit is the complement of the UART Out2 (nUARTOut2) modem status output. That is, when the bit is programmed to a 1, the output is 0. For DTE this can be used as Ring Indicator (RI).</description>
-              <name>OUT2</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[12:12]</bitRange>
-              <description>This bit is the complement of the UART Out1 (nUARTOut1) modem status output. That is, when the bit is programmed to a 1 the output is 0. For DTE this can be used as Data Carrier Detect (DCD).</description>
-              <name>OUT1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[11:11]</bitRange>
-              <description>Request to send. This bit is the complement of the UART request to send, nUARTRTS, modem status output. That is, when the bit is programmed to a 1 then nUARTRTS is LOW.</description>
-              <name>RTS</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[10:10]</bitRange>
-              <description>Data transmit ready. This bit is the complement of the UART data transmit ready, nUARTDTR, modem status output. That is, when the bit is programmed to a 1 then nUARTDTR is LOW.</description>
-              <name>DTR</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[9:9]</bitRange>
-              <description>Receive enable. If this bit is set to 1, the receive section of the UART is enabled. Data reception occurs for either UART signals or SIR signals depending on the setting of the SIREN bit. When the UART is disabled in the middle of reception, it completes the current character before stopping.</description>
-              <name>RXE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[8:8]</bitRange>
-              <description>Transmit enable. If this bit is set to 1, the transmit section of the UART is enabled. Data transmission occurs for either UART signals, or SIR signals depending on the setting of the SIREN bit. When the UART is disabled in the middle of transmission, it completes the current character before stopping.</description>
-              <name>TXE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[7:7]</bitRange>
-              <description>Loopback enable. If this bit is set to 1 and the SIREN bit is set to 1 and the SIRTEST bit in the Test Control Register, UARTTCR is set to 1, then the nSIROUT path is inverted, and fed through to the SIRIN path. The SIRTEST bit in the test register must be set to 1 to override the normal half-duplex SIR operation. This must be the requirement for accessing the test registers during normal operation, and SIRTEST must be cleared to 0 when loopback testing is finished. This feature reduces the amount of external coupling required during system test. If this bit is set to 1, and the SIRTEST bit is set to 0, the UARTTXD path is fed through to the UARTRXD path. In either SIR mode or UART mode, when this bit is set, the modem outputs are also fed through to the modem inputs. This bit is cleared to 0 on reset, to disable loopback.</description>
-              <name>LBE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[2:2]</bitRange>
-              <description>SIR low-power IrDA mode. This bit selects the IrDA encoding mode. If this bit is cleared to 0, low-level bits are transmitted as an active high pulse with a width of 3 / 16th of the bit period. If this bit is set to 1, low-level bits are transmitted with a pulse width that is 3 times the period of the IrLPBaud16 input signal, regardless of the selected bit rate. Setting this bit uses less power, but might reduce transmission distances.</description>
-              <name>SIRLP</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[1:1]</bitRange>
-              <description>SIR enable: 0 = IrDA SIR ENDEC is disabled. nSIROUT remains LOW (no light pulse generated), and signal transitions on SIRIN have no effect. 1 = IrDA SIR ENDEC is enabled. Data is transmitted and received on nSIROUT and SIRIN. UARTTXD remains HIGH, in the marking state. Signal transitions on UARTRXD or modem status inputs have no effect. This bit has no effect if the UARTEN bit disables the UART.</description>
-              <name>SIREN</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[0:0]</bitRange>
-              <description>UART enable: 0 = UART is disabled. If the UART is disabled in the middle of transmission or reception, it completes the current character before stopping. 1 = the UART is enabled. Data transmission and reception occurs for either UART signals or SIR signals depending on the setting of the SIREN bit.</description>
-              <name>UARTEN</name>
-            </field>
-          </fields>
-          <name>UARTCR</name>
-          <resetValue>0x00000300</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0034</addressOffset>
-          <description>Interrupt FIFO Level Select Register, UARTIFLS</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[5:3]</bitRange>
-              <description>Receive interrupt FIFO level select. The trigger points for the receive interrupt are as follows: b000 = Receive FIFO becomes &gt;= 1 / 8 full b001 = Receive FIFO becomes &gt;= 1 / 4 full b010 = Receive FIFO becomes &gt;= 1 / 2 full b011 = Receive FIFO becomes &gt;= 3 / 4 full b100 = Receive FIFO becomes &gt;= 7 / 8 full b101-b111 = reserved.</description>
-              <name>RXIFLSEL</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[2:0]</bitRange>
-              <description>Transmit interrupt FIFO level select. The trigger points for the transmit interrupt are as follows: b000 = Transmit FIFO becomes &lt;= 1 / 8 full b001 = Transmit FIFO becomes &lt;= 1 / 4 full b010 = Transmit FIFO becomes &lt;= 1 / 2 full b011 = Transmit FIFO becomes &lt;= 3 / 4 full b100 = Transmit FIFO becomes &lt;= 7 / 8 full b101-b111 = reserved.</description>
-              <name>TXIFLSEL</name>
-            </field>
-          </fields>
-          <name>UARTIFLS</name>
-          <resetValue>0x00000012</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0038</addressOffset>
-          <description>Interrupt Mask Set/Clear Register, UARTIMSC</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[10:10]</bitRange>
-              <description>Overrun error interrupt mask. A read returns the current mask for the UARTOEINTR interrupt. On a write of 1, the mask of the UARTOEINTR interrupt is set. A write of 0 clears the mask.</description>
-              <name>OEIM</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[9:9]</bitRange>
-              <description>Break error interrupt mask. A read returns the current mask for the UARTBEINTR interrupt. On a write of 1, the mask of the UARTBEINTR interrupt is set. A write of 0 clears the mask.</description>
-              <name>BEIM</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[8:8]</bitRange>
-              <description>Parity error interrupt mask. A read returns the current mask for the UARTPEINTR interrupt. On a write of 1, the mask of the UARTPEINTR interrupt is set. A write of 0 clears the mask.</description>
-              <name>PEIM</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[7:7]</bitRange>
-              <description>Framing error interrupt mask. A read returns the current mask for the UARTFEINTR interrupt. On a write of 1, the mask of the UARTFEINTR interrupt is set. A write of 0 clears the mask.</description>
-              <name>FEIM</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[6:6]</bitRange>
-              <description>Receive timeout interrupt mask. A read returns the current mask for the UARTRTINTR interrupt. On a write of 1, the mask of the UARTRTINTR interrupt is set. A write of 0 clears the mask.</description>
-              <name>RTIM</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[5:5]</bitRange>
-              <description>Transmit interrupt mask. A read returns the current mask for the UARTTXINTR interrupt. On a write of 1, the mask of the UARTTXINTR interrupt is set. A write of 0 clears the mask.</description>
-              <name>TXIM</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[4:4]</bitRange>
-              <description>Receive interrupt mask. A read returns the current mask for the UARTRXINTR interrupt. On a write of 1, the mask of the UARTRXINTR interrupt is set. A write of 0 clears the mask.</description>
-              <name>RXIM</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[3:3]</bitRange>
-              <description>nUARTDSR modem interrupt mask. A read returns the current mask for the UARTDSRINTR interrupt. On a write of 1, the mask of the UARTDSRINTR interrupt is set. A write of 0 clears the mask.</description>
-              <name>DSRMIM</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[2:2]</bitRange>
-              <description>nUARTDCD modem interrupt mask. A read returns the current mask for the UARTDCDINTR interrupt. On a write of 1, the mask of the UARTDCDINTR interrupt is set. A write of 0 clears the mask.</description>
-              <name>DCDMIM</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[1:1]</bitRange>
-              <description>nUARTCTS modem interrupt mask. A read returns the current mask for the UARTCTSINTR interrupt. On a write of 1, the mask of the UARTCTSINTR interrupt is set. A write of 0 clears the mask.</description>
-              <name>CTSMIM</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[0:0]</bitRange>
-              <description>nUARTRI modem interrupt mask. A read returns the current mask for the UARTRIINTR interrupt. On a write of 1, the mask of the UARTRIINTR interrupt is set. A write of 0 clears the mask.</description>
-              <name>RIMIM</name>
-            </field>
-          </fields>
-          <name>UARTIMSC</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x003c</addressOffset>
-          <description>Raw Interrupt Status Register, UARTRIS</description>
-          <fields>
-            <field>
-              <access>read-only</access>
-              <bitRange>[10:10]</bitRange>
-              <description>Overrun error interrupt status. Returns the raw interrupt state of the UARTOEINTR interrupt.</description>
-              <name>OERIS</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[9:9]</bitRange>
-              <description>Break error interrupt status. Returns the raw interrupt state of the UARTBEINTR interrupt.</description>
-              <name>BERIS</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[8:8]</bitRange>
-              <description>Parity error interrupt status. Returns the raw interrupt state of the UARTPEINTR interrupt.</description>
-              <name>PERIS</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[7:7]</bitRange>
-              <description>Framing error interrupt status. Returns the raw interrupt state of the UARTFEINTR interrupt.</description>
-              <name>FERIS</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[6:6]</bitRange>
-              <description>Receive timeout interrupt status. Returns the raw interrupt state of the UARTRTINTR interrupt. a</description>
-              <name>RTRIS</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[5:5]</bitRange>
-              <description>Transmit interrupt status. Returns the raw interrupt state of the UARTTXINTR interrupt.</description>
-              <name>TXRIS</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[4:4]</bitRange>
-              <description>Receive interrupt status. Returns the raw interrupt state of the UARTRXINTR interrupt.</description>
-              <name>RXRIS</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[3:3]</bitRange>
-              <description>nUARTDSR modem interrupt status. Returns the raw interrupt state of the UARTDSRINTR interrupt.</description>
-              <name>DSRRMIS</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[2:2]</bitRange>
-              <description>nUARTDCD modem interrupt status. Returns the raw interrupt state of the UARTDCDINTR interrupt.</description>
-              <name>DCDRMIS</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[1:1]</bitRange>
-              <description>nUARTCTS modem interrupt status. Returns the raw interrupt state of the UARTCTSINTR interrupt.</description>
-              <name>CTSRMIS</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[0:0]</bitRange>
-              <description>nUARTRI modem interrupt status. Returns the raw interrupt state of the UARTRIINTR interrupt.</description>
-              <name>RIRMIS</name>
-            </field>
-          </fields>
-          <name>UARTRIS</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0040</addressOffset>
-          <description>Masked Interrupt Status Register, UARTMIS</description>
-          <fields>
-            <field>
-              <access>read-only</access>
-              <bitRange>[10:10]</bitRange>
-              <description>Overrun error masked interrupt status. Returns the masked interrupt state of the UARTOEINTR interrupt.</description>
-              <name>OEMIS</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[9:9]</bitRange>
-              <description>Break error masked interrupt status. Returns the masked interrupt state of the UARTBEINTR interrupt.</description>
-              <name>BEMIS</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[8:8]</bitRange>
-              <description>Parity error masked interrupt status. Returns the masked interrupt state of the UARTPEINTR interrupt.</description>
-              <name>PEMIS</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[7:7]</bitRange>
-              <description>Framing error masked interrupt status. Returns the masked interrupt state of the UARTFEINTR interrupt.</description>
-              <name>FEMIS</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[6:6]</bitRange>
-              <description>Receive timeout masked interrupt status. Returns the masked interrupt state of the UARTRTINTR interrupt.</description>
-              <name>RTMIS</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[5:5]</bitRange>
-              <description>Transmit masked interrupt status. Returns the masked interrupt state of the UARTTXINTR interrupt.</description>
-              <name>TXMIS</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[4:4]</bitRange>
-              <description>Receive masked interrupt status. Returns the masked interrupt state of the UARTRXINTR interrupt.</description>
-              <name>RXMIS</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[3:3]</bitRange>
-              <description>nUARTDSR modem masked interrupt status. Returns the masked interrupt state of the UARTDSRINTR interrupt.</description>
-              <name>DSRMMIS</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[2:2]</bitRange>
-              <description>nUARTDCD modem masked interrupt status. Returns the masked interrupt state of the UARTDCDINTR interrupt.</description>
-              <name>DCDMMIS</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[1:1]</bitRange>
-              <description>nUARTCTS modem masked interrupt status. Returns the masked interrupt state of the UARTCTSINTR interrupt.</description>
-              <name>CTSMMIS</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[0:0]</bitRange>
-              <description>nUARTRI modem masked interrupt status. Returns the masked interrupt state of the UARTRIINTR interrupt.</description>
-              <name>RIMMIS</name>
-            </field>
-          </fields>
-          <name>UARTMIS</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0044</addressOffset>
-          <description>Interrupt Clear Register, UARTICR</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[10:10]</bitRange>
-              <description>Overrun error interrupt clear. Clears the UARTOEINTR interrupt.</description>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>OEIC</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[9:9]</bitRange>
-              <description>Break error interrupt clear. Clears the UARTBEINTR interrupt.</description>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>BEIC</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[8:8]</bitRange>
-              <description>Parity error interrupt clear. Clears the UARTPEINTR interrupt.</description>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>PEIC</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[7:7]</bitRange>
-              <description>Framing error interrupt clear. Clears the UARTFEINTR interrupt.</description>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>FEIC</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[6:6]</bitRange>
-              <description>Receive timeout interrupt clear. Clears the UARTRTINTR interrupt.</description>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>RTIC</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[5:5]</bitRange>
-              <description>Transmit interrupt clear. Clears the UARTTXINTR interrupt.</description>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>TXIC</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[4:4]</bitRange>
-              <description>Receive interrupt clear. Clears the UARTRXINTR interrupt.</description>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>RXIC</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[3:3]</bitRange>
-              <description>nUARTDSR modem interrupt clear. Clears the UARTDSRINTR interrupt.</description>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>DSRMIC</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[2:2]</bitRange>
-              <description>nUARTDCD modem interrupt clear. Clears the UARTDCDINTR interrupt.</description>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>DCDMIC</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[1:1]</bitRange>
-              <description>nUARTCTS modem interrupt clear. Clears the UARTCTSINTR interrupt.</description>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>CTSMIC</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[0:0]</bitRange>
-              <description>nUARTRI modem interrupt clear. Clears the UARTRIINTR interrupt.</description>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>RIMIC</name>
-            </field>
-          </fields>
-          <name>UARTICR</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0048</addressOffset>
-          <description>DMA Control Register, UARTDMACR</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[2:2]</bitRange>
-              <description>DMA on error. If this bit is set to 1, the DMA receive request outputs, UARTRXDMASREQ or UARTRXDMABREQ, are disabled when the UART error interrupt is asserted.</description>
-              <name>DMAONERR</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[1:1]</bitRange>
-              <description>Transmit DMA enable. If this bit is set to 1, DMA for the transmit FIFO is enabled.</description>
-              <name>TXDMAE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[0:0]</bitRange>
-              <description>Receive DMA enable. If this bit is set to 1, DMA for the receive FIFO is enabled.</description>
-              <name>RXDMAE</name>
-            </field>
-          </fields>
-          <name>UARTDMACR</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0fe0</addressOffset>
-          <description>UARTPeriphID0 Register</description>
-          <fields>
-            <field>
-              <access>read-only</access>
-              <bitRange>[7:0]</bitRange>
-              <description>These bits read back as 0x11</description>
-              <name>PARTNUMBER0</name>
-            </field>
-          </fields>
-          <name>UARTPERIPHID0</name>
-          <resetValue>0x00000011</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0fe4</addressOffset>
-          <description>UARTPeriphID1 Register</description>
-          <fields>
-            <field>
-              <access>read-only</access>
-              <bitRange>[7:4]</bitRange>
-              <description>These bits read back as 0x1</description>
-              <name>DESIGNER0</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[3:0]</bitRange>
-              <description>These bits read back as 0x0</description>
-              <name>PARTNUMBER1</name>
-            </field>
-          </fields>
-          <name>UARTPERIPHID1</name>
-          <resetValue>0x00000010</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0fe8</addressOffset>
-          <description>UARTPeriphID2 Register</description>
-          <fields>
-            <field>
-              <access>read-only</access>
-              <bitRange>[7:4]</bitRange>
-              <description>This field depends on the revision of the UART: r1p0 0x0 r1p1 0x1 r1p3 0x2 r1p4 0x2 r1p5 0x3</description>
-              <name>REVISION</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[3:0]</bitRange>
-              <description>These bits read back as 0x4</description>
-              <name>DESIGNER1</name>
-            </field>
-          </fields>
-          <name>UARTPERIPHID2</name>
-          <resetValue>0x00000034</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0fec</addressOffset>
-          <description>UARTPeriphID3 Register</description>
-          <fields>
-            <field>
-              <access>read-only</access>
-              <bitRange>[7:0]</bitRange>
-              <description>These bits read back as 0x00</description>
-              <name>CONFIGURATION</name>
-            </field>
-          </fields>
-          <name>UARTPERIPHID3</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0ff0</addressOffset>
-          <description>UARTPCellID0 Register</description>
-          <fields>
-            <field>
-              <access>read-only</access>
-              <bitRange>[7:0]</bitRange>
-              <description>These bits read back as 0x0D</description>
-              <name>UARTPCELLID0</name>
-            </field>
-          </fields>
-          <name>UARTPCELLID0</name>
-          <resetValue>0x0000000d</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0ff4</addressOffset>
-          <description>UARTPCellID1 Register</description>
-          <fields>
-            <field>
-              <access>read-only</access>
-              <bitRange>[7:0]</bitRange>
-              <description>These bits read back as 0xF0</description>
-              <name>UARTPCELLID1</name>
-            </field>
-          </fields>
-          <name>UARTPCELLID1</name>
-          <resetValue>0x000000f0</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0ff8</addressOffset>
-          <description>UARTPCellID2 Register</description>
-          <fields>
-            <field>
-              <access>read-only</access>
-              <bitRange>[7:0]</bitRange>
-              <description>These bits read back as 0x05</description>
-              <name>UARTPCELLID2</name>
-            </field>
-          </fields>
-          <name>UARTPCELLID2</name>
-          <resetValue>0x00000005</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0ffc</addressOffset>
-          <description>UARTPCellID3 Register</description>
-          <fields>
-            <field>
-              <access>read-only</access>
-              <bitRange>[7:0]</bitRange>
-              <description>These bits read back as 0xB1</description>
-              <name>UARTPCELLID3</name>
-            </field>
-          </fields>
-          <name>UARTPCELLID3</name>
-          <resetValue>0x000000b1</resetValue>
-        </register>
-      </registers>
-      <size>32</size>
-      <version>1</version>
-    </peripheral>
-    <peripheral derivedFrom="UART0">
-      <baseAddress>0x40038000</baseAddress>
-      <interrupt>
-        <name>UART1_IRQ</name>
-        <value>21</value>
-      </interrupt>
-      <name>UART1</name>
-    </peripheral>
-    <peripheral>
-      <addressBlock>
-        <offset>0</offset>
-        <size>0x1000</size>
-        <usage>registers</usage>
-      </addressBlock>
-      <baseAddress>0x4003c000</baseAddress>
-      <interrupt>
-        <name>SPI0_IRQ</name>
-        <value>18</value>
-      </interrupt>
-      <name>SPI0</name>
-      <registers>
-        <register>
-          <addressOffset>0x0000</addressOffset>
-          <description>Control register 0, SSPCR0 on page 3-4</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[15:8]</bitRange>
-              <description>Serial clock rate. The value SCR is used to generate the transmit and receive bit rate of the PrimeCell SSP. The bit rate is: F SSPCLK CPSDVSR x (1+SCR) where CPSDVSR is an even value from 2-254, programmed through the SSPCPSR register and SCR is a value from 0-255.</description>
-              <name>SCR</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[7:7]</bitRange>
-              <description>SSPCLKOUT phase, applicable to Motorola SPI frame format only. See Motorola SPI frame format on page 2-10.</description>
-              <name>SPH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[6:6]</bitRange>
-              <description>SSPCLKOUT polarity, applicable to Motorola SPI frame format only. See Motorola SPI frame format on page 2-10.</description>
-              <name>SPO</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[5:4]</bitRange>
-              <description>Frame format: 00 Motorola SPI frame format. 01 TI synchronous serial frame format. 10 National Microwire frame format. 11 Reserved, undefined operation.</description>
-              <name>FRF</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[3:0]</bitRange>
-              <description>Data Size Select: 0000 Reserved, undefined operation. 0001 Reserved, undefined operation. 0010 Reserved, undefined operation. 0011 4-bit data. 0100 5-bit data. 0101 6-bit data. 0110 7-bit data. 0111 8-bit data. 1000 9-bit data. 1001 10-bit data. 1010 11-bit data. 1011 12-bit data. 1100 13-bit data. 1101 14-bit data. 1110 15-bit data. 1111 16-bit data.</description>
-              <name>DSS</name>
-            </field>
-          </fields>
-          <name>SSPCR0</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0004</addressOffset>
-          <description>Control register 1, SSPCR1 on page 3-5</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[3:3]</bitRange>
-              <description>Slave-mode output disable. This bit is relevant only in the slave mode, MS=1. In multiple-slave systems, it is possible for an PrimeCell SSP master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto its serial output line. In such systems the RXD lines from multiple slaves could be tied together. To operate in such systems, the SOD bit can be set if the PrimeCell SSP slave is not supposed to drive the SSPTXD line: 0 SSP can drive the SSPTXD output in slave mode. 1 SSP must not drive the SSPTXD output in slave mode.</description>
-              <name>SOD</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[2:2]</bitRange>
-              <description>Master or slave mode select. This bit can be modified only when the PrimeCell SSP is disabled, SSE=0: 0 Device configured as master, default. 1 Device configured as slave.</description>
-              <name>MS</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[1:1]</bitRange>
-              <description>Synchronous serial port enable: 0 SSP operation disabled. 1 SSP operation enabled.</description>
-              <name>SSE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[0:0]</bitRange>
-              <description>Loop back mode: 0 Normal serial port operation enabled. 1 Output of transmit serial shifter is connected to input of receive serial shifter internally.</description>
-              <name>LBM</name>
-            </field>
-          </fields>
-          <name>SSPCR1</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0008</addressOffset>
-          <description>Data register, SSPDR on page 3-6</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[15:0]</bitRange>
-              <description>Transmit/Receive FIFO: Read Receive FIFO. Write Transmit FIFO. You must right-justify data when the PrimeCell SSP is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies.</description>
-              <name>DATA</name>
-            </field>
-          </fields>
-          <name>SSPDR</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x000c</addressOffset>
-          <description>Status register, SSPSR on page 3-7</description>
-          <fields>
-            <field>
-              <access>read-only</access>
-              <bitRange>[4:4]</bitRange>
-              <description>PrimeCell SSP busy flag, RO: 0 SSP is idle. 1 SSP is currently transmitting and/or receiving a frame or the transmit FIFO is not empty.</description>
-              <name>BSY</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[3:3]</bitRange>
-              <description>Receive FIFO full, RO: 0 Receive FIFO is not full. 1 Receive FIFO is full.</description>
-              <name>RFF</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[2:2]</bitRange>
-              <description>Receive FIFO not empty, RO: 0 Receive FIFO is empty. 1 Receive FIFO is not empty.</description>
-              <name>RNE</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[1:1]</bitRange>
-              <description>Transmit FIFO not full, RO: 0 Transmit FIFO is full. 1 Transmit FIFO is not full.</description>
-              <name>TNF</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[0:0]</bitRange>
-              <description>Transmit FIFO empty, RO: 0 Transmit FIFO is not empty. 1 Transmit FIFO is empty.</description>
-              <name>TFE</name>
-            </field>
-          </fields>
-          <name>SSPSR</name>
-          <resetValue>0x00000003</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0010</addressOffset>
-          <description>Clock prescale register, SSPCPSR on page 3-8</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[7:0]</bitRange>
-              <description>Clock prescale divisor. Must be an even number from 2-254, depending on the frequency of SSPCLK. The least significant bit always returns zero on reads.</description>
-              <name>CPSDVSR</name>
-            </field>
-          </fields>
-          <name>SSPCPSR</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0014</addressOffset>
-          <description>Interrupt mask set or clear register, SSPIMSC on page 3-9</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[3:3]</bitRange>
-              <description>Transmit FIFO interrupt mask: 0 Transmit FIFO half empty or less condition interrupt is masked. 1 Transmit FIFO half empty or less condition interrupt is not masked.</description>
-              <name>TXIM</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[2:2]</bitRange>
-              <description>Receive FIFO interrupt mask: 0 Receive FIFO half full or less condition interrupt is masked. 1 Receive FIFO half full or less condition interrupt is not masked.</description>
-              <name>RXIM</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[1:1]</bitRange>
-              <description>Receive timeout interrupt mask: 0 Receive FIFO not empty and no read prior to timeout period interrupt is masked. 1 Receive FIFO not empty and no read prior to timeout period interrupt is not masked.</description>
-              <name>RTIM</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[0:0]</bitRange>
-              <description>Receive overrun interrupt mask: 0 Receive FIFO written to while full condition interrupt is masked. 1 Receive FIFO written to while full condition interrupt is not masked.</description>
-              <name>RORIM</name>
-            </field>
-          </fields>
-          <name>SSPIMSC</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0018</addressOffset>
-          <description>Raw interrupt status register, SSPRIS on page 3-10</description>
-          <fields>
-            <field>
-              <access>read-only</access>
-              <bitRange>[3:3]</bitRange>
-              <description>Gives the raw interrupt state, prior to masking, of the SSPTXINTR interrupt</description>
-              <name>TXRIS</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[2:2]</bitRange>
-              <description>Gives the raw interrupt state, prior to masking, of the SSPRXINTR interrupt</description>
-              <name>RXRIS</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[1:1]</bitRange>
-              <description>Gives the raw interrupt state, prior to masking, of the SSPRTINTR interrupt</description>
-              <name>RTRIS</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[0:0]</bitRange>
-              <description>Gives the raw interrupt state, prior to masking, of the SSPRORINTR interrupt</description>
-              <name>RORRIS</name>
-            </field>
-          </fields>
-          <name>SSPRIS</name>
-          <resetValue>0x00000008</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x001c</addressOffset>
-          <description>Masked interrupt status register, SSPMIS on page 3-11</description>
-          <fields>
-            <field>
-              <access>read-only</access>
-              <bitRange>[3:3]</bitRange>
-              <description>Gives the transmit FIFO masked interrupt state, after masking, of the SSPTXINTR interrupt</description>
-              <name>TXMIS</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[2:2]</bitRange>
-              <description>Gives the receive FIFO masked interrupt state, after masking, of the SSPRXINTR interrupt</description>
-              <name>RXMIS</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[1:1]</bitRange>
-              <description>Gives the receive timeout masked interrupt state, after masking, of the SSPRTINTR interrupt</description>
-              <name>RTMIS</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[0:0]</bitRange>
-              <description>Gives the receive over run masked interrupt status, after masking, of the SSPRORINTR interrupt</description>
-              <name>RORMIS</name>
-            </field>
-          </fields>
-          <name>SSPMIS</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0020</addressOffset>
-          <description>Interrupt clear register, SSPICR on page 3-11</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[1:1]</bitRange>
-              <description>Clears the SSPRTINTR interrupt</description>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>RTIC</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[0:0]</bitRange>
-              <description>Clears the SSPRORINTR interrupt</description>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>RORIC</name>
-            </field>
-          </fields>
-          <name>SSPICR</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0024</addressOffset>
-          <description>DMA control register, SSPDMACR on page 3-12</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[1:1]</bitRange>
-              <description>Transmit DMA Enable. If this bit is set to 1, DMA for the transmit FIFO is enabled.</description>
-              <name>TXDMAE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[0:0]</bitRange>
-              <description>Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO is enabled.</description>
-              <name>RXDMAE</name>
-            </field>
-          </fields>
-          <name>SSPDMACR</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0fe0</addressOffset>
-          <description>Peripheral identification registers, SSPPeriphID0-3 on page 3-13</description>
-          <fields>
-            <field>
-              <access>read-only</access>
-              <bitRange>[7:0]</bitRange>
-              <description>These bits read back as 0x22</description>
-              <name>PARTNUMBER0</name>
-            </field>
-          </fields>
-          <name>SSPPERIPHID0</name>
-          <resetValue>0x00000022</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0fe4</addressOffset>
-          <description>Peripheral identification registers, SSPPeriphID0-3 on page 3-13</description>
-          <fields>
-            <field>
-              <access>read-only</access>
-              <bitRange>[7:4]</bitRange>
-              <description>These bits read back as 0x1</description>
-              <name>DESIGNER0</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[3:0]</bitRange>
-              <description>These bits read back as 0x0</description>
-              <name>PARTNUMBER1</name>
-            </field>
-          </fields>
-          <name>SSPPERIPHID1</name>
-          <resetValue>0x00000010</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0fe8</addressOffset>
-          <description>Peripheral identification registers, SSPPeriphID0-3 on page 3-13</description>
-          <fields>
-            <field>
-              <access>read-only</access>
-              <bitRange>[7:4]</bitRange>
-              <description>These bits return the peripheral revision</description>
-              <name>REVISION</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[3:0]</bitRange>
-              <description>These bits read back as 0x4</description>
-              <name>DESIGNER1</name>
-            </field>
-          </fields>
-          <name>SSPPERIPHID2</name>
-          <resetValue>0x00000034</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0fec</addressOffset>
-          <description>Peripheral identification registers, SSPPeriphID0-3 on page 3-13</description>
-          <fields>
-            <field>
-              <access>read-only</access>
-              <bitRange>[7:0]</bitRange>
-              <description>These bits read back as 0x00</description>
-              <name>CONFIGURATION</name>
-            </field>
-          </fields>
-          <name>SSPPERIPHID3</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0ff0</addressOffset>
-          <description>PrimeCell identification registers, SSPPCellID0-3 on page 3-16</description>
-          <fields>
-            <field>
-              <access>read-only</access>
-              <bitRange>[7:0]</bitRange>
-              <description>These bits read back as 0x0D</description>
-              <name>SSPPCELLID0</name>
-            </field>
-          </fields>
-          <name>SSPPCELLID0</name>
-          <resetValue>0x0000000d</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0ff4</addressOffset>
-          <description>PrimeCell identification registers, SSPPCellID0-3 on page 3-16</description>
-          <fields>
-            <field>
-              <access>read-only</access>
-              <bitRange>[7:0]</bitRange>
-              <description>These bits read back as 0xF0</description>
-              <name>SSPPCELLID1</name>
-            </field>
-          </fields>
-          <name>SSPPCELLID1</name>
-          <resetValue>0x000000f0</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0ff8</addressOffset>
-          <description>PrimeCell identification registers, SSPPCellID0-3 on page 3-16</description>
-          <fields>
-            <field>
-              <access>read-only</access>
-              <bitRange>[7:0]</bitRange>
-              <description>These bits read back as 0x05</description>
-              <name>SSPPCELLID2</name>
-            </field>
-          </fields>
-          <name>SSPPCELLID2</name>
-          <resetValue>0x00000005</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0ffc</addressOffset>
-          <description>PrimeCell identification registers, SSPPCellID0-3 on page 3-16</description>
-          <fields>
-            <field>
-              <access>read-only</access>
-              <bitRange>[7:0]</bitRange>
-              <description>These bits read back as 0xB1</description>
-              <name>SSPPCELLID3</name>
-            </field>
-          </fields>
-          <name>SSPPCELLID3</name>
-          <resetValue>0x000000b1</resetValue>
-        </register>
-      </registers>
-      <size>32</size>
-      <version>1</version>
-    </peripheral>
-    <peripheral derivedFrom="SPI0">
-      <baseAddress>0x40040000</baseAddress>
-      <interrupt>
-        <name>SPI1_IRQ</name>
-        <value>19</value>
-      </interrupt>
-      <name>SPI1</name>
-    </peripheral>
-    <peripheral>
-      <addressBlock>
-        <offset>0</offset>
-        <size>0x0100</size>
-        <usage>registers</usage>
-      </addressBlock>
-      <baseAddress>0x40044000</baseAddress>
-      <description>DW_apb_i2c address block\n\n
-        List of configuration constants for the Synopsys I2C hardware (you may see references to these in I2C register header; these are *fixed* values, set at hardware design time):\n\n
-        IC_ULTRA_FAST_MODE ................ 0x0\n
-        IC_UFM_TBUF_CNT_DEFAULT ........... 0x8\n
-        IC_UFM_SCL_LOW_COUNT .............. 0x0008\n
-        IC_UFM_SCL_HIGH_COUNT ............. 0x0006\n
-        IC_TX_TL .......................... 0x0\n
-        IC_TX_CMD_BLOCK ................... 0x1\n
-        IC_HAS_DMA ........................ 0x1\n
-        IC_HAS_ASYNC_FIFO ................. 0x0\n
-        IC_SMBUS_ARP ...................... 0x0\n
-        IC_FIRST_DATA_BYTE_STATUS ......... 0x1\n
-        IC_INTR_IO ........................ 0x1\n
-        IC_MASTER_MODE .................... 0x1\n
-        IC_DEFAULT_ACK_GENERAL_CALL ....... 0x1\n
-        IC_INTR_POL ....................... 0x1\n
-        IC_OPTIONAL_SAR ................... 0x0\n
-        IC_DEFAULT_TAR_SLAVE_ADDR ......... 0x055\n
-        IC_DEFAULT_SLAVE_ADDR ............. 0x055\n
-        IC_DEFAULT_HS_SPKLEN .............. 0x1\n
-        IC_FS_SCL_HIGH_COUNT .............. 0x0006\n
-        IC_HS_SCL_LOW_COUNT ............... 0x0008\n
-        IC_DEVICE_ID_VALUE ................ 0x0\n
-        IC_10BITADDR_MASTER ............... 0x0\n
-        IC_CLK_FREQ_OPTIMIZATION .......... 0x0\n
-        IC_DEFAULT_FS_SPKLEN .............. 0x7\n
-        IC_ADD_ENCODED_PARAMS ............. 0x0\n
-        IC_DEFAULT_SDA_HOLD ............... 0x000001\n
-        IC_DEFAULT_SDA_SETUP .............. 0x64\n
-        IC_AVOID_RX_FIFO_FLUSH_ON_TX_ABRT . 0x0\n
-        IC_CLOCK_PERIOD ................... 100\n
-        IC_EMPTYFIFO_HOLD_MASTER_EN ....... 1\n
-        IC_RESTART_EN ..................... 0x1\n
-        IC_TX_CMD_BLOCK_DEFAULT ........... 0x0\n
-        IC_BUS_CLEAR_FEATURE .............. 0x0\n
-        IC_CAP_LOADING .................... 100\n
-        IC_FS_SCL_LOW_COUNT ............... 0x000d\n
-        APB_DATA_WIDTH .................... 32\n
-        IC_SDA_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff\n
-        IC_SLV_DATA_NACK_ONLY ............. 0x1\n
-        IC_10BITADDR_SLAVE ................ 0x0\n
-        IC_CLK_TYPE ....................... 0x0\n
-        IC_SMBUS_UDID_MSB ................. 0x0\n
-        IC_SMBUS_SUSPEND_ALERT ............ 0x0\n
-        IC_HS_SCL_HIGH_COUNT .............. 0x0006\n
-        IC_SLV_RESTART_DET_EN ............. 0x1\n
-        IC_SMBUS .......................... 0x0\n
-        IC_OPTIONAL_SAR_DEFAULT ........... 0x0\n
-        IC_PERSISTANT_SLV_ADDR_DEFAULT .... 0x0\n
-        IC_USE_COUNTS ..................... 0x0\n
-        IC_RX_BUFFER_DEPTH ................ 16\n
-        IC_SCL_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff\n
-        IC_RX_FULL_HLD_BUS_EN ............. 0x1\n
-        IC_SLAVE_DISABLE .................. 0x1\n
-        IC_RX_TL .......................... 0x0\n
-        IC_DEVICE_ID ...................... 0x0\n
-        IC_HC_COUNT_VALUES ................ 0x0\n
-        I2C_DYNAMIC_TAR_UPDATE ............ 0\n
-        IC_SMBUS_CLK_LOW_MEXT_DEFAULT ..... 0xffffffff\n
-        IC_SMBUS_CLK_LOW_SEXT_DEFAULT ..... 0xffffffff\n
-        IC_HS_MASTER_CODE ................. 0x1\n
-        IC_SMBUS_RST_IDLE_CNT_DEFAULT ..... 0xffff\n
-        IC_SMBUS_UDID_LSB_DEFAULT ......... 0xffffffff\n
-        IC_SS_SCL_HIGH_COUNT .............. 0x0028\n
-        IC_SS_SCL_LOW_COUNT ............... 0x002f\n
-        IC_MAX_SPEED_MODE ................. 0x2\n
-        IC_STAT_FOR_CLK_STRETCH ........... 0x0\n
-        IC_STOP_DET_IF_MASTER_ACTIVE ...... 0x0\n
-        IC_DEFAULT_UFM_SPKLEN ............. 0x1\n
-        IC_TX_BUFFER_DEPTH ................ 16</description>
-      <interrupt>
-        <name>I2C0_IRQ</name>
-        <value>23</value>
-      </interrupt>
-      <name>I2C0</name>
-      <registers>
-        <register>
-          <addressOffset>0x0000</addressOffset>
-          <description>I2C Control Register. This register can be written only when the DW_apb_i2c is disabled, which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect.\n\n
-            Read/Write Access: - bit 10 is read only. - bit 11 is read only - bit 16 is read only - bit 17 is read only - bits 18 and 19 are read only.</description>
-          <fields>
-            <field>
-              <access>read-only</access>
-              <bitRange>[10:10]</bitRange>
-              <description>Master issues the STOP_DET interrupt irrespective of whether master is active or not</description>
-              <name>STOP_DET_IF_MASTER_ACTIVE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[9:9]</bitRange>
-              <description>This bit controls whether DW_apb_i2c should hold the bus when the Rx FIFO is physically full to its RX_BUFFER_DEPTH, as described in the IC_RX_FULL_HLD_BUS_EN parameter.\n\n
-                Reset value: 0x0.</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>Overflow when RX_FIFO is full</description>
-                  <name>DISABLED</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>Hold bus when RX_FIFO is full</description>
-                  <name>ENABLED</name>
-                  <value>1</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>RX_FIFO_FULL_HLD_CTRL</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[8:8]</bitRange>
-              <description>This bit controls the generation of the TX_EMPTY interrupt, as described in the IC_RAW_INTR_STAT register.\n\n
-                Reset value: 0x0.</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>Default behaviour of TX_EMPTY interrupt</description>
-                  <name>DISABLED</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>Controlled generation of TX_EMPTY interrupt</description>
-                  <name>ENABLED</name>
-                  <value>1</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>TX_EMPTY_CTRL</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[7:7]</bitRange>
-              <description>In slave mode: - 1'b1:  issues the STOP_DET interrupt only when it is addressed. - 1'b0:  issues the STOP_DET irrespective of whether it's addressed or not. Reset value: 0x0\n\n
-                NOTE: During a general call address, this slave does not issue the STOP_DET interrupt if STOP_DET_IF_ADDRESSED = 1'b1, even if the slave responds to the general call address by generating ACK. The STOP_DET interrupt is generated only when the transmitted address matches the slave address (SAR).</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>slave issues STOP_DET intr always</description>
-                  <name>DISABLED</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>slave issues STOP_DET intr only if addressed</description>
-                  <name>ENABLED</name>
-                  <value>1</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>STOP_DET_IFADDRESSED</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[6:6]</bitRange>
-              <description>This bit controls whether I2C has its slave disabled, which means once the presetn signal is applied, then this bit is set and the slave is disabled.\n\n
-                If this bit is set (slave is disabled), DW_apb_i2c functions only as a master and does not perform any action that requires a slave.\n\n
-                NOTE: Software should ensure that if this bit is written with 0, then bit 0 should also be written with a 0.</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>Slave mode is enabled</description>
-                  <name>SLAVE_ENABLED</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>Slave mode is disabled</description>
-                  <name>SLAVE_DISABLED</name>
-                  <value>1</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>IC_SLAVE_DISABLE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[5:5]</bitRange>
-              <description>Determines whether RESTART conditions may be sent when acting as a master. Some older slaves do not support handling RESTART conditions; however, RESTART conditions are used in several DW_apb_i2c operations. When RESTART is disabled, the master is prohibited from performing the following functions: - Sending a START BYTE - Performing any high-speed mode operation - High-speed mode operation - Performing direction changes in combined format mode - Performing a read operation with a 10-bit address By replacing RESTART condition followed by a STOP and a subsequent START condition, split operations are broken down into multiple DW_apb_i2c transfers. If the above operations are performed, it will result in setting bit 6 (TX_ABRT) of the IC_RAW_INTR_STAT register.\n\n
-                Reset value: ENABLED</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>Master restart disabled</description>
-                  <name>DISABLED</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>Master restart enabled</description>
-                  <name>ENABLED</name>
-                  <value>1</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>IC_RESTART_EN</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[4:4]</bitRange>
-              <description>Controls whether the DW_apb_i2c starts its transfers in 7- or 10-bit addressing mode when acting as a master. - 0: 7-bit addressing - 1: 10-bit addressing</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>Master 7Bit addressing mode</description>
-                  <name>ADDR_7BITS</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>Master 10Bit addressing mode</description>
-                  <name>ADDR_10BITS</name>
-                  <value>1</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>IC_10BITADDR_MASTER</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[3:3]</bitRange>
-              <description>When acting as a slave, this bit controls whether the DW_apb_i2c responds to 7- or 10-bit addresses. - 0: 7-bit addressing. The DW_apb_i2c ignores transactions that involve 10-bit addressing; for 7-bit addressing, only the lower 7 bits of the IC_SAR register are compared. - 1: 10-bit addressing. The DW_apb_i2c responds to only 10-bit addressing transfers that match the full 10 bits of the IC_SAR register.</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>Slave 7Bit addressing</description>
-                  <name>ADDR_7BITS</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>Slave 10Bit addressing</description>
-                  <name>ADDR_10BITS</name>
-                  <value>1</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>IC_10BITADDR_SLAVE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[2:1]</bitRange>
-              <description>These bits control at which speed the DW_apb_i2c operates; its setting is relevant only if one is operating the DW_apb_i2c in master mode. Hardware protects against illegal values being programmed by software. These bits must be programmed appropriately for slave mode also, as it is used to capture correct value of spike filter as per the speed mode.\n\n
-                This register should be programmed only with a value in the range of 1 to IC_MAX_SPEED_MODE; otherwise, hardware updates this register with the value of IC_MAX_SPEED_MODE.\n\n
-                1: standard mode (100 kbit/s)\n\n
-                2: fast mode (&lt;=400 kbit/s) or fast mode plus (&lt;=1000Kbit/s)\n\n
-                3: high speed mode (3.4 Mbit/s)\n\n
-                Note: This field is not applicable when IC_ULTRA_FAST_MODE=1</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>Standard Speed mode of operation</description>
-                  <name>STANDARD</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>Fast or Fast Plus mode of operation</description>
-                  <name>FAST</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>High Speed mode of operation</description>
-                  <name>HIGH</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>SPEED</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[0:0]</bitRange>
-              <description>This bit controls whether the DW_apb_i2c master is enabled.\n\n
-                NOTE: Software should ensure that if this bit is written with '1' then bit 6 should also be written with a '1'.</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>Master mode is disabled</description>
-                  <name>DISABLED</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>Master mode is enabled</description>
-                  <name>ENABLED</name>
-                  <value>1</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>MASTER_MODE</name>
-            </field>
-          </fields>
-          <name>IC_CON</name>
-          <resetValue>0x00000065</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0004</addressOffset>
-          <description>I2C Target Address Register\n\n
-            This register is 12 bits wide, and bits 31:12 are reserved. This register can be written to only when IC_ENABLE[0] is set to 0.\n\n
-            Note: If the software or application is aware that the DW_apb_i2c is not using the TAR address for the pending commands in the Tx FIFO, then it is possible to update the TAR address even while the Tx FIFO has entries (IC_STATUS[2]= 0). - It is not necessary to perform any write to this register if DW_apb_i2c is enabled as an I2C slave only.</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[11:11]</bitRange>
-              <description>This bit indicates whether software performs a Device-ID or General Call or START BYTE command. - 0: ignore bit 10 GC_OR_START and use IC_TAR normally - 1: perform special I2C command as specified in Device_ID or GC_OR_START bit Reset value: 0x0</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>Disables programming of GENERAL_CALL or START_BYTE transmission</description>
-                  <name>DISABLED</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>Enables programming of GENERAL_CALL or START_BYTE transmission</description>
-                  <name>ENABLED</name>
-                  <value>1</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>SPECIAL</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[10:10]</bitRange>
-              <description>If bit 11 (SPECIAL) is set to 1 and bit 13(Device-ID) is set to 0, then this bit indicates whether a General Call or START byte command is to be performed by the DW_apb_i2c. - 0: General Call Address - after issuing a General Call, only writes may be performed. Attempting to issue a read command results in setting bit 6 (TX_ABRT) of the IC_RAW_INTR_STAT register. The DW_apb_i2c remains in General Call mode until the SPECIAL bit value (bit 11) is cleared. - 1: START BYTE Reset value: 0x0</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>GENERAL_CALL byte transmission</description>
-                  <name>GENERAL_CALL</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>START byte transmission</description>
-                  <name>START_BYTE</name>
-                  <value>1</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>GC_OR_START</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[9:0]</bitRange>
-              <description>This is the target address for any master transaction. When transmitting a General Call, these bits are ignored. To generate a START BYTE, the CPU needs to write only once into these bits.\n\n
-                If the IC_TAR and IC_SAR are the same, loopback exists but the FIFOs are shared between master and slave, so full loopback is not feasible. Only one direction loopback mode is supported (simplex), not duplex. A master cannot transmit to itself; it can transmit to only a slave.</description>
-              <name>IC_TAR</name>
-            </field>
-          </fields>
-          <name>IC_TAR</name>
-          <resetValue>0x00000055</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0008</addressOffset>
-          <description>I2C Slave Address Register</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[9:0]</bitRange>
-              <description>The IC_SAR holds the slave address when the I2C is operating as a slave. For 7-bit addressing, only IC_SAR[6:0] is used.\n\n
-                This register can be written only when the I2C interface is disabled, which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect.\n\n
-                Note: The default values cannot be any of the reserved address locations: that is, 0x00 to 0x07, or 0x78 to 0x7f. The correct operation of the device is not guaranteed if you program the IC_SAR or IC_TAR to a reserved value. Refer to &lt;&lt;table_I2C_firstbyte_bit_defs&gt;&gt; for a complete list of these reserved values.</description>
-              <name>IC_SAR</name>
-            </field>
-          </fields>
-          <name>IC_SAR</name>
-          <resetValue>0x00000055</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0010</addressOffset>
-          <description>I2C Rx/Tx Data Buffer and Command Register; this is the register the CPU writes to when filling the TX FIFO and the CPU reads from when retrieving bytes from RX FIFO.\n\n
-            The size of the register changes as follows:\n\n
-            Write: - 11 bits when IC_EMPTYFIFO_HOLD_MASTER_EN=1 - 9 bits when IC_EMPTYFIFO_HOLD_MASTER_EN=0 Read: - 12 bits when IC_FIRST_DATA_BYTE_STATUS = 1 - 8 bits when IC_FIRST_DATA_BYTE_STATUS = 0 Note: In order for the DW_apb_i2c to continue acknowledging reads, a read command should be written for every byte that is to be received; otherwise the DW_apb_i2c will stop acknowledging.</description>
-          <fields>
-            <field>
-              <access>read-only</access>
-              <bitRange>[11:11]</bitRange>
-              <description>Indicates the first data byte received after the address phase for receive transfer in Master receiver or Slave receiver mode.\n\n
-                Reset value : 0x0\n\n
-                NOTE:  In case of APB_DATA_WIDTH=8,\n\n
-                1. The user has to perform two APB Reads to IC_DATA_CMD in order to get status on 11 bit.\n\n
-                2. In order to read the 11 bit, the user has to perform the first data byte read [7:0] (offset 0x10) and then perform the second read [15:8] (offset 0x11) in order to know the status of 11 bit (whether the data received in previous read is a first data byte or not).\n\n
-                3. The 11th bit is an optional read field, user can ignore 2nd byte read [15:8] (offset 0x11) if not interested in FIRST_DATA_BYTE status.</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>Sequential data byte received</description>
-                  <name>INACTIVE</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>Non sequential data byte received</description>
-                  <name>ACTIVE</name>
-                  <value>1</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>FIRST_DATA_BYTE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[10:10]</bitRange>
-              <description>This bit controls whether a RESTART is issued before the byte is sent or received.\n\n
-                1 - If IC_RESTART_EN is 1, a RESTART is issued before the data is sent/received (according to the value of CMD), regardless of whether or not the transfer direction is changing from the previous command; if IC_RESTART_EN is 0, a STOP followed by a START is issued instead.\n\n
-                0 - If IC_RESTART_EN is 1, a RESTART is issued only if the transfer direction is changing from the previous command; if IC_RESTART_EN is 0, a STOP followed by a START is issued instead.\n\n
-                Reset value: 0x0</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>Don't Issue RESTART before this command</description>
-                  <name>DISABLE</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>Issue RESTART before this command</description>
-                  <name>ENABLE</name>
-                  <value>1</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <modifiedWriteValues>clear</modifiedWriteValues>
-              <name>RESTART</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[9:9]</bitRange>
-              <description>This bit controls whether a STOP is issued after the byte is sent or received.\n\n
-                - 1 - STOP is issued after this byte, regardless of whether or not the Tx FIFO is empty. If the Tx FIFO is not empty, the master immediately tries to start a new transfer by issuing a START and arbitrating for the bus. - 0 - STOP is not issued after this byte, regardless of whether or not the Tx FIFO is empty. If the Tx FIFO is not empty, the master continues the current transfer by sending/receiving data bytes according to the value of the CMD bit. If the Tx FIFO is empty, the master holds the SCL line low and stalls the bus until a new command is available in the Tx FIFO. Reset value: 0x0</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>Don't Issue STOP after this command</description>
-                  <name>DISABLE</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>Issue STOP after this command</description>
-                  <name>ENABLE</name>
-                  <value>1</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <modifiedWriteValues>clear</modifiedWriteValues>
-              <name>STOP</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[8:8]</bitRange>
-              <description>This bit controls whether a read or a write is performed. This bit does not control the direction when the DW_apb_i2con acts as a slave. It controls only the direction when it acts as a master.\n\n
-                When a command is entered in the TX FIFO, this bit distinguishes the write and read commands. In slave-receiver mode, this bit is a 'don't care' because writes to this register are not required. In slave-transmitter mode, a '0' indicates that the data in IC_DATA_CMD is to be transmitted.\n\n
-                When programming this bit, you should remember the following: attempting to perform a read operation after a General Call command has been sent results in a TX_ABRT interrupt (bit 6 of the IC_RAW_INTR_STAT register), unless bit 11 (SPECIAL) in the IC_TAR register has been cleared. If a '1' is written to this bit after receiving a RD_REQ interrupt, then a TX_ABRT interrupt occurs.\n\n
-                Reset value: 0x0</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>Master Write Command</description>
-                  <name>WRITE</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>Master Read Command</description>
-                  <name>READ</name>
-                  <value>1</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <modifiedWriteValues>clear</modifiedWriteValues>
-              <name>CMD</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[7:0]</bitRange>
-              <description>This register contains the data to be transmitted or received on the I2C bus. If you are writing to this register and want to perform a read, bits 7:0 (DAT) are ignored by the DW_apb_i2c. However, when you read this register, these bits return the value of data received on the DW_apb_i2c interface.\n\n
-                Reset value: 0x0</description>
-              <name>DAT</name>
-            </field>
-          </fields>
-          <name>IC_DATA_CMD</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0014</addressOffset>
-          <description>Standard Speed I2C Clock SCL High Count Register</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[15:0]</bitRange>
-              <description>This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock high-period count for standard speed. For more information, refer to 'IC_CLK Frequency Configuration'.\n\n
-                This register can be written only when the I2C interface is disabled which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect.\n\n
-                The minimum valid value is 6; hardware prevents values less than this being written, and if attempted results in 6 being set. For designs with APB_DATA_WIDTH = 8, the order of programming is important to ensure the correct operation of the DW_apb_i2c. The lower byte must be programmed first. Then the upper byte is programmed.\n\n
-                NOTE: This register must not be programmed to a value higher than 65525, because DW_apb_i2c uses a 16-bit counter to flag an I2C bus idle condition when this counter reaches a value of IC_SS_SCL_HCNT + 10.</description>
-              <name>IC_SS_SCL_HCNT</name>
-            </field>
-          </fields>
-          <name>IC_SS_SCL_HCNT</name>
-          <resetValue>0x00000028</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0018</addressOffset>
-          <description>Standard Speed I2C Clock SCL Low Count Register</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[15:0]</bitRange>
-              <description>This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock low period count for standard speed. For more information, refer to 'IC_CLK Frequency Configuration'\n\n
-                This register can be written only when the I2C interface is disabled which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect.\n\n
-                The minimum valid value is 8; hardware prevents values less than this being written, and if attempted, results in 8 being set. For designs with APB_DATA_WIDTH = 8, the order of programming is important to ensure the correct operation of DW_apb_i2c. The lower byte must be programmed first, and then the upper byte is programmed.</description>
-              <name>IC_SS_SCL_LCNT</name>
-            </field>
-          </fields>
-          <name>IC_SS_SCL_LCNT</name>
-          <resetValue>0x0000002f</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x001c</addressOffset>
-          <description>Fast Mode or Fast Mode Plus I2C Clock SCL High Count Register</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[15:0]</bitRange>
-              <description>This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock high-period count for fast mode or fast mode plus. It is used in high-speed mode to send the Master Code and START BYTE or General CALL. For more information, refer to 'IC_CLK Frequency Configuration'.\n\n
-                This register goes away and becomes read-only returning 0s if IC_MAX_SPEED_MODE = standard. This register can be written only when the I2C interface is disabled, which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect.\n\n
-                The minimum valid value is 6; hardware prevents values less than this being written, and if attempted results in 6 being set. For designs with APB_DATA_WIDTH == 8 the order of programming is important to ensure the correct operation of the DW_apb_i2c. The lower byte must be programmed first. Then the upper byte is programmed.</description>
-              <name>IC_FS_SCL_HCNT</name>
-            </field>
-          </fields>
-          <name>IC_FS_SCL_HCNT</name>
-          <resetValue>0x00000006</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0020</addressOffset>
-          <description>Fast Mode or Fast Mode Plus I2C Clock SCL Low Count Register</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[15:0]</bitRange>
-              <description>This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock low period count for fast speed. It is used in high-speed mode to send the Master Code and START BYTE or General CALL. For more information, refer to 'IC_CLK Frequency Configuration'.\n\n
-                This register goes away and becomes read-only returning 0s if IC_MAX_SPEED_MODE = standard.\n\n
-                This register can be written only when the I2C interface is disabled, which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect.\n\n
-                The minimum valid value is 8; hardware prevents values less than this being written, and if attempted results in 8 being set. For designs with APB_DATA_WIDTH = 8 the order of programming is important to ensure the correct operation of the DW_apb_i2c. The lower byte must be programmed first. Then the upper byte is programmed. If the value is less than 8 then the count value gets changed to 8.</description>
-              <name>IC_FS_SCL_LCNT</name>
-            </field>
-          </fields>
-          <name>IC_FS_SCL_LCNT</name>
-          <resetValue>0x0000000d</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x002c</addressOffset>
-          <description>I2C Interrupt Status Register\n\n
-            Each bit in this register has a corresponding mask bit in the IC_INTR_MASK register. These bits are cleared by reading the matching interrupt clear register. The unmasked raw versions of these bits are available in the IC_RAW_INTR_STAT register.</description>
-          <fields>
-            <field>
-              <access>read-only</access>
-              <bitRange>[12:12]</bitRange>
-              <description>See IC_RAW_INTR_STAT for a detailed description of R_RESTART_DET bit.\n\n
-                Reset value: 0x0</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>R_RESTART_DET interrupt is inactive</description>
-                  <name>INACTIVE</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>R_RESTART_DET interrupt is active</description>
-                  <name>ACTIVE</name>
-                  <value>1</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>R_RESTART_DET</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[11:11]</bitRange>
-              <description>See IC_RAW_INTR_STAT for a detailed description of R_GEN_CALL bit.\n\n
-                Reset value: 0x0</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>R_GEN_CALL interrupt is inactive</description>
-                  <name>INACTIVE</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>R_GEN_CALL interrupt is active</description>
-                  <name>ACTIVE</name>
-                  <value>1</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>R_GEN_CALL</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[10:10]</bitRange>
-              <description>See IC_RAW_INTR_STAT for a detailed description of R_START_DET bit.\n\n
-                Reset value: 0x0</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>R_START_DET interrupt is inactive</description>
-                  <name>INACTIVE</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>R_START_DET interrupt is active</description>
-                  <name>ACTIVE</name>
-                  <value>1</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>R_START_DET</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[9:9]</bitRange>
-              <description>See IC_RAW_INTR_STAT for a detailed description of R_STOP_DET bit.\n\n
-                Reset value: 0x0</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>R_STOP_DET interrupt is inactive</description>
-                  <name>INACTIVE</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>R_STOP_DET interrupt is active</description>
-                  <name>ACTIVE</name>
-                  <value>1</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>R_STOP_DET</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[8:8]</bitRange>
-              <description>See IC_RAW_INTR_STAT for a detailed description of R_ACTIVITY bit.\n\n
-                Reset value: 0x0</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>R_ACTIVITY interrupt is inactive</description>
-                  <name>INACTIVE</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>R_ACTIVITY interrupt is active</description>
-                  <name>ACTIVE</name>
-                  <value>1</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>R_ACTIVITY</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[7:7]</bitRange>
-              <description>See IC_RAW_INTR_STAT for a detailed description of R_RX_DONE bit.\n\n
-                Reset value: 0x0</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>R_RX_DONE interrupt is inactive</description>
-                  <name>INACTIVE</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>R_RX_DONE interrupt is active</description>
-                  <name>ACTIVE</name>
-                  <value>1</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>R_RX_DONE</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[6:6]</bitRange>
-              <description>See IC_RAW_INTR_STAT for a detailed description of R_TX_ABRT bit.\n\n
-                Reset value: 0x0</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>R_TX_ABRT interrupt is inactive</description>
-                  <name>INACTIVE</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>R_TX_ABRT interrupt is active</description>
-                  <name>ACTIVE</name>
-                  <value>1</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>R_TX_ABRT</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[5:5]</bitRange>
-              <description>See IC_RAW_INTR_STAT for a detailed description of R_RD_REQ bit.\n\n
-                Reset value: 0x0</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>R_RD_REQ interrupt is inactive</description>
-                  <name>INACTIVE</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>R_RD_REQ interrupt is active</description>
-                  <name>ACTIVE</name>
-                  <value>1</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>R_RD_REQ</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[4:4]</bitRange>
-              <description>See IC_RAW_INTR_STAT for a detailed description of R_TX_EMPTY bit.\n\n
-                Reset value: 0x0</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>R_TX_EMPTY interrupt is inactive</description>
-                  <name>INACTIVE</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>R_TX_EMPTY interrupt is active</description>
-                  <name>ACTIVE</name>
-                  <value>1</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>R_TX_EMPTY</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[3:3]</bitRange>
-              <description>See IC_RAW_INTR_STAT for a detailed description of R_TX_OVER bit.\n\n
-                Reset value: 0x0</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>R_TX_OVER interrupt is inactive</description>
-                  <name>INACTIVE</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>R_TX_OVER interrupt is active</description>
-                  <name>ACTIVE</name>
-                  <value>1</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>R_TX_OVER</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[2:2]</bitRange>
-              <description>See IC_RAW_INTR_STAT for a detailed description of R_RX_FULL bit.\n\n
-                Reset value: 0x0</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>R_RX_FULL interrupt is inactive</description>
-                  <name>INACTIVE</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>R_RX_FULL interrupt is active</description>
-                  <name>ACTIVE</name>
-                  <value>1</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>R_RX_FULL</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[1:1]</bitRange>
-              <description>See IC_RAW_INTR_STAT for a detailed description of R_RX_OVER bit.\n\n
-                Reset value: 0x0</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>R_RX_OVER interrupt is inactive</description>
-                  <name>INACTIVE</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>R_RX_OVER interrupt is active</description>
-                  <name>ACTIVE</name>
-                  <value>1</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>R_RX_OVER</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[0:0]</bitRange>
-              <description>See IC_RAW_INTR_STAT for a detailed description of R_RX_UNDER bit.\n\n
-                Reset value: 0x0</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>RX_UNDER interrupt is inactive</description>
-                  <name>INACTIVE</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>RX_UNDER interrupt is active</description>
-                  <name>ACTIVE</name>
-                  <value>1</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>R_RX_UNDER</name>
-            </field>
-          </fields>
-          <name>IC_INTR_STAT</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0030</addressOffset>
-          <description>I2C Interrupt Mask Register.\n\n
-            These bits mask their corresponding interrupt status bits. This register is active low; a value of 0 masks the interrupt, whereas a value of 1 unmasks the interrupt.</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[12:12]</bitRange>
-              <description>This bit masks the R_RESTART_DET interrupt in IC_INTR_STAT register.\n\n
-                Reset value: 0x0</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>RESTART_DET interrupt is masked</description>
-                  <name>ENABLED</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>RESTART_DET interrupt is unmasked</description>
-                  <name>DISABLED</name>
-                  <value>1</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>M_RESTART_DET</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[11:11]</bitRange>
-              <description>This bit masks the R_GEN_CALL interrupt in IC_INTR_STAT register.\n\n
-                Reset value: 0x1</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>GEN_CALL interrupt is masked</description>
-                  <name>ENABLED</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>GEN_CALL interrupt is unmasked</description>
-                  <name>DISABLED</name>
-                  <value>1</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>M_GEN_CALL</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[10:10]</bitRange>
-              <description>This bit masks the R_START_DET interrupt in IC_INTR_STAT register.\n\n
-                Reset value: 0x0</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>START_DET interrupt is masked</description>
-                  <name>ENABLED</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>START_DET interrupt is unmasked</description>
-                  <name>DISABLED</name>
-                  <value>1</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>M_START_DET</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[9:9]</bitRange>
-              <description>This bit masks the R_STOP_DET interrupt in IC_INTR_STAT register.\n\n
-                Reset value: 0x0</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>STOP_DET interrupt is masked</description>
-                  <name>ENABLED</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>STOP_DET interrupt is unmasked</description>
-                  <name>DISABLED</name>
-                  <value>1</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>M_STOP_DET</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[8:8]</bitRange>
-              <description>This bit masks the R_ACTIVITY interrupt in IC_INTR_STAT register.\n\n
-                Reset value: 0x0</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>ACTIVITY interrupt is masked</description>
-                  <name>ENABLED</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>ACTIVITY interrupt is unmasked</description>
-                  <name>DISABLED</name>
-                  <value>1</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>M_ACTIVITY</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[7:7]</bitRange>
-              <description>This bit masks the R_RX_DONE interrupt in IC_INTR_STAT register.\n\n
-                Reset value: 0x1</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>RX_DONE interrupt is masked</description>
-                  <name>ENABLED</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>RX_DONE interrupt is unmasked</description>
-                  <name>DISABLED</name>
-                  <value>1</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>M_RX_DONE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[6:6]</bitRange>
-              <description>This bit masks the R_TX_ABRT interrupt in IC_INTR_STAT register.\n\n
-                Reset value: 0x1</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>TX_ABORT interrupt is masked</description>
-                  <name>ENABLED</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>TX_ABORT interrupt is unmasked</description>
-                  <name>DISABLED</name>
-                  <value>1</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>M_TX_ABRT</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[5:5]</bitRange>
-              <description>This bit masks the R_RD_REQ interrupt in IC_INTR_STAT register.\n\n
-                Reset value: 0x1</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>RD_REQ interrupt is masked</description>
-                  <name>ENABLED</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>RD_REQ interrupt is unmasked</description>
-                  <name>DISABLED</name>
-                  <value>1</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>M_RD_REQ</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[4:4]</bitRange>
-              <description>This bit masks the R_TX_EMPTY interrupt in IC_INTR_STAT register.\n\n
-                Reset value: 0x1</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>TX_EMPTY interrupt is masked</description>
-                  <name>ENABLED</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>TX_EMPTY interrupt is unmasked</description>
-                  <name>DISABLED</name>
-                  <value>1</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>M_TX_EMPTY</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[3:3]</bitRange>
-              <description>This bit masks the R_TX_OVER interrupt in IC_INTR_STAT register.\n\n
-                Reset value: 0x1</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>TX_OVER interrupt is masked</description>
-                  <name>ENABLED</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>TX_OVER interrupt is unmasked</description>
-                  <name>DISABLED</name>
-                  <value>1</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>M_TX_OVER</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[2:2]</bitRange>
-              <description>This bit masks the R_RX_FULL interrupt in IC_INTR_STAT register.\n\n
-                Reset value: 0x1</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>RX_FULL interrupt is masked</description>
-                  <name>ENABLED</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>RX_FULL interrupt is unmasked</description>
-                  <name>DISABLED</name>
-                  <value>1</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>M_RX_FULL</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[1:1]</bitRange>
-              <description>This bit masks the R_RX_OVER interrupt in IC_INTR_STAT register.\n\n
-                Reset value: 0x1</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>RX_OVER interrupt is masked</description>
-                  <name>ENABLED</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>RX_OVER interrupt is unmasked</description>
-                  <name>DISABLED</name>
-                  <value>1</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>M_RX_OVER</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[0:0]</bitRange>
-              <description>This bit masks the R_RX_UNDER interrupt in IC_INTR_STAT register.\n\n
-                Reset value: 0x1</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>RX_UNDER interrupt is masked</description>
-                  <name>ENABLED</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>RX_UNDER interrupt is unmasked</description>
-                  <name>DISABLED</name>
-                  <value>1</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>M_RX_UNDER</name>
-            </field>
-          </fields>
-          <name>IC_INTR_MASK</name>
-          <resetValue>0x000008ff</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0034</addressOffset>
-          <description>I2C Raw Interrupt Status Register\n\n
-            Unlike the IC_INTR_STAT register, these bits are not masked so they always show the true status of the DW_apb_i2c.</description>
-          <fields>
-            <field>
-              <access>read-only</access>
-              <bitRange>[12:12]</bitRange>
-              <description>Indicates whether a RESTART condition has occurred on the I2C interface when DW_apb_i2c is operating in Slave mode and the slave is being addressed. Enabled only when IC_SLV_RESTART_DET_EN=1.\n\n
-                Note: However, in high-speed mode or during a START BYTE transfer, the RESTART comes before the address field as per the I2C protocol. In this case, the slave is not the addressed slave when the RESTART is issued, therefore DW_apb_i2c does not generate the RESTART_DET interrupt.\n\n
-                Reset value: 0x0</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>RESTART_DET interrupt is inactive</description>
-                  <name>INACTIVE</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>RESTART_DET interrupt is active</description>
-                  <name>ACTIVE</name>
-                  <value>1</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>RESTART_DET</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[11:11]</bitRange>
-              <description>Set only when a General Call address is received and it is acknowledged. It stays set until it is cleared either by disabling DW_apb_i2c or when the CPU reads bit 0 of the IC_CLR_GEN_CALL register. DW_apb_i2c stores the received data in the Rx buffer.\n\n
-                Reset value: 0x0</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>GEN_CALL interrupt is inactive</description>
-                  <name>INACTIVE</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>GEN_CALL interrupt is active</description>
-                  <name>ACTIVE</name>
-                  <value>1</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>GEN_CALL</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[10:10]</bitRange>
-              <description>Indicates whether a START or RESTART condition has occurred on the I2C interface regardless of whether DW_apb_i2c is operating in slave or master mode.\n\n
-                Reset value: 0x0</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>START_DET interrupt is inactive</description>
-                  <name>INACTIVE</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>START_DET interrupt is active</description>
-                  <name>ACTIVE</name>
-                  <value>1</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>START_DET</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[9:9]</bitRange>
-              <description>Indicates whether a STOP condition has occurred on the I2C interface regardless of whether DW_apb_i2c is operating in slave or master mode.\n\n
-                In Slave Mode: - If IC_CON[7]=1'b1  (STOP_DET_IFADDRESSED), the STOP_DET interrupt will be issued only if slave is addressed. Note: During a general call address, this slave does not issue a STOP_DET interrupt if STOP_DET_IF_ADDRESSED=1'b1, even if the slave responds to the general call address by generating ACK. The STOP_DET interrupt is generated only when the transmitted address matches the slave address (SAR). - If IC_CON[7]=1'b0 (STOP_DET_IFADDRESSED), the STOP_DET interrupt is issued irrespective of whether it is being addressed. In Master Mode: - If IC_CON[10]=1'b1  (STOP_DET_IF_MASTER_ACTIVE),the STOP_DET interrupt will be issued only if Master is active. - If IC_CON[10]=1'b0  (STOP_DET_IFADDRESSED),the STOP_DET interrupt will be issued irrespective of whether master is active or not. Reset value: 0x0</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>STOP_DET interrupt is inactive</description>
-                  <name>INACTIVE</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>STOP_DET interrupt is active</description>
-                  <name>ACTIVE</name>
-                  <value>1</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>STOP_DET</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[8:8]</bitRange>
-              <description>This bit captures DW_apb_i2c activity and stays set until it is cleared. There are four ways to clear it: - Disabling the DW_apb_i2c - Reading the IC_CLR_ACTIVITY register - Reading the IC_CLR_INTR register - System reset Once this bit is set, it stays set unless one of the four methods is used to clear it. Even if the DW_apb_i2c module is idle, this bit remains set until cleared, indicating that there was activity on the bus.\n\n
-                Reset value: 0x0</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>RAW_INTR_ACTIVITY interrupt is inactive</description>
-                  <name>INACTIVE</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>RAW_INTR_ACTIVITY interrupt is active</description>
-                  <name>ACTIVE</name>
-                  <value>1</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>ACTIVITY</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[7:7]</bitRange>
-              <description>When the DW_apb_i2c is acting as a slave-transmitter, this bit is set to 1 if the master does not acknowledge a transmitted byte. This occurs on the last byte of the transmission, indicating that the transmission is done.\n\n
-                Reset value: 0x0</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>RX_DONE interrupt is inactive</description>
-                  <name>INACTIVE</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>RX_DONE interrupt is active</description>
-                  <name>ACTIVE</name>
-                  <value>1</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>RX_DONE</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[6:6]</bitRange>
-              <description>This bit indicates if DW_apb_i2c, as an I2C transmitter, is unable to complete the intended actions on the contents of the transmit FIFO. This situation can occur both as an I2C master or an I2C slave, and is referred to as a 'transmit abort'. When this bit is set to 1, the IC_TX_ABRT_SOURCE register indicates the reason why the transmit abort takes places.\n\n
-                Note:  The DW_apb_i2c flushes/resets/empties the TX_FIFO and RX_FIFO whenever there is a transmit abort caused by any of the events tracked by the IC_TX_ABRT_SOURCE register. The FIFOs remains in this flushed state until the register IC_CLR_TX_ABRT is read. Once this read is performed, the Tx FIFO is then ready to accept more data bytes from the APB interface.\n\n
-                Reset value: 0x0</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>TX_ABRT interrupt is inactive</description>
-                  <name>INACTIVE</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>TX_ABRT interrupt is active</description>
-                  <name>ACTIVE</name>
-                  <value>1</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>TX_ABRT</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[5:5]</bitRange>
-              <description>This bit is set to 1 when DW_apb_i2c is acting as a slave and another I2C master is attempting to read data from DW_apb_i2c. The DW_apb_i2c holds the I2C bus in a wait state (SCL=0) until this interrupt is serviced, which means that the slave has been addressed by a remote master that is asking for data to be transferred. The processor must respond to this interrupt and then write the requested data to the IC_DATA_CMD register. This bit is set to 0 just after the processor reads the IC_CLR_RD_REQ register.\n\n
-                Reset value: 0x0</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>RD_REQ interrupt is inactive</description>
-                  <name>INACTIVE</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>RD_REQ interrupt is active</description>
-                  <name>ACTIVE</name>
-                  <value>1</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>RD_REQ</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[4:4]</bitRange>
-              <description>The behavior of the TX_EMPTY interrupt status differs based on the TX_EMPTY_CTRL selection in the IC_CON register. - When TX_EMPTY_CTRL = 0: This bit is set to 1 when the transmit buffer is at or below the threshold value set in the IC_TX_TL register. - When TX_EMPTY_CTRL = 1: This bit is set to 1 when the transmit buffer is at or below the threshold value set in the IC_TX_TL register and the transmission of the address/data from the internal shift register for the most recently popped command is completed. It is automatically cleared by hardware when the buffer level goes above the threshold. When IC_ENABLE[0] is set to 0, the TX FIFO is flushed and held in reset. There the TX FIFO looks like it has no data within it, so this bit is set to 1, provided there is activity in the master or slave state machines. When there is no longer any activity, then with ic_en=0, this bit is set to 0.\n\n
-                Reset value: 0x0.</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>TX_EMPTY interrupt is inactive</description>
-                  <name>INACTIVE</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>TX_EMPTY interrupt is active</description>
-                  <name>ACTIVE</name>
-                  <value>1</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>TX_EMPTY</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[3:3]</bitRange>
-              <description>Set during transmit if the transmit buffer is filled to IC_TX_BUFFER_DEPTH and the processor attempts to issue another I2C command by writing to the IC_DATA_CMD register. When the module is disabled, this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared.\n\n
-                Reset value: 0x0</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>TX_OVER interrupt is inactive</description>
-                  <name>INACTIVE</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>TX_OVER interrupt is active</description>
-                  <name>ACTIVE</name>
-                  <value>1</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>TX_OVER</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[2:2]</bitRange>
-              <description>Set when the receive buffer reaches or goes above the RX_TL threshold in the IC_RX_TL register. It is automatically cleared by hardware when buffer level goes below the threshold. If the module is disabled (IC_ENABLE[0]=0), the RX FIFO is flushed and held in reset; therefore the RX FIFO is not full. So this bit is cleared once the IC_ENABLE bit 0 is programmed with a 0, regardless of the activity that continues.\n\n
-                Reset value: 0x0</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>RX_FULL interrupt is inactive</description>
-                  <name>INACTIVE</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>RX_FULL interrupt is active</description>
-                  <name>ACTIVE</name>
-                  <value>1</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>RX_FULL</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[1:1]</bitRange>
-              <description>Set if the receive buffer is completely filled to IC_RX_BUFFER_DEPTH and an additional byte is received from an external I2C device. The DW_apb_i2c acknowledges this, but any data bytes received after the FIFO is full are lost. If the module is disabled (IC_ENABLE[0]=0), this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared.\n\n
-                Note:  If bit 9 of the IC_CON register (RX_FIFO_FULL_HLD_CTRL) is programmed to HIGH, then the RX_OVER interrupt never occurs, because the Rx FIFO never overflows.\n\n
-                Reset value: 0x0</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>RX_OVER interrupt is inactive</description>
-                  <name>INACTIVE</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>RX_OVER interrupt is active</description>
-                  <name>ACTIVE</name>
-                  <value>1</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>RX_OVER</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[0:0]</bitRange>
-              <description>Set if the processor attempts to read the receive buffer when it is empty by reading from the IC_DATA_CMD register. If the module is disabled (IC_ENABLE[0]=0), this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared.\n\n
-                Reset value: 0x0</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>RX_UNDER interrupt is inactive</description>
-                  <name>INACTIVE</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>RX_UNDER interrupt is active</description>
-                  <name>ACTIVE</name>
-                  <value>1</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>RX_UNDER</name>
-            </field>
-          </fields>
-          <name>IC_RAW_INTR_STAT</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0038</addressOffset>
-          <description>I2C Receive FIFO Threshold Register</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[7:0]</bitRange>
-              <description>Receive FIFO Threshold Level.\n\n
-                Controls the level of entries (or above) that triggers the RX_FULL interrupt (bit 2 in IC_RAW_INTR_STAT register). The valid range is 0-255, with the additional restriction that hardware does not allow this value to be set to a value larger than the depth of the buffer. If an attempt is made to do that, the actual value set will be the maximum depth of the buffer. A value of 0 sets the threshold for 1 entry, and a value of 255 sets the threshold for 256 entries.</description>
-              <name>RX_TL</name>
-            </field>
-          </fields>
-          <name>IC_RX_TL</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x003c</addressOffset>
-          <description>I2C Transmit FIFO Threshold Register</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[7:0]</bitRange>
-              <description>Transmit FIFO Threshold Level.\n\n
-                Controls the level of entries (or below) that trigger the TX_EMPTY interrupt (bit 4 in IC_RAW_INTR_STAT register). The valid range is 0-255, with the additional restriction that it may not be set to value larger than the depth of the buffer. If an attempt is made to do that, the actual value set will be the maximum depth of the buffer. A value of 0 sets the threshold for 0 entries, and a value of 255 sets the threshold for 255 entries.</description>
-              <name>TX_TL</name>
-            </field>
-          </fields>
-          <name>IC_TX_TL</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0040</addressOffset>
-          <description>Clear Combined and Individual Interrupt Register</description>
-          <fields>
-            <field>
-              <access>read-only</access>
-              <bitRange>[0:0]</bitRange>
-              <description>Read this register to clear the combined interrupt, all individual interrupts, and the IC_TX_ABRT_SOURCE register. This bit does not clear hardware clearable interrupts but software clearable interrupts. Refer to Bit 9 of the IC_TX_ABRT_SOURCE register for an exception to clearing IC_TX_ABRT_SOURCE.\n\n
-                Reset value: 0x0</description>
-              <name>CLR_INTR</name>
-            </field>
-          </fields>
-          <name>IC_CLR_INTR</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0044</addressOffset>
-          <description>Clear RX_UNDER Interrupt Register</description>
-          <fields>
-            <field>
-              <access>read-only</access>
-              <bitRange>[0:0]</bitRange>
-              <description>Read this register to clear the RX_UNDER interrupt (bit 0) of the IC_RAW_INTR_STAT register.\n\n
-                Reset value: 0x0</description>
-              <name>CLR_RX_UNDER</name>
-            </field>
-          </fields>
-          <name>IC_CLR_RX_UNDER</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0048</addressOffset>
-          <description>Clear RX_OVER Interrupt Register</description>
-          <fields>
-            <field>
-              <access>read-only</access>
-              <bitRange>[0:0]</bitRange>
-              <description>Read this register to clear the RX_OVER interrupt (bit 1) of the IC_RAW_INTR_STAT register.\n\n
-                Reset value: 0x0</description>
-              <name>CLR_RX_OVER</name>
-            </field>
-          </fields>
-          <name>IC_CLR_RX_OVER</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x004c</addressOffset>
-          <description>Clear TX_OVER Interrupt Register</description>
-          <fields>
-            <field>
-              <access>read-only</access>
-              <bitRange>[0:0]</bitRange>
-              <description>Read this register to clear the TX_OVER interrupt (bit 3) of the IC_RAW_INTR_STAT register.\n\n
-                Reset value: 0x0</description>
-              <name>CLR_TX_OVER</name>
-            </field>
-          </fields>
-          <name>IC_CLR_TX_OVER</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0050</addressOffset>
-          <description>Clear RD_REQ Interrupt Register</description>
-          <fields>
-            <field>
-              <access>read-only</access>
-              <bitRange>[0:0]</bitRange>
-              <description>Read this register to clear the RD_REQ interrupt (bit 5) of the IC_RAW_INTR_STAT register.\n\n
-                Reset value: 0x0</description>
-              <name>CLR_RD_REQ</name>
-            </field>
-          </fields>
-          <name>IC_CLR_RD_REQ</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0054</addressOffset>
-          <description>Clear TX_ABRT Interrupt Register</description>
-          <fields>
-            <field>
-              <access>read-only</access>
-              <bitRange>[0:0]</bitRange>
-              <description>Read this register to clear the TX_ABRT interrupt (bit 6) of the IC_RAW_INTR_STAT register, and the IC_TX_ABRT_SOURCE register. This also releases the TX FIFO from the flushed/reset state, allowing more writes to the TX FIFO. Refer to Bit 9 of the IC_TX_ABRT_SOURCE register for an exception to clearing IC_TX_ABRT_SOURCE.\n\n
-                Reset value: 0x0</description>
-              <name>CLR_TX_ABRT</name>
-            </field>
-          </fields>
-          <name>IC_CLR_TX_ABRT</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0058</addressOffset>
-          <description>Clear RX_DONE Interrupt Register</description>
-          <fields>
-            <field>
-              <access>read-only</access>
-              <bitRange>[0:0]</bitRange>
-              <description>Read this register to clear the RX_DONE interrupt (bit 7) of the IC_RAW_INTR_STAT register.\n\n
-                Reset value: 0x0</description>
-              <name>CLR_RX_DONE</name>
-            </field>
-          </fields>
-          <name>IC_CLR_RX_DONE</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x005c</addressOffset>
-          <description>Clear ACTIVITY Interrupt Register</description>
-          <fields>
-            <field>
-              <access>read-only</access>
-              <bitRange>[0:0]</bitRange>
-              <description>Reading this register clears the ACTIVITY interrupt if the I2C is not active anymore. If the I2C module is still active on the bus, the ACTIVITY interrupt bit continues to be set. It is automatically cleared by hardware if the module is disabled and if there is no further activity on the bus. The value read from this register to get status of the ACTIVITY interrupt (bit 8) of the IC_RAW_INTR_STAT register.\n\n
-                Reset value: 0x0</description>
-              <name>CLR_ACTIVITY</name>
-            </field>
-          </fields>
-          <name>IC_CLR_ACTIVITY</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0060</addressOffset>
-          <description>Clear STOP_DET Interrupt Register</description>
-          <fields>
-            <field>
-              <access>read-only</access>
-              <bitRange>[0:0]</bitRange>
-              <description>Read this register to clear the STOP_DET interrupt (bit 9) of the IC_RAW_INTR_STAT register.\n\n
-                Reset value: 0x0</description>
-              <name>CLR_STOP_DET</name>
-            </field>
-          </fields>
-          <name>IC_CLR_STOP_DET</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0064</addressOffset>
-          <description>Clear START_DET Interrupt Register</description>
-          <fields>
-            <field>
-              <access>read-only</access>
-              <bitRange>[0:0]</bitRange>
-              <description>Read this register to clear the START_DET interrupt (bit 10) of the IC_RAW_INTR_STAT register.\n\n
-                Reset value: 0x0</description>
-              <name>CLR_START_DET</name>
-            </field>
-          </fields>
-          <name>IC_CLR_START_DET</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0068</addressOffset>
-          <description>Clear GEN_CALL Interrupt Register</description>
-          <fields>
-            <field>
-              <access>read-only</access>
-              <bitRange>[0:0]</bitRange>
-              <description>Read this register to clear the GEN_CALL interrupt (bit 11) of IC_RAW_INTR_STAT register.\n\n
-                Reset value: 0x0</description>
-              <name>CLR_GEN_CALL</name>
-            </field>
-          </fields>
-          <name>IC_CLR_GEN_CALL</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x006c</addressOffset>
-          <description>I2C Enable Register</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[2:2]</bitRange>
-              <description>In Master mode: - 1'b1: Blocks the transmission of data on I2C bus even if Tx FIFO has data to transmit. - 1'b0: The transmission of data starts on I2C bus automatically, as soon as the first data is available in the Tx FIFO. Note: To block the execution of Master commands, set the TX_CMD_BLOCK bit only when Tx FIFO is empty (IC_STATUS[2]==1) and Master is in Idle state (IC_STATUS[5] == 0). Any further commands put in the Tx FIFO are not executed until TX_CMD_BLOCK bit is unset. Reset value:  IC_TX_CMD_BLOCK_DEFAULT</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>Tx Command execution not blocked</description>
-                  <name>NOT_BLOCKED</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>Tx Command execution blocked</description>
-                  <name>BLOCKED</name>
-                  <value>1</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>TX_CMD_BLOCK</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[1:1]</bitRange>
-              <description>When set, the controller initiates the transfer abort. - 0: ABORT not initiated or ABORT done - 1: ABORT operation in progress The software can abort the I2C transfer in master mode by setting this bit. The software can set this bit only when ENABLE is already set; otherwise, the controller ignores any write to ABORT bit. The software cannot clear the ABORT bit once set. In response to an ABORT, the controller issues a STOP and flushes the Tx FIFO after completing the current transfer, then sets the TX_ABORT interrupt after the abort operation. The ABORT bit is cleared automatically after the abort operation.\n\n
-                For a detailed description on how to abort I2C transfers, refer to 'Aborting I2C Transfers'.\n\n
-                Reset value: 0x0</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>ABORT operation not in progress</description>
-                  <name>DISABLE</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>ABORT operation in progress</description>
-                  <name>ENABLED</name>
-                  <value>1</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>ABORT</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[0:0]</bitRange>
-              <description>Controls whether the DW_apb_i2c is enabled. - 0: Disables DW_apb_i2c (TX and RX FIFOs are held in an erased state) - 1: Enables DW_apb_i2c Software can disable DW_apb_i2c while it is active. However, it is important that care be taken to ensure that DW_apb_i2c is disabled properly. A recommended procedure is described in 'Disabling DW_apb_i2c'.\n\n
-                When DW_apb_i2c is disabled, the following occurs: - The TX FIFO and RX FIFO get flushed. - Status bits in the IC_INTR_STAT register are still active until DW_apb_i2c goes into IDLE state. If the module is transmitting, it stops as well as deletes the contents of the transmit buffer after the current transfer is complete. If the module is receiving, the DW_apb_i2c stops the current transfer at the end of the current byte and does not acknowledge the transfer.\n\n
-                In systems with asynchronous pclk and ic_clk when IC_CLK_TYPE parameter set to asynchronous (1), there is a two ic_clk delay when enabling or disabling the DW_apb_i2c. For a detailed description on how to disable DW_apb_i2c, refer to 'Disabling DW_apb_i2c'\n\n
-                Reset value: 0x0</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>I2C is disabled</description>
-                  <name>DISABLED</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>I2C is enabled</description>
-                  <name>ENABLED</name>
-                  <value>1</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>ENABLE</name>
-            </field>
-          </fields>
-          <name>IC_ENABLE</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0070</addressOffset>
-          <description>I2C Status Register\n\n
-            This is a read-only register used to indicate the current transfer status and FIFO status. The status register may be read at any time. None of the bits in this register request an interrupt.\n\n
-            When the I2C is disabled by writing 0 in bit 0 of the IC_ENABLE register: - Bits 1 and 2 are set to 1 - Bits 3 and 10 are set to 0 When the master or slave state machines goes to idle and ic_en=0: - Bits 5 and 6 are set to 0</description>
-          <fields>
-            <field>
-              <access>read-only</access>
-              <bitRange>[6:6]</bitRange>
-              <description>Slave FSM Activity Status. When the Slave Finite State Machine (FSM) is not in the IDLE state, this bit is set. - 0: Slave FSM is in IDLE state so the Slave part of DW_apb_i2c is not Active - 1: Slave FSM is not in IDLE state so the Slave part of DW_apb_i2c is Active Reset value: 0x0</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>Slave is idle</description>
-                  <name>IDLE</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>Slave not idle</description>
-                  <name>ACTIVE</name>
-                  <value>1</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>SLV_ACTIVITY</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[5:5]</bitRange>
-              <description>Master FSM Activity Status. When the Master Finite State Machine (FSM) is not in the IDLE state, this bit is set. - 0: Master FSM is in IDLE state so the Master part of DW_apb_i2c is not Active - 1: Master FSM is not in IDLE state so the Master part of DW_apb_i2c is Active Note: IC_STATUS[0]-that is, ACTIVITY bit-is the OR of SLV_ACTIVITY and MST_ACTIVITY bits.\n\n
-                Reset value: 0x0</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>Master is idle</description>
-                  <name>IDLE</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>Master not idle</description>
-                  <name>ACTIVE</name>
-                  <value>1</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>MST_ACTIVITY</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[4:4]</bitRange>
-              <description>Receive FIFO Completely Full. When the receive FIFO is completely full, this bit is set. When the receive FIFO contains one or more empty location, this bit is cleared. - 0: Receive FIFO is not full - 1: Receive FIFO is full Reset value: 0x0</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>Rx FIFO not full</description>
-                  <name>NOT_FULL</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>Rx FIFO is full</description>
-                  <name>FULL</name>
-                  <value>1</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>RFF</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[3:3]</bitRange>
-              <description>Receive FIFO Not Empty. This bit is set when the receive FIFO contains one or more entries; it is cleared when the receive FIFO is empty. - 0: Receive FIFO is empty - 1: Receive FIFO is not empty Reset value: 0x0</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>Rx FIFO is empty</description>
-                  <name>EMPTY</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>Rx FIFO not empty</description>
-                  <name>NOT_EMPTY</name>
-                  <value>1</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>RFNE</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[2:2]</bitRange>
-              <description>Transmit FIFO Completely Empty. When the transmit FIFO is completely empty, this bit is set. When it contains one or more valid entries, this bit is cleared. This bit field does not request an interrupt. - 0: Transmit FIFO is not empty - 1: Transmit FIFO is empty Reset value: 0x1</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>Tx FIFO not empty</description>
-                  <name>NON_EMPTY</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>Tx FIFO is empty</description>
-                  <name>EMPTY</name>
-                  <value>1</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>TFE</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[1:1]</bitRange>
-              <description>Transmit FIFO Not Full. Set when the transmit FIFO contains one or more empty locations, and is cleared when the FIFO is full. - 0: Transmit FIFO is full - 1: Transmit FIFO is not full Reset value: 0x1</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>Tx FIFO is full</description>
-                  <name>FULL</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>Tx FIFO not full</description>
-                  <name>NOT_FULL</name>
-                  <value>1</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>TFNF</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[0:0]</bitRange>
-              <description>I2C Activity Status. Reset value: 0x0</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>I2C is idle</description>
-                  <name>INACTIVE</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>I2C is active</description>
-                  <name>ACTIVE</name>
-                  <value>1</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>ACTIVITY</name>
-            </field>
-          </fields>
-          <name>IC_STATUS</name>
-          <resetValue>0x00000006</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0074</addressOffset>
-          <description>I2C Transmit FIFO Level Register This register contains the number of valid data entries in the transmit FIFO buffer. It is cleared whenever: - The I2C is disabled - There is a transmit abort - that is, TX_ABRT bit is set in the IC_RAW_INTR_STAT register - The slave bulk transmit mode is aborted The register increments whenever data is placed into the transmit FIFO and decrements when data is taken from the transmit FIFO.</description>
-          <fields>
-            <field>
-              <access>read-only</access>
-              <bitRange>[4:0]</bitRange>
-              <description>Transmit FIFO Level. Contains the number of valid data entries in the transmit FIFO.\n\n
-                Reset value: 0x0</description>
-              <name>TXFLR</name>
-            </field>
-          </fields>
-          <name>IC_TXFLR</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0078</addressOffset>
-          <description>I2C Receive FIFO Level Register This register contains the number of valid data entries in the receive FIFO buffer. It is cleared whenever: - The I2C is disabled - Whenever there is a transmit abort caused by any of the events tracked in IC_TX_ABRT_SOURCE The register increments whenever data is placed into the receive FIFO and decrements when data is taken from the receive FIFO.</description>
-          <fields>
-            <field>
-              <access>read-only</access>
-              <bitRange>[4:0]</bitRange>
-              <description>Receive FIFO Level. Contains the number of valid data entries in the receive FIFO.\n\n
-                Reset value: 0x0</description>
-              <name>RXFLR</name>
-            </field>
-          </fields>
-          <name>IC_RXFLR</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x007c</addressOffset>
-          <description>I2C SDA Hold Time Length Register\n\n
-            The bits [15:0] of this register are used to control the hold time of SDA during transmit in both slave and master mode (after SCL goes from HIGH to LOW).\n\n
-            The bits [23:16] of this register are used to extend the SDA transition (if any) whenever SCL is HIGH in the receiver in either master or slave mode.\n\n
-            Writes to this register succeed only when IC_ENABLE[0]=0.\n\n
-            The values in this register are in units of ic_clk period. The value programmed in IC_SDA_TX_HOLD must be greater than the minimum hold time in each mode (one cycle in master mode, seven cycles in slave mode) for the value to be implemented.\n\n
-            The programmed SDA hold time during transmit (IC_SDA_TX_HOLD) cannot exceed at any time the duration of the low part of scl. Therefore the programmed value cannot be larger than N_SCL_LOW-2, where N_SCL_LOW is the duration of the low part of the scl period measured in ic_clk cycles.</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[23:16]</bitRange>
-              <description>Sets the required SDA hold time in units of ic_clk period, when DW_apb_i2c acts as a receiver.\n\n
-                Reset value: IC_DEFAULT_SDA_HOLD[23:16].</description>
-              <name>IC_SDA_RX_HOLD</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[15:0]</bitRange>
-              <description>Sets the required SDA hold time in units of ic_clk period, when DW_apb_i2c acts as a transmitter.\n\n
-                Reset value: IC_DEFAULT_SDA_HOLD[15:0].</description>
-              <name>IC_SDA_TX_HOLD</name>
-            </field>
-          </fields>
-          <name>IC_SDA_HOLD</name>
-          <resetValue>0x00000001</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0080</addressOffset>
-          <description>I2C Transmit Abort Source Register\n\n
-            This register has 32 bits that indicate the source of the TX_ABRT bit. Except for Bit 9, this register is cleared whenever the IC_CLR_TX_ABRT register or the IC_CLR_INTR register is read. To clear Bit 9, the source of the ABRT_SBYTE_NORSTRT must be fixed first; RESTART must be enabled (IC_CON[5]=1), the SPECIAL bit must be cleared (IC_TAR[11]), or the GC_OR_START bit must be cleared (IC_TAR[10]).\n\n
-            Once the source of the ABRT_SBYTE_NORSTRT is fixed, then this bit can be cleared in the same manner as other bits in this register. If the source of the ABRT_SBYTE_NORSTRT is not fixed before attempting to clear this bit, Bit 9 clears for one cycle and is then re-asserted.</description>
-          <fields>
-            <field>
-              <access>read-only</access>
-              <bitRange>[31:23]</bitRange>
-              <description>This field indicates the number of Tx FIFO Data Commands which are flushed due to TX_ABRT interrupt. It is cleared whenever I2C is disabled.\n\n
-                Reset value: 0x0\n\n
-                Role of DW_apb_i2c:  Master-Transmitter or Slave-Transmitter</description>
-              <name>TX_FLUSH_CNT</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[16:16]</bitRange>
-              <description>This is a master-mode-only bit. Master has detected the transfer abort (IC_ENABLE[1])\n\n
-                Reset value: 0x0\n\n
-                Role of DW_apb_i2c:  Master-Transmitter</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>Transfer abort detected by master- scenario not present</description>
-                  <name>ABRT_USER_ABRT_VOID</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>Transfer abort detected by master</description>
-                  <name>ABRT_USER_ABRT_GENERATED</name>
-                  <value>1</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>ABRT_USER_ABRT</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[15:15]</bitRange>
-              <description>1: When the processor side responds to a slave mode request for data to be transmitted to a remote master and user writes a 1 in CMD (bit 8) of IC_DATA_CMD register.\n\n
-                Reset value: 0x0\n\n
-                Role of DW_apb_i2c:  Slave-Transmitter</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>Slave trying to transmit to remote master in read mode- scenario not present</description>
-                  <name>ABRT_SLVRD_INTX_VOID</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>Slave trying to transmit to remote master in read mode</description>
-                  <name>ABRT_SLVRD_INTX_GENERATED</name>
-                  <value>1</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>ABRT_SLVRD_INTX</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[14:14]</bitRange>
-              <description>This field indicates that a Slave has lost the bus while transmitting data to a remote master. IC_TX_ABRT_SOURCE[12] is set at the same time. Note:  Even though the slave never 'owns' the bus, something could go wrong on the bus. This is a fail safe check. For instance, during a data transmission at the low-to-high transition of SCL, if what is on the data bus is not what is supposed to be transmitted, then DW_apb_i2c no longer own the bus.\n\n
-                Reset value: 0x0\n\n
-                Role of DW_apb_i2c:  Slave-Transmitter</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>Slave lost arbitration to remote master- scenario not present</description>
-                  <name>ABRT_SLV_ARBLOST_VOID</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>Slave lost arbitration to remote master</description>
-                  <name>ABRT_SLV_ARBLOST_GENERATED</name>
-                  <value>1</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>ABRT_SLV_ARBLOST</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[13:13]</bitRange>
-              <description>This field specifies that the Slave has received a read command and some data exists in the TX FIFO, so the slave issues a TX_ABRT interrupt to flush old data in TX FIFO.\n\n
-                Reset value: 0x0\n\n
-                Role of DW_apb_i2c:  Slave-Transmitter</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>Slave flushes existing data in TX-FIFO upon getting read command- scenario not present</description>
-                  <name>ABRT_SLVFLUSH_TXFIFO_VOID</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>Slave flushes existing data in TX-FIFO upon getting read command</description>
-                  <name>ABRT_SLVFLUSH_TXFIFO_GENERATED</name>
-                  <value>1</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>ABRT_SLVFLUSH_TXFIFO</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[12:12]</bitRange>
-              <description>This field specifies that the Master has lost arbitration, or if IC_TX_ABRT_SOURCE[14] is also set, then the slave transmitter has lost arbitration.\n\n
-                Reset value: 0x0\n\n
-                Role of DW_apb_i2c:  Master-Transmitter or Slave-Transmitter</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>Master or Slave-Transmitter lost arbitration- scenario not present</description>
-                  <name>ABRT_LOST_VOID</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>Master or Slave-Transmitter lost arbitration</description>
-                  <name>ABRT_LOST_GENERATED</name>
-                  <value>1</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>ARB_LOST</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[11:11]</bitRange>
-              <description>This field indicates that the User tries to initiate a Master operation with the Master mode disabled.\n\n
-                Reset value: 0x0\n\n
-                Role of DW_apb_i2c:  Master-Transmitter or Master-Receiver</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>User initiating master operation when MASTER disabled- scenario not present</description>
-                  <name>ABRT_MASTER_DIS_VOID</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>User initiating master operation when MASTER disabled</description>
-                  <name>ABRT_MASTER_DIS_GENERATED</name>
-                  <value>1</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>ABRT_MASTER_DIS</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[10:10]</bitRange>
-              <description>This field indicates that the restart is disabled (IC_RESTART_EN bit (IC_CON[5]) =0) and the master sends a read command in 10-bit addressing mode.\n\n
-                Reset value: 0x0\n\n
-                Role of DW_apb_i2c:  Master-Receiver</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>Master not trying to read in 10Bit addressing mode when RESTART disabled</description>
-                  <name>ABRT_10B_RD_VOID</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>Master trying to read in 10Bit addressing mode when RESTART disabled</description>
-                  <name>ABRT_10B_RD_GENERATED</name>
-                  <value>1</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>ABRT_10B_RD_NORSTRT</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[9:9]</bitRange>
-              <description>To clear Bit 9, the source of the ABRT_SBYTE_NORSTRT must be fixed first; restart must be enabled (IC_CON[5]=1), the SPECIAL bit must be cleared (IC_TAR[11]), or the GC_OR_START bit must be cleared (IC_TAR[10]). Once the source of the ABRT_SBYTE_NORSTRT is fixed, then this bit can be cleared in the same manner as other bits in this register. If the source of the ABRT_SBYTE_NORSTRT is not fixed before attempting to clear this bit, bit 9 clears for one cycle and then gets reasserted. When this field is set to 1, the restart is disabled (IC_RESTART_EN bit (IC_CON[5]) =0) and the user is trying to send a START Byte.\n\n
-                Reset value: 0x0\n\n
-                Role of DW_apb_i2c:  Master</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>User trying to send START byte when RESTART disabled- scenario not present</description>
-                  <name>ABRT_SBYTE_NORSTRT_VOID</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>User trying to send START byte when RESTART disabled</description>
-                  <name>ABRT_SBYTE_NORSTRT_GENERATED</name>
-                  <value>1</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>ABRT_SBYTE_NORSTRT</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[8:8]</bitRange>
-              <description>This field indicates that the restart is disabled (IC_RESTART_EN bit (IC_CON[5]) =0) and the user is trying to use the master to transfer data in High Speed mode.\n\n
-                Reset value: 0x0\n\n
-                Role of DW_apb_i2c:  Master-Transmitter or Master-Receiver</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>User trying to switch Master to HS mode when RESTART disabled- scenario not present</description>
-                  <name>ABRT_HS_NORSTRT_VOID</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>User trying to switch Master to HS mode when RESTART disabled</description>
-                  <name>ABRT_HS_NORSTRT_GENERATED</name>
-                  <value>1</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>ABRT_HS_NORSTRT</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[7:7]</bitRange>
-              <description>This field indicates that the Master has sent a START Byte and the START Byte was acknowledged (wrong behavior).\n\n
-                Reset value: 0x0\n\n
-                Role of DW_apb_i2c:  Master</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>ACK detected for START byte- scenario not present</description>
-                  <name>ABRT_SBYTE_ACKDET_VOID</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>ACK detected for START byte</description>
-                  <name>ABRT_SBYTE_ACKDET_GENERATED</name>
-                  <value>1</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>ABRT_SBYTE_ACKDET</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[6:6]</bitRange>
-              <description>This field indicates that the Master is in High Speed mode and the High Speed Master code was acknowledged (wrong behavior).\n\n
-                Reset value: 0x0\n\n
-                Role of DW_apb_i2c:  Master</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>HS Master code ACKed in HS Mode- scenario not present</description>
-                  <name>ABRT_HS_ACK_VOID</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>HS Master code ACKed in HS Mode</description>
-                  <name>ABRT_HS_ACK_GENERATED</name>
-                  <value>1</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>ABRT_HS_ACKDET</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[5:5]</bitRange>
-              <description>This field indicates that DW_apb_i2c in the master mode has sent a General Call but the user programmed the byte following the General Call to be a read from the bus (IC_DATA_CMD[9] is set to 1).\n\n
-                Reset value: 0x0\n\n
-                Role of DW_apb_i2c:  Master-Transmitter</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>GCALL is followed by read from bus-scenario not present</description>
-                  <name>ABRT_GCALL_READ_VOID</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>GCALL is followed by read from bus</description>
-                  <name>ABRT_GCALL_READ_GENERATED</name>
-                  <value>1</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>ABRT_GCALL_READ</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[4:4]</bitRange>
-              <description>This field indicates that DW_apb_i2c in master mode has sent a General Call and no slave on the bus acknowledged the General Call.\n\n
-                Reset value: 0x0\n\n
-                Role of DW_apb_i2c:  Master-Transmitter</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>GCALL not ACKed by any slave-scenario not present</description>
-                  <name>ABRT_GCALL_NOACK_VOID</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>GCALL not ACKed by any slave</description>
-                  <name>ABRT_GCALL_NOACK_GENERATED</name>
-                  <value>1</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>ABRT_GCALL_NOACK</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[3:3]</bitRange>
-              <description>This field indicates the master-mode only bit. When the master receives an acknowledgement for the address, but when it sends data byte(s) following the address, it did not receive an acknowledge from the remote slave(s).\n\n
-                Reset value: 0x0\n\n
-                Role of DW_apb_i2c:  Master-Transmitter</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>Transmitted data non-ACKed by addressed slave-scenario not present</description>
-                  <name>ABRT_TXDATA_NOACK_VOID</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>Transmitted data not ACKed by addressed slave</description>
-                  <name>ABRT_TXDATA_NOACK_GENERATED</name>
-                  <value>1</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>ABRT_TXDATA_NOACK</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[2:2]</bitRange>
-              <description>This field indicates that the Master is in 10-bit address mode and that the second address byte of the 10-bit address was not acknowledged by any slave.\n\n
-                Reset value: 0x0\n\n
-                Role of DW_apb_i2c:  Master-Transmitter or Master-Receiver</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>This abort is not generated</description>
-                  <name>INACTIVE</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>Byte 2 of 10Bit Address not ACKed by any slave</description>
-                  <name>ACTIVE</name>
-                  <value>1</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>ABRT_10ADDR2_NOACK</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[1:1]</bitRange>
-              <description>This field indicates that the Master is in 10-bit address mode and the first 10-bit address byte was not acknowledged by any slave.\n\n
-                Reset value: 0x0\n\n
-                Role of DW_apb_i2c:  Master-Transmitter or Master-Receiver</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>This abort is not generated</description>
-                  <name>INACTIVE</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>Byte 1 of 10Bit Address not ACKed by any slave</description>
-                  <name>ACTIVE</name>
-                  <value>1</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>ABRT_10ADDR1_NOACK</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[0:0]</bitRange>
-              <description>This field indicates that the Master is in 7-bit addressing mode and the address sent was not acknowledged by any slave.\n\n
-                Reset value: 0x0\n\n
-                Role of DW_apb_i2c:  Master-Transmitter or Master-Receiver</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>This abort is not generated</description>
-                  <name>INACTIVE</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>This abort is generated because of NOACK for 7-bit address</description>
-                  <name>ACTIVE</name>
-                  <value>1</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>ABRT_7B_ADDR_NOACK</name>
-            </field>
-          </fields>
-          <name>IC_TX_ABRT_SOURCE</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0084</addressOffset>
-          <description>Generate Slave Data NACK Register\n\n
-            The register is used to generate a NACK for the data part of a transfer when DW_apb_i2c is acting as a slave-receiver. This register only exists when the IC_SLV_DATA_NACK_ONLY parameter is set to 1. When this parameter disabled, this register does not exist and writing to the register's address has no effect.\n\n
-            A write can occur on this register if both of the following conditions are met: - DW_apb_i2c is disabled (IC_ENABLE[0] = 0) - Slave part is inactive (IC_STATUS[6] = 0) Note: The IC_STATUS[6] is a register read-back location for the internal slv_activity signal; the user should poll this before writing the ic_slv_data_nack_only bit.</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[0:0]</bitRange>
-              <description>Generate NACK. This NACK generation only occurs when DW_apb_i2c is a slave-receiver. If this register is set to a value of 1, it can only generate a NACK after a data byte is received; hence, the data transfer is aborted and the data received is not pushed to the receive buffer.\n\n
-                When the register is set to a value of 0, it generates NACK/ACK, depending on normal criteria. - 1: generate NACK after data byte received - 0: generate NACK/ACK normally Reset value: 0x0</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>Slave receiver generates NACK normally</description>
-                  <name>DISABLED</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>Slave receiver generates NACK upon data reception only</description>
-                  <name>ENABLED</name>
-                  <value>1</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>NACK</name>
-            </field>
-          </fields>
-          <name>IC_SLV_DATA_NACK_ONLY</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0088</addressOffset>
-          <description>DMA Control Register\n\n
-            The register is used to enable the DMA Controller interface operation. There is a separate bit for transmit and receive. This can be programmed regardless of the state of IC_ENABLE.</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[1:1]</bitRange>
-              <description>Transmit DMA Enable. This bit enables/disables the transmit FIFO DMA channel. Reset value: 0x0</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>transmit FIFO DMA channel disabled</description>
-                  <name>DISABLED</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>Transmit FIFO DMA channel enabled</description>
-                  <name>ENABLED</name>
-                  <value>1</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>TDMAE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[0:0]</bitRange>
-              <description>Receive DMA Enable. This bit enables/disables the receive FIFO DMA channel. Reset value: 0x0</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>Receive FIFO DMA channel disabled</description>
-                  <name>DISABLED</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>Receive FIFO DMA channel enabled</description>
-                  <name>ENABLED</name>
-                  <value>1</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>RDMAE</name>
-            </field>
-          </fields>
-          <name>IC_DMA_CR</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x008c</addressOffset>
-          <description>DMA Transmit Data Level Register</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[3:0]</bitRange>
-              <description>Transmit Data Level. This bit field controls the level at which a DMA request is made by the transmit logic. It is equal to the watermark level; that is, the dma_tx_req signal is generated when the number of valid data entries in the transmit FIFO is equal to or below this field value, and TDMAE = 1.\n\n
-                Reset value: 0x0</description>
-              <name>DMATDL</name>
-            </field>
-          </fields>
-          <name>IC_DMA_TDLR</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0090</addressOffset>
-          <description>I2C Receive Data Level Register</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[3:0]</bitRange>
-              <description>Receive Data Level. This bit field controls the level at which a DMA request is made by the receive logic. The watermark level = DMARDL+1; that is, dma_rx_req is generated when the number of valid data entries in the receive FIFO is equal to or more than this field value + 1, and RDMAE =1. For instance, when DMARDL is 0, then dma_rx_req is asserted when 1 or more data entries are present in the receive FIFO.\n\n
-                Reset value: 0x0</description>
-              <name>DMARDL</name>
-            </field>
-          </fields>
-          <name>IC_DMA_RDLR</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0094</addressOffset>
-          <description>I2C SDA Setup Register\n\n
-            This register controls the amount of time delay (in terms of number of ic_clk clock periods) introduced in the rising edge of SCL - relative to SDA changing - when DW_apb_i2c services a read request in a slave-transmitter operation. The relevant I2C requirement is tSU:DAT (note 4) as detailed in the I2C Bus Specification. This register must be programmed with a value equal to or greater than 2.\n\n
-            Writes to this register succeed only when IC_ENABLE[0] = 0.\n\n
-            Note: The length of setup time is calculated using [(IC_SDA_SETUP - 1) * (ic_clk_period)], so if the user requires 10 ic_clk periods of setup time, they should program a value of 11. The IC_SDA_SETUP register is only used by the DW_apb_i2c when operating as a slave transmitter.</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[7:0]</bitRange>
-              <description>SDA Setup. It is recommended that if the required delay is 1000ns, then for an ic_clk frequency of 10 MHz, IC_SDA_SETUP should be programmed to a value of 11. IC_SDA_SETUP must be programmed with a minimum value of 2.</description>
-              <name>SDA_SETUP</name>
-            </field>
-          </fields>
-          <name>IC_SDA_SETUP</name>
-          <resetValue>0x00000064</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0098</addressOffset>
-          <description>I2C ACK General Call Register\n\n
-            The register controls whether DW_apb_i2c responds with a ACK or NACK when it receives an I2C General Call address.\n\n
-            This register is applicable only when the DW_apb_i2c is in slave mode.</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[0:0]</bitRange>
-              <description>ACK General Call. When set to 1, DW_apb_i2c responds with a ACK (by asserting ic_data_oe) when it receives a General Call. Otherwise, DW_apb_i2c responds with a NACK (by negating ic_data_oe).</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>Generate NACK for a General Call</description>
-                  <name>DISABLED</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>Generate ACK for a General Call</description>
-                  <name>ENABLED</name>
-                  <value>1</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>ACK_GEN_CALL</name>
-            </field>
-          </fields>
-          <name>IC_ACK_GENERAL_CALL</name>
-          <resetValue>0x00000001</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x009c</addressOffset>
-          <description>I2C Enable Status Register\n\n
-            The register is used to report the DW_apb_i2c hardware status when the IC_ENABLE[0] register is set from 1 to 0; that is, when DW_apb_i2c is disabled.\n\n
-            If IC_ENABLE[0] has been set to 1, bits 2:1 are forced to 0, and bit 0 is forced to 1.\n\n
-            If IC_ENABLE[0] has been set to 0, bits 2:1 is only be valid as soon as bit 0 is read as '0'.\n\n
-            Note: When IC_ENABLE[0] has been set to 0, a delay occurs for bit 0 to be read as 0 because disabling the DW_apb_i2c depends on I2C bus activities.</description>
-          <fields>
-            <field>
-              <access>read-only</access>
-              <bitRange>[2:2]</bitRange>
-              <description>Slave Received Data Lost. This bit indicates if a Slave-Receiver operation has been aborted with at least one data byte received from an I2C transfer due to the setting bit 0 of IC_ENABLE from 1 to 0. When read as 1, DW_apb_i2c is deemed to have been actively engaged in an aborted I2C transfer (with matching address) and the data phase of the I2C transfer has been entered, even though a data byte has been responded with a NACK.\n\n
-                Note:  If the remote I2C master terminates the transfer with a STOP condition before the DW_apb_i2c has a chance to NACK a transfer, and IC_ENABLE[0] has been set to 0, then this bit is also set to 1.\n\n
-                When read as 0, DW_apb_i2c is deemed to have been disabled without being actively involved in the data phase of a Slave-Receiver transfer.\n\n
-                Note:  The CPU can safely read this bit when IC_EN (bit 0) is read as 0.\n\n
-                Reset value: 0x0</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>Slave RX Data is not lost</description>
-                  <name>INACTIVE</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>Slave RX Data is lost</description>
-                  <name>ACTIVE</name>
-                  <value>1</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>SLV_RX_DATA_LOST</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[1:1]</bitRange>
-              <description>Slave Disabled While Busy (Transmit, Receive). This bit indicates if a potential or active Slave operation has been aborted due to the setting bit 0 of the IC_ENABLE register from 1 to 0. This bit is set when the CPU writes a 0 to the IC_ENABLE register while:\n\n
-                (a) DW_apb_i2c is receiving the address byte of the Slave-Transmitter operation from a remote master;\n\n
-                OR,\n\n
-                (b) address and data bytes of the Slave-Receiver operation from a remote master.\n\n
-                When read as 1, DW_apb_i2c is deemed to have forced a NACK during any part of an I2C transfer, irrespective of whether the I2C address matches the slave address set in DW_apb_i2c (IC_SAR register) OR if the transfer is completed before IC_ENABLE is set to 0 but has not taken effect.\n\n
-                Note:  If the remote I2C master terminates the transfer with a STOP condition before the DW_apb_i2c has a chance to NACK a transfer, and IC_ENABLE[0] has been set to 0, then this bit will also be set to 1.\n\n
-                When read as 0, DW_apb_i2c is deemed to have been disabled when there is master activity, or when the I2C bus is idle.\n\n
-                Note:  The CPU can safely read this bit when IC_EN (bit 0) is read as 0.\n\n
-                Reset value: 0x0</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>Slave is disabled when it is idle</description>
-                  <name>INACTIVE</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>Slave is disabled when it is active</description>
-                  <name>ACTIVE</name>
-                  <value>1</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>SLV_DISABLED_WHILE_BUSY</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[0:0]</bitRange>
-              <description>ic_en Status. This bit always reflects the value driven on the output port ic_en. - When read as 1, DW_apb_i2c is deemed to be in an enabled state. - When read as 0, DW_apb_i2c is deemed completely inactive. Note:  The CPU can safely read this bit anytime. When this bit is read as 0, the CPU can safely read SLV_RX_DATA_LOST (bit 2) and SLV_DISABLED_WHILE_BUSY (bit 1).\n\n
-                Reset value: 0x0</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>I2C disabled</description>
-                  <name>DISABLED</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>I2C enabled</description>
-                  <name>ENABLED</name>
-                  <value>1</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>IC_EN</name>
-            </field>
-          </fields>
-          <name>IC_ENABLE_STATUS</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x00a0</addressOffset>
-          <description>I2C SS, FS or FM+ spike suppression limit\n\n
-            This register is used to store the duration, measured in ic_clk cycles, of the longest spike that is filtered out by the spike suppression logic when the component is operating in SS, FS or FM+ modes. The relevant I2C requirement is tSP (table 4) as detailed in the I2C Bus Specification. This register must be programmed with a minimum value of 1.</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[7:0]</bitRange>
-              <description>This register must be set before any I2C bus transaction can take place to ensure stable operation. This register sets the duration, measured in ic_clk cycles, of the longest spike in the SCL or SDA lines that will be filtered out by the spike suppression logic. This register can be written only when the I2C interface is disabled which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect. The minimum valid value is 1; hardware prevents values less than this being written, and if attempted results in 1 being set. or more information, refer to 'Spike Suppression'.</description>
-              <name>IC_FS_SPKLEN</name>
-            </field>
-          </fields>
-          <name>IC_FS_SPKLEN</name>
-          <resetValue>0x00000007</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x00a8</addressOffset>
-          <description>Clear RESTART_DET Interrupt Register</description>
-          <fields>
-            <field>
-              <access>read-only</access>
-              <bitRange>[0:0]</bitRange>
-              <description>Read this register to clear the RESTART_DET interrupt (bit 12) of IC_RAW_INTR_STAT register.\n\n
-                Reset value: 0x0</description>
-              <name>CLR_RESTART_DET</name>
-            </field>
-          </fields>
-          <name>IC_CLR_RESTART_DET</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x00f4</addressOffset>
-          <description>Component Parameter Register 1\n\n
-            Note This register is not implemented and therefore reads as 0. If it was implemented it would be a constant read-only register that contains encoded information about the component's parameter settings. Fields shown below are the settings for those parameters</description>
-          <fields>
-            <field>
-              <access>read-only</access>
-              <bitRange>[23:16]</bitRange>
-              <description>TX Buffer Depth = 16</description>
-              <name>TX_BUFFER_DEPTH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[15:8]</bitRange>
-              <description>RX Buffer Depth = 16</description>
-              <name>RX_BUFFER_DEPTH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[7:7]</bitRange>
-              <description>Encoded parameters not visible</description>
-              <name>ADD_ENCODED_PARAMS</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[6:6]</bitRange>
-              <description>DMA handshaking signals are enabled</description>
-              <name>HAS_DMA</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[5:5]</bitRange>
-              <description>COMBINED Interrupt outputs</description>
-              <name>INTR_IO</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[4:4]</bitRange>
-              <description>Programmable count values for each mode.</description>
-              <name>HC_COUNT_VALUES</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[3:2]</bitRange>
-              <description>MAX SPEED MODE = FAST MODE</description>
-              <name>MAX_SPEED_MODE</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[1:0]</bitRange>
-              <description>APB data bus width is 32 bits</description>
-              <name>APB_DATA_WIDTH</name>
-            </field>
-          </fields>
-          <name>IC_COMP_PARAM_1</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x00f8</addressOffset>
-          <description>I2C Component Version Register</description>
-          <fields>
-            <field>
-              <access>read-only</access>
-              <bitRange>[31:0]</bitRange>
-              <name>IC_COMP_VERSION</name>
-            </field>
-          </fields>
-          <name>IC_COMP_VERSION</name>
-          <resetValue>0x3230312a</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x00fc</addressOffset>
-          <description>I2C Component Type Register</description>
-          <fields>
-            <field>
-              <access>read-only</access>
-              <bitRange>[31:0]</bitRange>
-              <description>Designware Component Type number = 0x44_57_01_40. This assigned unique hex value is constant and is derived from the two ASCII letters 'DW' followed by a 16-bit unsigned number.</description>
-              <name>IC_COMP_TYPE</name>
-            </field>
-          </fields>
-          <name>IC_COMP_TYPE</name>
-          <resetValue>0x44570140</resetValue>
-        </register>
-      </registers>
-      <size>32</size>
-      <version>1</version>
-    </peripheral>
-    <peripheral derivedFrom="I2C0">
-      <baseAddress>0x40048000</baseAddress>
-      <interrupt>
-        <name>I2C1_IRQ</name>
-        <value>24</value>
-      </interrupt>
-      <name>I2C1</name>
-    </peripheral>
-    <peripheral>
-      <addressBlock>
-        <offset>0</offset>
-        <size>0x1000</size>
-        <usage>registers</usage>
-      </addressBlock>
-      <baseAddress>0x4004c000</baseAddress>
-      <description>Control and data interface to SAR ADC</description>
-      <interrupt>
-        <name>ADC_IRQ_FIFO</name>
-        <value>22</value>
-      </interrupt>
-      <name>ADC</name>
-      <registers>
-        <register>
-          <addressOffset>0x0000</addressOffset>
-          <description>ADC Control and Status</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[20:16]</bitRange>
-              <description>Round-robin sampling. 1 bit per channel. Set all bits to 0 to disable.\n
-                Otherwise, the ADC will cycle through each enabled channel in a round-robin fashion.\n
-                The first channel to be sampled will be the one currently indicated by AINSEL.\n
-                AINSEL will be updated after each conversion with the newly-selected channel.</description>
-              <name>RROBIN</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[14:12]</bitRange>
-              <description>Select analog mux input. Updated automatically in round-robin mode.</description>
-              <name>AINSEL</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[10:10]</bitRange>
-              <description>Some past ADC conversion encountered an error. Write 1 to clear.</description>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>ERR_STICKY</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[9:9]</bitRange>
-              <description>The most recent ADC conversion encountered an error; result is undefined or noisy.</description>
-              <name>ERR</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[8:8]</bitRange>
-              <description>1 if the ADC is ready to start a new conversion. Implies any previous conversion has completed.\n
-                0 whilst conversion in progress.</description>
-              <name>READY</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[3:3]</bitRange>
-              <description>Continuously perform conversions whilst this bit is 1. A new conversion will start immediately after the previous finishes.</description>
-              <name>START_MANY</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[2:2]</bitRange>
-              <description>Start a single conversion. Self-clearing. Ignored if start_many is asserted.</description>
-              <modifiedWriteValues>clear</modifiedWriteValues>
-              <name>START_ONCE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[1:1]</bitRange>
-              <description>Power on temperature sensor. 1 - enabled. 0 - disabled.</description>
-              <name>TS_EN</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[0:0]</bitRange>
-              <description>Power on ADC and enable its clock.\n
-                1 - enabled. 0 - disabled.</description>
-              <name>EN</name>
-            </field>
-          </fields>
-          <name>CS</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0004</addressOffset>
-          <description>Result of most recent ADC conversion</description>
-          <fields>
-            <field>
-              <access>read-only</access>
-              <bitRange>[11:0]</bitRange>
-              <name>RESULT</name>
-            </field>
-          </fields>
-          <name>RESULT</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0008</addressOffset>
-          <description>FIFO control and status</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[27:24]</bitRange>
-              <description>DREQ/IRQ asserted when level &gt;= threshold</description>
-              <name>THRESH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[19:16]</bitRange>
-              <description>The number of conversion results currently waiting in the FIFO</description>
-              <name>LEVEL</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[11:11]</bitRange>
-              <description>1 if the FIFO has been overflowed. Write 1 to clear.</description>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>OVER</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[10:10]</bitRange>
-              <description>1 if the FIFO has been underflowed. Write 1 to clear.</description>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>UNDER</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[9:9]</bitRange>
-              <name>FULL</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[8:8]</bitRange>
-              <name>EMPTY</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[3:3]</bitRange>
-              <description>If 1: assert DMA requests when FIFO contains data</description>
-              <name>DREQ_EN</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[2:2]</bitRange>
-              <description>If 1: conversion error bit appears in the FIFO alongside the result</description>
-              <name>ERR</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[1:1]</bitRange>
-              <description>If 1: FIFO results are right-shifted to be one byte in size. Enables DMA to byte buffers.</description>
-              <name>SHIFT</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[0:0]</bitRange>
-              <description>If 1: write result to the FIFO after each conversion.</description>
-              <name>EN</name>
-            </field>
-          </fields>
-          <name>FCS</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x000c</addressOffset>
-          <description>Conversion result FIFO</description>
-          <fields>
-            <field>
-              <access>read-only</access>
-              <bitRange>[15:15]</bitRange>
-              <description>1 if this particular sample experienced a conversion error. Remains in the same location if the sample is shifted.</description>
-              <name>ERR</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[11:0]</bitRange>
-              <name>VAL</name>
-            </field>
-          </fields>
-          <name>FIFO</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0010</addressOffset>
-          <description>Clock divider. If non-zero, CS_START_MANY will start conversions\n
-            at regular intervals rather than back-to-back.\n
-            The divider is reset when either of these fields are written.\n
-            Total period is 1 + INT + FRAC / 256</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[23:8]</bitRange>
-              <description>Integer part of clock divisor.</description>
-              <name>INT</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[7:0]</bitRange>
-              <description>Fractional part of clock divisor. First-order delta-sigma.</description>
-              <name>FRAC</name>
-            </field>
-          </fields>
-          <name>DIV</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0014</addressOffset>
-          <description>Raw Interrupts</description>
-          <fields>
-            <field>
-              <access>read-only</access>
-              <bitRange>[0:0]</bitRange>
-              <description>Triggered when the sample FIFO reaches a certain level.\n
-                This level can be programmed via the FCS_THRESH field.</description>
-              <name>FIFO</name>
-            </field>
-          </fields>
-          <name>INTR</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0018</addressOffset>
-          <description>Interrupt Enable</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[0:0]</bitRange>
-              <description>Triggered when the sample FIFO reaches a certain level.\n
-                This level can be programmed via the FCS_THRESH field.</description>
-              <name>FIFO</name>
-            </field>
-          </fields>
-          <name>INTE</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x001c</addressOffset>
-          <description>Interrupt Force</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[0:0]</bitRange>
-              <description>Triggered when the sample FIFO reaches a certain level.\n
-                This level can be programmed via the FCS_THRESH field.</description>
-              <name>FIFO</name>
-            </field>
-          </fields>
-          <name>INTF</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0020</addressOffset>
-          <description>Interrupt status after masking &amp; forcing</description>
-          <fields>
-            <field>
-              <access>read-only</access>
-              <bitRange>[0:0]</bitRange>
-              <description>Triggered when the sample FIFO reaches a certain level.\n
-                This level can be programmed via the FCS_THRESH field.</description>
-              <name>FIFO</name>
-            </field>
-          </fields>
-          <name>INTS</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-      </registers>
-      <size>32</size>
-      <version>2</version>
-    </peripheral>
-    <peripheral>
-      <addressBlock>
-        <offset>0</offset>
-        <size>0x1000</size>
-        <usage>registers</usage>
-      </addressBlock>
-      <baseAddress>0x40050000</baseAddress>
-      <description>Simple PWM</description>
-      <interrupt>
-        <name>PWM_IRQ_WRAP</name>
-        <value>4</value>
-      </interrupt>
-      <name>PWM</name>
-      <registers>
-        <register>
-          <addressOffset>0x0000</addressOffset>
-          <description>Control and status register</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[7:7]</bitRange>
-              <description>Advance the phase of the counter by 1 count, while it is running.\n
-                Self-clearing. Write a 1, and poll until low. Counter must be running\n
-                at less than full speed (div_int + div_frac / 16 &gt; 1)</description>
-              <modifiedWriteValues>clear</modifiedWriteValues>
-              <name>PH_ADV</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[6:6]</bitRange>
-              <description>Retard the phase of the counter by 1 count, while it is running.\n
-                Self-clearing. Write a 1, and poll until low. Counter must be running.</description>
-              <modifiedWriteValues>clear</modifiedWriteValues>
-              <name>PH_RET</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[5:4]</bitRange>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>Free-running counting at rate dictated by fractional divider</description>
-                  <name>div</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>Fractional divider operation is gated by the PWM B pin.</description>
-                  <name>level</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>Counter advances with each rising edge of the PWM B pin.</description>
-                  <name>rise</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>Counter advances with each falling edge of the PWM B pin.</description>
-                  <name>fall</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>DIVMODE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[3:3]</bitRange>
-              <description>Invert output B</description>
-              <name>B_INV</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[2:2]</bitRange>
-              <description>Invert output A</description>
-              <name>A_INV</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[1:1]</bitRange>
-              <description>1: Enable phase-correct modulation. 0: Trailing-edge</description>
-              <name>PH_CORRECT</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[0:0]</bitRange>
-              <description>Enable the PWM channel.</description>
-              <name>EN</name>
-            </field>
-          </fields>
-          <name>CH0_CSR</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0004</addressOffset>
-          <description>INT and FRAC form a fixed-point fractional number.\n
-            Counting rate is system clock frequency divided by this number.\n
-            Fractional division uses simple 1st-order sigma-delta.</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[11:4]</bitRange>
-              <name>INT</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[3:0]</bitRange>
-              <name>FRAC</name>
-            </field>
-          </fields>
-          <name>CH0_DIV</name>
-          <resetValue>0x00000010</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0008</addressOffset>
-          <description>Direct access to the PWM counter</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[15:0]</bitRange>
-              <name>CH0_CTR</name>
-            </field>
-          </fields>
-          <name>CH0_CTR</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x000c</addressOffset>
-          <description>Counter compare values</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[31:16]</bitRange>
-              <name>B</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[15:0]</bitRange>
-              <name>A</name>
-            </field>
-          </fields>
-          <name>CH0_CC</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0010</addressOffset>
-          <description>Counter wrap value</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[15:0]</bitRange>
-              <name>CH0_TOP</name>
-            </field>
-          </fields>
-          <name>CH0_TOP</name>
-          <resetValue>0x0000ffff</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0014</addressOffset>
-          <description>Control and status register</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[7:7]</bitRange>
-              <description>Advance the phase of the counter by 1 count, while it is running.\n
-                Self-clearing. Write a 1, and poll until low. Counter must be running\n
-                at less than full speed (div_int + div_frac / 16 &gt; 1)</description>
-              <modifiedWriteValues>clear</modifiedWriteValues>
-              <name>PH_ADV</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[6:6]</bitRange>
-              <description>Retard the phase of the counter by 1 count, while it is running.\n
-                Self-clearing. Write a 1, and poll until low. Counter must be running.</description>
-              <modifiedWriteValues>clear</modifiedWriteValues>
-              <name>PH_RET</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[5:4]</bitRange>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>Free-running counting at rate dictated by fractional divider</description>
-                  <name>div</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>Fractional divider operation is gated by the PWM B pin.</description>
-                  <name>level</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>Counter advances with each rising edge of the PWM B pin.</description>
-                  <name>rise</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>Counter advances with each falling edge of the PWM B pin.</description>
-                  <name>fall</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>DIVMODE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[3:3]</bitRange>
-              <description>Invert output B</description>
-              <name>B_INV</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[2:2]</bitRange>
-              <description>Invert output A</description>
-              <name>A_INV</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[1:1]</bitRange>
-              <description>1: Enable phase-correct modulation. 0: Trailing-edge</description>
-              <name>PH_CORRECT</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[0:0]</bitRange>
-              <description>Enable the PWM channel.</description>
-              <name>EN</name>
-            </field>
-          </fields>
-          <name>CH1_CSR</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0018</addressOffset>
-          <description>INT and FRAC form a fixed-point fractional number.\n
-            Counting rate is system clock frequency divided by this number.\n
-            Fractional division uses simple 1st-order sigma-delta.</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[11:4]</bitRange>
-              <name>INT</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[3:0]</bitRange>
-              <name>FRAC</name>
-            </field>
-          </fields>
-          <name>CH1_DIV</name>
-          <resetValue>0x00000010</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x001c</addressOffset>
-          <description>Direct access to the PWM counter</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[15:0]</bitRange>
-              <name>CH1_CTR</name>
-            </field>
-          </fields>
-          <name>CH1_CTR</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0020</addressOffset>
-          <description>Counter compare values</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[31:16]</bitRange>
-              <name>B</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[15:0]</bitRange>
-              <name>A</name>
-            </field>
-          </fields>
-          <name>CH1_CC</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0024</addressOffset>
-          <description>Counter wrap value</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[15:0]</bitRange>
-              <name>CH1_TOP</name>
-            </field>
-          </fields>
-          <name>CH1_TOP</name>
-          <resetValue>0x0000ffff</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0028</addressOffset>
-          <description>Control and status register</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[7:7]</bitRange>
-              <description>Advance the phase of the counter by 1 count, while it is running.\n
-                Self-clearing. Write a 1, and poll until low. Counter must be running\n
-                at less than full speed (div_int + div_frac / 16 &gt; 1)</description>
-              <modifiedWriteValues>clear</modifiedWriteValues>
-              <name>PH_ADV</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[6:6]</bitRange>
-              <description>Retard the phase of the counter by 1 count, while it is running.\n
-                Self-clearing. Write a 1, and poll until low. Counter must be running.</description>
-              <modifiedWriteValues>clear</modifiedWriteValues>
-              <name>PH_RET</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[5:4]</bitRange>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>Free-running counting at rate dictated by fractional divider</description>
-                  <name>div</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>Fractional divider operation is gated by the PWM B pin.</description>
-                  <name>level</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>Counter advances with each rising edge of the PWM B pin.</description>
-                  <name>rise</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>Counter advances with each falling edge of the PWM B pin.</description>
-                  <name>fall</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>DIVMODE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[3:3]</bitRange>
-              <description>Invert output B</description>
-              <name>B_INV</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[2:2]</bitRange>
-              <description>Invert output A</description>
-              <name>A_INV</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[1:1]</bitRange>
-              <description>1: Enable phase-correct modulation. 0: Trailing-edge</description>
-              <name>PH_CORRECT</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[0:0]</bitRange>
-              <description>Enable the PWM channel.</description>
-              <name>EN</name>
-            </field>
-          </fields>
-          <name>CH2_CSR</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x002c</addressOffset>
-          <description>INT and FRAC form a fixed-point fractional number.\n
-            Counting rate is system clock frequency divided by this number.\n
-            Fractional division uses simple 1st-order sigma-delta.</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[11:4]</bitRange>
-              <name>INT</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[3:0]</bitRange>
-              <name>FRAC</name>
-            </field>
-          </fields>
-          <name>CH2_DIV</name>
-          <resetValue>0x00000010</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0030</addressOffset>
-          <description>Direct access to the PWM counter</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[15:0]</bitRange>
-              <name>CH2_CTR</name>
-            </field>
-          </fields>
-          <name>CH2_CTR</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0034</addressOffset>
-          <description>Counter compare values</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[31:16]</bitRange>
-              <name>B</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[15:0]</bitRange>
-              <name>A</name>
-            </field>
-          </fields>
-          <name>CH2_CC</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0038</addressOffset>
-          <description>Counter wrap value</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[15:0]</bitRange>
-              <name>CH2_TOP</name>
-            </field>
-          </fields>
-          <name>CH2_TOP</name>
-          <resetValue>0x0000ffff</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x003c</addressOffset>
-          <description>Control and status register</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[7:7]</bitRange>
-              <description>Advance the phase of the counter by 1 count, while it is running.\n
-                Self-clearing. Write a 1, and poll until low. Counter must be running\n
-                at less than full speed (div_int + div_frac / 16 &gt; 1)</description>
-              <modifiedWriteValues>clear</modifiedWriteValues>
-              <name>PH_ADV</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[6:6]</bitRange>
-              <description>Retard the phase of the counter by 1 count, while it is running.\n
-                Self-clearing. Write a 1, and poll until low. Counter must be running.</description>
-              <modifiedWriteValues>clear</modifiedWriteValues>
-              <name>PH_RET</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[5:4]</bitRange>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>Free-running counting at rate dictated by fractional divider</description>
-                  <name>div</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>Fractional divider operation is gated by the PWM B pin.</description>
-                  <name>level</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>Counter advances with each rising edge of the PWM B pin.</description>
-                  <name>rise</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>Counter advances with each falling edge of the PWM B pin.</description>
-                  <name>fall</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>DIVMODE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[3:3]</bitRange>
-              <description>Invert output B</description>
-              <name>B_INV</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[2:2]</bitRange>
-              <description>Invert output A</description>
-              <name>A_INV</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[1:1]</bitRange>
-              <description>1: Enable phase-correct modulation. 0: Trailing-edge</description>
-              <name>PH_CORRECT</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[0:0]</bitRange>
-              <description>Enable the PWM channel.</description>
-              <name>EN</name>
-            </field>
-          </fields>
-          <name>CH3_CSR</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0040</addressOffset>
-          <description>INT and FRAC form a fixed-point fractional number.\n
-            Counting rate is system clock frequency divided by this number.\n
-            Fractional division uses simple 1st-order sigma-delta.</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[11:4]</bitRange>
-              <name>INT</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[3:0]</bitRange>
-              <name>FRAC</name>
-            </field>
-          </fields>
-          <name>CH3_DIV</name>
-          <resetValue>0x00000010</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0044</addressOffset>
-          <description>Direct access to the PWM counter</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[15:0]</bitRange>
-              <name>CH3_CTR</name>
-            </field>
-          </fields>
-          <name>CH3_CTR</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0048</addressOffset>
-          <description>Counter compare values</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[31:16]</bitRange>
-              <name>B</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[15:0]</bitRange>
-              <name>A</name>
-            </field>
-          </fields>
-          <name>CH3_CC</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x004c</addressOffset>
-          <description>Counter wrap value</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[15:0]</bitRange>
-              <name>CH3_TOP</name>
-            </field>
-          </fields>
-          <name>CH3_TOP</name>
-          <resetValue>0x0000ffff</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0050</addressOffset>
-          <description>Control and status register</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[7:7]</bitRange>
-              <description>Advance the phase of the counter by 1 count, while it is running.\n
-                Self-clearing. Write a 1, and poll until low. Counter must be running\n
-                at less than full speed (div_int + div_frac / 16 &gt; 1)</description>
-              <modifiedWriteValues>clear</modifiedWriteValues>
-              <name>PH_ADV</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[6:6]</bitRange>
-              <description>Retard the phase of the counter by 1 count, while it is running.\n
-                Self-clearing. Write a 1, and poll until low. Counter must be running.</description>
-              <modifiedWriteValues>clear</modifiedWriteValues>
-              <name>PH_RET</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[5:4]</bitRange>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>Free-running counting at rate dictated by fractional divider</description>
-                  <name>div</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>Fractional divider operation is gated by the PWM B pin.</description>
-                  <name>level</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>Counter advances with each rising edge of the PWM B pin.</description>
-                  <name>rise</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>Counter advances with each falling edge of the PWM B pin.</description>
-                  <name>fall</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>DIVMODE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[3:3]</bitRange>
-              <description>Invert output B</description>
-              <name>B_INV</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[2:2]</bitRange>
-              <description>Invert output A</description>
-              <name>A_INV</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[1:1]</bitRange>
-              <description>1: Enable phase-correct modulation. 0: Trailing-edge</description>
-              <name>PH_CORRECT</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[0:0]</bitRange>
-              <description>Enable the PWM channel.</description>
-              <name>EN</name>
-            </field>
-          </fields>
-          <name>CH4_CSR</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0054</addressOffset>
-          <description>INT and FRAC form a fixed-point fractional number.\n
-            Counting rate is system clock frequency divided by this number.\n
-            Fractional division uses simple 1st-order sigma-delta.</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[11:4]</bitRange>
-              <name>INT</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[3:0]</bitRange>
-              <name>FRAC</name>
-            </field>
-          </fields>
-          <name>CH4_DIV</name>
-          <resetValue>0x00000010</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0058</addressOffset>
-          <description>Direct access to the PWM counter</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[15:0]</bitRange>
-              <name>CH4_CTR</name>
-            </field>
-          </fields>
-          <name>CH4_CTR</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x005c</addressOffset>
-          <description>Counter compare values</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[31:16]</bitRange>
-              <name>B</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[15:0]</bitRange>
-              <name>A</name>
-            </field>
-          </fields>
-          <name>CH4_CC</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0060</addressOffset>
-          <description>Counter wrap value</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[15:0]</bitRange>
-              <name>CH4_TOP</name>
-            </field>
-          </fields>
-          <name>CH4_TOP</name>
-          <resetValue>0x0000ffff</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0064</addressOffset>
-          <description>Control and status register</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[7:7]</bitRange>
-              <description>Advance the phase of the counter by 1 count, while it is running.\n
-                Self-clearing. Write a 1, and poll until low. Counter must be running\n
-                at less than full speed (div_int + div_frac / 16 &gt; 1)</description>
-              <modifiedWriteValues>clear</modifiedWriteValues>
-              <name>PH_ADV</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[6:6]</bitRange>
-              <description>Retard the phase of the counter by 1 count, while it is running.\n
-                Self-clearing. Write a 1, and poll until low. Counter must be running.</description>
-              <modifiedWriteValues>clear</modifiedWriteValues>
-              <name>PH_RET</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[5:4]</bitRange>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>Free-running counting at rate dictated by fractional divider</description>
-                  <name>div</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>Fractional divider operation is gated by the PWM B pin.</description>
-                  <name>level</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>Counter advances with each rising edge of the PWM B pin.</description>
-                  <name>rise</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>Counter advances with each falling edge of the PWM B pin.</description>
-                  <name>fall</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>DIVMODE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[3:3]</bitRange>
-              <description>Invert output B</description>
-              <name>B_INV</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[2:2]</bitRange>
-              <description>Invert output A</description>
-              <name>A_INV</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[1:1]</bitRange>
-              <description>1: Enable phase-correct modulation. 0: Trailing-edge</description>
-              <name>PH_CORRECT</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[0:0]</bitRange>
-              <description>Enable the PWM channel.</description>
-              <name>EN</name>
-            </field>
-          </fields>
-          <name>CH5_CSR</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0068</addressOffset>
-          <description>INT and FRAC form a fixed-point fractional number.\n
-            Counting rate is system clock frequency divided by this number.\n
-            Fractional division uses simple 1st-order sigma-delta.</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[11:4]</bitRange>
-              <name>INT</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[3:0]</bitRange>
-              <name>FRAC</name>
-            </field>
-          </fields>
-          <name>CH5_DIV</name>
-          <resetValue>0x00000010</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x006c</addressOffset>
-          <description>Direct access to the PWM counter</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[15:0]</bitRange>
-              <name>CH5_CTR</name>
-            </field>
-          </fields>
-          <name>CH5_CTR</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0070</addressOffset>
-          <description>Counter compare values</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[31:16]</bitRange>
-              <name>B</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[15:0]</bitRange>
-              <name>A</name>
-            </field>
-          </fields>
-          <name>CH5_CC</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0074</addressOffset>
-          <description>Counter wrap value</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[15:0]</bitRange>
-              <name>CH5_TOP</name>
-            </field>
-          </fields>
-          <name>CH5_TOP</name>
-          <resetValue>0x0000ffff</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0078</addressOffset>
-          <description>Control and status register</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[7:7]</bitRange>
-              <description>Advance the phase of the counter by 1 count, while it is running.\n
-                Self-clearing. Write a 1, and poll until low. Counter must be running\n
-                at less than full speed (div_int + div_frac / 16 &gt; 1)</description>
-              <modifiedWriteValues>clear</modifiedWriteValues>
-              <name>PH_ADV</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[6:6]</bitRange>
-              <description>Retard the phase of the counter by 1 count, while it is running.\n
-                Self-clearing. Write a 1, and poll until low. Counter must be running.</description>
-              <modifiedWriteValues>clear</modifiedWriteValues>
-              <name>PH_RET</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[5:4]</bitRange>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>Free-running counting at rate dictated by fractional divider</description>
-                  <name>div</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>Fractional divider operation is gated by the PWM B pin.</description>
-                  <name>level</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>Counter advances with each rising edge of the PWM B pin.</description>
-                  <name>rise</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>Counter advances with each falling edge of the PWM B pin.</description>
-                  <name>fall</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>DIVMODE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[3:3]</bitRange>
-              <description>Invert output B</description>
-              <name>B_INV</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[2:2]</bitRange>
-              <description>Invert output A</description>
-              <name>A_INV</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[1:1]</bitRange>
-              <description>1: Enable phase-correct modulation. 0: Trailing-edge</description>
-              <name>PH_CORRECT</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[0:0]</bitRange>
-              <description>Enable the PWM channel.</description>
-              <name>EN</name>
-            </field>
-          </fields>
-          <name>CH6_CSR</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x007c</addressOffset>
-          <description>INT and FRAC form a fixed-point fractional number.\n
-            Counting rate is system clock frequency divided by this number.\n
-            Fractional division uses simple 1st-order sigma-delta.</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[11:4]</bitRange>
-              <name>INT</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[3:0]</bitRange>
-              <name>FRAC</name>
-            </field>
-          </fields>
-          <name>CH6_DIV</name>
-          <resetValue>0x00000010</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0080</addressOffset>
-          <description>Direct access to the PWM counter</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[15:0]</bitRange>
-              <name>CH6_CTR</name>
-            </field>
-          </fields>
-          <name>CH6_CTR</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0084</addressOffset>
-          <description>Counter compare values</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[31:16]</bitRange>
-              <name>B</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[15:0]</bitRange>
-              <name>A</name>
-            </field>
-          </fields>
-          <name>CH6_CC</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0088</addressOffset>
-          <description>Counter wrap value</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[15:0]</bitRange>
-              <name>CH6_TOP</name>
-            </field>
-          </fields>
-          <name>CH6_TOP</name>
-          <resetValue>0x0000ffff</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x008c</addressOffset>
-          <description>Control and status register</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[7:7]</bitRange>
-              <description>Advance the phase of the counter by 1 count, while it is running.\n
-                Self-clearing. Write a 1, and poll until low. Counter must be running\n
-                at less than full speed (div_int + div_frac / 16 &gt; 1)</description>
-              <modifiedWriteValues>clear</modifiedWriteValues>
-              <name>PH_ADV</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[6:6]</bitRange>
-              <description>Retard the phase of the counter by 1 count, while it is running.\n
-                Self-clearing. Write a 1, and poll until low. Counter must be running.</description>
-              <modifiedWriteValues>clear</modifiedWriteValues>
-              <name>PH_RET</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[5:4]</bitRange>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>Free-running counting at rate dictated by fractional divider</description>
-                  <name>div</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>Fractional divider operation is gated by the PWM B pin.</description>
-                  <name>level</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>Counter advances with each rising edge of the PWM B pin.</description>
-                  <name>rise</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>Counter advances with each falling edge of the PWM B pin.</description>
-                  <name>fall</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>DIVMODE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[3:3]</bitRange>
-              <description>Invert output B</description>
-              <name>B_INV</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[2:2]</bitRange>
-              <description>Invert output A</description>
-              <name>A_INV</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[1:1]</bitRange>
-              <description>1: Enable phase-correct modulation. 0: Trailing-edge</description>
-              <name>PH_CORRECT</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[0:0]</bitRange>
-              <description>Enable the PWM channel.</description>
-              <name>EN</name>
-            </field>
-          </fields>
-          <name>CH7_CSR</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0090</addressOffset>
-          <description>INT and FRAC form a fixed-point fractional number.\n
-            Counting rate is system clock frequency divided by this number.\n
-            Fractional division uses simple 1st-order sigma-delta.</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[11:4]</bitRange>
-              <name>INT</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[3:0]</bitRange>
-              <name>FRAC</name>
-            </field>
-          </fields>
-          <name>CH7_DIV</name>
-          <resetValue>0x00000010</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0094</addressOffset>
-          <description>Direct access to the PWM counter</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[15:0]</bitRange>
-              <name>CH7_CTR</name>
-            </field>
-          </fields>
-          <name>CH7_CTR</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0098</addressOffset>
-          <description>Counter compare values</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[31:16]</bitRange>
-              <name>B</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[15:0]</bitRange>
-              <name>A</name>
-            </field>
-          </fields>
-          <name>CH7_CC</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x009c</addressOffset>
-          <description>Counter wrap value</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[15:0]</bitRange>
-              <name>CH7_TOP</name>
-            </field>
-          </fields>
-          <name>CH7_TOP</name>
-          <resetValue>0x0000ffff</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x00a0</addressOffset>
-          <description>This register aliases the CSR_EN bits for all channels.\n
-            Writing to this register allows multiple channels to be enabled\n
-            or disabled simultaneously, so they can run in perfect sync.\n
-            For each channel, there is only one physical EN register bit,\n
-            which can be accessed through here or CHx_CSR.</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[7:7]</bitRange>
-              <name>CH7</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[6:6]</bitRange>
-              <name>CH6</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[5:5]</bitRange>
-              <name>CH5</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[4:4]</bitRange>
-              <name>CH4</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[3:3]</bitRange>
-              <name>CH3</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[2:2]</bitRange>
-              <name>CH2</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[1:1]</bitRange>
-              <name>CH1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[0:0]</bitRange>
-              <name>CH0</name>
-            </field>
-          </fields>
-          <name>EN</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x00a4</addressOffset>
-          <description>Raw Interrupts</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[7:7]</bitRange>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>CH7</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[6:6]</bitRange>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>CH6</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[5:5]</bitRange>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>CH5</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[4:4]</bitRange>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>CH4</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[3:3]</bitRange>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>CH3</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[2:2]</bitRange>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>CH2</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[1:1]</bitRange>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>CH1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[0:0]</bitRange>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>CH0</name>
-            </field>
-          </fields>
-          <name>INTR</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x00a8</addressOffset>
-          <description>Interrupt Enable</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[7:7]</bitRange>
-              <name>CH7</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[6:6]</bitRange>
-              <name>CH6</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[5:5]</bitRange>
-              <name>CH5</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[4:4]</bitRange>
-              <name>CH4</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[3:3]</bitRange>
-              <name>CH3</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[2:2]</bitRange>
-              <name>CH2</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[1:1]</bitRange>
-              <name>CH1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[0:0]</bitRange>
-              <name>CH0</name>
-            </field>
-          </fields>
-          <name>INTE</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x00ac</addressOffset>
-          <description>Interrupt Force</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[7:7]</bitRange>
-              <name>CH7</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[6:6]</bitRange>
-              <name>CH6</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[5:5]</bitRange>
-              <name>CH5</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[4:4]</bitRange>
-              <name>CH4</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[3:3]</bitRange>
-              <name>CH3</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[2:2]</bitRange>
-              <name>CH2</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[1:1]</bitRange>
-              <name>CH1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[0:0]</bitRange>
-              <name>CH0</name>
-            </field>
-          </fields>
-          <name>INTF</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x00b0</addressOffset>
-          <description>Interrupt status after masking &amp; forcing</description>
-          <fields>
-            <field>
-              <access>read-only</access>
-              <bitRange>[7:7]</bitRange>
-              <name>CH7</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[6:6]</bitRange>
-              <name>CH6</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[5:5]</bitRange>
-              <name>CH5</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[4:4]</bitRange>
-              <name>CH4</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[3:3]</bitRange>
-              <name>CH3</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[2:2]</bitRange>
-              <name>CH2</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[1:1]</bitRange>
-              <name>CH1</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[0:0]</bitRange>
-              <name>CH0</name>
-            </field>
-          </fields>
-          <name>INTS</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-      </registers>
-      <size>32</size>
-      <version>1</version>
-    </peripheral>
-    <peripheral>
-      <addressBlock>
-        <offset>0</offset>
-        <size>0x1000</size>
-        <usage>registers</usage>
-      </addressBlock>
-      <baseAddress>0x40054000</baseAddress>
-      <description>Controls time and alarms\n
-        time is a 64 bit value indicating the time in usec since power-on\n
-        timeh is the top 32 bits of time &amp; timel is the bottom 32 bits\n
-        to change time write to timelw before timehw\n
-        to read time read from timelr before timehr\n
-        An alarm is set by setting alarm_enable and writing to the corresponding alarm register\n
-        When an alarm is pending, the corresponding alarm_running signal will be high\n
-        An alarm can be cancelled before it has finished by clearing the alarm_enable\n
-        When an alarm fires, the corresponding alarm_irq is set and alarm_running is cleared\n
-        To clear the interrupt write a 1 to the corresponding alarm_irq</description>
-      <interrupt>
-        <name>TIMER_IRQ_0</name>
-        <value>0</value>
-      </interrupt>
-      <interrupt>
-        <name>TIMER_IRQ_1</name>
-        <value>1</value>
-      </interrupt>
-      <interrupt>
-        <name>TIMER_IRQ_2</name>
-        <value>2</value>
-      </interrupt>
-      <interrupt>
-        <name>TIMER_IRQ_3</name>
-        <value>3</value>
-      </interrupt>
-      <name>TIMER</name>
-      <registers>
-        <register>
-          <access>write-only</access>
-          <addressOffset>0x0000</addressOffset>
-          <description>Write to bits 63:32 of time\n
-            always write timelw before timehw</description>
-          <name>TIMEHW</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>write-only</access>
-          <addressOffset>0x0004</addressOffset>
-          <description>Write to bits 31:0 of time\n
-            writes do not get copied to time until timehw is written</description>
-          <name>TIMELW</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-only</access>
-          <addressOffset>0x0008</addressOffset>
-          <description>Read from bits 63:32 of time\n
-            always read timelr before timehr</description>
-          <name>TIMEHR</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-only</access>
-          <addressOffset>0x000c</addressOffset>
-          <description>Read from bits 31:0 of time</description>
-          <name>TIMELR</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x0010</addressOffset>
-          <description>Arm alarm 0, and configure the time it will fire.\n
-            Once armed, the alarm fires when TIMER_ALARM0 == TIMELR.\n
-            The alarm will disarm itself once it fires, and can\n
-            be disarmed early using the ARMED status register.</description>
-          <name>ALARM0</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x0014</addressOffset>
-          <description>Arm alarm 1, and configure the time it will fire.\n
-            Once armed, the alarm fires when TIMER_ALARM1 == TIMELR.\n
-            The alarm will disarm itself once it fires, and can\n
-            be disarmed early using the ARMED status register.</description>
-          <name>ALARM1</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x0018</addressOffset>
-          <description>Arm alarm 2, and configure the time it will fire.\n
-            Once armed, the alarm fires when TIMER_ALARM2 == TIMELR.\n
-            The alarm will disarm itself once it fires, and can\n
-            be disarmed early using the ARMED status register.</description>
-          <name>ALARM2</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x001c</addressOffset>
-          <description>Arm alarm 3, and configure the time it will fire.\n
-            Once armed, the alarm fires when TIMER_ALARM3 == TIMELR.\n
-            The alarm will disarm itself once it fires, and can\n
-            be disarmed early using the ARMED status register.</description>
-          <name>ALARM3</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0020</addressOffset>
-          <description>Indicates the armed/disarmed status of each alarm.\n
-            A write to the corresponding ALARMx register arms the alarm.\n
-            Alarms automatically disarm upon firing, but writing ones here\n
-            will disarm immediately without waiting to fire.</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[3:0]</bitRange>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>ARMED</name>
-            </field>
-          </fields>
-          <name>ARMED</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-only</access>
-          <addressOffset>0x0024</addressOffset>
-          <description>Raw read from bits 63:32 of time (no side effects)</description>
-          <name>TIMERAWH</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-only</access>
-          <addressOffset>0x0028</addressOffset>
-          <description>Raw read from bits 31:0 of time (no side effects)</description>
-          <name>TIMERAWL</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x002c</addressOffset>
-          <description>Set bits high to enable pause when the corresponding debug ports are active</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[2:2]</bitRange>
-              <description>Pause when processor 1 is in debug mode</description>
-              <name>DBG1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[1:1]</bitRange>
-              <description>Pause when processor 0 is in debug mode</description>
-              <name>DBG0</name>
-            </field>
-          </fields>
-          <name>DBGPAUSE</name>
-          <resetValue>0x00000007</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0030</addressOffset>
-          <description>Set high to pause the timer</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[0:0]</bitRange>
-              <name>PAUSE</name>
-            </field>
-          </fields>
-          <name>PAUSE</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0034</addressOffset>
-          <description>Raw Interrupts</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[3:3]</bitRange>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>ALARM_3</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[2:2]</bitRange>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>ALARM_2</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[1:1]</bitRange>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>ALARM_1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[0:0]</bitRange>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>ALARM_0</name>
-            </field>
-          </fields>
-          <name>INTR</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0038</addressOffset>
-          <description>Interrupt Enable</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[3:3]</bitRange>
-              <name>ALARM_3</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[2:2]</bitRange>
-              <name>ALARM_2</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[1:1]</bitRange>
-              <name>ALARM_1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[0:0]</bitRange>
-              <name>ALARM_0</name>
-            </field>
-          </fields>
-          <name>INTE</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x003c</addressOffset>
-          <description>Interrupt Force</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[3:3]</bitRange>
-              <name>ALARM_3</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[2:2]</bitRange>
-              <name>ALARM_2</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[1:1]</bitRange>
-              <name>ALARM_1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[0:0]</bitRange>
-              <name>ALARM_0</name>
-            </field>
-          </fields>
-          <name>INTF</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0040</addressOffset>
-          <description>Interrupt status after masking &amp; forcing</description>
-          <fields>
-            <field>
-              <access>read-only</access>
-              <bitRange>[3:3]</bitRange>
-              <name>ALARM_3</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[2:2]</bitRange>
-              <name>ALARM_2</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[1:1]</bitRange>
-              <name>ALARM_1</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[0:0]</bitRange>
-              <name>ALARM_0</name>
-            </field>
-          </fields>
-          <name>INTS</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-      </registers>
-      <size>32</size>
-      <version>1</version>
-    </peripheral>
-    <peripheral>
-      <addressBlock>
-        <offset>0</offset>
-        <size>0x1000</size>
-        <usage>registers</usage>
-      </addressBlock>
-      <baseAddress>0x40058000</baseAddress>
-      <name>WATCHDOG</name>
-      <registers>
-        <register>
-          <addressOffset>0x0000</addressOffset>
-          <description>Watchdog control\n
-            The rst_wdsel register determines which subsystems are reset when the watchdog is triggered.\n
-            The watchdog can be triggered in software.</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[31:31]</bitRange>
-              <description>Trigger a watchdog reset</description>
-              <modifiedWriteValues>clear</modifiedWriteValues>
-              <name>TRIGGER</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[30:30]</bitRange>
-              <description>When not enabled the watchdog timer is paused</description>
-              <name>ENABLE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[26:26]</bitRange>
-              <description>Pause the watchdog timer when processor 1 is in debug mode</description>
-              <name>PAUSE_DBG1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[25:25]</bitRange>
-              <description>Pause the watchdog timer when processor 0 is in debug mode</description>
-              <name>PAUSE_DBG0</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[24:24]</bitRange>
-              <description>Pause the watchdog timer when JTAG is accessing the bus fabric</description>
-              <name>PAUSE_JTAG</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[23:0]</bitRange>
-              <description>Indicates the number of ticks / 2 (see errata RP2040-E1) before a watchdog reset will be triggered</description>
-              <name>TIME</name>
-            </field>
-          </fields>
-          <name>CTRL</name>
-          <resetValue>0x07000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0004</addressOffset>
-          <description>Load the watchdog timer. The maximum setting is 0xffffff which corresponds to 0xffffff / 2 ticks before triggering a watchdog reset (see errata RP2040-E1).</description>
-          <fields>
-            <field>
-              <access>write-only</access>
-              <bitRange>[23:0]</bitRange>
-              <name>LOAD</name>
-            </field>
-          </fields>
-          <name>LOAD</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0008</addressOffset>
-          <description>Logs the reason for the last reset. Both bits are zero for the case of a hardware reset.</description>
-          <fields>
-            <field>
-              <access>read-only</access>
-              <bitRange>[1:1]</bitRange>
-              <name>FORCE</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[0:0]</bitRange>
-              <name>TIMER</name>
-            </field>
-          </fields>
-          <name>REASON</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x000c</addressOffset>
-          <description>Scratch register. Information persists through soft reset of the chip.</description>
-          <name>SCRATCH0</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x0010</addressOffset>
-          <description>Scratch register. Information persists through soft reset of the chip.</description>
-          <name>SCRATCH1</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x0014</addressOffset>
-          <description>Scratch register. Information persists through soft reset of the chip.</description>
-          <name>SCRATCH2</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x0018</addressOffset>
-          <description>Scratch register. Information persists through soft reset of the chip.</description>
-          <name>SCRATCH3</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x001c</addressOffset>
-          <description>Scratch register. Information persists through soft reset of the chip.</description>
-          <name>SCRATCH4</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x0020</addressOffset>
-          <description>Scratch register. Information persists through soft reset of the chip.</description>
-          <name>SCRATCH5</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x0024</addressOffset>
-          <description>Scratch register. Information persists through soft reset of the chip.</description>
-          <name>SCRATCH6</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x0028</addressOffset>
-          <description>Scratch register. Information persists through soft reset of the chip.</description>
-          <name>SCRATCH7</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x002c</addressOffset>
-          <description>Controls the tick generator</description>
-          <fields>
-            <field>
-              <access>read-only</access>
-              <bitRange>[19:11]</bitRange>
-              <description>Count down timer: the remaining number clk_tick cycles before the next tick is generated.</description>
-              <name>COUNT</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[10:10]</bitRange>
-              <description>Is the tick generator running?</description>
-              <name>RUNNING</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[9:9]</bitRange>
-              <description>start / stop tick generation</description>
-              <name>ENABLE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[8:0]</bitRange>
-              <description>Total number of clk_tick cycles before the next tick.</description>
-              <name>CYCLES</name>
-            </field>
-          </fields>
-          <name>TICK</name>
-          <resetValue>0x00000200</resetValue>
-        </register>
-      </registers>
-      <size>32</size>
-      <version>1</version>
-    </peripheral>
-    <peripheral>
-      <addressBlock>
-        <offset>0</offset>
-        <size>0x1000</size>
-        <usage>registers</usage>
-      </addressBlock>
-      <baseAddress>0x4005c000</baseAddress>
-      <description>Register block to control RTC</description>
-      <interrupt>
-        <name>RTC_IRQ</name>
-        <value>25</value>
-      </interrupt>
-      <name>RTC</name>
-      <registers>
-        <register>
-          <addressOffset>0x0000</addressOffset>
-          <description>Divider minus 1 for the 1 second counter. Safe to change the value when RTC is not enabled.</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[15:0]</bitRange>
-              <name>CLKDIV_M1</name>
-            </field>
-          </fields>
-          <name>CLKDIV_M1</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0004</addressOffset>
-          <description>RTC setup register 0</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[23:12]</bitRange>
-              <description>Year</description>
-              <name>YEAR</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[11:8]</bitRange>
-              <description>Month (1..12)</description>
-              <name>MONTH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[4:0]</bitRange>
-              <description>Day of the month (1..31)</description>
-              <name>DAY</name>
-            </field>
-          </fields>
-          <name>SETUP_0</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0008</addressOffset>
-          <description>RTC setup register 1</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[26:24]</bitRange>
-              <description>Day of the week: 1-Monday...0-Sunday ISO 8601 mod 7</description>
-              <name>DOTW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[20:16]</bitRange>
-              <description>Hours</description>
-              <name>HOUR</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[13:8]</bitRange>
-              <description>Minutes</description>
-              <name>MIN</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[5:0]</bitRange>
-              <description>Seconds</description>
-              <name>SEC</name>
-            </field>
-          </fields>
-          <name>SETUP_1</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x000c</addressOffset>
-          <description>RTC Control and status</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[8:8]</bitRange>
-              <description>If set, leapyear is forced off.\n
-                Useful for years divisible by 100 but not by 400</description>
-              <name>FORCE_NOTLEAPYEAR</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[4:4]</bitRange>
-              <description>Load RTC</description>
-              <modifiedWriteValues>clear</modifiedWriteValues>
-              <name>LOAD</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[1:1]</bitRange>
-              <description>RTC enabled (running)</description>
-              <name>RTC_ACTIVE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[0:0]</bitRange>
-              <description>Enable RTC</description>
-              <name>RTC_ENABLE</name>
-            </field>
-          </fields>
-          <name>CTRL</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0010</addressOffset>
-          <description>Interrupt setup register 0</description>
-          <fields>
-            <field>
-              <access>read-only</access>
-              <bitRange>[29:29]</bitRange>
-              <name>MATCH_ACTIVE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[28:28]</bitRange>
-              <description>Global match enable. Don't change any other value while this one is enabled</description>
-              <name>MATCH_ENA</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[26:26]</bitRange>
-              <description>Enable year matching</description>
-              <name>YEAR_ENA</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[25:25]</bitRange>
-              <description>Enable month matching</description>
-              <name>MONTH_ENA</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[24:24]</bitRange>
-              <description>Enable day matching</description>
-              <name>DAY_ENA</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[23:12]</bitRange>
-              <description>Year</description>
-              <name>YEAR</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[11:8]</bitRange>
-              <description>Month (1..12)</description>
-              <name>MONTH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[4:0]</bitRange>
-              <description>Day of the month (1..31)</description>
-              <name>DAY</name>
-            </field>
-          </fields>
-          <name>IRQ_SETUP_0</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0014</addressOffset>
-          <description>Interrupt setup register 1</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[31:31]</bitRange>
-              <description>Enable day of the week matching</description>
-              <name>DOTW_ENA</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[30:30]</bitRange>
-              <description>Enable hour matching</description>
-              <name>HOUR_ENA</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[29:29]</bitRange>
-              <description>Enable minute matching</description>
-              <name>MIN_ENA</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[28:28]</bitRange>
-              <description>Enable second matching</description>
-              <name>SEC_ENA</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[26:24]</bitRange>
-              <description>Day of the week</description>
-              <name>DOTW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[20:16]</bitRange>
-              <description>Hours</description>
-              <name>HOUR</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[13:8]</bitRange>
-              <description>Minutes</description>
-              <name>MIN</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[5:0]</bitRange>
-              <description>Seconds</description>
-              <name>SEC</name>
-            </field>
-          </fields>
-          <name>IRQ_SETUP_1</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0018</addressOffset>
-          <description>RTC register 1.</description>
-          <fields>
-            <field>
-              <access>read-only</access>
-              <bitRange>[23:12]</bitRange>
-              <description>Year</description>
-              <name>YEAR</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[11:8]</bitRange>
-              <description>Month (1..12)</description>
-              <name>MONTH</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[4:0]</bitRange>
-              <description>Day of the month (1..31)</description>
-              <name>DAY</name>
-            </field>
-          </fields>
-          <name>RTC_1</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x001c</addressOffset>
-          <description>RTC register 0\n
-            Read this before RTC 1!</description>
-          <fields>
-            <field>
-              <access>read-only</access>
-              <bitRange>[26:24]</bitRange>
-              <description>Day of the week</description>
-              <name>DOTW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[20:16]</bitRange>
-              <description>Hours</description>
-              <name>HOUR</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[13:8]</bitRange>
-              <description>Minutes</description>
-              <name>MIN</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[5:0]</bitRange>
-              <description>Seconds</description>
-              <name>SEC</name>
-            </field>
-          </fields>
-          <name>RTC_0</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0020</addressOffset>
-          <description>Raw Interrupts</description>
-          <fields>
-            <field>
-              <access>read-only</access>
-              <bitRange>[0:0]</bitRange>
-              <name>RTC</name>
-            </field>
-          </fields>
-          <name>INTR</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0024</addressOffset>
-          <description>Interrupt Enable</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[0:0]</bitRange>
-              <name>RTC</name>
-            </field>
-          </fields>
-          <name>INTE</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0028</addressOffset>
-          <description>Interrupt Force</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[0:0]</bitRange>
-              <name>RTC</name>
-            </field>
-          </fields>
-          <name>INTF</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x002c</addressOffset>
-          <description>Interrupt status after masking &amp; forcing</description>
-          <fields>
-            <field>
-              <access>read-only</access>
-              <bitRange>[0:0]</bitRange>
-              <name>RTC</name>
-            </field>
-          </fields>
-          <name>INTS</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-      </registers>
-      <size>32</size>
-      <version>1</version>
-    </peripheral>
-    <peripheral>
-      <addressBlock>
-        <offset>0</offset>
-        <size>0x1000</size>
-        <usage>registers</usage>
-      </addressBlock>
-      <baseAddress>0x40060000</baseAddress>
-      <name>ROSC</name>
-      <registers>
-        <register>
-          <addressOffset>0x0000</addressOffset>
-          <description>Ring Oscillator control</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[23:12]</bitRange>
-              <description>On power-up this field is initialised to ENABLE\n
-                The system clock must be switched to another source before setting this field to DISABLE otherwise the chip will lock up\n
-                The 12-bit code is intended to give some protection against accidental writes. An invalid setting will enable the oscillator.</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>DISABLE</name>
-                  <value>3358</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>ENABLE</name>
-                  <value>4011</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>ENABLE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[11:0]</bitRange>
-              <description>Controls the number of delay stages in the ROSC ring\n
-                LOW uses stages 0 to 7\n
-                MEDIUM uses stages 0 to 5\n
-                HIGH uses stages 0 to 3\n
-                TOOHIGH uses stages 0 to 1 and should not be used because its frequency exceeds design specifications\n
-                The clock output will not glitch when changing the range up one step at a time\n
-                The clock output will glitch when changing the range down\n
-                Note: the values here are gray coded which is why HIGH comes before TOOHIGH</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>LOW</name>
-                  <value>4004</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>MEDIUM</name>
-                  <value>4005</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>HIGH</name>
-                  <value>4007</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>TOOHIGH</name>
-                  <value>4006</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>FREQ_RANGE</name>
-            </field>
-          </fields>
-          <name>CTRL</name>
-          <resetValue>0x00000aa0</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0004</addressOffset>
-          <description>The FREQA &amp; FREQB registers control the frequency by controlling the drive strength of each stage\n
-            The drive strength has 4 levels determined by the number of bits set\n
-            Increasing the number of bits set increases the drive strength and increases the oscillation frequency\n
-            0 bits set is the default drive strength\n
-            1 bit set doubles the drive strength\n
-            2 bits set triples drive strength\n
-            3 bits set quadruples drive strength</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[31:16]</bitRange>
-              <description>Set to 0x9696 to apply the settings\n
-                Any other value in this field will set all drive strengths to 0</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>PASS</name>
-                  <value>38550</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>PASSWD</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[14:12]</bitRange>
-              <description>Stage 3 drive strength</description>
-              <name>DS3</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[10:8]</bitRange>
-              <description>Stage 2 drive strength</description>
-              <name>DS2</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[6:4]</bitRange>
-              <description>Stage 1 drive strength</description>
-              <name>DS1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[2:0]</bitRange>
-              <description>Stage 0 drive strength</description>
-              <name>DS0</name>
-            </field>
-          </fields>
-          <name>FREQA</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0008</addressOffset>
-          <description>For a detailed description see freqa register</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[31:16]</bitRange>
-              <description>Set to 0x9696 to apply the settings\n
-                Any other value in this field will set all drive strengths to 0</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>PASS</name>
-                  <value>38550</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>PASSWD</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[14:12]</bitRange>
-              <description>Stage 7 drive strength</description>
-              <name>DS7</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[10:8]</bitRange>
-              <description>Stage 6 drive strength</description>
-              <name>DS6</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[6:4]</bitRange>
-              <description>Stage 5 drive strength</description>
-              <name>DS5</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[2:0]</bitRange>
-              <description>Stage 4 drive strength</description>
-              <name>DS4</name>
-            </field>
-          </fields>
-          <name>FREQB</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x000c</addressOffset>
-          <description>Ring Oscillator pause control\n
-            This is used to save power by pausing the ROSC\n
-            On power-up this field is initialised to WAKE\n
-            An invalid write will also select WAKE\n
-            Warning: setup the irq before selecting dormant mode</description>
-          <name>DORMANT</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0010</addressOffset>
-          <description>Controls the output divider</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[11:0]</bitRange>
-              <description>set to 0xaa0 + div where\n
-                div = 0 divides by 32\n
-                div = 1-31 divides by div\n
-                any other value sets div=31\n
-                this register resets to div=16</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>PASS</name>
-                  <value>2720</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>DIV</name>
-            </field>
-          </fields>
-          <name>DIV</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0014</addressOffset>
-          <description>Controls the phase shifted output</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[11:4]</bitRange>
-              <description>set to 0xaa\n
-                any other value enables the output with shift=0</description>
-              <name>PASSWD</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[3:3]</bitRange>
-              <description>enable the phase-shifted output\n
-                this can be changed on-the-fly</description>
-              <name>ENABLE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[2:2]</bitRange>
-              <description>invert the phase-shifted output\n
-                this is ignored when div=1</description>
-              <name>FLIP</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[1:0]</bitRange>
-              <description>phase shift the phase-shifted output by SHIFT input clocks\n
-                this can be changed on-the-fly\n
-                must be set to 0 before setting div=1</description>
-              <name>SHIFT</name>
-            </field>
-          </fields>
-          <name>PHASE</name>
-          <resetValue>0x00000008</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0018</addressOffset>
-          <description>Ring Oscillator Status</description>
-          <fields>
-            <field>
-              <access>read-only</access>
-              <bitRange>[31:31]</bitRange>
-              <description>Oscillator is running and stable</description>
-              <name>STABLE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[24:24]</bitRange>
-              <description>An invalid value has been written to CTRL_ENABLE or CTRL_FREQ_RANGE or FREQA or FREQB or DIV or PHASE or DORMANT</description>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>BADWRITE</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[16:16]</bitRange>
-              <description>post-divider is running\n
-                this resets to 0 but transitions to 1 during chip startup</description>
-              <name>DIV_RUNNING</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[12:12]</bitRange>
-              <description>Oscillator is enabled but not necessarily running and stable\n
-                this resets to 0 but transitions to 1 during chip startup</description>
-              <name>ENABLED</name>
-            </field>
-          </fields>
-          <name>STATUS</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x001c</addressOffset>
-          <description>This just reads the state of the oscillator output so randomness is compromised if the ring oscillator is stopped or run at a harmonic of the bus frequency</description>
-          <fields>
-            <field>
-              <access>read-only</access>
-              <bitRange>[0:0]</bitRange>
-              <name>RANDOMBIT</name>
-            </field>
-          </fields>
-          <name>RANDOMBIT</name>
-          <resetValue>0x00000001</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0020</addressOffset>
-          <description>A down counter running at the ROSC frequency which counts to zero and stops.\n
-            To start the counter write a non-zero value.\n
-            Can be used for short software pauses when setting up time sensitive hardware.</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[7:0]</bitRange>
-              <name>COUNT</name>
-            </field>
-          </fields>
-          <name>COUNT</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-      </registers>
-      <size>32</size>
-      <version>1</version>
-    </peripheral>
-    <peripheral>
-      <addressBlock>
-        <offset>0</offset>
-        <size>0x1000</size>
-        <usage>registers</usage>
-      </addressBlock>
-      <baseAddress>0x40064000</baseAddress>
-      <description>control and status for on-chip voltage regulator and chip level reset subsystem</description>
-      <name>VREG_AND_CHIP_RESET</name>
-      <registers>
-        <register>
-          <addressOffset>0x0000</addressOffset>
-          <description>Voltage regulator control and status</description>
-          <fields>
-            <field>
-              <access>read-only</access>
-              <bitRange>[12:12]</bitRange>
-              <description>regulation status\n
-                0=not in regulation, 1=in regulation</description>
-              <name>ROK</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[7:4]</bitRange>
-              <description>output voltage select\n
-                0000 to 0101 - 0.80V\n
-                0110         - 0.85V\n
-                0111         - 0.90V\n
-                1000         - 0.95V\n
-                1001         - 1.00V\n
-                1010         - 1.05V\n
-                1011         - 1.10V (default)\n
-                1100         - 1.15V\n
-                1101         - 1.20V\n
-                1110         - 1.25V\n
-                1111         - 1.30V</description>
-              <name>VSEL</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[1:1]</bitRange>
-              <description>high impedance mode select\n
-                0=not in high impedance mode, 1=in high impedance mode</description>
-              <name>HIZ</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[0:0]</bitRange>
-              <description>enable\n
-                0=not enabled, 1=enabled</description>
-              <name>EN</name>
-            </field>
-          </fields>
-          <name>VREG</name>
-          <resetValue>0x000000b1</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0004</addressOffset>
-          <description>brown-out detection control</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[7:4]</bitRange>
-              <description>threshold select\n
-                0000 - 0.473V\n
-                0001 - 0.516V\n
-                0010 - 0.559V\n
-                0011 - 0.602V\n
-                0100 - 0.645V\n
-                0101 - 0.688V\n
-                0110 - 0.731V\n
-                0111 - 0.774V\n
-                1000 - 0.817V\n
-                1001 - 0.860V (default)\n
-                1010 - 0.903V\n
-                1011 - 0.946V\n
-                1100 - 0.989V\n
-                1101 - 1.032V\n
-                1110 - 1.075V\n
-                1111 - 1.118V</description>
-              <name>VSEL</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[0:0]</bitRange>
-              <description>enable\n
-                0=not enabled, 1=enabled</description>
-              <name>EN</name>
-            </field>
-          </fields>
-          <name>BOD</name>
-          <resetValue>0x00000091</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0008</addressOffset>
-          <description>Chip reset control and status</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[24:24]</bitRange>
-              <description>This is set by psm_restart from the debugger.\n
-                Its purpose is to branch bootcode to a safe mode when the debugger has issued a psm_restart in order to recover from a boot lock-up.\n
-                In the safe mode the debugger can repair the boot code, clear this flag then reboot the processor.</description>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>PSM_RESTART_FLAG</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[20:20]</bitRange>
-              <description>Last reset was from the debug port</description>
-              <name>HAD_PSM_RESTART</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[16:16]</bitRange>
-              <description>Last reset was from the RUN pin</description>
-              <name>HAD_RUN</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[8:8]</bitRange>
-              <description>Last reset was from the power-on reset or brown-out detection blocks</description>
-              <name>HAD_POR</name>
-            </field>
-          </fields>
-          <name>CHIP_RESET</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-      </registers>
-      <size>32</size>
-      <version>1</version>
-    </peripheral>
-    <peripheral>
-      <addressBlock>
-        <offset>0</offset>
-        <size>0x1000</size>
-        <usage>registers</usage>
-      </addressBlock>
-      <baseAddress>0x4006c000</baseAddress>
-      <description>Testbench manager. Allows the programmer to know what platform their software is running on.</description>
-      <name>TBMAN</name>
-      <registers>
-        <register>
-          <addressOffset>0x0000</addressOffset>
-          <description>Indicates the type of platform in use</description>
-          <fields>
-            <field>
-              <access>read-only</access>
-              <bitRange>[1:1]</bitRange>
-              <description>Indicates the platform is an FPGA</description>
-              <name>FPGA</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[0:0]</bitRange>
-              <description>Indicates the platform is an ASIC</description>
-              <name>ASIC</name>
-            </field>
-          </fields>
-          <name>PLATFORM</name>
-          <resetValue>0x00000005</resetValue>
-        </register>
-      </registers>
-      <size>32</size>
-      <version>1</version>
-    </peripheral>
-    <peripheral>
-      <addressBlock>
-        <offset>0</offset>
-        <size>0x1000</size>
-        <usage>registers</usage>
-      </addressBlock>
-      <baseAddress>0x50000000</baseAddress>
-      <description>DMA with separate read and write masters</description>
-      <interrupt>
-        <name>DMA_IRQ_0</name>
-        <value>11</value>
-      </interrupt>
-      <interrupt>
-        <name>DMA_IRQ_1</name>
-        <value>12</value>
-      </interrupt>
-      <name>DMA</name>
-      <registers>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x0000</addressOffset>
-          <description>DMA Channel 0 Read Address pointer\n
-            This register updates automatically each time a read completes. The current value is the next address to be read by this channel.</description>
-          <name>CH0_READ_ADDR</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x0004</addressOffset>
-          <description>DMA Channel 0 Write Address pointer\n
-            This register updates automatically each time a write completes. The current value is the next address to be written by this channel.</description>
-          <name>CH0_WRITE_ADDR</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x0008</addressOffset>
-          <description>DMA Channel 0 Transfer Count\n
-            Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).\n\n
-            When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.\n\n
-            Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.\n\n
-            The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD.</description>
-          <name>CH0_TRANS_COUNT</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x000c</addressOffset>
-          <description>DMA Channel 0 Control and Status</description>
-          <fields>
-            <field>
-              <access>read-only</access>
-              <bitRange>[31:31]</bitRange>
-              <description>Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag.</description>
-              <name>AHB_ERROR</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[30:30]</bitRange>
-              <description>If 1, the channel received a read bus error. Write one to clear.\n
-                READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)</description>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>READ_ERROR</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[29:29]</bitRange>
-              <description>If 1, the channel received a write bus error. Write one to clear.\n
-                WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)</description>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>WRITE_ERROR</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[24:24]</bitRange>
-              <description>This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.\n\n
-                To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT.</description>
-              <name>BUSY</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[23:23]</bitRange>
-              <description>If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.\n\n
-                This allows checksum to be enabled or disabled on a per-control- block basis.</description>
-              <name>SNIFF_EN</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[22:22]</bitRange>
-              <description>Apply byte-swap transformation to DMA data.\n
-                For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.</description>
-              <name>BSWAP</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[21:21]</bitRange>
-              <description>In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.\n\n
-                This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.</description>
-              <name>IRQ_QUIET</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[20:15]</bitRange>
-              <description>Select a Transfer Request signal.\n
-                The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).\n
-                0x0 to 0x3a -&gt; select DREQ n as TREQ</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>Select Timer 0 as TREQ</description>
-                  <name>TIMER0</name>
-                  <value>59</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>Select Timer 1 as TREQ</description>
-                  <name>TIMER1</name>
-                  <value>60</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>Select Timer 2 as TREQ (Optional)</description>
-                  <name>TIMER2</name>
-                  <value>61</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>Select Timer 3 as TREQ (Optional)</description>
-                  <name>TIMER3</name>
-                  <value>62</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>Permanent request, for unpaced transfers.</description>
-                  <name>PERMANENT</name>
-                  <value>63</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>TREQ_SEL</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[14:11]</bitRange>
-              <description>When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.</description>
-              <name>CHAIN_TO</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[10:10]</bitRange>
-              <description>Select whether RING_SIZE applies to read or write addresses.\n
-                If 0, read addresses are wrapped on a (1 &lt;&lt; RING_SIZE) boundary. If 1, write addresses are wrapped.</description>
-              <name>RING_SEL</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[9:6]</bitRange>
-              <description>Size of address wrap region. If 0, don't wrap. For values n &gt; 0, only the lower n bits of the address will change. This wraps the address on a (1 &lt;&lt; n) byte boundary, facilitating access to naturally-aligned ring buffers.\n\n
-                Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>RING_NONE</name>
-                  <value>0</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>RING_SIZE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[5:5]</bitRange>
-              <description>If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.\n\n
-                Generally this should be disabled for memory-to-peripheral transfers.</description>
-              <name>INCR_WRITE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[4:4]</bitRange>
-              <description>If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.\n\n
-                Generally this should be disabled for peripheral-to-memory transfers.</description>
-              <name>INCR_READ</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[3:2]</bitRange>
-              <description>Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>SIZE_BYTE</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>SIZE_HALFWORD</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>SIZE_WORD</name>
-                  <value>2</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>DATA_SIZE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[1:1]</bitRange>
-              <description>HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.\n\n
-                This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.</description>
-              <name>HIGH_PRIORITY</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[0:0]</bitRange>
-              <description>DMA Channel Enable.\n
-                When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)</description>
-              <name>EN</name>
-            </field>
-          </fields>
-          <name>CH0_CTRL_TRIG</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x0010</addressOffset>
-          <description>Alias for channel 0 CTRL register</description>
-          <name>CH0_AL1_CTRL</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x0014</addressOffset>
-          <description>Alias for channel 0 READ_ADDR register</description>
-          <name>CH0_AL1_READ_ADDR</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x0018</addressOffset>
-          <description>Alias for channel 0 WRITE_ADDR register</description>
-          <name>CH0_AL1_WRITE_ADDR</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x001c</addressOffset>
-          <description>Alias for channel 0 TRANS_COUNT register\n
-            This is a trigger register (0xc). Writing a nonzero value will\n
-            reload the channel counter and start the channel.</description>
-          <name>CH0_AL1_TRANS_COUNT_TRIG</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x0020</addressOffset>
-          <description>Alias for channel 0 CTRL register</description>
-          <name>CH0_AL2_CTRL</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x0024</addressOffset>
-          <description>Alias for channel 0 TRANS_COUNT register</description>
-          <name>CH0_AL2_TRANS_COUNT</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x0028</addressOffset>
-          <description>Alias for channel 0 READ_ADDR register</description>
-          <name>CH0_AL2_READ_ADDR</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x002c</addressOffset>
-          <description>Alias for channel 0 WRITE_ADDR register\n
-            This is a trigger register (0xc). Writing a nonzero value will\n
-            reload the channel counter and start the channel.</description>
-          <name>CH0_AL2_WRITE_ADDR_TRIG</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x0030</addressOffset>
-          <description>Alias for channel 0 CTRL register</description>
-          <name>CH0_AL3_CTRL</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x0034</addressOffset>
-          <description>Alias for channel 0 WRITE_ADDR register</description>
-          <name>CH0_AL3_WRITE_ADDR</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x0038</addressOffset>
-          <description>Alias for channel 0 TRANS_COUNT register</description>
-          <name>CH0_AL3_TRANS_COUNT</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x003c</addressOffset>
-          <description>Alias for channel 0 READ_ADDR register\n
-            This is a trigger register (0xc). Writing a nonzero value will\n
-            reload the channel counter and start the channel.</description>
-          <name>CH0_AL3_READ_ADDR_TRIG</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x0040</addressOffset>
-          <description>DMA Channel 1 Read Address pointer\n
-            This register updates automatically each time a read completes. The current value is the next address to be read by this channel.</description>
-          <name>CH1_READ_ADDR</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x0044</addressOffset>
-          <description>DMA Channel 1 Write Address pointer\n
-            This register updates automatically each time a write completes. The current value is the next address to be written by this channel.</description>
-          <name>CH1_WRITE_ADDR</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x0048</addressOffset>
-          <description>DMA Channel 1 Transfer Count\n
-            Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).\n\n
-            When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.\n\n
-            Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.\n\n
-            The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD.</description>
-          <name>CH1_TRANS_COUNT</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x004c</addressOffset>
-          <description>DMA Channel 1 Control and Status</description>
-          <fields>
-            <field>
-              <access>read-only</access>
-              <bitRange>[31:31]</bitRange>
-              <description>Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag.</description>
-              <name>AHB_ERROR</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[30:30]</bitRange>
-              <description>If 1, the channel received a read bus error. Write one to clear.\n
-                READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)</description>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>READ_ERROR</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[29:29]</bitRange>
-              <description>If 1, the channel received a write bus error. Write one to clear.\n
-                WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)</description>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>WRITE_ERROR</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[24:24]</bitRange>
-              <description>This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.\n\n
-                To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT.</description>
-              <name>BUSY</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[23:23]</bitRange>
-              <description>If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.\n\n
-                This allows checksum to be enabled or disabled on a per-control- block basis.</description>
-              <name>SNIFF_EN</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[22:22]</bitRange>
-              <description>Apply byte-swap transformation to DMA data.\n
-                For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.</description>
-              <name>BSWAP</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[21:21]</bitRange>
-              <description>In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.\n\n
-                This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.</description>
-              <name>IRQ_QUIET</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[20:15]</bitRange>
-              <description>Select a Transfer Request signal.\n
-                The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).\n
-                0x0 to 0x3a -&gt; select DREQ n as TREQ</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>Select Timer 0 as TREQ</description>
-                  <name>TIMER0</name>
-                  <value>59</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>Select Timer 1 as TREQ</description>
-                  <name>TIMER1</name>
-                  <value>60</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>Select Timer 2 as TREQ (Optional)</description>
-                  <name>TIMER2</name>
-                  <value>61</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>Select Timer 3 as TREQ (Optional)</description>
-                  <name>TIMER3</name>
-                  <value>62</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>Permanent request, for unpaced transfers.</description>
-                  <name>PERMANENT</name>
-                  <value>63</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>TREQ_SEL</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[14:11]</bitRange>
-              <description>When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.</description>
-              <name>CHAIN_TO</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[10:10]</bitRange>
-              <description>Select whether RING_SIZE applies to read or write addresses.\n
-                If 0, read addresses are wrapped on a (1 &lt;&lt; RING_SIZE) boundary. If 1, write addresses are wrapped.</description>
-              <name>RING_SEL</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[9:6]</bitRange>
-              <description>Size of address wrap region. If 0, don't wrap. For values n &gt; 0, only the lower n bits of the address will change. This wraps the address on a (1 &lt;&lt; n) byte boundary, facilitating access to naturally-aligned ring buffers.\n\n
-                Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>RING_NONE</name>
-                  <value>0</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>RING_SIZE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[5:5]</bitRange>
-              <description>If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.\n\n
-                Generally this should be disabled for memory-to-peripheral transfers.</description>
-              <name>INCR_WRITE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[4:4]</bitRange>
-              <description>If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.\n\n
-                Generally this should be disabled for peripheral-to-memory transfers.</description>
-              <name>INCR_READ</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[3:2]</bitRange>
-              <description>Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>SIZE_BYTE</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>SIZE_HALFWORD</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>SIZE_WORD</name>
-                  <value>2</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>DATA_SIZE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[1:1]</bitRange>
-              <description>HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.\n\n
-                This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.</description>
-              <name>HIGH_PRIORITY</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[0:0]</bitRange>
-              <description>DMA Channel Enable.\n
-                When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)</description>
-              <name>EN</name>
-            </field>
-          </fields>
-          <name>CH1_CTRL_TRIG</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x0050</addressOffset>
-          <description>Alias for channel 1 CTRL register</description>
-          <name>CH1_AL1_CTRL</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x0054</addressOffset>
-          <description>Alias for channel 1 READ_ADDR register</description>
-          <name>CH1_AL1_READ_ADDR</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x0058</addressOffset>
-          <description>Alias for channel 1 WRITE_ADDR register</description>
-          <name>CH1_AL1_WRITE_ADDR</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x005c</addressOffset>
-          <description>Alias for channel 1 TRANS_COUNT register\n
-            This is a trigger register (0xc). Writing a nonzero value will\n
-            reload the channel counter and start the channel.</description>
-          <name>CH1_AL1_TRANS_COUNT_TRIG</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x0060</addressOffset>
-          <description>Alias for channel 1 CTRL register</description>
-          <name>CH1_AL2_CTRL</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x0064</addressOffset>
-          <description>Alias for channel 1 TRANS_COUNT register</description>
-          <name>CH1_AL2_TRANS_COUNT</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x0068</addressOffset>
-          <description>Alias for channel 1 READ_ADDR register</description>
-          <name>CH1_AL2_READ_ADDR</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x006c</addressOffset>
-          <description>Alias for channel 1 WRITE_ADDR register\n
-            This is a trigger register (0xc). Writing a nonzero value will\n
-            reload the channel counter and start the channel.</description>
-          <name>CH1_AL2_WRITE_ADDR_TRIG</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x0070</addressOffset>
-          <description>Alias for channel 1 CTRL register</description>
-          <name>CH1_AL3_CTRL</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x0074</addressOffset>
-          <description>Alias for channel 1 WRITE_ADDR register</description>
-          <name>CH1_AL3_WRITE_ADDR</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x0078</addressOffset>
-          <description>Alias for channel 1 TRANS_COUNT register</description>
-          <name>CH1_AL3_TRANS_COUNT</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x007c</addressOffset>
-          <description>Alias for channel 1 READ_ADDR register\n
-            This is a trigger register (0xc). Writing a nonzero value will\n
-            reload the channel counter and start the channel.</description>
-          <name>CH1_AL3_READ_ADDR_TRIG</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x0080</addressOffset>
-          <description>DMA Channel 2 Read Address pointer\n
-            This register updates automatically each time a read completes. The current value is the next address to be read by this channel.</description>
-          <name>CH2_READ_ADDR</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x0084</addressOffset>
-          <description>DMA Channel 2 Write Address pointer\n
-            This register updates automatically each time a write completes. The current value is the next address to be written by this channel.</description>
-          <name>CH2_WRITE_ADDR</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x0088</addressOffset>
-          <description>DMA Channel 2 Transfer Count\n
-            Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).\n\n
-            When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.\n\n
-            Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.\n\n
-            The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD.</description>
-          <name>CH2_TRANS_COUNT</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x008c</addressOffset>
-          <description>DMA Channel 2 Control and Status</description>
-          <fields>
-            <field>
-              <access>read-only</access>
-              <bitRange>[31:31]</bitRange>
-              <description>Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag.</description>
-              <name>AHB_ERROR</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[30:30]</bitRange>
-              <description>If 1, the channel received a read bus error. Write one to clear.\n
-                READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)</description>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>READ_ERROR</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[29:29]</bitRange>
-              <description>If 1, the channel received a write bus error. Write one to clear.\n
-                WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)</description>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>WRITE_ERROR</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[24:24]</bitRange>
-              <description>This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.\n\n
-                To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT.</description>
-              <name>BUSY</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[23:23]</bitRange>
-              <description>If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.\n\n
-                This allows checksum to be enabled or disabled on a per-control- block basis.</description>
-              <name>SNIFF_EN</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[22:22]</bitRange>
-              <description>Apply byte-swap transformation to DMA data.\n
-                For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.</description>
-              <name>BSWAP</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[21:21]</bitRange>
-              <description>In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.\n\n
-                This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.</description>
-              <name>IRQ_QUIET</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[20:15]</bitRange>
-              <description>Select a Transfer Request signal.\n
-                The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).\n
-                0x0 to 0x3a -&gt; select DREQ n as TREQ</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>Select Timer 0 as TREQ</description>
-                  <name>TIMER0</name>
-                  <value>59</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>Select Timer 1 as TREQ</description>
-                  <name>TIMER1</name>
-                  <value>60</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>Select Timer 2 as TREQ (Optional)</description>
-                  <name>TIMER2</name>
-                  <value>61</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>Select Timer 3 as TREQ (Optional)</description>
-                  <name>TIMER3</name>
-                  <value>62</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>Permanent request, for unpaced transfers.</description>
-                  <name>PERMANENT</name>
-                  <value>63</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>TREQ_SEL</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[14:11]</bitRange>
-              <description>When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.</description>
-              <name>CHAIN_TO</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[10:10]</bitRange>
-              <description>Select whether RING_SIZE applies to read or write addresses.\n
-                If 0, read addresses are wrapped on a (1 &lt;&lt; RING_SIZE) boundary. If 1, write addresses are wrapped.</description>
-              <name>RING_SEL</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[9:6]</bitRange>
-              <description>Size of address wrap region. If 0, don't wrap. For values n &gt; 0, only the lower n bits of the address will change. This wraps the address on a (1 &lt;&lt; n) byte boundary, facilitating access to naturally-aligned ring buffers.\n\n
-                Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>RING_NONE</name>
-                  <value>0</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>RING_SIZE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[5:5]</bitRange>
-              <description>If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.\n\n
-                Generally this should be disabled for memory-to-peripheral transfers.</description>
-              <name>INCR_WRITE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[4:4]</bitRange>
-              <description>If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.\n\n
-                Generally this should be disabled for peripheral-to-memory transfers.</description>
-              <name>INCR_READ</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[3:2]</bitRange>
-              <description>Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>SIZE_BYTE</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>SIZE_HALFWORD</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>SIZE_WORD</name>
-                  <value>2</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>DATA_SIZE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[1:1]</bitRange>
-              <description>HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.\n\n
-                This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.</description>
-              <name>HIGH_PRIORITY</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[0:0]</bitRange>
-              <description>DMA Channel Enable.\n
-                When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)</description>
-              <name>EN</name>
-            </field>
-          </fields>
-          <name>CH2_CTRL_TRIG</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x0090</addressOffset>
-          <description>Alias for channel 2 CTRL register</description>
-          <name>CH2_AL1_CTRL</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x0094</addressOffset>
-          <description>Alias for channel 2 READ_ADDR register</description>
-          <name>CH2_AL1_READ_ADDR</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x0098</addressOffset>
-          <description>Alias for channel 2 WRITE_ADDR register</description>
-          <name>CH2_AL1_WRITE_ADDR</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x009c</addressOffset>
-          <description>Alias for channel 2 TRANS_COUNT register\n
-            This is a trigger register (0xc). Writing a nonzero value will\n
-            reload the channel counter and start the channel.</description>
-          <name>CH2_AL1_TRANS_COUNT_TRIG</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x00a0</addressOffset>
-          <description>Alias for channel 2 CTRL register</description>
-          <name>CH2_AL2_CTRL</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x00a4</addressOffset>
-          <description>Alias for channel 2 TRANS_COUNT register</description>
-          <name>CH2_AL2_TRANS_COUNT</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x00a8</addressOffset>
-          <description>Alias for channel 2 READ_ADDR register</description>
-          <name>CH2_AL2_READ_ADDR</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x00ac</addressOffset>
-          <description>Alias for channel 2 WRITE_ADDR register\n
-            This is a trigger register (0xc). Writing a nonzero value will\n
-            reload the channel counter and start the channel.</description>
-          <name>CH2_AL2_WRITE_ADDR_TRIG</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x00b0</addressOffset>
-          <description>Alias for channel 2 CTRL register</description>
-          <name>CH2_AL3_CTRL</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x00b4</addressOffset>
-          <description>Alias for channel 2 WRITE_ADDR register</description>
-          <name>CH2_AL3_WRITE_ADDR</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x00b8</addressOffset>
-          <description>Alias for channel 2 TRANS_COUNT register</description>
-          <name>CH2_AL3_TRANS_COUNT</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x00bc</addressOffset>
-          <description>Alias for channel 2 READ_ADDR register\n
-            This is a trigger register (0xc). Writing a nonzero value will\n
-            reload the channel counter and start the channel.</description>
-          <name>CH2_AL3_READ_ADDR_TRIG</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x00c0</addressOffset>
-          <description>DMA Channel 3 Read Address pointer\n
-            This register updates automatically each time a read completes. The current value is the next address to be read by this channel.</description>
-          <name>CH3_READ_ADDR</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x00c4</addressOffset>
-          <description>DMA Channel 3 Write Address pointer\n
-            This register updates automatically each time a write completes. The current value is the next address to be written by this channel.</description>
-          <name>CH3_WRITE_ADDR</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x00c8</addressOffset>
-          <description>DMA Channel 3 Transfer Count\n
-            Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).\n\n
-            When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.\n\n
-            Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.\n\n
-            The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD.</description>
-          <name>CH3_TRANS_COUNT</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x00cc</addressOffset>
-          <description>DMA Channel 3 Control and Status</description>
-          <fields>
-            <field>
-              <access>read-only</access>
-              <bitRange>[31:31]</bitRange>
-              <description>Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag.</description>
-              <name>AHB_ERROR</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[30:30]</bitRange>
-              <description>If 1, the channel received a read bus error. Write one to clear.\n
-                READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)</description>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>READ_ERROR</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[29:29]</bitRange>
-              <description>If 1, the channel received a write bus error. Write one to clear.\n
-                WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)</description>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>WRITE_ERROR</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[24:24]</bitRange>
-              <description>This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.\n\n
-                To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT.</description>
-              <name>BUSY</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[23:23]</bitRange>
-              <description>If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.\n\n
-                This allows checksum to be enabled or disabled on a per-control- block basis.</description>
-              <name>SNIFF_EN</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[22:22]</bitRange>
-              <description>Apply byte-swap transformation to DMA data.\n
-                For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.</description>
-              <name>BSWAP</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[21:21]</bitRange>
-              <description>In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.\n\n
-                This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.</description>
-              <name>IRQ_QUIET</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[20:15]</bitRange>
-              <description>Select a Transfer Request signal.\n
-                The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).\n
-                0x0 to 0x3a -&gt; select DREQ n as TREQ</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>Select Timer 0 as TREQ</description>
-                  <name>TIMER0</name>
-                  <value>59</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>Select Timer 1 as TREQ</description>
-                  <name>TIMER1</name>
-                  <value>60</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>Select Timer 2 as TREQ (Optional)</description>
-                  <name>TIMER2</name>
-                  <value>61</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>Select Timer 3 as TREQ (Optional)</description>
-                  <name>TIMER3</name>
-                  <value>62</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>Permanent request, for unpaced transfers.</description>
-                  <name>PERMANENT</name>
-                  <value>63</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>TREQ_SEL</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[14:11]</bitRange>
-              <description>When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.</description>
-              <name>CHAIN_TO</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[10:10]</bitRange>
-              <description>Select whether RING_SIZE applies to read or write addresses.\n
-                If 0, read addresses are wrapped on a (1 &lt;&lt; RING_SIZE) boundary. If 1, write addresses are wrapped.</description>
-              <name>RING_SEL</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[9:6]</bitRange>
-              <description>Size of address wrap region. If 0, don't wrap. For values n &gt; 0, only the lower n bits of the address will change. This wraps the address on a (1 &lt;&lt; n) byte boundary, facilitating access to naturally-aligned ring buffers.\n\n
-                Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>RING_NONE</name>
-                  <value>0</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>RING_SIZE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[5:5]</bitRange>
-              <description>If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.\n\n
-                Generally this should be disabled for memory-to-peripheral transfers.</description>
-              <name>INCR_WRITE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[4:4]</bitRange>
-              <description>If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.\n\n
-                Generally this should be disabled for peripheral-to-memory transfers.</description>
-              <name>INCR_READ</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[3:2]</bitRange>
-              <description>Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>SIZE_BYTE</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>SIZE_HALFWORD</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>SIZE_WORD</name>
-                  <value>2</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>DATA_SIZE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[1:1]</bitRange>
-              <description>HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.\n\n
-                This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.</description>
-              <name>HIGH_PRIORITY</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[0:0]</bitRange>
-              <description>DMA Channel Enable.\n
-                When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)</description>
-              <name>EN</name>
-            </field>
-          </fields>
-          <name>CH3_CTRL_TRIG</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x00d0</addressOffset>
-          <description>Alias for channel 3 CTRL register</description>
-          <name>CH3_AL1_CTRL</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x00d4</addressOffset>
-          <description>Alias for channel 3 READ_ADDR register</description>
-          <name>CH3_AL1_READ_ADDR</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x00d8</addressOffset>
-          <description>Alias for channel 3 WRITE_ADDR register</description>
-          <name>CH3_AL1_WRITE_ADDR</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x00dc</addressOffset>
-          <description>Alias for channel 3 TRANS_COUNT register\n
-            This is a trigger register (0xc). Writing a nonzero value will\n
-            reload the channel counter and start the channel.</description>
-          <name>CH3_AL1_TRANS_COUNT_TRIG</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x00e0</addressOffset>
-          <description>Alias for channel 3 CTRL register</description>
-          <name>CH3_AL2_CTRL</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x00e4</addressOffset>
-          <description>Alias for channel 3 TRANS_COUNT register</description>
-          <name>CH3_AL2_TRANS_COUNT</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x00e8</addressOffset>
-          <description>Alias for channel 3 READ_ADDR register</description>
-          <name>CH3_AL2_READ_ADDR</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x00ec</addressOffset>
-          <description>Alias for channel 3 WRITE_ADDR register\n
-            This is a trigger register (0xc). Writing a nonzero value will\n
-            reload the channel counter and start the channel.</description>
-          <name>CH3_AL2_WRITE_ADDR_TRIG</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x00f0</addressOffset>
-          <description>Alias for channel 3 CTRL register</description>
-          <name>CH3_AL3_CTRL</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x00f4</addressOffset>
-          <description>Alias for channel 3 WRITE_ADDR register</description>
-          <name>CH3_AL3_WRITE_ADDR</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x00f8</addressOffset>
-          <description>Alias for channel 3 TRANS_COUNT register</description>
-          <name>CH3_AL3_TRANS_COUNT</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x00fc</addressOffset>
-          <description>Alias for channel 3 READ_ADDR register\n
-            This is a trigger register (0xc). Writing a nonzero value will\n
-            reload the channel counter and start the channel.</description>
-          <name>CH3_AL3_READ_ADDR_TRIG</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x0100</addressOffset>
-          <description>DMA Channel 4 Read Address pointer\n
-            This register updates automatically each time a read completes. The current value is the next address to be read by this channel.</description>
-          <name>CH4_READ_ADDR</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x0104</addressOffset>
-          <description>DMA Channel 4 Write Address pointer\n
-            This register updates automatically each time a write completes. The current value is the next address to be written by this channel.</description>
-          <name>CH4_WRITE_ADDR</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x0108</addressOffset>
-          <description>DMA Channel 4 Transfer Count\n
-            Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).\n\n
-            When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.\n\n
-            Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.\n\n
-            The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD.</description>
-          <name>CH4_TRANS_COUNT</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x010c</addressOffset>
-          <description>DMA Channel 4 Control and Status</description>
-          <fields>
-            <field>
-              <access>read-only</access>
-              <bitRange>[31:31]</bitRange>
-              <description>Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag.</description>
-              <name>AHB_ERROR</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[30:30]</bitRange>
-              <description>If 1, the channel received a read bus error. Write one to clear.\n
-                READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)</description>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>READ_ERROR</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[29:29]</bitRange>
-              <description>If 1, the channel received a write bus error. Write one to clear.\n
-                WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)</description>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>WRITE_ERROR</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[24:24]</bitRange>
-              <description>This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.\n\n
-                To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT.</description>
-              <name>BUSY</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[23:23]</bitRange>
-              <description>If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.\n\n
-                This allows checksum to be enabled or disabled on a per-control- block basis.</description>
-              <name>SNIFF_EN</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[22:22]</bitRange>
-              <description>Apply byte-swap transformation to DMA data.\n
-                For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.</description>
-              <name>BSWAP</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[21:21]</bitRange>
-              <description>In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.\n\n
-                This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.</description>
-              <name>IRQ_QUIET</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[20:15]</bitRange>
-              <description>Select a Transfer Request signal.\n
-                The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).\n
-                0x0 to 0x3a -&gt; select DREQ n as TREQ</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>Select Timer 0 as TREQ</description>
-                  <name>TIMER0</name>
-                  <value>59</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>Select Timer 1 as TREQ</description>
-                  <name>TIMER1</name>
-                  <value>60</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>Select Timer 2 as TREQ (Optional)</description>
-                  <name>TIMER2</name>
-                  <value>61</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>Select Timer 3 as TREQ (Optional)</description>
-                  <name>TIMER3</name>
-                  <value>62</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>Permanent request, for unpaced transfers.</description>
-                  <name>PERMANENT</name>
-                  <value>63</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>TREQ_SEL</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[14:11]</bitRange>
-              <description>When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.</description>
-              <name>CHAIN_TO</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[10:10]</bitRange>
-              <description>Select whether RING_SIZE applies to read or write addresses.\n
-                If 0, read addresses are wrapped on a (1 &lt;&lt; RING_SIZE) boundary. If 1, write addresses are wrapped.</description>
-              <name>RING_SEL</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[9:6]</bitRange>
-              <description>Size of address wrap region. If 0, don't wrap. For values n &gt; 0, only the lower n bits of the address will change. This wraps the address on a (1 &lt;&lt; n) byte boundary, facilitating access to naturally-aligned ring buffers.\n\n
-                Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>RING_NONE</name>
-                  <value>0</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>RING_SIZE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[5:5]</bitRange>
-              <description>If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.\n\n
-                Generally this should be disabled for memory-to-peripheral transfers.</description>
-              <name>INCR_WRITE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[4:4]</bitRange>
-              <description>If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.\n\n
-                Generally this should be disabled for peripheral-to-memory transfers.</description>
-              <name>INCR_READ</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[3:2]</bitRange>
-              <description>Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>SIZE_BYTE</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>SIZE_HALFWORD</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>SIZE_WORD</name>
-                  <value>2</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>DATA_SIZE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[1:1]</bitRange>
-              <description>HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.\n\n
-                This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.</description>
-              <name>HIGH_PRIORITY</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[0:0]</bitRange>
-              <description>DMA Channel Enable.\n
-                When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)</description>
-              <name>EN</name>
-            </field>
-          </fields>
-          <name>CH4_CTRL_TRIG</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x0110</addressOffset>
-          <description>Alias for channel 4 CTRL register</description>
-          <name>CH4_AL1_CTRL</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x0114</addressOffset>
-          <description>Alias for channel 4 READ_ADDR register</description>
-          <name>CH4_AL1_READ_ADDR</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x0118</addressOffset>
-          <description>Alias for channel 4 WRITE_ADDR register</description>
-          <name>CH4_AL1_WRITE_ADDR</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x011c</addressOffset>
-          <description>Alias for channel 4 TRANS_COUNT register\n
-            This is a trigger register (0xc). Writing a nonzero value will\n
-            reload the channel counter and start the channel.</description>
-          <name>CH4_AL1_TRANS_COUNT_TRIG</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x0120</addressOffset>
-          <description>Alias for channel 4 CTRL register</description>
-          <name>CH4_AL2_CTRL</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x0124</addressOffset>
-          <description>Alias for channel 4 TRANS_COUNT register</description>
-          <name>CH4_AL2_TRANS_COUNT</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x0128</addressOffset>
-          <description>Alias for channel 4 READ_ADDR register</description>
-          <name>CH4_AL2_READ_ADDR</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x012c</addressOffset>
-          <description>Alias for channel 4 WRITE_ADDR register\n
-            This is a trigger register (0xc). Writing a nonzero value will\n
-            reload the channel counter and start the channel.</description>
-          <name>CH4_AL2_WRITE_ADDR_TRIG</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x0130</addressOffset>
-          <description>Alias for channel 4 CTRL register</description>
-          <name>CH4_AL3_CTRL</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x0134</addressOffset>
-          <description>Alias for channel 4 WRITE_ADDR register</description>
-          <name>CH4_AL3_WRITE_ADDR</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x0138</addressOffset>
-          <description>Alias for channel 4 TRANS_COUNT register</description>
-          <name>CH4_AL3_TRANS_COUNT</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x013c</addressOffset>
-          <description>Alias for channel 4 READ_ADDR register\n
-            This is a trigger register (0xc). Writing a nonzero value will\n
-            reload the channel counter and start the channel.</description>
-          <name>CH4_AL3_READ_ADDR_TRIG</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x0140</addressOffset>
-          <description>DMA Channel 5 Read Address pointer\n
-            This register updates automatically each time a read completes. The current value is the next address to be read by this channel.</description>
-          <name>CH5_READ_ADDR</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x0144</addressOffset>
-          <description>DMA Channel 5 Write Address pointer\n
-            This register updates automatically each time a write completes. The current value is the next address to be written by this channel.</description>
-          <name>CH5_WRITE_ADDR</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x0148</addressOffset>
-          <description>DMA Channel 5 Transfer Count\n
-            Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).\n\n
-            When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.\n\n
-            Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.\n\n
-            The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD.</description>
-          <name>CH5_TRANS_COUNT</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x014c</addressOffset>
-          <description>DMA Channel 5 Control and Status</description>
-          <fields>
-            <field>
-              <access>read-only</access>
-              <bitRange>[31:31]</bitRange>
-              <description>Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag.</description>
-              <name>AHB_ERROR</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[30:30]</bitRange>
-              <description>If 1, the channel received a read bus error. Write one to clear.\n
-                READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)</description>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>READ_ERROR</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[29:29]</bitRange>
-              <description>If 1, the channel received a write bus error. Write one to clear.\n
-                WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)</description>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>WRITE_ERROR</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[24:24]</bitRange>
-              <description>This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.\n\n
-                To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT.</description>
-              <name>BUSY</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[23:23]</bitRange>
-              <description>If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.\n\n
-                This allows checksum to be enabled or disabled on a per-control- block basis.</description>
-              <name>SNIFF_EN</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[22:22]</bitRange>
-              <description>Apply byte-swap transformation to DMA data.\n
-                For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.</description>
-              <name>BSWAP</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[21:21]</bitRange>
-              <description>In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.\n\n
-                This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.</description>
-              <name>IRQ_QUIET</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[20:15]</bitRange>
-              <description>Select a Transfer Request signal.\n
-                The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).\n
-                0x0 to 0x3a -&gt; select DREQ n as TREQ</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>Select Timer 0 as TREQ</description>
-                  <name>TIMER0</name>
-                  <value>59</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>Select Timer 1 as TREQ</description>
-                  <name>TIMER1</name>
-                  <value>60</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>Select Timer 2 as TREQ (Optional)</description>
-                  <name>TIMER2</name>
-                  <value>61</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>Select Timer 3 as TREQ (Optional)</description>
-                  <name>TIMER3</name>
-                  <value>62</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>Permanent request, for unpaced transfers.</description>
-                  <name>PERMANENT</name>
-                  <value>63</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>TREQ_SEL</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[14:11]</bitRange>
-              <description>When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.</description>
-              <name>CHAIN_TO</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[10:10]</bitRange>
-              <description>Select whether RING_SIZE applies to read or write addresses.\n
-                If 0, read addresses are wrapped on a (1 &lt;&lt; RING_SIZE) boundary. If 1, write addresses are wrapped.</description>
-              <name>RING_SEL</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[9:6]</bitRange>
-              <description>Size of address wrap region. If 0, don't wrap. For values n &gt; 0, only the lower n bits of the address will change. This wraps the address on a (1 &lt;&lt; n) byte boundary, facilitating access to naturally-aligned ring buffers.\n\n
-                Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>RING_NONE</name>
-                  <value>0</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>RING_SIZE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[5:5]</bitRange>
-              <description>If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.\n\n
-                Generally this should be disabled for memory-to-peripheral transfers.</description>
-              <name>INCR_WRITE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[4:4]</bitRange>
-              <description>If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.\n\n
-                Generally this should be disabled for peripheral-to-memory transfers.</description>
-              <name>INCR_READ</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[3:2]</bitRange>
-              <description>Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>SIZE_BYTE</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>SIZE_HALFWORD</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>SIZE_WORD</name>
-                  <value>2</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>DATA_SIZE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[1:1]</bitRange>
-              <description>HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.\n\n
-                This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.</description>
-              <name>HIGH_PRIORITY</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[0:0]</bitRange>
-              <description>DMA Channel Enable.\n
-                When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)</description>
-              <name>EN</name>
-            </field>
-          </fields>
-          <name>CH5_CTRL_TRIG</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x0150</addressOffset>
-          <description>Alias for channel 5 CTRL register</description>
-          <name>CH5_AL1_CTRL</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x0154</addressOffset>
-          <description>Alias for channel 5 READ_ADDR register</description>
-          <name>CH5_AL1_READ_ADDR</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x0158</addressOffset>
-          <description>Alias for channel 5 WRITE_ADDR register</description>
-          <name>CH5_AL1_WRITE_ADDR</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x015c</addressOffset>
-          <description>Alias for channel 5 TRANS_COUNT register\n
-            This is a trigger register (0xc). Writing a nonzero value will\n
-            reload the channel counter and start the channel.</description>
-          <name>CH5_AL1_TRANS_COUNT_TRIG</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x0160</addressOffset>
-          <description>Alias for channel 5 CTRL register</description>
-          <name>CH5_AL2_CTRL</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x0164</addressOffset>
-          <description>Alias for channel 5 TRANS_COUNT register</description>
-          <name>CH5_AL2_TRANS_COUNT</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x0168</addressOffset>
-          <description>Alias for channel 5 READ_ADDR register</description>
-          <name>CH5_AL2_READ_ADDR</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x016c</addressOffset>
-          <description>Alias for channel 5 WRITE_ADDR register\n
-            This is a trigger register (0xc). Writing a nonzero value will\n
-            reload the channel counter and start the channel.</description>
-          <name>CH5_AL2_WRITE_ADDR_TRIG</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x0170</addressOffset>
-          <description>Alias for channel 5 CTRL register</description>
-          <name>CH5_AL3_CTRL</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x0174</addressOffset>
-          <description>Alias for channel 5 WRITE_ADDR register</description>
-          <name>CH5_AL3_WRITE_ADDR</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x0178</addressOffset>
-          <description>Alias for channel 5 TRANS_COUNT register</description>
-          <name>CH5_AL3_TRANS_COUNT</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x017c</addressOffset>
-          <description>Alias for channel 5 READ_ADDR register\n
-            This is a trigger register (0xc). Writing a nonzero value will\n
-            reload the channel counter and start the channel.</description>
-          <name>CH5_AL3_READ_ADDR_TRIG</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x0180</addressOffset>
-          <description>DMA Channel 6 Read Address pointer\n
-            This register updates automatically each time a read completes. The current value is the next address to be read by this channel.</description>
-          <name>CH6_READ_ADDR</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x0184</addressOffset>
-          <description>DMA Channel 6 Write Address pointer\n
-            This register updates automatically each time a write completes. The current value is the next address to be written by this channel.</description>
-          <name>CH6_WRITE_ADDR</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x0188</addressOffset>
-          <description>DMA Channel 6 Transfer Count\n
-            Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).\n\n
-            When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.\n\n
-            Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.\n\n
-            The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD.</description>
-          <name>CH6_TRANS_COUNT</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x018c</addressOffset>
-          <description>DMA Channel 6 Control and Status</description>
-          <fields>
-            <field>
-              <access>read-only</access>
-              <bitRange>[31:31]</bitRange>
-              <description>Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag.</description>
-              <name>AHB_ERROR</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[30:30]</bitRange>
-              <description>If 1, the channel received a read bus error. Write one to clear.\n
-                READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)</description>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>READ_ERROR</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[29:29]</bitRange>
-              <description>If 1, the channel received a write bus error. Write one to clear.\n
-                WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)</description>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>WRITE_ERROR</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[24:24]</bitRange>
-              <description>This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.\n\n
-                To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT.</description>
-              <name>BUSY</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[23:23]</bitRange>
-              <description>If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.\n\n
-                This allows checksum to be enabled or disabled on a per-control- block basis.</description>
-              <name>SNIFF_EN</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[22:22]</bitRange>
-              <description>Apply byte-swap transformation to DMA data.\n
-                For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.</description>
-              <name>BSWAP</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[21:21]</bitRange>
-              <description>In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.\n\n
-                This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.</description>
-              <name>IRQ_QUIET</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[20:15]</bitRange>
-              <description>Select a Transfer Request signal.\n
-                The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).\n
-                0x0 to 0x3a -&gt; select DREQ n as TREQ</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>Select Timer 0 as TREQ</description>
-                  <name>TIMER0</name>
-                  <value>59</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>Select Timer 1 as TREQ</description>
-                  <name>TIMER1</name>
-                  <value>60</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>Select Timer 2 as TREQ (Optional)</description>
-                  <name>TIMER2</name>
-                  <value>61</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>Select Timer 3 as TREQ (Optional)</description>
-                  <name>TIMER3</name>
-                  <value>62</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>Permanent request, for unpaced transfers.</description>
-                  <name>PERMANENT</name>
-                  <value>63</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>TREQ_SEL</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[14:11]</bitRange>
-              <description>When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.</description>
-              <name>CHAIN_TO</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[10:10]</bitRange>
-              <description>Select whether RING_SIZE applies to read or write addresses.\n
-                If 0, read addresses are wrapped on a (1 &lt;&lt; RING_SIZE) boundary. If 1, write addresses are wrapped.</description>
-              <name>RING_SEL</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[9:6]</bitRange>
-              <description>Size of address wrap region. If 0, don't wrap. For values n &gt; 0, only the lower n bits of the address will change. This wraps the address on a (1 &lt;&lt; n) byte boundary, facilitating access to naturally-aligned ring buffers.\n\n
-                Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>RING_NONE</name>
-                  <value>0</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>RING_SIZE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[5:5]</bitRange>
-              <description>If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.\n\n
-                Generally this should be disabled for memory-to-peripheral transfers.</description>
-              <name>INCR_WRITE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[4:4]</bitRange>
-              <description>If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.\n\n
-                Generally this should be disabled for peripheral-to-memory transfers.</description>
-              <name>INCR_READ</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[3:2]</bitRange>
-              <description>Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>SIZE_BYTE</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>SIZE_HALFWORD</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>SIZE_WORD</name>
-                  <value>2</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>DATA_SIZE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[1:1]</bitRange>
-              <description>HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.\n\n
-                This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.</description>
-              <name>HIGH_PRIORITY</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[0:0]</bitRange>
-              <description>DMA Channel Enable.\n
-                When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)</description>
-              <name>EN</name>
-            </field>
-          </fields>
-          <name>CH6_CTRL_TRIG</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x0190</addressOffset>
-          <description>Alias for channel 6 CTRL register</description>
-          <name>CH6_AL1_CTRL</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x0194</addressOffset>
-          <description>Alias for channel 6 READ_ADDR register</description>
-          <name>CH6_AL1_READ_ADDR</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x0198</addressOffset>
-          <description>Alias for channel 6 WRITE_ADDR register</description>
-          <name>CH6_AL1_WRITE_ADDR</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x019c</addressOffset>
-          <description>Alias for channel 6 TRANS_COUNT register\n
-            This is a trigger register (0xc). Writing a nonzero value will\n
-            reload the channel counter and start the channel.</description>
-          <name>CH6_AL1_TRANS_COUNT_TRIG</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x01a0</addressOffset>
-          <description>Alias for channel 6 CTRL register</description>
-          <name>CH6_AL2_CTRL</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x01a4</addressOffset>
-          <description>Alias for channel 6 TRANS_COUNT register</description>
-          <name>CH6_AL2_TRANS_COUNT</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x01a8</addressOffset>
-          <description>Alias for channel 6 READ_ADDR register</description>
-          <name>CH6_AL2_READ_ADDR</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x01ac</addressOffset>
-          <description>Alias for channel 6 WRITE_ADDR register\n
-            This is a trigger register (0xc). Writing a nonzero value will\n
-            reload the channel counter and start the channel.</description>
-          <name>CH6_AL2_WRITE_ADDR_TRIG</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x01b0</addressOffset>
-          <description>Alias for channel 6 CTRL register</description>
-          <name>CH6_AL3_CTRL</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x01b4</addressOffset>
-          <description>Alias for channel 6 WRITE_ADDR register</description>
-          <name>CH6_AL3_WRITE_ADDR</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x01b8</addressOffset>
-          <description>Alias for channel 6 TRANS_COUNT register</description>
-          <name>CH6_AL3_TRANS_COUNT</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x01bc</addressOffset>
-          <description>Alias for channel 6 READ_ADDR register\n
-            This is a trigger register (0xc). Writing a nonzero value will\n
-            reload the channel counter and start the channel.</description>
-          <name>CH6_AL3_READ_ADDR_TRIG</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x01c0</addressOffset>
-          <description>DMA Channel 7 Read Address pointer\n
-            This register updates automatically each time a read completes. The current value is the next address to be read by this channel.</description>
-          <name>CH7_READ_ADDR</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x01c4</addressOffset>
-          <description>DMA Channel 7 Write Address pointer\n
-            This register updates automatically each time a write completes. The current value is the next address to be written by this channel.</description>
-          <name>CH7_WRITE_ADDR</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x01c8</addressOffset>
-          <description>DMA Channel 7 Transfer Count\n
-            Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).\n\n
-            When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.\n\n
-            Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.\n\n
-            The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD.</description>
-          <name>CH7_TRANS_COUNT</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x01cc</addressOffset>
-          <description>DMA Channel 7 Control and Status</description>
-          <fields>
-            <field>
-              <access>read-only</access>
-              <bitRange>[31:31]</bitRange>
-              <description>Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag.</description>
-              <name>AHB_ERROR</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[30:30]</bitRange>
-              <description>If 1, the channel received a read bus error. Write one to clear.\n
-                READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)</description>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>READ_ERROR</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[29:29]</bitRange>
-              <description>If 1, the channel received a write bus error. Write one to clear.\n
-                WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)</description>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>WRITE_ERROR</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[24:24]</bitRange>
-              <description>This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.\n\n
-                To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT.</description>
-              <name>BUSY</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[23:23]</bitRange>
-              <description>If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.\n\n
-                This allows checksum to be enabled or disabled on a per-control- block basis.</description>
-              <name>SNIFF_EN</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[22:22]</bitRange>
-              <description>Apply byte-swap transformation to DMA data.\n
-                For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.</description>
-              <name>BSWAP</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[21:21]</bitRange>
-              <description>In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.\n\n
-                This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.</description>
-              <name>IRQ_QUIET</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[20:15]</bitRange>
-              <description>Select a Transfer Request signal.\n
-                The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).\n
-                0x0 to 0x3a -&gt; select DREQ n as TREQ</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>Select Timer 0 as TREQ</description>
-                  <name>TIMER0</name>
-                  <value>59</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>Select Timer 1 as TREQ</description>
-                  <name>TIMER1</name>
-                  <value>60</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>Select Timer 2 as TREQ (Optional)</description>
-                  <name>TIMER2</name>
-                  <value>61</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>Select Timer 3 as TREQ (Optional)</description>
-                  <name>TIMER3</name>
-                  <value>62</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>Permanent request, for unpaced transfers.</description>
-                  <name>PERMANENT</name>
-                  <value>63</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>TREQ_SEL</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[14:11]</bitRange>
-              <description>When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.</description>
-              <name>CHAIN_TO</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[10:10]</bitRange>
-              <description>Select whether RING_SIZE applies to read or write addresses.\n
-                If 0, read addresses are wrapped on a (1 &lt;&lt; RING_SIZE) boundary. If 1, write addresses are wrapped.</description>
-              <name>RING_SEL</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[9:6]</bitRange>
-              <description>Size of address wrap region. If 0, don't wrap. For values n &gt; 0, only the lower n bits of the address will change. This wraps the address on a (1 &lt;&lt; n) byte boundary, facilitating access to naturally-aligned ring buffers.\n\n
-                Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>RING_NONE</name>
-                  <value>0</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>RING_SIZE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[5:5]</bitRange>
-              <description>If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.\n\n
-                Generally this should be disabled for memory-to-peripheral transfers.</description>
-              <name>INCR_WRITE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[4:4]</bitRange>
-              <description>If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.\n\n
-                Generally this should be disabled for peripheral-to-memory transfers.</description>
-              <name>INCR_READ</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[3:2]</bitRange>
-              <description>Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>SIZE_BYTE</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>SIZE_HALFWORD</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>SIZE_WORD</name>
-                  <value>2</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>DATA_SIZE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[1:1]</bitRange>
-              <description>HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.\n\n
-                This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.</description>
-              <name>HIGH_PRIORITY</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[0:0]</bitRange>
-              <description>DMA Channel Enable.\n
-                When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)</description>
-              <name>EN</name>
-            </field>
-          </fields>
-          <name>CH7_CTRL_TRIG</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x01d0</addressOffset>
-          <description>Alias for channel 7 CTRL register</description>
-          <name>CH7_AL1_CTRL</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x01d4</addressOffset>
-          <description>Alias for channel 7 READ_ADDR register</description>
-          <name>CH7_AL1_READ_ADDR</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x01d8</addressOffset>
-          <description>Alias for channel 7 WRITE_ADDR register</description>
-          <name>CH7_AL1_WRITE_ADDR</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x01dc</addressOffset>
-          <description>Alias for channel 7 TRANS_COUNT register\n
-            This is a trigger register (0xc). Writing a nonzero value will\n
-            reload the channel counter and start the channel.</description>
-          <name>CH7_AL1_TRANS_COUNT_TRIG</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x01e0</addressOffset>
-          <description>Alias for channel 7 CTRL register</description>
-          <name>CH7_AL2_CTRL</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x01e4</addressOffset>
-          <description>Alias for channel 7 TRANS_COUNT register</description>
-          <name>CH7_AL2_TRANS_COUNT</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x01e8</addressOffset>
-          <description>Alias for channel 7 READ_ADDR register</description>
-          <name>CH7_AL2_READ_ADDR</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x01ec</addressOffset>
-          <description>Alias for channel 7 WRITE_ADDR register\n
-            This is a trigger register (0xc). Writing a nonzero value will\n
-            reload the channel counter and start the channel.</description>
-          <name>CH7_AL2_WRITE_ADDR_TRIG</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x01f0</addressOffset>
-          <description>Alias for channel 7 CTRL register</description>
-          <name>CH7_AL3_CTRL</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x01f4</addressOffset>
-          <description>Alias for channel 7 WRITE_ADDR register</description>
-          <name>CH7_AL3_WRITE_ADDR</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x01f8</addressOffset>
-          <description>Alias for channel 7 TRANS_COUNT register</description>
-          <name>CH7_AL3_TRANS_COUNT</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x01fc</addressOffset>
-          <description>Alias for channel 7 READ_ADDR register\n
-            This is a trigger register (0xc). Writing a nonzero value will\n
-            reload the channel counter and start the channel.</description>
-          <name>CH7_AL3_READ_ADDR_TRIG</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x0200</addressOffset>
-          <description>DMA Channel 8 Read Address pointer\n
-            This register updates automatically each time a read completes. The current value is the next address to be read by this channel.</description>
-          <name>CH8_READ_ADDR</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x0204</addressOffset>
-          <description>DMA Channel 8 Write Address pointer\n
-            This register updates automatically each time a write completes. The current value is the next address to be written by this channel.</description>
-          <name>CH8_WRITE_ADDR</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x0208</addressOffset>
-          <description>DMA Channel 8 Transfer Count\n
-            Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).\n\n
-            When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.\n\n
-            Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.\n\n
-            The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD.</description>
-          <name>CH8_TRANS_COUNT</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x020c</addressOffset>
-          <description>DMA Channel 8 Control and Status</description>
-          <fields>
-            <field>
-              <access>read-only</access>
-              <bitRange>[31:31]</bitRange>
-              <description>Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag.</description>
-              <name>AHB_ERROR</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[30:30]</bitRange>
-              <description>If 1, the channel received a read bus error. Write one to clear.\n
-                READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)</description>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>READ_ERROR</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[29:29]</bitRange>
-              <description>If 1, the channel received a write bus error. Write one to clear.\n
-                WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)</description>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>WRITE_ERROR</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[24:24]</bitRange>
-              <description>This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.\n\n
-                To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT.</description>
-              <name>BUSY</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[23:23]</bitRange>
-              <description>If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.\n\n
-                This allows checksum to be enabled or disabled on a per-control- block basis.</description>
-              <name>SNIFF_EN</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[22:22]</bitRange>
-              <description>Apply byte-swap transformation to DMA data.\n
-                For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.</description>
-              <name>BSWAP</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[21:21]</bitRange>
-              <description>In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.\n\n
-                This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.</description>
-              <name>IRQ_QUIET</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[20:15]</bitRange>
-              <description>Select a Transfer Request signal.\n
-                The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).\n
-                0x0 to 0x3a -&gt; select DREQ n as TREQ</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>Select Timer 0 as TREQ</description>
-                  <name>TIMER0</name>
-                  <value>59</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>Select Timer 1 as TREQ</description>
-                  <name>TIMER1</name>
-                  <value>60</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>Select Timer 2 as TREQ (Optional)</description>
-                  <name>TIMER2</name>
-                  <value>61</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>Select Timer 3 as TREQ (Optional)</description>
-                  <name>TIMER3</name>
-                  <value>62</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>Permanent request, for unpaced transfers.</description>
-                  <name>PERMANENT</name>
-                  <value>63</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>TREQ_SEL</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[14:11]</bitRange>
-              <description>When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.</description>
-              <name>CHAIN_TO</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[10:10]</bitRange>
-              <description>Select whether RING_SIZE applies to read or write addresses.\n
-                If 0, read addresses are wrapped on a (1 &lt;&lt; RING_SIZE) boundary. If 1, write addresses are wrapped.</description>
-              <name>RING_SEL</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[9:6]</bitRange>
-              <description>Size of address wrap region. If 0, don't wrap. For values n &gt; 0, only the lower n bits of the address will change. This wraps the address on a (1 &lt;&lt; n) byte boundary, facilitating access to naturally-aligned ring buffers.\n\n
-                Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>RING_NONE</name>
-                  <value>0</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>RING_SIZE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[5:5]</bitRange>
-              <description>If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.\n\n
-                Generally this should be disabled for memory-to-peripheral transfers.</description>
-              <name>INCR_WRITE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[4:4]</bitRange>
-              <description>If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.\n\n
-                Generally this should be disabled for peripheral-to-memory transfers.</description>
-              <name>INCR_READ</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[3:2]</bitRange>
-              <description>Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>SIZE_BYTE</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>SIZE_HALFWORD</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>SIZE_WORD</name>
-                  <value>2</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>DATA_SIZE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[1:1]</bitRange>
-              <description>HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.\n\n
-                This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.</description>
-              <name>HIGH_PRIORITY</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[0:0]</bitRange>
-              <description>DMA Channel Enable.\n
-                When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)</description>
-              <name>EN</name>
-            </field>
-          </fields>
-          <name>CH8_CTRL_TRIG</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x0210</addressOffset>
-          <description>Alias for channel 8 CTRL register</description>
-          <name>CH8_AL1_CTRL</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x0214</addressOffset>
-          <description>Alias for channel 8 READ_ADDR register</description>
-          <name>CH8_AL1_READ_ADDR</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x0218</addressOffset>
-          <description>Alias for channel 8 WRITE_ADDR register</description>
-          <name>CH8_AL1_WRITE_ADDR</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x021c</addressOffset>
-          <description>Alias for channel 8 TRANS_COUNT register\n
-            This is a trigger register (0xc). Writing a nonzero value will\n
-            reload the channel counter and start the channel.</description>
-          <name>CH8_AL1_TRANS_COUNT_TRIG</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x0220</addressOffset>
-          <description>Alias for channel 8 CTRL register</description>
-          <name>CH8_AL2_CTRL</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x0224</addressOffset>
-          <description>Alias for channel 8 TRANS_COUNT register</description>
-          <name>CH8_AL2_TRANS_COUNT</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x0228</addressOffset>
-          <description>Alias for channel 8 READ_ADDR register</description>
-          <name>CH8_AL2_READ_ADDR</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x022c</addressOffset>
-          <description>Alias for channel 8 WRITE_ADDR register\n
-            This is a trigger register (0xc). Writing a nonzero value will\n
-            reload the channel counter and start the channel.</description>
-          <name>CH8_AL2_WRITE_ADDR_TRIG</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x0230</addressOffset>
-          <description>Alias for channel 8 CTRL register</description>
-          <name>CH8_AL3_CTRL</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x0234</addressOffset>
-          <description>Alias for channel 8 WRITE_ADDR register</description>
-          <name>CH8_AL3_WRITE_ADDR</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x0238</addressOffset>
-          <description>Alias for channel 8 TRANS_COUNT register</description>
-          <name>CH8_AL3_TRANS_COUNT</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x023c</addressOffset>
-          <description>Alias for channel 8 READ_ADDR register\n
-            This is a trigger register (0xc). Writing a nonzero value will\n
-            reload the channel counter and start the channel.</description>
-          <name>CH8_AL3_READ_ADDR_TRIG</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x0240</addressOffset>
-          <description>DMA Channel 9 Read Address pointer\n
-            This register updates automatically each time a read completes. The current value is the next address to be read by this channel.</description>
-          <name>CH9_READ_ADDR</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x0244</addressOffset>
-          <description>DMA Channel 9 Write Address pointer\n
-            This register updates automatically each time a write completes. The current value is the next address to be written by this channel.</description>
-          <name>CH9_WRITE_ADDR</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x0248</addressOffset>
-          <description>DMA Channel 9 Transfer Count\n
-            Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).\n\n
-            When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.\n\n
-            Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.\n\n
-            The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD.</description>
-          <name>CH9_TRANS_COUNT</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x024c</addressOffset>
-          <description>DMA Channel 9 Control and Status</description>
-          <fields>
-            <field>
-              <access>read-only</access>
-              <bitRange>[31:31]</bitRange>
-              <description>Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag.</description>
-              <name>AHB_ERROR</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[30:30]</bitRange>
-              <description>If 1, the channel received a read bus error. Write one to clear.\n
-                READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)</description>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>READ_ERROR</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[29:29]</bitRange>
-              <description>If 1, the channel received a write bus error. Write one to clear.\n
-                WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)</description>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>WRITE_ERROR</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[24:24]</bitRange>
-              <description>This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.\n\n
-                To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT.</description>
-              <name>BUSY</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[23:23]</bitRange>
-              <description>If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.\n\n
-                This allows checksum to be enabled or disabled on a per-control- block basis.</description>
-              <name>SNIFF_EN</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[22:22]</bitRange>
-              <description>Apply byte-swap transformation to DMA data.\n
-                For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.</description>
-              <name>BSWAP</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[21:21]</bitRange>
-              <description>In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.\n\n
-                This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.</description>
-              <name>IRQ_QUIET</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[20:15]</bitRange>
-              <description>Select a Transfer Request signal.\n
-                The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).\n
-                0x0 to 0x3a -&gt; select DREQ n as TREQ</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>Select Timer 0 as TREQ</description>
-                  <name>TIMER0</name>
-                  <value>59</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>Select Timer 1 as TREQ</description>
-                  <name>TIMER1</name>
-                  <value>60</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>Select Timer 2 as TREQ (Optional)</description>
-                  <name>TIMER2</name>
-                  <value>61</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>Select Timer 3 as TREQ (Optional)</description>
-                  <name>TIMER3</name>
-                  <value>62</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>Permanent request, for unpaced transfers.</description>
-                  <name>PERMANENT</name>
-                  <value>63</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>TREQ_SEL</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[14:11]</bitRange>
-              <description>When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.</description>
-              <name>CHAIN_TO</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[10:10]</bitRange>
-              <description>Select whether RING_SIZE applies to read or write addresses.\n
-                If 0, read addresses are wrapped on a (1 &lt;&lt; RING_SIZE) boundary. If 1, write addresses are wrapped.</description>
-              <name>RING_SEL</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[9:6]</bitRange>
-              <description>Size of address wrap region. If 0, don't wrap. For values n &gt; 0, only the lower n bits of the address will change. This wraps the address on a (1 &lt;&lt; n) byte boundary, facilitating access to naturally-aligned ring buffers.\n\n
-                Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>RING_NONE</name>
-                  <value>0</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>RING_SIZE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[5:5]</bitRange>
-              <description>If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.\n\n
-                Generally this should be disabled for memory-to-peripheral transfers.</description>
-              <name>INCR_WRITE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[4:4]</bitRange>
-              <description>If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.\n\n
-                Generally this should be disabled for peripheral-to-memory transfers.</description>
-              <name>INCR_READ</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[3:2]</bitRange>
-              <description>Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>SIZE_BYTE</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>SIZE_HALFWORD</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>SIZE_WORD</name>
-                  <value>2</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>DATA_SIZE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[1:1]</bitRange>
-              <description>HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.\n\n
-                This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.</description>
-              <name>HIGH_PRIORITY</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[0:0]</bitRange>
-              <description>DMA Channel Enable.\n
-                When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)</description>
-              <name>EN</name>
-            </field>
-          </fields>
-          <name>CH9_CTRL_TRIG</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x0250</addressOffset>
-          <description>Alias for channel 9 CTRL register</description>
-          <name>CH9_AL1_CTRL</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x0254</addressOffset>
-          <description>Alias for channel 9 READ_ADDR register</description>
-          <name>CH9_AL1_READ_ADDR</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x0258</addressOffset>
-          <description>Alias for channel 9 WRITE_ADDR register</description>
-          <name>CH9_AL1_WRITE_ADDR</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x025c</addressOffset>
-          <description>Alias for channel 9 TRANS_COUNT register\n
-            This is a trigger register (0xc). Writing a nonzero value will\n
-            reload the channel counter and start the channel.</description>
-          <name>CH9_AL1_TRANS_COUNT_TRIG</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x0260</addressOffset>
-          <description>Alias for channel 9 CTRL register</description>
-          <name>CH9_AL2_CTRL</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x0264</addressOffset>
-          <description>Alias for channel 9 TRANS_COUNT register</description>
-          <name>CH9_AL2_TRANS_COUNT</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x0268</addressOffset>
-          <description>Alias for channel 9 READ_ADDR register</description>
-          <name>CH9_AL2_READ_ADDR</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x026c</addressOffset>
-          <description>Alias for channel 9 WRITE_ADDR register\n
-            This is a trigger register (0xc). Writing a nonzero value will\n
-            reload the channel counter and start the channel.</description>
-          <name>CH9_AL2_WRITE_ADDR_TRIG</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x0270</addressOffset>
-          <description>Alias for channel 9 CTRL register</description>
-          <name>CH9_AL3_CTRL</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x0274</addressOffset>
-          <description>Alias for channel 9 WRITE_ADDR register</description>
-          <name>CH9_AL3_WRITE_ADDR</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x0278</addressOffset>
-          <description>Alias for channel 9 TRANS_COUNT register</description>
-          <name>CH9_AL3_TRANS_COUNT</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x027c</addressOffset>
-          <description>Alias for channel 9 READ_ADDR register\n
-            This is a trigger register (0xc). Writing a nonzero value will\n
-            reload the channel counter and start the channel.</description>
-          <name>CH9_AL3_READ_ADDR_TRIG</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x0280</addressOffset>
-          <description>DMA Channel 10 Read Address pointer\n
-            This register updates automatically each time a read completes. The current value is the next address to be read by this channel.</description>
-          <name>CH10_READ_ADDR</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x0284</addressOffset>
-          <description>DMA Channel 10 Write Address pointer\n
-            This register updates automatically each time a write completes. The current value is the next address to be written by this channel.</description>
-          <name>CH10_WRITE_ADDR</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x0288</addressOffset>
-          <description>DMA Channel 10 Transfer Count\n
-            Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).\n\n
-            When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.\n\n
-            Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.\n\n
-            The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD.</description>
-          <name>CH10_TRANS_COUNT</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x028c</addressOffset>
-          <description>DMA Channel 10 Control and Status</description>
-          <fields>
-            <field>
-              <access>read-only</access>
-              <bitRange>[31:31]</bitRange>
-              <description>Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag.</description>
-              <name>AHB_ERROR</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[30:30]</bitRange>
-              <description>If 1, the channel received a read bus error. Write one to clear.\n
-                READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)</description>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>READ_ERROR</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[29:29]</bitRange>
-              <description>If 1, the channel received a write bus error. Write one to clear.\n
-                WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)</description>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>WRITE_ERROR</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[24:24]</bitRange>
-              <description>This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.\n\n
-                To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT.</description>
-              <name>BUSY</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[23:23]</bitRange>
-              <description>If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.\n\n
-                This allows checksum to be enabled or disabled on a per-control- block basis.</description>
-              <name>SNIFF_EN</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[22:22]</bitRange>
-              <description>Apply byte-swap transformation to DMA data.\n
-                For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.</description>
-              <name>BSWAP</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[21:21]</bitRange>
-              <description>In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.\n\n
-                This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.</description>
-              <name>IRQ_QUIET</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[20:15]</bitRange>
-              <description>Select a Transfer Request signal.\n
-                The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).\n
-                0x0 to 0x3a -&gt; select DREQ n as TREQ</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>Select Timer 0 as TREQ</description>
-                  <name>TIMER0</name>
-                  <value>59</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>Select Timer 1 as TREQ</description>
-                  <name>TIMER1</name>
-                  <value>60</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>Select Timer 2 as TREQ (Optional)</description>
-                  <name>TIMER2</name>
-                  <value>61</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>Select Timer 3 as TREQ (Optional)</description>
-                  <name>TIMER3</name>
-                  <value>62</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>Permanent request, for unpaced transfers.</description>
-                  <name>PERMANENT</name>
-                  <value>63</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>TREQ_SEL</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[14:11]</bitRange>
-              <description>When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.</description>
-              <name>CHAIN_TO</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[10:10]</bitRange>
-              <description>Select whether RING_SIZE applies to read or write addresses.\n
-                If 0, read addresses are wrapped on a (1 &lt;&lt; RING_SIZE) boundary. If 1, write addresses are wrapped.</description>
-              <name>RING_SEL</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[9:6]</bitRange>
-              <description>Size of address wrap region. If 0, don't wrap. For values n &gt; 0, only the lower n bits of the address will change. This wraps the address on a (1 &lt;&lt; n) byte boundary, facilitating access to naturally-aligned ring buffers.\n\n
-                Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>RING_NONE</name>
-                  <value>0</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>RING_SIZE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[5:5]</bitRange>
-              <description>If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.\n\n
-                Generally this should be disabled for memory-to-peripheral transfers.</description>
-              <name>INCR_WRITE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[4:4]</bitRange>
-              <description>If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.\n\n
-                Generally this should be disabled for peripheral-to-memory transfers.</description>
-              <name>INCR_READ</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[3:2]</bitRange>
-              <description>Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>SIZE_BYTE</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>SIZE_HALFWORD</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>SIZE_WORD</name>
-                  <value>2</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>DATA_SIZE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[1:1]</bitRange>
-              <description>HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.\n\n
-                This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.</description>
-              <name>HIGH_PRIORITY</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[0:0]</bitRange>
-              <description>DMA Channel Enable.\n
-                When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)</description>
-              <name>EN</name>
-            </field>
-          </fields>
-          <name>CH10_CTRL_TRIG</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x0290</addressOffset>
-          <description>Alias for channel 10 CTRL register</description>
-          <name>CH10_AL1_CTRL</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x0294</addressOffset>
-          <description>Alias for channel 10 READ_ADDR register</description>
-          <name>CH10_AL1_READ_ADDR</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x0298</addressOffset>
-          <description>Alias for channel 10 WRITE_ADDR register</description>
-          <name>CH10_AL1_WRITE_ADDR</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x029c</addressOffset>
-          <description>Alias for channel 10 TRANS_COUNT register\n
-            This is a trigger register (0xc). Writing a nonzero value will\n
-            reload the channel counter and start the channel.</description>
-          <name>CH10_AL1_TRANS_COUNT_TRIG</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x02a0</addressOffset>
-          <description>Alias for channel 10 CTRL register</description>
-          <name>CH10_AL2_CTRL</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x02a4</addressOffset>
-          <description>Alias for channel 10 TRANS_COUNT register</description>
-          <name>CH10_AL2_TRANS_COUNT</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x02a8</addressOffset>
-          <description>Alias for channel 10 READ_ADDR register</description>
-          <name>CH10_AL2_READ_ADDR</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x02ac</addressOffset>
-          <description>Alias for channel 10 WRITE_ADDR register\n
-            This is a trigger register (0xc). Writing a nonzero value will\n
-            reload the channel counter and start the channel.</description>
-          <name>CH10_AL2_WRITE_ADDR_TRIG</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x02b0</addressOffset>
-          <description>Alias for channel 10 CTRL register</description>
-          <name>CH10_AL3_CTRL</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x02b4</addressOffset>
-          <description>Alias for channel 10 WRITE_ADDR register</description>
-          <name>CH10_AL3_WRITE_ADDR</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x02b8</addressOffset>
-          <description>Alias for channel 10 TRANS_COUNT register</description>
-          <name>CH10_AL3_TRANS_COUNT</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x02bc</addressOffset>
-          <description>Alias for channel 10 READ_ADDR register\n
-            This is a trigger register (0xc). Writing a nonzero value will\n
-            reload the channel counter and start the channel.</description>
-          <name>CH10_AL3_READ_ADDR_TRIG</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x02c0</addressOffset>
-          <description>DMA Channel 11 Read Address pointer\n
-            This register updates automatically each time a read completes. The current value is the next address to be read by this channel.</description>
-          <name>CH11_READ_ADDR</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x02c4</addressOffset>
-          <description>DMA Channel 11 Write Address pointer\n
-            This register updates automatically each time a write completes. The current value is the next address to be written by this channel.</description>
-          <name>CH11_WRITE_ADDR</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x02c8</addressOffset>
-          <description>DMA Channel 11 Transfer Count\n
-            Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).\n\n
-            When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.\n\n
-            Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.\n\n
-            The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD.</description>
-          <name>CH11_TRANS_COUNT</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x02cc</addressOffset>
-          <description>DMA Channel 11 Control and Status</description>
-          <fields>
-            <field>
-              <access>read-only</access>
-              <bitRange>[31:31]</bitRange>
-              <description>Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag.</description>
-              <name>AHB_ERROR</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[30:30]</bitRange>
-              <description>If 1, the channel received a read bus error. Write one to clear.\n
-                READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)</description>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>READ_ERROR</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[29:29]</bitRange>
-              <description>If 1, the channel received a write bus error. Write one to clear.\n
-                WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)</description>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>WRITE_ERROR</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[24:24]</bitRange>
-              <description>This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.\n\n
-                To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT.</description>
-              <name>BUSY</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[23:23]</bitRange>
-              <description>If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.\n\n
-                This allows checksum to be enabled or disabled on a per-control- block basis.</description>
-              <name>SNIFF_EN</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[22:22]</bitRange>
-              <description>Apply byte-swap transformation to DMA data.\n
-                For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.</description>
-              <name>BSWAP</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[21:21]</bitRange>
-              <description>In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.\n\n
-                This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.</description>
-              <name>IRQ_QUIET</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[20:15]</bitRange>
-              <description>Select a Transfer Request signal.\n
-                The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).\n
-                0x0 to 0x3a -&gt; select DREQ n as TREQ</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>Select Timer 0 as TREQ</description>
-                  <name>TIMER0</name>
-                  <value>59</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>Select Timer 1 as TREQ</description>
-                  <name>TIMER1</name>
-                  <value>60</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>Select Timer 2 as TREQ (Optional)</description>
-                  <name>TIMER2</name>
-                  <value>61</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>Select Timer 3 as TREQ (Optional)</description>
-                  <name>TIMER3</name>
-                  <value>62</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>Permanent request, for unpaced transfers.</description>
-                  <name>PERMANENT</name>
-                  <value>63</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>TREQ_SEL</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[14:11]</bitRange>
-              <description>When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.</description>
-              <name>CHAIN_TO</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[10:10]</bitRange>
-              <description>Select whether RING_SIZE applies to read or write addresses.\n
-                If 0, read addresses are wrapped on a (1 &lt;&lt; RING_SIZE) boundary. If 1, write addresses are wrapped.</description>
-              <name>RING_SEL</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[9:6]</bitRange>
-              <description>Size of address wrap region. If 0, don't wrap. For values n &gt; 0, only the lower n bits of the address will change. This wraps the address on a (1 &lt;&lt; n) byte boundary, facilitating access to naturally-aligned ring buffers.\n\n
-                Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>RING_NONE</name>
-                  <value>0</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>RING_SIZE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[5:5]</bitRange>
-              <description>If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.\n\n
-                Generally this should be disabled for memory-to-peripheral transfers.</description>
-              <name>INCR_WRITE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[4:4]</bitRange>
-              <description>If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.\n\n
-                Generally this should be disabled for peripheral-to-memory transfers.</description>
-              <name>INCR_READ</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[3:2]</bitRange>
-              <description>Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>SIZE_BYTE</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>SIZE_HALFWORD</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>SIZE_WORD</name>
-                  <value>2</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>DATA_SIZE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[1:1]</bitRange>
-              <description>HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.\n\n
-                This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.</description>
-              <name>HIGH_PRIORITY</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[0:0]</bitRange>
-              <description>DMA Channel Enable.\n
-                When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)</description>
-              <name>EN</name>
-            </field>
-          </fields>
-          <name>CH11_CTRL_TRIG</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x02d0</addressOffset>
-          <description>Alias for channel 11 CTRL register</description>
-          <name>CH11_AL1_CTRL</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x02d4</addressOffset>
-          <description>Alias for channel 11 READ_ADDR register</description>
-          <name>CH11_AL1_READ_ADDR</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x02d8</addressOffset>
-          <description>Alias for channel 11 WRITE_ADDR register</description>
-          <name>CH11_AL1_WRITE_ADDR</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x02dc</addressOffset>
-          <description>Alias for channel 11 TRANS_COUNT register\n
-            This is a trigger register (0xc). Writing a nonzero value will\n
-            reload the channel counter and start the channel.</description>
-          <name>CH11_AL1_TRANS_COUNT_TRIG</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x02e0</addressOffset>
-          <description>Alias for channel 11 CTRL register</description>
-          <name>CH11_AL2_CTRL</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x02e4</addressOffset>
-          <description>Alias for channel 11 TRANS_COUNT register</description>
-          <name>CH11_AL2_TRANS_COUNT</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x02e8</addressOffset>
-          <description>Alias for channel 11 READ_ADDR register</description>
-          <name>CH11_AL2_READ_ADDR</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x02ec</addressOffset>
-          <description>Alias for channel 11 WRITE_ADDR register\n
-            This is a trigger register (0xc). Writing a nonzero value will\n
-            reload the channel counter and start the channel.</description>
-          <name>CH11_AL2_WRITE_ADDR_TRIG</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x02f0</addressOffset>
-          <description>Alias for channel 11 CTRL register</description>
-          <name>CH11_AL3_CTRL</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x02f4</addressOffset>
-          <description>Alias for channel 11 WRITE_ADDR register</description>
-          <name>CH11_AL3_WRITE_ADDR</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x02f8</addressOffset>
-          <description>Alias for channel 11 TRANS_COUNT register</description>
-          <name>CH11_AL3_TRANS_COUNT</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x02fc</addressOffset>
-          <description>Alias for channel 11 READ_ADDR register\n
-            This is a trigger register (0xc). Writing a nonzero value will\n
-            reload the channel counter and start the channel.</description>
-          <name>CH11_AL3_READ_ADDR_TRIG</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0400</addressOffset>
-          <description>Interrupt Status (raw)</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[15:0]</bitRange>
-              <description>Raw interrupt status for DMA Channels 0..15. Bit n corresponds to channel n. Ignores any masking or forcing. Channel interrupts can be cleared by writing a bit mask to INTR, INTS0 or INTS1.\n\n
-                Channel interrupts can be routed to either of two system-level IRQs based on INTE0 and INTE1.\n\n
-                This can be used vector different channel interrupts to different ISRs: this might be done to allow NVIC IRQ preemption for more time-critical channels, or to spread IRQ load across different cores.\n\n
-                It is also valid to ignore this behaviour and just use INTE0/INTS0/IRQ 0.</description>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>INTR</name>
-            </field>
-          </fields>
-          <name>INTR</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0404</addressOffset>
-          <description>Interrupt Enables for IRQ 0</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[15:0]</bitRange>
-              <description>Set bit n to pass interrupts from channel n to DMA IRQ 0.</description>
-              <name>INTE0</name>
-            </field>
-          </fields>
-          <name>INTE0</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0408</addressOffset>
-          <description>Force Interrupts</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[15:0]</bitRange>
-              <description>Write 1s to force the corresponding bits in INTE0. The interrupt remains asserted until INTF0 is cleared.</description>
-              <name>INTF0</name>
-            </field>
-          </fields>
-          <name>INTF0</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x040c</addressOffset>
-          <description>Interrupt Status for IRQ 0</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[15:0]</bitRange>
-              <description>Indicates active channel interrupt requests which are currently causing IRQ 0 to be asserted.\n
-                Channel interrupts can be cleared by writing a bit mask here.</description>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>INTS0</name>
-            </field>
-          </fields>
-          <name>INTS0</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0414</addressOffset>
-          <description>Interrupt Enables for IRQ 1</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[15:0]</bitRange>
-              <description>Set bit n to pass interrupts from channel n to DMA IRQ 1.</description>
-              <name>INTE1</name>
-            </field>
-          </fields>
-          <name>INTE1</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0418</addressOffset>
-          <description>Force Interrupts for IRQ 1</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[15:0]</bitRange>
-              <description>Write 1s to force the corresponding bits in INTE0. The interrupt remains asserted until INTF0 is cleared.</description>
-              <name>INTF1</name>
-            </field>
-          </fields>
-          <name>INTF1</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x041c</addressOffset>
-          <description>Interrupt Status (masked) for IRQ 1</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[15:0]</bitRange>
-              <description>Indicates active channel interrupt requests which are currently causing IRQ 1 to be asserted.\n
-                Channel interrupts can be cleared by writing a bit mask here.</description>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>INTS1</name>
-            </field>
-          </fields>
-          <name>INTS1</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0420</addressOffset>
-          <description>Pacing (X/Y) Fractional Timer\n
-            The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less.</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[31:16]</bitRange>
-              <description>Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer.</description>
-              <name>X</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[15:0]</bitRange>
-              <description>Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer.</description>
-              <name>Y</name>
-            </field>
-          </fields>
-          <name>TIMER0</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0424</addressOffset>
-          <description>Pacing (X/Y) Fractional Timer\n
-            The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less.</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[31:16]</bitRange>
-              <description>Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer.</description>
-              <name>X</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[15:0]</bitRange>
-              <description>Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer.</description>
-              <name>Y</name>
-            </field>
-          </fields>
-          <name>TIMER1</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0428</addressOffset>
-          <description>Pacing (X/Y) Fractional Timer\n
-            The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less.</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[31:16]</bitRange>
-              <description>Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer.</description>
-              <name>X</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[15:0]</bitRange>
-              <description>Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer.</description>
-              <name>Y</name>
-            </field>
-          </fields>
-          <name>TIMER2</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x042c</addressOffset>
-          <description>Pacing (X/Y) Fractional Timer\n
-            The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less.</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[31:16]</bitRange>
-              <description>Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer.</description>
-              <name>X</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[15:0]</bitRange>
-              <description>Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer.</description>
-              <name>Y</name>
-            </field>
-          </fields>
-          <name>TIMER3</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0430</addressOffset>
-          <description>Trigger one or more channels simultaneously</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[15:0]</bitRange>
-              <description>Each bit in this register corresponds to a DMA channel. Writing a 1 to the relevant bit is the same as writing to that channel's trigger register; the channel will start if it is currently enabled and not already busy.</description>
-              <modifiedWriteValues>clear</modifiedWriteValues>
-              <name>MULTI_CHAN_TRIGGER</name>
-            </field>
-          </fields>
-          <name>MULTI_CHAN_TRIGGER</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0434</addressOffset>
-          <description>Sniffer Control</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[11:11]</bitRange>
-              <description>If set, the result appears inverted (bitwise complement) when read. This does not affect the way the checksum is calculated; the result is transformed on-the-fly between the result register and the bus.</description>
-              <name>OUT_INV</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[10:10]</bitRange>
-              <description>If set, the result appears bit-reversed when read. This does not affect the way the checksum is calculated; the result is transformed on-the-fly between the result register and the bus.</description>
-              <name>OUT_REV</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[9:9]</bitRange>
-              <description>Locally perform a byte reverse on the sniffed data, before feeding into checksum.\n\n
-                Note that the sniff hardware is downstream of the DMA channel byteswap performed in the read master: if channel CTRL_BSWAP and SNIFF_CTRL_BSWAP are both enabled, their effects cancel from the sniffer's point of view.</description>
-              <name>BSWAP</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[8:5]</bitRange>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>Calculate a CRC-32 (IEEE802.3 polynomial)</description>
-                  <name>CRC32</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>Calculate a CRC-32 (IEEE802.3 polynomial) with bit reversed data</description>
-                  <name>CRC32R</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>Calculate a CRC-16-CCITT</description>
-                  <name>CRC16</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>Calculate a CRC-16-CCITT with bit reversed data</description>
-                  <name>CRC16R</name>
-                  <value>3</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>XOR reduction over all data. == 1 if the total 1 population count is odd.</description>
-                  <name>EVEN</name>
-                  <value>14</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>Calculate a simple 32-bit checksum (addition with a 32 bit accumulator)</description>
-                  <name>SUM</name>
-                  <value>15</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>CALC</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[4:1]</bitRange>
-              <description>DMA channel for Sniffer to observe</description>
-              <name>DMACH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[0:0]</bitRange>
-              <description>Enable sniffer</description>
-              <name>EN</name>
-            </field>
-          </fields>
-          <name>SNIFF_CTRL</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x0438</addressOffset>
-          <description>Data accumulator for sniff hardware\n
-            Write an initial seed value here before starting a DMA transfer on the channel indicated by SNIFF_CTRL_DMACH. The hardware will update this register each time it observes a read from the indicated channel. Once the channel completes, the final result can be read from this register.</description>
-          <name>SNIFF_DATA</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0440</addressOffset>
-          <description>Debug RAF, WAF, TDF levels</description>
-          <fields>
-            <field>
-              <access>read-only</access>
-              <bitRange>[23:16]</bitRange>
-              <description>Current Read-Address-FIFO fill level</description>
-              <name>RAF_LVL</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[15:8]</bitRange>
-              <description>Current Write-Address-FIFO fill level</description>
-              <name>WAF_LVL</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[7:0]</bitRange>
-              <description>Current Transfer-Data-FIFO fill level</description>
-              <name>TDF_LVL</name>
-            </field>
-          </fields>
-          <name>FIFO_LEVELS</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0444</addressOffset>
-          <description>Abort an in-progress transfer sequence on one or more channels</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[15:0]</bitRange>
-              <description>Each bit corresponds to a channel. Writing a 1 aborts whatever transfer sequence is in progress on that channel. The bit will remain high until any in-flight transfers have been flushed through the address and data FIFOs.\n\n
-                After writing, this register must be polled until it returns all-zero. Until this point, it is unsafe to restart the channel.</description>
-              <modifiedWriteValues>clear</modifiedWriteValues>
-              <name>CHAN_ABORT</name>
-            </field>
-          </fields>
-          <name>CHAN_ABORT</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0448</addressOffset>
-          <description>The number of channels this DMA instance is equipped with. This DMA supports up to 16 hardware channels, but can be configured with as few as one, to minimise silicon area.</description>
-          <fields>
-            <field>
-              <access>read-only</access>
-              <bitRange>[4:0]</bitRange>
-              <name>N_CHANNELS</name>
-            </field>
-          </fields>
-          <name>N_CHANNELS</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0800</addressOffset>
-          <description>Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[5:0]</bitRange>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>CH0_DBG_CTDREQ</name>
-            </field>
-          </fields>
-          <name>CH0_DBG_CTDREQ</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-only</access>
-          <addressOffset>0x0804</addressOffset>
-          <description>Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer</description>
-          <name>CH0_DBG_TCR</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0840</addressOffset>
-          <description>Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[5:0]</bitRange>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>CH1_DBG_CTDREQ</name>
-            </field>
-          </fields>
-          <name>CH1_DBG_CTDREQ</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-only</access>
-          <addressOffset>0x0844</addressOffset>
-          <description>Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer</description>
-          <name>CH1_DBG_TCR</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0880</addressOffset>
-          <description>Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[5:0]</bitRange>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>CH2_DBG_CTDREQ</name>
-            </field>
-          </fields>
-          <name>CH2_DBG_CTDREQ</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-only</access>
-          <addressOffset>0x0884</addressOffset>
-          <description>Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer</description>
-          <name>CH2_DBG_TCR</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x08c0</addressOffset>
-          <description>Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[5:0]</bitRange>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>CH3_DBG_CTDREQ</name>
-            </field>
-          </fields>
-          <name>CH3_DBG_CTDREQ</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-only</access>
-          <addressOffset>0x08c4</addressOffset>
-          <description>Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer</description>
-          <name>CH3_DBG_TCR</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0900</addressOffset>
-          <description>Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[5:0]</bitRange>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>CH4_DBG_CTDREQ</name>
-            </field>
-          </fields>
-          <name>CH4_DBG_CTDREQ</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-only</access>
-          <addressOffset>0x0904</addressOffset>
-          <description>Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer</description>
-          <name>CH4_DBG_TCR</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0940</addressOffset>
-          <description>Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[5:0]</bitRange>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>CH5_DBG_CTDREQ</name>
-            </field>
-          </fields>
-          <name>CH5_DBG_CTDREQ</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-only</access>
-          <addressOffset>0x0944</addressOffset>
-          <description>Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer</description>
-          <name>CH5_DBG_TCR</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0980</addressOffset>
-          <description>Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[5:0]</bitRange>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>CH6_DBG_CTDREQ</name>
-            </field>
-          </fields>
-          <name>CH6_DBG_CTDREQ</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-only</access>
-          <addressOffset>0x0984</addressOffset>
-          <description>Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer</description>
-          <name>CH6_DBG_TCR</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x09c0</addressOffset>
-          <description>Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[5:0]</bitRange>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>CH7_DBG_CTDREQ</name>
-            </field>
-          </fields>
-          <name>CH7_DBG_CTDREQ</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-only</access>
-          <addressOffset>0x09c4</addressOffset>
-          <description>Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer</description>
-          <name>CH7_DBG_TCR</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0a00</addressOffset>
-          <description>Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[5:0]</bitRange>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>CH8_DBG_CTDREQ</name>
-            </field>
-          </fields>
-          <name>CH8_DBG_CTDREQ</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-only</access>
-          <addressOffset>0x0a04</addressOffset>
-          <description>Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer</description>
-          <name>CH8_DBG_TCR</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0a40</addressOffset>
-          <description>Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[5:0]</bitRange>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>CH9_DBG_CTDREQ</name>
-            </field>
-          </fields>
-          <name>CH9_DBG_CTDREQ</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-only</access>
-          <addressOffset>0x0a44</addressOffset>
-          <description>Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer</description>
-          <name>CH9_DBG_TCR</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0a80</addressOffset>
-          <description>Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[5:0]</bitRange>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>CH10_DBG_CTDREQ</name>
-            </field>
-          </fields>
-          <name>CH10_DBG_CTDREQ</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-only</access>
-          <addressOffset>0x0a84</addressOffset>
-          <description>Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer</description>
-          <name>CH10_DBG_TCR</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0ac0</addressOffset>
-          <description>Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[5:0]</bitRange>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>CH11_DBG_CTDREQ</name>
-            </field>
-          </fields>
-          <name>CH11_DBG_CTDREQ</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-only</access>
-          <addressOffset>0x0ac4</addressOffset>
-          <description>Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer</description>
-          <name>CH11_DBG_TCR</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-      </registers>
-      <size>32</size>
-      <version>1</version>
-    </peripheral>
-    <peripheral>
-      <addressBlock>
-        <offset>0</offset>
-        <size>0x0100</size>
-        <usage>registers</usage>
-      </addressBlock>
-      <baseAddress>0x50100000</baseAddress>
-      <description>DPRAM layout for USB device.</description>
-      <name>USBCTRL_DPRAM</name>
-      <registers>
-        <register>
-          <addressOffset>0x0000</addressOffset>
-          <description>Bytes 0-3 of the SETUP packet from the host.</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[31:16]</bitRange>
-              <name>WVALUE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[15:8]</bitRange>
-              <name>BREQUEST</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[7:0]</bitRange>
-              <name>BMREQUESTTYPE</name>
-            </field>
-          </fields>
-          <name>SETUP_PACKET_LOW</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0004</addressOffset>
-          <description>Bytes 4-7 of the setup packet from the host.</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[31:16]</bitRange>
-              <name>WLENGTH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[15:0]</bitRange>
-              <name>WINDEX</name>
-            </field>
-          </fields>
-          <name>SETUP_PACKET_HIGH</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0008</addressOffset>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[31:31]</bitRange>
-              <description>Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.</description>
-              <name>ENABLE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[30:30]</bitRange>
-              <description>This endpoint is double buffered.</description>
-              <name>DOUBLE_BUFFERED</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[29:29]</bitRange>
-              <description>Trigger an interrupt each time a buffer is done.</description>
-              <name>INTERRUPT_PER_BUFF</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[28:28]</bitRange>
-              <description>Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.</description>
-              <name>INTERRUPT_PER_DOUBLE_BUFF</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[27:26]</bitRange>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>Control</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>Isochronous</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>Bulk</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>Interrupt</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>ENDPOINT_TYPE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[17:17]</bitRange>
-              <description>Trigger an interrupt if a STALL is sent. Intended for debug only.</description>
-              <name>INTERRUPT_ON_STALL</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[16:16]</bitRange>
-              <description>Trigger an interrupt if a NAK is sent. Intended for debug only.</description>
-              <name>INTERRUPT_ON_NAK</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[15:0]</bitRange>
-              <description>64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.</description>
-              <name>BUFFER_ADDRESS</name>
-            </field>
-          </fields>
-          <name>EP1_IN_CONTROL</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x000c</addressOffset>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[31:31]</bitRange>
-              <description>Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.</description>
-              <name>ENABLE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[30:30]</bitRange>
-              <description>This endpoint is double buffered.</description>
-              <name>DOUBLE_BUFFERED</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[29:29]</bitRange>
-              <description>Trigger an interrupt each time a buffer is done.</description>
-              <name>INTERRUPT_PER_BUFF</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[28:28]</bitRange>
-              <description>Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.</description>
-              <name>INTERRUPT_PER_DOUBLE_BUFF</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[27:26]</bitRange>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>Control</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>Isochronous</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>Bulk</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>Interrupt</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>ENDPOINT_TYPE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[17:17]</bitRange>
-              <description>Trigger an interrupt if a STALL is sent. Intended for debug only.</description>
-              <name>INTERRUPT_ON_STALL</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[16:16]</bitRange>
-              <description>Trigger an interrupt if a NAK is sent. Intended for debug only.</description>
-              <name>INTERRUPT_ON_NAK</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[15:0]</bitRange>
-              <description>64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.</description>
-              <name>BUFFER_ADDRESS</name>
-            </field>
-          </fields>
-          <name>EP1_OUT_CONTROL</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0010</addressOffset>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[31:31]</bitRange>
-              <description>Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.</description>
-              <name>ENABLE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[30:30]</bitRange>
-              <description>This endpoint is double buffered.</description>
-              <name>DOUBLE_BUFFERED</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[29:29]</bitRange>
-              <description>Trigger an interrupt each time a buffer is done.</description>
-              <name>INTERRUPT_PER_BUFF</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[28:28]</bitRange>
-              <description>Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.</description>
-              <name>INTERRUPT_PER_DOUBLE_BUFF</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[27:26]</bitRange>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>Control</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>Isochronous</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>Bulk</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>Interrupt</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>ENDPOINT_TYPE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[17:17]</bitRange>
-              <description>Trigger an interrupt if a STALL is sent. Intended for debug only.</description>
-              <name>INTERRUPT_ON_STALL</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[16:16]</bitRange>
-              <description>Trigger an interrupt if a NAK is sent. Intended for debug only.</description>
-              <name>INTERRUPT_ON_NAK</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[15:0]</bitRange>
-              <description>64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.</description>
-              <name>BUFFER_ADDRESS</name>
-            </field>
-          </fields>
-          <name>EP2_IN_CONTROL</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0014</addressOffset>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[31:31]</bitRange>
-              <description>Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.</description>
-              <name>ENABLE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[30:30]</bitRange>
-              <description>This endpoint is double buffered.</description>
-              <name>DOUBLE_BUFFERED</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[29:29]</bitRange>
-              <description>Trigger an interrupt each time a buffer is done.</description>
-              <name>INTERRUPT_PER_BUFF</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[28:28]</bitRange>
-              <description>Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.</description>
-              <name>INTERRUPT_PER_DOUBLE_BUFF</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[27:26]</bitRange>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>Control</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>Isochronous</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>Bulk</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>Interrupt</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>ENDPOINT_TYPE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[17:17]</bitRange>
-              <description>Trigger an interrupt if a STALL is sent. Intended for debug only.</description>
-              <name>INTERRUPT_ON_STALL</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[16:16]</bitRange>
-              <description>Trigger an interrupt if a NAK is sent. Intended for debug only.</description>
-              <name>INTERRUPT_ON_NAK</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[15:0]</bitRange>
-              <description>64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.</description>
-              <name>BUFFER_ADDRESS</name>
-            </field>
-          </fields>
-          <name>EP2_OUT_CONTROL</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0018</addressOffset>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[31:31]</bitRange>
-              <description>Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.</description>
-              <name>ENABLE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[30:30]</bitRange>
-              <description>This endpoint is double buffered.</description>
-              <name>DOUBLE_BUFFERED</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[29:29]</bitRange>
-              <description>Trigger an interrupt each time a buffer is done.</description>
-              <name>INTERRUPT_PER_BUFF</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[28:28]</bitRange>
-              <description>Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.</description>
-              <name>INTERRUPT_PER_DOUBLE_BUFF</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[27:26]</bitRange>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>Control</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>Isochronous</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>Bulk</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>Interrupt</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>ENDPOINT_TYPE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[17:17]</bitRange>
-              <description>Trigger an interrupt if a STALL is sent. Intended for debug only.</description>
-              <name>INTERRUPT_ON_STALL</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[16:16]</bitRange>
-              <description>Trigger an interrupt if a NAK is sent. Intended for debug only.</description>
-              <name>INTERRUPT_ON_NAK</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[15:0]</bitRange>
-              <description>64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.</description>
-              <name>BUFFER_ADDRESS</name>
-            </field>
-          </fields>
-          <name>EP3_IN_CONTROL</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x001c</addressOffset>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[31:31]</bitRange>
-              <description>Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.</description>
-              <name>ENABLE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[30:30]</bitRange>
-              <description>This endpoint is double buffered.</description>
-              <name>DOUBLE_BUFFERED</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[29:29]</bitRange>
-              <description>Trigger an interrupt each time a buffer is done.</description>
-              <name>INTERRUPT_PER_BUFF</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[28:28]</bitRange>
-              <description>Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.</description>
-              <name>INTERRUPT_PER_DOUBLE_BUFF</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[27:26]</bitRange>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>Control</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>Isochronous</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>Bulk</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>Interrupt</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>ENDPOINT_TYPE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[17:17]</bitRange>
-              <description>Trigger an interrupt if a STALL is sent. Intended for debug only.</description>
-              <name>INTERRUPT_ON_STALL</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[16:16]</bitRange>
-              <description>Trigger an interrupt if a NAK is sent. Intended for debug only.</description>
-              <name>INTERRUPT_ON_NAK</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[15:0]</bitRange>
-              <description>64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.</description>
-              <name>BUFFER_ADDRESS</name>
-            </field>
-          </fields>
-          <name>EP3_OUT_CONTROL</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0020</addressOffset>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[31:31]</bitRange>
-              <description>Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.</description>
-              <name>ENABLE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[30:30]</bitRange>
-              <description>This endpoint is double buffered.</description>
-              <name>DOUBLE_BUFFERED</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[29:29]</bitRange>
-              <description>Trigger an interrupt each time a buffer is done.</description>
-              <name>INTERRUPT_PER_BUFF</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[28:28]</bitRange>
-              <description>Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.</description>
-              <name>INTERRUPT_PER_DOUBLE_BUFF</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[27:26]</bitRange>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>Control</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>Isochronous</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>Bulk</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>Interrupt</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>ENDPOINT_TYPE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[17:17]</bitRange>
-              <description>Trigger an interrupt if a STALL is sent. Intended for debug only.</description>
-              <name>INTERRUPT_ON_STALL</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[16:16]</bitRange>
-              <description>Trigger an interrupt if a NAK is sent. Intended for debug only.</description>
-              <name>INTERRUPT_ON_NAK</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[15:0]</bitRange>
-              <description>64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.</description>
-              <name>BUFFER_ADDRESS</name>
-            </field>
-          </fields>
-          <name>EP4_IN_CONTROL</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0024</addressOffset>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[31:31]</bitRange>
-              <description>Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.</description>
-              <name>ENABLE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[30:30]</bitRange>
-              <description>This endpoint is double buffered.</description>
-              <name>DOUBLE_BUFFERED</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[29:29]</bitRange>
-              <description>Trigger an interrupt each time a buffer is done.</description>
-              <name>INTERRUPT_PER_BUFF</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[28:28]</bitRange>
-              <description>Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.</description>
-              <name>INTERRUPT_PER_DOUBLE_BUFF</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[27:26]</bitRange>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>Control</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>Isochronous</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>Bulk</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>Interrupt</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>ENDPOINT_TYPE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[17:17]</bitRange>
-              <description>Trigger an interrupt if a STALL is sent. Intended for debug only.</description>
-              <name>INTERRUPT_ON_STALL</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[16:16]</bitRange>
-              <description>Trigger an interrupt if a NAK is sent. Intended for debug only.</description>
-              <name>INTERRUPT_ON_NAK</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[15:0]</bitRange>
-              <description>64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.</description>
-              <name>BUFFER_ADDRESS</name>
-            </field>
-          </fields>
-          <name>EP4_OUT_CONTROL</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0028</addressOffset>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[31:31]</bitRange>
-              <description>Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.</description>
-              <name>ENABLE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[30:30]</bitRange>
-              <description>This endpoint is double buffered.</description>
-              <name>DOUBLE_BUFFERED</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[29:29]</bitRange>
-              <description>Trigger an interrupt each time a buffer is done.</description>
-              <name>INTERRUPT_PER_BUFF</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[28:28]</bitRange>
-              <description>Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.</description>
-              <name>INTERRUPT_PER_DOUBLE_BUFF</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[27:26]</bitRange>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>Control</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>Isochronous</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>Bulk</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>Interrupt</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>ENDPOINT_TYPE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[17:17]</bitRange>
-              <description>Trigger an interrupt if a STALL is sent. Intended for debug only.</description>
-              <name>INTERRUPT_ON_STALL</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[16:16]</bitRange>
-              <description>Trigger an interrupt if a NAK is sent. Intended for debug only.</description>
-              <name>INTERRUPT_ON_NAK</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[15:0]</bitRange>
-              <description>64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.</description>
-              <name>BUFFER_ADDRESS</name>
-            </field>
-          </fields>
-          <name>EP5_IN_CONTROL</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x002c</addressOffset>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[31:31]</bitRange>
-              <description>Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.</description>
-              <name>ENABLE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[30:30]</bitRange>
-              <description>This endpoint is double buffered.</description>
-              <name>DOUBLE_BUFFERED</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[29:29]</bitRange>
-              <description>Trigger an interrupt each time a buffer is done.</description>
-              <name>INTERRUPT_PER_BUFF</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[28:28]</bitRange>
-              <description>Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.</description>
-              <name>INTERRUPT_PER_DOUBLE_BUFF</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[27:26]</bitRange>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>Control</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>Isochronous</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>Bulk</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>Interrupt</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>ENDPOINT_TYPE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[17:17]</bitRange>
-              <description>Trigger an interrupt if a STALL is sent. Intended for debug only.</description>
-              <name>INTERRUPT_ON_STALL</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[16:16]</bitRange>
-              <description>Trigger an interrupt if a NAK is sent. Intended for debug only.</description>
-              <name>INTERRUPT_ON_NAK</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[15:0]</bitRange>
-              <description>64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.</description>
-              <name>BUFFER_ADDRESS</name>
-            </field>
-          </fields>
-          <name>EP5_OUT_CONTROL</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0030</addressOffset>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[31:31]</bitRange>
-              <description>Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.</description>
-              <name>ENABLE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[30:30]</bitRange>
-              <description>This endpoint is double buffered.</description>
-              <name>DOUBLE_BUFFERED</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[29:29]</bitRange>
-              <description>Trigger an interrupt each time a buffer is done.</description>
-              <name>INTERRUPT_PER_BUFF</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[28:28]</bitRange>
-              <description>Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.</description>
-              <name>INTERRUPT_PER_DOUBLE_BUFF</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[27:26]</bitRange>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>Control</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>Isochronous</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>Bulk</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>Interrupt</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>ENDPOINT_TYPE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[17:17]</bitRange>
-              <description>Trigger an interrupt if a STALL is sent. Intended for debug only.</description>
-              <name>INTERRUPT_ON_STALL</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[16:16]</bitRange>
-              <description>Trigger an interrupt if a NAK is sent. Intended for debug only.</description>
-              <name>INTERRUPT_ON_NAK</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[15:0]</bitRange>
-              <description>64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.</description>
-              <name>BUFFER_ADDRESS</name>
-            </field>
-          </fields>
-          <name>EP6_IN_CONTROL</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0034</addressOffset>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[31:31]</bitRange>
-              <description>Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.</description>
-              <name>ENABLE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[30:30]</bitRange>
-              <description>This endpoint is double buffered.</description>
-              <name>DOUBLE_BUFFERED</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[29:29]</bitRange>
-              <description>Trigger an interrupt each time a buffer is done.</description>
-              <name>INTERRUPT_PER_BUFF</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[28:28]</bitRange>
-              <description>Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.</description>
-              <name>INTERRUPT_PER_DOUBLE_BUFF</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[27:26]</bitRange>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>Control</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>Isochronous</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>Bulk</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>Interrupt</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>ENDPOINT_TYPE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[17:17]</bitRange>
-              <description>Trigger an interrupt if a STALL is sent. Intended for debug only.</description>
-              <name>INTERRUPT_ON_STALL</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[16:16]</bitRange>
-              <description>Trigger an interrupt if a NAK is sent. Intended for debug only.</description>
-              <name>INTERRUPT_ON_NAK</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[15:0]</bitRange>
-              <description>64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.</description>
-              <name>BUFFER_ADDRESS</name>
-            </field>
-          </fields>
-          <name>EP6_OUT_CONTROL</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0038</addressOffset>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[31:31]</bitRange>
-              <description>Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.</description>
-              <name>ENABLE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[30:30]</bitRange>
-              <description>This endpoint is double buffered.</description>
-              <name>DOUBLE_BUFFERED</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[29:29]</bitRange>
-              <description>Trigger an interrupt each time a buffer is done.</description>
-              <name>INTERRUPT_PER_BUFF</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[28:28]</bitRange>
-              <description>Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.</description>
-              <name>INTERRUPT_PER_DOUBLE_BUFF</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[27:26]</bitRange>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>Control</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>Isochronous</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>Bulk</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>Interrupt</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>ENDPOINT_TYPE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[17:17]</bitRange>
-              <description>Trigger an interrupt if a STALL is sent. Intended for debug only.</description>
-              <name>INTERRUPT_ON_STALL</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[16:16]</bitRange>
-              <description>Trigger an interrupt if a NAK is sent. Intended for debug only.</description>
-              <name>INTERRUPT_ON_NAK</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[15:0]</bitRange>
-              <description>64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.</description>
-              <name>BUFFER_ADDRESS</name>
-            </field>
-          </fields>
-          <name>EP7_IN_CONTROL</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x003c</addressOffset>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[31:31]</bitRange>
-              <description>Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.</description>
-              <name>ENABLE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[30:30]</bitRange>
-              <description>This endpoint is double buffered.</description>
-              <name>DOUBLE_BUFFERED</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[29:29]</bitRange>
-              <description>Trigger an interrupt each time a buffer is done.</description>
-              <name>INTERRUPT_PER_BUFF</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[28:28]</bitRange>
-              <description>Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.</description>
-              <name>INTERRUPT_PER_DOUBLE_BUFF</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[27:26]</bitRange>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>Control</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>Isochronous</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>Bulk</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>Interrupt</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>ENDPOINT_TYPE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[17:17]</bitRange>
-              <description>Trigger an interrupt if a STALL is sent. Intended for debug only.</description>
-              <name>INTERRUPT_ON_STALL</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[16:16]</bitRange>
-              <description>Trigger an interrupt if a NAK is sent. Intended for debug only.</description>
-              <name>INTERRUPT_ON_NAK</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[15:0]</bitRange>
-              <description>64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.</description>
-              <name>BUFFER_ADDRESS</name>
-            </field>
-          </fields>
-          <name>EP7_OUT_CONTROL</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0040</addressOffset>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[31:31]</bitRange>
-              <description>Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.</description>
-              <name>ENABLE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[30:30]</bitRange>
-              <description>This endpoint is double buffered.</description>
-              <name>DOUBLE_BUFFERED</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[29:29]</bitRange>
-              <description>Trigger an interrupt each time a buffer is done.</description>
-              <name>INTERRUPT_PER_BUFF</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[28:28]</bitRange>
-              <description>Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.</description>
-              <name>INTERRUPT_PER_DOUBLE_BUFF</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[27:26]</bitRange>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>Control</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>Isochronous</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>Bulk</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>Interrupt</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>ENDPOINT_TYPE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[17:17]</bitRange>
-              <description>Trigger an interrupt if a STALL is sent. Intended for debug only.</description>
-              <name>INTERRUPT_ON_STALL</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[16:16]</bitRange>
-              <description>Trigger an interrupt if a NAK is sent. Intended for debug only.</description>
-              <name>INTERRUPT_ON_NAK</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[15:0]</bitRange>
-              <description>64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.</description>
-              <name>BUFFER_ADDRESS</name>
-            </field>
-          </fields>
-          <name>EP8_IN_CONTROL</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0044</addressOffset>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[31:31]</bitRange>
-              <description>Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.</description>
-              <name>ENABLE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[30:30]</bitRange>
-              <description>This endpoint is double buffered.</description>
-              <name>DOUBLE_BUFFERED</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[29:29]</bitRange>
-              <description>Trigger an interrupt each time a buffer is done.</description>
-              <name>INTERRUPT_PER_BUFF</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[28:28]</bitRange>
-              <description>Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.</description>
-              <name>INTERRUPT_PER_DOUBLE_BUFF</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[27:26]</bitRange>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>Control</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>Isochronous</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>Bulk</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>Interrupt</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>ENDPOINT_TYPE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[17:17]</bitRange>
-              <description>Trigger an interrupt if a STALL is sent. Intended for debug only.</description>
-              <name>INTERRUPT_ON_STALL</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[16:16]</bitRange>
-              <description>Trigger an interrupt if a NAK is sent. Intended for debug only.</description>
-              <name>INTERRUPT_ON_NAK</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[15:0]</bitRange>
-              <description>64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.</description>
-              <name>BUFFER_ADDRESS</name>
-            </field>
-          </fields>
-          <name>EP8_OUT_CONTROL</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0048</addressOffset>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[31:31]</bitRange>
-              <description>Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.</description>
-              <name>ENABLE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[30:30]</bitRange>
-              <description>This endpoint is double buffered.</description>
-              <name>DOUBLE_BUFFERED</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[29:29]</bitRange>
-              <description>Trigger an interrupt each time a buffer is done.</description>
-              <name>INTERRUPT_PER_BUFF</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[28:28]</bitRange>
-              <description>Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.</description>
-              <name>INTERRUPT_PER_DOUBLE_BUFF</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[27:26]</bitRange>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>Control</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>Isochronous</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>Bulk</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>Interrupt</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>ENDPOINT_TYPE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[17:17]</bitRange>
-              <description>Trigger an interrupt if a STALL is sent. Intended for debug only.</description>
-              <name>INTERRUPT_ON_STALL</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[16:16]</bitRange>
-              <description>Trigger an interrupt if a NAK is sent. Intended for debug only.</description>
-              <name>INTERRUPT_ON_NAK</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[15:0]</bitRange>
-              <description>64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.</description>
-              <name>BUFFER_ADDRESS</name>
-            </field>
-          </fields>
-          <name>EP9_IN_CONTROL</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x004c</addressOffset>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[31:31]</bitRange>
-              <description>Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.</description>
-              <name>ENABLE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[30:30]</bitRange>
-              <description>This endpoint is double buffered.</description>
-              <name>DOUBLE_BUFFERED</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[29:29]</bitRange>
-              <description>Trigger an interrupt each time a buffer is done.</description>
-              <name>INTERRUPT_PER_BUFF</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[28:28]</bitRange>
-              <description>Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.</description>
-              <name>INTERRUPT_PER_DOUBLE_BUFF</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[27:26]</bitRange>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>Control</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>Isochronous</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>Bulk</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>Interrupt</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>ENDPOINT_TYPE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[17:17]</bitRange>
-              <description>Trigger an interrupt if a STALL is sent. Intended for debug only.</description>
-              <name>INTERRUPT_ON_STALL</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[16:16]</bitRange>
-              <description>Trigger an interrupt if a NAK is sent. Intended for debug only.</description>
-              <name>INTERRUPT_ON_NAK</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[15:0]</bitRange>
-              <description>64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.</description>
-              <name>BUFFER_ADDRESS</name>
-            </field>
-          </fields>
-          <name>EP9_OUT_CONTROL</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0050</addressOffset>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[31:31]</bitRange>
-              <description>Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.</description>
-              <name>ENABLE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[30:30]</bitRange>
-              <description>This endpoint is double buffered.</description>
-              <name>DOUBLE_BUFFERED</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[29:29]</bitRange>
-              <description>Trigger an interrupt each time a buffer is done.</description>
-              <name>INTERRUPT_PER_BUFF</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[28:28]</bitRange>
-              <description>Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.</description>
-              <name>INTERRUPT_PER_DOUBLE_BUFF</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[27:26]</bitRange>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>Control</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>Isochronous</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>Bulk</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>Interrupt</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>ENDPOINT_TYPE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[17:17]</bitRange>
-              <description>Trigger an interrupt if a STALL is sent. Intended for debug only.</description>
-              <name>INTERRUPT_ON_STALL</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[16:16]</bitRange>
-              <description>Trigger an interrupt if a NAK is sent. Intended for debug only.</description>
-              <name>INTERRUPT_ON_NAK</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[15:0]</bitRange>
-              <description>64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.</description>
-              <name>BUFFER_ADDRESS</name>
-            </field>
-          </fields>
-          <name>EP10_IN_CONTROL</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0054</addressOffset>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[31:31]</bitRange>
-              <description>Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.</description>
-              <name>ENABLE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[30:30]</bitRange>
-              <description>This endpoint is double buffered.</description>
-              <name>DOUBLE_BUFFERED</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[29:29]</bitRange>
-              <description>Trigger an interrupt each time a buffer is done.</description>
-              <name>INTERRUPT_PER_BUFF</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[28:28]</bitRange>
-              <description>Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.</description>
-              <name>INTERRUPT_PER_DOUBLE_BUFF</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[27:26]</bitRange>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>Control</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>Isochronous</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>Bulk</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>Interrupt</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>ENDPOINT_TYPE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[17:17]</bitRange>
-              <description>Trigger an interrupt if a STALL is sent. Intended for debug only.</description>
-              <name>INTERRUPT_ON_STALL</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[16:16]</bitRange>
-              <description>Trigger an interrupt if a NAK is sent. Intended for debug only.</description>
-              <name>INTERRUPT_ON_NAK</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[15:0]</bitRange>
-              <description>64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.</description>
-              <name>BUFFER_ADDRESS</name>
-            </field>
-          </fields>
-          <name>EP10_OUT_CONTROL</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0058</addressOffset>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[31:31]</bitRange>
-              <description>Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.</description>
-              <name>ENABLE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[30:30]</bitRange>
-              <description>This endpoint is double buffered.</description>
-              <name>DOUBLE_BUFFERED</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[29:29]</bitRange>
-              <description>Trigger an interrupt each time a buffer is done.</description>
-              <name>INTERRUPT_PER_BUFF</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[28:28]</bitRange>
-              <description>Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.</description>
-              <name>INTERRUPT_PER_DOUBLE_BUFF</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[27:26]</bitRange>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>Control</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>Isochronous</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>Bulk</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>Interrupt</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>ENDPOINT_TYPE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[17:17]</bitRange>
-              <description>Trigger an interrupt if a STALL is sent. Intended for debug only.</description>
-              <name>INTERRUPT_ON_STALL</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[16:16]</bitRange>
-              <description>Trigger an interrupt if a NAK is sent. Intended for debug only.</description>
-              <name>INTERRUPT_ON_NAK</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[15:0]</bitRange>
-              <description>64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.</description>
-              <name>BUFFER_ADDRESS</name>
-            </field>
-          </fields>
-          <name>EP11_IN_CONTROL</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x005c</addressOffset>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[31:31]</bitRange>
-              <description>Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.</description>
-              <name>ENABLE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[30:30]</bitRange>
-              <description>This endpoint is double buffered.</description>
-              <name>DOUBLE_BUFFERED</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[29:29]</bitRange>
-              <description>Trigger an interrupt each time a buffer is done.</description>
-              <name>INTERRUPT_PER_BUFF</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[28:28]</bitRange>
-              <description>Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.</description>
-              <name>INTERRUPT_PER_DOUBLE_BUFF</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[27:26]</bitRange>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>Control</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>Isochronous</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>Bulk</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>Interrupt</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>ENDPOINT_TYPE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[17:17]</bitRange>
-              <description>Trigger an interrupt if a STALL is sent. Intended for debug only.</description>
-              <name>INTERRUPT_ON_STALL</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[16:16]</bitRange>
-              <description>Trigger an interrupt if a NAK is sent. Intended for debug only.</description>
-              <name>INTERRUPT_ON_NAK</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[15:0]</bitRange>
-              <description>64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.</description>
-              <name>BUFFER_ADDRESS</name>
-            </field>
-          </fields>
-          <name>EP11_OUT_CONTROL</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0060</addressOffset>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[31:31]</bitRange>
-              <description>Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.</description>
-              <name>ENABLE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[30:30]</bitRange>
-              <description>This endpoint is double buffered.</description>
-              <name>DOUBLE_BUFFERED</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[29:29]</bitRange>
-              <description>Trigger an interrupt each time a buffer is done.</description>
-              <name>INTERRUPT_PER_BUFF</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[28:28]</bitRange>
-              <description>Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.</description>
-              <name>INTERRUPT_PER_DOUBLE_BUFF</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[27:26]</bitRange>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>Control</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>Isochronous</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>Bulk</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>Interrupt</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>ENDPOINT_TYPE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[17:17]</bitRange>
-              <description>Trigger an interrupt if a STALL is sent. Intended for debug only.</description>
-              <name>INTERRUPT_ON_STALL</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[16:16]</bitRange>
-              <description>Trigger an interrupt if a NAK is sent. Intended for debug only.</description>
-              <name>INTERRUPT_ON_NAK</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[15:0]</bitRange>
-              <description>64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.</description>
-              <name>BUFFER_ADDRESS</name>
-            </field>
-          </fields>
-          <name>EP12_IN_CONTROL</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0064</addressOffset>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[31:31]</bitRange>
-              <description>Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.</description>
-              <name>ENABLE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[30:30]</bitRange>
-              <description>This endpoint is double buffered.</description>
-              <name>DOUBLE_BUFFERED</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[29:29]</bitRange>
-              <description>Trigger an interrupt each time a buffer is done.</description>
-              <name>INTERRUPT_PER_BUFF</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[28:28]</bitRange>
-              <description>Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.</description>
-              <name>INTERRUPT_PER_DOUBLE_BUFF</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[27:26]</bitRange>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>Control</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>Isochronous</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>Bulk</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>Interrupt</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>ENDPOINT_TYPE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[17:17]</bitRange>
-              <description>Trigger an interrupt if a STALL is sent. Intended for debug only.</description>
-              <name>INTERRUPT_ON_STALL</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[16:16]</bitRange>
-              <description>Trigger an interrupt if a NAK is sent. Intended for debug only.</description>
-              <name>INTERRUPT_ON_NAK</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[15:0]</bitRange>
-              <description>64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.</description>
-              <name>BUFFER_ADDRESS</name>
-            </field>
-          </fields>
-          <name>EP12_OUT_CONTROL</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0068</addressOffset>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[31:31]</bitRange>
-              <description>Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.</description>
-              <name>ENABLE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[30:30]</bitRange>
-              <description>This endpoint is double buffered.</description>
-              <name>DOUBLE_BUFFERED</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[29:29]</bitRange>
-              <description>Trigger an interrupt each time a buffer is done.</description>
-              <name>INTERRUPT_PER_BUFF</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[28:28]</bitRange>
-              <description>Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.</description>
-              <name>INTERRUPT_PER_DOUBLE_BUFF</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[27:26]</bitRange>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>Control</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>Isochronous</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>Bulk</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>Interrupt</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>ENDPOINT_TYPE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[17:17]</bitRange>
-              <description>Trigger an interrupt if a STALL is sent. Intended for debug only.</description>
-              <name>INTERRUPT_ON_STALL</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[16:16]</bitRange>
-              <description>Trigger an interrupt if a NAK is sent. Intended for debug only.</description>
-              <name>INTERRUPT_ON_NAK</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[15:0]</bitRange>
-              <description>64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.</description>
-              <name>BUFFER_ADDRESS</name>
-            </field>
-          </fields>
-          <name>EP13_IN_CONTROL</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x006c</addressOffset>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[31:31]</bitRange>
-              <description>Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.</description>
-              <name>ENABLE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[30:30]</bitRange>
-              <description>This endpoint is double buffered.</description>
-              <name>DOUBLE_BUFFERED</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[29:29]</bitRange>
-              <description>Trigger an interrupt each time a buffer is done.</description>
-              <name>INTERRUPT_PER_BUFF</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[28:28]</bitRange>
-              <description>Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.</description>
-              <name>INTERRUPT_PER_DOUBLE_BUFF</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[27:26]</bitRange>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>Control</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>Isochronous</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>Bulk</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>Interrupt</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>ENDPOINT_TYPE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[17:17]</bitRange>
-              <description>Trigger an interrupt if a STALL is sent. Intended for debug only.</description>
-              <name>INTERRUPT_ON_STALL</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[16:16]</bitRange>
-              <description>Trigger an interrupt if a NAK is sent. Intended for debug only.</description>
-              <name>INTERRUPT_ON_NAK</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[15:0]</bitRange>
-              <description>64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.</description>
-              <name>BUFFER_ADDRESS</name>
-            </field>
-          </fields>
-          <name>EP13_OUT_CONTROL</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0070</addressOffset>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[31:31]</bitRange>
-              <description>Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.</description>
-              <name>ENABLE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[30:30]</bitRange>
-              <description>This endpoint is double buffered.</description>
-              <name>DOUBLE_BUFFERED</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[29:29]</bitRange>
-              <description>Trigger an interrupt each time a buffer is done.</description>
-              <name>INTERRUPT_PER_BUFF</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[28:28]</bitRange>
-              <description>Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.</description>
-              <name>INTERRUPT_PER_DOUBLE_BUFF</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[27:26]</bitRange>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>Control</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>Isochronous</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>Bulk</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>Interrupt</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>ENDPOINT_TYPE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[17:17]</bitRange>
-              <description>Trigger an interrupt if a STALL is sent. Intended for debug only.</description>
-              <name>INTERRUPT_ON_STALL</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[16:16]</bitRange>
-              <description>Trigger an interrupt if a NAK is sent. Intended for debug only.</description>
-              <name>INTERRUPT_ON_NAK</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[15:0]</bitRange>
-              <description>64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.</description>
-              <name>BUFFER_ADDRESS</name>
-            </field>
-          </fields>
-          <name>EP14_IN_CONTROL</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0074</addressOffset>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[31:31]</bitRange>
-              <description>Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.</description>
-              <name>ENABLE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[30:30]</bitRange>
-              <description>This endpoint is double buffered.</description>
-              <name>DOUBLE_BUFFERED</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[29:29]</bitRange>
-              <description>Trigger an interrupt each time a buffer is done.</description>
-              <name>INTERRUPT_PER_BUFF</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[28:28]</bitRange>
-              <description>Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.</description>
-              <name>INTERRUPT_PER_DOUBLE_BUFF</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[27:26]</bitRange>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>Control</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>Isochronous</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>Bulk</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>Interrupt</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>ENDPOINT_TYPE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[17:17]</bitRange>
-              <description>Trigger an interrupt if a STALL is sent. Intended for debug only.</description>
-              <name>INTERRUPT_ON_STALL</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[16:16]</bitRange>
-              <description>Trigger an interrupt if a NAK is sent. Intended for debug only.</description>
-              <name>INTERRUPT_ON_NAK</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[15:0]</bitRange>
-              <description>64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.</description>
-              <name>BUFFER_ADDRESS</name>
-            </field>
-          </fields>
-          <name>EP14_OUT_CONTROL</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0078</addressOffset>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[31:31]</bitRange>
-              <description>Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.</description>
-              <name>ENABLE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[30:30]</bitRange>
-              <description>This endpoint is double buffered.</description>
-              <name>DOUBLE_BUFFERED</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[29:29]</bitRange>
-              <description>Trigger an interrupt each time a buffer is done.</description>
-              <name>INTERRUPT_PER_BUFF</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[28:28]</bitRange>
-              <description>Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.</description>
-              <name>INTERRUPT_PER_DOUBLE_BUFF</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[27:26]</bitRange>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>Control</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>Isochronous</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>Bulk</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>Interrupt</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>ENDPOINT_TYPE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[17:17]</bitRange>
-              <description>Trigger an interrupt if a STALL is sent. Intended for debug only.</description>
-              <name>INTERRUPT_ON_STALL</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[16:16]</bitRange>
-              <description>Trigger an interrupt if a NAK is sent. Intended for debug only.</description>
-              <name>INTERRUPT_ON_NAK</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[15:0]</bitRange>
-              <description>64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.</description>
-              <name>BUFFER_ADDRESS</name>
-            </field>
-          </fields>
-          <name>EP15_IN_CONTROL</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x007c</addressOffset>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[31:31]</bitRange>
-              <description>Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.</description>
-              <name>ENABLE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[30:30]</bitRange>
-              <description>This endpoint is double buffered.</description>
-              <name>DOUBLE_BUFFERED</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[29:29]</bitRange>
-              <description>Trigger an interrupt each time a buffer is done.</description>
-              <name>INTERRUPT_PER_BUFF</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[28:28]</bitRange>
-              <description>Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.</description>
-              <name>INTERRUPT_PER_DOUBLE_BUFF</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[27:26]</bitRange>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>Control</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>Isochronous</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>Bulk</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>Interrupt</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>ENDPOINT_TYPE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[17:17]</bitRange>
-              <description>Trigger an interrupt if a STALL is sent. Intended for debug only.</description>
-              <name>INTERRUPT_ON_STALL</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[16:16]</bitRange>
-              <description>Trigger an interrupt if a NAK is sent. Intended for debug only.</description>
-              <name>INTERRUPT_ON_NAK</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[15:0]</bitRange>
-              <description>64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.</description>
-              <name>BUFFER_ADDRESS</name>
-            </field>
-          </fields>
-          <name>EP15_OUT_CONTROL</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0080</addressOffset>
-          <description>Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n
-            Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[31:31]</bitRange>
-              <description>Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
-              <name>FULL_1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[30:30]</bitRange>
-              <description>Buffer 1 is the last buffer of the transfer.</description>
-              <name>LAST_1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[29:29]</bitRange>
-              <description>The data pid of buffer 1.</description>
-              <name>PID_1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[28:27]</bitRange>
-              <description>The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n
-                For a non Isochronous endpoint the offset is always 64 bytes.</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>128</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>256</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>512</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>1024</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>DOUBLE_BUFFER_ISO_OFFSET</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[26:26]</bitRange>
-              <description>Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
-              <name>AVAILABLE_1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[25:16]</bitRange>
-              <description>The length of the data in buffer 1.</description>
-              <name>LENGTH_1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[15:15]</bitRange>
-              <description>Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
-              <name>FULL_0</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[14:14]</bitRange>
-              <description>Buffer 0 is the last buffer of the transfer.</description>
-              <name>LAST_0</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[13:13]</bitRange>
-              <description>The data pid of buffer 0.</description>
-              <name>PID_0</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[12:12]</bitRange>
-              <description>Reset the buffer selector to buffer 0.</description>
-              <name>RESET</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[11:11]</bitRange>
-              <description>Reply with a stall (valid for both buffers).</description>
-              <name>STALL</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[10:10]</bitRange>
-              <description>Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
-              <name>AVAILABLE_0</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[9:0]</bitRange>
-              <description>The length of the data in buffer 0.</description>
-              <name>LENGTH_0</name>
-            </field>
-          </fields>
-          <name>EP0_IN_BUFFER_CONTROL</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0084</addressOffset>
-          <description>Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n
-            Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[31:31]</bitRange>
-              <description>Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
-              <name>FULL_1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[30:30]</bitRange>
-              <description>Buffer 1 is the last buffer of the transfer.</description>
-              <name>LAST_1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[29:29]</bitRange>
-              <description>The data pid of buffer 1.</description>
-              <name>PID_1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[28:27]</bitRange>
-              <description>The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n
-                For a non Isochronous endpoint the offset is always 64 bytes.</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>128</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>256</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>512</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>1024</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>DOUBLE_BUFFER_ISO_OFFSET</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[26:26]</bitRange>
-              <description>Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
-              <name>AVAILABLE_1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[25:16]</bitRange>
-              <description>The length of the data in buffer 1.</description>
-              <name>LENGTH_1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[15:15]</bitRange>
-              <description>Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
-              <name>FULL_0</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[14:14]</bitRange>
-              <description>Buffer 0 is the last buffer of the transfer.</description>
-              <name>LAST_0</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[13:13]</bitRange>
-              <description>The data pid of buffer 0.</description>
-              <name>PID_0</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[12:12]</bitRange>
-              <description>Reset the buffer selector to buffer 0.</description>
-              <name>RESET</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[11:11]</bitRange>
-              <description>Reply with a stall (valid for both buffers).</description>
-              <name>STALL</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[10:10]</bitRange>
-              <description>Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
-              <name>AVAILABLE_0</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[9:0]</bitRange>
-              <description>The length of the data in buffer 0.</description>
-              <name>LENGTH_0</name>
-            </field>
-          </fields>
-          <name>EP0_OUT_BUFFER_CONTROL</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0088</addressOffset>
-          <description>Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n
-            Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[31:31]</bitRange>
-              <description>Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
-              <name>FULL_1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[30:30]</bitRange>
-              <description>Buffer 1 is the last buffer of the transfer.</description>
-              <name>LAST_1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[29:29]</bitRange>
-              <description>The data pid of buffer 1.</description>
-              <name>PID_1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[28:27]</bitRange>
-              <description>The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n
-                For a non Isochronous endpoint the offset is always 64 bytes.</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>128</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>256</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>512</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>1024</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>DOUBLE_BUFFER_ISO_OFFSET</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[26:26]</bitRange>
-              <description>Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
-              <name>AVAILABLE_1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[25:16]</bitRange>
-              <description>The length of the data in buffer 1.</description>
-              <name>LENGTH_1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[15:15]</bitRange>
-              <description>Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
-              <name>FULL_0</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[14:14]</bitRange>
-              <description>Buffer 0 is the last buffer of the transfer.</description>
-              <name>LAST_0</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[13:13]</bitRange>
-              <description>The data pid of buffer 0.</description>
-              <name>PID_0</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[12:12]</bitRange>
-              <description>Reset the buffer selector to buffer 0.</description>
-              <name>RESET</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[11:11]</bitRange>
-              <description>Reply with a stall (valid for both buffers).</description>
-              <name>STALL</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[10:10]</bitRange>
-              <description>Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
-              <name>AVAILABLE_0</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[9:0]</bitRange>
-              <description>The length of the data in buffer 0.</description>
-              <name>LENGTH_0</name>
-            </field>
-          </fields>
-          <name>EP1_IN_BUFFER_CONTROL</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x008c</addressOffset>
-          <description>Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n
-            Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[31:31]</bitRange>
-              <description>Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
-              <name>FULL_1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[30:30]</bitRange>
-              <description>Buffer 1 is the last buffer of the transfer.</description>
-              <name>LAST_1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[29:29]</bitRange>
-              <description>The data pid of buffer 1.</description>
-              <name>PID_1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[28:27]</bitRange>
-              <description>The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n
-                For a non Isochronous endpoint the offset is always 64 bytes.</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>128</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>256</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>512</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>1024</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>DOUBLE_BUFFER_ISO_OFFSET</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[26:26]</bitRange>
-              <description>Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
-              <name>AVAILABLE_1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[25:16]</bitRange>
-              <description>The length of the data in buffer 1.</description>
-              <name>LENGTH_1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[15:15]</bitRange>
-              <description>Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
-              <name>FULL_0</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[14:14]</bitRange>
-              <description>Buffer 0 is the last buffer of the transfer.</description>
-              <name>LAST_0</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[13:13]</bitRange>
-              <description>The data pid of buffer 0.</description>
-              <name>PID_0</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[12:12]</bitRange>
-              <description>Reset the buffer selector to buffer 0.</description>
-              <name>RESET</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[11:11]</bitRange>
-              <description>Reply with a stall (valid for both buffers).</description>
-              <name>STALL</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[10:10]</bitRange>
-              <description>Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
-              <name>AVAILABLE_0</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[9:0]</bitRange>
-              <description>The length of the data in buffer 0.</description>
-              <name>LENGTH_0</name>
-            </field>
-          </fields>
-          <name>EP1_OUT_BUFFER_CONTROL</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0090</addressOffset>
-          <description>Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n
-            Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[31:31]</bitRange>
-              <description>Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
-              <name>FULL_1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[30:30]</bitRange>
-              <description>Buffer 1 is the last buffer of the transfer.</description>
-              <name>LAST_1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[29:29]</bitRange>
-              <description>The data pid of buffer 1.</description>
-              <name>PID_1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[28:27]</bitRange>
-              <description>The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n
-                For a non Isochronous endpoint the offset is always 64 bytes.</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>128</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>256</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>512</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>1024</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>DOUBLE_BUFFER_ISO_OFFSET</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[26:26]</bitRange>
-              <description>Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
-              <name>AVAILABLE_1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[25:16]</bitRange>
-              <description>The length of the data in buffer 1.</description>
-              <name>LENGTH_1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[15:15]</bitRange>
-              <description>Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
-              <name>FULL_0</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[14:14]</bitRange>
-              <description>Buffer 0 is the last buffer of the transfer.</description>
-              <name>LAST_0</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[13:13]</bitRange>
-              <description>The data pid of buffer 0.</description>
-              <name>PID_0</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[12:12]</bitRange>
-              <description>Reset the buffer selector to buffer 0.</description>
-              <name>RESET</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[11:11]</bitRange>
-              <description>Reply with a stall (valid for both buffers).</description>
-              <name>STALL</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[10:10]</bitRange>
-              <description>Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
-              <name>AVAILABLE_0</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[9:0]</bitRange>
-              <description>The length of the data in buffer 0.</description>
-              <name>LENGTH_0</name>
-            </field>
-          </fields>
-          <name>EP2_IN_BUFFER_CONTROL</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0094</addressOffset>
-          <description>Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n
-            Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[31:31]</bitRange>
-              <description>Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
-              <name>FULL_1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[30:30]</bitRange>
-              <description>Buffer 1 is the last buffer of the transfer.</description>
-              <name>LAST_1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[29:29]</bitRange>
-              <description>The data pid of buffer 1.</description>
-              <name>PID_1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[28:27]</bitRange>
-              <description>The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n
-                For a non Isochronous endpoint the offset is always 64 bytes.</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>128</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>256</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>512</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>1024</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>DOUBLE_BUFFER_ISO_OFFSET</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[26:26]</bitRange>
-              <description>Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
-              <name>AVAILABLE_1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[25:16]</bitRange>
-              <description>The length of the data in buffer 1.</description>
-              <name>LENGTH_1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[15:15]</bitRange>
-              <description>Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
-              <name>FULL_0</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[14:14]</bitRange>
-              <description>Buffer 0 is the last buffer of the transfer.</description>
-              <name>LAST_0</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[13:13]</bitRange>
-              <description>The data pid of buffer 0.</description>
-              <name>PID_0</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[12:12]</bitRange>
-              <description>Reset the buffer selector to buffer 0.</description>
-              <name>RESET</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[11:11]</bitRange>
-              <description>Reply with a stall (valid for both buffers).</description>
-              <name>STALL</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[10:10]</bitRange>
-              <description>Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
-              <name>AVAILABLE_0</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[9:0]</bitRange>
-              <description>The length of the data in buffer 0.</description>
-              <name>LENGTH_0</name>
-            </field>
-          </fields>
-          <name>EP2_OUT_BUFFER_CONTROL</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0098</addressOffset>
-          <description>Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n
-            Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[31:31]</bitRange>
-              <description>Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
-              <name>FULL_1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[30:30]</bitRange>
-              <description>Buffer 1 is the last buffer of the transfer.</description>
-              <name>LAST_1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[29:29]</bitRange>
-              <description>The data pid of buffer 1.</description>
-              <name>PID_1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[28:27]</bitRange>
-              <description>The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n
-                For a non Isochronous endpoint the offset is always 64 bytes.</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>128</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>256</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>512</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>1024</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>DOUBLE_BUFFER_ISO_OFFSET</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[26:26]</bitRange>
-              <description>Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
-              <name>AVAILABLE_1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[25:16]</bitRange>
-              <description>The length of the data in buffer 1.</description>
-              <name>LENGTH_1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[15:15]</bitRange>
-              <description>Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
-              <name>FULL_0</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[14:14]</bitRange>
-              <description>Buffer 0 is the last buffer of the transfer.</description>
-              <name>LAST_0</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[13:13]</bitRange>
-              <description>The data pid of buffer 0.</description>
-              <name>PID_0</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[12:12]</bitRange>
-              <description>Reset the buffer selector to buffer 0.</description>
-              <name>RESET</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[11:11]</bitRange>
-              <description>Reply with a stall (valid for both buffers).</description>
-              <name>STALL</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[10:10]</bitRange>
-              <description>Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
-              <name>AVAILABLE_0</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[9:0]</bitRange>
-              <description>The length of the data in buffer 0.</description>
-              <name>LENGTH_0</name>
-            </field>
-          </fields>
-          <name>EP3_IN_BUFFER_CONTROL</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x009c</addressOffset>
-          <description>Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n
-            Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[31:31]</bitRange>
-              <description>Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
-              <name>FULL_1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[30:30]</bitRange>
-              <description>Buffer 1 is the last buffer of the transfer.</description>
-              <name>LAST_1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[29:29]</bitRange>
-              <description>The data pid of buffer 1.</description>
-              <name>PID_1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[28:27]</bitRange>
-              <description>The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n
-                For a non Isochronous endpoint the offset is always 64 bytes.</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>128</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>256</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>512</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>1024</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>DOUBLE_BUFFER_ISO_OFFSET</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[26:26]</bitRange>
-              <description>Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
-              <name>AVAILABLE_1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[25:16]</bitRange>
-              <description>The length of the data in buffer 1.</description>
-              <name>LENGTH_1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[15:15]</bitRange>
-              <description>Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
-              <name>FULL_0</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[14:14]</bitRange>
-              <description>Buffer 0 is the last buffer of the transfer.</description>
-              <name>LAST_0</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[13:13]</bitRange>
-              <description>The data pid of buffer 0.</description>
-              <name>PID_0</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[12:12]</bitRange>
-              <description>Reset the buffer selector to buffer 0.</description>
-              <name>RESET</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[11:11]</bitRange>
-              <description>Reply with a stall (valid for both buffers).</description>
-              <name>STALL</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[10:10]</bitRange>
-              <description>Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
-              <name>AVAILABLE_0</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[9:0]</bitRange>
-              <description>The length of the data in buffer 0.</description>
-              <name>LENGTH_0</name>
-            </field>
-          </fields>
-          <name>EP3_OUT_BUFFER_CONTROL</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x00a0</addressOffset>
-          <description>Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n
-            Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[31:31]</bitRange>
-              <description>Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
-              <name>FULL_1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[30:30]</bitRange>
-              <description>Buffer 1 is the last buffer of the transfer.</description>
-              <name>LAST_1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[29:29]</bitRange>
-              <description>The data pid of buffer 1.</description>
-              <name>PID_1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[28:27]</bitRange>
-              <description>The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n
-                For a non Isochronous endpoint the offset is always 64 bytes.</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>128</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>256</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>512</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>1024</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>DOUBLE_BUFFER_ISO_OFFSET</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[26:26]</bitRange>
-              <description>Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
-              <name>AVAILABLE_1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[25:16]</bitRange>
-              <description>The length of the data in buffer 1.</description>
-              <name>LENGTH_1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[15:15]</bitRange>
-              <description>Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
-              <name>FULL_0</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[14:14]</bitRange>
-              <description>Buffer 0 is the last buffer of the transfer.</description>
-              <name>LAST_0</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[13:13]</bitRange>
-              <description>The data pid of buffer 0.</description>
-              <name>PID_0</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[12:12]</bitRange>
-              <description>Reset the buffer selector to buffer 0.</description>
-              <name>RESET</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[11:11]</bitRange>
-              <description>Reply with a stall (valid for both buffers).</description>
-              <name>STALL</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[10:10]</bitRange>
-              <description>Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
-              <name>AVAILABLE_0</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[9:0]</bitRange>
-              <description>The length of the data in buffer 0.</description>
-              <name>LENGTH_0</name>
-            </field>
-          </fields>
-          <name>EP4_IN_BUFFER_CONTROL</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x00a4</addressOffset>
-          <description>Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n
-            Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[31:31]</bitRange>
-              <description>Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
-              <name>FULL_1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[30:30]</bitRange>
-              <description>Buffer 1 is the last buffer of the transfer.</description>
-              <name>LAST_1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[29:29]</bitRange>
-              <description>The data pid of buffer 1.</description>
-              <name>PID_1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[28:27]</bitRange>
-              <description>The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n
-                For a non Isochronous endpoint the offset is always 64 bytes.</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>128</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>256</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>512</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>1024</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>DOUBLE_BUFFER_ISO_OFFSET</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[26:26]</bitRange>
-              <description>Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
-              <name>AVAILABLE_1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[25:16]</bitRange>
-              <description>The length of the data in buffer 1.</description>
-              <name>LENGTH_1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[15:15]</bitRange>
-              <description>Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
-              <name>FULL_0</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[14:14]</bitRange>
-              <description>Buffer 0 is the last buffer of the transfer.</description>
-              <name>LAST_0</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[13:13]</bitRange>
-              <description>The data pid of buffer 0.</description>
-              <name>PID_0</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[12:12]</bitRange>
-              <description>Reset the buffer selector to buffer 0.</description>
-              <name>RESET</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[11:11]</bitRange>
-              <description>Reply with a stall (valid for both buffers).</description>
-              <name>STALL</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[10:10]</bitRange>
-              <description>Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
-              <name>AVAILABLE_0</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[9:0]</bitRange>
-              <description>The length of the data in buffer 0.</description>
-              <name>LENGTH_0</name>
-            </field>
-          </fields>
-          <name>EP4_OUT_BUFFER_CONTROL</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x00a8</addressOffset>
-          <description>Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n
-            Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[31:31]</bitRange>
-              <description>Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
-              <name>FULL_1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[30:30]</bitRange>
-              <description>Buffer 1 is the last buffer of the transfer.</description>
-              <name>LAST_1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[29:29]</bitRange>
-              <description>The data pid of buffer 1.</description>
-              <name>PID_1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[28:27]</bitRange>
-              <description>The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n
-                For a non Isochronous endpoint the offset is always 64 bytes.</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>128</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>256</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>512</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>1024</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>DOUBLE_BUFFER_ISO_OFFSET</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[26:26]</bitRange>
-              <description>Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
-              <name>AVAILABLE_1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[25:16]</bitRange>
-              <description>The length of the data in buffer 1.</description>
-              <name>LENGTH_1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[15:15]</bitRange>
-              <description>Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
-              <name>FULL_0</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[14:14]</bitRange>
-              <description>Buffer 0 is the last buffer of the transfer.</description>
-              <name>LAST_0</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[13:13]</bitRange>
-              <description>The data pid of buffer 0.</description>
-              <name>PID_0</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[12:12]</bitRange>
-              <description>Reset the buffer selector to buffer 0.</description>
-              <name>RESET</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[11:11]</bitRange>
-              <description>Reply with a stall (valid for both buffers).</description>
-              <name>STALL</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[10:10]</bitRange>
-              <description>Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
-              <name>AVAILABLE_0</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[9:0]</bitRange>
-              <description>The length of the data in buffer 0.</description>
-              <name>LENGTH_0</name>
-            </field>
-          </fields>
-          <name>EP5_IN_BUFFER_CONTROL</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x00ac</addressOffset>
-          <description>Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n
-            Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[31:31]</bitRange>
-              <description>Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
-              <name>FULL_1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[30:30]</bitRange>
-              <description>Buffer 1 is the last buffer of the transfer.</description>
-              <name>LAST_1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[29:29]</bitRange>
-              <description>The data pid of buffer 1.</description>
-              <name>PID_1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[28:27]</bitRange>
-              <description>The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n
-                For a non Isochronous endpoint the offset is always 64 bytes.</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>128</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>256</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>512</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>1024</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>DOUBLE_BUFFER_ISO_OFFSET</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[26:26]</bitRange>
-              <description>Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
-              <name>AVAILABLE_1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[25:16]</bitRange>
-              <description>The length of the data in buffer 1.</description>
-              <name>LENGTH_1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[15:15]</bitRange>
-              <description>Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
-              <name>FULL_0</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[14:14]</bitRange>
-              <description>Buffer 0 is the last buffer of the transfer.</description>
-              <name>LAST_0</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[13:13]</bitRange>
-              <description>The data pid of buffer 0.</description>
-              <name>PID_0</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[12:12]</bitRange>
-              <description>Reset the buffer selector to buffer 0.</description>
-              <name>RESET</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[11:11]</bitRange>
-              <description>Reply with a stall (valid for both buffers).</description>
-              <name>STALL</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[10:10]</bitRange>
-              <description>Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
-              <name>AVAILABLE_0</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[9:0]</bitRange>
-              <description>The length of the data in buffer 0.</description>
-              <name>LENGTH_0</name>
-            </field>
-          </fields>
-          <name>EP5_OUT_BUFFER_CONTROL</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x00b0</addressOffset>
-          <description>Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n
-            Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[31:31]</bitRange>
-              <description>Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
-              <name>FULL_1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[30:30]</bitRange>
-              <description>Buffer 1 is the last buffer of the transfer.</description>
-              <name>LAST_1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[29:29]</bitRange>
-              <description>The data pid of buffer 1.</description>
-              <name>PID_1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[28:27]</bitRange>
-              <description>The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n
-                For a non Isochronous endpoint the offset is always 64 bytes.</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>128</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>256</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>512</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>1024</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>DOUBLE_BUFFER_ISO_OFFSET</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[26:26]</bitRange>
-              <description>Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
-              <name>AVAILABLE_1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[25:16]</bitRange>
-              <description>The length of the data in buffer 1.</description>
-              <name>LENGTH_1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[15:15]</bitRange>
-              <description>Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
-              <name>FULL_0</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[14:14]</bitRange>
-              <description>Buffer 0 is the last buffer of the transfer.</description>
-              <name>LAST_0</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[13:13]</bitRange>
-              <description>The data pid of buffer 0.</description>
-              <name>PID_0</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[12:12]</bitRange>
-              <description>Reset the buffer selector to buffer 0.</description>
-              <name>RESET</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[11:11]</bitRange>
-              <description>Reply with a stall (valid for both buffers).</description>
-              <name>STALL</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[10:10]</bitRange>
-              <description>Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
-              <name>AVAILABLE_0</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[9:0]</bitRange>
-              <description>The length of the data in buffer 0.</description>
-              <name>LENGTH_0</name>
-            </field>
-          </fields>
-          <name>EP6_IN_BUFFER_CONTROL</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x00b4</addressOffset>
-          <description>Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n
-            Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[31:31]</bitRange>
-              <description>Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
-              <name>FULL_1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[30:30]</bitRange>
-              <description>Buffer 1 is the last buffer of the transfer.</description>
-              <name>LAST_1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[29:29]</bitRange>
-              <description>The data pid of buffer 1.</description>
-              <name>PID_1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[28:27]</bitRange>
-              <description>The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n
-                For a non Isochronous endpoint the offset is always 64 bytes.</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>128</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>256</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>512</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>1024</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>DOUBLE_BUFFER_ISO_OFFSET</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[26:26]</bitRange>
-              <description>Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
-              <name>AVAILABLE_1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[25:16]</bitRange>
-              <description>The length of the data in buffer 1.</description>
-              <name>LENGTH_1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[15:15]</bitRange>
-              <description>Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
-              <name>FULL_0</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[14:14]</bitRange>
-              <description>Buffer 0 is the last buffer of the transfer.</description>
-              <name>LAST_0</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[13:13]</bitRange>
-              <description>The data pid of buffer 0.</description>
-              <name>PID_0</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[12:12]</bitRange>
-              <description>Reset the buffer selector to buffer 0.</description>
-              <name>RESET</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[11:11]</bitRange>
-              <description>Reply with a stall (valid for both buffers).</description>
-              <name>STALL</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[10:10]</bitRange>
-              <description>Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
-              <name>AVAILABLE_0</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[9:0]</bitRange>
-              <description>The length of the data in buffer 0.</description>
-              <name>LENGTH_0</name>
-            </field>
-          </fields>
-          <name>EP6_OUT_BUFFER_CONTROL</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x00b8</addressOffset>
-          <description>Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n
-            Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[31:31]</bitRange>
-              <description>Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
-              <name>FULL_1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[30:30]</bitRange>
-              <description>Buffer 1 is the last buffer of the transfer.</description>
-              <name>LAST_1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[29:29]</bitRange>
-              <description>The data pid of buffer 1.</description>
-              <name>PID_1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[28:27]</bitRange>
-              <description>The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n
-                For a non Isochronous endpoint the offset is always 64 bytes.</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>128</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>256</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>512</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>1024</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>DOUBLE_BUFFER_ISO_OFFSET</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[26:26]</bitRange>
-              <description>Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
-              <name>AVAILABLE_1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[25:16]</bitRange>
-              <description>The length of the data in buffer 1.</description>
-              <name>LENGTH_1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[15:15]</bitRange>
-              <description>Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
-              <name>FULL_0</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[14:14]</bitRange>
-              <description>Buffer 0 is the last buffer of the transfer.</description>
-              <name>LAST_0</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[13:13]</bitRange>
-              <description>The data pid of buffer 0.</description>
-              <name>PID_0</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[12:12]</bitRange>
-              <description>Reset the buffer selector to buffer 0.</description>
-              <name>RESET</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[11:11]</bitRange>
-              <description>Reply with a stall (valid for both buffers).</description>
-              <name>STALL</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[10:10]</bitRange>
-              <description>Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
-              <name>AVAILABLE_0</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[9:0]</bitRange>
-              <description>The length of the data in buffer 0.</description>
-              <name>LENGTH_0</name>
-            </field>
-          </fields>
-          <name>EP7_IN_BUFFER_CONTROL</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x00bc</addressOffset>
-          <description>Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n
-            Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[31:31]</bitRange>
-              <description>Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
-              <name>FULL_1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[30:30]</bitRange>
-              <description>Buffer 1 is the last buffer of the transfer.</description>
-              <name>LAST_1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[29:29]</bitRange>
-              <description>The data pid of buffer 1.</description>
-              <name>PID_1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[28:27]</bitRange>
-              <description>The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n
-                For a non Isochronous endpoint the offset is always 64 bytes.</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>128</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>256</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>512</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>1024</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>DOUBLE_BUFFER_ISO_OFFSET</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[26:26]</bitRange>
-              <description>Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
-              <name>AVAILABLE_1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[25:16]</bitRange>
-              <description>The length of the data in buffer 1.</description>
-              <name>LENGTH_1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[15:15]</bitRange>
-              <description>Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
-              <name>FULL_0</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[14:14]</bitRange>
-              <description>Buffer 0 is the last buffer of the transfer.</description>
-              <name>LAST_0</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[13:13]</bitRange>
-              <description>The data pid of buffer 0.</description>
-              <name>PID_0</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[12:12]</bitRange>
-              <description>Reset the buffer selector to buffer 0.</description>
-              <name>RESET</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[11:11]</bitRange>
-              <description>Reply with a stall (valid for both buffers).</description>
-              <name>STALL</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[10:10]</bitRange>
-              <description>Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
-              <name>AVAILABLE_0</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[9:0]</bitRange>
-              <description>The length of the data in buffer 0.</description>
-              <name>LENGTH_0</name>
-            </field>
-          </fields>
-          <name>EP7_OUT_BUFFER_CONTROL</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x00c0</addressOffset>
-          <description>Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n
-            Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[31:31]</bitRange>
-              <description>Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
-              <name>FULL_1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[30:30]</bitRange>
-              <description>Buffer 1 is the last buffer of the transfer.</description>
-              <name>LAST_1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[29:29]</bitRange>
-              <description>The data pid of buffer 1.</description>
-              <name>PID_1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[28:27]</bitRange>
-              <description>The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n
-                For a non Isochronous endpoint the offset is always 64 bytes.</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>128</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>256</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>512</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>1024</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>DOUBLE_BUFFER_ISO_OFFSET</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[26:26]</bitRange>
-              <description>Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
-              <name>AVAILABLE_1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[25:16]</bitRange>
-              <description>The length of the data in buffer 1.</description>
-              <name>LENGTH_1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[15:15]</bitRange>
-              <description>Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
-              <name>FULL_0</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[14:14]</bitRange>
-              <description>Buffer 0 is the last buffer of the transfer.</description>
-              <name>LAST_0</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[13:13]</bitRange>
-              <description>The data pid of buffer 0.</description>
-              <name>PID_0</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[12:12]</bitRange>
-              <description>Reset the buffer selector to buffer 0.</description>
-              <name>RESET</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[11:11]</bitRange>
-              <description>Reply with a stall (valid for both buffers).</description>
-              <name>STALL</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[10:10]</bitRange>
-              <description>Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
-              <name>AVAILABLE_0</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[9:0]</bitRange>
-              <description>The length of the data in buffer 0.</description>
-              <name>LENGTH_0</name>
-            </field>
-          </fields>
-          <name>EP8_IN_BUFFER_CONTROL</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x00c4</addressOffset>
-          <description>Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n
-            Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[31:31]</bitRange>
-              <description>Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
-              <name>FULL_1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[30:30]</bitRange>
-              <description>Buffer 1 is the last buffer of the transfer.</description>
-              <name>LAST_1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[29:29]</bitRange>
-              <description>The data pid of buffer 1.</description>
-              <name>PID_1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[28:27]</bitRange>
-              <description>The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n
-                For a non Isochronous endpoint the offset is always 64 bytes.</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>128</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>256</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>512</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>1024</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>DOUBLE_BUFFER_ISO_OFFSET</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[26:26]</bitRange>
-              <description>Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
-              <name>AVAILABLE_1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[25:16]</bitRange>
-              <description>The length of the data in buffer 1.</description>
-              <name>LENGTH_1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[15:15]</bitRange>
-              <description>Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
-              <name>FULL_0</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[14:14]</bitRange>
-              <description>Buffer 0 is the last buffer of the transfer.</description>
-              <name>LAST_0</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[13:13]</bitRange>
-              <description>The data pid of buffer 0.</description>
-              <name>PID_0</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[12:12]</bitRange>
-              <description>Reset the buffer selector to buffer 0.</description>
-              <name>RESET</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[11:11]</bitRange>
-              <description>Reply with a stall (valid for both buffers).</description>
-              <name>STALL</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[10:10]</bitRange>
-              <description>Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
-              <name>AVAILABLE_0</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[9:0]</bitRange>
-              <description>The length of the data in buffer 0.</description>
-              <name>LENGTH_0</name>
-            </field>
-          </fields>
-          <name>EP8_OUT_BUFFER_CONTROL</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x00c8</addressOffset>
-          <description>Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n
-            Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[31:31]</bitRange>
-              <description>Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
-              <name>FULL_1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[30:30]</bitRange>
-              <description>Buffer 1 is the last buffer of the transfer.</description>
-              <name>LAST_1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[29:29]</bitRange>
-              <description>The data pid of buffer 1.</description>
-              <name>PID_1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[28:27]</bitRange>
-              <description>The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n
-                For a non Isochronous endpoint the offset is always 64 bytes.</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>128</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>256</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>512</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>1024</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>DOUBLE_BUFFER_ISO_OFFSET</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[26:26]</bitRange>
-              <description>Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
-              <name>AVAILABLE_1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[25:16]</bitRange>
-              <description>The length of the data in buffer 1.</description>
-              <name>LENGTH_1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[15:15]</bitRange>
-              <description>Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
-              <name>FULL_0</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[14:14]</bitRange>
-              <description>Buffer 0 is the last buffer of the transfer.</description>
-              <name>LAST_0</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[13:13]</bitRange>
-              <description>The data pid of buffer 0.</description>
-              <name>PID_0</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[12:12]</bitRange>
-              <description>Reset the buffer selector to buffer 0.</description>
-              <name>RESET</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[11:11]</bitRange>
-              <description>Reply with a stall (valid for both buffers).</description>
-              <name>STALL</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[10:10]</bitRange>
-              <description>Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
-              <name>AVAILABLE_0</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[9:0]</bitRange>
-              <description>The length of the data in buffer 0.</description>
-              <name>LENGTH_0</name>
-            </field>
-          </fields>
-          <name>EP9_IN_BUFFER_CONTROL</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x00cc</addressOffset>
-          <description>Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n
-            Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[31:31]</bitRange>
-              <description>Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
-              <name>FULL_1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[30:30]</bitRange>
-              <description>Buffer 1 is the last buffer of the transfer.</description>
-              <name>LAST_1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[29:29]</bitRange>
-              <description>The data pid of buffer 1.</description>
-              <name>PID_1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[28:27]</bitRange>
-              <description>The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n
-                For a non Isochronous endpoint the offset is always 64 bytes.</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>128</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>256</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>512</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>1024</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>DOUBLE_BUFFER_ISO_OFFSET</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[26:26]</bitRange>
-              <description>Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
-              <name>AVAILABLE_1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[25:16]</bitRange>
-              <description>The length of the data in buffer 1.</description>
-              <name>LENGTH_1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[15:15]</bitRange>
-              <description>Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
-              <name>FULL_0</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[14:14]</bitRange>
-              <description>Buffer 0 is the last buffer of the transfer.</description>
-              <name>LAST_0</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[13:13]</bitRange>
-              <description>The data pid of buffer 0.</description>
-              <name>PID_0</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[12:12]</bitRange>
-              <description>Reset the buffer selector to buffer 0.</description>
-              <name>RESET</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[11:11]</bitRange>
-              <description>Reply with a stall (valid for both buffers).</description>
-              <name>STALL</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[10:10]</bitRange>
-              <description>Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
-              <name>AVAILABLE_0</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[9:0]</bitRange>
-              <description>The length of the data in buffer 0.</description>
-              <name>LENGTH_0</name>
-            </field>
-          </fields>
-          <name>EP9_OUT_BUFFER_CONTROL</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x00d0</addressOffset>
-          <description>Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n
-            Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[31:31]</bitRange>
-              <description>Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
-              <name>FULL_1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[30:30]</bitRange>
-              <description>Buffer 1 is the last buffer of the transfer.</description>
-              <name>LAST_1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[29:29]</bitRange>
-              <description>The data pid of buffer 1.</description>
-              <name>PID_1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[28:27]</bitRange>
-              <description>The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n
-                For a non Isochronous endpoint the offset is always 64 bytes.</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>128</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>256</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>512</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>1024</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>DOUBLE_BUFFER_ISO_OFFSET</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[26:26]</bitRange>
-              <description>Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
-              <name>AVAILABLE_1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[25:16]</bitRange>
-              <description>The length of the data in buffer 1.</description>
-              <name>LENGTH_1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[15:15]</bitRange>
-              <description>Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
-              <name>FULL_0</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[14:14]</bitRange>
-              <description>Buffer 0 is the last buffer of the transfer.</description>
-              <name>LAST_0</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[13:13]</bitRange>
-              <description>The data pid of buffer 0.</description>
-              <name>PID_0</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[12:12]</bitRange>
-              <description>Reset the buffer selector to buffer 0.</description>
-              <name>RESET</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[11:11]</bitRange>
-              <description>Reply with a stall (valid for both buffers).</description>
-              <name>STALL</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[10:10]</bitRange>
-              <description>Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
-              <name>AVAILABLE_0</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[9:0]</bitRange>
-              <description>The length of the data in buffer 0.</description>
-              <name>LENGTH_0</name>
-            </field>
-          </fields>
-          <name>EP10_IN_BUFFER_CONTROL</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x00d4</addressOffset>
-          <description>Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n
-            Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[31:31]</bitRange>
-              <description>Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
-              <name>FULL_1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[30:30]</bitRange>
-              <description>Buffer 1 is the last buffer of the transfer.</description>
-              <name>LAST_1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[29:29]</bitRange>
-              <description>The data pid of buffer 1.</description>
-              <name>PID_1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[28:27]</bitRange>
-              <description>The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n
-                For a non Isochronous endpoint the offset is always 64 bytes.</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>128</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>256</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>512</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>1024</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>DOUBLE_BUFFER_ISO_OFFSET</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[26:26]</bitRange>
-              <description>Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
-              <name>AVAILABLE_1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[25:16]</bitRange>
-              <description>The length of the data in buffer 1.</description>
-              <name>LENGTH_1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[15:15]</bitRange>
-              <description>Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
-              <name>FULL_0</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[14:14]</bitRange>
-              <description>Buffer 0 is the last buffer of the transfer.</description>
-              <name>LAST_0</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[13:13]</bitRange>
-              <description>The data pid of buffer 0.</description>
-              <name>PID_0</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[12:12]</bitRange>
-              <description>Reset the buffer selector to buffer 0.</description>
-              <name>RESET</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[11:11]</bitRange>
-              <description>Reply with a stall (valid for both buffers).</description>
-              <name>STALL</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[10:10]</bitRange>
-              <description>Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
-              <name>AVAILABLE_0</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[9:0]</bitRange>
-              <description>The length of the data in buffer 0.</description>
-              <name>LENGTH_0</name>
-            </field>
-          </fields>
-          <name>EP10_OUT_BUFFER_CONTROL</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x00d8</addressOffset>
-          <description>Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n
-            Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[31:31]</bitRange>
-              <description>Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
-              <name>FULL_1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[30:30]</bitRange>
-              <description>Buffer 1 is the last buffer of the transfer.</description>
-              <name>LAST_1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[29:29]</bitRange>
-              <description>The data pid of buffer 1.</description>
-              <name>PID_1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[28:27]</bitRange>
-              <description>The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n
-                For a non Isochronous endpoint the offset is always 64 bytes.</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>128</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>256</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>512</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>1024</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>DOUBLE_BUFFER_ISO_OFFSET</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[26:26]</bitRange>
-              <description>Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
-              <name>AVAILABLE_1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[25:16]</bitRange>
-              <description>The length of the data in buffer 1.</description>
-              <name>LENGTH_1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[15:15]</bitRange>
-              <description>Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
-              <name>FULL_0</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[14:14]</bitRange>
-              <description>Buffer 0 is the last buffer of the transfer.</description>
-              <name>LAST_0</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[13:13]</bitRange>
-              <description>The data pid of buffer 0.</description>
-              <name>PID_0</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[12:12]</bitRange>
-              <description>Reset the buffer selector to buffer 0.</description>
-              <name>RESET</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[11:11]</bitRange>
-              <description>Reply with a stall (valid for both buffers).</description>
-              <name>STALL</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[10:10]</bitRange>
-              <description>Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
-              <name>AVAILABLE_0</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[9:0]</bitRange>
-              <description>The length of the data in buffer 0.</description>
-              <name>LENGTH_0</name>
-            </field>
-          </fields>
-          <name>EP11_IN_BUFFER_CONTROL</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x00dc</addressOffset>
-          <description>Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n
-            Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[31:31]</bitRange>
-              <description>Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
-              <name>FULL_1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[30:30]</bitRange>
-              <description>Buffer 1 is the last buffer of the transfer.</description>
-              <name>LAST_1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[29:29]</bitRange>
-              <description>The data pid of buffer 1.</description>
-              <name>PID_1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[28:27]</bitRange>
-              <description>The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n
-                For a non Isochronous endpoint the offset is always 64 bytes.</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>128</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>256</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>512</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>1024</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>DOUBLE_BUFFER_ISO_OFFSET</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[26:26]</bitRange>
-              <description>Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
-              <name>AVAILABLE_1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[25:16]</bitRange>
-              <description>The length of the data in buffer 1.</description>
-              <name>LENGTH_1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[15:15]</bitRange>
-              <description>Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
-              <name>FULL_0</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[14:14]</bitRange>
-              <description>Buffer 0 is the last buffer of the transfer.</description>
-              <name>LAST_0</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[13:13]</bitRange>
-              <description>The data pid of buffer 0.</description>
-              <name>PID_0</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[12:12]</bitRange>
-              <description>Reset the buffer selector to buffer 0.</description>
-              <name>RESET</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[11:11]</bitRange>
-              <description>Reply with a stall (valid for both buffers).</description>
-              <name>STALL</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[10:10]</bitRange>
-              <description>Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
-              <name>AVAILABLE_0</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[9:0]</bitRange>
-              <description>The length of the data in buffer 0.</description>
-              <name>LENGTH_0</name>
-            </field>
-          </fields>
-          <name>EP11_OUT_BUFFER_CONTROL</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x00e0</addressOffset>
-          <description>Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n
-            Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[31:31]</bitRange>
-              <description>Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
-              <name>FULL_1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[30:30]</bitRange>
-              <description>Buffer 1 is the last buffer of the transfer.</description>
-              <name>LAST_1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[29:29]</bitRange>
-              <description>The data pid of buffer 1.</description>
-              <name>PID_1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[28:27]</bitRange>
-              <description>The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n
-                For a non Isochronous endpoint the offset is always 64 bytes.</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>128</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>256</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>512</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>1024</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>DOUBLE_BUFFER_ISO_OFFSET</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[26:26]</bitRange>
-              <description>Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
-              <name>AVAILABLE_1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[25:16]</bitRange>
-              <description>The length of the data in buffer 1.</description>
-              <name>LENGTH_1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[15:15]</bitRange>
-              <description>Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
-              <name>FULL_0</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[14:14]</bitRange>
-              <description>Buffer 0 is the last buffer of the transfer.</description>
-              <name>LAST_0</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[13:13]</bitRange>
-              <description>The data pid of buffer 0.</description>
-              <name>PID_0</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[12:12]</bitRange>
-              <description>Reset the buffer selector to buffer 0.</description>
-              <name>RESET</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[11:11]</bitRange>
-              <description>Reply with a stall (valid for both buffers).</description>
-              <name>STALL</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[10:10]</bitRange>
-              <description>Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
-              <name>AVAILABLE_0</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[9:0]</bitRange>
-              <description>The length of the data in buffer 0.</description>
-              <name>LENGTH_0</name>
-            </field>
-          </fields>
-          <name>EP12_IN_BUFFER_CONTROL</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x00e4</addressOffset>
-          <description>Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n
-            Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[31:31]</bitRange>
-              <description>Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
-              <name>FULL_1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[30:30]</bitRange>
-              <description>Buffer 1 is the last buffer of the transfer.</description>
-              <name>LAST_1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[29:29]</bitRange>
-              <description>The data pid of buffer 1.</description>
-              <name>PID_1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[28:27]</bitRange>
-              <description>The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n
-                For a non Isochronous endpoint the offset is always 64 bytes.</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>128</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>256</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>512</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>1024</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>DOUBLE_BUFFER_ISO_OFFSET</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[26:26]</bitRange>
-              <description>Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
-              <name>AVAILABLE_1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[25:16]</bitRange>
-              <description>The length of the data in buffer 1.</description>
-              <name>LENGTH_1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[15:15]</bitRange>
-              <description>Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
-              <name>FULL_0</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[14:14]</bitRange>
-              <description>Buffer 0 is the last buffer of the transfer.</description>
-              <name>LAST_0</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[13:13]</bitRange>
-              <description>The data pid of buffer 0.</description>
-              <name>PID_0</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[12:12]</bitRange>
-              <description>Reset the buffer selector to buffer 0.</description>
-              <name>RESET</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[11:11]</bitRange>
-              <description>Reply with a stall (valid for both buffers).</description>
-              <name>STALL</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[10:10]</bitRange>
-              <description>Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
-              <name>AVAILABLE_0</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[9:0]</bitRange>
-              <description>The length of the data in buffer 0.</description>
-              <name>LENGTH_0</name>
-            </field>
-          </fields>
-          <name>EP12_OUT_BUFFER_CONTROL</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x00e8</addressOffset>
-          <description>Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n
-            Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[31:31]</bitRange>
-              <description>Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
-              <name>FULL_1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[30:30]</bitRange>
-              <description>Buffer 1 is the last buffer of the transfer.</description>
-              <name>LAST_1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[29:29]</bitRange>
-              <description>The data pid of buffer 1.</description>
-              <name>PID_1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[28:27]</bitRange>
-              <description>The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n
-                For a non Isochronous endpoint the offset is always 64 bytes.</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>128</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>256</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>512</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>1024</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>DOUBLE_BUFFER_ISO_OFFSET</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[26:26]</bitRange>
-              <description>Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
-              <name>AVAILABLE_1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[25:16]</bitRange>
-              <description>The length of the data in buffer 1.</description>
-              <name>LENGTH_1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[15:15]</bitRange>
-              <description>Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
-              <name>FULL_0</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[14:14]</bitRange>
-              <description>Buffer 0 is the last buffer of the transfer.</description>
-              <name>LAST_0</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[13:13]</bitRange>
-              <description>The data pid of buffer 0.</description>
-              <name>PID_0</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[12:12]</bitRange>
-              <description>Reset the buffer selector to buffer 0.</description>
-              <name>RESET</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[11:11]</bitRange>
-              <description>Reply with a stall (valid for both buffers).</description>
-              <name>STALL</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[10:10]</bitRange>
-              <description>Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
-              <name>AVAILABLE_0</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[9:0]</bitRange>
-              <description>The length of the data in buffer 0.</description>
-              <name>LENGTH_0</name>
-            </field>
-          </fields>
-          <name>EP13_IN_BUFFER_CONTROL</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x00ec</addressOffset>
-          <description>Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n
-            Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[31:31]</bitRange>
-              <description>Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
-              <name>FULL_1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[30:30]</bitRange>
-              <description>Buffer 1 is the last buffer of the transfer.</description>
-              <name>LAST_1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[29:29]</bitRange>
-              <description>The data pid of buffer 1.</description>
-              <name>PID_1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[28:27]</bitRange>
-              <description>The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n
-                For a non Isochronous endpoint the offset is always 64 bytes.</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>128</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>256</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>512</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>1024</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>DOUBLE_BUFFER_ISO_OFFSET</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[26:26]</bitRange>
-              <description>Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
-              <name>AVAILABLE_1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[25:16]</bitRange>
-              <description>The length of the data in buffer 1.</description>
-              <name>LENGTH_1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[15:15]</bitRange>
-              <description>Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
-              <name>FULL_0</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[14:14]</bitRange>
-              <description>Buffer 0 is the last buffer of the transfer.</description>
-              <name>LAST_0</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[13:13]</bitRange>
-              <description>The data pid of buffer 0.</description>
-              <name>PID_0</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[12:12]</bitRange>
-              <description>Reset the buffer selector to buffer 0.</description>
-              <name>RESET</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[11:11]</bitRange>
-              <description>Reply with a stall (valid for both buffers).</description>
-              <name>STALL</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[10:10]</bitRange>
-              <description>Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
-              <name>AVAILABLE_0</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[9:0]</bitRange>
-              <description>The length of the data in buffer 0.</description>
-              <name>LENGTH_0</name>
-            </field>
-          </fields>
-          <name>EP13_OUT_BUFFER_CONTROL</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x00f0</addressOffset>
-          <description>Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n
-            Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[31:31]</bitRange>
-              <description>Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
-              <name>FULL_1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[30:30]</bitRange>
-              <description>Buffer 1 is the last buffer of the transfer.</description>
-              <name>LAST_1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[29:29]</bitRange>
-              <description>The data pid of buffer 1.</description>
-              <name>PID_1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[28:27]</bitRange>
-              <description>The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n
-                For a non Isochronous endpoint the offset is always 64 bytes.</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>128</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>256</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>512</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>1024</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>DOUBLE_BUFFER_ISO_OFFSET</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[26:26]</bitRange>
-              <description>Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
-              <name>AVAILABLE_1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[25:16]</bitRange>
-              <description>The length of the data in buffer 1.</description>
-              <name>LENGTH_1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[15:15]</bitRange>
-              <description>Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
-              <name>FULL_0</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[14:14]</bitRange>
-              <description>Buffer 0 is the last buffer of the transfer.</description>
-              <name>LAST_0</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[13:13]</bitRange>
-              <description>The data pid of buffer 0.</description>
-              <name>PID_0</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[12:12]</bitRange>
-              <description>Reset the buffer selector to buffer 0.</description>
-              <name>RESET</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[11:11]</bitRange>
-              <description>Reply with a stall (valid for both buffers).</description>
-              <name>STALL</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[10:10]</bitRange>
-              <description>Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
-              <name>AVAILABLE_0</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[9:0]</bitRange>
-              <description>The length of the data in buffer 0.</description>
-              <name>LENGTH_0</name>
-            </field>
-          </fields>
-          <name>EP14_IN_BUFFER_CONTROL</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x00f4</addressOffset>
-          <description>Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n
-            Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[31:31]</bitRange>
-              <description>Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
-              <name>FULL_1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[30:30]</bitRange>
-              <description>Buffer 1 is the last buffer of the transfer.</description>
-              <name>LAST_1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[29:29]</bitRange>
-              <description>The data pid of buffer 1.</description>
-              <name>PID_1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[28:27]</bitRange>
-              <description>The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n
-                For a non Isochronous endpoint the offset is always 64 bytes.</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>128</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>256</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>512</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>1024</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>DOUBLE_BUFFER_ISO_OFFSET</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[26:26]</bitRange>
-              <description>Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
-              <name>AVAILABLE_1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[25:16]</bitRange>
-              <description>The length of the data in buffer 1.</description>
-              <name>LENGTH_1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[15:15]</bitRange>
-              <description>Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
-              <name>FULL_0</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[14:14]</bitRange>
-              <description>Buffer 0 is the last buffer of the transfer.</description>
-              <name>LAST_0</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[13:13]</bitRange>
-              <description>The data pid of buffer 0.</description>
-              <name>PID_0</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[12:12]</bitRange>
-              <description>Reset the buffer selector to buffer 0.</description>
-              <name>RESET</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[11:11]</bitRange>
-              <description>Reply with a stall (valid for both buffers).</description>
-              <name>STALL</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[10:10]</bitRange>
-              <description>Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
-              <name>AVAILABLE_0</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[9:0]</bitRange>
-              <description>The length of the data in buffer 0.</description>
-              <name>LENGTH_0</name>
-            </field>
-          </fields>
-          <name>EP14_OUT_BUFFER_CONTROL</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x00f8</addressOffset>
-          <description>Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n
-            Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[31:31]</bitRange>
-              <description>Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
-              <name>FULL_1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[30:30]</bitRange>
-              <description>Buffer 1 is the last buffer of the transfer.</description>
-              <name>LAST_1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[29:29]</bitRange>
-              <description>The data pid of buffer 1.</description>
-              <name>PID_1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[28:27]</bitRange>
-              <description>The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n
-                For a non Isochronous endpoint the offset is always 64 bytes.</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>128</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>256</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>512</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>1024</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>DOUBLE_BUFFER_ISO_OFFSET</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[26:26]</bitRange>
-              <description>Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
-              <name>AVAILABLE_1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[25:16]</bitRange>
-              <description>The length of the data in buffer 1.</description>
-              <name>LENGTH_1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[15:15]</bitRange>
-              <description>Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
-              <name>FULL_0</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[14:14]</bitRange>
-              <description>Buffer 0 is the last buffer of the transfer.</description>
-              <name>LAST_0</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[13:13]</bitRange>
-              <description>The data pid of buffer 0.</description>
-              <name>PID_0</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[12:12]</bitRange>
-              <description>Reset the buffer selector to buffer 0.</description>
-              <name>RESET</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[11:11]</bitRange>
-              <description>Reply with a stall (valid for both buffers).</description>
-              <name>STALL</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[10:10]</bitRange>
-              <description>Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
-              <name>AVAILABLE_0</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[9:0]</bitRange>
-              <description>The length of the data in buffer 0.</description>
-              <name>LENGTH_0</name>
-            </field>
-          </fields>
-          <name>EP15_IN_BUFFER_CONTROL</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x00fc</addressOffset>
-          <description>Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n
-            Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[31:31]</bitRange>
-              <description>Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
-              <name>FULL_1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[30:30]</bitRange>
-              <description>Buffer 1 is the last buffer of the transfer.</description>
-              <name>LAST_1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[29:29]</bitRange>
-              <description>The data pid of buffer 1.</description>
-              <name>PID_1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[28:27]</bitRange>
-              <description>The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n
-                For a non Isochronous endpoint the offset is always 64 bytes.</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>128</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>256</name>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>512</name>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>1024</name>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>DOUBLE_BUFFER_ISO_OFFSET</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[26:26]</bitRange>
-              <description>Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
-              <name>AVAILABLE_1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[25:16]</bitRange>
-              <description>The length of the data in buffer 1.</description>
-              <name>LENGTH_1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[15:15]</bitRange>
-              <description>Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
-              <name>FULL_0</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[14:14]</bitRange>
-              <description>Buffer 0 is the last buffer of the transfer.</description>
-              <name>LAST_0</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[13:13]</bitRange>
-              <description>The data pid of buffer 0.</description>
-              <name>PID_0</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[12:12]</bitRange>
-              <description>Reset the buffer selector to buffer 0.</description>
-              <name>RESET</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[11:11]</bitRange>
-              <description>Reply with a stall (valid for both buffers).</description>
-              <name>STALL</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[10:10]</bitRange>
-              <description>Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
-              <name>AVAILABLE_0</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[9:0]</bitRange>
-              <description>The length of the data in buffer 0.</description>
-              <name>LENGTH_0</name>
-            </field>
-          </fields>
-          <name>EP15_OUT_BUFFER_CONTROL</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-      </registers>
-      <size>32</size>
-      <version>1</version>
-    </peripheral>
-    <peripheral>
-      <addressBlock>
-        <offset>0</offset>
-        <size>0x1000</size>
-        <usage>registers</usage>
-      </addressBlock>
-      <baseAddress>0x50110000</baseAddress>
-      <description>USB FS/LS controller device registers</description>
-      <interrupt>
-        <name>USBCTRL_IRQ</name>
-        <value>5</value>
-      </interrupt>
-      <name>USBCTRL_REGS</name>
-      <registers>
-        <register>
-          <addressOffset>0x0000</addressOffset>
-          <description>Device address and endpoint control</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[19:16]</bitRange>
-              <description>Device endpoint to send data to. Only valid for HOST mode.</description>
-              <name>ENDPOINT</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[6:0]</bitRange>
-              <description>In device mode, the address that the device should respond to. Set in response to a SET_ADDR setup packet from the host. In host mode set to the address of the device to communicate with.</description>
-              <name>ADDRESS</name>
-            </field>
-          </fields>
-          <name>ADDR_ENDP</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0004</addressOffset>
-          <description>Interrupt endpoint 1. Only valid for HOST mode.</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[26:26]</bitRange>
-              <description>Interrupt EP requires preamble (is a low speed device on a full speed hub)</description>
-              <name>INTEP_PREAMBLE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[25:25]</bitRange>
-              <description>Direction of the interrupt endpoint. In=0, Out=1</description>
-              <name>INTEP_DIR</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[19:16]</bitRange>
-              <description>Endpoint number of the interrupt endpoint</description>
-              <name>ENDPOINT</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[6:0]</bitRange>
-              <description>Device address</description>
-              <name>ADDRESS</name>
-            </field>
-          </fields>
-          <name>ADDR_ENDP1</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0008</addressOffset>
-          <description>Interrupt endpoint 2. Only valid for HOST mode.</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[26:26]</bitRange>
-              <description>Interrupt EP requires preamble (is a low speed device on a full speed hub)</description>
-              <name>INTEP_PREAMBLE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[25:25]</bitRange>
-              <description>Direction of the interrupt endpoint. In=0, Out=1</description>
-              <name>INTEP_DIR</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[19:16]</bitRange>
-              <description>Endpoint number of the interrupt endpoint</description>
-              <name>ENDPOINT</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[6:0]</bitRange>
-              <description>Device address</description>
-              <name>ADDRESS</name>
-            </field>
-          </fields>
-          <name>ADDR_ENDP2</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x000c</addressOffset>
-          <description>Interrupt endpoint 3. Only valid for HOST mode.</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[26:26]</bitRange>
-              <description>Interrupt EP requires preamble (is a low speed device on a full speed hub)</description>
-              <name>INTEP_PREAMBLE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[25:25]</bitRange>
-              <description>Direction of the interrupt endpoint. In=0, Out=1</description>
-              <name>INTEP_DIR</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[19:16]</bitRange>
-              <description>Endpoint number of the interrupt endpoint</description>
-              <name>ENDPOINT</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[6:0]</bitRange>
-              <description>Device address</description>
-              <name>ADDRESS</name>
-            </field>
-          </fields>
-          <name>ADDR_ENDP3</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0010</addressOffset>
-          <description>Interrupt endpoint 4. Only valid for HOST mode.</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[26:26]</bitRange>
-              <description>Interrupt EP requires preamble (is a low speed device on a full speed hub)</description>
-              <name>INTEP_PREAMBLE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[25:25]</bitRange>
-              <description>Direction of the interrupt endpoint. In=0, Out=1</description>
-              <name>INTEP_DIR</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[19:16]</bitRange>
-              <description>Endpoint number of the interrupt endpoint</description>
-              <name>ENDPOINT</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[6:0]</bitRange>
-              <description>Device address</description>
-              <name>ADDRESS</name>
-            </field>
-          </fields>
-          <name>ADDR_ENDP4</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0014</addressOffset>
-          <description>Interrupt endpoint 5. Only valid for HOST mode.</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[26:26]</bitRange>
-              <description>Interrupt EP requires preamble (is a low speed device on a full speed hub)</description>
-              <name>INTEP_PREAMBLE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[25:25]</bitRange>
-              <description>Direction of the interrupt endpoint. In=0, Out=1</description>
-              <name>INTEP_DIR</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[19:16]</bitRange>
-              <description>Endpoint number of the interrupt endpoint</description>
-              <name>ENDPOINT</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[6:0]</bitRange>
-              <description>Device address</description>
-              <name>ADDRESS</name>
-            </field>
-          </fields>
-          <name>ADDR_ENDP5</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0018</addressOffset>
-          <description>Interrupt endpoint 6. Only valid for HOST mode.</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[26:26]</bitRange>
-              <description>Interrupt EP requires preamble (is a low speed device on a full speed hub)</description>
-              <name>INTEP_PREAMBLE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[25:25]</bitRange>
-              <description>Direction of the interrupt endpoint. In=0, Out=1</description>
-              <name>INTEP_DIR</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[19:16]</bitRange>
-              <description>Endpoint number of the interrupt endpoint</description>
-              <name>ENDPOINT</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[6:0]</bitRange>
-              <description>Device address</description>
-              <name>ADDRESS</name>
-            </field>
-          </fields>
-          <name>ADDR_ENDP6</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x001c</addressOffset>
-          <description>Interrupt endpoint 7. Only valid for HOST mode.</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[26:26]</bitRange>
-              <description>Interrupt EP requires preamble (is a low speed device on a full speed hub)</description>
-              <name>INTEP_PREAMBLE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[25:25]</bitRange>
-              <description>Direction of the interrupt endpoint. In=0, Out=1</description>
-              <name>INTEP_DIR</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[19:16]</bitRange>
-              <description>Endpoint number of the interrupt endpoint</description>
-              <name>ENDPOINT</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[6:0]</bitRange>
-              <description>Device address</description>
-              <name>ADDRESS</name>
-            </field>
-          </fields>
-          <name>ADDR_ENDP7</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0020</addressOffset>
-          <description>Interrupt endpoint 8. Only valid for HOST mode.</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[26:26]</bitRange>
-              <description>Interrupt EP requires preamble (is a low speed device on a full speed hub)</description>
-              <name>INTEP_PREAMBLE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[25:25]</bitRange>
-              <description>Direction of the interrupt endpoint. In=0, Out=1</description>
-              <name>INTEP_DIR</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[19:16]</bitRange>
-              <description>Endpoint number of the interrupt endpoint</description>
-              <name>ENDPOINT</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[6:0]</bitRange>
-              <description>Device address</description>
-              <name>ADDRESS</name>
-            </field>
-          </fields>
-          <name>ADDR_ENDP8</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0024</addressOffset>
-          <description>Interrupt endpoint 9. Only valid for HOST mode.</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[26:26]</bitRange>
-              <description>Interrupt EP requires preamble (is a low speed device on a full speed hub)</description>
-              <name>INTEP_PREAMBLE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[25:25]</bitRange>
-              <description>Direction of the interrupt endpoint. In=0, Out=1</description>
-              <name>INTEP_DIR</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[19:16]</bitRange>
-              <description>Endpoint number of the interrupt endpoint</description>
-              <name>ENDPOINT</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[6:0]</bitRange>
-              <description>Device address</description>
-              <name>ADDRESS</name>
-            </field>
-          </fields>
-          <name>ADDR_ENDP9</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0028</addressOffset>
-          <description>Interrupt endpoint 10. Only valid for HOST mode.</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[26:26]</bitRange>
-              <description>Interrupt EP requires preamble (is a low speed device on a full speed hub)</description>
-              <name>INTEP_PREAMBLE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[25:25]</bitRange>
-              <description>Direction of the interrupt endpoint. In=0, Out=1</description>
-              <name>INTEP_DIR</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[19:16]</bitRange>
-              <description>Endpoint number of the interrupt endpoint</description>
-              <name>ENDPOINT</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[6:0]</bitRange>
-              <description>Device address</description>
-              <name>ADDRESS</name>
-            </field>
-          </fields>
-          <name>ADDR_ENDP10</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x002c</addressOffset>
-          <description>Interrupt endpoint 11. Only valid for HOST mode.</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[26:26]</bitRange>
-              <description>Interrupt EP requires preamble (is a low speed device on a full speed hub)</description>
-              <name>INTEP_PREAMBLE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[25:25]</bitRange>
-              <description>Direction of the interrupt endpoint. In=0, Out=1</description>
-              <name>INTEP_DIR</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[19:16]</bitRange>
-              <description>Endpoint number of the interrupt endpoint</description>
-              <name>ENDPOINT</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[6:0]</bitRange>
-              <description>Device address</description>
-              <name>ADDRESS</name>
-            </field>
-          </fields>
-          <name>ADDR_ENDP11</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0030</addressOffset>
-          <description>Interrupt endpoint 12. Only valid for HOST mode.</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[26:26]</bitRange>
-              <description>Interrupt EP requires preamble (is a low speed device on a full speed hub)</description>
-              <name>INTEP_PREAMBLE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[25:25]</bitRange>
-              <description>Direction of the interrupt endpoint. In=0, Out=1</description>
-              <name>INTEP_DIR</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[19:16]</bitRange>
-              <description>Endpoint number of the interrupt endpoint</description>
-              <name>ENDPOINT</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[6:0]</bitRange>
-              <description>Device address</description>
-              <name>ADDRESS</name>
-            </field>
-          </fields>
-          <name>ADDR_ENDP12</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0034</addressOffset>
-          <description>Interrupt endpoint 13. Only valid for HOST mode.</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[26:26]</bitRange>
-              <description>Interrupt EP requires preamble (is a low speed device on a full speed hub)</description>
-              <name>INTEP_PREAMBLE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[25:25]</bitRange>
-              <description>Direction of the interrupt endpoint. In=0, Out=1</description>
-              <name>INTEP_DIR</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[19:16]</bitRange>
-              <description>Endpoint number of the interrupt endpoint</description>
-              <name>ENDPOINT</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[6:0]</bitRange>
-              <description>Device address</description>
-              <name>ADDRESS</name>
-            </field>
-          </fields>
-          <name>ADDR_ENDP13</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0038</addressOffset>
-          <description>Interrupt endpoint 14. Only valid for HOST mode.</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[26:26]</bitRange>
-              <description>Interrupt EP requires preamble (is a low speed device on a full speed hub)</description>
-              <name>INTEP_PREAMBLE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[25:25]</bitRange>
-              <description>Direction of the interrupt endpoint. In=0, Out=1</description>
-              <name>INTEP_DIR</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[19:16]</bitRange>
-              <description>Endpoint number of the interrupt endpoint</description>
-              <name>ENDPOINT</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[6:0]</bitRange>
-              <description>Device address</description>
-              <name>ADDRESS</name>
-            </field>
-          </fields>
-          <name>ADDR_ENDP14</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x003c</addressOffset>
-          <description>Interrupt endpoint 15. Only valid for HOST mode.</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[26:26]</bitRange>
-              <description>Interrupt EP requires preamble (is a low speed device on a full speed hub)</description>
-              <name>INTEP_PREAMBLE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[25:25]</bitRange>
-              <description>Direction of the interrupt endpoint. In=0, Out=1</description>
-              <name>INTEP_DIR</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[19:16]</bitRange>
-              <description>Endpoint number of the interrupt endpoint</description>
-              <name>ENDPOINT</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[6:0]</bitRange>
-              <description>Device address</description>
-              <name>ADDRESS</name>
-            </field>
-          </fields>
-          <name>ADDR_ENDP15</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0040</addressOffset>
-          <description>Main control register</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[31:31]</bitRange>
-              <description>Reduced timings for simulation</description>
-              <name>SIM_TIMING</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[1:1]</bitRange>
-              <description>Device mode = 0, Host mode = 1</description>
-              <name>HOST_NDEVICE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[0:0]</bitRange>
-              <description>Enable controller</description>
-              <name>CONTROLLER_EN</name>
-            </field>
-          </fields>
-          <name>MAIN_CTRL</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0044</addressOffset>
-          <description>Set the SOF (Start of Frame) frame number in the host controller. The SOF packet is sent every 1ms and the host will increment the frame number by 1 each time.</description>
-          <fields>
-            <field>
-              <access>write-only</access>
-              <bitRange>[10:0]</bitRange>
-              <name>COUNT</name>
-            </field>
-          </fields>
-          <name>SOF_WR</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0048</addressOffset>
-          <description>Read the last SOF (Start of Frame) frame number seen. In device mode the last SOF received from the host. In host mode the last SOF sent by the host.</description>
-          <fields>
-            <field>
-              <access>read-only</access>
-              <bitRange>[10:0]</bitRange>
-              <name>COUNT</name>
-            </field>
-          </fields>
-          <name>SOF_RD</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x004c</addressOffset>
-          <description>SIE control register</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[31:31]</bitRange>
-              <description>Device: Set bit in EP_STATUS_STALL_NAK when EP0 sends a STALL</description>
-              <name>EP0_INT_STALL</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[30:30]</bitRange>
-              <description>Device: EP0 single buffered = 0, double buffered = 1</description>
-              <name>EP0_DOUBLE_BUF</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[29:29]</bitRange>
-              <description>Device: Set bit in BUFF_STATUS for every buffer completed on EP0</description>
-              <name>EP0_INT_1BUF</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[28:28]</bitRange>
-              <description>Device: Set bit in BUFF_STATUS for every 2 buffers completed on EP0</description>
-              <name>EP0_INT_2BUF</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[27:27]</bitRange>
-              <description>Device: Set bit in EP_STATUS_STALL_NAK when EP0 sends a NAK</description>
-              <name>EP0_INT_NAK</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[26:26]</bitRange>
-              <description>Direct bus drive enable</description>
-              <name>DIRECT_EN</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[25:25]</bitRange>
-              <description>Direct control of DP</description>
-              <name>DIRECT_DP</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[24:24]</bitRange>
-              <description>Direct control of DM</description>
-              <name>DIRECT_DM</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[18:18]</bitRange>
-              <description>Power down bus transceiver</description>
-              <name>TRANSCEIVER_PD</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[17:17]</bitRange>
-              <description>Device: Pull-up strength (0=1K2, 1=2k3)</description>
-              <name>RPU_OPT</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[16:16]</bitRange>
-              <description>Device: Enable pull up resistor</description>
-              <name>PULLUP_EN</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[15:15]</bitRange>
-              <description>Host: Enable pull down resistors</description>
-              <name>PULLDOWN_EN</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[13:13]</bitRange>
-              <description>Host: Reset bus</description>
-              <modifiedWriteValues>clear</modifiedWriteValues>
-              <name>RESET_BUS</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[12:12]</bitRange>
-              <description>Device: Remote wakeup. Device can initiate its own resume after suspend.</description>
-              <modifiedWriteValues>clear</modifiedWriteValues>
-              <name>RESUME</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[11:11]</bitRange>
-              <description>Host: Enable VBUS</description>
-              <name>VBUS_EN</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[10:10]</bitRange>
-              <description>Host: Enable keep alive packet (for low speed bus)</description>
-              <name>KEEP_ALIVE_EN</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[9:9]</bitRange>
-              <description>Host: Enable SOF generation (for full speed bus)</description>
-              <name>SOF_EN</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[8:8]</bitRange>
-              <description>Host: Delay packet(s) until after SOF</description>
-              <name>SOF_SYNC</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[6:6]</bitRange>
-              <description>Host: Preable enable for LS device on FS hub</description>
-              <name>PREAMBLE_EN</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[4:4]</bitRange>
-              <description>Host: Stop transaction</description>
-              <modifiedWriteValues>clear</modifiedWriteValues>
-              <name>STOP_TRANS</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[3:3]</bitRange>
-              <description>Host: Receive transaction (IN to host)</description>
-              <name>RECEIVE_DATA</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[2:2]</bitRange>
-              <description>Host: Send transaction (OUT from host)</description>
-              <name>SEND_DATA</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[1:1]</bitRange>
-              <description>Host: Send Setup packet</description>
-              <name>SEND_SETUP</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[0:0]</bitRange>
-              <description>Host: Start transaction</description>
-              <modifiedWriteValues>clear</modifiedWriteValues>
-              <name>START_TRANS</name>
-            </field>
-          </fields>
-          <name>SIE_CTRL</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0050</addressOffset>
-          <description>SIE status register</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[31:31]</bitRange>
-              <description>Data Sequence Error.\n\n
-                The device can raise a sequence error in the following conditions:\n\n
-                * A SETUP packet is received followed by a DATA1 packet (data phase should always be DATA0) * An OUT packet is received from the host but doesn't match the data pid in the buffer control register read from DPSRAM\n\n
-                The host can raise a data sequence error in the following conditions:\n\n
-                * An IN packet from the device has the wrong data PID</description>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>DATA_SEQ_ERROR</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[30:30]</bitRange>
-              <description>ACK received. Raised by both host and device.</description>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>ACK_REC</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[29:29]</bitRange>
-              <description>Host: STALL received</description>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>STALL_REC</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[28:28]</bitRange>
-              <description>Host: NAK received</description>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>NAK_REC</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[27:27]</bitRange>
-              <description>RX timeout is raised by both the host and device if an ACK is not received in the maximum time specified by the USB spec.</description>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>RX_TIMEOUT</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[26:26]</bitRange>
-              <description>RX overflow is raised by the Serial RX engine if the incoming data is too fast.</description>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>RX_OVERFLOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[25:25]</bitRange>
-              <description>Bit Stuff Error. Raised by the Serial RX engine.</description>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>BIT_STUFF_ERROR</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[24:24]</bitRange>
-              <description>CRC Error. Raised by the Serial RX engine.</description>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>CRC_ERROR</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[19:19]</bitRange>
-              <description>Device: bus reset received</description>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>BUS_RESET</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[18:18]</bitRange>
-              <description>Transaction complete.\n\n
-                Raised by device if:\n\n
-                * An IN or OUT packet is sent with the `LAST_BUFF` bit set in the buffer control register\n\n
-                Raised by host if:\n\n
-                * A setup packet is sent when no data in or data out transaction follows * An IN packet is received and the `LAST_BUFF` bit is set in the buffer control register * An IN packet is received with zero length * An OUT packet is sent and the `LAST_BUFF` bit is set</description>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>TRANS_COMPLETE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[17:17]</bitRange>
-              <description>Device: Setup packet received</description>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>SETUP_REC</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[16:16]</bitRange>
-              <description>Device: connected</description>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>CONNECTED</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[11:11]</bitRange>
-              <description>Host: Device has initiated a remote resume. Device: host has initiated a resume.</description>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>RESUME</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[10:10]</bitRange>
-              <description>VBUS over current detected</description>
-              <name>VBUS_OVER_CURR</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[9:8]</bitRange>
-              <description>Host: device speed. Disconnected = 00, LS = 01, FS = 10</description>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>SPEED</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[4:4]</bitRange>
-              <description>Bus in suspended state. Valid for device and host. Host and device will go into suspend if neither Keep Alive / SOF frames are enabled.</description>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>SUSPENDED</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[3:2]</bitRange>
-              <description>USB bus line state</description>
-              <name>LINE_STATE</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[0:0]</bitRange>
-              <description>Device: VBUS Detected</description>
-              <name>VBUS_DETECTED</name>
-            </field>
-          </fields>
-          <name>SIE_STATUS</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0054</addressOffset>
-          <description>interrupt endpoint control register</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[15:1]</bitRange>
-              <description>Host: Enable interrupt endpoint 1 -&gt; 15</description>
-              <name>INT_EP_ACTIVE</name>
-            </field>
-          </fields>
-          <name>INT_EP_CTRL</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0058</addressOffset>
-          <description>Buffer status register. A bit set here indicates that a buffer has completed on the endpoint (if the buffer interrupt is enabled). It is possible for 2 buffers to be completed, so clearing the buffer status bit may instantly re set it on the next clock cycle.</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[31:31]</bitRange>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>EP15_OUT</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[30:30]</bitRange>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>EP15_IN</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[29:29]</bitRange>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>EP14_OUT</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[28:28]</bitRange>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>EP14_IN</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[27:27]</bitRange>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>EP13_OUT</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[26:26]</bitRange>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>EP13_IN</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[25:25]</bitRange>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>EP12_OUT</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[24:24]</bitRange>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>EP12_IN</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[23:23]</bitRange>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>EP11_OUT</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[22:22]</bitRange>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>EP11_IN</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[21:21]</bitRange>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>EP10_OUT</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[20:20]</bitRange>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>EP10_IN</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[19:19]</bitRange>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>EP9_OUT</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[18:18]</bitRange>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>EP9_IN</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[17:17]</bitRange>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>EP8_OUT</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[16:16]</bitRange>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>EP8_IN</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[15:15]</bitRange>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>EP7_OUT</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[14:14]</bitRange>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>EP7_IN</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[13:13]</bitRange>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>EP6_OUT</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[12:12]</bitRange>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>EP6_IN</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[11:11]</bitRange>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>EP5_OUT</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[10:10]</bitRange>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>EP5_IN</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[9:9]</bitRange>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>EP4_OUT</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[8:8]</bitRange>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>EP4_IN</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[7:7]</bitRange>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>EP3_OUT</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[6:6]</bitRange>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>EP3_IN</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[5:5]</bitRange>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>EP2_OUT</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[4:4]</bitRange>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>EP2_IN</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[3:3]</bitRange>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>EP1_OUT</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[2:2]</bitRange>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>EP1_IN</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[1:1]</bitRange>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>EP0_OUT</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[0:0]</bitRange>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>EP0_IN</name>
-            </field>
-          </fields>
-          <name>BUFF_STATUS</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x005c</addressOffset>
-          <description>Which of the double buffers should be handled. Only valid if using an interrupt per buffer (i.e. not per 2 buffers). Not valid for host interrupt endpoint polling because they are only single buffered.</description>
-          <fields>
-            <field>
-              <access>read-only</access>
-              <bitRange>[31:31]</bitRange>
-              <name>EP15_OUT</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[30:30]</bitRange>
-              <name>EP15_IN</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[29:29]</bitRange>
-              <name>EP14_OUT</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[28:28]</bitRange>
-              <name>EP14_IN</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[27:27]</bitRange>
-              <name>EP13_OUT</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[26:26]</bitRange>
-              <name>EP13_IN</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[25:25]</bitRange>
-              <name>EP12_OUT</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[24:24]</bitRange>
-              <name>EP12_IN</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[23:23]</bitRange>
-              <name>EP11_OUT</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[22:22]</bitRange>
-              <name>EP11_IN</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[21:21]</bitRange>
-              <name>EP10_OUT</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[20:20]</bitRange>
-              <name>EP10_IN</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[19:19]</bitRange>
-              <name>EP9_OUT</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[18:18]</bitRange>
-              <name>EP9_IN</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[17:17]</bitRange>
-              <name>EP8_OUT</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[16:16]</bitRange>
-              <name>EP8_IN</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[15:15]</bitRange>
-              <name>EP7_OUT</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[14:14]</bitRange>
-              <name>EP7_IN</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[13:13]</bitRange>
-              <name>EP6_OUT</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[12:12]</bitRange>
-              <name>EP6_IN</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[11:11]</bitRange>
-              <name>EP5_OUT</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[10:10]</bitRange>
-              <name>EP5_IN</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[9:9]</bitRange>
-              <name>EP4_OUT</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[8:8]</bitRange>
-              <name>EP4_IN</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[7:7]</bitRange>
-              <name>EP3_OUT</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[6:6]</bitRange>
-              <name>EP3_IN</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[5:5]</bitRange>
-              <name>EP2_OUT</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[4:4]</bitRange>
-              <name>EP2_IN</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[3:3]</bitRange>
-              <name>EP1_OUT</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[2:2]</bitRange>
-              <name>EP1_IN</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[1:1]</bitRange>
-              <name>EP0_OUT</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[0:0]</bitRange>
-              <name>EP0_IN</name>
-            </field>
-          </fields>
-          <name>BUFF_CPU_SHOULD_HANDLE</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0060</addressOffset>
-          <description>Device only: Can be set to ignore the buffer control register for this endpoint in case you would like to revoke a buffer. A NAK will be sent for every access to the endpoint until this bit is cleared. A corresponding bit in `EP_ABORT_DONE` is set when it is safe to modify the buffer control register.</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[31:31]</bitRange>
-              <name>EP15_OUT</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[30:30]</bitRange>
-              <name>EP15_IN</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[29:29]</bitRange>
-              <name>EP14_OUT</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[28:28]</bitRange>
-              <name>EP14_IN</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[27:27]</bitRange>
-              <name>EP13_OUT</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[26:26]</bitRange>
-              <name>EP13_IN</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[25:25]</bitRange>
-              <name>EP12_OUT</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[24:24]</bitRange>
-              <name>EP12_IN</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[23:23]</bitRange>
-              <name>EP11_OUT</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[22:22]</bitRange>
-              <name>EP11_IN</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[21:21]</bitRange>
-              <name>EP10_OUT</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[20:20]</bitRange>
-              <name>EP10_IN</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[19:19]</bitRange>
-              <name>EP9_OUT</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[18:18]</bitRange>
-              <name>EP9_IN</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[17:17]</bitRange>
-              <name>EP8_OUT</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[16:16]</bitRange>
-              <name>EP8_IN</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[15:15]</bitRange>
-              <name>EP7_OUT</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[14:14]</bitRange>
-              <name>EP7_IN</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[13:13]</bitRange>
-              <name>EP6_OUT</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[12:12]</bitRange>
-              <name>EP6_IN</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[11:11]</bitRange>
-              <name>EP5_OUT</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[10:10]</bitRange>
-              <name>EP5_IN</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[9:9]</bitRange>
-              <name>EP4_OUT</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[8:8]</bitRange>
-              <name>EP4_IN</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[7:7]</bitRange>
-              <name>EP3_OUT</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[6:6]</bitRange>
-              <name>EP3_IN</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[5:5]</bitRange>
-              <name>EP2_OUT</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[4:4]</bitRange>
-              <name>EP2_IN</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[3:3]</bitRange>
-              <name>EP1_OUT</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[2:2]</bitRange>
-              <name>EP1_IN</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[1:1]</bitRange>
-              <name>EP0_OUT</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[0:0]</bitRange>
-              <name>EP0_IN</name>
-            </field>
-          </fields>
-          <name>EP_ABORT</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0064</addressOffset>
-          <description>Device only: Used in conjunction with `EP_ABORT`. Set once an endpoint is idle so the programmer knows it is safe to modify the buffer control register.</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[31:31]</bitRange>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>EP15_OUT</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[30:30]</bitRange>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>EP15_IN</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[29:29]</bitRange>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>EP14_OUT</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[28:28]</bitRange>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>EP14_IN</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[27:27]</bitRange>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>EP13_OUT</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[26:26]</bitRange>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>EP13_IN</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[25:25]</bitRange>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>EP12_OUT</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[24:24]</bitRange>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>EP12_IN</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[23:23]</bitRange>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>EP11_OUT</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[22:22]</bitRange>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>EP11_IN</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[21:21]</bitRange>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>EP10_OUT</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[20:20]</bitRange>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>EP10_IN</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[19:19]</bitRange>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>EP9_OUT</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[18:18]</bitRange>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>EP9_IN</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[17:17]</bitRange>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>EP8_OUT</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[16:16]</bitRange>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>EP8_IN</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[15:15]</bitRange>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>EP7_OUT</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[14:14]</bitRange>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>EP7_IN</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[13:13]</bitRange>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>EP6_OUT</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[12:12]</bitRange>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>EP6_IN</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[11:11]</bitRange>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>EP5_OUT</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[10:10]</bitRange>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>EP5_IN</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[9:9]</bitRange>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>EP4_OUT</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[8:8]</bitRange>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>EP4_IN</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[7:7]</bitRange>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>EP3_OUT</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[6:6]</bitRange>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>EP3_IN</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[5:5]</bitRange>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>EP2_OUT</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[4:4]</bitRange>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>EP2_IN</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[3:3]</bitRange>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>EP1_OUT</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[2:2]</bitRange>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>EP1_IN</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[1:1]</bitRange>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>EP0_OUT</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[0:0]</bitRange>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>EP0_IN</name>
-            </field>
-          </fields>
-          <name>EP_ABORT_DONE</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0068</addressOffset>
-          <description>Device: this bit must be set in conjunction with the `STALL` bit in the buffer control register to send a STALL on EP0. The device controller clears these bits when a SETUP packet is received because the USB spec requires that a STALL condition is cleared when a SETUP packet is received.</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[1:1]</bitRange>
-              <name>EP0_OUT</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[0:0]</bitRange>
-              <name>EP0_IN</name>
-            </field>
-          </fields>
-          <name>EP_STALL_ARM</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x006c</addressOffset>
-          <description>Used by the host controller. Sets the wait time in microseconds before trying again if the device replies with a NAK.</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[25:16]</bitRange>
-              <description>NAK polling interval for a full speed device</description>
-              <name>DELAY_FS</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[9:0]</bitRange>
-              <description>NAK polling interval for a low speed device</description>
-              <name>DELAY_LS</name>
-            </field>
-          </fields>
-          <name>NAK_POLL</name>
-          <resetValue>0x00100010</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0070</addressOffset>
-          <description>Device: bits are set when the `IRQ_ON_NAK` or `IRQ_ON_STALL` bits are set. For EP0 this comes from `SIE_CTRL`. For all other endpoints it comes from the endpoint control register.</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[31:31]</bitRange>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>EP15_OUT</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[30:30]</bitRange>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>EP15_IN</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[29:29]</bitRange>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>EP14_OUT</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[28:28]</bitRange>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>EP14_IN</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[27:27]</bitRange>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>EP13_OUT</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[26:26]</bitRange>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>EP13_IN</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[25:25]</bitRange>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>EP12_OUT</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[24:24]</bitRange>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>EP12_IN</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[23:23]</bitRange>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>EP11_OUT</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[22:22]</bitRange>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>EP11_IN</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[21:21]</bitRange>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>EP10_OUT</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[20:20]</bitRange>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>EP10_IN</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[19:19]</bitRange>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>EP9_OUT</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[18:18]</bitRange>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>EP9_IN</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[17:17]</bitRange>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>EP8_OUT</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[16:16]</bitRange>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>EP8_IN</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[15:15]</bitRange>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>EP7_OUT</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[14:14]</bitRange>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>EP7_IN</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[13:13]</bitRange>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>EP6_OUT</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[12:12]</bitRange>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>EP6_IN</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[11:11]</bitRange>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>EP5_OUT</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[10:10]</bitRange>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>EP5_IN</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[9:9]</bitRange>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>EP4_OUT</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[8:8]</bitRange>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>EP4_IN</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[7:7]</bitRange>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>EP3_OUT</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[6:6]</bitRange>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>EP3_IN</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[5:5]</bitRange>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>EP2_OUT</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[4:4]</bitRange>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>EP2_IN</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[3:3]</bitRange>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>EP1_OUT</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[2:2]</bitRange>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>EP1_IN</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[1:1]</bitRange>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>EP0_OUT</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[0:0]</bitRange>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>EP0_IN</name>
-            </field>
-          </fields>
-          <name>EP_STATUS_STALL_NAK</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0074</addressOffset>
-          <description>Where to connect the USB controller. Should be to_phy by default.</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[3:3]</bitRange>
-              <name>SOFTCON</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[2:2]</bitRange>
-              <name>TO_DIGITAL_PAD</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[1:1]</bitRange>
-              <name>TO_EXTPHY</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[0:0]</bitRange>
-              <name>TO_PHY</name>
-            </field>
-          </fields>
-          <name>USB_MUXING</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0078</addressOffset>
-          <description>Overrides for the power signals in the event that the VBUS signals are not hooked up to GPIO. Set the value of the override and then the override enable to switch over to the override value.</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[5:5]</bitRange>
-              <name>OVERCURR_DETECT_EN</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[4:4]</bitRange>
-              <name>OVERCURR_DETECT</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[3:3]</bitRange>
-              <name>VBUS_DETECT_OVERRIDE_EN</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[2:2]</bitRange>
-              <name>VBUS_DETECT</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[1:1]</bitRange>
-              <name>VBUS_EN_OVERRIDE_EN</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[0:0]</bitRange>
-              <name>VBUS_EN</name>
-            </field>
-          </fields>
-          <name>USB_PWR</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x007c</addressOffset>
-          <description>This register allows for direct control of the USB phy. Use in conjunction with usbphy_direct_override register to enable each override bit.</description>
-          <fields>
-            <field>
-              <access>read-only</access>
-              <bitRange>[22:22]</bitRange>
-              <description>DM over voltage</description>
-              <name>DM_OVV</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[21:21]</bitRange>
-              <description>DP over voltage</description>
-              <name>DP_OVV</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[20:20]</bitRange>
-              <description>DM overcurrent</description>
-              <name>DM_OVCN</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[19:19]</bitRange>
-              <description>DP overcurrent</description>
-              <name>DP_OVCN</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[18:18]</bitRange>
-              <description>DPM pin state</description>
-              <name>RX_DM</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[17:17]</bitRange>
-              <description>DPP pin state</description>
-              <name>RX_DP</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[16:16]</bitRange>
-              <description>Differential RX</description>
-              <name>RX_DD</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[15:15]</bitRange>
-              <description>TX_DIFFMODE=0: Single ended mode\n
-                TX_DIFFMODE=1: Differential drive mode (TX_DM, TX_DM_OE ignored)</description>
-              <name>TX_DIFFMODE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[14:14]</bitRange>
-              <description>TX_FSSLEW=0: Low speed slew rate\n
-                TX_FSSLEW=1: Full speed slew rate</description>
-              <name>TX_FSSLEW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[13:13]</bitRange>
-              <description>TX power down override (if override enable is set). 1 = powered down.</description>
-              <name>TX_PD</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[12:12]</bitRange>
-              <description>RX power down override (if override enable is set). 1 = powered down.</description>
-              <name>RX_PD</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[11:11]</bitRange>
-              <description>Output data. TX_DIFFMODE=1, Ignored\n
-                TX_DIFFMODE=0, Drives DPM only. TX_DM_OE=1 to enable drive. DPM=TX_DM</description>
-              <name>TX_DM</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[10:10]</bitRange>
-              <description>Output data. If TX_DIFFMODE=1, Drives DPP/DPM diff pair. TX_DP_OE=1 to enable drive. DPP=TX_DP, DPM=~TX_DP\n
-                If TX_DIFFMODE=0, Drives DPP only. TX_DP_OE=1 to enable drive. DPP=TX_DP</description>
-              <name>TX_DP</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[9:9]</bitRange>
-              <description>Output enable. If TX_DIFFMODE=1, Ignored.\n
-                If TX_DIFFMODE=0, OE for DPM only. 0 - DPM in Hi-Z state; 1 - DPM driving</description>
-              <name>TX_DM_OE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[8:8]</bitRange>
-              <description>Output enable. If TX_DIFFMODE=1, OE for DPP/DPM diff pair. 0 - DPP/DPM in Hi-Z state; 1 - DPP/DPM driving\n
-                If TX_DIFFMODE=0, OE for DPP only. 0 - DPP in Hi-Z state; 1 - DPP driving</description>
-              <name>TX_DP_OE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[6:6]</bitRange>
-              <description>DM pull down enable</description>
-              <name>DM_PULLDN_EN</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[5:5]</bitRange>
-              <description>DM pull up enable</description>
-              <name>DM_PULLUP_EN</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[4:4]</bitRange>
-              <description>Enable the second DM pull up resistor. 0 - Pull = Rpu2; 1 - Pull = Rpu1 + Rpu2</description>
-              <name>DM_PULLUP_HISEL</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[2:2]</bitRange>
-              <description>DP pull down enable</description>
-              <name>DP_PULLDN_EN</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[1:1]</bitRange>
-              <description>DP pull up enable</description>
-              <name>DP_PULLUP_EN</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[0:0]</bitRange>
-              <description>Enable the second DP pull up resistor. 0 - Pull = Rpu2; 1 - Pull = Rpu1 + Rpu2</description>
-              <name>DP_PULLUP_HISEL</name>
-            </field>
-          </fields>
-          <name>USBPHY_DIRECT</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0080</addressOffset>
-          <description>Override enable for each control in usbphy_direct</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[15:15]</bitRange>
-              <name>TX_DIFFMODE_OVERRIDE_EN</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[12:12]</bitRange>
-              <name>DM_PULLUP_OVERRIDE_EN</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[11:11]</bitRange>
-              <name>TX_FSSLEW_OVERRIDE_EN</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[10:10]</bitRange>
-              <name>TX_PD_OVERRIDE_EN</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[9:9]</bitRange>
-              <name>RX_PD_OVERRIDE_EN</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[8:8]</bitRange>
-              <name>TX_DM_OVERRIDE_EN</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[7:7]</bitRange>
-              <name>TX_DP_OVERRIDE_EN</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[6:6]</bitRange>
-              <name>TX_DM_OE_OVERRIDE_EN</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[5:5]</bitRange>
-              <name>TX_DP_OE_OVERRIDE_EN</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[4:4]</bitRange>
-              <name>DM_PULLDN_EN_OVERRIDE_EN</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[3:3]</bitRange>
-              <name>DP_PULLDN_EN_OVERRIDE_EN</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[2:2]</bitRange>
-              <name>DP_PULLUP_EN_OVERRIDE_EN</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[1:1]</bitRange>
-              <name>DM_PULLUP_HISEL_OVERRIDE_EN</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[0:0]</bitRange>
-              <name>DP_PULLUP_HISEL_OVERRIDE_EN</name>
-            </field>
-          </fields>
-          <name>USBPHY_DIRECT_OVERRIDE</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0084</addressOffset>
-          <description>Used to adjust trim values of USB phy pull down resistors.</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[12:8]</bitRange>
-              <description>Value to drive to USB PHY\n
-                DM pulldown resistor trim control\n
-                Experimental data suggests that the reset value will work, but this register allows adjustment if required</description>
-              <name>DM_PULLDN_TRIM</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[4:0]</bitRange>
-              <description>Value to drive to USB PHY\n
-                DP pulldown resistor trim control\n
-                Experimental data suggests that the reset value will work, but this register allows adjustment if required</description>
-              <name>DP_PULLDN_TRIM</name>
-            </field>
-          </fields>
-          <name>USBPHY_TRIM</name>
-          <resetValue>0x00001f1f</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x008c</addressOffset>
-          <description>Raw Interrupts</description>
-          <fields>
-            <field>
-              <access>read-only</access>
-              <bitRange>[19:19]</bitRange>
-              <description>Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by clearing all bits in EP_STATUS_STALL_NAK.</description>
-              <name>EP_STALL_NAK</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[18:18]</bitRange>
-              <description>Raised when any bit in ABORT_DONE is set. Clear by clearing all bits in ABORT_DONE.</description>
-              <name>ABORT_DONE</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[17:17]</bitRange>
-              <description>Set every time the device receives a SOF (Start of Frame) packet. Cleared by reading SOF_RD</description>
-              <name>DEV_SOF</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[16:16]</bitRange>
-              <description>Device. Source: SIE_STATUS.SETUP_REC</description>
-              <name>SETUP_REQ</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[15:15]</bitRange>
-              <description>Set when the device receives a resume from the host. Cleared by writing to SIE_STATUS.RESUME</description>
-              <name>DEV_RESUME_FROM_HOST</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[14:14]</bitRange>
-              <description>Set when the device suspend state changes. Cleared by writing to SIE_STATUS.SUSPENDED</description>
-              <name>DEV_SUSPEND</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[13:13]</bitRange>
-              <description>Set when the device connection state changes. Cleared by writing to SIE_STATUS.CONNECTED</description>
-              <name>DEV_CONN_DIS</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[12:12]</bitRange>
-              <description>Source: SIE_STATUS.BUS_RESET</description>
-              <name>BUS_RESET</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[11:11]</bitRange>
-              <description>Source: SIE_STATUS.VBUS_DETECTED</description>
-              <name>VBUS_DETECT</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[10:10]</bitRange>
-              <description>Source: SIE_STATUS.STALL_REC</description>
-              <name>STALL</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[9:9]</bitRange>
-              <description>Source: SIE_STATUS.CRC_ERROR</description>
-              <name>ERROR_CRC</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[8:8]</bitRange>
-              <description>Source: SIE_STATUS.BIT_STUFF_ERROR</description>
-              <name>ERROR_BIT_STUFF</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[7:7]</bitRange>
-              <description>Source: SIE_STATUS.RX_OVERFLOW</description>
-              <name>ERROR_RX_OVERFLOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[6:6]</bitRange>
-              <description>Source: SIE_STATUS.RX_TIMEOUT</description>
-              <name>ERROR_RX_TIMEOUT</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[5:5]</bitRange>
-              <description>Source: SIE_STATUS.DATA_SEQ_ERROR</description>
-              <name>ERROR_DATA_SEQ</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[4:4]</bitRange>
-              <description>Raised when any bit in BUFF_STATUS is set. Clear by clearing all bits in BUFF_STATUS.</description>
-              <name>BUFF_STATUS</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[3:3]</bitRange>
-              <description>Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by writing to this bit.</description>
-              <name>TRANS_COMPLETE</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[2:2]</bitRange>
-              <description>Host: raised every time the host sends a SOF (Start of Frame). Cleared by reading SOF_RD</description>
-              <name>HOST_SOF</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[1:1]</bitRange>
-              <description>Host: raised when a device wakes up the host. Cleared by writing to SIE_STATUS.RESUME</description>
-              <name>HOST_RESUME</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[0:0]</bitRange>
-              <description>Host: raised when a device is connected or disconnected (i.e. when SIE_STATUS.SPEED changes). Cleared by writing to SIE_STATUS.SPEED</description>
-              <name>HOST_CONN_DIS</name>
-            </field>
-          </fields>
-          <name>INTR</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0090</addressOffset>
-          <description>Interrupt Enable</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[19:19]</bitRange>
-              <description>Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by clearing all bits in EP_STATUS_STALL_NAK.</description>
-              <name>EP_STALL_NAK</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[18:18]</bitRange>
-              <description>Raised when any bit in ABORT_DONE is set. Clear by clearing all bits in ABORT_DONE.</description>
-              <name>ABORT_DONE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[17:17]</bitRange>
-              <description>Set every time the device receives a SOF (Start of Frame) packet. Cleared by reading SOF_RD</description>
-              <name>DEV_SOF</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[16:16]</bitRange>
-              <description>Device. Source: SIE_STATUS.SETUP_REC</description>
-              <name>SETUP_REQ</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[15:15]</bitRange>
-              <description>Set when the device receives a resume from the host. Cleared by writing to SIE_STATUS.RESUME</description>
-              <name>DEV_RESUME_FROM_HOST</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[14:14]</bitRange>
-              <description>Set when the device suspend state changes. Cleared by writing to SIE_STATUS.SUSPENDED</description>
-              <name>DEV_SUSPEND</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[13:13]</bitRange>
-              <description>Set when the device connection state changes. Cleared by writing to SIE_STATUS.CONNECTED</description>
-              <name>DEV_CONN_DIS</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[12:12]</bitRange>
-              <description>Source: SIE_STATUS.BUS_RESET</description>
-              <name>BUS_RESET</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[11:11]</bitRange>
-              <description>Source: SIE_STATUS.VBUS_DETECTED</description>
-              <name>VBUS_DETECT</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[10:10]</bitRange>
-              <description>Source: SIE_STATUS.STALL_REC</description>
-              <name>STALL</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[9:9]</bitRange>
-              <description>Source: SIE_STATUS.CRC_ERROR</description>
-              <name>ERROR_CRC</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[8:8]</bitRange>
-              <description>Source: SIE_STATUS.BIT_STUFF_ERROR</description>
-              <name>ERROR_BIT_STUFF</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[7:7]</bitRange>
-              <description>Source: SIE_STATUS.RX_OVERFLOW</description>
-              <name>ERROR_RX_OVERFLOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[6:6]</bitRange>
-              <description>Source: SIE_STATUS.RX_TIMEOUT</description>
-              <name>ERROR_RX_TIMEOUT</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[5:5]</bitRange>
-              <description>Source: SIE_STATUS.DATA_SEQ_ERROR</description>
-              <name>ERROR_DATA_SEQ</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[4:4]</bitRange>
-              <description>Raised when any bit in BUFF_STATUS is set. Clear by clearing all bits in BUFF_STATUS.</description>
-              <name>BUFF_STATUS</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[3:3]</bitRange>
-              <description>Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by writing to this bit.</description>
-              <name>TRANS_COMPLETE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[2:2]</bitRange>
-              <description>Host: raised every time the host sends a SOF (Start of Frame). Cleared by reading SOF_RD</description>
-              <name>HOST_SOF</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[1:1]</bitRange>
-              <description>Host: raised when a device wakes up the host. Cleared by writing to SIE_STATUS.RESUME</description>
-              <name>HOST_RESUME</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[0:0]</bitRange>
-              <description>Host: raised when a device is connected or disconnected (i.e. when SIE_STATUS.SPEED changes). Cleared by writing to SIE_STATUS.SPEED</description>
-              <name>HOST_CONN_DIS</name>
-            </field>
-          </fields>
-          <name>INTE</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0094</addressOffset>
-          <description>Interrupt Force</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[19:19]</bitRange>
-              <description>Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by clearing all bits in EP_STATUS_STALL_NAK.</description>
-              <name>EP_STALL_NAK</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[18:18]</bitRange>
-              <description>Raised when any bit in ABORT_DONE is set. Clear by clearing all bits in ABORT_DONE.</description>
-              <name>ABORT_DONE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[17:17]</bitRange>
-              <description>Set every time the device receives a SOF (Start of Frame) packet. Cleared by reading SOF_RD</description>
-              <name>DEV_SOF</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[16:16]</bitRange>
-              <description>Device. Source: SIE_STATUS.SETUP_REC</description>
-              <name>SETUP_REQ</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[15:15]</bitRange>
-              <description>Set when the device receives a resume from the host. Cleared by writing to SIE_STATUS.RESUME</description>
-              <name>DEV_RESUME_FROM_HOST</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[14:14]</bitRange>
-              <description>Set when the device suspend state changes. Cleared by writing to SIE_STATUS.SUSPENDED</description>
-              <name>DEV_SUSPEND</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[13:13]</bitRange>
-              <description>Set when the device connection state changes. Cleared by writing to SIE_STATUS.CONNECTED</description>
-              <name>DEV_CONN_DIS</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[12:12]</bitRange>
-              <description>Source: SIE_STATUS.BUS_RESET</description>
-              <name>BUS_RESET</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[11:11]</bitRange>
-              <description>Source: SIE_STATUS.VBUS_DETECTED</description>
-              <name>VBUS_DETECT</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[10:10]</bitRange>
-              <description>Source: SIE_STATUS.STALL_REC</description>
-              <name>STALL</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[9:9]</bitRange>
-              <description>Source: SIE_STATUS.CRC_ERROR</description>
-              <name>ERROR_CRC</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[8:8]</bitRange>
-              <description>Source: SIE_STATUS.BIT_STUFF_ERROR</description>
-              <name>ERROR_BIT_STUFF</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[7:7]</bitRange>
-              <description>Source: SIE_STATUS.RX_OVERFLOW</description>
-              <name>ERROR_RX_OVERFLOW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[6:6]</bitRange>
-              <description>Source: SIE_STATUS.RX_TIMEOUT</description>
-              <name>ERROR_RX_TIMEOUT</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[5:5]</bitRange>
-              <description>Source: SIE_STATUS.DATA_SEQ_ERROR</description>
-              <name>ERROR_DATA_SEQ</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[4:4]</bitRange>
-              <description>Raised when any bit in BUFF_STATUS is set. Clear by clearing all bits in BUFF_STATUS.</description>
-              <name>BUFF_STATUS</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[3:3]</bitRange>
-              <description>Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by writing to this bit.</description>
-              <name>TRANS_COMPLETE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[2:2]</bitRange>
-              <description>Host: raised every time the host sends a SOF (Start of Frame). Cleared by reading SOF_RD</description>
-              <name>HOST_SOF</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[1:1]</bitRange>
-              <description>Host: raised when a device wakes up the host. Cleared by writing to SIE_STATUS.RESUME</description>
-              <name>HOST_RESUME</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[0:0]</bitRange>
-              <description>Host: raised when a device is connected or disconnected (i.e. when SIE_STATUS.SPEED changes). Cleared by writing to SIE_STATUS.SPEED</description>
-              <name>HOST_CONN_DIS</name>
-            </field>
-          </fields>
-          <name>INTF</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0098</addressOffset>
-          <description>Interrupt status after masking &amp; forcing</description>
-          <fields>
-            <field>
-              <access>read-only</access>
-              <bitRange>[19:19]</bitRange>
-              <description>Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by clearing all bits in EP_STATUS_STALL_NAK.</description>
-              <name>EP_STALL_NAK</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[18:18]</bitRange>
-              <description>Raised when any bit in ABORT_DONE is set. Clear by clearing all bits in ABORT_DONE.</description>
-              <name>ABORT_DONE</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[17:17]</bitRange>
-              <description>Set every time the device receives a SOF (Start of Frame) packet. Cleared by reading SOF_RD</description>
-              <name>DEV_SOF</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[16:16]</bitRange>
-              <description>Device. Source: SIE_STATUS.SETUP_REC</description>
-              <name>SETUP_REQ</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[15:15]</bitRange>
-              <description>Set when the device receives a resume from the host. Cleared by writing to SIE_STATUS.RESUME</description>
-              <name>DEV_RESUME_FROM_HOST</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[14:14]</bitRange>
-              <description>Set when the device suspend state changes. Cleared by writing to SIE_STATUS.SUSPENDED</description>
-              <name>DEV_SUSPEND</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[13:13]</bitRange>
-              <description>Set when the device connection state changes. Cleared by writing to SIE_STATUS.CONNECTED</description>
-              <name>DEV_CONN_DIS</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[12:12]</bitRange>
-              <description>Source: SIE_STATUS.BUS_RESET</description>
-              <name>BUS_RESET</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[11:11]</bitRange>
-              <description>Source: SIE_STATUS.VBUS_DETECTED</description>
-              <name>VBUS_DETECT</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[10:10]</bitRange>
-              <description>Source: SIE_STATUS.STALL_REC</description>
-              <name>STALL</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[9:9]</bitRange>
-              <description>Source: SIE_STATUS.CRC_ERROR</description>
-              <name>ERROR_CRC</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[8:8]</bitRange>
-              <description>Source: SIE_STATUS.BIT_STUFF_ERROR</description>
-              <name>ERROR_BIT_STUFF</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[7:7]</bitRange>
-              <description>Source: SIE_STATUS.RX_OVERFLOW</description>
-              <name>ERROR_RX_OVERFLOW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[6:6]</bitRange>
-              <description>Source: SIE_STATUS.RX_TIMEOUT</description>
-              <name>ERROR_RX_TIMEOUT</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[5:5]</bitRange>
-              <description>Source: SIE_STATUS.DATA_SEQ_ERROR</description>
-              <name>ERROR_DATA_SEQ</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[4:4]</bitRange>
-              <description>Raised when any bit in BUFF_STATUS is set. Clear by clearing all bits in BUFF_STATUS.</description>
-              <name>BUFF_STATUS</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[3:3]</bitRange>
-              <description>Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by writing to this bit.</description>
-              <name>TRANS_COMPLETE</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[2:2]</bitRange>
-              <description>Host: raised every time the host sends a SOF (Start of Frame). Cleared by reading SOF_RD</description>
-              <name>HOST_SOF</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[1:1]</bitRange>
-              <description>Host: raised when a device wakes up the host. Cleared by writing to SIE_STATUS.RESUME</description>
-              <name>HOST_RESUME</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[0:0]</bitRange>
-              <description>Host: raised when a device is connected or disconnected (i.e. when SIE_STATUS.SPEED changes). Cleared by writing to SIE_STATUS.SPEED</description>
-              <name>HOST_CONN_DIS</name>
-            </field>
-          </fields>
-          <name>INTS</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-      </registers>
-      <size>32</size>
-      <version>1</version>
-    </peripheral>
-    <peripheral>
-      <addressBlock>
-        <offset>0</offset>
-        <size>0x1000</size>
-        <usage>registers</usage>
-      </addressBlock>
-      <baseAddress>0x50200000</baseAddress>
-      <description>Programmable IO block</description>
-      <interrupt>
-        <name>PIO0_IRQ_0</name>
-        <value>7</value>
-      </interrupt>
-      <interrupt>
-        <name>PIO0_IRQ_1</name>
-        <value>8</value>
-      </interrupt>
-      <name>PIO0</name>
-      <registers>
-        <register>
-          <addressOffset>0x0000</addressOffset>
-          <description>PIO control register</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[11:8]</bitRange>
-              <description>Restart a state machine's clock divider from an initial phase of 0. Clock dividers are free-running, so once started, their output (including fractional jitter) is completely determined by the integer/fractional divisor configured in SMx_CLKDIV. This means that, if multiple clock dividers with the same divisor are restarted simultaneously, by writing multiple 1 bits to this field, the execution clocks of those state machines will run in precise lockstep.\n\n
-                Note that setting/clearing SM_ENABLE does not stop the clock divider from running, so once multiple state machines' clocks are synchronised, it is safe to disable/reenable a state machine, whilst keeping the clock dividers in sync.\n\n
-                Note also that CLKDIV_RESTART can be written to whilst the state machine is running, and this is useful to resynchronise clock dividers after the divisors (SMx_CLKDIV) have been changed on-the-fly.</description>
-              <modifiedWriteValues>clear</modifiedWriteValues>
-              <name>CLKDIV_RESTART</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[7:4]</bitRange>
-              <description>Write 1 to instantly clear internal SM state which may be otherwise difficult to access and will affect future execution.\n\n
-                Specifically, the following are cleared: input and output shift counters; the contents of the input shift register; the delay counter; the waiting-on-IRQ state; any stalled instruction written to SMx_INSTR or run by OUT/MOV EXEC; any pin write left asserted due to OUT_STICKY.\n\n
-                The program counter, the contents of the output shift register and the X/Y scratch registers are not affected.</description>
-              <modifiedWriteValues>clear</modifiedWriteValues>
-              <name>SM_RESTART</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[3:0]</bitRange>
-              <description>Enable/disable each of the four state machines by writing 1/0 to each of these four bits. When disabled, a state machine will cease executing instructions, except those written directly to SMx_INSTR by the system. Multiple bits can be set/cleared at once to run/halt multiple state machines simultaneously.</description>
-              <name>SM_ENABLE</name>
-            </field>
-          </fields>
-          <name>CTRL</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0004</addressOffset>
-          <description>FIFO status register</description>
-          <fields>
-            <field>
-              <access>read-only</access>
-              <bitRange>[27:24]</bitRange>
-              <description>State machine TX FIFO is empty</description>
-              <name>TXEMPTY</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[19:16]</bitRange>
-              <description>State machine TX FIFO is full</description>
-              <name>TXFULL</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[11:8]</bitRange>
-              <description>State machine RX FIFO is empty</description>
-              <name>RXEMPTY</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[3:0]</bitRange>
-              <description>State machine RX FIFO is full</description>
-              <name>RXFULL</name>
-            </field>
-          </fields>
-          <name>FSTAT</name>
-          <resetValue>0x0f000f00</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0008</addressOffset>
-          <description>FIFO debug register</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[27:24]</bitRange>
-              <description>State machine has stalled on empty TX FIFO during a blocking PULL, or an OUT with autopull enabled. Write 1 to clear.</description>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>TXSTALL</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[19:16]</bitRange>
-              <description>TX FIFO overflow (i.e. write-on-full by the system) has occurred. Write 1 to clear. Note that write-on-full does not alter the state or contents of the FIFO in any way, but the data that the system attempted to write is dropped, so if this flag is set, your software has quite likely dropped some data on the floor.</description>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>TXOVER</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[11:8]</bitRange>
-              <description>RX FIFO underflow (i.e. read-on-empty by the system) has occurred. Write 1 to clear. Note that read-on-empty does not perturb the state of the FIFO in any way, but the data returned by reading from an empty FIFO is undefined, so this flag generally only becomes set due to some kind of software error.</description>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>RXUNDER</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[3:0]</bitRange>
-              <description>State machine has stalled on full RX FIFO during a blocking PUSH, or an IN with autopush enabled. This flag is also set when a nonblocking PUSH to a full FIFO took place, in which case the state machine has dropped data. Write 1 to clear.</description>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>RXSTALL</name>
-            </field>
-          </fields>
-          <name>FDEBUG</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x000c</addressOffset>
-          <description>FIFO levels</description>
-          <fields>
-            <field>
-              <access>read-only</access>
-              <bitRange>[31:28]</bitRange>
-              <name>RX3</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[27:24]</bitRange>
-              <name>TX3</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[23:20]</bitRange>
-              <name>RX2</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[19:16]</bitRange>
-              <name>TX2</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[15:12]</bitRange>
-              <name>RX1</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[11:8]</bitRange>
-              <name>TX1</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[7:4]</bitRange>
-              <name>RX0</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[3:0]</bitRange>
-              <name>TX0</name>
-            </field>
-          </fields>
-          <name>FLEVEL</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>write-only</access>
-          <addressOffset>0x0010</addressOffset>
-          <description>Direct write access to the TX FIFO for this state machine. Each write pushes one word to the FIFO. Attempting to write to a full FIFO has no effect on the FIFO state or contents, and sets the sticky FDEBUG_TXOVER error flag for this FIFO.</description>
-          <name>TXF0</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>write-only</access>
-          <addressOffset>0x0014</addressOffset>
-          <description>Direct write access to the TX FIFO for this state machine. Each write pushes one word to the FIFO. Attempting to write to a full FIFO has no effect on the FIFO state or contents, and sets the sticky FDEBUG_TXOVER error flag for this FIFO.</description>
-          <name>TXF1</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>write-only</access>
-          <addressOffset>0x0018</addressOffset>
-          <description>Direct write access to the TX FIFO for this state machine. Each write pushes one word to the FIFO. Attempting to write to a full FIFO has no effect on the FIFO state or contents, and sets the sticky FDEBUG_TXOVER error flag for this FIFO.</description>
-          <name>TXF2</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>write-only</access>
-          <addressOffset>0x001c</addressOffset>
-          <description>Direct write access to the TX FIFO for this state machine. Each write pushes one word to the FIFO. Attempting to write to a full FIFO has no effect on the FIFO state or contents, and sets the sticky FDEBUG_TXOVER error flag for this FIFO.</description>
-          <name>TXF3</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-only</access>
-          <addressOffset>0x0020</addressOffset>
-          <description>Direct read access to the RX FIFO for this state machine. Each read pops one word from the FIFO. Attempting to read from an empty FIFO has no effect on the FIFO state, and sets the sticky FDEBUG_RXUNDER error flag for this FIFO. The data returned to the system on a read from an empty FIFO is undefined.</description>
-          <name>RXF0</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-only</access>
-          <addressOffset>0x0024</addressOffset>
-          <description>Direct read access to the RX FIFO for this state machine. Each read pops one word from the FIFO. Attempting to read from an empty FIFO has no effect on the FIFO state, and sets the sticky FDEBUG_RXUNDER error flag for this FIFO. The data returned to the system on a read from an empty FIFO is undefined.</description>
-          <name>RXF1</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-only</access>
-          <addressOffset>0x0028</addressOffset>
-          <description>Direct read access to the RX FIFO for this state machine. Each read pops one word from the FIFO. Attempting to read from an empty FIFO has no effect on the FIFO state, and sets the sticky FDEBUG_RXUNDER error flag for this FIFO. The data returned to the system on a read from an empty FIFO is undefined.</description>
-          <name>RXF2</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-only</access>
-          <addressOffset>0x002c</addressOffset>
-          <description>Direct read access to the RX FIFO for this state machine. Each read pops one word from the FIFO. Attempting to read from an empty FIFO has no effect on the FIFO state, and sets the sticky FDEBUG_RXUNDER error flag for this FIFO. The data returned to the system on a read from an empty FIFO is undefined.</description>
-          <name>RXF3</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0030</addressOffset>
-          <description>State machine IRQ flags register. Write 1 to clear. There are 8 state machine IRQ flags, which can be set, cleared, and waited on by the state machines. There's no fixed association between flags and state machines -- any state machine can use any flag.\n\n
-            Any of the 8 flags can be used for timing synchronisation between state machines, using IRQ and WAIT instructions. The lower four of these flags are also routed out to system-level interrupt requests, alongside FIFO status interrupts -- see e.g. IRQ0_INTE.</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[7:0]</bitRange>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>IRQ</name>
-            </field>
-          </fields>
-          <name>IRQ</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0034</addressOffset>
-          <description>Writing a 1 to each of these bits will forcibly assert the corresponding IRQ. Note this is different to the INTF register: writing here affects PIO internal state. INTF just asserts the processor-facing IRQ signal for testing ISRs, and is not visible to the state machines.</description>
-          <fields>
-            <field>
-              <access>write-only</access>
-              <bitRange>[7:0]</bitRange>
-              <name>IRQ_FORCE</name>
-            </field>
-          </fields>
-          <name>IRQ_FORCE</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x0038</addressOffset>
-          <description>There is a 2-flipflop synchronizer on each GPIO input, which protects PIO logic from metastabilities. This increases input delay, and for fast synchronous IO (e.g. SPI) these synchronizers may need to be bypassed. Each bit in this register corresponds to one GPIO.\n
-            0 -&gt; input is synchronized (default)\n
-            1 -&gt; synchronizer is bypassed\n
-            If in doubt, leave this register as all zeroes.</description>
-          <name>INPUT_SYNC_BYPASS</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-only</access>
-          <addressOffset>0x003c</addressOffset>
-          <description>Read to sample the pad output values PIO is currently driving to the GPIOs. On RP2040 there are 30 GPIOs, so the two most significant bits are hardwired to 0.</description>
-          <name>DBG_PADOUT</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-only</access>
-          <addressOffset>0x0040</addressOffset>
-          <description>Read to sample the pad output enables (direction) PIO is currently driving to the GPIOs. On RP2040 there are 30 GPIOs, so the two most significant bits are hardwired to 0.</description>
-          <name>DBG_PADOE</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0044</addressOffset>
-          <description>The PIO hardware has some free parameters that may vary between chip products.\n
-            These should be provided in the chip datasheet, but are also exposed here.</description>
-          <fields>
-            <field>
-              <access>read-only</access>
-              <bitRange>[21:16]</bitRange>
-              <description>The size of the instruction memory, measured in units of one instruction</description>
-              <name>IMEM_SIZE</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[11:8]</bitRange>
-              <description>The number of state machines this PIO instance is equipped with.</description>
-              <name>SM_COUNT</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[5:0]</bitRange>
-              <description>The depth of the state machine TX/RX FIFOs, measured in words.\n
-                Joining fifos via SHIFTCTRL_FJOIN gives one FIFO with double\n
-                this depth.</description>
-              <name>FIFO_DEPTH</name>
-            </field>
-          </fields>
-          <name>DBG_CFGINFO</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0048</addressOffset>
-          <description>Write-only access to instruction memory location 0</description>
-          <fields>
-            <field>
-              <access>write-only</access>
-              <bitRange>[15:0]</bitRange>
-              <name>INSTR_MEM0</name>
-            </field>
-          </fields>
-          <name>INSTR_MEM0</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x004c</addressOffset>
-          <description>Write-only access to instruction memory location 1</description>
-          <fields>
-            <field>
-              <access>write-only</access>
-              <bitRange>[15:0]</bitRange>
-              <name>INSTR_MEM1</name>
-            </field>
-          </fields>
-          <name>INSTR_MEM1</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0050</addressOffset>
-          <description>Write-only access to instruction memory location 2</description>
-          <fields>
-            <field>
-              <access>write-only</access>
-              <bitRange>[15:0]</bitRange>
-              <name>INSTR_MEM2</name>
-            </field>
-          </fields>
-          <name>INSTR_MEM2</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0054</addressOffset>
-          <description>Write-only access to instruction memory location 3</description>
-          <fields>
-            <field>
-              <access>write-only</access>
-              <bitRange>[15:0]</bitRange>
-              <name>INSTR_MEM3</name>
-            </field>
-          </fields>
-          <name>INSTR_MEM3</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0058</addressOffset>
-          <description>Write-only access to instruction memory location 4</description>
-          <fields>
-            <field>
-              <access>write-only</access>
-              <bitRange>[15:0]</bitRange>
-              <name>INSTR_MEM4</name>
-            </field>
-          </fields>
-          <name>INSTR_MEM4</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x005c</addressOffset>
-          <description>Write-only access to instruction memory location 5</description>
-          <fields>
-            <field>
-              <access>write-only</access>
-              <bitRange>[15:0]</bitRange>
-              <name>INSTR_MEM5</name>
-            </field>
-          </fields>
-          <name>INSTR_MEM5</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0060</addressOffset>
-          <description>Write-only access to instruction memory location 6</description>
-          <fields>
-            <field>
-              <access>write-only</access>
-              <bitRange>[15:0]</bitRange>
-              <name>INSTR_MEM6</name>
-            </field>
-          </fields>
-          <name>INSTR_MEM6</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0064</addressOffset>
-          <description>Write-only access to instruction memory location 7</description>
-          <fields>
-            <field>
-              <access>write-only</access>
-              <bitRange>[15:0]</bitRange>
-              <name>INSTR_MEM7</name>
-            </field>
-          </fields>
-          <name>INSTR_MEM7</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0068</addressOffset>
-          <description>Write-only access to instruction memory location 8</description>
-          <fields>
-            <field>
-              <access>write-only</access>
-              <bitRange>[15:0]</bitRange>
-              <name>INSTR_MEM8</name>
-            </field>
-          </fields>
-          <name>INSTR_MEM8</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x006c</addressOffset>
-          <description>Write-only access to instruction memory location 9</description>
-          <fields>
-            <field>
-              <access>write-only</access>
-              <bitRange>[15:0]</bitRange>
-              <name>INSTR_MEM9</name>
-            </field>
-          </fields>
-          <name>INSTR_MEM9</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0070</addressOffset>
-          <description>Write-only access to instruction memory location 10</description>
-          <fields>
-            <field>
-              <access>write-only</access>
-              <bitRange>[15:0]</bitRange>
-              <name>INSTR_MEM10</name>
-            </field>
-          </fields>
-          <name>INSTR_MEM10</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0074</addressOffset>
-          <description>Write-only access to instruction memory location 11</description>
-          <fields>
-            <field>
-              <access>write-only</access>
-              <bitRange>[15:0]</bitRange>
-              <name>INSTR_MEM11</name>
-            </field>
-          </fields>
-          <name>INSTR_MEM11</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0078</addressOffset>
-          <description>Write-only access to instruction memory location 12</description>
-          <fields>
-            <field>
-              <access>write-only</access>
-              <bitRange>[15:0]</bitRange>
-              <name>INSTR_MEM12</name>
-            </field>
-          </fields>
-          <name>INSTR_MEM12</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x007c</addressOffset>
-          <description>Write-only access to instruction memory location 13</description>
-          <fields>
-            <field>
-              <access>write-only</access>
-              <bitRange>[15:0]</bitRange>
-              <name>INSTR_MEM13</name>
-            </field>
-          </fields>
-          <name>INSTR_MEM13</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0080</addressOffset>
-          <description>Write-only access to instruction memory location 14</description>
-          <fields>
-            <field>
-              <access>write-only</access>
-              <bitRange>[15:0]</bitRange>
-              <name>INSTR_MEM14</name>
-            </field>
-          </fields>
-          <name>INSTR_MEM14</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0084</addressOffset>
-          <description>Write-only access to instruction memory location 15</description>
-          <fields>
-            <field>
-              <access>write-only</access>
-              <bitRange>[15:0]</bitRange>
-              <name>INSTR_MEM15</name>
-            </field>
-          </fields>
-          <name>INSTR_MEM15</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0088</addressOffset>
-          <description>Write-only access to instruction memory location 16</description>
-          <fields>
-            <field>
-              <access>write-only</access>
-              <bitRange>[15:0]</bitRange>
-              <name>INSTR_MEM16</name>
-            </field>
-          </fields>
-          <name>INSTR_MEM16</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x008c</addressOffset>
-          <description>Write-only access to instruction memory location 17</description>
-          <fields>
-            <field>
-              <access>write-only</access>
-              <bitRange>[15:0]</bitRange>
-              <name>INSTR_MEM17</name>
-            </field>
-          </fields>
-          <name>INSTR_MEM17</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0090</addressOffset>
-          <description>Write-only access to instruction memory location 18</description>
-          <fields>
-            <field>
-              <access>write-only</access>
-              <bitRange>[15:0]</bitRange>
-              <name>INSTR_MEM18</name>
-            </field>
-          </fields>
-          <name>INSTR_MEM18</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0094</addressOffset>
-          <description>Write-only access to instruction memory location 19</description>
-          <fields>
-            <field>
-              <access>write-only</access>
-              <bitRange>[15:0]</bitRange>
-              <name>INSTR_MEM19</name>
-            </field>
-          </fields>
-          <name>INSTR_MEM19</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0098</addressOffset>
-          <description>Write-only access to instruction memory location 20</description>
-          <fields>
-            <field>
-              <access>write-only</access>
-              <bitRange>[15:0]</bitRange>
-              <name>INSTR_MEM20</name>
-            </field>
-          </fields>
-          <name>INSTR_MEM20</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x009c</addressOffset>
-          <description>Write-only access to instruction memory location 21</description>
-          <fields>
-            <field>
-              <access>write-only</access>
-              <bitRange>[15:0]</bitRange>
-              <name>INSTR_MEM21</name>
-            </field>
-          </fields>
-          <name>INSTR_MEM21</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x00a0</addressOffset>
-          <description>Write-only access to instruction memory location 22</description>
-          <fields>
-            <field>
-              <access>write-only</access>
-              <bitRange>[15:0]</bitRange>
-              <name>INSTR_MEM22</name>
-            </field>
-          </fields>
-          <name>INSTR_MEM22</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x00a4</addressOffset>
-          <description>Write-only access to instruction memory location 23</description>
-          <fields>
-            <field>
-              <access>write-only</access>
-              <bitRange>[15:0]</bitRange>
-              <name>INSTR_MEM23</name>
-            </field>
-          </fields>
-          <name>INSTR_MEM23</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x00a8</addressOffset>
-          <description>Write-only access to instruction memory location 24</description>
-          <fields>
-            <field>
-              <access>write-only</access>
-              <bitRange>[15:0]</bitRange>
-              <name>INSTR_MEM24</name>
-            </field>
-          </fields>
-          <name>INSTR_MEM24</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x00ac</addressOffset>
-          <description>Write-only access to instruction memory location 25</description>
-          <fields>
-            <field>
-              <access>write-only</access>
-              <bitRange>[15:0]</bitRange>
-              <name>INSTR_MEM25</name>
-            </field>
-          </fields>
-          <name>INSTR_MEM25</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x00b0</addressOffset>
-          <description>Write-only access to instruction memory location 26</description>
-          <fields>
-            <field>
-              <access>write-only</access>
-              <bitRange>[15:0]</bitRange>
-              <name>INSTR_MEM26</name>
-            </field>
-          </fields>
-          <name>INSTR_MEM26</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x00b4</addressOffset>
-          <description>Write-only access to instruction memory location 27</description>
-          <fields>
-            <field>
-              <access>write-only</access>
-              <bitRange>[15:0]</bitRange>
-              <name>INSTR_MEM27</name>
-            </field>
-          </fields>
-          <name>INSTR_MEM27</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x00b8</addressOffset>
-          <description>Write-only access to instruction memory location 28</description>
-          <fields>
-            <field>
-              <access>write-only</access>
-              <bitRange>[15:0]</bitRange>
-              <name>INSTR_MEM28</name>
-            </field>
-          </fields>
-          <name>INSTR_MEM28</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x00bc</addressOffset>
-          <description>Write-only access to instruction memory location 29</description>
-          <fields>
-            <field>
-              <access>write-only</access>
-              <bitRange>[15:0]</bitRange>
-              <name>INSTR_MEM29</name>
-            </field>
-          </fields>
-          <name>INSTR_MEM29</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x00c0</addressOffset>
-          <description>Write-only access to instruction memory location 30</description>
-          <fields>
-            <field>
-              <access>write-only</access>
-              <bitRange>[15:0]</bitRange>
-              <name>INSTR_MEM30</name>
-            </field>
-          </fields>
-          <name>INSTR_MEM30</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x00c4</addressOffset>
-          <description>Write-only access to instruction memory location 31</description>
-          <fields>
-            <field>
-              <access>write-only</access>
-              <bitRange>[15:0]</bitRange>
-              <name>INSTR_MEM31</name>
-            </field>
-          </fields>
-          <name>INSTR_MEM31</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x00c8</addressOffset>
-          <description>Clock divisor register for state machine 0\n
-            Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256)</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[31:16]</bitRange>
-              <description>Effective frequency is sysclk/(int + frac/256).\n
-                Value of 0 is interpreted as 65536. If INT is 0, FRAC must also be 0.</description>
-              <name>INT</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[15:8]</bitRange>
-              <description>Fractional part of clock divisor</description>
-              <name>FRAC</name>
-            </field>
-          </fields>
-          <name>SM0_CLKDIV</name>
-          <resetValue>0x00010000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x00cc</addressOffset>
-          <description>Execution/behavioural settings for state machine 0</description>
-          <fields>
-            <field>
-              <access>read-only</access>
-              <bitRange>[31:31]</bitRange>
-              <description>If 1, an instruction written to SMx_INSTR is stalled, and latched by the state machine. Will clear to 0 once this instruction completes.</description>
-              <name>EXEC_STALLED</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[30:30]</bitRange>
-              <description>If 1, the MSB of the Delay/Side-set instruction field is used as side-set enable, rather than a side-set data bit. This allows instructions to perform side-set optionally, rather than on every instruction, but the maximum possible side-set width is reduced from 5 to 4. Note that the value of PINCTRL_SIDESET_COUNT is inclusive of this enable bit.</description>
-              <name>SIDE_EN</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[29:29]</bitRange>
-              <description>If 1, side-set data is asserted to pin directions, instead of pin values</description>
-              <name>SIDE_PINDIR</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[28:24]</bitRange>
-              <description>The GPIO number to use as condition for JMP PIN. Unaffected by input mapping.</description>
-              <name>JMP_PIN</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[23:19]</bitRange>
-              <description>Which data bit to use for inline OUT enable</description>
-              <name>OUT_EN_SEL</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[18:18]</bitRange>
-              <description>If 1, use a bit of OUT data as an auxiliary write enable\n
-                When used in conjunction with OUT_STICKY, writes with an enable of 0 will\n
-                deassert the latest pin write. This can create useful masking/override behaviour\n
-                due to the priority ordering of state machine pin writes (SM0 &lt; SM1 &lt; ...)</description>
-              <name>INLINE_OUT_EN</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[17:17]</bitRange>
-              <description>Continuously assert the most recent OUT/SET to the pins</description>
-              <name>OUT_STICKY</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[16:12]</bitRange>
-              <description>After reaching this address, execution is wrapped to wrap_bottom.\n
-                If the instruction is a jump, and the jump condition is true, the jump takes priority.</description>
-              <name>WRAP_TOP</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[11:7]</bitRange>
-              <description>After reaching wrap_top, execution is wrapped to this address.</description>
-              <name>WRAP_BOTTOM</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[4:4]</bitRange>
-              <description>Comparison used for the MOV x, STATUS instruction.</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>All-ones if TX FIFO level &lt; N, otherwise all-zeroes</description>
-                  <name>TXLEVEL</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>All-ones if RX FIFO level &lt; N, otherwise all-zeroes</description>
-                  <name>RXLEVEL</name>
-                  <value>1</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>STATUS_SEL</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[3:0]</bitRange>
-              <description>Comparison level for the MOV x, STATUS instruction</description>
-              <name>STATUS_N</name>
-            </field>
-          </fields>
-          <name>SM0_EXECCTRL</name>
-          <resetValue>0x0001f000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x00d0</addressOffset>
-          <description>Control behaviour of the input/output shift registers for state machine 0</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[31:31]</bitRange>
-              <description>When 1, RX FIFO steals the TX FIFO's storage, and becomes twice as deep.\n
-                TX FIFO is disabled as a result (always reads as both full and empty).\n
-                FIFOs are flushed when this bit is changed.</description>
-              <name>FJOIN_RX</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[30:30]</bitRange>
-              <description>When 1, TX FIFO steals the RX FIFO's storage, and becomes twice as deep.\n
-                RX FIFO is disabled as a result (always reads as both full and empty).\n
-                FIFOs are flushed when this bit is changed.</description>
-              <name>FJOIN_TX</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[29:25]</bitRange>
-              <description>Number of bits shifted out of OSR before autopull, or conditional pull (PULL IFEMPTY), will take place.\n
-                Write 0 for value of 32.</description>
-              <name>PULL_THRESH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[24:20]</bitRange>
-              <description>Number of bits shifted into ISR before autopush, or conditional push (PUSH IFFULL), will take place.\n
-                Write 0 for value of 32.</description>
-              <name>PUSH_THRESH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[19:19]</bitRange>
-              <description>1 = shift out of output shift register to right. 0 = to left.</description>
-              <name>OUT_SHIFTDIR</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[18:18]</bitRange>
-              <description>1 = shift input shift register to right (data enters from left). 0 = to left.</description>
-              <name>IN_SHIFTDIR</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[17:17]</bitRange>
-              <description>Pull automatically when the output shift register is emptied, i.e. on or following an OUT instruction which causes the output shift counter to reach or exceed PULL_THRESH.</description>
-              <name>AUTOPULL</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[16:16]</bitRange>
-              <description>Push automatically when the input shift register is filled, i.e. on an IN instruction which causes the input shift counter to reach or exceed PUSH_THRESH.</description>
-              <name>AUTOPUSH</name>
-            </field>
-          </fields>
-          <name>SM0_SHIFTCTRL</name>
-          <resetValue>0x000c0000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x00d4</addressOffset>
-          <description>Current instruction address of state machine 0</description>
-          <fields>
-            <field>
-              <access>read-only</access>
-              <bitRange>[4:0]</bitRange>
-              <name>SM0_ADDR</name>
-            </field>
-          </fields>
-          <name>SM0_ADDR</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x00d8</addressOffset>
-          <description>Read to see the instruction currently addressed by state machine 0's program counter\n
-            Write to execute an instruction immediately (including jumps) and then resume execution.</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[15:0]</bitRange>
-              <name>SM0_INSTR</name>
-            </field>
-          </fields>
-          <name>SM0_INSTR</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x00dc</addressOffset>
-          <description>State machine pin control</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[31:29]</bitRange>
-              <description>The number of MSBs of the Delay/Side-set instruction field which are used for side-set. Inclusive of the enable bit, if present. Minimum of 0 (all delay bits, no side-set) and maximum of 5 (all side-set, no delay).</description>
-              <name>SIDESET_COUNT</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[28:26]</bitRange>
-              <description>The number of pins asserted by a SET. In the range 0 to 5 inclusive.</description>
-              <name>SET_COUNT</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[25:20]</bitRange>
-              <description>The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV PINS instruction. In the range 0 to 32 inclusive.</description>
-              <name>OUT_COUNT</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[19:15]</bitRange>
-              <description>The pin which is mapped to the least-significant bit of a state machine's IN data bus. Higher-numbered pins are mapped to consecutively more-significant data bits, with a modulo of 32 applied to pin number.</description>
-              <name>IN_BASE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[14:10]</bitRange>
-              <description>The lowest-numbered pin that will be affected by a side-set operation. The MSBs of an instruction's side-set/delay field (up to 5, determined by SIDESET_COUNT) are used for side-set data, with the remaining LSBs used for delay. The least-significant bit of the side-set portion is the bit written to this pin, with more-significant bits written to higher-numbered pins.</description>
-              <name>SIDESET_BASE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[9:5]</bitRange>
-              <description>The lowest-numbered pin that will be affected by a SET PINS or SET PINDIRS instruction. The data written to this pin is the least-significant bit of the SET data.</description>
-              <name>SET_BASE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[4:0]</bitRange>
-              <description>The lowest-numbered pin that will be affected by an OUT PINS, OUT PINDIRS or MOV PINS instruction. The data written to this pin will always be the least-significant bit of the OUT or MOV data.</description>
-              <name>OUT_BASE</name>
-            </field>
-          </fields>
-          <name>SM0_PINCTRL</name>
-          <resetValue>0x14000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x00e0</addressOffset>
-          <description>Clock divisor register for state machine 1\n
-            Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256)</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[31:16]</bitRange>
-              <description>Effective frequency is sysclk/(int + frac/256).\n
-                Value of 0 is interpreted as 65536. If INT is 0, FRAC must also be 0.</description>
-              <name>INT</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[15:8]</bitRange>
-              <description>Fractional part of clock divisor</description>
-              <name>FRAC</name>
-            </field>
-          </fields>
-          <name>SM1_CLKDIV</name>
-          <resetValue>0x00010000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x00e4</addressOffset>
-          <description>Execution/behavioural settings for state machine 1</description>
-          <fields>
-            <field>
-              <access>read-only</access>
-              <bitRange>[31:31]</bitRange>
-              <description>If 1, an instruction written to SMx_INSTR is stalled, and latched by the state machine. Will clear to 0 once this instruction completes.</description>
-              <name>EXEC_STALLED</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[30:30]</bitRange>
-              <description>If 1, the MSB of the Delay/Side-set instruction field is used as side-set enable, rather than a side-set data bit. This allows instructions to perform side-set optionally, rather than on every instruction, but the maximum possible side-set width is reduced from 5 to 4. Note that the value of PINCTRL_SIDESET_COUNT is inclusive of this enable bit.</description>
-              <name>SIDE_EN</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[29:29]</bitRange>
-              <description>If 1, side-set data is asserted to pin directions, instead of pin values</description>
-              <name>SIDE_PINDIR</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[28:24]</bitRange>
-              <description>The GPIO number to use as condition for JMP PIN. Unaffected by input mapping.</description>
-              <name>JMP_PIN</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[23:19]</bitRange>
-              <description>Which data bit to use for inline OUT enable</description>
-              <name>OUT_EN_SEL</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[18:18]</bitRange>
-              <description>If 1, use a bit of OUT data as an auxiliary write enable\n
-                When used in conjunction with OUT_STICKY, writes with an enable of 0 will\n
-                deassert the latest pin write. This can create useful masking/override behaviour\n
-                due to the priority ordering of state machine pin writes (SM0 &lt; SM1 &lt; ...)</description>
-              <name>INLINE_OUT_EN</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[17:17]</bitRange>
-              <description>Continuously assert the most recent OUT/SET to the pins</description>
-              <name>OUT_STICKY</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[16:12]</bitRange>
-              <description>After reaching this address, execution is wrapped to wrap_bottom.\n
-                If the instruction is a jump, and the jump condition is true, the jump takes priority.</description>
-              <name>WRAP_TOP</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[11:7]</bitRange>
-              <description>After reaching wrap_top, execution is wrapped to this address.</description>
-              <name>WRAP_BOTTOM</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[4:4]</bitRange>
-              <description>Comparison used for the MOV x, STATUS instruction.</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>All-ones if TX FIFO level &lt; N, otherwise all-zeroes</description>
-                  <name>TXLEVEL</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>All-ones if RX FIFO level &lt; N, otherwise all-zeroes</description>
-                  <name>RXLEVEL</name>
-                  <value>1</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>STATUS_SEL</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[3:0]</bitRange>
-              <description>Comparison level for the MOV x, STATUS instruction</description>
-              <name>STATUS_N</name>
-            </field>
-          </fields>
-          <name>SM1_EXECCTRL</name>
-          <resetValue>0x0001f000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x00e8</addressOffset>
-          <description>Control behaviour of the input/output shift registers for state machine 1</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[31:31]</bitRange>
-              <description>When 1, RX FIFO steals the TX FIFO's storage, and becomes twice as deep.\n
-                TX FIFO is disabled as a result (always reads as both full and empty).\n
-                FIFOs are flushed when this bit is changed.</description>
-              <name>FJOIN_RX</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[30:30]</bitRange>
-              <description>When 1, TX FIFO steals the RX FIFO's storage, and becomes twice as deep.\n
-                RX FIFO is disabled as a result (always reads as both full and empty).\n
-                FIFOs are flushed when this bit is changed.</description>
-              <name>FJOIN_TX</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[29:25]</bitRange>
-              <description>Number of bits shifted out of OSR before autopull, or conditional pull (PULL IFEMPTY), will take place.\n
-                Write 0 for value of 32.</description>
-              <name>PULL_THRESH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[24:20]</bitRange>
-              <description>Number of bits shifted into ISR before autopush, or conditional push (PUSH IFFULL), will take place.\n
-                Write 0 for value of 32.</description>
-              <name>PUSH_THRESH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[19:19]</bitRange>
-              <description>1 = shift out of output shift register to right. 0 = to left.</description>
-              <name>OUT_SHIFTDIR</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[18:18]</bitRange>
-              <description>1 = shift input shift register to right (data enters from left). 0 = to left.</description>
-              <name>IN_SHIFTDIR</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[17:17]</bitRange>
-              <description>Pull automatically when the output shift register is emptied, i.e. on or following an OUT instruction which causes the output shift counter to reach or exceed PULL_THRESH.</description>
-              <name>AUTOPULL</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[16:16]</bitRange>
-              <description>Push automatically when the input shift register is filled, i.e. on an IN instruction which causes the input shift counter to reach or exceed PUSH_THRESH.</description>
-              <name>AUTOPUSH</name>
-            </field>
-          </fields>
-          <name>SM1_SHIFTCTRL</name>
-          <resetValue>0x000c0000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x00ec</addressOffset>
-          <description>Current instruction address of state machine 1</description>
-          <fields>
-            <field>
-              <access>read-only</access>
-              <bitRange>[4:0]</bitRange>
-              <name>SM1_ADDR</name>
-            </field>
-          </fields>
-          <name>SM1_ADDR</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x00f0</addressOffset>
-          <description>Read to see the instruction currently addressed by state machine 1's program counter\n
-            Write to execute an instruction immediately (including jumps) and then resume execution.</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[15:0]</bitRange>
-              <name>SM1_INSTR</name>
-            </field>
-          </fields>
-          <name>SM1_INSTR</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x00f4</addressOffset>
-          <description>State machine pin control</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[31:29]</bitRange>
-              <description>The number of MSBs of the Delay/Side-set instruction field which are used for side-set. Inclusive of the enable bit, if present. Minimum of 0 (all delay bits, no side-set) and maximum of 5 (all side-set, no delay).</description>
-              <name>SIDESET_COUNT</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[28:26]</bitRange>
-              <description>The number of pins asserted by a SET. In the range 0 to 5 inclusive.</description>
-              <name>SET_COUNT</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[25:20]</bitRange>
-              <description>The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV PINS instruction. In the range 0 to 32 inclusive.</description>
-              <name>OUT_COUNT</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[19:15]</bitRange>
-              <description>The pin which is mapped to the least-significant bit of a state machine's IN data bus. Higher-numbered pins are mapped to consecutively more-significant data bits, with a modulo of 32 applied to pin number.</description>
-              <name>IN_BASE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[14:10]</bitRange>
-              <description>The lowest-numbered pin that will be affected by a side-set operation. The MSBs of an instruction's side-set/delay field (up to 5, determined by SIDESET_COUNT) are used for side-set data, with the remaining LSBs used for delay. The least-significant bit of the side-set portion is the bit written to this pin, with more-significant bits written to higher-numbered pins.</description>
-              <name>SIDESET_BASE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[9:5]</bitRange>
-              <description>The lowest-numbered pin that will be affected by a SET PINS or SET PINDIRS instruction. The data written to this pin is the least-significant bit of the SET data.</description>
-              <name>SET_BASE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[4:0]</bitRange>
-              <description>The lowest-numbered pin that will be affected by an OUT PINS, OUT PINDIRS or MOV PINS instruction. The data written to this pin will always be the least-significant bit of the OUT or MOV data.</description>
-              <name>OUT_BASE</name>
-            </field>
-          </fields>
-          <name>SM1_PINCTRL</name>
-          <resetValue>0x14000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x00f8</addressOffset>
-          <description>Clock divisor register for state machine 2\n
-            Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256)</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[31:16]</bitRange>
-              <description>Effective frequency is sysclk/(int + frac/256).\n
-                Value of 0 is interpreted as 65536. If INT is 0, FRAC must also be 0.</description>
-              <name>INT</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[15:8]</bitRange>
-              <description>Fractional part of clock divisor</description>
-              <name>FRAC</name>
-            </field>
-          </fields>
-          <name>SM2_CLKDIV</name>
-          <resetValue>0x00010000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x00fc</addressOffset>
-          <description>Execution/behavioural settings for state machine 2</description>
-          <fields>
-            <field>
-              <access>read-only</access>
-              <bitRange>[31:31]</bitRange>
-              <description>If 1, an instruction written to SMx_INSTR is stalled, and latched by the state machine. Will clear to 0 once this instruction completes.</description>
-              <name>EXEC_STALLED</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[30:30]</bitRange>
-              <description>If 1, the MSB of the Delay/Side-set instruction field is used as side-set enable, rather than a side-set data bit. This allows instructions to perform side-set optionally, rather than on every instruction, but the maximum possible side-set width is reduced from 5 to 4. Note that the value of PINCTRL_SIDESET_COUNT is inclusive of this enable bit.</description>
-              <name>SIDE_EN</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[29:29]</bitRange>
-              <description>If 1, side-set data is asserted to pin directions, instead of pin values</description>
-              <name>SIDE_PINDIR</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[28:24]</bitRange>
-              <description>The GPIO number to use as condition for JMP PIN. Unaffected by input mapping.</description>
-              <name>JMP_PIN</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[23:19]</bitRange>
-              <description>Which data bit to use for inline OUT enable</description>
-              <name>OUT_EN_SEL</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[18:18]</bitRange>
-              <description>If 1, use a bit of OUT data as an auxiliary write enable\n
-                When used in conjunction with OUT_STICKY, writes with an enable of 0 will\n
-                deassert the latest pin write. This can create useful masking/override behaviour\n
-                due to the priority ordering of state machine pin writes (SM0 &lt; SM1 &lt; ...)</description>
-              <name>INLINE_OUT_EN</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[17:17]</bitRange>
-              <description>Continuously assert the most recent OUT/SET to the pins</description>
-              <name>OUT_STICKY</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[16:12]</bitRange>
-              <description>After reaching this address, execution is wrapped to wrap_bottom.\n
-                If the instruction is a jump, and the jump condition is true, the jump takes priority.</description>
-              <name>WRAP_TOP</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[11:7]</bitRange>
-              <description>After reaching wrap_top, execution is wrapped to this address.</description>
-              <name>WRAP_BOTTOM</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[4:4]</bitRange>
-              <description>Comparison used for the MOV x, STATUS instruction.</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>All-ones if TX FIFO level &lt; N, otherwise all-zeroes</description>
-                  <name>TXLEVEL</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>All-ones if RX FIFO level &lt; N, otherwise all-zeroes</description>
-                  <name>RXLEVEL</name>
-                  <value>1</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>STATUS_SEL</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[3:0]</bitRange>
-              <description>Comparison level for the MOV x, STATUS instruction</description>
-              <name>STATUS_N</name>
-            </field>
-          </fields>
-          <name>SM2_EXECCTRL</name>
-          <resetValue>0x0001f000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0100</addressOffset>
-          <description>Control behaviour of the input/output shift registers for state machine 2</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[31:31]</bitRange>
-              <description>When 1, RX FIFO steals the TX FIFO's storage, and becomes twice as deep.\n
-                TX FIFO is disabled as a result (always reads as both full and empty).\n
-                FIFOs are flushed when this bit is changed.</description>
-              <name>FJOIN_RX</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[30:30]</bitRange>
-              <description>When 1, TX FIFO steals the RX FIFO's storage, and becomes twice as deep.\n
-                RX FIFO is disabled as a result (always reads as both full and empty).\n
-                FIFOs are flushed when this bit is changed.</description>
-              <name>FJOIN_TX</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[29:25]</bitRange>
-              <description>Number of bits shifted out of OSR before autopull, or conditional pull (PULL IFEMPTY), will take place.\n
-                Write 0 for value of 32.</description>
-              <name>PULL_THRESH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[24:20]</bitRange>
-              <description>Number of bits shifted into ISR before autopush, or conditional push (PUSH IFFULL), will take place.\n
-                Write 0 for value of 32.</description>
-              <name>PUSH_THRESH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[19:19]</bitRange>
-              <description>1 = shift out of output shift register to right. 0 = to left.</description>
-              <name>OUT_SHIFTDIR</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[18:18]</bitRange>
-              <description>1 = shift input shift register to right (data enters from left). 0 = to left.</description>
-              <name>IN_SHIFTDIR</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[17:17]</bitRange>
-              <description>Pull automatically when the output shift register is emptied, i.e. on or following an OUT instruction which causes the output shift counter to reach or exceed PULL_THRESH.</description>
-              <name>AUTOPULL</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[16:16]</bitRange>
-              <description>Push automatically when the input shift register is filled, i.e. on an IN instruction which causes the input shift counter to reach or exceed PUSH_THRESH.</description>
-              <name>AUTOPUSH</name>
-            </field>
-          </fields>
-          <name>SM2_SHIFTCTRL</name>
-          <resetValue>0x000c0000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0104</addressOffset>
-          <description>Current instruction address of state machine 2</description>
-          <fields>
-            <field>
-              <access>read-only</access>
-              <bitRange>[4:0]</bitRange>
-              <name>SM2_ADDR</name>
-            </field>
-          </fields>
-          <name>SM2_ADDR</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0108</addressOffset>
-          <description>Read to see the instruction currently addressed by state machine 2's program counter\n
-            Write to execute an instruction immediately (including jumps) and then resume execution.</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[15:0]</bitRange>
-              <name>SM2_INSTR</name>
-            </field>
-          </fields>
-          <name>SM2_INSTR</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x010c</addressOffset>
-          <description>State machine pin control</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[31:29]</bitRange>
-              <description>The number of MSBs of the Delay/Side-set instruction field which are used for side-set. Inclusive of the enable bit, if present. Minimum of 0 (all delay bits, no side-set) and maximum of 5 (all side-set, no delay).</description>
-              <name>SIDESET_COUNT</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[28:26]</bitRange>
-              <description>The number of pins asserted by a SET. In the range 0 to 5 inclusive.</description>
-              <name>SET_COUNT</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[25:20]</bitRange>
-              <description>The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV PINS instruction. In the range 0 to 32 inclusive.</description>
-              <name>OUT_COUNT</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[19:15]</bitRange>
-              <description>The pin which is mapped to the least-significant bit of a state machine's IN data bus. Higher-numbered pins are mapped to consecutively more-significant data bits, with a modulo of 32 applied to pin number.</description>
-              <name>IN_BASE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[14:10]</bitRange>
-              <description>The lowest-numbered pin that will be affected by a side-set operation. The MSBs of an instruction's side-set/delay field (up to 5, determined by SIDESET_COUNT) are used for side-set data, with the remaining LSBs used for delay. The least-significant bit of the side-set portion is the bit written to this pin, with more-significant bits written to higher-numbered pins.</description>
-              <name>SIDESET_BASE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[9:5]</bitRange>
-              <description>The lowest-numbered pin that will be affected by a SET PINS or SET PINDIRS instruction. The data written to this pin is the least-significant bit of the SET data.</description>
-              <name>SET_BASE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[4:0]</bitRange>
-              <description>The lowest-numbered pin that will be affected by an OUT PINS, OUT PINDIRS or MOV PINS instruction. The data written to this pin will always be the least-significant bit of the OUT or MOV data.</description>
-              <name>OUT_BASE</name>
-            </field>
-          </fields>
-          <name>SM2_PINCTRL</name>
-          <resetValue>0x14000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0110</addressOffset>
-          <description>Clock divisor register for state machine 3\n
-            Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256)</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[31:16]</bitRange>
-              <description>Effective frequency is sysclk/(int + frac/256).\n
-                Value of 0 is interpreted as 65536. If INT is 0, FRAC must also be 0.</description>
-              <name>INT</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[15:8]</bitRange>
-              <description>Fractional part of clock divisor</description>
-              <name>FRAC</name>
-            </field>
-          </fields>
-          <name>SM3_CLKDIV</name>
-          <resetValue>0x00010000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0114</addressOffset>
-          <description>Execution/behavioural settings for state machine 3</description>
-          <fields>
-            <field>
-              <access>read-only</access>
-              <bitRange>[31:31]</bitRange>
-              <description>If 1, an instruction written to SMx_INSTR is stalled, and latched by the state machine. Will clear to 0 once this instruction completes.</description>
-              <name>EXEC_STALLED</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[30:30]</bitRange>
-              <description>If 1, the MSB of the Delay/Side-set instruction field is used as side-set enable, rather than a side-set data bit. This allows instructions to perform side-set optionally, rather than on every instruction, but the maximum possible side-set width is reduced from 5 to 4. Note that the value of PINCTRL_SIDESET_COUNT is inclusive of this enable bit.</description>
-              <name>SIDE_EN</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[29:29]</bitRange>
-              <description>If 1, side-set data is asserted to pin directions, instead of pin values</description>
-              <name>SIDE_PINDIR</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[28:24]</bitRange>
-              <description>The GPIO number to use as condition for JMP PIN. Unaffected by input mapping.</description>
-              <name>JMP_PIN</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[23:19]</bitRange>
-              <description>Which data bit to use for inline OUT enable</description>
-              <name>OUT_EN_SEL</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[18:18]</bitRange>
-              <description>If 1, use a bit of OUT data as an auxiliary write enable\n
-                When used in conjunction with OUT_STICKY, writes with an enable of 0 will\n
-                deassert the latest pin write. This can create useful masking/override behaviour\n
-                due to the priority ordering of state machine pin writes (SM0 &lt; SM1 &lt; ...)</description>
-              <name>INLINE_OUT_EN</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[17:17]</bitRange>
-              <description>Continuously assert the most recent OUT/SET to the pins</description>
-              <name>OUT_STICKY</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[16:12]</bitRange>
-              <description>After reaching this address, execution is wrapped to wrap_bottom.\n
-                If the instruction is a jump, and the jump condition is true, the jump takes priority.</description>
-              <name>WRAP_TOP</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[11:7]</bitRange>
-              <description>After reaching wrap_top, execution is wrapped to this address.</description>
-              <name>WRAP_BOTTOM</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[4:4]</bitRange>
-              <description>Comparison used for the MOV x, STATUS instruction.</description>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <description>All-ones if TX FIFO level &lt; N, otherwise all-zeroes</description>
-                  <name>TXLEVEL</name>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <description>All-ones if RX FIFO level &lt; N, otherwise all-zeroes</description>
-                  <name>RXLEVEL</name>
-                  <value>1</value>
-                </enumeratedValue>
-              </enumeratedValues>
-              <name>STATUS_SEL</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[3:0]</bitRange>
-              <description>Comparison level for the MOV x, STATUS instruction</description>
-              <name>STATUS_N</name>
-            </field>
-          </fields>
-          <name>SM3_EXECCTRL</name>
-          <resetValue>0x0001f000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0118</addressOffset>
-          <description>Control behaviour of the input/output shift registers for state machine 3</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[31:31]</bitRange>
-              <description>When 1, RX FIFO steals the TX FIFO's storage, and becomes twice as deep.\n
-                TX FIFO is disabled as a result (always reads as both full and empty).\n
-                FIFOs are flushed when this bit is changed.</description>
-              <name>FJOIN_RX</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[30:30]</bitRange>
-              <description>When 1, TX FIFO steals the RX FIFO's storage, and becomes twice as deep.\n
-                RX FIFO is disabled as a result (always reads as both full and empty).\n
-                FIFOs are flushed when this bit is changed.</description>
-              <name>FJOIN_TX</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[29:25]</bitRange>
-              <description>Number of bits shifted out of OSR before autopull, or conditional pull (PULL IFEMPTY), will take place.\n
-                Write 0 for value of 32.</description>
-              <name>PULL_THRESH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[24:20]</bitRange>
-              <description>Number of bits shifted into ISR before autopush, or conditional push (PUSH IFFULL), will take place.\n
-                Write 0 for value of 32.</description>
-              <name>PUSH_THRESH</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[19:19]</bitRange>
-              <description>1 = shift out of output shift register to right. 0 = to left.</description>
-              <name>OUT_SHIFTDIR</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[18:18]</bitRange>
-              <description>1 = shift input shift register to right (data enters from left). 0 = to left.</description>
-              <name>IN_SHIFTDIR</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[17:17]</bitRange>
-              <description>Pull automatically when the output shift register is emptied, i.e. on or following an OUT instruction which causes the output shift counter to reach or exceed PULL_THRESH.</description>
-              <name>AUTOPULL</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[16:16]</bitRange>
-              <description>Push automatically when the input shift register is filled, i.e. on an IN instruction which causes the input shift counter to reach or exceed PUSH_THRESH.</description>
-              <name>AUTOPUSH</name>
-            </field>
-          </fields>
-          <name>SM3_SHIFTCTRL</name>
-          <resetValue>0x000c0000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x011c</addressOffset>
-          <description>Current instruction address of state machine 3</description>
-          <fields>
-            <field>
-              <access>read-only</access>
-              <bitRange>[4:0]</bitRange>
-              <name>SM3_ADDR</name>
-            </field>
-          </fields>
-          <name>SM3_ADDR</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0120</addressOffset>
-          <description>Read to see the instruction currently addressed by state machine 3's program counter\n
-            Write to execute an instruction immediately (including jumps) and then resume execution.</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[15:0]</bitRange>
-              <name>SM3_INSTR</name>
-            </field>
-          </fields>
-          <name>SM3_INSTR</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0124</addressOffset>
-          <description>State machine pin control</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[31:29]</bitRange>
-              <description>The number of MSBs of the Delay/Side-set instruction field which are used for side-set. Inclusive of the enable bit, if present. Minimum of 0 (all delay bits, no side-set) and maximum of 5 (all side-set, no delay).</description>
-              <name>SIDESET_COUNT</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[28:26]</bitRange>
-              <description>The number of pins asserted by a SET. In the range 0 to 5 inclusive.</description>
-              <name>SET_COUNT</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[25:20]</bitRange>
-              <description>The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV PINS instruction. In the range 0 to 32 inclusive.</description>
-              <name>OUT_COUNT</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[19:15]</bitRange>
-              <description>The pin which is mapped to the least-significant bit of a state machine's IN data bus. Higher-numbered pins are mapped to consecutively more-significant data bits, with a modulo of 32 applied to pin number.</description>
-              <name>IN_BASE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[14:10]</bitRange>
-              <description>The lowest-numbered pin that will be affected by a side-set operation. The MSBs of an instruction's side-set/delay field (up to 5, determined by SIDESET_COUNT) are used for side-set data, with the remaining LSBs used for delay. The least-significant bit of the side-set portion is the bit written to this pin, with more-significant bits written to higher-numbered pins.</description>
-              <name>SIDESET_BASE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[9:5]</bitRange>
-              <description>The lowest-numbered pin that will be affected by a SET PINS or SET PINDIRS instruction. The data written to this pin is the least-significant bit of the SET data.</description>
-              <name>SET_BASE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[4:0]</bitRange>
-              <description>The lowest-numbered pin that will be affected by an OUT PINS, OUT PINDIRS or MOV PINS instruction. The data written to this pin will always be the least-significant bit of the OUT or MOV data.</description>
-              <name>OUT_BASE</name>
-            </field>
-          </fields>
-          <name>SM3_PINCTRL</name>
-          <resetValue>0x14000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0128</addressOffset>
-          <description>Raw Interrupts</description>
-          <fields>
-            <field>
-              <access>read-only</access>
-              <bitRange>[11:11]</bitRange>
-              <name>SM3</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[10:10]</bitRange>
-              <name>SM2</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[9:9]</bitRange>
-              <name>SM1</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[8:8]</bitRange>
-              <name>SM0</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[7:7]</bitRange>
-              <name>SM3_TXNFULL</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[6:6]</bitRange>
-              <name>SM2_TXNFULL</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[5:5]</bitRange>
-              <name>SM1_TXNFULL</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[4:4]</bitRange>
-              <name>SM0_TXNFULL</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[3:3]</bitRange>
-              <name>SM3_RXNEMPTY</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[2:2]</bitRange>
-              <name>SM2_RXNEMPTY</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[1:1]</bitRange>
-              <name>SM1_RXNEMPTY</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[0:0]</bitRange>
-              <name>SM0_RXNEMPTY</name>
-            </field>
-          </fields>
-          <name>INTR</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x012c</addressOffset>
-          <description>Interrupt Enable for irq0</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[11:11]</bitRange>
-              <name>SM3</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[10:10]</bitRange>
-              <name>SM2</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[9:9]</bitRange>
-              <name>SM1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[8:8]</bitRange>
-              <name>SM0</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[7:7]</bitRange>
-              <name>SM3_TXNFULL</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[6:6]</bitRange>
-              <name>SM2_TXNFULL</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[5:5]</bitRange>
-              <name>SM1_TXNFULL</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[4:4]</bitRange>
-              <name>SM0_TXNFULL</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[3:3]</bitRange>
-              <name>SM3_RXNEMPTY</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[2:2]</bitRange>
-              <name>SM2_RXNEMPTY</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[1:1]</bitRange>
-              <name>SM1_RXNEMPTY</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[0:0]</bitRange>
-              <name>SM0_RXNEMPTY</name>
-            </field>
-          </fields>
-          <name>IRQ0_INTE</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0130</addressOffset>
-          <description>Interrupt Force for irq0</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[11:11]</bitRange>
-              <name>SM3</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[10:10]</bitRange>
-              <name>SM2</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[9:9]</bitRange>
-              <name>SM1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[8:8]</bitRange>
-              <name>SM0</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[7:7]</bitRange>
-              <name>SM3_TXNFULL</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[6:6]</bitRange>
-              <name>SM2_TXNFULL</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[5:5]</bitRange>
-              <name>SM1_TXNFULL</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[4:4]</bitRange>
-              <name>SM0_TXNFULL</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[3:3]</bitRange>
-              <name>SM3_RXNEMPTY</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[2:2]</bitRange>
-              <name>SM2_RXNEMPTY</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[1:1]</bitRange>
-              <name>SM1_RXNEMPTY</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[0:0]</bitRange>
-              <name>SM0_RXNEMPTY</name>
-            </field>
-          </fields>
-          <name>IRQ0_INTF</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0134</addressOffset>
-          <description>Interrupt status after masking &amp; forcing for irq0</description>
-          <fields>
-            <field>
-              <access>read-only</access>
-              <bitRange>[11:11]</bitRange>
-              <name>SM3</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[10:10]</bitRange>
-              <name>SM2</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[9:9]</bitRange>
-              <name>SM1</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[8:8]</bitRange>
-              <name>SM0</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[7:7]</bitRange>
-              <name>SM3_TXNFULL</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[6:6]</bitRange>
-              <name>SM2_TXNFULL</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[5:5]</bitRange>
-              <name>SM1_TXNFULL</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[4:4]</bitRange>
-              <name>SM0_TXNFULL</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[3:3]</bitRange>
-              <name>SM3_RXNEMPTY</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[2:2]</bitRange>
-              <name>SM2_RXNEMPTY</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[1:1]</bitRange>
-              <name>SM1_RXNEMPTY</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[0:0]</bitRange>
-              <name>SM0_RXNEMPTY</name>
-            </field>
-          </fields>
-          <name>IRQ0_INTS</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0138</addressOffset>
-          <description>Interrupt Enable for irq1</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[11:11]</bitRange>
-              <name>SM3</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[10:10]</bitRange>
-              <name>SM2</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[9:9]</bitRange>
-              <name>SM1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[8:8]</bitRange>
-              <name>SM0</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[7:7]</bitRange>
-              <name>SM3_TXNFULL</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[6:6]</bitRange>
-              <name>SM2_TXNFULL</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[5:5]</bitRange>
-              <name>SM1_TXNFULL</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[4:4]</bitRange>
-              <name>SM0_TXNFULL</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[3:3]</bitRange>
-              <name>SM3_RXNEMPTY</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[2:2]</bitRange>
-              <name>SM2_RXNEMPTY</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[1:1]</bitRange>
-              <name>SM1_RXNEMPTY</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[0:0]</bitRange>
-              <name>SM0_RXNEMPTY</name>
-            </field>
-          </fields>
-          <name>IRQ1_INTE</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x013c</addressOffset>
-          <description>Interrupt Force for irq1</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[11:11]</bitRange>
-              <name>SM3</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[10:10]</bitRange>
-              <name>SM2</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[9:9]</bitRange>
-              <name>SM1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[8:8]</bitRange>
-              <name>SM0</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[7:7]</bitRange>
-              <name>SM3_TXNFULL</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[6:6]</bitRange>
-              <name>SM2_TXNFULL</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[5:5]</bitRange>
-              <name>SM1_TXNFULL</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[4:4]</bitRange>
-              <name>SM0_TXNFULL</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[3:3]</bitRange>
-              <name>SM3_RXNEMPTY</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[2:2]</bitRange>
-              <name>SM2_RXNEMPTY</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[1:1]</bitRange>
-              <name>SM1_RXNEMPTY</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[0:0]</bitRange>
-              <name>SM0_RXNEMPTY</name>
-            </field>
-          </fields>
-          <name>IRQ1_INTF</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0140</addressOffset>
-          <description>Interrupt status after masking &amp; forcing for irq1</description>
-          <fields>
-            <field>
-              <access>read-only</access>
-              <bitRange>[11:11]</bitRange>
-              <name>SM3</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[10:10]</bitRange>
-              <name>SM2</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[9:9]</bitRange>
-              <name>SM1</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[8:8]</bitRange>
-              <name>SM0</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[7:7]</bitRange>
-              <name>SM3_TXNFULL</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[6:6]</bitRange>
-              <name>SM2_TXNFULL</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[5:5]</bitRange>
-              <name>SM1_TXNFULL</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[4:4]</bitRange>
-              <name>SM0_TXNFULL</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[3:3]</bitRange>
-              <name>SM3_RXNEMPTY</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[2:2]</bitRange>
-              <name>SM2_RXNEMPTY</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[1:1]</bitRange>
-              <name>SM1_RXNEMPTY</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[0:0]</bitRange>
-              <name>SM0_RXNEMPTY</name>
-            </field>
-          </fields>
-          <name>IRQ1_INTS</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-      </registers>
-      <size>32</size>
-      <version>1</version>
-    </peripheral>
-    <peripheral derivedFrom="PIO0">
-      <baseAddress>0x50300000</baseAddress>
-      <interrupt>
-        <name>PIO1_IRQ_0</name>
-        <value>9</value>
-      </interrupt>
-      <interrupt>
-        <name>PIO1_IRQ_1</name>
-        <value>10</value>
-      </interrupt>
-      <name>PIO1</name>
-    </peripheral>
-    <peripheral>
-      <addressBlock>
-        <offset>0</offset>
-        <size>0x0200</size>
-        <usage>registers</usage>
-      </addressBlock>
-      <baseAddress>0xd0000000</baseAddress>
-      <description>Single-cycle IO block\n
-        Provides core-local and inter-core hardware for the two processors, with single-cycle access.</description>
-      <interrupt>
-        <name>SIO_IRQ_PROC0</name>
-        <value>15</value>
-      </interrupt>
-      <interrupt>
-        <name>SIO_IRQ_PROC1</name>
-        <value>16</value>
-      </interrupt>
-      <name>SIO</name>
-      <registers>
-        <register>
-          <access>read-only</access>
-          <addressOffset>0x0000</addressOffset>
-          <description>Processor core identifier\n
-            Value is 0 when read from processor core 0, and 1 when read from processor core 1.</description>
-          <name>CPUID</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0004</addressOffset>
-          <description>Input value for GPIO pins</description>
-          <fields>
-            <field>
-              <access>read-only</access>
-              <bitRange>[29:0]</bitRange>
-              <description>Input value for GPIO0...29</description>
-              <name>GPIO_IN</name>
-            </field>
-          </fields>
-          <name>GPIO_IN</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0008</addressOffset>
-          <description>Input value for QSPI pins</description>
-          <fields>
-            <field>
-              <access>read-only</access>
-              <bitRange>[5:0]</bitRange>
-              <description>Input value on QSPI IO in order 0..5: SCLK, SSn, SD0, SD1, SD2, SD3</description>
-              <name>GPIO_HI_IN</name>
-            </field>
-          </fields>
-          <name>GPIO_HI_IN</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0010</addressOffset>
-          <description>GPIO output value</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[29:0]</bitRange>
-              <description>Set output level (1/0 -&gt; high/low) for GPIO0...29.\n
-                Reading back gives the last value written, NOT the input value from the pins.\n
-                If core 0 and core 1 both write to GPIO_OUT simultaneously (or to a SET/CLR/XOR alias),\n
-                the result is as though the write from core 0 took place first,\n
-                and the write from core 1 was then applied to that intermediate result.</description>
-              <name>GPIO_OUT</name>
-            </field>
-          </fields>
-          <name>GPIO_OUT</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0014</addressOffset>
-          <description>GPIO output value set</description>
-          <fields>
-            <field>
-              <access>write-only</access>
-              <bitRange>[29:0]</bitRange>
-              <description>Perform an atomic bit-set on GPIO_OUT, i.e. `GPIO_OUT |= wdata`</description>
-              <name>GPIO_OUT_SET</name>
-            </field>
-          </fields>
-          <name>GPIO_OUT_SET</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0018</addressOffset>
-          <description>GPIO output value clear</description>
-          <fields>
-            <field>
-              <access>write-only</access>
-              <bitRange>[29:0]</bitRange>
-              <description>Perform an atomic bit-clear on GPIO_OUT, i.e. `GPIO_OUT &amp;= ~wdata`</description>
-              <name>GPIO_OUT_CLR</name>
-            </field>
-          </fields>
-          <name>GPIO_OUT_CLR</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x001c</addressOffset>
-          <description>GPIO output value XOR</description>
-          <fields>
-            <field>
-              <access>write-only</access>
-              <bitRange>[29:0]</bitRange>
-              <description>Perform an atomic bitwise XOR on GPIO_OUT, i.e. `GPIO_OUT ^= wdata`</description>
-              <name>GPIO_OUT_XOR</name>
-            </field>
-          </fields>
-          <name>GPIO_OUT_XOR</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0020</addressOffset>
-          <description>GPIO output enable</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[29:0]</bitRange>
-              <description>Set output enable (1/0 -&gt; output/input) for GPIO0...29.\n
-                Reading back gives the last value written.\n
-                If core 0 and core 1 both write to GPIO_OE simultaneously (or to a SET/CLR/XOR alias),\n
-                the result is as though the write from core 0 took place first,\n
-                and the write from core 1 was then applied to that intermediate result.</description>
-              <name>GPIO_OE</name>
-            </field>
-          </fields>
-          <name>GPIO_OE</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0024</addressOffset>
-          <description>GPIO output enable set</description>
-          <fields>
-            <field>
-              <access>write-only</access>
-              <bitRange>[29:0]</bitRange>
-              <description>Perform an atomic bit-set on GPIO_OE, i.e. `GPIO_OE |= wdata`</description>
-              <name>GPIO_OE_SET</name>
-            </field>
-          </fields>
-          <name>GPIO_OE_SET</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0028</addressOffset>
-          <description>GPIO output enable clear</description>
-          <fields>
-            <field>
-              <access>write-only</access>
-              <bitRange>[29:0]</bitRange>
-              <description>Perform an atomic bit-clear on GPIO_OE, i.e. `GPIO_OE &amp;= ~wdata`</description>
-              <name>GPIO_OE_CLR</name>
-            </field>
-          </fields>
-          <name>GPIO_OE_CLR</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x002c</addressOffset>
-          <description>GPIO output enable XOR</description>
-          <fields>
-            <field>
-              <access>write-only</access>
-              <bitRange>[29:0]</bitRange>
-              <description>Perform an atomic bitwise XOR on GPIO_OE, i.e. `GPIO_OE ^= wdata`</description>
-              <name>GPIO_OE_XOR</name>
-            </field>
-          </fields>
-          <name>GPIO_OE_XOR</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0030</addressOffset>
-          <description>QSPI output value</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[5:0]</bitRange>
-              <description>Set output level (1/0 -&gt; high/low) for QSPI IO0...5.\n
-                Reading back gives the last value written, NOT the input value from the pins.\n
-                If core 0 and core 1 both write to GPIO_HI_OUT simultaneously (or to a SET/CLR/XOR alias),\n
-                the result is as though the write from core 0 took place first,\n
-                and the write from core 1 was then applied to that intermediate result.</description>
-              <name>GPIO_HI_OUT</name>
-            </field>
-          </fields>
-          <name>GPIO_HI_OUT</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0034</addressOffset>
-          <description>QSPI output value set</description>
-          <fields>
-            <field>
-              <access>write-only</access>
-              <bitRange>[5:0]</bitRange>
-              <description>Perform an atomic bit-set on GPIO_HI_OUT, i.e. `GPIO_HI_OUT |= wdata`</description>
-              <name>GPIO_HI_OUT_SET</name>
-            </field>
-          </fields>
-          <name>GPIO_HI_OUT_SET</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0038</addressOffset>
-          <description>QSPI output value clear</description>
-          <fields>
-            <field>
-              <access>write-only</access>
-              <bitRange>[5:0]</bitRange>
-              <description>Perform an atomic bit-clear on GPIO_HI_OUT, i.e. `GPIO_HI_OUT &amp;= ~wdata`</description>
-              <name>GPIO_HI_OUT_CLR</name>
-            </field>
-          </fields>
-          <name>GPIO_HI_OUT_CLR</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x003c</addressOffset>
-          <description>QSPI output value XOR</description>
-          <fields>
-            <field>
-              <access>write-only</access>
-              <bitRange>[5:0]</bitRange>
-              <description>Perform an atomic bitwise XOR on GPIO_HI_OUT, i.e. `GPIO_HI_OUT ^= wdata`</description>
-              <name>GPIO_HI_OUT_XOR</name>
-            </field>
-          </fields>
-          <name>GPIO_HI_OUT_XOR</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0040</addressOffset>
-          <description>QSPI output enable</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[5:0]</bitRange>
-              <description>Set output enable (1/0 -&gt; output/input) for QSPI IO0...5.\n
-                Reading back gives the last value written.\n
-                If core 0 and core 1 both write to GPIO_HI_OE simultaneously (or to a SET/CLR/XOR alias),\n
-                the result is as though the write from core 0 took place first,\n
-                and the write from core 1 was then applied to that intermediate result.</description>
-              <name>GPIO_HI_OE</name>
-            </field>
-          </fields>
-          <name>GPIO_HI_OE</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0044</addressOffset>
-          <description>QSPI output enable set</description>
-          <fields>
-            <field>
-              <access>write-only</access>
-              <bitRange>[5:0]</bitRange>
-              <description>Perform an atomic bit-set on GPIO_HI_OE, i.e. `GPIO_HI_OE |= wdata`</description>
-              <name>GPIO_HI_OE_SET</name>
-            </field>
-          </fields>
-          <name>GPIO_HI_OE_SET</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0048</addressOffset>
-          <description>QSPI output enable clear</description>
-          <fields>
-            <field>
-              <access>write-only</access>
-              <bitRange>[5:0]</bitRange>
-              <description>Perform an atomic bit-clear on GPIO_HI_OE, i.e. `GPIO_HI_OE &amp;= ~wdata`</description>
-              <name>GPIO_HI_OE_CLR</name>
-            </field>
-          </fields>
-          <name>GPIO_HI_OE_CLR</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x004c</addressOffset>
-          <description>QSPI output enable XOR</description>
-          <fields>
-            <field>
-              <access>write-only</access>
-              <bitRange>[5:0]</bitRange>
-              <description>Perform an atomic bitwise XOR on GPIO_HI_OE, i.e. `GPIO_HI_OE ^= wdata`</description>
-              <name>GPIO_HI_OE_XOR</name>
-            </field>
-          </fields>
-          <name>GPIO_HI_OE_XOR</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0050</addressOffset>
-          <description>Status register for inter-core FIFOs (mailboxes).\n
-            There is one FIFO in the core 0 -&gt; core 1 direction, and one core 1 -&gt; core 0. Both are 32 bits wide and 8 words deep.\n
-            Core 0 can see the read side of the 1-&gt;0 FIFO (RX), and the write side of 0-&gt;1 FIFO (TX).\n
-            Core 1 can see the read side of the 0-&gt;1 FIFO (RX), and the write side of 1-&gt;0 FIFO (TX).\n
-            The SIO IRQ for each core is the logical OR of the VLD, WOF and ROE fields of its FIFO_ST register.</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[3:3]</bitRange>
-              <description>Sticky flag indicating the RX FIFO was read when empty. This read was ignored by the FIFO.</description>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>ROE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[2:2]</bitRange>
-              <description>Sticky flag indicating the TX FIFO was written when full. This write was ignored by the FIFO.</description>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <name>WOF</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[1:1]</bitRange>
-              <description>Value is 1 if this core's TX FIFO is not full (i.e. if FIFO_WR is ready for more data)</description>
-              <name>RDY</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[0:0]</bitRange>
-              <description>Value is 1 if this core's RX FIFO is not empty (i.e. if FIFO_RD is valid)</description>
-              <name>VLD</name>
-            </field>
-          </fields>
-          <name>FIFO_ST</name>
-          <resetValue>0x00000002</resetValue>
-        </register>
-        <register>
-          <access>write-only</access>
-          <addressOffset>0x0054</addressOffset>
-          <description>Write access to this core's TX FIFO</description>
-          <name>FIFO_WR</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-only</access>
-          <addressOffset>0x0058</addressOffset>
-          <description>Read access to this core's RX FIFO</description>
-          <name>FIFO_RD</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-only</access>
-          <addressOffset>0x005c</addressOffset>
-          <description>Spinlock state\n
-            A bitmap containing the state of all 32 spinlocks (1=locked).\n
-            Mainly intended for debugging.</description>
-          <name>SPINLOCK_ST</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x0060</addressOffset>
-          <description>Divider unsigned dividend\n
-            Write to the DIVIDEND operand of the divider, i.e. the p in `p / q`.\n
-            Any operand write starts a new calculation. The results appear in QUOTIENT, REMAINDER.\n
-            UDIVIDEND/SDIVIDEND are aliases of the same internal register. The U alias starts an\n
-            unsigned calculation, and the S alias starts a signed calculation.</description>
-          <name>DIV_UDIVIDEND</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x0064</addressOffset>
-          <description>Divider unsigned divisor\n
-            Write to the DIVISOR operand of the divider, i.e. the q in `p / q`.\n
-            Any operand write starts a new calculation. The results appear in QUOTIENT, REMAINDER.\n
-            UDIVISOR/SDIVISOR are aliases of the same internal register. The U alias starts an\n
-            unsigned calculation, and the S alias starts a signed calculation.</description>
-          <name>DIV_UDIVISOR</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x0068</addressOffset>
-          <description>Divider signed dividend\n
-            The same as UDIVIDEND, but starts a signed calculation, rather than unsigned.</description>
-          <name>DIV_SDIVIDEND</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x006c</addressOffset>
-          <description>Divider signed divisor\n
-            The same as UDIVISOR, but starts a signed calculation, rather than unsigned.</description>
-          <name>DIV_SDIVISOR</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x0070</addressOffset>
-          <description>Divider result quotient\n
-            The result of `DIVIDEND / DIVISOR` (division). Contents undefined while CSR_READY is low.\n
-            For signed calculations, QUOTIENT is negative when the signs of DIVIDEND and DIVISOR differ.\n
-            This register can be written to directly, for context save/restore purposes. This halts any\n
-            in-progress calculation and sets the CSR_READY and CSR_DIRTY flags.\n
-            Reading from QUOTIENT clears the CSR_DIRTY flag, so should read results in the order\n
-            REMAINDER, QUOTIENT if CSR_DIRTY is used.</description>
-          <name>DIV_QUOTIENT</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x0074</addressOffset>
-          <description>Divider result remainder\n
-            The result of `DIVIDEND % DIVISOR` (modulo). Contents undefined while CSR_READY is low.\n
-            For signed calculations, REMAINDER is negative only when DIVIDEND is negative.\n
-            This register can be written to directly, for context save/restore purposes. This halts any\n
-            in-progress calculation and sets the CSR_READY and CSR_DIRTY flags.</description>
-          <name>DIV_REMAINDER</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x0078</addressOffset>
-          <description>Control and status register for divider.</description>
-          <fields>
-            <field>
-              <access>read-only</access>
-              <bitRange>[1:1]</bitRange>
-              <description>Changes to 1 when any register is written, and back to 0 when QUOTIENT is read.\n
-                Software can use this flag to make save/restore more efficient (skip if not DIRTY).\n
-                If the flag is used in this way, it's recommended to either read QUOTIENT only,\n
-                or REMAINDER and then QUOTIENT, to prevent data loss on context switch.</description>
-              <name>DIRTY</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[0:0]</bitRange>
-              <description>Reads as 0 when a calculation is in progress, 1 otherwise.\n
-                Writing an operand (xDIVIDEND, xDIVISOR) will immediately start a new calculation, no\n
-                matter if one is already in progress.\n
-                Writing to a result register will immediately terminate any in-progress calculation\n
-                and set the READY and DIRTY flags.</description>
-              <name>READY</name>
-            </field>
-          </fields>
-          <name>DIV_CSR</name>
-          <resetValue>0x00000001</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x0080</addressOffset>
-          <description>Read/write access to accumulator 0</description>
-          <name>INTERP0_ACCUM0</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x0084</addressOffset>
-          <description>Read/write access to accumulator 1</description>
-          <name>INTERP0_ACCUM1</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x0088</addressOffset>
-          <description>Read/write access to BASE0 register.</description>
-          <name>INTERP0_BASE0</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x008c</addressOffset>
-          <description>Read/write access to BASE1 register.</description>
-          <name>INTERP0_BASE1</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x0090</addressOffset>
-          <description>Read/write access to BASE2 register.</description>
-          <name>INTERP0_BASE2</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-only</access>
-          <addressOffset>0x0094</addressOffset>
-          <description>Read LANE0 result, and simultaneously write lane results to both accumulators (POP).</description>
-          <name>INTERP0_POP_LANE0</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-only</access>
-          <addressOffset>0x0098</addressOffset>
-          <description>Read LANE1 result, and simultaneously write lane results to both accumulators (POP).</description>
-          <name>INTERP0_POP_LANE1</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-only</access>
-          <addressOffset>0x009c</addressOffset>
-          <description>Read FULL result, and simultaneously write lane results to both accumulators (POP).</description>
-          <name>INTERP0_POP_FULL</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-only</access>
-          <addressOffset>0x00a0</addressOffset>
-          <description>Read LANE0 result, without altering any internal state (PEEK).</description>
-          <name>INTERP0_PEEK_LANE0</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-only</access>
-          <addressOffset>0x00a4</addressOffset>
-          <description>Read LANE1 result, without altering any internal state (PEEK).</description>
-          <name>INTERP0_PEEK_LANE1</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-only</access>
-          <addressOffset>0x00a8</addressOffset>
-          <description>Read FULL result, without altering any internal state (PEEK).</description>
-          <name>INTERP0_PEEK_FULL</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x00ac</addressOffset>
-          <description>Control register for lane 0</description>
-          <fields>
-            <field>
-              <access>read-only</access>
-              <bitRange>[25:25]</bitRange>
-              <description>Set if either OVERF0 or OVERF1 is set.</description>
-              <name>OVERF</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[24:24]</bitRange>
-              <description>Indicates if any masked-off MSBs in ACCUM1 are set.</description>
-              <name>OVERF1</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[23:23]</bitRange>
-              <description>Indicates if any masked-off MSBs in ACCUM0 are set.</description>
-              <name>OVERF0</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[21:21]</bitRange>
-              <description>Only present on INTERP0 on each core. If BLEND mode is enabled:\n
-                - LANE1 result is a linear interpolation between BASE0 and BASE1, controlled\n
-                by the 8 LSBs of lane 1 shift and mask value (a fractional number between\n
-                0 and 255/256ths)\n
-                - LANE0 result does not have BASE0 added (yields only the 8 LSBs of lane 1 shift+mask value)\n
-                - FULL result does not have lane 1 shift+mask value added (BASE2 + lane 0 shift+mask)\n
-                LANE1 SIGNED flag controls whether the interpolation is signed or unsigned.</description>
-              <name>BLEND</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[20:19]</bitRange>
-              <description>ORed into bits 29:28 of the lane result presented to the processor on the bus.\n
-                No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence\n
-                of pointers into flash or SRAM.</description>
-              <name>FORCE_MSB</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[18:18]</bitRange>
-              <description>If 1, mask + shift is bypassed for LANE0 result. This does not affect FULL result.</description>
-              <name>ADD_RAW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[17:17]</bitRange>
-              <description>If 1, feed the opposite lane's result into this lane's accumulator on POP.</description>
-              <name>CROSS_RESULT</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[16:16]</bitRange>
-              <description>If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware.\n
-                Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass)</description>
-              <name>CROSS_INPUT</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[15:15]</bitRange>
-              <description>If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits\n
-                before adding to BASE0, and LANE0 PEEK/POP appear extended to 32 bits when read by processor.</description>
-              <name>SIGNED</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[14:10]</bitRange>
-              <description>The most-significant bit allowed to pass by the mask (inclusive)\n
-                Setting MSB &lt; LSB may cause chip to turn inside-out</description>
-              <name>MASK_MSB</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[9:5]</bitRange>
-              <description>The least-significant bit allowed to pass by the mask (inclusive)</description>
-              <name>MASK_LSB</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[4:0]</bitRange>
-              <description>Logical right-shift applied to accumulator before masking</description>
-              <name>SHIFT</name>
-            </field>
-          </fields>
-          <name>INTERP0_CTRL_LANE0</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x00b0</addressOffset>
-          <description>Control register for lane 1</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[20:19]</bitRange>
-              <description>ORed into bits 29:28 of the lane result presented to the processor on the bus.\n
-                No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence\n
-                of pointers into flash or SRAM.</description>
-              <name>FORCE_MSB</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[18:18]</bitRange>
-              <description>If 1, mask + shift is bypassed for LANE1 result. This does not affect FULL result.</description>
-              <name>ADD_RAW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[17:17]</bitRange>
-              <description>If 1, feed the opposite lane's result into this lane's accumulator on POP.</description>
-              <name>CROSS_RESULT</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[16:16]</bitRange>
-              <description>If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware.\n
-                Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass)</description>
-              <name>CROSS_INPUT</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[15:15]</bitRange>
-              <description>If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits\n
-                before adding to BASE1, and LANE1 PEEK/POP appear extended to 32 bits when read by processor.</description>
-              <name>SIGNED</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[14:10]</bitRange>
-              <description>The most-significant bit allowed to pass by the mask (inclusive)\n
-                Setting MSB &lt; LSB may cause chip to turn inside-out</description>
-              <name>MASK_MSB</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[9:5]</bitRange>
-              <description>The least-significant bit allowed to pass by the mask (inclusive)</description>
-              <name>MASK_LSB</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[4:0]</bitRange>
-              <description>Logical right-shift applied to accumulator before masking</description>
-              <name>SHIFT</name>
-            </field>
-          </fields>
-          <name>INTERP0_CTRL_LANE1</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x00b4</addressOffset>
-          <description>Values written here are atomically added to ACCUM0\n
-            Reading yields lane 0's raw shift and mask value (BASE0 not added).</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[23:0]</bitRange>
-              <name>INTERP0_ACCUM0_ADD</name>
-            </field>
-          </fields>
-          <name>INTERP0_ACCUM0_ADD</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x00b8</addressOffset>
-          <description>Values written here are atomically added to ACCUM1\n
-            Reading yields lane 1's raw shift and mask value (BASE1 not added).</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[23:0]</bitRange>
-              <name>INTERP0_ACCUM1_ADD</name>
-            </field>
-          </fields>
-          <name>INTERP0_ACCUM1_ADD</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>write-only</access>
-          <addressOffset>0x00bc</addressOffset>
-          <description>On write, the lower 16 bits go to BASE0, upper bits to BASE1 simultaneously.\n
-            Each half is sign-extended to 32 bits if that lane's SIGNED flag is set.</description>
-          <name>INTERP0_BASE_1AND0</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x00c0</addressOffset>
-          <description>Read/write access to accumulator 0</description>
-          <name>INTERP1_ACCUM0</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x00c4</addressOffset>
-          <description>Read/write access to accumulator 1</description>
-          <name>INTERP1_ACCUM1</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x00c8</addressOffset>
-          <description>Read/write access to BASE0 register.</description>
-          <name>INTERP1_BASE0</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x00cc</addressOffset>
-          <description>Read/write access to BASE1 register.</description>
-          <name>INTERP1_BASE1</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x00d0</addressOffset>
-          <description>Read/write access to BASE2 register.</description>
-          <name>INTERP1_BASE2</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-only</access>
-          <addressOffset>0x00d4</addressOffset>
-          <description>Read LANE0 result, and simultaneously write lane results to both accumulators (POP).</description>
-          <name>INTERP1_POP_LANE0</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-only</access>
-          <addressOffset>0x00d8</addressOffset>
-          <description>Read LANE1 result, and simultaneously write lane results to both accumulators (POP).</description>
-          <name>INTERP1_POP_LANE1</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-only</access>
-          <addressOffset>0x00dc</addressOffset>
-          <description>Read FULL result, and simultaneously write lane results to both accumulators (POP).</description>
-          <name>INTERP1_POP_FULL</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-only</access>
-          <addressOffset>0x00e0</addressOffset>
-          <description>Read LANE0 result, without altering any internal state (PEEK).</description>
-          <name>INTERP1_PEEK_LANE0</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-only</access>
-          <addressOffset>0x00e4</addressOffset>
-          <description>Read LANE1 result, without altering any internal state (PEEK).</description>
-          <name>INTERP1_PEEK_LANE1</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-only</access>
-          <addressOffset>0x00e8</addressOffset>
-          <description>Read FULL result, without altering any internal state (PEEK).</description>
-          <name>INTERP1_PEEK_FULL</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x00ec</addressOffset>
-          <description>Control register for lane 0</description>
-          <fields>
-            <field>
-              <access>read-only</access>
-              <bitRange>[25:25]</bitRange>
-              <description>Set if either OVERF0 or OVERF1 is set.</description>
-              <name>OVERF</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[24:24]</bitRange>
-              <description>Indicates if any masked-off MSBs in ACCUM1 are set.</description>
-              <name>OVERF1</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[23:23]</bitRange>
-              <description>Indicates if any masked-off MSBs in ACCUM0 are set.</description>
-              <name>OVERF0</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[22:22]</bitRange>
-              <description>Only present on INTERP1 on each core. If CLAMP mode is enabled:\n
-                - LANE0 result is shifted and masked ACCUM0, clamped by a lower bound of\n
-                BASE0 and an upper bound of BASE1.\n
-                - Signedness of these comparisons is determined by LANE0_CTRL_SIGNED</description>
-              <name>CLAMP</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[20:19]</bitRange>
-              <description>ORed into bits 29:28 of the lane result presented to the processor on the bus.\n
-                No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence\n
-                of pointers into flash or SRAM.</description>
-              <name>FORCE_MSB</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[18:18]</bitRange>
-              <description>If 1, mask + shift is bypassed for LANE0 result. This does not affect FULL result.</description>
-              <name>ADD_RAW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[17:17]</bitRange>
-              <description>If 1, feed the opposite lane's result into this lane's accumulator on POP.</description>
-              <name>CROSS_RESULT</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[16:16]</bitRange>
-              <description>If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware.\n
-                Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass)</description>
-              <name>CROSS_INPUT</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[15:15]</bitRange>
-              <description>If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits\n
-                before adding to BASE0, and LANE0 PEEK/POP appear extended to 32 bits when read by processor.</description>
-              <name>SIGNED</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[14:10]</bitRange>
-              <description>The most-significant bit allowed to pass by the mask (inclusive)\n
-                Setting MSB &lt; LSB may cause chip to turn inside-out</description>
-              <name>MASK_MSB</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[9:5]</bitRange>
-              <description>The least-significant bit allowed to pass by the mask (inclusive)</description>
-              <name>MASK_LSB</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[4:0]</bitRange>
-              <description>Logical right-shift applied to accumulator before masking</description>
-              <name>SHIFT</name>
-            </field>
-          </fields>
-          <name>INTERP1_CTRL_LANE0</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x00f0</addressOffset>
-          <description>Control register for lane 1</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[20:19]</bitRange>
-              <description>ORed into bits 29:28 of the lane result presented to the processor on the bus.\n
-                No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence\n
-                of pointers into flash or SRAM.</description>
-              <name>FORCE_MSB</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[18:18]</bitRange>
-              <description>If 1, mask + shift is bypassed for LANE1 result. This does not affect FULL result.</description>
-              <name>ADD_RAW</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[17:17]</bitRange>
-              <description>If 1, feed the opposite lane's result into this lane's accumulator on POP.</description>
-              <name>CROSS_RESULT</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[16:16]</bitRange>
-              <description>If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware.\n
-                Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass)</description>
-              <name>CROSS_INPUT</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[15:15]</bitRange>
-              <description>If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits\n
-                before adding to BASE1, and LANE1 PEEK/POP appear extended to 32 bits when read by processor.</description>
-              <name>SIGNED</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[14:10]</bitRange>
-              <description>The most-significant bit allowed to pass by the mask (inclusive)\n
-                Setting MSB &lt; LSB may cause chip to turn inside-out</description>
-              <name>MASK_MSB</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[9:5]</bitRange>
-              <description>The least-significant bit allowed to pass by the mask (inclusive)</description>
-              <name>MASK_LSB</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[4:0]</bitRange>
-              <description>Logical right-shift applied to accumulator before masking</description>
-              <name>SHIFT</name>
-            </field>
-          </fields>
-          <name>INTERP1_CTRL_LANE1</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x00f4</addressOffset>
-          <description>Values written here are atomically added to ACCUM0\n
-            Reading yields lane 0's raw shift and mask value (BASE0 not added).</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[23:0]</bitRange>
-              <name>INTERP1_ACCUM0_ADD</name>
-            </field>
-          </fields>
-          <name>INTERP1_ACCUM0_ADD</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0x00f8</addressOffset>
-          <description>Values written here are atomically added to ACCUM1\n
-            Reading yields lane 1's raw shift and mask value (BASE1 not added).</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[23:0]</bitRange>
-              <name>INTERP1_ACCUM1_ADD</name>
-            </field>
-          </fields>
-          <name>INTERP1_ACCUM1_ADD</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>write-only</access>
-          <addressOffset>0x00fc</addressOffset>
-          <description>On write, the lower 16 bits go to BASE0, upper bits to BASE1 simultaneously.\n
-            Each half is sign-extended to 32 bits if that lane's SIGNED flag is set.</description>
-          <name>INTERP1_BASE_1AND0</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x0100</addressOffset>
-          <description>Reading from a spinlock address will:\n
-            - Return 0 if lock is already locked\n
-            - Otherwise return nonzero, and simultaneously claim the lock\n\n
-            Writing (any value) releases the lock.\n
-            If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n
-            The value returned on success is 0x1 &lt;&lt; lock number.</description>
-          <name>SPINLOCK0</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x0104</addressOffset>
-          <description>Reading from a spinlock address will:\n
-            - Return 0 if lock is already locked\n
-            - Otherwise return nonzero, and simultaneously claim the lock\n\n
-            Writing (any value) releases the lock.\n
-            If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n
-            The value returned on success is 0x1 &lt;&lt; lock number.</description>
-          <name>SPINLOCK1</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x0108</addressOffset>
-          <description>Reading from a spinlock address will:\n
-            - Return 0 if lock is already locked\n
-            - Otherwise return nonzero, and simultaneously claim the lock\n\n
-            Writing (any value) releases the lock.\n
-            If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n
-            The value returned on success is 0x1 &lt;&lt; lock number.</description>
-          <name>SPINLOCK2</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x010c</addressOffset>
-          <description>Reading from a spinlock address will:\n
-            - Return 0 if lock is already locked\n
-            - Otherwise return nonzero, and simultaneously claim the lock\n\n
-            Writing (any value) releases the lock.\n
-            If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n
-            The value returned on success is 0x1 &lt;&lt; lock number.</description>
-          <name>SPINLOCK3</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x0110</addressOffset>
-          <description>Reading from a spinlock address will:\n
-            - Return 0 if lock is already locked\n
-            - Otherwise return nonzero, and simultaneously claim the lock\n\n
-            Writing (any value) releases the lock.\n
-            If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n
-            The value returned on success is 0x1 &lt;&lt; lock number.</description>
-          <name>SPINLOCK4</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x0114</addressOffset>
-          <description>Reading from a spinlock address will:\n
-            - Return 0 if lock is already locked\n
-            - Otherwise return nonzero, and simultaneously claim the lock\n\n
-            Writing (any value) releases the lock.\n
-            If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n
-            The value returned on success is 0x1 &lt;&lt; lock number.</description>
-          <name>SPINLOCK5</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x0118</addressOffset>
-          <description>Reading from a spinlock address will:\n
-            - Return 0 if lock is already locked\n
-            - Otherwise return nonzero, and simultaneously claim the lock\n\n
-            Writing (any value) releases the lock.\n
-            If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n
-            The value returned on success is 0x1 &lt;&lt; lock number.</description>
-          <name>SPINLOCK6</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x011c</addressOffset>
-          <description>Reading from a spinlock address will:\n
-            - Return 0 if lock is already locked\n
-            - Otherwise return nonzero, and simultaneously claim the lock\n\n
-            Writing (any value) releases the lock.\n
-            If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n
-            The value returned on success is 0x1 &lt;&lt; lock number.</description>
-          <name>SPINLOCK7</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x0120</addressOffset>
-          <description>Reading from a spinlock address will:\n
-            - Return 0 if lock is already locked\n
-            - Otherwise return nonzero, and simultaneously claim the lock\n\n
-            Writing (any value) releases the lock.\n
-            If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n
-            The value returned on success is 0x1 &lt;&lt; lock number.</description>
-          <name>SPINLOCK8</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x0124</addressOffset>
-          <description>Reading from a spinlock address will:\n
-            - Return 0 if lock is already locked\n
-            - Otherwise return nonzero, and simultaneously claim the lock\n\n
-            Writing (any value) releases the lock.\n
-            If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n
-            The value returned on success is 0x1 &lt;&lt; lock number.</description>
-          <name>SPINLOCK9</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x0128</addressOffset>
-          <description>Reading from a spinlock address will:\n
-            - Return 0 if lock is already locked\n
-            - Otherwise return nonzero, and simultaneously claim the lock\n\n
-            Writing (any value) releases the lock.\n
-            If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n
-            The value returned on success is 0x1 &lt;&lt; lock number.</description>
-          <name>SPINLOCK10</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x012c</addressOffset>
-          <description>Reading from a spinlock address will:\n
-            - Return 0 if lock is already locked\n
-            - Otherwise return nonzero, and simultaneously claim the lock\n\n
-            Writing (any value) releases the lock.\n
-            If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n
-            The value returned on success is 0x1 &lt;&lt; lock number.</description>
-          <name>SPINLOCK11</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x0130</addressOffset>
-          <description>Reading from a spinlock address will:\n
-            - Return 0 if lock is already locked\n
-            - Otherwise return nonzero, and simultaneously claim the lock\n\n
-            Writing (any value) releases the lock.\n
-            If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n
-            The value returned on success is 0x1 &lt;&lt; lock number.</description>
-          <name>SPINLOCK12</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x0134</addressOffset>
-          <description>Reading from a spinlock address will:\n
-            - Return 0 if lock is already locked\n
-            - Otherwise return nonzero, and simultaneously claim the lock\n\n
-            Writing (any value) releases the lock.\n
-            If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n
-            The value returned on success is 0x1 &lt;&lt; lock number.</description>
-          <name>SPINLOCK13</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x0138</addressOffset>
-          <description>Reading from a spinlock address will:\n
-            - Return 0 if lock is already locked\n
-            - Otherwise return nonzero, and simultaneously claim the lock\n\n
-            Writing (any value) releases the lock.\n
-            If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n
-            The value returned on success is 0x1 &lt;&lt; lock number.</description>
-          <name>SPINLOCK14</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x013c</addressOffset>
-          <description>Reading from a spinlock address will:\n
-            - Return 0 if lock is already locked\n
-            - Otherwise return nonzero, and simultaneously claim the lock\n\n
-            Writing (any value) releases the lock.\n
-            If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n
-            The value returned on success is 0x1 &lt;&lt; lock number.</description>
-          <name>SPINLOCK15</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x0140</addressOffset>
-          <description>Reading from a spinlock address will:\n
-            - Return 0 if lock is already locked\n
-            - Otherwise return nonzero, and simultaneously claim the lock\n\n
-            Writing (any value) releases the lock.\n
-            If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n
-            The value returned on success is 0x1 &lt;&lt; lock number.</description>
-          <name>SPINLOCK16</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x0144</addressOffset>
-          <description>Reading from a spinlock address will:\n
-            - Return 0 if lock is already locked\n
-            - Otherwise return nonzero, and simultaneously claim the lock\n\n
-            Writing (any value) releases the lock.\n
-            If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n
-            The value returned on success is 0x1 &lt;&lt; lock number.</description>
-          <name>SPINLOCK17</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x0148</addressOffset>
-          <description>Reading from a spinlock address will:\n
-            - Return 0 if lock is already locked\n
-            - Otherwise return nonzero, and simultaneously claim the lock\n\n
-            Writing (any value) releases the lock.\n
-            If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n
-            The value returned on success is 0x1 &lt;&lt; lock number.</description>
-          <name>SPINLOCK18</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x014c</addressOffset>
-          <description>Reading from a spinlock address will:\n
-            - Return 0 if lock is already locked\n
-            - Otherwise return nonzero, and simultaneously claim the lock\n\n
-            Writing (any value) releases the lock.\n
-            If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n
-            The value returned on success is 0x1 &lt;&lt; lock number.</description>
-          <name>SPINLOCK19</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x0150</addressOffset>
-          <description>Reading from a spinlock address will:\n
-            - Return 0 if lock is already locked\n
-            - Otherwise return nonzero, and simultaneously claim the lock\n\n
-            Writing (any value) releases the lock.\n
-            If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n
-            The value returned on success is 0x1 &lt;&lt; lock number.</description>
-          <name>SPINLOCK20</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x0154</addressOffset>
-          <description>Reading from a spinlock address will:\n
-            - Return 0 if lock is already locked\n
-            - Otherwise return nonzero, and simultaneously claim the lock\n\n
-            Writing (any value) releases the lock.\n
-            If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n
-            The value returned on success is 0x1 &lt;&lt; lock number.</description>
-          <name>SPINLOCK21</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x0158</addressOffset>
-          <description>Reading from a spinlock address will:\n
-            - Return 0 if lock is already locked\n
-            - Otherwise return nonzero, and simultaneously claim the lock\n\n
-            Writing (any value) releases the lock.\n
-            If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n
-            The value returned on success is 0x1 &lt;&lt; lock number.</description>
-          <name>SPINLOCK22</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x015c</addressOffset>
-          <description>Reading from a spinlock address will:\n
-            - Return 0 if lock is already locked\n
-            - Otherwise return nonzero, and simultaneously claim the lock\n\n
-            Writing (any value) releases the lock.\n
-            If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n
-            The value returned on success is 0x1 &lt;&lt; lock number.</description>
-          <name>SPINLOCK23</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x0160</addressOffset>
-          <description>Reading from a spinlock address will:\n
-            - Return 0 if lock is already locked\n
-            - Otherwise return nonzero, and simultaneously claim the lock\n\n
-            Writing (any value) releases the lock.\n
-            If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n
-            The value returned on success is 0x1 &lt;&lt; lock number.</description>
-          <name>SPINLOCK24</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x0164</addressOffset>
-          <description>Reading from a spinlock address will:\n
-            - Return 0 if lock is already locked\n
-            - Otherwise return nonzero, and simultaneously claim the lock\n\n
-            Writing (any value) releases the lock.\n
-            If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n
-            The value returned on success is 0x1 &lt;&lt; lock number.</description>
-          <name>SPINLOCK25</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x0168</addressOffset>
-          <description>Reading from a spinlock address will:\n
-            - Return 0 if lock is already locked\n
-            - Otherwise return nonzero, and simultaneously claim the lock\n\n
-            Writing (any value) releases the lock.\n
-            If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n
-            The value returned on success is 0x1 &lt;&lt; lock number.</description>
-          <name>SPINLOCK26</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x016c</addressOffset>
-          <description>Reading from a spinlock address will:\n
-            - Return 0 if lock is already locked\n
-            - Otherwise return nonzero, and simultaneously claim the lock\n\n
-            Writing (any value) releases the lock.\n
-            If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n
-            The value returned on success is 0x1 &lt;&lt; lock number.</description>
-          <name>SPINLOCK27</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x0170</addressOffset>
-          <description>Reading from a spinlock address will:\n
-            - Return 0 if lock is already locked\n
-            - Otherwise return nonzero, and simultaneously claim the lock\n\n
-            Writing (any value) releases the lock.\n
-            If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n
-            The value returned on success is 0x1 &lt;&lt; lock number.</description>
-          <name>SPINLOCK28</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x0174</addressOffset>
-          <description>Reading from a spinlock address will:\n
-            - Return 0 if lock is already locked\n
-            - Otherwise return nonzero, and simultaneously claim the lock\n\n
-            Writing (any value) releases the lock.\n
-            If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n
-            The value returned on success is 0x1 &lt;&lt; lock number.</description>
-          <name>SPINLOCK29</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x0178</addressOffset>
-          <description>Reading from a spinlock address will:\n
-            - Return 0 if lock is already locked\n
-            - Otherwise return nonzero, and simultaneously claim the lock\n\n
-            Writing (any value) releases the lock.\n
-            If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n
-            The value returned on success is 0x1 &lt;&lt; lock number.</description>
-          <name>SPINLOCK30</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <access>read-write</access>
-          <addressOffset>0x017c</addressOffset>
-          <description>Reading from a spinlock address will:\n
-            - Return 0 if lock is already locked\n
-            - Otherwise return nonzero, and simultaneously claim the lock\n\n
-            Writing (any value) releases the lock.\n
-            If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n
-            The value returned on success is 0x1 &lt;&lt; lock number.</description>
-          <name>SPINLOCK31</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-      </registers>
-      <size>32</size>
-      <version>1</version>
-    </peripheral>
-    <peripheral>
-      <addressBlock>
-        <offset>0</offset>
-        <size>0x10000</size>
-        <usage>registers</usage>
-      </addressBlock>
-      <baseAddress>0xe0000000</baseAddress>
-      <name>PPB</name>
-      <registers>
-        <register>
-          <addressOffset>0xe010</addressOffset>
-          <description>Use the SysTick Control and Status Register to enable the SysTick features.</description>
-          <fields>
-            <field>
-              <access>read-only</access>
-              <bitRange>[16:16]</bitRange>
-              <description>Returns 1 if timer counted to 0 since last time this was read. Clears on read by application or debugger.</description>
-              <name>COUNTFLAG</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[2:2]</bitRange>
-              <description>SysTick clock source. Always reads as one if SYST_CALIB reports NOREF.\n
-                Selects the SysTick timer clock source:\n
-                0 = External reference clock.\n
-                1 = Processor clock.</description>
-              <name>CLKSOURCE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[1:1]</bitRange>
-              <description>Enables SysTick exception request:\n
-                0 = Counting down to zero does not assert the SysTick exception request.\n
-                1 = Counting down to zero to asserts the SysTick exception request.</description>
-              <name>TICKINT</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[0:0]</bitRange>
-              <description>Enable SysTick counter:\n
-                0 = Counter disabled.\n
-                1 = Counter enabled.</description>
-              <name>ENABLE</name>
-            </field>
-          </fields>
-          <name>SYST_CSR</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0xe014</addressOffset>
-          <description>Use the SysTick Reload Value Register to specify the start value to load into the current value register when the counter reaches 0. It can be any value between 0 and 0x00FFFFFF. A start value of 0 is possible, but has no effect because the SysTick interrupt and COUNTFLAG are activated when counting from 1 to 0. The reset value of this register is UNKNOWN.\n
-            To generate a multi-shot timer with a period of N processor clock cycles, use a RELOAD value of N-1. For example, if the SysTick interrupt is required every 100 clock pulses, set RELOAD to 99.</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[23:0]</bitRange>
-              <description>Value to load into the SysTick Current Value Register when the counter reaches 0.</description>
-              <name>RELOAD</name>
-            </field>
-          </fields>
-          <name>SYST_RVR</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0xe018</addressOffset>
-          <description>Use the SysTick Current Value Register to find the current value in the register. The reset value of this register is UNKNOWN.</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[23:0]</bitRange>
-              <description>Reads return the current value of the SysTick counter. This register is write-clear. Writing to it with any value clears the register to 0. Clearing this register also clears the COUNTFLAG bit of the SysTick Control and Status Register.</description>
-              <name>CURRENT</name>
-            </field>
-          </fields>
-          <name>SYST_CVR</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0xe01c</addressOffset>
-          <description>Use the SysTick Calibration Value Register to enable software to scale to any required speed using divide and multiply.</description>
-          <fields>
-            <field>
-              <access>read-only</access>
-              <bitRange>[31:31]</bitRange>
-              <description>If reads as 1, the Reference clock is not provided - the CLKSOURCE bit of the SysTick Control and Status register will be forced to 1 and cannot be cleared to 0.</description>
-              <name>NOREF</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[30:30]</bitRange>
-              <description>If reads as 1, the calibration value for 10ms is inexact (due to clock frequency).</description>
-              <name>SKEW</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[23:0]</bitRange>
-              <description>An optional Reload value to be used for 10ms (100Hz) timing, subject to system clock skew errors. If the value reads as 0, the calibration value is not known.</description>
-              <name>TENMS</name>
-            </field>
-          </fields>
-          <name>SYST_CALIB</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0xe100</addressOffset>
-          <description>Use the Interrupt Set-Enable Register to enable interrupts and determine which interrupts are currently enabled.\n
-            If a pending interrupt is enabled, the NVIC activates the interrupt based on its priority. If an interrupt is not enabled, asserting its interrupt signal changes the interrupt state to pending, but the NVIC never activates the interrupt, regardless of its priority.</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[31:0]</bitRange>
-              <description>Interrupt set-enable bits.\n
-                Write:\n
-                0 = No effect.\n
-                1 = Enable interrupt.\n
-                Read:\n
-                0 = Interrupt disabled.\n
-                1 = Interrupt enabled.</description>
-              <name>SETENA</name>
-            </field>
-          </fields>
-          <name>NVIC_ISER</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0xe180</addressOffset>
-          <description>Use the Interrupt Clear-Enable Registers to disable interrupts and determine which interrupts are currently enabled.</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[31:0]</bitRange>
-              <description>Interrupt clear-enable bits.\n
-                Write:\n
-                0 = No effect.\n
-                1 = Disable interrupt.\n
-                Read:\n
-                0 = Interrupt disabled.\n
-                1 = Interrupt enabled.</description>
-              <name>CLRENA</name>
-            </field>
-          </fields>
-          <name>NVIC_ICER</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0xe200</addressOffset>
-          <description>The NVIC_ISPR forces interrupts into the pending state, and shows which interrupts are pending.</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[31:0]</bitRange>
-              <description>Interrupt set-pending bits.\n
-                Write:\n
-                0 = No effect.\n
-                1 = Changes interrupt state to pending.\n
-                Read:\n
-                0 = Interrupt is not pending.\n
-                1 = Interrupt is pending.\n
-                Note: Writing 1 to the NVIC_ISPR bit corresponding to:\n
-                An interrupt that is pending has no effect.\n
-                A disabled interrupt sets the state of that interrupt to pending.</description>
-              <name>SETPEND</name>
-            </field>
-          </fields>
-          <name>NVIC_ISPR</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0xe280</addressOffset>
-          <description>Use the Interrupt Clear-Pending Register to clear pending interrupts and determine which interrupts are currently pending.</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[31:0]</bitRange>
-              <description>Interrupt clear-pending bits.\n
-                Write:\n
-                0 = No effect.\n
-                1 = Removes pending state and interrupt.\n
-                Read:\n
-                0 = Interrupt is not pending.\n
-                1 = Interrupt is pending.</description>
-              <name>CLRPEND</name>
-            </field>
-          </fields>
-          <name>NVIC_ICPR</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0xe400</addressOffset>
-          <description>Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest.\n
-            Note: Writing 1 to an NVIC_ICPR bit does not affect the active state of the corresponding interrupt.\n
-            These registers are only word-accessible</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[31:30]</bitRange>
-              <description>Priority of interrupt 3</description>
-              <name>IP_3</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[23:22]</bitRange>
-              <description>Priority of interrupt 2</description>
-              <name>IP_2</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[15:14]</bitRange>
-              <description>Priority of interrupt 1</description>
-              <name>IP_1</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[7:6]</bitRange>
-              <description>Priority of interrupt 0</description>
-              <name>IP_0</name>
-            </field>
-          </fields>
-          <name>NVIC_IPR0</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0xe404</addressOffset>
-          <description>Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest.</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[31:30]</bitRange>
-              <description>Priority of interrupt 7</description>
-              <name>IP_7</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[23:22]</bitRange>
-              <description>Priority of interrupt 6</description>
-              <name>IP_6</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[15:14]</bitRange>
-              <description>Priority of interrupt 5</description>
-              <name>IP_5</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[7:6]</bitRange>
-              <description>Priority of interrupt 4</description>
-              <name>IP_4</name>
-            </field>
-          </fields>
-          <name>NVIC_IPR1</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0xe408</addressOffset>
-          <description>Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest.</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[31:30]</bitRange>
-              <description>Priority of interrupt 11</description>
-              <name>IP_11</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[23:22]</bitRange>
-              <description>Priority of interrupt 10</description>
-              <name>IP_10</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[15:14]</bitRange>
-              <description>Priority of interrupt 9</description>
-              <name>IP_9</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[7:6]</bitRange>
-              <description>Priority of interrupt 8</description>
-              <name>IP_8</name>
-            </field>
-          </fields>
-          <name>NVIC_IPR2</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0xe40c</addressOffset>
-          <description>Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest.</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[31:30]</bitRange>
-              <description>Priority of interrupt 15</description>
-              <name>IP_15</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[23:22]</bitRange>
-              <description>Priority of interrupt 14</description>
-              <name>IP_14</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[15:14]</bitRange>
-              <description>Priority of interrupt 13</description>
-              <name>IP_13</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[7:6]</bitRange>
-              <description>Priority of interrupt 12</description>
-              <name>IP_12</name>
-            </field>
-          </fields>
-          <name>NVIC_IPR3</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0xe410</addressOffset>
-          <description>Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest.</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[31:30]</bitRange>
-              <description>Priority of interrupt 19</description>
-              <name>IP_19</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[23:22]</bitRange>
-              <description>Priority of interrupt 18</description>
-              <name>IP_18</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[15:14]</bitRange>
-              <description>Priority of interrupt 17</description>
-              <name>IP_17</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[7:6]</bitRange>
-              <description>Priority of interrupt 16</description>
-              <name>IP_16</name>
-            </field>
-          </fields>
-          <name>NVIC_IPR4</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0xe414</addressOffset>
-          <description>Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest.</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[31:30]</bitRange>
-              <description>Priority of interrupt 23</description>
-              <name>IP_23</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[23:22]</bitRange>
-              <description>Priority of interrupt 22</description>
-              <name>IP_22</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[15:14]</bitRange>
-              <description>Priority of interrupt 21</description>
-              <name>IP_21</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[7:6]</bitRange>
-              <description>Priority of interrupt 20</description>
-              <name>IP_20</name>
-            </field>
-          </fields>
-          <name>NVIC_IPR5</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0xe418</addressOffset>
-          <description>Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest.</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[31:30]</bitRange>
-              <description>Priority of interrupt 27</description>
-              <name>IP_27</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[23:22]</bitRange>
-              <description>Priority of interrupt 26</description>
-              <name>IP_26</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[15:14]</bitRange>
-              <description>Priority of interrupt 25</description>
-              <name>IP_25</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[7:6]</bitRange>
-              <description>Priority of interrupt 24</description>
-              <name>IP_24</name>
-            </field>
-          </fields>
-          <name>NVIC_IPR6</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0xe41c</addressOffset>
-          <description>Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest.</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[31:30]</bitRange>
-              <description>Priority of interrupt 31</description>
-              <name>IP_31</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[23:22]</bitRange>
-              <description>Priority of interrupt 30</description>
-              <name>IP_30</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[15:14]</bitRange>
-              <description>Priority of interrupt 29</description>
-              <name>IP_29</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[7:6]</bitRange>
-              <description>Priority of interrupt 28</description>
-              <name>IP_28</name>
-            </field>
-          </fields>
-          <name>NVIC_IPR7</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0xed00</addressOffset>
-          <description>Read the CPU ID Base Register to determine: the ID number of the processor core, the version number of the processor core, the implementation details of the processor core.</description>
-          <fields>
-            <field>
-              <access>read-only</access>
-              <bitRange>[31:24]</bitRange>
-              <description>Implementor code: 0x41 = ARM</description>
-              <name>IMPLEMENTER</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[23:20]</bitRange>
-              <description>Major revision number n in the rnpm revision status:\n
-                0x0 = Revision 0.</description>
-              <name>VARIANT</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[19:16]</bitRange>
-              <description>Constant that defines the architecture of the processor:\n
-                0xC = ARMv6-M architecture.</description>
-              <name>ARCHITECTURE</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[15:4]</bitRange>
-              <description>Number of processor within family: 0xC60 = Cortex-M0+</description>
-              <name>PARTNO</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[3:0]</bitRange>
-              <description>Minor revision number m in the rnpm revision status:\n
-                0x1 = Patch 1.</description>
-              <name>REVISION</name>
-            </field>
-          </fields>
-          <name>CPUID</name>
-          <resetValue>0x410cc601</resetValue>
-        </register>
-        <register>
-          <addressOffset>0xed04</addressOffset>
-          <description>Use the Interrupt Control State Register to set a pending Non-Maskable Interrupt (NMI), set or clear a pending PendSV, set or clear a pending SysTick, check for pending exceptions, check the vector number of the highest priority pended exception, check the vector number of the active exception.</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[31:31]</bitRange>
-              <description>Setting this bit will activate an NMI. Since NMI is the highest priority exception, it will activate as soon as it is registered.\n
-                NMI set-pending bit.\n
-                Write:\n
-                0 = No effect.\n
-                1 = Changes NMI exception state to pending.\n
-                Read:\n
-                0 = NMI exception is not pending.\n
-                1 = NMI exception is pending.\n
-                Because NMI is the highest-priority exception, normally the processor enters the NMI\n
-                exception handler as soon as it detects a write of 1 to this bit. Entering the handler then clears\n
-                this bit to 0. This means a read of this bit by the NMI exception handler returns 1 only if the\n
-                NMI signal is reasserted while the processor is executing that handler.</description>
-              <name>NMIPENDSET</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[28:28]</bitRange>
-              <description>PendSV set-pending bit.\n
-                Write:\n
-                0 = No effect.\n
-                1 = Changes PendSV exception state to pending.\n
-                Read:\n
-                0 = PendSV exception is not pending.\n
-                1 = PendSV exception is pending.\n
-                Writing 1 to this bit is the only way to set the PendSV exception state to pending.</description>
-              <name>PENDSVSET</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[27:27]</bitRange>
-              <description>PendSV clear-pending bit.\n
-                Write:\n
-                0 = No effect.\n
-                1 = Removes the pending state from the PendSV exception.</description>
-              <name>PENDSVCLR</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[26:26]</bitRange>
-              <description>SysTick exception set-pending bit.\n
-                Write:\n
-                0 = No effect.\n
-                1 = Changes SysTick exception state to pending.\n
-                Read:\n
-                0 = SysTick exception is not pending.\n
-                1 = SysTick exception is pending.</description>
-              <name>PENDSTSET</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[25:25]</bitRange>
-              <description>SysTick exception clear-pending bit.\n
-                Write:\n
-                0 = No effect.\n
-                1 = Removes the pending state from the SysTick exception.\n
-                This bit is WO. On a register read its value is Unknown.</description>
-              <name>PENDSTCLR</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[23:23]</bitRange>
-              <description>The system can only access this bit when the core is halted. It indicates that a pending interrupt is to be taken in the next running cycle. If C_MASKINTS is clear in the Debug Halting Control and Status Register, the interrupt is serviced.</description>
-              <name>ISRPREEMPT</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[22:22]</bitRange>
-              <description>External interrupt pending flag</description>
-              <name>ISRPENDING</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[20:12]</bitRange>
-              <description>Indicates the exception number for the highest priority pending exception: 0 = no pending exceptions. Non zero = The pending state includes the effect of memory-mapped enable and mask registers. It does not include the PRIMASK special-purpose register qualifier.</description>
-              <name>VECTPENDING</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[8:0]</bitRange>
-              <description>Active exception number field. Reset clears the VECTACTIVE field.</description>
-              <name>VECTACTIVE</name>
-            </field>
-          </fields>
-          <name>ICSR</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0xed08</addressOffset>
-          <description>The VTOR holds the vector table offset address.</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[31:8]</bitRange>
-              <description>Bits [31:8] of the indicate the vector table offset address.</description>
-              <name>TBLOFF</name>
-            </field>
-          </fields>
-          <name>VTOR</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0xed0c</addressOffset>
-          <description>Use the Application Interrupt and Reset Control Register to: determine data endianness, clear all active state information from debug halt mode, request a system reset.</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[31:16]</bitRange>
-              <description>Register key:\n
-                Reads as Unknown\n
-                On writes, write 0x05FA to VECTKEY, otherwise the write is ignored.</description>
-              <name>VECTKEY</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[15:15]</bitRange>
-              <description>Data endianness implemented:\n
-                0 = Little-endian.</description>
-              <name>ENDIANESS</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[2:2]</bitRange>
-              <description>Writing 1 to this bit causes the SYSRESETREQ signal to the outer system to be asserted to request a reset. The intention is to force a large system reset of all major components except for debug. The C_HALT bit in the DHCSR is cleared as a result of the system reset requested. The debugger does not lose contact with the device.</description>
-              <name>SYSRESETREQ</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[1:1]</bitRange>
-              <description>Clears all active state information for fixed and configurable exceptions. This bit: is self-clearing, can only be set by the DAP when the core is halted.  When set: clears all active exception status of the processor, forces a return to Thread mode, forces an IPSR of 0. A debugger must re-initialize the stack.</description>
-              <name>VECTCLRACTIVE</name>
-            </field>
-          </fields>
-          <name>AIRCR</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0xed10</addressOffset>
-          <description>System Control Register. Use the System Control Register for power-management functions: signal to the system when the processor can enter a low power state, control how the processor enters and exits low power states.</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[4:4]</bitRange>
-              <description>Send Event on Pending bit:\n
-                0 = Only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded.\n
-                1 = Enabled events and all interrupts, including disabled interrupts, can wakeup the processor.\n
-                When an event or interrupt becomes pending, the event signal wakes up the processor from WFE. If the\n
-                processor is not waiting for an event, the event is registered and affects the next WFE.\n
-                The processor also wakes up on execution of an SEV instruction or an external event.</description>
-              <name>SEVONPEND</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[2:2]</bitRange>
-              <description>Controls whether the processor uses sleep or deep sleep as its low power mode:\n
-                0 = Sleep.\n
-                1 = Deep sleep.</description>
-              <name>SLEEPDEEP</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[1:1]</bitRange>
-              <description>Indicates sleep-on-exit when returning from Handler mode to Thread mode:\n
-                0 = Do not sleep when returning to Thread mode.\n
-                1 = Enter sleep, or deep sleep, on return from an ISR to Thread mode.\n
-                Setting this bit to 1 enables an interrupt driven application to avoid returning to an empty main application.</description>
-              <name>SLEEPONEXIT</name>
-            </field>
-          </fields>
-          <name>SCR</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0xed14</addressOffset>
-          <description>The Configuration and Control Register permanently enables stack alignment and causes unaligned accesses to result in a Hard Fault.</description>
-          <fields>
-            <field>
-              <access>read-only</access>
-              <bitRange>[9:9]</bitRange>
-              <description>Always reads as one, indicates 8-byte stack alignment on exception entry. On exception entry, the processor uses bit[9] of the stacked PSR to indicate the stack alignment. On return from the exception it uses this stacked bit to restore the correct stack alignment.</description>
-              <name>STKALIGN</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[3:3]</bitRange>
-              <description>Always reads as one, indicates that all unaligned accesses generate a HardFault.</description>
-              <name>UNALIGN_TRP</name>
-            </field>
-          </fields>
-          <name>CCR</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0xed1c</addressOffset>
-          <description>System handlers are a special class of exception handler that can have their priority set to any of the priority levels. Use the System Handler Priority Register 2 to set the priority of SVCall.</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[31:30]</bitRange>
-              <description>Priority of system handler 11, SVCall</description>
-              <name>PRI_11</name>
-            </field>
-          </fields>
-          <name>SHPR2</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0xed20</addressOffset>
-          <description>System handlers are a special class of exception handler that can have their priority set to any of the priority levels. Use the System Handler Priority Register 3 to set the priority of PendSV and SysTick.</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[31:30]</bitRange>
-              <description>Priority of system handler 15, SysTick</description>
-              <name>PRI_15</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[23:22]</bitRange>
-              <description>Priority of system handler 14, PendSV</description>
-              <name>PRI_14</name>
-            </field>
-          </fields>
-          <name>SHPR3</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0xed24</addressOffset>
-          <description>Use the System Handler Control and State Register to determine or clear the pending status of SVCall.</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[15:15]</bitRange>
-              <description>Reads as 1 if SVCall is Pending.  Write 1 to set pending SVCall, write 0 to clear pending SVCall.</description>
-              <name>SVCALLPENDED</name>
-            </field>
-          </fields>
-          <name>SHCSR</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0xed90</addressOffset>
-          <description>Read the MPU Type Register to determine if the processor implements an MPU, and how many regions the MPU supports.</description>
-          <fields>
-            <field>
-              <access>read-only</access>
-              <bitRange>[23:16]</bitRange>
-              <description>Instruction region. Reads as zero as ARMv6-M only supports a unified MPU.</description>
-              <name>IREGION</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[15:8]</bitRange>
-              <description>Number of regions supported by the MPU.</description>
-              <name>DREGION</name>
-            </field>
-            <field>
-              <access>read-only</access>
-              <bitRange>[0:0]</bitRange>
-              <description>Indicates support for separate instruction and data address maps. Reads as 0 as ARMv6-M only supports a unified MPU.</description>
-              <name>SEPARATE</name>
-            </field>
-          </fields>
-          <name>MPU_TYPE</name>
-          <resetValue>0x00000800</resetValue>
-        </register>
-        <register>
-          <addressOffset>0xed94</addressOffset>
-          <description>Use the MPU Control Register to enable and disable the MPU, and to control whether the default memory map is enabled as a background region for privileged accesses, and whether the MPU is enabled for HardFaults and NMIs.</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[2:2]</bitRange>
-              <description>Controls whether the default memory map is enabled as a background region for privileged accesses. This bit is ignored when ENABLE is clear.\n
-                0 = If the MPU is enabled, disables use of the default memory map. Any memory access to a location not\n
-                covered by any enabled region causes a fault.\n
-                1 = If the MPU is enabled, enables use of the default memory map as a background region for privileged software accesses.\n
-                When enabled, the background region acts as if it is region number -1. Any region that is defined and enabled has priority over this default map.</description>
-              <name>PRIVDEFENA</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[1:1]</bitRange>
-              <description>Controls the use of the MPU for HardFaults and NMIs. Setting this bit when ENABLE is clear results in UNPREDICTABLE behaviour.\n
-                When the MPU is enabled:\n
-                0 = MPU is disabled during HardFault and NMI handlers, regardless of the value of the ENABLE bit.\n
-                1 = the MPU is enabled during HardFault and NMI handlers.</description>
-              <name>HFNMIENA</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[0:0]</bitRange>
-              <description>Enables the MPU. If the MPU is disabled, privileged and unprivileged accesses use the default memory map.\n
-                0 = MPU disabled.\n
-                1 = MPU enabled.</description>
-              <name>ENABLE</name>
-            </field>
-          </fields>
-          <name>MPU_CTRL</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0xed98</addressOffset>
-          <description>Use the MPU Region Number Register to select the region currently accessed by MPU_RBAR and MPU_RASR.</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[3:0]</bitRange>
-              <description>Indicates the MPU region referenced by the MPU_RBAR and MPU_RASR registers.\n
-                The MPU supports 8 memory regions, so the permitted values of this field are 0-7.</description>
-              <name>REGION</name>
-            </field>
-          </fields>
-          <name>MPU_RNR</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0xed9c</addressOffset>
-          <description>Read the MPU Region Base Address Register to determine the base address of the region identified by MPU_RNR. Write to update the base address of said region or that of a specified region, with whose number MPU_RNR will also be updated.</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[31:8]</bitRange>
-              <description>Base address of the region.</description>
-              <name>ADDR</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[4:4]</bitRange>
-              <description>On writes, indicates whether the write must update the base address of the region identified by the REGION field, updating the MPU_RNR to indicate this new region.\n
-                Write:\n
-                0 = MPU_RNR not changed, and the processor:\n
-                Updates the base address for the region specified in the MPU_RNR.\n
-                Ignores the value of the REGION field.\n
-                1 = The processor:\n
-                Updates the value of the MPU_RNR to the value of the REGION field.\n
-                Updates the base address for the region specified in the REGION field.\n
-                Always reads as zero.</description>
-              <name>VALID</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[3:0]</bitRange>
-              <description>On writes, specifies the number of the region whose base address to update provided VALID is set written as 1. On reads, returns bits [3:0] of MPU_RNR.</description>
-              <name>REGION</name>
-            </field>
-          </fields>
-          <name>MPU_RBAR</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-        <register>
-          <addressOffset>0xeda0</addressOffset>
-          <description>Use the MPU Region Attribute and Size Register to define the size, access behaviour and memory type of the region identified by MPU_RNR, and enable that region.</description>
-          <fields>
-            <field>
-              <access>read-write</access>
-              <bitRange>[31:16]</bitRange>
-              <description>The MPU Region Attribute field. Use to define the region attribute control.\n
-                28 = XN: Instruction access disable bit:\n
-                0 = Instruction fetches enabled.\n
-                1 = Instruction fetches disabled.\n
-                26:24 = AP: Access permission field\n
-                18 = S: Shareable bit\n
-                17 = C: Cacheable bit\n
-                16 = B: Bufferable bit</description>
-              <name>ATTRS</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[15:8]</bitRange>
-              <description>Subregion Disable. For regions of 256 bytes or larger, each bit of this field controls whether one of the eight equal subregions is enabled.</description>
-              <name>SRD</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[5:1]</bitRange>
-              <description>Indicates the region size. Region size in bytes = 2^(SIZE+1). The minimum permitted value is 7 (b00111) = 256Bytes</description>
-              <name>SIZE</name>
-            </field>
-            <field>
-              <access>read-write</access>
-              <bitRange>[0:0]</bitRange>
-              <description>Enables the region.</description>
-              <name>ENABLE</name>
-            </field>
-          </fields>
-          <name>MPU_RASR</name>
-          <resetValue>0x00000000</resetValue>
-        </register>
-      </registers>
-      <size>32</size>
-      <version>1</version>
-    </peripheral>
-    <peripheral>
-      <name>SWI_IRQ</name>
-      <description>Virtual Peripheral to access unused NVIC software interrupts</description>
-      <baseAddress>0</baseAddress>
-      <registers></registers>
-      <interrupt>
-        <name>SWI_IRQ_0</name>
-        <value>26</value>
-      </interrupt>
-      <interrupt>
-        <name>SWI_IRQ_1</name>
-        <value>27</value>
-      </interrupt>
-      <interrupt>
-        <name>SWI_IRQ_2</name>
-        <value>28</value>
-      </interrupt>
-      <interrupt>
-        <name>SWI_IRQ_3</name>
-        <value>29</value>
-      </interrupt>
-      <interrupt>
-        <name>SWI_IRQ_4</name>
-        <value>30</value>
-      </interrupt>
-      <interrupt>
-        <name>SWI_IRQ_5</name>
-        <value>31</value>
-      </interrupt>
-    </peripheral>
-  </peripherals>
-</device>
\ No newline at end of file
diff --git a/svd/rp2040.yaml b/svd/rp2040.yaml
index ca61c523..67b0cdb0 100644
--- a/svd/rp2040.yaml
+++ b/svd/rp2040.yaml
@@ -98,7 +98,7 @@ transforms:
       from: pio::Pio0
       to: pio::Pio
   - MergeEnums:
-      from: pio::vals::Sm\d+ExecctrlStatusSel
+      from: pio::vals::Sm\d+(ExecctrlStatusSel|ExecctrlStatusN)
       to: pio::vals::SmExecctrlStatusSel
   - RenameFields:
       fieldset: pio::regs::Sm\d+(Pinctrl|Shiftctrl|Clkdiv|Execctrl|Addr|Instr)
@@ -337,9 +337,6 @@ transforms:
       from: ep\d+_(.*)
       to: ep_$1
 
-  - Rename:
-      from: usbctrl_dpram::(.*)
-      to: usb_dpram::$1
   - MergeEnums:
       from: usb_dpram::vals::Ep\d+(In|Out)(.*)
       to: usb_dpram::vals::Ep$2
diff --git a/svd/rp2350.yaml b/svd/rp2350.yaml
new file mode 100644
index 00000000..53d2f453
--- /dev/null
+++ b/svd/rp2350.yaml
@@ -0,0 +1,411 @@
+transforms:
+  #- DeleteEnums:
+  #    from: .*
+  #    bit_size: 1
+  - DeleteFieldsets:
+      from: .*
+      useless: true
+
+  # =========== DMA
+  - MergeEnums:
+      from: dma::vals::Ch\d+CtrlTrigTreqSel
+      to: dma::vals::TreqSel
+  - MergeEnums:
+      from: dma::vals::Ch\d+CtrlTrigDataSize
+      to: dma::vals::DataSize
+  - DeleteEnums:
+      from: dma::vals::Ch\d+CtrlTrigRingSize
+  - MergeFieldsets:
+      from: dma::regs::Timer\d+
+      to: dma::regs::Timer
+  - MergeFieldsets:
+      from: dma::regs::Ch\d+CtrlTrig
+      to: dma::regs::CtrlTrig
+  - RenameFields:
+      fieldset: dma::regs::Ch\d+DbgCtdreq
+      from: ch\d+_(.*)
+      to: $1
+  - MergeFieldsets:
+      from: dma::regs::Ch\d+DbgCtdreq
+      to: dma::regs::DbgCtdreq
+  - MakeBlock:
+      blocks: dma::Dma
+      from: ch(\d+)_(.*)
+      to_block: dma::Channel
+      to_outer: ch$1
+      to_inner: $2
+  - MakeRegisterArray:
+      blocks: dma::Dma
+      from: ch\d+
+      to: ch
+  - MakeRegisterArray:
+      blocks: dma::Dma
+      from: timer\d+
+      to: timer
+
+  # =========== TIMER
+  - MakeRegisterArray:
+      blocks: timer0::Timer0
+      from: alarm\d+
+      to: alarm
+  - MergeFieldsets:
+      from: timer0::regs::Int[efrs]
+      to: timer0::regs::Int
+  - MakeFieldArray:
+      fieldsets: timer0::regs::Int
+      from: alarm_\d+
+      to: alarm
+  - Rename:
+      from: timer0::(.*)
+      to: timer::$1
+  - Rename:
+      from: timer::Timer0
+      to: timer::Timer
+
+  # =========== UART
+  - Rename:
+      from: uart0::(.*)
+      to: uart::$1
+  - Rename:
+      from: uart::Uart0
+      to: uart::Uart
+
+  # =========== SPI
+  - Rename:
+      from: spi0::(.*)
+      to: spi::$1
+  - Rename:
+      from: spi::Spi0
+      to: spi::Spi
+  - RenameRegisters:
+      block: spi::Spi
+      from: ssp(.*)
+      to: $1
+  - Rename:
+      from: spi::regs::Ssp(.*)
+      to: spi::regs::$1
+
+  # =========== I2C
+  - Rename:
+      from: i2c0::(.*)
+      to: i2c::$1
+  - Rename:
+      from: i2c::I2c0
+      to: i2c::I2c
+  - DeleteEnums:
+      from: i2c::vals::.*
+      bit_size: 1
+
+  # =========== PIO
+  - Rename:
+      from: pio0::(.*)
+      to: pio::$1
+  - Rename:
+      from: pio::Pio0
+      to: pio::Pio
+  - MergeEnums:
+      from: pio::vals::Sm\d+(ExecctrlStatusSel|ExecctrlStatusN)
+      to: pio::vals::$1
+  - RenameFields:
+      fieldset: pio::regs::Sm\d+(Pinctrl|Shiftctrl|Clkdiv|Execctrl|Addr|Instr)
+      from: sm\d+_(.*)
+      to: $1
+  - MergeFieldsets:
+      from: pio::regs::Sm\d+(Pinctrl|Shiftctrl|Clkdiv|Execctrl|Addr|Instr)
+      to: pio::regs::Sm$1
+  - RenameFields:
+      fieldset: pio::regs::InstrMem\d+
+      from: instr_mem\d+
+      to: instr_mem
+  - MergeFieldsets:
+      from: pio::regs::InstrMem\d+
+      to: pio::regs::InstrMem
+  - MergeFieldsets:
+      from: pio::regs::(Irq\dInt.|Intr)
+      to: pio::regs::Intr
+  - MakeRegisterArray:
+      blocks: pio::Pio
+      from: (instr_mem|txf|rxf)\d+
+      to: $1
+  - MakeBlock:
+      blocks: pio::Pio
+      from: sm(\d+)_(.+)
+      to_outer: sm$1
+      to_inner: $2
+      to_block: pio::StateMachine
+  - MakeRegisterArray:
+      blocks: pio::Pio
+      from: sm\d+
+      to: sm
+  - MakeBlock:
+      blocks: pio::Pio
+      from: irq(\d+)_(.+)
+      to_outer: irq$1
+      to_inner: $2
+      to_block: pio::Irq
+  - MakeRegisterArray:
+      blocks: pio::Pio
+      from: irq\d+
+      to: irqs
+
+  # ========= SIO
+  - MakeBlock:
+      blocks: sio::Sio
+      from: interp(\d+)_(.*)
+      to_block: sio::Interp
+      to_outer: interp$1
+      to_inner: $2
+  - MakeBlock:
+      blocks: sio::Sio
+      from: div_(.*)
+      to_block: sio::Div
+      to_outer: div
+      to_inner: $1
+  - MakeBlock:
+      blocks: sio::Sio
+      from: fifo_(.*)
+      to_block: sio::Fifo
+      to_outer: fifo
+      to_inner: $1
+  - MakeRegisterArray:
+      blocks: sio::Sio
+      from: interp(\d+)
+      to: interp
+  - MakeRegisterArray:
+      blocks: sio::Sio
+      from: spinlock(\d+)
+      to: spinlock
+  - DeleteFieldsets:
+      from: sio::regs::Gpio.*
+  - MakeBlock:
+      blocks: sio::Sio
+      from: gpio_(hi_)?(out|oe)(|_set|_clr|_xor)
+      to_block: sio::Gpio
+      to_outer: gpio_$1$2
+      to_inner: value$3
+  - MakeRegisterArray:
+      blocks: sio::Sio
+      from: gpio_(hi_)?(in|out|oe)
+      to: gpio_$2
+
+  # ========= IO
+  - Rename:
+      from: io_bank0::(.*)
+      to: io::$1
+  - Rename:
+      from: io::IoBank0
+      to: io::Io
+  - MergeEnums:
+      from: io::vals::Gpio.+Ctrl(.+)over
+      to: io::vals::${1}over
+  - DeleteEnums:
+      from: io::vals::Gpio\d+CtrlFuncsel
+      soft: true
+  - MergeFieldsets:
+      from: io::regs::Gpio\d+(Status|Ctrl)
+      to: io::regs::Gpio$1
+  - MakeBlock:
+      blocks: io::Io
+      from: gpio(\d+)_(.*)
+      to_block: io::Gpio
+      to_outer: gpio$1
+      to_inner: $2
+  - MakeRegisterArray:
+      blocks: io::Io
+      from: gpio\d+
+      to: gpio
+  - MakeFieldArray:
+      fieldsets: io::regs::.*Int.*
+      from: gpio\d+_(.*)
+      to: $1
+  - MergeFieldsets:
+      from: io::regs::.*Int.*
+      to: io::regs::Int
+      # io has only 30 gpios, so the last reg has only 6 instead of 8.
+      # homogenize this by picking the first reg and disabling checking.
+      main: .*0
+      check: NoCheck
+  - MakeRegisterArray:
+      blocks: io::Io
+      from: (.*int.*)\d+
+      to: $1
+  - MakeBlock:
+      blocks: io::Io
+      from: (.*)_(int[sfre])
+      to_block: io::Int
+      to_outer: int_$1
+      to_inner: $2
+  - MakeRegisterArray:
+      blocks: io::Io
+      from: int_proc\d
+      to: int_proc
+  - MergeBlocks:
+      from: (io::Io|io_qspi::IoQspi)
+      main: io::Io
+      to: io::Io
+      check: NoCheck
+
+  # =========== PADS
+  - Rename:
+      from: pads_bank0::(.*)
+      to: pads::$1
+  - Rename:
+      from: pads::PadsBank0
+      to: pads::Pads
+  - MergeEnums:
+      from: pads::vals::.*Drive
+      to: pads::vals::Drive
+  - MergeFieldsets:
+      from: pads::regs::(Gpio\d+|Swclk|Swd)
+      to: pads::regs::GpioCtrl
+  - MakeRegisterArray:
+      blocks: pads::Pads
+      from: (gpio\d+|swclk|swd)
+      to: gpio
+  - MergeBlocks:
+      from: (pads::Pads|pads_qspi::PadsQspi)
+      main: pads::Pads
+      to: pads::Pads
+      check: NoCheck
+
+  # ========= PLL
+  - Rename:
+      from: pll_sys::(.*)
+      to: pll::$1
+  - Rename:
+      from: pll::PllSys
+      to: pll::Pll
+
+  # ========= RTC
+  - MergeFieldsets:
+      from: rtc::regs::Int.
+      to: rtc::regs::Int
+
+  # ========= ADC
+  - MergeFieldsets:
+      from: adc::regs::Int.
+      to: adc::regs::Int
+
+  # ========= BUSCTRL
+  - RenameFields:
+      fieldset: busctrl::regs::(Perfctr|Perfsel)\d+
+      from: (perfctr|perfsel)\d
+      to: $1
+  - MergeEnums:
+      from: busctrl::vals::Perfsel\d+
+      to: busctrl::vals::Perfsel
+  - MergeFieldsets:
+      from: busctrl::regs::(Perfctr|Perfsel)\d+
+      to: busctrl::regs::$1
+  - MakeRegisterArray:
+      blocks: busctrl::Busctrl
+      from: (perfctr|perfsel)\d
+      to: $1
+
+  # ========= CLOCKS
+  - MergeFieldsets:
+      from: clocks::regs::Int.
+      to: clocks::regs::Int
+  - RenameEnumVariants:
+      enum: clocks::vals::ClkGpout\dCtrlAuxsrc
+      from: ROSC_CLKSRC_PH
+      to: ROSC_CLKSRC
+  - MergeEnums:
+      from: clocks::vals::ClkGpout\dCtrlAuxsrc
+      to: clocks::vals::ClkGpoutCtrlAuxsrc
+  - MergeFieldsets:
+      from: clocks::regs::ClkGpout\d(Ctrl|Div)
+      to: clocks::regs::ClkGpout$1
+  - MakeRegisterArray:
+      blocks: clocks::Clocks
+      from: clk_gpout\d_(ctrl|div|selected)
+      to: clk_gpout_$1
+
+  # ========= USB
+  - Rename:
+      from: usbctrl_regs::(.*)
+      to: usb::$1
+  - Rename:
+      from: usb::UsbctrlRegs
+      to: usb::Usb
+  - MergeFieldsets:
+      from: usb::regs::Int.
+      to: usb::regs::Int
+  - MergeFieldsets:
+      from: usb::regs::AddrEndp\d+
+      to: usb::regs::AddrEndpX
+  - MakeRegisterArray:
+      blocks: usb::Usb
+      from: addr_endp\d+
+      to: addr_endp_x
+  - MakeFieldArray:
+      fieldsets: usb::regs::(BuffStatus|BuffCpuShouldHandle|EpAbort|EpAbortDone|EpStatusStallNak)
+      from: ep\d+_(.*)
+      to: ep_$1
+
+  - Rename:
+      from: usbctrl_dpram::(.*)
+      to: usb_dpram::$1
+  - MergeEnums:
+      from: usb_dpram::vals::Ep\d+(In|Out)(.*)
+      to: usb_dpram::vals::Ep$2
+  - MergeFieldsets:
+      from: usb_dpram::regs::Ep\d+(In|Out)(.*)
+      to: usb_dpram::regs::Ep$2
+  - Rename:
+      from: usb_dpram::UsbctrlDpram
+      to: usb_dpram::UsbDpram
+  - MakeRegisterArray:
+      blocks: usb_dpram::UsbDpram
+      from: ep\d+(.*)
+      to: ep$1
+  - MakeFieldArray:
+      fieldsets: usb_dpram::regs::.*BufferControl
+      from: (.*)_[01]
+      to: $1
+
+  # =========== PWM
+  - MergeFieldsets:
+      from: pwm::regs::Ch\d+(.+)
+      to: pwm::regs::Ch$1
+      check: NoCheck
+  - RenameFields:
+      fieldset: pwm::regs::Ch.+
+      from: ch\d+_(.+)
+      to: $1
+  - MergeEnums:
+      from: pwm::vals::Ch\dCsrDivmode
+      to: pwm::vals::Divmode
+  - MakeBlock:
+      blocks: pwm::Pwm
+      from: ch(\d+)_(.+)
+      to_block: pwm::Channel
+      to_outer: ch$1
+      to_inner: $2
+  - MakeRegisterArray:
+      blocks: pwm::Pwm
+      from: ch\d+
+      to: ch
+
+
+  # =========== Misc
+  - MergeEnums:
+      from: rosc::vals::.+Passwd
+      to: rosc::vals::Passwd
+  - MergeFieldsets:
+      from: resets::regs::(Reset|ResetDone)
+      to: resets::regs::Peripherals
+  - Rename:
+      from: xip_ctrl
+      to: xip
+
+  # =========== Cleanup
+  - Delete:
+      from: ppb::.* # We already get this from cortex_m crate
+  - Delete:
+      from: io_qspi::.*
+  - Delete:
+      from: swi_irq::.*
+  - Delete:
+      from: pads_qspi::.*
+  - Sanitize: {}
diff --git a/update.sh b/update.sh
index 18b5feb7..dfc9bb13 100755
--- a/update.sh
+++ b/update.sh
@@ -6,11 +6,17 @@ rm -rf src
 mkdir src
 
 #(cd ../chiptool/; cargo build)
-#RUST_LOG=info ../chiptool/target/debug/chiptool generate --svd svd/rp2040.svd --transform svd/rp2040.yaml
-chiptool generate --svd svd/rp2040.svd --transform svd/rp2040.yaml
+#RUST_LOG=info ../chiptool/target/debug/chiptool generate --svd svd/RP2040.svd --transform svd/rp2040.yaml
+chiptool generate --svd svd/RP2040.svd --transform svd/rp2040.yaml
 
 # cargo install form
-form -i lib.rs -o src
+form -i lib.rs -o src/rp2040
+rm lib.rs
+
+chiptool generate --svd svd/RP2350.svd --transform svd/rp2350.yaml
+
+# cargo install form
+form -i lib.rs -o src/rp2350
 rm lib.rs
 
 cargo fmt